diff --git a/br-ext-chip-hisilicon/board/hi3516cv500/kernel/patches/00_hi3516cv500_kernel-4.9.37_sdk-2.0.2.0.patch b/br-ext-chip-hisilicon/board/hi3516cv500/kernel/patches/00_hi3516cv500_kernel-4.9.37_sdk-2.0.2.1.patch
similarity index 77%
rename from br-ext-chip-hisilicon/board/hi3516cv500/kernel/patches/00_hi3516cv500_kernel-4.9.37_sdk-2.0.2.0.patch
rename to br-ext-chip-hisilicon/board/hi3516cv500/kernel/patches/00_hi3516cv500_kernel-4.9.37_sdk-2.0.2.1.patch
index 1e17be8f..2f2500d1 100644
--- a/br-ext-chip-hisilicon/board/hi3516cv500/kernel/patches/00_hi3516cv500_kernel-4.9.37_sdk-2.0.2.0.patch
+++ b/br-ext-chip-hisilicon/board/hi3516cv500/kernel/patches/00_hi3516cv500_kernel-4.9.37_sdk-2.0.2.1.patch
@@ -143,6 +143,29 @@ index 0000000..ea096d2
+ reg = <1>;
+ };
+ };
+diff --git a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt
+new file mode 100644
+index 0000000..1653a71
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt
+@@ -0,0 +1,17 @@
++Hisilicon PWM controller
++
++Required properties:
++-compatible: should contain one SoC specific compatible string and one generic compatible
++string "hisilicon, hibvt-pwm". The SoC specific strings supported including:
++ "hisilicon,hi3516cv500-pwm"
++- reg: physical base address and length of the controller's registers.
++- clocks: phandle and clock specifier of the PWM reference clock.
++- resets: phandle and reset specifier for the PWM controller reset.
++
++Example:
++ pwm: pwm@12070000 {
++ compatible = "hisilicon,hi3516xx-pwm", "hisilicon,hibvt-pwm";
++ reg = <0x12070000 0x10000>;
++ clocks = <&crg_ctrl HI3516CV500_PWM_CLK>;
++ resets = <&crg_ctrl 0x1bc 6>;
++ };
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index 7790c81..1b6be33 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -310,10 +333,10 @@ index b5d529f..2a84d1b 100644
source "arch/arm/mach-iop32x/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
-index d83f7c3..0b69f73 100644
+index d83f7c3..5f2c5d5 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
-@@ -287,6 +287,126 @@ choice
+@@ -287,6 +287,142 @@ choice
Say Y here if you want kernel low-level debugging support
on HI3620 UART.
@@ -389,6 +412,22 @@ index d83f7c3..0b69f73 100644
+ Say Y here if you want kernel low-level debugging support
+ on HI3559V200 UART.
+
++ config DEBUG_HI3562V100_UART
++ bool "Hisilicon Hi3562V100 Debug UART"
++ depends on ARCH_HI3562V100
++ select DEBUG_UART_PL01X
++ help
++ Say Y here if you want kernel low-level debugging support
++ on HI3562V100 UART.
++
++ config DEBUG_HI3566V100_UART
++ bool "Hisilicon Hi3566V100 Debug UART"
++ depends on ARCH_HI3566V100
++ select DEBUG_UART_PL01X
++ help
++ Say Y here if you want kernel low-level debugging support
++ on HI3566V100 UART.
++
+ config DEBUG_HI3518EV20X_UART
+ bool "Hisilicon Hi3518EV20X Debug UART"
+ depends on ARCH_HI3518EV20X
@@ -440,7 +479,7 @@ index d83f7c3..0b69f73 100644
config DEBUG_HIGHBANK_UART
bool "Kernel low-level debugging messages via Highbank UART"
depends on ARCH_HIGHBANK
-@@ -1530,6 +1650,20 @@ config DEBUG_UART_PHYS
+@@ -1530,6 +1666,20 @@ config DEBUG_UART_PHYS
default 0xf991e000 if DEBUG_QCOM_UARTDM
default 0xfc00c000 if DEBUG_AT91_SAMA5D4_USART3
default 0xfcb00000 if DEBUG_HI3620_UART
@@ -461,7 +500,7 @@ index d83f7c3..0b69f73 100644
default 0xfd883000 if DEBUG_ALPINE_UART0
default 0xfe800000 if ARCH_IOP32X
default 0xff690000 if DEBUG_RK32_UART2
-@@ -1619,6 +1753,20 @@ config DEBUG_UART_VIRT
+@@ -1619,6 +1769,20 @@ config DEBUG_UART_VIRT
default 0xfe300000 if DEBUG_BCM_KONA_UART
default 0xfe800000 if ARCH_IOP32X
default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
@@ -562,7 +601,7 @@ index 50f8d1b..9732bdf 100644
$(call if_changed,uimage)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
-index fc6d541..405edb2 100644
+index fc6d541..93769c8 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -218,6 +218,22 @@ not_angel:
@@ -571,9 +610,9 @@ index fc6d541..405edb2 100644
orrcc r4, r4, #1 @ remember we skipped cache_on
+
+/*TODO all the Cortex-A7 Single Core must fix this bug */
-+#if defined(CONFIG_ARCH_HI3516A) || defined(CONFIG_ARCH_HI3536DV100)|| defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)\
++#if defined(CONFIG_ARCH_HI3516A) || defined(CONFIG_ARCH_HI3536DV100) || defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)\
+ || defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || defined(CONFIG_ARCH_HI3518EV300)\
-+ || defined(CONFIG_ARCH_HI3516DV200)
++ || defined(CONFIG_ARCH_HI3516DV200) || defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+/*
+ * This is a bug on Cortex-A7 MPCORE. see buglist of Cortex-A7
+ * The D-caches are disabled when ACTLR.SMP is set to 0 regardless of the
@@ -589,10 +628,10 @@ index fc6d541..405edb2 100644
restart: adr r0, LC0
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 7037201..595e138 100644
+index 7037201..414b2e6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
-@@ -174,6 +174,58 @@ dtb-$(CONFIG_ARCH_HISI) += \
+@@ -174,6 +174,62 @@ dtb-$(CONFIG_ARCH_HISI) += \
hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
@@ -615,6 +654,10 @@ index 7037201..595e138 100644
+ hi3556v200-demb.dtb
+dtb-$(CONFIG_ARCH_HI3559V200) += \
+ hi3559v200-demb.dtb
++dtb-$(CONFIG_ARCH_HI3562V100) += \
++ hi3562v100-demb.dtb
++dtb-$(CONFIG_ARCH_HI3566V100) += \
++ hi3566v100-demb.dtb
+dtb-$(CONFIG_ARCH_HI3518EV20X) += \
+ hi3518ev20x-demb.dtb
+dtb-$(CONFIG_ARCH_HI3521A) += \
@@ -1588,10 +1631,10 @@ index 0000000..1a5c569
+};
diff --git a/arch/arm/boot/dts/hi3516cv500-demb.dts b/arch/arm/boot/dts/hi3516cv500-demb.dts
new file mode 100644
-index 0000000..7c70765
+index 0000000..a68bfbb
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516cv500-demb.dts
-@@ -0,0 +1,270 @@
+@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -1758,6 +1801,10 @@ index 0000000..7c70765
+ status = "okay";
+};
+
++&pwm {
++ status = "disabled";
++};
++
+&hidmac {
+ status = "disabled";
+};
@@ -1810,64 +1857,12 @@ index 0000000..7c70765
+ status = "okay";
+};
+
-+&osal {
-+ /*module param*/
-+ anony = <1>;
-+ setup_zones = "anonymous,0,0x88000000,384M";
-+ setup_allocator = "hisi";
-+ mmap_zones="";
-+};
-+
-+&sys_config {
-+ /*module param*/
-+ g_online_flag = <0>;
-+ g_cmos_yuv_flag = <0>;
-+ sensor_list = "sns0=imx327,sns1=imx327";
-+ chip_list = "hi3516cv500";
-+};
-+
-+&gdc {
-+ /*module param*/
-+ max_gdc_job = <32>;
-+ max_gdc_task = <64>;
-+ max_gdc_node = <64>;
-+};
-+
-+&vgs {
-+ /*module param*/
-+ max_vgs_job = <128>;
-+ max_vgs_task = <200>;
-+ max_vgs_node = <200>;
-+};
-+
-+&hifb {
-+ /*module param*/
-+ video = "hifb:vram0_size:16200";
-+};
-+
-+&venc {
-+ /*module param*/
-+ VencMaxChnNum = <16>;
-+};
-+
-+&ive {
-+ /*module param*/
-+ save_power = /bits/ 8 <0>;
-+ max_node_num = /bits/ 16 <512>;
-+};
-+
-+&nnie {
-+ /*module param*/
-+ nnie_save_power = /bits/ 8 <1>;
-+ nnie_max_tskbuf_num = /bits/ 16 <32>;
-+};
-+
diff --git a/arch/arm/boot/dts/hi3516cv500.dtsi b/arch/arm/boot/dts/hi3516cv500.dtsi
new file mode 100644
-index 0000000..75c0ab5
+index 0000000..596d055
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516cv500.dtsi
-@@ -0,0 +1,862 @@
+@@ -0,0 +1,871 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -2068,9 +2063,18 @@ index 0000000..75c0ab5
+ reg = <0x12051000 0x1000>;
+ clocks = <&clk_3m>,<&clk_apb>;
+ clock-names = "wdog_clk", "apb_pclk";
-+ ysctrltatus = "disabled";
++ status = "disabled";
+ };
+
++ pwm: pwm@12070000 {
++ compatible = "hisilicon,hi3516xx-pwm","hisilicon,hibvt-pwm";
++ reg = <0x12070000 0x10000>;
++ clocks = <&clock HI3516CV500_PWM_CLK>;
++ resets = <&clock 0x1bc 6>;
++ #pwm-cells = <2>;
++ status = "disabled";
++ };
++
+ uart0: uart@120a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x120a0000 0x1000>;
@@ -2710,7 +2714,7 @@ index 0000000..75c0ab5
+ interrupts = <0 65 4>;
+ resets = <&clock 0x1bc 2>;
+ reset-names = "lsadc-crg";
-+ status = "okay";
++ status = "disabled";
+ };
+ ir: ir@120f0000 {
+ compatible = "hisilicon,hi_ir";
@@ -2913,10 +2917,10 @@ index 0000000..9111353
+
diff --git a/arch/arm/boot/dts/hi3516dv200.dtsi b/arch/arm/boot/dts/hi3516dv200.dtsi
new file mode 100644
-index 0000000..e706ab8
+index 0000000..af32785
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516dv200.dtsi
-@@ -0,0 +1,698 @@
+@@ -0,0 +1,702 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2019 HiSilicon Technologies Co., Ltd.
@@ -3590,13 +3594,17 @@ index 0000000..e706ab8
+ interrupt-names = "gzip";
+ };
+
-+ venc: venc@11410000 {
++ vedu: vedu@11410000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
+ reg-names = "vedu0", "jpge";
+ interrupts = <0 47 4>, <0 48 4>;
+ interrupt-names = "vedu0","jpge";
-+ };
++ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
+
+ aiao: aiao@100e0000 {
+ compatible = "hisilicon,hisi-aiao";
@@ -3617,10 +3625,10 @@ index 0000000..e706ab8
+};
diff --git a/arch/arm/boot/dts/hi3516dv300-demb.dts b/arch/arm/boot/dts/hi3516dv300-demb.dts
new file mode 100644
-index 0000000..1d2b1a8
+index 0000000..89c1e5c
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516dv300-demb.dts
-@@ -0,0 +1,275 @@
+@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -3792,6 +3800,10 @@ index 0000000..1d2b1a8
+ status = "okay";
+};
+
++&pwm {
++ status = "disabled";
++};
++
+&hidmac {
+ status = "disabled";
+};
@@ -3843,65 +3855,13 @@ index 0000000..1d2b1a8
+&gpio_chip11 {
+ status = "okay";
+};
-+
-+&osal {
-+ /*module param*/
-+ anony = <1>;
-+ setup_zones = "anonymous,0,0x88000000,384M";
-+ setup_allocator = "hisi";
-+ mmap_zones="";
-+};
-+
-+&sys_config {
-+ /*module param*/
-+ g_online_flag = <0>;
-+ g_cmos_yuv_flag = <0>;
-+ sensor_list = "sns0=imx327,sns1=imx327";
-+ chip_list = "hi3516cv500";
-+};
-+
-+&gdc {
-+ /*module param*/
-+ max_gdc_job = <32>;
-+ max_gdc_task = <64>;
-+ max_gdc_node = <64>;
-+};
-+
-+&vgs {
-+ /*module param*/
-+ max_vgs_job = <128>;
-+ max_vgs_task = <200>;
-+ max_vgs_node = <200>;
-+};
-+
-+&hifb {
-+ /*module param*/
-+ video = "hifb:vram0_size:16200";
-+};
-+
-+&venc {
-+ /*module param*/
-+ VencMaxChnNum = <16>;
-+};
-+
-+&ive {
-+ /*module param*/
-+ save_power = /bits/ 8 <0>;
-+ max_node_num = /bits/ 16 <512>;
-+};
-+
-+&nnie {
-+ /*module param*/
-+ nnie_save_power = /bits/ 8 <1>;
-+ nnie_max_tskbuf_num = /bits/ 16 <32>;
-+};
-+
+\ No newline at end of file
diff --git a/arch/arm/boot/dts/hi3516dv300.dtsi b/arch/arm/boot/dts/hi3516dv300.dtsi
new file mode 100644
-index 0000000..7dd2b87
+index 0000000..3ec16b9
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516dv300.dtsi
-@@ -0,0 +1,886 @@
+@@ -0,0 +1,895 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -4103,9 +4063,18 @@ index 0000000..7dd2b87
+ reg = <0x12051000 0x1000>;
+ clocks = <&clk_3m>,<&clk_apb>;
+ clock-names = "wdog_clk", "apb_pclk";
-+ ysctrltatus = "disabled";
++ status = "disabled";
+ };
+
++ pwm: pwm@12070000 {
++ compatible = "hisilicon,hi3516xx-pwm","hisilicon,hibvt-pwm";
++ reg = <0x12070000 0x10000>;
++ clocks = <&clock HI3516DV300_PWM_CLK>;
++ resets = <&clock 0x1bc 6>;
++ #pwm-cells = <2>;
++ status = "disabled";
++ };
++
+ uart0: uart@120a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x120a0000 0x1000>;
@@ -4768,7 +4737,7 @@ index 0000000..7dd2b87
+ interrupts = <0 65 4>;
+ resets = <&clock 0x1bc 2>;
+ reset-names = "lsadc-crg";
-+ status = "okay";
++ status = "disabled";
+ };
+ ir: ir@120f0000 {
+ compatible = "hisilicon,hi_ir";
@@ -4962,10 +4931,10 @@ index 0000000..5738138
+
diff --git a/arch/arm/boot/dts/hi3516ev200.dtsi b/arch/arm/boot/dts/hi3516ev200.dtsi
new file mode 100644
-index 0000000..5756ba3
+index 0000000..2a89c8b
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516ev200.dtsi
-@@ -0,0 +1,676 @@
+@@ -0,0 +1,680 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -5617,13 +5586,17 @@ index 0000000..5756ba3
+ interrupt-names = "gzip";
+ };
+
-+ venc: venc@11410000 {
++ vedu: vedu@11410000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
+ reg-names = "vedu0", "jpge";
+ interrupts = <0 47 4>, <0 48 4>;
+ interrupt-names = "vedu0","jpge";
-+ };
++ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
+
+ aiao: aiao@100e0000 {
+ compatible = "hisilicon,hisi-aiao";
@@ -5824,10 +5797,10 @@ index 0000000..dbc2297
+
diff --git a/arch/arm/boot/dts/hi3516ev300.dtsi b/arch/arm/boot/dts/hi3516ev300.dtsi
new file mode 100644
-index 0000000..a973234
+index 0000000..9d14627
--- /dev/null
+++ b/arch/arm/boot/dts/hi3516ev300.dtsi
-@@ -0,0 +1,697 @@
+@@ -0,0 +1,701 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -6500,13 +6473,17 @@ index 0000000..a973234
+ interrupt-names = "gzip";
+ };
+
-+ venc: venc@11410000 {
++ vedu: vedu@11410000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
+ reg-names = "vedu0", "jpge";
+ interrupts = <0 47 4>, <0 48 4>;
+ interrupt-names = "vedu0","jpge";
-+ };
++ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
+
+ aiao: aiao@100e0000 {
+ compatible = "hisilicon,hisi-aiao";
@@ -7485,10 +7462,10 @@ index 0000000..d383a9e
+
diff --git a/arch/arm/boot/dts/hi3518ev300.dtsi b/arch/arm/boot/dts/hi3518ev300.dtsi
new file mode 100644
-index 0000000..a73e44b
+index 0000000..3cfb135
--- /dev/null
+++ b/arch/arm/boot/dts/hi3518ev300.dtsi
-@@ -0,0 +1,676 @@
+@@ -0,0 +1,680 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -8140,13 +8117,17 @@ index 0000000..a73e44b
+ interrupt-names = "gzip";
+ };
+
-+ venc: venc@11410000 {
++ vedu: vedu@11410000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
+ reg-names = "vedu0", "jpge";
+ interrupts = <0 47 4>, <0 48 4>;
+ interrupt-names = "vedu0","jpge";
-+ };
++ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
+
+ aiao: aiao@100e0000 {
+ compatible = "hisilicon,hisi-aiao";
@@ -8893,10 +8874,10 @@ index 0000000..f439426
+};
diff --git a/arch/arm/boot/dts/hi3519av100.dtsi b/arch/arm/boot/dts/hi3519av100.dtsi
new file mode 100644
-index 0000000..969fc3f
+index 0000000..89c1030
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519av100.dtsi
-@@ -0,0 +1,1081 @@
+@@ -0,0 +1,1085 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -9895,13 +9876,17 @@ index 0000000..969fc3f
+ interrupt-names = "jpegd";
+ };
+
-+ venc: venc@047c0000 {
++ vedu: vedu@047c0000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x047c0000 0x8000>, <0x047c8000 0x8000>;
+ reg-names = "vedu0", "jpge";
+ interrupts = <0 115 4>, <0 132 4>;
+ interrupt-names = "vedu0","jpge";
+ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
+
+ vdh: vdh@047d0000 {
+ compatible = "hisilicon,hisi-vdh";
@@ -12159,10 +12144,10 @@ index 0000000..20b22c1
+};
diff --git a/arch/arm/boot/dts/hi3556av100.dtsi b/arch/arm/boot/dts/hi3556av100.dtsi
new file mode 100644
-index 0000000..64e8e4f
+index 0000000..7db6cd4
--- /dev/null
+++ b/arch/arm/boot/dts/hi3556av100.dtsi
-@@ -0,0 +1,973 @@
+@@ -0,0 +1,979 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -12739,6 +12724,8 @@ index 0000000..64e8e4f
+ interrupt-names = "peripheral";
+ maximum-speed = "super-speed";
+ dr_mode = "peripheral";
++ snps,dis_initiate_u1;
++ snps,dis_initiate_u2;
+ };
+#endif
+#ifdef CONFIG_USB_DRD1_IN_DEVICE
@@ -13053,13 +13040,17 @@ index 0000000..64e8e4f
+ interrupt-names = "jpegd";
+ };
+
-+ venc: venc@047c0000 {
++ vedu: vedu@047c0000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x047c0000 0x8000>, <0x047c8000 0x8000>;
+ reg-names = "vedu0", "jpge";
+ interrupts = <0 115 4>, <0 132 4>;
+ interrupt-names = "vedu0","jpge";
+ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
+
+ vdh: vdh@047d0000 {
+ compatible = "hisilicon,hisi-vdh";
@@ -13138,10 +13129,10 @@ index 0000000..64e8e4f
+};
diff --git a/arch/arm/boot/dts/hi3556v200-demb.dts b/arch/arm/boot/dts/hi3556v200-demb.dts
new file mode 100644
-index 0000000..8669226
+index 0000000..5e9d5cd
--- /dev/null
+++ b/arch/arm/boot/dts/hi3556v200-demb.dts
-@@ -0,0 +1,226 @@
+@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -13177,6 +13168,11 @@ index 0000000..8669226
+&uart0 {
+ status = "okay";
+};
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++&uart1 {
++ status = "okay";
++};
++#endif
+&uart2 {
+ status = "okay";
+};
@@ -13313,9 +13309,21 @@ index 0000000..8669226
+};
+
+&mmc2 {
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ status = "disabled";
++#else
++ status = "okay";
++#endif
++};
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++&watchdog {
+ status = "okay";
+};
+
++&pwm {
++ status = "disabled";
++};
++#endif
+&hidmac {
+ status = "disabled";
+};
@@ -13370,10 +13378,10 @@ index 0000000..8669226
+
diff --git a/arch/arm/boot/dts/hi3556v200.dtsi b/arch/arm/boot/dts/hi3556v200.dtsi
new file mode 100644
-index 0000000..71c5dff
+index 0000000..5bdf804
--- /dev/null
+++ b/arch/arm/boot/dts/hi3556v200.dtsi
-@@ -0,0 +1,864 @@
+@@ -0,0 +1,896 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -13398,15 +13406,17 @@ index 0000000..71c5dff
+/ {
+ aliases {
+ serial0 = &uart0;
-+ i2c3 = &i2c_bus3;
-+ i2c7 = &i2c_bus7;
-+ i2c2 = &i2c_bus2;
+#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ serial1 = &uart1;
+ i2c0 = &i2c_bus0;
+ i2c1 = &i2c_bus1;
+#endif
++ i2c2 = &i2c_bus2;
++ i2c3 = &i2c_bus3;
++ i2c4 = &i2c_bus4;
+ i2c5 = &i2c_bus5;
+ i2c6 = &i2c_bus6;
++ i2c7 = &i2c_bus7;
+#ifndef CONFIG_ARCH_HISI_BVT_AMP
+ spi0 = &spi_bus0;
+ spi1 = &spi_bus1;
@@ -13567,7 +13577,25 @@ index 0000000..71c5dff
+ clock-names = "timer20", "timer21", "apb_pclk";
+ status = "disabled";
+ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ watchdog: watchdog@12051000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ arm,primecell-periphid = <0x00141805>;
++ reg = <0x12051000 0x1000>;
++ clocks = <&clk_3m>,<&clk_apb>;
++ clock-names = "wdog_clk", "apb_pclk";
++ status = "disabled";
++ };
+
++ pwm: pwm@12070000 {
++ compatible = "hisilicon,hi3516xx-pwm","hisilicon,hibvt-pwm";
++ reg = <0x12070000 0x10000>;
++ clocks = <&clock HI3556V200_PWM_CLK>;
++ resets = <&clock 0x1bc 6>;
++ #pwm-cells = <2>;
++ status = "disabled";
++ };
++#endif
+ uart0: uart@120a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x120a0000 0x1000>;
@@ -14062,7 +14090,11 @@ index 0000000..71c5dff
+ osal: osal {
+ compatible = "hisilicon,osal";
+ };
-+
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ sys_config: sys_config {
++ compatible = "hisilicon,sys_config";
++ };
++#endif
+ sys: sys@12010000 {
+ compatible = "hisilicon,hisi-sys";
+ reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
@@ -14141,7 +14173,11 @@ index 0000000..71c5dff
+ interrupts = <0 35 4>;
+ interrupt-names = "tde_osr_isr";
+ };
-+
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ gyro_dis: gyro {
++ compatible = "hisilicon,hisi-gyro-dis";
++ };
++#endif
+ gdc: gdc@11110000 {
+ compatible = "hisilicon,hisi-gdc";
+ reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
@@ -14166,7 +14202,7 @@ index 0000000..71c5dff
+ interrupt-names = "jpegd";
+ };
+
-+ venc: venc@11500000 {
++ vedu: vedu@11500000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
+ reg-names = "vedu0", "jpge";
@@ -14174,6 +14210,10 @@ index 0000000..71c5dff
+ interrupt-names = "vedu0","jpge";
+ };
+
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
++
+ scd: scd@10030000 {
+ compatible = "hisilicon,hisi-scd";
+ reg = <0x10030000 0x10000>;
@@ -14240,10 +14280,10 @@ index 0000000..71c5dff
+};
diff --git a/arch/arm/boot/dts/hi3559v200-demb.dts b/arch/arm/boot/dts/hi3559v200-demb.dts
new file mode 100644
-index 0000000..31cee13
+index 0000000..db8b5c6
--- /dev/null
+++ b/arch/arm/boot/dts/hi3559v200-demb.dts
-@@ -0,0 +1,226 @@
+@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -14279,6 +14319,11 @@ index 0000000..31cee13
+&uart0 {
+ status = "okay";
+};
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++&uart1 {
++ status = "okay";
++};
++#endif
+&uart2 {
+ status = "okay";
+};
@@ -14296,6 +14341,11 @@ index 0000000..31cee13
+ clock-frequency = <100000>;
+};
+
++&i2c_bus2 {
++ status = "okay";
++ clock-frequency = <400000>;
++};
++
+#ifndef CONFIG_ARCH_HISI_BVT_AMP
+&i2c_bus0 {
+ status = "okay";
@@ -14307,11 +14357,6 @@ index 0000000..31cee13
+ clock-frequency = <100000>;
+};
+
-+&i2c_bus2 {
-+ status = "okay";
-+ clock-frequency = <100000>;
-+};
-+
+&i2c_bus4 {
+ status = "okay";
+ clock-frequency = <100000>;
@@ -14415,6 +14460,1151 @@ index 0000000..31cee13
+};
+
+&mmc2 {
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ status = "disabled";
++#else
++ status = "okay";
++#endif
++};
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++&watchdog {
++ status = "okay";
++};
++
++&pwm {
++ status = "disabled";
++};
++#endif
++&hidmac {
++ status = "disabled";
++};
++
++&gpio_chip0 {
++ status = "okay";
++};
++
++&gpio_chip1 {
++ status = "okay";
++};
++
++&gpio_chip2 {
++ status = "okay";
++};
++
++&gpio_chip3 {
++ status = "okay";
++};
++
++&gpio_chip4 {
++ status = "okay";
++};
++
++&gpio_chip5 {
++ status = "okay";
++};
++
++&gpio_chip6 {
++ status = "okay";
++};
++
++&gpio_chip7 {
++ status = "okay";
++};
++
++&gpio_chip8 {
++ status = "okay";
++};
++
++&gpio_chip9 {
++ status = "okay";
++};
++
++&gpio_chip10 {
++ status = "okay";
++};
++
++&gpio_chip11 {
++ status = "okay";
++};
++
+diff --git a/arch/arm/boot/dts/hi3559v200.dtsi b/arch/arm/boot/dts/hi3559v200.dtsi
+new file mode 100644
+index 0000000..9240f6f
+--- /dev/null
++++ b/arch/arm/boot/dts/hi3559v200.dtsi
+@@ -0,0 +1,895 @@
++/*
++ * Copyright (c) 2013-2014 Linaro Ltd.
++ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++#include <../../../../../include/generated/autoconf.h>
++#include "skeleton.dtsi"
++#include <dt-bindings/clock/hi3559v200-clock.h>
++/ {
++ aliases {
++ serial0 = &uart0;
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ serial1 = &uart1;
++ i2c0 = &i2c_bus0;
++ i2c1 = &i2c_bus1;
++#endif
++ i2c2 = &i2c_bus2;
++ i2c3 = &i2c_bus3;
++ i2c4 = &i2c_bus4;
++ i2c5 = &i2c_bus5;
++ i2c6 = &i2c_bus6;
++ i2c7 = &i2c_bus7;
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ spi0 = &spi_bus0;
++ spi1 = &spi_bus1;
++ spi2 = &spi_bus2;
++#endif
++ gpio0 = &gpio_chip0;
++ gpio1 = &gpio_chip1;
++ gpio2 = &gpio_chip2;
++ gpio3 = &gpio_chip3;
++ gpio4 = &gpio_chip4;
++ gpio5 = &gpio_chip5;
++ gpio6 = &gpio_chip6;
++ gpio7 = &gpio_chip7;
++ gpio8 = &gpio_chip8;
++ gpio9 = &gpio_chip9;
++ gpio10 = &gpio_chip10;
++ gpio11 = &gpio_chip11;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ enable-method = "hisilicon,hi3559v200";
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ clock-frequency = <HI3559V200_FIXED_1000M>;
++ reg = <0>;
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ clock-frequency = <HI3559V200_FIXED_1000M>;
++ reg = <1>;
++ };
++#endif
++ };
++
++ clock: clock@12010000 {
++ compatible = "hisilicon,hi3559v200-clock";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #clock-cells = <1>;
++ #reset-cells = <2>;
++ reg = <0x12010000 0x1000>;
++ };
++
++ gic: interrupt-controller@10300000 {
++ compatible = "arm,cortex-a7-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ /* gic dist base, gic cpu base , no virtual support */
++ reg = <0x10301000 0x1000>, <0x10302000 0x100>;
++ };
++
++ syscounter {
++ compatible = "arm,armv7-timer";
++ interrupt-parent = <&gic>;
++ interrupts = <1 13 0xf08>,
++ <1 14 0xf08>;
++ clock-frequency = <50000000>;
++ };
++
++ soc {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ interrupt-parent = <&gic>;
++ ranges;
++
++ clk_3m: clk_3m {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <3000000>;
++ };
++
++ clk_apb: clk_apb {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <50000000>;
++ };
++
++ pmu {
++ compatible = "arm,cortex-a7-pmu";
++ interrupts = <0 54 4>;
++ };
++#ifdef CONFIG_HIEDMACV310
++ hiedmacv310_0: hiedma-controller@10060000 {
++ compatible = "hisilicon,hiedmacv310";
++ reg = <0x10060000 0x1000>;
++ interrupts = <0 28 4>;
++ clocks = <&clock HI3559V200_DMAC_CLK>, <&clock HI3559V200_DMAC_AXICLK>;
++ clock-names = "apb_pclk", "axi_aclk";
++ #clock-cells = <2>;
++ resets = <&clock 0x194 0>;
++ reset-names = "dma-reset";
++ dma-requests = <32>;
++ dma-channels = <8>;
++ devid = <0>;
++ #dma-cells = <2>;
++ status = "okay";
++ };
++#endif
++#ifdef CONFIG_HIEDMAC
++ hiedmacv310_0: hiedma-controller@10060000 {
++ compatible = "hisilicon,hiedmacv310_n";
++ reg = <0x10060000 0x1000>;
++ interrupts = <0 28 4>;
++ clocks = <&clock HI3559V200_DMAC_CLK>, <&clock HI3559V200_DMAC_AXICLK>;
++ clock-names = "apb_pclk", "axi_aclk";
++ #clock-cells = <2>;
++ resets = <&clock 0x194 0>;
++ reset-names = "dma-reset";
++ dma-requests = <32>;
++ dma-channels = <8>;
++ devid = <0>;
++ #dma-cells = <2>;
++ status = "okay";
++ };
++#endif
++
++ sysctrl: system-controller@12020000 {
++ compatible = "hisilicon,sysctrl";
++ reg = <0x12020000 0x1000>;
++ reboot-offset = <0x4>;
++ #clock-cells = <1>;
++ };
++
++ amba {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "arm,amba-bus";
++ ranges;
++
++ timer@hisp804 {
++ compatible = "hisilicon,hisp804";
++ /* timer0 & timer1 & timer2 */
++ reg = <0x12000000 0x20>, /* clocksource */
++ <0x12000020 0x20>, /* local timer for each cpu */
++ <0x12001000 0x20>;
++ interrupts = <0 1 4>, /* irq of local timer */
++ <0 2 4>;
++ clocks = <&clock HI3559V200_FIXED_3M>,
++ <&clock HI3559V200_FIXED_3M>,
++ <&clock HI3559V200_FIXED_3M>;
++ clock-names = "timer0", "timer1", "timer2";
++ };
++
++ dual_timer2: dual_timer@12002000 {
++ compatible = "arm,sp804", "arm,primecell";
++ /* timer4 & timer5 */
++ interrupts = <0 3 4>;
++ reg = <0x12002000 0x1000>;
++ clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
++ clock-names = "timer20", "timer21", "apb_pclk";
++ status = "disabled";
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ watchdog: watchdog@12051000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ arm,primecell-periphid = <0x00141805>;
++ reg = <0x12051000 0x1000>;
++ clocks = <&clk_3m>,<&clk_apb>;
++ clock-names = "wdog_clk", "apb_pclk";
++ status = "disabled";
++ };
++
++ pwm: pwm@12070000 {
++ compatible = "hisilicon,hi3516xx-pwm","hisilicon,hibvt-pwm";
++ reg = <0x12070000 0x10000>;
++ clocks = <&clock HI3559V200_PWM_CLK>;
++ resets = <&clock 0x1bc 6>;
++ #pwm-cells = <2>;
++ status = "disabled";
++ };
++#endif
++ uart0: uart@120a0000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a0000 0x1000>;
++ interrupts = <0 6 4>;
++ clocks = <&clock HI3559V200_UART0_CLK>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ uart1: uart@120a1000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a1000 0x1000>;
++ interrupts = <0 7 4>;
++ clocks = <&clock HI3559V200_UART1_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 19 19>, <&hiedmacv310_0 18 18>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++#endif
++ uart2: uart@120a2000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a2000 0x1000>;
++ interrupts = <0 8 4>;
++ clocks = <&clock HI3559V200_UART2_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 21 21>, <&hiedmacv310_0 20 20>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ uart3: uart@120a3000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a3000 0x1000>;
++ interrupts = <0 9 4>;
++ clocks = <&clock HI3559V200_UART3_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 23 23>, <&hiedmacv310_0 22 22>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ uart4: uart@120a4000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a4000 0x1000>;
++ interrupts = <0 10 4>;
++ clocks = <&clock HI3559V200_UART4_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 25 25>, <&hiedmacv310_0 24 24>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ };
++
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ i2c_bus0: i2c@120b0000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b0000 0x1000>;
++ clocks = <&clock HI3559V200_I2C0_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus1: i2c@120b1000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b1000 0x1000>;
++ clocks = <&clock HI3559V200_I2C1_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 3 3>, <&hiedmacv310_0 2 2>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++#endif
++
++ i2c_bus2: i2c@120b2000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b2000 0x1000>;
++ clocks = <&clock HI3559V200_I2C2_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 5 5>, <&hiedmacv310_0 4 4>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus3: i2c@120b3000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b3000 0x1000>;
++ clocks = <&clock HI3559V200_I2C3_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 7 7>, <&hiedmacv310_0 6 6>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++ i2c_bus4: i2c@120b4000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b4000 0x1000>;
++ clocks = <&clock HI3559V200_I2C4_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 9 9>, <&hiedmacv310_0 8 8>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++ i2c_bus5: i2c@120b5000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b5000 0x1000>;
++ clocks = <&clock HI3559V200_I2C5_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 11 11>, <&hiedmacv310_0 10 10>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus6: i2c@120b6000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b6000 0x1000>;
++ clocks = <&clock HI3559V200_I2C6_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 13 13>, <&hiedmacv310_0 12 12>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus7: i2c@120b7000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b7000 0x1000>;
++ clocks = <&clock HI3559V200_I2C7_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 15 15>, <&hiedmacv310_0 14 14>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ spi_bus0: spi@120c0000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x120c0000 0x1000>;
++ interrupts = <0 68 4>;
++ clocks = <&clock HI3559V200_SPI0_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 27 27>, <&hiedmacv310_0 26 26>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ spi_bus1: spi@120c1000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
++ interrupts = <0 69 4>;
++ clocks = <&clock HI3559V200_SPI1_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ num-cs = <2>;
++ hisi,spi_cs_sb = <2>;
++ hisi,spi_cs_mask_bit = <0x4>;//0100
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 29 29>, <&hiedmacv310_0 28 28>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ spi_bus2: spi@120c2000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x120c2000 0x1000>;
++ interrupts = <0 70 4>;
++ clocks = <&clock HI3559V200_SPI2_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 31 31>, <&hiedmacv310_0 30 30>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++#endif
++
++ ipcm: ipcm@045E0000 {
++ compatible = "hisilicon,ipcm-interrupt";
++ interrupt-parent = <&gic>;
++ interrupts = <0 10 4>;
++ reg = <0x10300000 0x4000>;
++ status = "okay";
++ };
++
++ mdio0: mdio@10011100 {
++ compatible = "hisilicon,hisi-femac-mdio";
++ reg = <0x10011100 0x10>;
++ clocks = <&clock HI3559V200_ETH0_CLK>;
++ clock-names = "mdio";
++ assigned-clocks = <&clock HI3559V200_ETH0_CLK>;
++ assigned-clock-rates = <54000000>;
++ resets = <&clock 0x16c 3>;
++ reset-names = "external-phy";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ hisi_femac0: ethernet@10010000 {
++ compatible = "hisilicon,hi3559v200-femac",
++ "hisilicon,hisi-femac-v2";
++ reg = <0x10010000 0x1000>,<0x10011300 0x200>;
++ interrupts = <0 32 4>;
++ clocks = <&clock HI3559V200_ETH0_CLK>;
++ resets = <&clock 0x16c 0>;
++ reset-names = "mac";
++ };
++
++ fmc: flash-memory-controller@10000000 {
++ compatible = "hisilicon,hisi-fmc";
++ reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
++ reg-names = "control", "memory";
++ clocks = <&clock HI3559V200_FMC_CLK>;
++ max-dma-size = <0x2000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hisfc:spi-nor@0 {
++ compatible = "hisilicon,fmc-spi-nor";
++ assigned-clocks = <&clock HI3559V200_FMC_CLK>;
++ assigned-clock-rates = <24000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ hisnfc:spi-nand@0 {
++ compatible = "hisilicon,fmc-spi-nand";
++ assigned-clocks = <&clock HI3559V200_FMC_CLK>;
++ assigned-clock-rates = <24000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
++ mmc0: himci.eMMC@0x10100000 {
++ compatible = "hisilicon,hi3559v200-himci";
++ reg = <0x10100000 0x1000>;
++ interrupts = <0 64 4>;
++ clocks = <&clock HI3559V200_MMC0_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x148 0>;
++ reset-names = "mmc_reset";
++ max-frequency = <150000000>;
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-mmc-hw-reset;
++ mmc-hs200-1_8v;
++ full-pwr-cycle;
++ devid = <0>;
++ status = "disabled";
++ };
++
++ mmc1: himci.SD@0x100f0000 {
++ compatible = "hisilicon,hi3559v200-himci";
++ reg = <0x100f0000 0x1000>;
++ interrupts = <0 30 4>;
++ clocks = <&clock HI3559V200_MMC1_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x160 0>;
++ reset-names = "mmc_reset";
++ max-frequency = <150000000>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ sd-uhs-sdr12;
++ sd-uhs-sdr25;
++ sd-uhs-sdr50;
++ sd-uhs-sdr104;
++ devid = <1>;
++ status = "disabled";
++ };
++
++ mmc2: himci.SD@0x10020000 {
++ compatible = "hisilicon,hi3559v200-himci";
++ reg = <0x10020000 0x1000>;
++ interrupts = <0 31 4>;
++ clocks = <&clock HI3559V200_MMC2_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x154 0>;
++ reset-names = "mmc_reset";
++ max-frequency = <100000000>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ sd-uhs-sdr12;
++ sd-uhs-sdr25;
++ sd-uhs-sdr50;
++ sd-uhs-sdr104;
++ devid = <2>;
++ status = "disabled";
++ };
++
++ hidmac: hidma-controller@10060000 {
++ compatible = "hisilicon,hisi-dmac";
++ reg = <0x10060000 0x1000>;
++ interrupts = <0 28 4>;
++ clocks = <&clock HI3559V200_DMAC_CLK>;
++ clock-names = "dmac_clk";
++ resets = <&clock 0xc8 4>;
++ reset-names = "dma-reset";
++ #dma-cells = <2>;
++ status = "disabled";
++ };
++
++ usb_phy: phy {
++ compatible = "hisilicon,hisi-usb-phy";
++ reg = <0x12010000 0x1000>;
++ #phy-cells = <0>;
++ };
++
++#ifdef CONFIG_USB_DRD0_IN_HOST
++ xhci_0@0x100e0000 {
++ compatible = "generic-xhci";
++ reg = <0x100e0000 0x10000>;
++ interrupts = <0 27 4>;
++ usb2-lpm-disable;
++ };
++#endif
++#ifdef CONFIG_USB_DRD0_IN_DEVICE
++ hidwc3_0@0x100e0000 {
++ compatible = "snps,dwc3";
++ reg = <0x100e0000 0x10000>;
++ interrupts = <0 27 4>;
++ interrupt-names = "peripheral";
++ maximum-speed = "high-speed";
++ dr_mode = "peripheral";
++ };
++#endif
++ gpio_chip0: gpio_chip@120d0000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d0000 0x1000>;
++ interrupts = <0 16 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip1: gpio_chip@120d1000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d1000 0x1000>;
++ interrupts = <0 17 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip2: gpio_chip@120d2000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d2000 0x1000>;
++ interrupts = <0 18 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip3: gpio_chip@120d3000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d3000 0x1000>;
++ interrupts = <0 19 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip4: gpio_chip@120d4000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d4000 0x1000>;
++ interrupts = <0 20 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip5: gpio_chip@120d5000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d5000 0x1000>;
++ interrupts = <0 21 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip6: gpio_chip@120d6000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d6000 0x1000>;
++ interrupts = <0 22 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip7: gpio_chip@120d7000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d7000 0x1000>;
++ interrupts = <0 23 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip8: gpio_chip@120d8000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d8000 0x1000>;
++ interrupts = <0 24 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip9: gpio_chip@120d9000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d9000 0x1000>;
++ interrupts = <0 25 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip10: gpio_chip@120da000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120da000 0x1000>;
++ interrupts = <0 26 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip11: gpio_chip@120db000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120db000 0x1000>;
++ interrupts = <0 80 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ cipher: cipher@0x100c0000 {
++ compatible = "hisilicon,hisi-cipher";
++ reg = <0x100c0000 0x10000>;
++ reg-names = "cipher";
++ interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
++ interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
++ };
++
++ };
++
++ media {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ interrupt-parent = <&gic>;
++ ranges;
++
++ osal: osal {
++ compatible = "hisilicon,osal";
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ sys_config: sys_config {
++ compatible = "hisilicon,sys_config";
++ };
++#endif
++ sys: sys@12010000 {
++ compatible = "hisilicon,hisi-sys";
++ reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
++ <0x12060000 0x10000>, <0x12030000 0x8000>;
++ reg-names = "crg", "sys", "ddr", "misc";
++ };
++
++ mipi: mipi@113a0000 {
++ compatible = "hisilicon,hisi-mipi";
++ reg = <0x113a0000 0x10000>;
++ reg-names = "mipi_rx";
++ interrupts = <0 57 4>;
++ interrupt-names = "mipi_rx";
++ };
++
++ mipi_tx: mipi_tx@11270000 {
++ compatible = "hisilicon,hisi-mipi_tx";
++ reg = <0x11270000 0x10000>;
++ reg-names = "mipi_tx";
++ interrupts = <0 63 4>;
++ interrupt-names = "mipi_tx";
++ };
++
++ vi: vi@11300000 {
++ compatible = "hisilicon,hisi-vi";
++ reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
++ reg-names = "VI_CAP0", "VI_PROC0";
++ interrupts = <0 56 4>, <0 44 4>;
++ interrupt-names = "VI_CAP0", "VI_PROC0";
++ };
++
++ isp: isp@11020000 {
++ compatible = "hisilicon,hisi-isp";
++ reg = <0x11020000 0x20000>;
++ reg-names = "ISP";
++ interrupts = <0 56 4>;
++ interrupt-names = "ISP";
++ };
++
++ vpss: vpss@11040000 {
++ compatible = "hisilicon,hisi-vpss";
++ reg = <0x11040000 0x10000>;
++ reg-names = "vpss0";
++ interrupts = <0 43 4>;
++ interrupt-names = "vpss0";
++ };
++
++ vgs: vgs@11240000 {
++ compatible = "hisilicon,hisi-vgs";
++ reg = <0x11240000 0x10000>;
++ reg-names = "vgs0";
++ interrupts = <0 38 4>;
++ interrupt-names = "vgs0";
++ };
++
++ vo: vo@11440000 {
++ compatible = "hisilicon,hisi-vo";
++ reg = <0x11440000 0x40000>;
++ reg-names = "vo";
++ interrupts = <0 58 4>;
++ interrupt-names = "vo";
++ };
++
++ hifb: hifb@11440000 {
++ compatible = "hisilicon,hisi-hifb";
++ reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
++ reg-names = "hifb", "sys";
++ interrupts = <0 59 4>, <0 51 4>;
++ interrupt-names = "hifb", "hifb_soft";
++ };
++
++ tde: tde@11210000 {
++ compatible = "hisilicon,hisi-tde";
++ reg = <0x11210000 0x10000>;
++ reg-names = "tde";
++ interrupts = <0 35 4>;
++ interrupt-names = "tde_osr_isr";
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ gyro_dis: gyro {
++ compatible = "hisilicon,hisi-gyro-dis";
++ };
++#endif
++ gdc: gdc@11110000 {
++ compatible = "hisilicon,hisi-gdc";
++ reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
++ reg-names = "gdc", "nnie0";
++ interrupts = <0 42 4>, <0 41 4>;
++ interrupt-names = "gdc", "nnie0";
++ };
++
++ gzip: gzip@11200000 {
++ compatible = "hisilicon,hisi-gzip";
++ reg = <0x11200000 0x10000>;
++ reg-names = "gzip";
++ interrupts = <0 34 4>;
++ interrupt-names = "gzip";
++ };
++
++ jpegd: jpegd@11260000 {
++ compatible = "hisilicon,hisi-jpegd";
++ reg = <0x11260000 0x10000>;
++ reg-names = "jpegd";
++ interrupts = <0 45 4>;
++ interrupt-names = "jpegd";
++ };
++
++ vedu: vedu@11500000 {
++ compatible = "hisilicon,hisi-vedu";
++ reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
++ reg-names = "vedu0", "jpge";
++ interrupts = <0 40 4>, <0 36 4>;
++ interrupt-names = "vedu0","jpge";
++ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
++
++ scd: scd@10030000 {
++ compatible = "hisilicon,hisi-scd";
++ reg = <0x10030000 0x10000>;
++ reg-names = "scd";
++ interrupts = <0 67 4>;
++ interrupt-names = "scd";
++ };
++
++ hdmi: hdmi@11400000 {
++ compatible = "hisilicon,hisi-hdmi";
++ reg = <0x11400000 0x30000>;
++ reg-names = "hdmi0";
++ };
++
++ aiao: aiao@113b0000 {
++ compatible = "hisilicon,hisi-aiao";
++ reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
++ reg-names = "aiao","acodec","crg";
++ interrupts = <0 55 4>;
++ interrupt-names = "AIO";
++ };
++
++ nnie: nnie@11100000 {
++ compatible = "hisilicon,hisi-nnie";
++ reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
++ reg-names = "nnie0","gdc";
++ interrupts = <0 41 4>,<0 42 4>;
++ interrupt-names = "nnie0","gdc";
++ };
++
++ ive: ive@11230000 {
++ compatible = "hisilicon,hisi-ive";
++ reg = <0x11230000 0x10000>;
++ reg-names = "ive";
++ interrupts = <0 37 4>;
++ interrupt-names = "ive";
++ };
++
++ adc: adc@120e0000 {
++ compatible = "hisilicon,hisi-lsadc";
++ reg = <0x120e0000 0x1000>;
++ interrupts = <0 65 4>;
++ resets = <&clock 0x1bc 2>;
++ reset-names = "lsadc-crg";
++ status = "okay";
++ };
++ ir: ir@120f0000 {
++ compatible = "hisilicon,hi_ir";
++ reg = <0x120f0000 0x1000>;
++ interrupts = <0 75 4>;
++ };
++
++ rtc: rtc@12080000 {
++ compatible = "hisilicon,hi35xx-rtc";
++ reg = <0x12080000 0x1000>;
++ interrupts = <0 5 4>;
++ };
++
++ wdg: wdg@12050000 {
++ compatible = "hisilicon,hi_wdg";
++ reg = <0x12050000 0x1000>;
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/hi3562v100-demb.dts b/arch/arm/boot/dts/hi3562v100-demb.dts
+new file mode 100644
+index 0000000..bb81ff1
+--- /dev/null
++++ b/arch/arm/boot/dts/hi3562v100-demb.dts
+@@ -0,0 +1,226 @@
++/*
++ * Copyright (c) 2013-2014 Linaro Ltd.
++ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++/dts-v1/;
++#include "hi3562v100.dtsi"
++
++/ {
++ model = "Hisilicon HI3562V100 DEMO Board";
++ compatible = "hisilicon,hi3562v100";
++
++ memory {
++ device_type = "memory";
++ reg = <0x82000000 0x20000000>;/* system memory base */
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++&uart2 {
++ status = "okay";
++};
++&uart3 {
++ status = "okay";
++};
++
++&i2c_bus3 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus7 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++&i2c_bus0 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus1 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus2 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus4 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus5 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus6 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&spi_bus0{
++ status = "okay";
++ num-cs = <1>;
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++&spi_bus1{
++ status = "okay";
++ num-cs = <2>;
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++&spi_bus2{
++ status = "okay";
++ num-cs = <1>;
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++#endif
++#if defined(CONFIG_HISI_FEMAC) || defined(CONFIG_HISI_FEMAC_MODULE)
++&mdio0 {
++ hisilicon,phy-reset-delays-us = <10000 20000 150000>;
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ };
++};
++
++&hisi_femac0 {
++ mac-address = [00 00 00 00 00 00];
++ phy-mode = "rmii";
++ phy-handle = <&phy0>;
++ status = "okay";
++};
++#endif
++&hisfc {
++ hi_sfc {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ };
++};
++
++&hisnfc {
++ hinand {
++ compatible = "jedec,spi-nand";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ };
++};
++
++&mmc0 {
++#ifdef CONFIG_MTD
++ status = "disabled";
++#else
++ status = "okay";
++#endif
++};
++
++&mmc1 {
++ status = "okay";
++};
++
++&mmc2 {
+ status = "okay";
+};
+
@@ -14470,12 +15660,12 @@ index 0000000..31cee13
+ status = "okay";
+};
+
-diff --git a/arch/arm/boot/dts/hi3559v200.dtsi b/arch/arm/boot/dts/hi3559v200.dtsi
+diff --git a/arch/arm/boot/dts/hi3562v100.dtsi b/arch/arm/boot/dts/hi3562v100.dtsi
new file mode 100644
-index 0000000..288eebf
+index 0000000..018eaee
--- /dev/null
-+++ b/arch/arm/boot/dts/hi3559v200.dtsi
-@@ -0,0 +1,863 @@
++++ b/arch/arm/boot/dts/hi3562v100.dtsi
+@@ -0,0 +1,868 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
@@ -15337,6 +16527,1117 @@ index 0000000..288eebf
+ compatible = "hisilicon,hi_wdg";
+ reg = <0x12050000 0x1000>;
+ };
++ pmc: pmc@12090000 {
++ compatible = "hisilicon,hi_pmc";
++ reg = <0x12090000 0x20>;
++ reg-names = "pmc";
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/hi3566v100-demb.dts b/arch/arm/boot/dts/hi3566v100-demb.dts
+new file mode 100644
+index 0000000..4ac9bee
+--- /dev/null
++++ b/arch/arm/boot/dts/hi3566v100-demb.dts
+@@ -0,0 +1,226 @@
++/*
++ * Copyright (c) 2013-2014 Linaro Ltd.
++ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++/dts-v1/;
++#include "hi3559v200.dtsi"
++
++/ {
++ model = "Hisilicon HI3559V200 DEMO Board";
++ compatible = "hisilicon,hi3559v200";
++
++ memory {
++ device_type = "memory";
++ reg = <0x82000000 0x20000000>;/* system memory base */
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++&uart2 {
++ status = "okay";
++};
++&uart3 {
++ status = "okay";
++};
++
++&i2c_bus3 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus7 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++&i2c_bus0 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus1 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus2 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus4 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus5 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&i2c_bus6 {
++ status = "okay";
++ clock-frequency = <100000>;
++};
++
++&spi_bus0{
++ status = "okay";
++ num-cs = <1>;
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++&spi_bus1{
++ status = "okay";
++ num-cs = <2>;
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++&spi_bus2{
++ status = "okay";
++ num-cs = <1>;
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++#endif
++#if defined(CONFIG_HISI_FEMAC) || defined(CONFIG_HISI_FEMAC_MODULE)
++&mdio0 {
++ hisilicon,phy-reset-delays-us = <10000 20000 150000>;
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ };
++};
++
++&hisi_femac0 {
++ mac-address = [00 00 00 00 00 00];
++ phy-mode = "rmii";
++ phy-handle = <&phy0>;
++ status = "okay";
++};
++#endif
++&hisfc {
++ hi_sfc {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ };
++};
++
++&hisnfc {
++ hinand {
++ compatible = "jedec,spi-nand";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ };
++};
++
++&mmc0 {
++#ifdef CONFIG_MTD
++ status = "disabled";
++#else
++ status = "okay";
++#endif
++};
++
++&mmc1 {
++ status = "okay";
++};
++
++&mmc2 {
++ status = "okay";
++};
++
++&hidmac {
++ status = "disabled";
++};
++
++&gpio_chip0 {
++ status = "okay";
++};
++
++&gpio_chip1 {
++ status = "okay";
++};
++
++&gpio_chip2 {
++ status = "okay";
++};
++
++&gpio_chip3 {
++ status = "okay";
++};
++
++&gpio_chip4 {
++ status = "okay";
++};
++
++&gpio_chip5 {
++ status = "okay";
++};
++
++&gpio_chip6 {
++ status = "okay";
++};
++
++&gpio_chip7 {
++ status = "okay";
++};
++
++&gpio_chip8 {
++ status = "okay";
++};
++
++&gpio_chip9 {
++ status = "okay";
++};
++
++&gpio_chip10 {
++ status = "okay";
++};
++
++&gpio_chip11 {
++ status = "okay";
++};
++
+diff --git a/arch/arm/boot/dts/hi3566v100.dtsi b/arch/arm/boot/dts/hi3566v100.dtsi
+new file mode 100644
+index 0000000..018eaee
+--- /dev/null
++++ b/arch/arm/boot/dts/hi3566v100.dtsi
+@@ -0,0 +1,868 @@
++/*
++ * Copyright (c) 2013-2014 Linaro Ltd.
++ * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++#include <../../../../../include/generated/autoconf.h>
++#include "skeleton.dtsi"
++#include <dt-bindings/clock/hi3559v200-clock.h>
++/ {
++ aliases {
++ serial0 = &uart0;
++ i2c3 = &i2c_bus3;
++ i2c7 = &i2c_bus7;
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ i2c0 = &i2c_bus0;
++ i2c1 = &i2c_bus1;
++ i2c2 = &i2c_bus2;
++#endif
++ i2c5 = &i2c_bus5;
++ i2c6 = &i2c_bus6;
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ spi0 = &spi_bus0;
++ spi1 = &spi_bus1;
++ spi2 = &spi_bus2;
++#endif
++ gpio0 = &gpio_chip0;
++ gpio1 = &gpio_chip1;
++ gpio2 = &gpio_chip2;
++ gpio3 = &gpio_chip3;
++ gpio4 = &gpio_chip4;
++ gpio5 = &gpio_chip5;
++ gpio6 = &gpio_chip6;
++ gpio7 = &gpio_chip7;
++ gpio8 = &gpio_chip8;
++ gpio9 = &gpio_chip9;
++ gpio10 = &gpio_chip10;
++ gpio11 = &gpio_chip11;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ enable-method = "hisilicon,hi3559v200";
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ clock-frequency = <HI3559V200_FIXED_1000M>;
++ reg = <0>;
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ clock-frequency = <HI3559V200_FIXED_1000M>;
++ reg = <1>;
++ };
++#endif
++ };
++
++ clock: clock@12010000 {
++ compatible = "hisilicon,hi3559v200-clock";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #clock-cells = <1>;
++ #reset-cells = <2>;
++ reg = <0x12010000 0x1000>;
++ };
++
++ gic: interrupt-controller@10300000 {
++ compatible = "arm,cortex-a7-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ /* gic dist base, gic cpu base , no virtual support */
++ reg = <0x10301000 0x1000>, <0x10302000 0x100>;
++ };
++
++ syscounter {
++ compatible = "arm,armv7-timer";
++ interrupt-parent = <&gic>;
++ interrupts = <1 13 0xf08>,
++ <1 14 0xf08>;
++ clock-frequency = <50000000>;
++ };
++
++ soc {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ interrupt-parent = <&gic>;
++ ranges;
++
++ clk_3m: clk_3m {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <3000000>;
++ };
++
++ clk_apb: clk_apb {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <50000000>;
++ };
++
++ pmu {
++ compatible = "arm,cortex-a7-pmu";
++ interrupts = <0 54 4>;
++ };
++#ifdef CONFIG_HIEDMACV310
++ hiedmacv310_0: hiedma-controller@10060000 {
++ compatible = "hisilicon,hiedmacv310";
++ reg = <0x10060000 0x1000>;
++ interrupts = <0 28 4>;
++ clocks = <&clock HI3559V200_DMAC_CLK>, <&clock HI3559V200_DMAC_AXICLK>;
++ clock-names = "apb_pclk", "axi_aclk";
++ #clock-cells = <2>;
++ resets = <&clock 0x194 0>;
++ reset-names = "dma-reset";
++ dma-requests = <32>;
++ dma-channels = <8>;
++ devid = <0>;
++ #dma-cells = <2>;
++ status = "okay";
++ };
++#endif
++#ifdef CONFIG_HIEDMAC
++ hiedmacv310_0: hiedma-controller@10060000 {
++ compatible = "hisilicon,hiedmacv310_n";
++ reg = <0x10060000 0x1000>;
++ interrupts = <0 28 4>;
++ clocks = <&clock HI3559V200_DMAC_CLK>, <&clock HI3559V200_DMAC_AXICLK>;
++ clock-names = "apb_pclk", "axi_aclk";
++ #clock-cells = <2>;
++ resets = <&clock 0x194 0>;
++ reset-names = "dma-reset";
++ dma-requests = <32>;
++ dma-channels = <8>;
++ devid = <0>;
++ #dma-cells = <2>;
++ status = "okay";
++ };
++#endif
++
++ sysctrl: system-controller@12020000 {
++ compatible = "hisilicon,sysctrl";
++ reg = <0x12020000 0x1000>;
++ reboot-offset = <0x4>;
++ #clock-cells = <1>;
++ };
++
++ amba {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "arm,amba-bus";
++ ranges;
++
++ timer@hisp804 {
++ compatible = "hisilicon,hisp804";
++ /* timer0 & timer1 & timer2 */
++ reg = <0x12000000 0x20>, /* clocksource */
++ <0x12000020 0x20>, /* local timer for each cpu */
++ <0x12001000 0x20>;
++ interrupts = <0 1 4>, /* irq of local timer */
++ <0 2 4>;
++ clocks = <&clock HI3559V200_FIXED_3M>,
++ <&clock HI3559V200_FIXED_3M>,
++ <&clock HI3559V200_FIXED_3M>;
++ clock-names = "timer0", "timer1", "timer2";
++ };
++
++ dual_timer2: dual_timer@12002000 {
++ compatible = "arm,sp804", "arm,primecell";
++ /* timer4 & timer5 */
++ interrupts = <0 3 4>;
++ reg = <0x12002000 0x1000>;
++ clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
++ clock-names = "timer20", "timer21", "apb_pclk";
++ status = "disabled";
++ };
++
++ uart0: uart@120a0000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a0000 0x1000>;
++ interrupts = <0 6 4>;
++ clocks = <&clock HI3559V200_UART0_CLK>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ uart1: uart@120a1000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a1000 0x1000>;
++ interrupts = <0 7 4>;
++ clocks = <&clock HI3559V200_UART1_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 19 19>, <&hiedmacv310_0 18 18>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++#endif
++ uart2: uart@120a2000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a2000 0x1000>;
++ interrupts = <0 8 4>;
++ clocks = <&clock HI3559V200_UART2_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 21 21>, <&hiedmacv310_0 20 20>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ uart3: uart@120a3000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a3000 0x1000>;
++ interrupts = <0 9 4>;
++ clocks = <&clock HI3559V200_UART3_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 23 23>, <&hiedmacv310_0 22 22>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ uart4: uart@120a4000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x120a4000 0x1000>;
++ interrupts = <0 10 4>;
++ clocks = <&clock HI3559V200_UART4_CLK>;
++ clock-names = "apb_pclk";
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 25 25>, <&hiedmacv310_0 24 24>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ };
++
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ i2c_bus0: i2c@120b0000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b0000 0x1000>;
++ clocks = <&clock HI3559V200_I2C0_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus1: i2c@120b1000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b1000 0x1000>;
++ clocks = <&clock HI3559V200_I2C1_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 3 3>, <&hiedmacv310_0 2 2>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus2: i2c@120b2000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b2000 0x1000>;
++ clocks = <&clock HI3559V200_I2C2_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 5 5>, <&hiedmacv310_0 4 4>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++#endif
++ i2c_bus3: i2c@120b3000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b3000 0x1000>;
++ clocks = <&clock HI3559V200_I2C3_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 7 7>, <&hiedmacv310_0 6 6>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++ i2c_bus4: i2c@120b4000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b4000 0x1000>;
++ clocks = <&clock HI3559V200_I2C4_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 9 9>, <&hiedmacv310_0 8 8>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++ i2c_bus5: i2c@120b5000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b5000 0x1000>;
++ clocks = <&clock HI3559V200_I2C5_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 11 11>, <&hiedmacv310_0 10 10>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus6: i2c@120b6000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b6000 0x1000>;
++ clocks = <&clock HI3559V200_I2C6_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 13 13>, <&hiedmacv310_0 12 12>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ i2c_bus7: i2c@120b7000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x120b7000 0x1000>;
++ clocks = <&clock HI3559V200_I2C7_CLK>;
++#ifdef CONFIG_HIEDMAC
++ dmas = <&hiedmacv310_0 15 15>, <&hiedmacv310_0 14 14>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ spi_bus0: spi@120c0000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x120c0000 0x1000>;
++ interrupts = <0 68 4>;
++ clocks = <&clock HI3559V200_SPI0_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 27 27>, <&hiedmacv310_0 26 26>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ spi_bus1: spi@120c1000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
++ interrupts = <0 69 4>;
++ clocks = <&clock HI3559V200_SPI1_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ num-cs = <2>;
++ hisi,spi_cs_sb = <2>;
++ hisi,spi_cs_mask_bit = <0x4>;//0100
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 29 29>, <&hiedmacv310_0 28 28>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++
++ spi_bus2: spi@120c2000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x120c2000 0x1000>;
++ interrupts = <0 70 4>;
++ clocks = <&clock HI3559V200_SPI2_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++#ifdef CONFIG_HIEDMACV310
++ dmas = <&hiedmacv310_0 31 31>, <&hiedmacv310_0 30 30>;
++ dma-names = "tx","rx";
++#endif
++ status = "disabled";
++ };
++#endif
++
++ ipcm: ipcm@045E0000 {
++ compatible = "hisilicon,ipcm-interrupt";
++ interrupt-parent = <&gic>;
++ interrupts = <0 10 4>;
++ reg = <0x10300000 0x4000>;
++ status = "okay";
++ };
++
++ mdio0: mdio@10011100 {
++ compatible = "hisilicon,hisi-femac-mdio";
++ reg = <0x10011100 0x10>;
++ clocks = <&clock HI3559V200_ETH0_CLK>;
++ clock-names = "mdio";
++ assigned-clocks = <&clock HI3559V200_ETH0_CLK>;
++ assigned-clock-rates = <54000000>;
++ resets = <&clock 0x16c 3>;
++ reset-names = "external-phy";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ hisi_femac0: ethernet@10010000 {
++ compatible = "hisilicon,hi3559v200-femac",
++ "hisilicon,hisi-femac-v2";
++ reg = <0x10010000 0x1000>,<0x10011300 0x200>;
++ interrupts = <0 32 4>;
++ clocks = <&clock HI3559V200_ETH0_CLK>;
++ resets = <&clock 0x16c 0>;
++ reset-names = "mac";
++ };
++
++ fmc: flash-memory-controller@10000000 {
++ compatible = "hisilicon,hisi-fmc";
++ reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
++ reg-names = "control", "memory";
++ clocks = <&clock HI3559V200_FMC_CLK>;
++ max-dma-size = <0x2000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hisfc:spi-nor@0 {
++ compatible = "hisilicon,fmc-spi-nor";
++ assigned-clocks = <&clock HI3559V200_FMC_CLK>;
++ assigned-clock-rates = <24000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ hisnfc:spi-nand@0 {
++ compatible = "hisilicon,fmc-spi-nand";
++ assigned-clocks = <&clock HI3559V200_FMC_CLK>;
++ assigned-clock-rates = <24000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
++ mmc0: himci.eMMC@0x10100000 {
++ compatible = "hisilicon,hi3559v200-himci";
++ reg = <0x10100000 0x1000>;
++ interrupts = <0 64 4>;
++ clocks = <&clock HI3559V200_MMC0_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x148 0>;
++ reset-names = "mmc_reset";
++ max-frequency = <150000000>;
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-mmc-hw-reset;
++ mmc-hs200-1_8v;
++ full-pwr-cycle;
++ devid = <0>;
++ status = "disabled";
++ };
++
++ mmc1: himci.SD@0x100f0000 {
++ compatible = "hisilicon,hi3559v200-himci";
++ reg = <0x100f0000 0x1000>;
++ interrupts = <0 30 4>;
++ clocks = <&clock HI3559V200_MMC1_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x160 0>;
++ reset-names = "mmc_reset";
++ max-frequency = <150000000>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ sd-uhs-sdr12;
++ sd-uhs-sdr25;
++ sd-uhs-sdr50;
++ sd-uhs-sdr104;
++ devid = <1>;
++ status = "disabled";
++ };
++
++ mmc2: himci.SD@0x10020000 {
++ compatible = "hisilicon,hi3559v200-himci";
++ reg = <0x10020000 0x1000>;
++ interrupts = <0 31 4>;
++ clocks = <&clock HI3559V200_MMC2_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x154 0>;
++ reset-names = "mmc_reset";
++ max-frequency = <100000000>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ sd-uhs-sdr12;
++ sd-uhs-sdr25;
++ sd-uhs-sdr50;
++ sd-uhs-sdr104;
++ devid = <2>;
++ status = "disabled";
++ };
++
++ hidmac: hidma-controller@10060000 {
++ compatible = "hisilicon,hisi-dmac";
++ reg = <0x10060000 0x1000>;
++ interrupts = <0 28 4>;
++ clocks = <&clock HI3559V200_DMAC_CLK>;
++ clock-names = "dmac_clk";
++ resets = <&clock 0xc8 4>;
++ reset-names = "dma-reset";
++ #dma-cells = <2>;
++ status = "disabled";
++ };
++
++ usb_phy: phy {
++ compatible = "hisilicon,hisi-usb-phy";
++ reg = <0x12010000 0x1000>;
++ #phy-cells = <0>;
++ };
++
++#ifdef CONFIG_USB_DRD0_IN_HOST
++ xhci_0@0x100e0000 {
++ compatible = "generic-xhci";
++ reg = <0x100e0000 0x10000>;
++ interrupts = <0 27 4>;
++ usb2-lpm-disable;
++ };
++#endif
++#ifdef CONFIG_USB_DRD0_IN_DEVICE
++ hidwc3_0@0x100e0000 {
++ compatible = "snps,dwc3";
++ reg = <0x100e0000 0x10000>;
++ interrupts = <0 27 4>;
++ interrupt-names = "peripheral";
++ maximum-speed = "high-speed";
++ dr_mode = "peripheral";
++ };
++#endif
++ gpio_chip0: gpio_chip@120d0000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d0000 0x1000>;
++ interrupts = <0 16 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip1: gpio_chip@120d1000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d1000 0x1000>;
++ interrupts = <0 17 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip2: gpio_chip@120d2000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d2000 0x1000>;
++ interrupts = <0 18 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip3: gpio_chip@120d3000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d3000 0x1000>;
++ interrupts = <0 19 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip4: gpio_chip@120d4000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d4000 0x1000>;
++ interrupts = <0 20 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip5: gpio_chip@120d5000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d5000 0x1000>;
++ interrupts = <0 21 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip6: gpio_chip@120d6000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d6000 0x1000>;
++ interrupts = <0 22 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip7: gpio_chip@120d7000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d7000 0x1000>;
++ interrupts = <0 23 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip8: gpio_chip@120d8000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d8000 0x1000>;
++ interrupts = <0 24 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip9: gpio_chip@120d9000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120d9000 0x1000>;
++ interrupts = <0 25 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip10: gpio_chip@120da000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120da000 0x1000>;
++ interrupts = <0 26 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ gpio_chip11: gpio_chip@120db000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x120db000 0x1000>;
++ interrupts = <0 80 4>;
++ clocks = <&clock HI3559V200_SYSAPB_CLK>;
++ clock-names = "apb_pclk";
++ #gpio-cells = <2>;
++ status = "disabled";
++ };
++
++ cipher: cipher@0x100c0000 {
++ compatible = "hisilicon,hisi-cipher";
++ reg = <0x100c0000 0x10000>;
++ reg-names = "cipher";
++ interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
++ interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
++ };
++
++ };
++
++ media {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ interrupt-parent = <&gic>;
++ ranges;
++
++ osal: osal {
++ compatible = "hisilicon,osal";
++ };
++
++ sys: sys@12010000 {
++ compatible = "hisilicon,hisi-sys";
++ reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
++ <0x12060000 0x10000>, <0x12030000 0x8000>;
++ reg-names = "crg", "sys", "ddr", "misc";
++ };
++
++ mipi: mipi@113a0000 {
++ compatible = "hisilicon,hisi-mipi";
++ reg = <0x113a0000 0x10000>;
++ reg-names = "mipi_rx";
++ interrupts = <0 57 4>;
++ interrupt-names = "mipi_rx";
++ };
++
++ mipi_tx: mipi_tx@11270000 {
++ compatible = "hisilicon,hisi-mipi_tx";
++ reg = <0x11270000 0x10000>;
++ reg-names = "mipi_tx";
++ interrupts = <0 63 4>;
++ interrupt-names = "mipi_tx";
++ };
++
++ vi: vi@11300000 {
++ compatible = "hisilicon,hisi-vi";
++ reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
++ reg-names = "VI_CAP0", "VI_PROC0";
++ interrupts = <0 56 4>, <0 44 4>;
++ interrupt-names = "VI_CAP0", "VI_PROC0";
++ };
++
++ isp: isp@11020000 {
++ compatible = "hisilicon,hisi-isp";
++ reg = <0x11020000 0x20000>;
++ reg-names = "ISP";
++ interrupts = <0 56 4>;
++ interrupt-names = "ISP";
++ };
++
++ vpss: vpss@11040000 {
++ compatible = "hisilicon,hisi-vpss";
++ reg = <0x11040000 0x10000>;
++ reg-names = "vpss0";
++ interrupts = <0 43 4>;
++ interrupt-names = "vpss0";
++ };
++
++ vgs: vgs@11240000 {
++ compatible = "hisilicon,hisi-vgs";
++ reg = <0x11240000 0x10000>;
++ reg-names = "vgs0";
++ interrupts = <0 38 4>;
++ interrupt-names = "vgs0";
++ };
++
++ vo: vo@11440000 {
++ compatible = "hisilicon,hisi-vo";
++ reg = <0x11440000 0x40000>;
++ reg-names = "vo";
++ interrupts = <0 58 4>;
++ interrupt-names = "vo";
++ };
++
++ hifb: hifb@11440000 {
++ compatible = "hisilicon,hisi-hifb";
++ reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
++ reg-names = "hifb", "sys";
++ interrupts = <0 59 4>, <0 51 4>;
++ interrupt-names = "hifb", "hifb_soft";
++ };
++
++ tde: tde@11210000 {
++ compatible = "hisilicon,hisi-tde";
++ reg = <0x11210000 0x10000>;
++ reg-names = "tde";
++ interrupts = <0 35 4>;
++ interrupt-names = "tde_osr_isr";
++ };
++
++ gdc: gdc@11110000 {
++ compatible = "hisilicon,hisi-gdc";
++ reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
++ reg-names = "gdc", "nnie0";
++ interrupts = <0 42 4>, <0 41 4>;
++ interrupt-names = "gdc", "nnie0";
++ };
++
++ gzip: gzip@11200000 {
++ compatible = "hisilicon,hisi-gzip";
++ reg = <0x11200000 0x10000>;
++ reg-names = "gzip";
++ interrupts = <0 34 4>;
++ interrupt-names = "gzip";
++ };
++
++ jpegd: jpegd@11260000 {
++ compatible = "hisilicon,hisi-jpegd";
++ reg = <0x11260000 0x10000>;
++ reg-names = "jpegd";
++ interrupts = <0 45 4>;
++ interrupt-names = "jpegd";
++ };
++
++ venc: venc@11500000 {
++ compatible = "hisilicon,hisi-vedu";
++ reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
++ reg-names = "vedu0", "jpge";
++ interrupts = <0 40 4>, <0 36 4>;
++ interrupt-names = "vedu0","jpge";
++ };
++
++ scd: scd@10030000 {
++ compatible = "hisilicon,hisi-scd";
++ reg = <0x10030000 0x10000>;
++ reg-names = "scd";
++ interrupts = <0 67 4>;
++ interrupt-names = "scd";
++ };
++
++ hdmi: hdmi@11400000 {
++ compatible = "hisilicon,hisi-hdmi";
++ reg = <0x11400000 0x30000>;
++ reg-names = "hdmi0";
++ };
++
++ aiao: aiao@113b0000 {
++ compatible = "hisilicon,hisi-aiao";
++ reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
++ reg-names = "aiao","acodec","crg";
++ interrupts = <0 55 4>;
++ interrupt-names = "AIO";
++ };
++
++ nnie: nnie@11100000 {
++ compatible = "hisilicon,hisi-nnie";
++ reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
++ reg-names = "nnie0","gdc";
++ interrupts = <0 41 4>,<0 42 4>;
++ interrupt-names = "nnie0","gdc";
++ };
++
++ ive: ive@11230000 {
++ compatible = "hisilicon,hisi-ive";
++ reg = <0x11230000 0x10000>;
++ reg-names = "ive";
++ interrupts = <0 37 4>;
++ interrupt-names = "ive";
++ };
++
++ adc: adc@120e0000 {
++ compatible = "hisilicon,hisi-lsadc";
++ reg = <0x120e0000 0x1000>;
++ interrupts = <0 65 4>;
++ resets = <&clock 0x1bc 2>;
++ reset-names = "lsadc-crg";
++ status = "okay";
++ };
++ ir: ir@120f0000 {
++ compatible = "hisilicon,hi_ir";
++ reg = <0x120f0000 0x1000>;
++ interrupts = <0 75 4>;
++ };
++
++ rtc: rtc@12080000 {
++ compatible = "hisilicon,hi35xx-rtc";
++ reg = <0x12080000 0x1000>;
++ interrupts = <0 5 4>;
++ };
++
++ wdg: wdg@12050000 {
++ compatible = "hisilicon,hi_wdg";
++ reg = <0x12050000 0x1000>;
++ };
++ pmc: pmc@12090000 {
++ compatible = "hisilicon,hi_pmc";
++ reg = <0x12090000 0x20>;
++ reg-names = "pmc";
++ };
+ };
+};
diff --git a/arch/arm/configs/hi3516a_full_defconfig b/arch/arm/configs/hi3516a_full_defconfig
@@ -25501,10 +27802,10 @@ index 0000000..762167f
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/hi3516av300_emmc_smp_defconfig b/arch/arm/configs/hi3516av300_emmc_smp_defconfig
new file mode 100644
-index 0000000..f640312
+index 0000000..b7380fc
--- /dev/null
+++ b/arch/arm/configs/hi3516av300_emmc_smp_defconfig
-@@ -0,0 +1,2953 @@
+@@ -0,0 +1,2954 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.9.37 Kernel Configuration
@@ -25863,6 +28164,8 @@ index 0000000..f640312
+# CONFIG_ARCH_HI3516DV200 is not set
+# CONFIG_ARCH_HI3556V200 is not set
+# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
+# CONFIG_ARCH_HI3536DV100 is not set
+# CONFIG_ARCH_HI3521A is not set
+# CONFIG_ARCH_HI3531A is not set
@@ -26092,7 +28395,7 @@ index 0000000..f640312
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
-+# CONFIG_KERNEL_MODE_NEON is not set
++CONFIG_KERNEL_MODE_NEON=y
+
+#
+# Userspace binary formats
@@ -27488,7 +29791,6 @@ index 0000000..f640312
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_MUSB_HDRC is not set
-+CONFIG_USB_DWC3_HISI=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_GADGET=y
@@ -28460,10 +30762,10 @@ index 0000000..f640312
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/hi3516av300_smp_defconfig b/arch/arm/configs/hi3516av300_smp_defconfig
new file mode 100644
-index 0000000..8cd581c
+index 0000000..f52ae0d
--- /dev/null
+++ b/arch/arm/configs/hi3516av300_smp_defconfig
-@@ -0,0 +1,3082 @@
+@@ -0,0 +1,3083 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.9.37 Kernel Configuration
@@ -28822,6 +31124,8 @@ index 0000000..8cd581c
+# CONFIG_ARCH_HI3516DV200 is not set
+# CONFIG_ARCH_HI3556V200 is not set
+# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
+# CONFIG_ARCH_HI3536DV100 is not set
+# CONFIG_ARCH_HI3521A is not set
+# CONFIG_ARCH_HI3531A is not set
@@ -29051,7 +31355,7 @@ index 0000000..8cd581c
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
-+# CONFIG_KERNEL_MODE_NEON is not set
++CONFIG_KERNEL_MODE_NEON=y
+
+#
+# Userspace binary formats
@@ -30549,7 +32853,6 @@ index 0000000..8cd581c
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_MUSB_HDRC is not set
-+CONFIG_USB_DWC3_HISI=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_GADGET=y
@@ -34195,10 +36498,10 @@ index 0000000..8b998a2
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/hi3516cv500_emmc_smp_defconfig b/arch/arm/configs/hi3516cv500_emmc_smp_defconfig
new file mode 100644
-index 0000000..a99b163
+index 0000000..08f457d
--- /dev/null
+++ b/arch/arm/configs/hi3516cv500_emmc_smp_defconfig
-@@ -0,0 +1,2953 @@
+@@ -0,0 +1,2954 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.9.37 Kernel Configuration
@@ -34557,6 +36860,8 @@ index 0000000..a99b163
+# CONFIG_ARCH_HI3516DV200 is not set
+# CONFIG_ARCH_HI3556V200 is not set
+# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
+# CONFIG_ARCH_HI3536DV100 is not set
+# CONFIG_ARCH_HI3521A is not set
+# CONFIG_ARCH_HI3531A is not set
@@ -34786,7 +37091,7 @@ index 0000000..a99b163
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
-+# CONFIG_KERNEL_MODE_NEON is not set
++CONFIG_KERNEL_MODE_NEON=y
+
+#
+# Userspace binary formats
@@ -36182,7 +38487,6 @@ index 0000000..a99b163
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_MUSB_HDRC is not set
-+CONFIG_USB_DWC3_HISI=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_GADGET=y
@@ -37154,10 +39458,10 @@ index 0000000..a99b163
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/hi3516cv500_smp_defconfig b/arch/arm/configs/hi3516cv500_smp_defconfig
new file mode 100644
-index 0000000..3866bd5
+index 0000000..4f15bf5
--- /dev/null
+++ b/arch/arm/configs/hi3516cv500_smp_defconfig
-@@ -0,0 +1,3082 @@
+@@ -0,0 +1,3083 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.9.37 Kernel Configuration
@@ -37516,6 +39820,8 @@ index 0000000..3866bd5
+# CONFIG_ARCH_HI3516DV200 is not set
+# CONFIG_ARCH_HI3556V200 is not set
+# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
+# CONFIG_ARCH_HI3536DV100 is not set
+# CONFIG_ARCH_HI3521A is not set
+# CONFIG_ARCH_HI3531A is not set
@@ -37745,7 +40051,7 @@ index 0000000..3866bd5
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
-+# CONFIG_KERNEL_MODE_NEON is not set
++CONFIG_KERNEL_MODE_NEON=y
+
+#
+# Userspace binary formats
@@ -39243,7 +41549,6 @@ index 0000000..3866bd5
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_MUSB_HDRC is not set
-+CONFIG_USB_DWC3_HISI=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_GADGET=y
@@ -46248,10 +48553,10 @@ index 0000000..7066fee
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/hi3516dv300_emmc_smp_defconfig b/arch/arm/configs/hi3516dv300_emmc_smp_defconfig
new file mode 100644
-index 0000000..f640312
+index 0000000..b7380fc
--- /dev/null
+++ b/arch/arm/configs/hi3516dv300_emmc_smp_defconfig
-@@ -0,0 +1,2953 @@
+@@ -0,0 +1,2954 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.9.37 Kernel Configuration
@@ -46610,6 +48915,8 @@ index 0000000..f640312
+# CONFIG_ARCH_HI3516DV200 is not set
+# CONFIG_ARCH_HI3556V200 is not set
+# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
+# CONFIG_ARCH_HI3536DV100 is not set
+# CONFIG_ARCH_HI3521A is not set
+# CONFIG_ARCH_HI3531A is not set
@@ -46839,7 +49146,7 @@ index 0000000..f640312
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
-+# CONFIG_KERNEL_MODE_NEON is not set
++CONFIG_KERNEL_MODE_NEON=y
+
+#
+# Userspace binary formats
@@ -48235,7 +50542,6 @@ index 0000000..f640312
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_MUSB_HDRC is not set
-+CONFIG_USB_DWC3_HISI=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_GADGET=y
@@ -49207,10 +51513,10 @@ index 0000000..f640312
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/hi3516dv300_smp_defconfig b/arch/arm/configs/hi3516dv300_smp_defconfig
new file mode 100644
-index 0000000..8cd581c
+index 0000000..f52ae0d
--- /dev/null
+++ b/arch/arm/configs/hi3516dv300_smp_defconfig
-@@ -0,0 +1,3082 @@
+@@ -0,0 +1,3083 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.9.37 Kernel Configuration
@@ -49569,6 +51875,8 @@ index 0000000..8cd581c
+# CONFIG_ARCH_HI3516DV200 is not set
+# CONFIG_ARCH_HI3556V200 is not set
+# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
+# CONFIG_ARCH_HI3536DV100 is not set
+# CONFIG_ARCH_HI3521A is not set
+# CONFIG_ARCH_HI3531A is not set
@@ -49798,7 +52106,7 @@ index 0000000..8cd581c
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
-+# CONFIG_KERNEL_MODE_NEON is not set
++CONFIG_KERNEL_MODE_NEON=y
+
+#
+# Userspace binary formats
@@ -51296,7 +53604,6 @@ index 0000000..8cd581c
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_MUSB_HDRC is not set
-+CONFIG_USB_DWC3_HISI=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_GADGET=y
@@ -136568,6 +138875,5853 @@ index 0000000..a2d715c
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_SBITMAP=y
+# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3556v200_emmc_smp_defconfig b/arch/arm/configs/hi3556v200_emmc_smp_defconfig
+new file mode 100644
+index 0000000..b47504a
+--- /dev/null
++++ b/arch/arm/configs/hi3556v200_emmc_smp_defconfig
+@@ -0,0 +1,2853 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++CONFIG_ARCH_HI3556V200=y
++# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_HISI_MC is not set
++CONFIG_HI_ZRELADDR=0x80008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_643719 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_798181 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_ARM_CPU_TOPOLOGY=y
++# CONFIG_SCHED_MC is not set
++# CONFIG_SCHED_SMT is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++# CONFIG_MCPM is not set
++# CONFIG_BIG_LITTLE is not set
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++CONFIG_NR_CPUS=2
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++CONFIG_HZ_100=y
++# CONFIG_HZ_200 is not set
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUG=y
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++CONFIG_AUTO_ZRELADDR=y
++# CONFIG_EFI is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=16
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++# CONFIG_MTD is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++# CONFIG_ETHERNET is not set
++# CONFIG_PHYLIB is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++CONFIG_JOYSTICK_XPAD=y
++CONFIG_JOYSTICK_XPAD_FF=y
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_RNDIS=y
++# CONFIG_USB_G_MULTI_CDC is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=y
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3556V200=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++CONFIG_TIMER_HISP804=y
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=m
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++# CONFIG_CRYPTO_SEQIV is not set
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=m
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3556v200_smp_defconfig b/arch/arm/configs/hi3556v200_smp_defconfig
+new file mode 100644
+index 0000000..77aa853
+--- /dev/null
++++ b/arch/arm/configs/hi3556v200_smp_defconfig
+@@ -0,0 +1,2982 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++CONFIG_ARCH_HI3556V200=y
++# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_HISI_MC is not set
++CONFIG_HI_ZRELADDR=0x80008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_643719 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_798181 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_ARM_CPU_TOPOLOGY=y
++# CONFIG_SCHED_MC is not set
++# CONFIG_SCHED_SMT is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++# CONFIG_MCPM is not set
++# CONFIG_BIG_LITTLE is not set
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++CONFIG_NR_CPUS=2
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++CONFIG_HZ_100=y
++# CONFIG_HZ_200 is not set
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUG=y
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++CONFIG_AUTO_ZRELADDR=y
++# CONFIG_EFI is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=16
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_LPDDR2_NVM is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_CADENCE_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_MTD_UBI_GLUEBI is not set
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++# CONFIG_ETHERNET is not set
++# CONFIG_PHYLIB is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++CONFIG_JOYSTICK_XPAD=y
++CONFIG_JOYSTICK_XPAD_FF=y
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_RNDIS=y
++# CONFIG_USB_G_MULTI_CDC is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=y
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3556V200=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++CONFIG_TIMER_HISP804=y
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_UBIFS_FS is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=m
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++# CONFIG_CRYPTO_SEQIV is not set
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=m
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/hi3559v200_amp_defconfig b/arch/arm/configs/hi3559v200_amp_defconfig
new file mode 100644
index 0000000..179ebe9
@@ -144507,6 +152661,26345 @@ index 0000000..d8267f1
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_SBITMAP=y
+# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3559v200_emmc_smp_defconfig b/arch/arm/configs/hi3559v200_emmc_smp_defconfig
+new file mode 100644
+index 0000000..ec6e447
+--- /dev/null
++++ b/arch/arm/configs/hi3559v200_emmc_smp_defconfig
+@@ -0,0 +1,2852 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++CONFIG_ARCH_HI3559V200=y
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_HISI_MC is not set
++CONFIG_HI_ZRELADDR=0x80008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_643719 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_798181 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_ARM_CPU_TOPOLOGY=y
++# CONFIG_SCHED_MC is not set
++# CONFIG_SCHED_SMT is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++# CONFIG_MCPM is not set
++# CONFIG_BIG_LITTLE is not set
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++CONFIG_NR_CPUS=2
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++CONFIG_HZ_100=y
++# CONFIG_HZ_200 is not set
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUG=y
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++CONFIG_AUTO_ZRELADDR=y
++# CONFIG_EFI is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=16
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++# CONFIG_MTD is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++# CONFIG_ETHERNET is not set
++# CONFIG_PHYLIB is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++CONFIG_JOYSTICK_XPAD=y
++CONFIG_JOYSTICK_XPAD_FF=y
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_RNDIS=y
++# CONFIG_USB_G_MULTI_CDC is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=y
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3559V200=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++CONFIG_TIMER_HISP804=y
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=m
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++# CONFIG_CRYPTO_SEQIV is not set
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=m
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3559v200_smp_defconfig b/arch/arm/configs/hi3559v200_smp_defconfig
+new file mode 100644
+index 0000000..b247219
+--- /dev/null
++++ b/arch/arm/configs/hi3559v200_smp_defconfig
+@@ -0,0 +1,2981 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++CONFIG_ARCH_HI3559V200=y
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_HISI_MC is not set
++CONFIG_HI_ZRELADDR=0x80008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_643719 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_798181 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_ARM_CPU_TOPOLOGY=y
++# CONFIG_SCHED_MC is not set
++# CONFIG_SCHED_SMT is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++# CONFIG_MCPM is not set
++# CONFIG_BIG_LITTLE is not set
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++CONFIG_NR_CPUS=2
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++CONFIG_HZ_100=y
++# CONFIG_HZ_200 is not set
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUG=y
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++CONFIG_AUTO_ZRELADDR=y
++# CONFIG_EFI is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=16
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_LPDDR2_NVM is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_CADENCE_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_MTD_UBI_GLUEBI is not set
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++# CONFIG_ETHERNET is not set
++# CONFIG_PHYLIB is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++CONFIG_JOYSTICK_XPAD=y
++CONFIG_JOYSTICK_XPAD_FF=y
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_RNDIS=y
++# CONFIG_USB_G_MULTI_CDC is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=y
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3559V200=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++CONFIG_TIMER_HISP804=y
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_UBIFS_FS is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=m
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++# CONFIG_CRYPTO_SEQIV is not set
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=m
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3562v100_amp_defconfig b/arch/arm/configs/hi3562v100_amp_defconfig
+new file mode 100644
+index 0000000..c6c61c4
+--- /dev/null
++++ b/arch/arm/configs/hi3562v100_amp_defconfig
+@@ -0,0 +1,2921 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TINY_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++# CONFIG_RCU_STALL_COMMON is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++# CONFIG_UTS_NS is not set
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_NET_NS is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR is not set
++CONFIG_CC_STACKPROTECTOR_NONE=y
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++# CONFIG_CC_STACKPROTECTOR_STRONG is not set
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_NOOP=y
++CONFIG_DEFAULT_IOSCHED="noop"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++# CONFIG_ARCH_HI3559V200 is not set
++CONFIG_ARCH_HI3562V100=y
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++CONFIG_HISI_MC=y
++CONFIG_AMP_ZRELADDR=0x82008000
++CONFIG_HI_ZRELADDR=0x82008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++# CONFIG_SMP is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_200=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=200
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_NEED_PER_CPU_KM=y
++# CONFIG_CLEANCACHE is not set
++# CONFIG_CMA is not set
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++# CONFIG_KERNEL_MODE_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++CONFIG_VLAN_8021Q=y
++# CONFIG_VLAN_8021Q_GVRP is not set
++# CONFIG_VLAN_8021Q_MVRP is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++# CONFIG_CFG80211_WEXT is not set
++# CONFIG_LIB80211 is not set
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_MINSTREL_HT=y
++# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++# CONFIG_MTD_NAND is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_LPDDR2_NVM is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_CADENCE_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++# CONFIG_MTD_UBI is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++CONFIG_HISI_FEMAC=y
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++# CONFIG_HIETH_GMAC is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++CONFIG_MDIO_HISI_FEMAC=y
++# CONFIG_MDIO_HISI_GEMAC is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_WLAN_VENDOR_BROADCOM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_BRCMSMAC is not set
++# CONFIG_BRCMFMAC is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++CONFIG_WLAN_VENDOR_ZYDAS=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_ZD1211RW is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=m
++CONFIG_VIDEOBUF2_MEMOPS=m
++CONFIG_VIDEOBUF2_VMALLOC=m
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=m
++CONFIG_USB_XHCI_PLATFORM=m
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=m
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++# CONFIG_USB_DWC3_OF_SIMPLE is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_ECM=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++CONFIG_USB_CONFIGFS_ACM=y
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++CONFIG_USB_CONFIGFS_ECM=y
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++CONFIG_USB_CONFIGFS_RNDIS=y
++# CONFIG_USB_CONFIGFS_EEM is not set
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=m
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_PWRSEQ_EMMC is not set
++CONFIG_PWRSEQ_SIMPLE=m
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=m
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=m
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++CONFIG_SYNC_FILE=y
++CONFIG_SW_SYNC=y
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3562V100=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++CONFIG_USB_DRD0_IN_HOST=y
++# CONFIG_USB_DRD0_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=m
++# CONFIG_FUSE_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_YAFFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_LZMA=y
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_JFFS2_CMODE_NONE is not set
++# CONFIG_JFFS2_CMODE_PRIORITY is not set
++CONFIG_JFFS2_CMODE_SIZE=y
++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_LZMA_COMPRESS=y
++CONFIG_LZMA_DECOMPRESS=y
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3562v100_amp_emmc_defconfig b/arch/arm/configs/hi3562v100_amp_emmc_defconfig
+new file mode 100644
+index 0000000..9cf155b
+--- /dev/null
++++ b/arch/arm/configs/hi3562v100_amp_emmc_defconfig
+@@ -0,0 +1,2825 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TINY_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++# CONFIG_RCU_STALL_COMMON is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++# CONFIG_UTS_NS is not set
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_NET_NS is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR is not set
++CONFIG_CC_STACKPROTECTOR_NONE=y
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++# CONFIG_CC_STACKPROTECTOR_STRONG is not set
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_NOOP=y
++CONFIG_DEFAULT_IOSCHED="noop"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++# CONFIG_ARCH_HI3559V200 is not set
++CONFIG_ARCH_HI3562V100=y
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++CONFIG_HISI_MC=y
++CONFIG_AMP_ZRELADDR=0x82008000
++CONFIG_HI_ZRELADDR=0x82008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++# CONFIG_SMP is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_200=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=200
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_NEED_PER_CPU_KM=y
++# CONFIG_CLEANCACHE is not set
++# CONFIG_CMA is not set
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++# CONFIG_KERNEL_MODE_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++CONFIG_VLAN_8021Q=y
++# CONFIG_VLAN_8021Q_GVRP is not set
++# CONFIG_VLAN_8021Q_MVRP is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++# CONFIG_CFG80211_WEXT is not set
++# CONFIG_LIB80211 is not set
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_MINSTREL_HT=y
++# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++# CONFIG_MTD is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++CONFIG_HISI_FEMAC=y
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++# CONFIG_HIETH_GMAC is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++CONFIG_MDIO_HISI_FEMAC=y
++# CONFIG_MDIO_HISI_GEMAC is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_WLAN_VENDOR_BROADCOM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_BRCMSMAC is not set
++# CONFIG_BRCMFMAC is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++CONFIG_WLAN_VENDOR_ZYDAS=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_ZD1211RW is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=m
++CONFIG_VIDEOBUF2_MEMOPS=m
++CONFIG_VIDEOBUF2_VMALLOC=m
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=m
++CONFIG_USB_XHCI_PLATFORM=m
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=m
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++# CONFIG_USB_DWC3_OF_SIMPLE is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_ECM=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++CONFIG_USB_CONFIGFS_ACM=y
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++CONFIG_USB_CONFIGFS_ECM=y
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++CONFIG_USB_CONFIGFS_RNDIS=y
++# CONFIG_USB_CONFIGFS_EEM is not set
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_PWRSEQ_EMMC is not set
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=y
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++CONFIG_SYNC_FILE=y
++CONFIG_SW_SYNC=y
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3562V100=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++CONFIG_USB_DRD0_IN_HOST=y
++# CONFIG_USB_DRD0_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++# CONFIG_EXT2_FS is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=m
++# CONFIG_FUSE_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3562v100_amp_spinand_defconfig b/arch/arm/configs/hi3562v100_amp_spinand_defconfig
+new file mode 100644
+index 0000000..4662b54
+--- /dev/null
++++ b/arch/arm/configs/hi3562v100_amp_spinand_defconfig
+@@ -0,0 +1,2937 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TINY_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++# CONFIG_RCU_STALL_COMMON is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++# CONFIG_UTS_NS is not set
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_NET_NS is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR is not set
++CONFIG_CC_STACKPROTECTOR_NONE=y
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++# CONFIG_CC_STACKPROTECTOR_STRONG is not set
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_NOOP=y
++CONFIG_DEFAULT_IOSCHED="noop"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++# CONFIG_ARCH_HI3559V200 is not set
++CONFIG_ARCH_HI3562V100=y
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++CONFIG_HISI_MC=y
++CONFIG_AMP_ZRELADDR=0x82008000
++CONFIG_HI_ZRELADDR=0x82008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++# CONFIG_SMP is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_200=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=200
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_NEED_PER_CPU_KM=y
++# CONFIG_CLEANCACHE is not set
++# CONFIG_CMA is not set
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++# CONFIG_KERNEL_MODE_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++CONFIG_VLAN_8021Q=y
++# CONFIG_VLAN_8021Q_GVRP is not set
++# CONFIG_VLAN_8021Q_MVRP is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++# CONFIG_CFG80211_WEXT is not set
++# CONFIG_LIB80211 is not set
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_MINSTREL_HT=y
++# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_LPDDR2_NVM is not set
++# CONFIG_MTD_SPI_NOR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++CONFIG_HISI_FEMAC=y
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++# CONFIG_HIETH_GMAC is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++CONFIG_MDIO_HISI_FEMAC=y
++# CONFIG_MDIO_HISI_GEMAC is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_WLAN_VENDOR_BROADCOM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_BRCMSMAC is not set
++# CONFIG_BRCMFMAC is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++CONFIG_WLAN_VENDOR_ZYDAS=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_ZD1211RW is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=m
++CONFIG_VIDEOBUF2_MEMOPS=m
++CONFIG_VIDEOBUF2_VMALLOC=m
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=m
++CONFIG_USB_XHCI_PLATFORM=m
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=m
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++# CONFIG_USB_DWC3_OF_SIMPLE is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_ECM=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++CONFIG_USB_CONFIGFS_ACM=y
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++CONFIG_USB_CONFIGFS_ECM=y
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++CONFIG_USB_CONFIGFS_RNDIS=y
++# CONFIG_USB_CONFIGFS_EEM is not set
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=m
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_PWRSEQ_EMMC is not set
++CONFIG_PWRSEQ_SIMPLE=m
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=m
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=m
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++CONFIG_SYNC_FILE=y
++CONFIG_SW_SYNC=y
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3562V100=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++CONFIG_USB_DRD0_IN_HOST=y
++# CONFIG_USB_DRD0_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=m
++# CONFIG_FUSE_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++# CONFIG_JFFS2_FS is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3566v100_amp_defconfig b/arch/arm/configs/hi3566v100_amp_defconfig
+new file mode 100644
+index 0000000..57e241e
+--- /dev/null
++++ b/arch/arm/configs/hi3566v100_amp_defconfig
+@@ -0,0 +1,2924 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TINY_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++# CONFIG_RCU_STALL_COMMON is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++# CONFIG_UTS_NS is not set
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_NET_NS is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR is not set
++CONFIG_CC_STACKPROTECTOR_NONE=y
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++# CONFIG_CC_STACKPROTECTOR_STRONG is not set
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_NOOP=y
++CONFIG_DEFAULT_IOSCHED="noop"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++CONFIG_ARCH_HI3566V100=y
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++CONFIG_HISI_MC=y
++CONFIG_AMP_ZRELADDR=0x82008000
++CONFIG_HI_ZRELADDR=0x82008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++# CONFIG_SMP is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_200=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=200
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_NEED_PER_CPU_KM=y
++# CONFIG_CLEANCACHE is not set
++# CONFIG_CMA is not set
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++# CONFIG_KERNEL_MODE_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++CONFIG_VLAN_8021Q=y
++# CONFIG_VLAN_8021Q_GVRP is not set
++# CONFIG_VLAN_8021Q_MVRP is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++# CONFIG_CFG80211_WEXT is not set
++# CONFIG_LIB80211 is not set
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_MINSTREL_HT=y
++# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++# CONFIG_MTD_NAND is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_LPDDR2_NVM is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_CADENCE_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++# CONFIG_MTD_UBI is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++CONFIG_HISI_FEMAC=y
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++# CONFIG_HIETH_GMAC is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++CONFIG_MDIO_HISI_FEMAC=y
++# CONFIG_MDIO_HISI_GEMAC is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_WLAN_VENDOR_BROADCOM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_BRCMSMAC is not set
++# CONFIG_BRCMFMAC is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++CONFIG_WLAN_VENDOR_ZYDAS=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_ZD1211RW is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=m
++CONFIG_VIDEOBUF2_MEMOPS=m
++CONFIG_VIDEOBUF2_VMALLOC=m
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=m
++CONFIG_USB_XHCI_PLATFORM=m
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_GADGET is not set
++# CONFIG_USB_MUSB_DUAL_ROLE is not set
++CONFIG_USB_DWC3=m
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++# CONFIG_USB_DWC3_OF_SIMPLE is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_ECM=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++CONFIG_USB_CONFIGFS_ACM=y
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++CONFIG_USB_CONFIGFS_ECM=y
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++CONFIG_USB_CONFIGFS_RNDIS=y
++# CONFIG_USB_CONFIGFS_EEM is not set
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=m
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_PWRSEQ_EMMC is not set
++CONFIG_PWRSEQ_SIMPLE=m
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=m
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=m
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++CONFIG_SYNC_FILE=y
++CONFIG_SW_SYNC=y
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3566V100=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++CONFIG_USB_DRD0_IN_HOST=y
++# CONFIG_USB_DRD0_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=m
++# CONFIG_FUSE_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_YAFFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_LZMA=y
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_JFFS2_CMODE_NONE is not set
++# CONFIG_JFFS2_CMODE_PRIORITY is not set
++CONFIG_JFFS2_CMODE_SIZE=y
++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_LZMA_COMPRESS=y
++CONFIG_LZMA_DECOMPRESS=y
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3566v100_amp_emmc_defconfig b/arch/arm/configs/hi3566v100_amp_emmc_defconfig
+new file mode 100644
+index 0000000..b4fbf2a
+--- /dev/null
++++ b/arch/arm/configs/hi3566v100_amp_emmc_defconfig
+@@ -0,0 +1,2825 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TINY_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++# CONFIG_RCU_STALL_COMMON is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++# CONFIG_UTS_NS is not set
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_NET_NS is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR is not set
++CONFIG_CC_STACKPROTECTOR_NONE=y
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++# CONFIG_CC_STACKPROTECTOR_STRONG is not set
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_NOOP=y
++CONFIG_DEFAULT_IOSCHED="noop"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++CONFIG_ARCH_HI3566V100=y
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++CONFIG_HISI_MC=y
++CONFIG_AMP_ZRELADDR=0x82008000
++CONFIG_HI_ZRELADDR=0x82008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++# CONFIG_SMP is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_200=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=200
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_NEED_PER_CPU_KM=y
++# CONFIG_CLEANCACHE is not set
++# CONFIG_CMA is not set
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++# CONFIG_KERNEL_MODE_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++CONFIG_VLAN_8021Q=y
++# CONFIG_VLAN_8021Q_GVRP is not set
++# CONFIG_VLAN_8021Q_MVRP is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++# CONFIG_CFG80211_WEXT is not set
++# CONFIG_LIB80211 is not set
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_MINSTREL_HT=y
++# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++# CONFIG_MTD is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++CONFIG_HISI_FEMAC=y
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++# CONFIG_HIETH_GMAC is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++CONFIG_MDIO_HISI_FEMAC=y
++# CONFIG_MDIO_HISI_GEMAC is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_WLAN_VENDOR_BROADCOM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_BRCMSMAC is not set
++# CONFIG_BRCMFMAC is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++CONFIG_WLAN_VENDOR_ZYDAS=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_ZD1211RW is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=m
++CONFIG_VIDEOBUF2_MEMOPS=m
++CONFIG_VIDEOBUF2_VMALLOC=m
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=m
++CONFIG_USB_XHCI_PLATFORM=m
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=m
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++# CONFIG_USB_DWC3_OF_SIMPLE is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_ECM=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++CONFIG_USB_CONFIGFS_ACM=y
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++CONFIG_USB_CONFIGFS_ECM=y
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++CONFIG_USB_CONFIGFS_RNDIS=y
++# CONFIG_USB_CONFIGFS_EEM is not set
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_PWRSEQ_EMMC is not set
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=y
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++CONFIG_SYNC_FILE=y
++CONFIG_SW_SYNC=y
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3566V100=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++CONFIG_USB_DRD0_IN_HOST=y
++# CONFIG_USB_DRD0_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++# CONFIG_EXT2_FS is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=m
++# CONFIG_FUSE_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi3566v100_amp_spinand_defconfig b/arch/arm/configs/hi3566v100_amp_spinand_defconfig
+new file mode 100644
+index 0000000..c5b29d2
+--- /dev/null
++++ b/arch/arm/configs/hi3566v100_amp_spinand_defconfig
+@@ -0,0 +1,2937 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TINY_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++# CONFIG_RCU_STALL_COMMON is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++# CONFIG_UTS_NS is not set
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_NET_NS is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR is not set
++CONFIG_CC_STACKPROTECTOR_NONE=y
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++# CONFIG_CC_STACKPROTECTOR_STRONG is not set
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_NOOP=y
++CONFIG_DEFAULT_IOSCHED="noop"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++# CONFIG_ARCH_HI3556V200 is not set
++# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++CONFIG_ARCH_HI3566V100=y
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++CONFIG_HISI_MC=y
++CONFIG_AMP_ZRELADDR=0x82008000
++CONFIG_HI_ZRELADDR=0x82008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++# CONFIG_SMP is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_200=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=200
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_NEED_PER_CPU_KM=y
++# CONFIG_CLEANCACHE is not set
++# CONFIG_CMA is not set
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++# CONFIG_KERNEL_MODE_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++CONFIG_VLAN_8021Q=y
++# CONFIG_VLAN_8021Q_GVRP is not set
++# CONFIG_VLAN_8021Q_MVRP is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++# CONFIG_CFG80211_WEXT is not set
++# CONFIG_LIB80211 is not set
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_MINSTREL_HT=y
++# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_LPDDR2_NVM is not set
++# CONFIG_MTD_SPI_NOR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++CONFIG_HISI_FEMAC=y
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++# CONFIG_HIETH_GMAC is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++CONFIG_MDIO_HISI_FEMAC=y
++# CONFIG_MDIO_HISI_GEMAC is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_WLAN_VENDOR_BROADCOM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_BRCMSMAC is not set
++# CONFIG_BRCMFMAC is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++CONFIG_WLAN_VENDOR_ZYDAS=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_ZD1211RW is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=m
++CONFIG_VIDEOBUF2_MEMOPS=m
++CONFIG_VIDEOBUF2_VMALLOC=m
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=m
++CONFIG_USB_XHCI_PLATFORM=m
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=m
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++# CONFIG_USB_DWC3_OF_SIMPLE is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_ECM=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++CONFIG_USB_CONFIGFS_ACM=y
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++CONFIG_USB_CONFIGFS_ECM=y
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++CONFIG_USB_CONFIGFS_RNDIS=y
++# CONFIG_USB_CONFIGFS_EEM is not set
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=m
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_PWRSEQ_EMMC is not set
++CONFIG_PWRSEQ_SIMPLE=m
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=m
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=m
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++CONFIG_SYNC_FILE=y
++CONFIG_SW_SYNC=y
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3566V100=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++CONFIG_USB_DRD0_IN_HOST=y
++# CONFIG_USB_DRD0_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=m
++# CONFIG_FUSE_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++# CONFIG_JFFS2_FS is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff --git a/arch/arm/configs/hi_eth_defconfig b/arch/arm/configs/hi_eth_defconfig
+new file mode 100644
+index 0000000..39ecf0a
+--- /dev/null
++++ b/arch/arm/configs/hi_eth_defconfig
+@@ -0,0 +1,3083 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 4.9.37 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_ARM_HAS_SG_CHAIN=y
++CONFIG_MIGHT_HAVE_PCI=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_PGTABLE_LEVELS=2
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_FHANDLE=y
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_DOMAIN_DEBUG=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_NMI_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_CGROUPS=y
++# CONFIG_MEMCG is not set
++# CONFIG_BLK_CGROUP is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_FREEZER is not set
++# CONFIG_CPUSETS is not set
++# CONFIG_CGROUP_DEVICE is not set
++# CONFIG_CGROUP_CPUACCT is not set
++# CONFIG_CGROUP_DEBUG is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_BPF=y
++# CONFIG_EXPERT is not set
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_BPF_SYSCALL is not set
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++# CONFIG_USERFAULTFD is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=16
++CONFIG_ARCH_MMAP_RND_BITS=8
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++CONFIG_ARCH_MULTIPLATFORM=y
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP1 is not set
++
++#
++# Multiple platform selection
++#
++
++#
++# CPU Core family selection
++#
++# CONFIG_ARCH_MULTI_V6 is not set
++CONFIG_ARCH_MULTI_V7=y
++CONFIG_ARCH_MULTI_V6_V7=y
++# CONFIG_ARCH_MULTI_CPU_AUTO is not set
++# CONFIG_ARCH_VIRT is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_ARTPEC is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCM is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_DIGICOLOR is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++
++#
++# Hisilicon BVT platform type
++#
++# CONFIG_ARCH_HI3516A is not set
++# CONFIG_ARCH_HI3516CV500 is not set
++# CONFIG_ARCH_HI3516DV300 is not set
++# CONFIG_ARCH_HI3516EV200 is not set
++# CONFIG_ARCH_HI3516EV300 is not set
++# CONFIG_ARCH_HI3518EV300 is not set
++# CONFIG_ARCH_HI3516DV200 is not set
++CONFIG_ARCH_HI3556V200=y
++# CONFIG_ARCH_HI3559V200 is not set
++# CONFIG_ARCH_HI3562V100 is not set
++# CONFIG_ARCH_HI3566V100 is not set
++# CONFIG_ARCH_HI3536DV100 is not set
++# CONFIG_ARCH_HI3521A is not set
++# CONFIG_ARCH_HI3531A is not set
++# CONFIG_ARCH_HI3556AV100 is not set
++# CONFIG_ARCH_HI3519AV100 is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_HISI_MC is not set
++CONFIG_HI_ZRELADDR=0x80008000
++CONFIG_HI_PARAMS_PHYS=0x00000100
++CONFIG_HI_INITRD_PHYS=0x00800000
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MEDIATEK is not set
++
++#
++# TI OMAP/AM/DM/DRA Family
++#
++# CONFIG_ARCH_OMAP3 is not set
++# CONFIG_ARCH_OMAP4 is not set
++# CONFIG_SOC_OMAP5 is not set
++# CONFIG_SOC_AM33XX is not set
++# CONFIG_SOC_AM43XX is not set
++# CONFIG_SOC_DRA7XX is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_SIRF is not set
++# CONFIG_ARCH_TANGO is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_WM8850 is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQ is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_SWP_EMULATE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_KUSER_HELPERS=y
++CONFIG_VDSO=y
++CONFIG_MIGHT_HAVE_CACHE_L2X0=y
++# CONFIG_CACHE_L2X0 is not set
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_DEBUG_ALIGN_RODATA=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_643719 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++# CONFIG_ARM_ERRATA_798181 is not set
++# CONFIG_ARM_ERRATA_773022 is not set
++# CONFIG_ARM_ERRATA_818325_852422 is not set
++# CONFIG_ARM_ERRATA_821420 is not set
++# CONFIG_ARM_ERRATA_825619 is not set
++# CONFIG_ARM_ERRATA_852421 is not set
++# CONFIG_ARM_ERRATA_852423 is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI is not set
++# CONFIG_PCI_DOMAINS_GENERIC is not set
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_ARM_CPU_TOPOLOGY=y
++# CONFIG_SCHED_MC is not set
++# CONFIG_SCHED_SMT is not set
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++# CONFIG_MCPM is not set
++# CONFIG_BIG_LITTLE is not set
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_3G_OPT is not set
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++CONFIG_NR_CPUS=2
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_ARM_PSCI is not set
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_FIXED=0
++CONFIG_HZ_100=y
++# CONFIG_HZ_200 is not set
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_500 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_ARM_PATCH_IDIV=y
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CPU_SW_DOMAIN_PAN=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_BOUNCE=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUG=y
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_XEN is not set
++
++#
++# Boot options
++#
++CONFIG_USE_OF=y
++CONFIG_ATAGS=y
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
++CONFIG_CMDLINE=""
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++CONFIG_AUTO_ZRELADDR=y
++# CONFIG_EFI is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_FPE_NWFPE is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_FLAT is not set
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_NET_IP_TUNNEL is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++CONFIG_VLAN_8021Q=y
++# CONFIG_VLAN_8021Q_GVRP is not set
++# CONFIG_VLAN_8021Q_MVRP is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_DST_CACHE is not set
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=16
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_LPDDR2_NVM is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_CADENCE_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_MTD_UBI_GLUEBI is not set
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++CONFIG_HISI_FEMAC=y
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++# CONFIG_HIETH_GMAC is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++CONFIG_MDIO_HISI_FEMAC=y
++# CONFIG_MDIO_HISI_GEMAC is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++CONFIG_USB_RTL8152=y
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++CONFIG_JOYSTICK_XPAD=y
++CONFIG_JOYSTICK_XPAD_FF=y
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_SINGLE is not set
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_EM is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_ZEVIO is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++# CONFIG_HTC_EGPIO is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++CONFIG_POWER_RESET_HISI=y
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_VERSATILE is not set
++CONFIG_POWER_RESET_SYSCON=y
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_PM8921_CORE is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_REGULATOR is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# Audio decoders, processors and mixers
++#
++
++#
++# RDS decoders
++#
++
++#
++# Video decoders
++#
++
++#
++# Video and audio decoders
++#
++
++#
++# Video encoders
++#
++
++#
++# Camera sensor devices
++#
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++
++#
++# Audio/Video compression chips
++#
++
++#
++# Miscellaneous helper chips
++#
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++# CONFIG_IMX_IPUV3_CORE is not set
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_ACM=m
++CONFIG_USB_U_SERIAL=m
++CONFIG_USB_U_ETHER=m
++CONFIG_USB_F_RNDIS=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_RNDIS=y
++# CONFIG_USB_G_MULTI_CDC is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++# CONFIG_MMC_SDHCI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++CONFIG_HIMCI=y
++# CONFIG_SEND_AUTO_STOP is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_SNVS is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++CONFIG_COMMON_CLK_HI3556V200=y
++CONFIG_RESET_HISI=y
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_ARM_TIMER_SP804=y
++CONFIG_TIMER_HISP804=y
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_SOC_BRCMSTB is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_ZYNQ is not set
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_PHY_HISI_USB2=y
++# CONFIG_PHY_HISI_USB3 is not set
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++CONFIG_USB_DRD0_IN_HOST=y
++# CONFIG_USB_DRD0_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_UBIFS_FS is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHED_INFO is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM_PTDUMP is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_LL is not set
++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
++# CONFIG_DEBUG_UART_8250 is not set
++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=m
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++# CONFIG_CRYPTO_SEQIV is not set
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_CMAC is not set
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=m
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++# CONFIG_ASYMMETRIC_KEY_TYPE is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM_CRYPTO is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
++# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h
deleted file mode 100644
index 6bda945..0000000
@@ -144597,7 +179090,7 @@ index 1f59ea0..8bedc3a 100644
}
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
-index 8e8d20c..c23f2ab 100644
+index 8e8d20c..b3d21a2 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -53,6 +53,11 @@ extern void fpundefinstr(void);
@@ -144606,7 +179099,7 @@ index 8e8d20c..c23f2ab 100644
void mmiocpy(void *, const void *, size_t);
+#ifdef CONFIG_HI_VDMA_V100
+extern int vdma_flag;
-+extern int hi_memcpy(void *dst, const void *src, size_t count);
++extern int hi_vdma_m2m_copy(void *dst, const void *src, size_t count);
+int vdma_waterline = CONFIG_HI_VDMA_TRANSFER_THRESHOLD;
+#endif
@@ -144624,7 +179117,7 @@ index 8e8d20c..c23f2ab 100644
+
+ if (n >= vdma_waterline * 1024) {
+ if (vdma_flag == 1) {
-+ ret = hi_memcpy(dest, src, n);
++ ret = hi_vdma_m2m_copy(dest, src, n);
+
+ if (ret < 0)
+ _memcpy(dest, src, n);
@@ -144652,7 +179145,7 @@ index 8e8d20c..c23f2ab 100644
+
+ if (n >= vdma_waterline * 1024) {
+ if (vdma_flag == 1) {
-+ ret = hi_memcpy(to, from, n);
++ ret = hi_vdma_m2m_copy(to, from, n);
+
+ if (ret < 0)
+ ret = __copy_from_user(to, from, n);
@@ -144673,7 +179166,7 @@ index 8e8d20c..c23f2ab 100644
+
+ if (n >= vdma_waterline * 1024) {
+ if (vdma_flag == 1) {
-+ ret = hi_memcpy(to, from, n);
++ ret = hi_vdma_m2m_copy(to, from, n);
+
+ if (ret < 0)
+ ret = __copy_to_user(to, from, n);
@@ -144765,10 +179258,10 @@ index 64111bd..e84488a 100644
ENDPROC(mmiocpy)
diff --git a/arch/arm/mach-hibvt/Kconfig b/arch/arm/mach-hibvt/Kconfig
new file mode 100644
-index 0000000..49db14f
+index 0000000..097260f
--- /dev/null
+++ b/arch/arm/mach-hibvt/Kconfig
-@@ -0,0 +1,216 @@
+@@ -0,0 +1,236 @@
+config ARCH_HISI_BVT
+ bool "Hisilicon BVT SoC Support"
+ select ARM_AMBA
@@ -144863,6 +179356,24 @@ index 0000000..49db14f
+ help
+ Support for Hisilicon Hi3559V200 Soc family.
+
++config ARCH_HI3562V100
++ bool "Hisilicon Hi3562V100 Cortex-A7 family"
++ depends on ARCH_MULTI_V7
++ select HAVE_ARM_ARCH_TIMER
++ select PINCTRL
++ select POWER_RESET_HISI
++ help
++ Support for Hisilicon Hi3562V100 Soc family.
++
++config ARCH_HI3566V100
++ bool "Hisilicon Hi3566V100 Cortex-A7 family"
++ depends on ARCH_MULTI_V7
++ select HAVE_ARM_ARCH_TIMER
++ select PINCTRL
++ select POWER_RESET_HISI
++ help
++ Support for Hisilicon Hi3566V100 Soc family.
++
+config ARCH_HI3518EV20X
+ bool "Hisilicon Hi3518ev20x ARM926T(Single) family"
+ depends on ARCH_MULTI_V5
@@ -144943,7 +179454,7 @@ index 0000000..49db14f
+
+config ARCH_HISI_BVT_AMP
+ bool "Hisilicon AMP solution support"
-+ depends on ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200
++ depends on ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200 || ARCH_HI3562V100 || ARCH_HI3566V100
+ help
+ support for Hisilicon AMP solution
+
@@ -144957,7 +179468,7 @@ index 0000000..49db14f
+ hex 'amp zreladdr'
+ depends on ARCH_HISI_BVT_AMP
+ default "0x32008000" if ARCH_HI3556AV100 || ARCH_HI3519AV100
-+ default "0x82008000" if ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200
++ default "0x82008000" if ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200 || ARCH_HI3562V100 || ARCH_HI3566V100
+ default "0x42008000" if ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV200
+
+config HI_ZRELADDR
@@ -144966,6 +179477,8 @@ index 0000000..49db14f
+ default "0x80008000" if ARCH_HI3516DV300
+ default "0x80008000" if ARCH_HI3556V200
+ default "0x80008000" if ARCH_HI3559V200
++ default "0x80008000" if ARCH_HI3562V100
++ default "0x80008000" if ARCH_HI3566V100
+ default "0x80008000" if ARCH_HI3516A
+ default "0x80008000" if ARCH_HI3518EV20X
+ default "0x80008000" if ARCH_HI3536DV100
@@ -144987,10 +179500,10 @@ index 0000000..49db14f
+endif
diff --git a/arch/arm/mach-hibvt/Makefile b/arch/arm/mach-hibvt/Makefile
new file mode 100644
-index 0000000..6a38110
+index 0000000..ece00ba
--- /dev/null
+++ b/arch/arm/mach-hibvt/Makefile
-@@ -0,0 +1,23 @@
+@@ -0,0 +1,25 @@
+#
+# Makefile for Hisilicon processors family
+#
@@ -145004,6 +179517,8 @@ index 0000000..6a38110
+obj-$(CONFIG_ARCH_HI3516DV300) += mach-hi3516dv300.o
+obj-$(CONFIG_ARCH_HI3556V200) += mach-hi3556v200.o
+obj-$(CONFIG_ARCH_HI3559V200) += mach-hi3559v200.o
++obj-$(CONFIG_ARCH_HI3562V100) += mach-hi3559v200.o
++obj-$(CONFIG_ARCH_HI3566V100) += mach-hi3559v200.o
+obj-$(CONFIG_ARCH_HI3518EV20X) += mach-hi3518ev20x.o
+obj-$(CONFIG_ARCH_HI3536DV100) += mach-hi3536dv100.o
+obj-$(CONFIG_ARCH_HI3521A) += mach-hi3521a.o
@@ -145768,10 +180283,10 @@ index 0000000..790981e
+#endif /* End of __HI3516CV500_CHIP_REGS_H__ */
diff --git a/arch/arm/mach-hibvt/include/mach/io.h b/arch/arm/mach-hibvt/include/mach/io.h
new file mode 100644
-index 0000000..30ed0f8
+index 0000000..b5fd58c
--- /dev/null
+++ b/arch/arm/mach-hibvt/include/mach/io.h
-@@ -0,0 +1,44 @@
+@@ -0,0 +1,52 @@
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
@@ -145811,6 +180326,14 @@ index 0000000..30ed0f8
+#include <mach/hi3559v200_io.h>
+#endif
+
++#ifdef CONFIG_ARCH_HI3562V100
++#include <mach/hi3559v200_io.h>
++#endif
++
++#ifdef CONFIG_ARCH_HI3566V100
++#include <mach/hi3559v200_io.h>
++#endif
++
+#ifdef CONFIG_ARCH_HI3519AV100
+#include <mach/hi3519av100_io.h>
+#endif
@@ -145818,10 +180341,10 @@ index 0000000..30ed0f8
+#endif
diff --git a/arch/arm/mach-hibvt/include/mach/platform.h b/arch/arm/mach-hibvt/include/mach/platform.h
new file mode 100644
-index 0000000..c8beffc
+index 0000000..4b8473c
--- /dev/null
+++ b/arch/arm/mach-hibvt/include/mach/platform.h
-@@ -0,0 +1,40 @@
+@@ -0,0 +1,48 @@
+#ifndef __HISI_PLATFORM_H__
+#define __HISI_PLATFORM_H__
+
@@ -145853,6 +180376,14 @@ index 0000000..c8beffc
+#include <mach/hi3559v200_platform.h>
+#endif
+
++#ifdef CONFIG_ARCH_HI3562V100
++#include <mach/hi3559v200_platform.h>
++#endif
++
++#ifdef CONFIG_ARCH_HI3566V100
++#include <mach/hi3559v200_platform.h>
++#endif
++
+#ifdef CONFIG_ARCH_HI3556AV100
+#include <mach/hi3556av100_platform.h>
+#endif
@@ -145864,7 +180395,7 @@ index 0000000..c8beffc
+#endif /* End of __HISI_PLATFORM_H__ */
diff --git a/arch/arm/mach-hibvt/l2cache.c b/arch/arm/mach-hibvt/l2cache.c
new file mode 100644
-index 0000000..79a06d5
+index 0000000..73dc254
--- /dev/null
+++ b/arch/arm/mach-hibvt/l2cache.c
@@ -0,0 +1,71 @@
@@ -145898,45 +180429,45 @@ index 0000000..79a06d5
+
+static int __init l2_cache_init(void)
+{
-+ u32 val;
-+ /*
-+ * Bits Value Description
-+ * [31] 0 : SBZ
-+ * [30] 1 : Double linefill enable (L3)
-+ * [29] 1 : Instruction prefetching enable
-+ * [28] 1 : Data prefetching enabled
-+ * [27] 0 : Double linefill on WRAP read enabled (L3)
-+ * [26:25] 0 : SBZ
-+ * [24] 1 : Prefetch drop enable (L3)
-+ * [23] 0 : Incr double Linefill enable (L3)
-+ * [22] 0 : SBZ
-+ * [21] 0 : Not same ID on exclusive sequence enable (L3)
-+ * [20:5] 0 : SBZ
-+ * [4:0] 0 : use the Prefetch offset values 0.
-+ */
-+ /* writel_relaxed(0x71000000, l2x0_virt_base + L2X0_PREFETCH_CTRL); */
-+ writel_relaxed(0x71000000, l2x0_virt_base + L310_PREFETCH_CTRL);
++ u32 val;
++ /*
++ * Bits Value Description
++ * [31] 0 : SBZ
++ * [30] 1 : Double linefill enable (L3)
++ * [29] 1 : Instruction prefetching enable
++ * [28] 1 : Data prefetching enabled
++ * [27] 0 : Double linefill on WRAP read enabled (L3)
++ * [26:25] 0 : SBZ
++ * [24] 1 : Prefetch drop enable (L3)
++ * [23] 0 : Incr double Linefill enable (L3)
++ * [22] 0 : SBZ
++ * [21] 0 : Not same ID on exclusive sequence enable (L3)
++ * [20:5] 0 : SBZ
++ * [4:0] 0 : use the Prefetch offset values 0.
++ */
++ /* writel_relaxed(0x71000000, l2x0_virt_base + L2X0_PREFETCH_CTRL); */
++ writel_relaxed(0x71000000, l2x0_virt_base + L310_PREFETCH_CTRL);
+
-+ val = __raw_readl(l2x0_virt_base + L2X0_AUX_CTRL);
-+ val |= (1 << 30); /* Early BRESP enabled */
-+ val |= (1 << 0); /* Full Line of Zero Enable */
-+ writel_relaxed(val, l2x0_virt_base + L2X0_AUX_CTRL);
-+ l2x0_init(l2x0_virt_base, 0x00430000, 0xFFB0FFFF);
-+ /*
-+ * 2. enable L2 prefetch hint [1]a
-+ * 3. enable write full line of zeros mode. [3]a
-+ * a: This feature must be enabled only when the slaves
-+ * connected on the Cortex-A9 AXI master port support it.
-+ */
-+ asm volatile (
-+ " mrc p15, 0, r0, c1, c0, 1\n"
-+ " orr r0, r0, #0x02\n"
-+ " mcr p15, 0, r0, c1, c0, 1\n"
-+ :
-+ :
-+ : "r0", "cc");
++ val = __raw_readl(l2x0_virt_base + L2X0_AUX_CTRL);
++ val |= (1 << 30); /* Early BRESP enabled */
++ val |= (1 << 0); /* Full Line of Zero Enable */
++ writel_relaxed(val, l2x0_virt_base + L2X0_AUX_CTRL);
++ l2x0_init(l2x0_virt_base, 0x00430000, 0xFFB0FFFF);
++ /*
++ * 2. enable L2 prefetch hint [1]a
++ * 3. enable write full line of zeros mode. [3]a
++ * a: This feature must be enabled only when the slaves
++ * connected on the Cortex-A9 AXI master port support it.
++ */
++ asm volatile (
++ " mrc p15, 0, r0, c1, c0, 1\n"
++ " orr r0, r0, #0x02\n"
++ " mcr p15, 0, r0, c1, c0, 1\n"
++ :
++ :
++ : "r0", "cc");
+
-+ return 0;
++ return 0;
+}
+early_initcall(l2_cache_init);
diff --git a/arch/arm/mach-hibvt/mach-common.h b/arch/arm/mach-hibvt/mach-common.h
@@ -145956,7 +180487,7 @@ index 0000000..f5edadb
+#endif /* __SMP_COMMON_H */
diff --git a/arch/arm/mach-hibvt/mach-hi3516a.c b/arch/arm/mach-hibvt/mach-hi3516a.c
new file mode 100644
-index 0000000..6d9b5a5
+index 0000000..9fc8b48
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3516a.c
@@ -0,0 +1,65 @@
@@ -145994,31 +180525,31 @@ index 0000000..6d9b5a5
+ * IO space.
+ */
+static struct map_desc hi3516a_io_desc[] __initdata = {
-+ {
-+ /* hi3516a_IOCH1 */
-+ .pfn = __phys_to_pfn(HI3516A_IOCH1_PHYS),
-+ .virtual = HI3516A_IOCH1_VIRT,
-+ .length = HI3516A_IOCH1_SIZE,
-+ .type = MT_DEVICE,
-+ },
-+ {
-+ /* hi3516a_IOCH2 */
-+ .pfn = __phys_to_pfn(HI3516A_IOCH2_PHYS),
-+ .virtual = HI3516A_IOCH2_VIRT,
-+ .length = HI3516A_IOCH2_SIZE,
-+ .type = MT_DEVICE,
-+ },
++ {
++ /* hi3516a_IOCH1 */
++ .pfn = __phys_to_pfn(HI3516A_IOCH1_PHYS),
++ .virtual = HI3516A_IOCH1_VIRT,
++ .length = HI3516A_IOCH1_SIZE,
++ .type = MT_DEVICE,
++ },
++ {
++ /* hi3516a_IOCH2 */
++ .pfn = __phys_to_pfn(HI3516A_IOCH2_PHYS),
++ .virtual = HI3516A_IOCH2_VIRT,
++ .length = HI3516A_IOCH2_SIZE,
++ .type = MT_DEVICE,
++ },
+};
+
+static void __init hi3516a_map_io(void)
+{
-+ /* debug_ll_io_init(); */
-+ iotable_init(hi3516a_io_desc, ARRAY_SIZE(hi3516a_io_desc));
++ /* debug_ll_io_init(); */
++ iotable_init(hi3516a_io_desc, ARRAY_SIZE(hi3516a_io_desc));
+}
+
+static const char *const hi3516a_compat[] __initconst = {
-+ "hisilicon,hi3516a",
-+ NULL,
++ "hisilicon,hi3516a",
++ NULL,
+};
+
+DT_MACHINE_START(HI3516A_DT, "Hisilicon Hi3516A (Flattened Device Tree)")
@@ -146027,10 +180558,10 @@ index 0000000..6d9b5a5
+MACHINE_END
diff --git a/arch/arm/mach-hibvt/mach-hi3516cv500.c b/arch/arm/mach-hibvt/mach-hi3516cv500.c
new file mode 100644
-index 0000000..45a1d15
+index 0000000..773df88
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3516cv500.c
-@@ -0,0 +1,66 @@
+@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -146062,44 +180593,45 @@ index 0000000..45a1d15
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516cv500-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516cv500-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
++ iounmap(crg_base);
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3516cv500_smp, "hisilicon,hi3516cv500", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3516dv200.c b/arch/arm/mach-hibvt/mach-hi3516dv200.c
new file mode 100644
-index 0000000..950bafa
+index 0000000..66654dc
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3516dv200.c
@@ -0,0 +1,66 @@
@@ -146134,47 +180666,47 @@ index 0000000..950bafa
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516dv200-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516dv200-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3516dv200_smp, "hisilicon,hi3516dv200-smp", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3516dv300.c b/arch/arm/mach-hibvt/mach-hi3516dv300.c
new file mode 100644
-index 0000000..9ddcded
+index 0000000..141bccf
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3516dv300.c
-@@ -0,0 +1,66 @@
+@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -146206,44 +180738,45 @@ index 0000000..9ddcded
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516dv300-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516dv300-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
++ iounmap(crg_base);
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3516dv300_smp, "hisilicon,hi3516dv300", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3516ev200.c b/arch/arm/mach-hibvt/mach-hi3516ev200.c
new file mode 100644
-index 0000000..97be1fd
+index 0000000..f18e7f0
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3516ev200.c
@@ -0,0 +1,66 @@
@@ -146278,44 +180811,44 @@ index 0000000..97be1fd
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516ev200-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516ev200-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3516ev200_smp, "hisilicon,hi3516ev200-smp", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3516ev300.c b/arch/arm/mach-hibvt/mach-hi3516ev300.c
new file mode 100644
-index 0000000..05e80e6
+index 0000000..141dd15
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3516ev300.c
@@ -0,0 +1,66 @@
@@ -146350,44 +180883,44 @@ index 0000000..05e80e6
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516ev300-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516ev300-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3516ev300_smp, "hisilicon,hi3516ev300-smp", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3518ev20x.c b/arch/arm/mach-hibvt/mach-hi3518ev20x.c
new file mode 100644
-index 0000000..861f6e2
+index 0000000..9a512cd
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3518ev20x.c
@@ -0,0 +1,63 @@
@@ -146425,29 +180958,29 @@ index 0000000..861f6e2
+ * IO space.
+ */
+static struct map_desc hi3518ev20x_io_desc[] __initdata = {
-+ /* hi3518ev20x_IOCH1 */
-+ {
-+ .virtual = HI3518EV20X_IOCH1_VIRT,
-+ .pfn = __phys_to_pfn(HI3518EV20X_IOCH1_PHYS),
-+ .length = HI3518EV20X_IOCH1_SIZE,
-+ .type = MT_DEVICE
-+ },
-+ /* hi3518ev20x_IOCH2 */
-+ {
-+ .virtual = HI3518EV20X_IOCH2_VIRT,
-+ .pfn = __phys_to_pfn(HI3518EV20X_IOCH2_PHYS),
-+ .length = HI3518EV20X_IOCH2_SIZE,
-+ .type = MT_DEVICE
-+ },
++ /* hi3518ev20x_IOCH1 */
++ {
++ .virtual = HI3518EV20X_IOCH1_VIRT,
++ .pfn = __phys_to_pfn(HI3518EV20X_IOCH1_PHYS),
++ .length = HI3518EV20X_IOCH1_SIZE,
++ .type = MT_DEVICE
++ },
++ /* hi3518ev20x_IOCH2 */
++ {
++ .virtual = HI3518EV20X_IOCH2_VIRT,
++ .pfn = __phys_to_pfn(HI3518EV20X_IOCH2_PHYS),
++ .length = HI3518EV20X_IOCH2_SIZE,
++ .type = MT_DEVICE
++ },
+};
+
+static void __init hi3518ev20x_map_io(void)
+{
-+ iotable_init(hi3518ev20x_io_desc, ARRAY_SIZE(hi3518ev20x_io_desc));
++ iotable_init(hi3518ev20x_io_desc, ARRAY_SIZE(hi3518ev20x_io_desc));
+}
+static const char *const hi3518ev20x_compat[] __initconst = {
-+ "hisilicon,hi3518ev20x",
-+ NULL,
++ "hisilicon,hi3518ev20x",
++ NULL,
+};
+
+DT_MACHINE_START(HI3518EV20x_DT, "Hisilicon Hi3518EV20X (Flattened Device Tree)")
@@ -146456,7 +180989,7 @@ index 0000000..861f6e2
+MACHINE_END
diff --git a/arch/arm/mach-hibvt/mach-hi3518ev300.c b/arch/arm/mach-hibvt/mach-hi3518ev300.c
new file mode 100644
-index 0000000..013fdf7
+index 0000000..bd85caa
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3518ev300.c
@@ -0,0 +1,66 @@
@@ -146491,44 +181024,44 @@ index 0000000..013fdf7
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3518ev300-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3518ev300-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3518ev300_smp, "hisilicon,hi3518ev300-smp", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3519av100.c b/arch/arm/mach-hibvt/mach-hi3519av100.c
new file mode 100644
-index 0000000..afa0cae
+index 0000000..feb273d
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3519av100.c
@@ -0,0 +1,90 @@
@@ -146562,24 +181095,24 @@ index 0000000..afa0cae
+
+void hi3519av100_set_cpu(int cpu, bool enable)
+{
-+ void *crg_base;
-+ unsigned int val;
++ void *crg_base;
++ unsigned int val;
+
-+ crg_base = ioremap_nocache(0x04510000, 0x1000);
++ crg_base = ioremap_nocache(0x04510000, 0x1000);
+
-+ if (enable) {
-+ val = readl_relaxed(crg_base + 0xcc);
-+ val &= ~((0x1 << 25) | (0x1 << 1));
-+ writel_relaxed(val, crg_base + 0xcc);
-+ }
++ if (enable) {
++ val = readl_relaxed(crg_base + 0xcc);
++ val &= ~((0x1 << 25) | (0x1 << 1));
++ writel_relaxed(val, crg_base + 0xcc);
++ }
+
-+ iounmap(crg_base);
-+ crg_base = NULL;
++ iounmap(crg_base);
++ crg_base = NULL;
+}
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ hi3519av100_set_cpu(cpu, enable);
++ hi3519av100_set_cpu(cpu, enable);
+}
+
+static void __init hi3519av100_smp_prepare_cpus(unsigned int max_cpus)
@@ -146588,35 +181121,35 @@ index 0000000..afa0cae
+
+static void hi3519av100_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
+{
-+ void __iomem *virt;
++ void __iomem *virt;
+
-+ /* virt = phys_to_virt(start_addr); */
-+ virt = ioremap_nocache(start_addr, 0x1000);
++ /* virt = phys_to_virt(start_addr); */
++ virt = ioremap_nocache(start_addr, 0x1000);
+
-+ writel_relaxed(0xe51ff004, virt);
-+ writel_relaxed(jump_addr, virt + 4);
++ writel_relaxed(0xe51ff004, virt);
++ writel_relaxed(jump_addr, virt + 4);
+
-+ iounmap(virt);
++ iounmap(virt);
+}
+
+static int hi3519av100_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
-+ phys_addr_t jumpaddr;
++ phys_addr_t jumpaddr;
+
-+ jumpaddr = virt_to_phys(secondary_startup);
-+ hi3519av100_set_boot_addr(0x04200000, jumpaddr);
++ jumpaddr = virt_to_phys(secondary_startup);
++ hi3519av100_set_boot_addr(0x04200000, jumpaddr);
+
-+ hi3519av100_set_cpu(cpu, true);
++ hi3519av100_set_cpu(cpu, true);
+
-+ return 0;
++ return 0;
+}
+
+static const struct smp_operations hi3519av100_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi3519av100_smp_prepare_cpus,
-+ .smp_boot_secondary = hi3519av100_boot_secondary,
++ .smp_prepare_cpus = hi3519av100_smp_prepare_cpus,
++ .smp_boot_secondary = hi3519av100_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
-+ // .cpu_die = hi3xxx_cpu_die,
-+ // .cpu_kill = hi3xxx_cpu_kill,
++ // .cpu_die = hi3xxx_cpu_die,
++ // .cpu_kill = hi3xxx_cpu_kill,
+#endif
+};
+
@@ -146624,7 +181157,7 @@ index 0000000..afa0cae
+#endif
diff --git a/arch/arm/mach-hibvt/mach-hi3521a.c b/arch/arm/mach-hibvt/mach-hi3521a.c
new file mode 100644
-index 0000000..40a4199
+index 0000000..0706684
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3521a.c
@@ -0,0 +1,74 @@
@@ -146662,40 +181195,40 @@ index 0000000..40a4199
+ * IO space.
+ */
+static struct map_desc hi3521a_io_desc[] __initdata = {
-+ /* hi3521a_IOCH1 */
-+ {
-+ .pfn = __phys_to_pfn(HI3521A_IOCH1_PHYS),
-+ .virtual = HI3521A_IOCH1_VIRT,
-+ .length = HI3521A_IOCH1_SIZE,
-+ .type = MT_DEVICE,
-+ },
++ /* hi3521a_IOCH1 */
++ {
++ .pfn = __phys_to_pfn(HI3521A_IOCH1_PHYS),
++ .virtual = HI3521A_IOCH1_VIRT,
++ .length = HI3521A_IOCH1_SIZE,
++ .type = MT_DEVICE,
++ },
+
-+ /* hi3521a_IOCH2 */
-+ {
-+ .pfn = __phys_to_pfn(HI3521A_IOCH2_PHYS),
-+ .virtual = HI3521A_IOCH2_VIRT,
-+ .length = HI3521A_IOCH2_SIZE,
-+ .type = MT_DEVICE,
-+ },
++ /* hi3521a_IOCH2 */
++ {
++ .pfn = __phys_to_pfn(HI3521A_IOCH2_PHYS),
++ .virtual = HI3521A_IOCH2_VIRT,
++ .length = HI3521A_IOCH2_SIZE,
++ .type = MT_DEVICE,
++ },
+
-+ /* hi3521a_IOCH3 */
-+ {
-+ .pfn = __phys_to_pfn(HI3521A_IOCH3_PHYS),
-+ .virtual = HI3521A_IOCH3_VIRT,
-+ .length = HI3521A_IOCH3_SIZE,
-+ .type = MT_DEVICE
-+ },
++ /* hi3521a_IOCH3 */
++ {
++ .pfn = __phys_to_pfn(HI3521A_IOCH3_PHYS),
++ .virtual = HI3521A_IOCH3_VIRT,
++ .length = HI3521A_IOCH3_SIZE,
++ .type = MT_DEVICE
++ },
+};
+
+static void __init hi3521a_map_io(void)
+{
-+ /* debug_ll_io_init(); */
-+ iotable_init(hi3521a_io_desc, ARRAY_SIZE(hi3521a_io_desc));
++ /* debug_ll_io_init(); */
++ iotable_init(hi3521a_io_desc, ARRAY_SIZE(hi3521a_io_desc));
+}
+
+static const char *const hi3521a_compat[] __initconst = {
-+ "hisilicon,hi3521a",
-+ NULL,
++ "hisilicon,hi3521a",
++ NULL,
+};
+
+DT_MACHINE_START(HI3521A_DT, "Hisilicon Hi3521A (Flattened Device Tree)")
@@ -146704,7 +181237,7 @@ index 0000000..40a4199
+MACHINE_END
diff --git a/arch/arm/mach-hibvt/mach-hi3531a.c b/arch/arm/mach-hibvt/mach-hi3531a.c
new file mode 100644
-index 0000000..11c0911
+index 0000000..548fb10
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3531a.c
@@ -0,0 +1,187 @@
@@ -146749,64 +181282,64 @@ index 0000000..11c0911
+ * IO space.
+ */
+static struct map_desc hi3531a_io_desc[] __initdata = {
-+ /* hi3531a_IOCH1 */
-+ {
-+ .pfn = __phys_to_pfn(HI3531A_IOCH1_PHYS),
-+ .virtual = HI3531A_IOCH1_VIRT,
-+ .length = HI3531A_IOCH1_SIZE,
-+ .type = MT_DEVICE,
-+ },
++ /* hi3531a_IOCH1 */
++ {
++ .pfn = __phys_to_pfn(HI3531A_IOCH1_PHYS),
++ .virtual = HI3531A_IOCH1_VIRT,
++ .length = HI3531A_IOCH1_SIZE,
++ .type = MT_DEVICE,
++ },
+
-+ /* hi3531a_IOCH2 */
-+ {
-+ .pfn = __phys_to_pfn(HI3531A_IOCH2_PHYS),
-+ .virtual = HI3531A_IOCH2_VIRT,
-+ .length = HI3531A_IOCH2_SIZE,
-+ .type = MT_DEVICE,
-+ },
++ /* hi3531a_IOCH2 */
++ {
++ .pfn = __phys_to_pfn(HI3531A_IOCH2_PHYS),
++ .virtual = HI3531A_IOCH2_VIRT,
++ .length = HI3531A_IOCH2_SIZE,
++ .type = MT_DEVICE,
++ },
+
-+ /* hi3531a_IOCH3 */
-+ {
-+ .pfn = __phys_to_pfn(HI3531A_IOCH3_PHYS),
-+ .virtual = HI3531A_IOCH3_VIRT,
-+ .length = HI3531A_IOCH3_SIZE,
-+ .type = MT_DEVICE
-+ },
++ /* hi3531a_IOCH3 */
++ {
++ .pfn = __phys_to_pfn(HI3531A_IOCH3_PHYS),
++ .virtual = HI3531A_IOCH3_VIRT,
++ .length = HI3531A_IOCH3_SIZE,
++ .type = MT_DEVICE
++ },
+
-+ /* hi3531a_IOCH4 */
-+ {
-+ .pfn = __phys_to_pfn(HI3531A_IOCH4_PHYS),
-+ .virtual = HI3531A_IOCH4_VIRT,
-+ .length = HI3531A_IOCH4_SIZE,
-+ .type = MT_DEVICE
-+ },
++ /* hi3531a_IOCH4 */
++ {
++ .pfn = __phys_to_pfn(HI3531A_IOCH4_PHYS),
++ .virtual = HI3531A_IOCH4_VIRT,
++ .length = HI3531A_IOCH4_SIZE,
++ .type = MT_DEVICE
++ },
+};
+
+static void __init hi3531a_map_io(void)
+{
-+ /* debug_ll_io_init(); */
-+ iotable_init(hi3531a_io_desc, ARRAY_SIZE(hi3531a_io_desc));
++ /* debug_ll_io_init(); */
++ iotable_init(hi3531a_io_desc, ARRAY_SIZE(hi3531a_io_desc));
+}
+
+static void __init hi3531a_init_early(void)
+{
-+ /*
-+ * 1. enable L1 prefetch [2]
-+ * 4. enable allocation in one cache way only. [8]
-+ */
-+ asm volatile (
-+ " mrc p15, 0, r0, c1, c0, 1\n"
-+ " orr r0, r0, #0x104\n"
-+ " mcr p15, 0, r0, c1, c0, 1\n"
-+ :
-+ :
-+ : "r0", "cc");
++ /*
++ * 1. enable L1 prefetch [2]
++ * 4. enable allocation in one cache way only. [8]
++ */
++ asm volatile (
++ " mrc p15, 0, r0, c1, c0, 1\n"
++ " orr r0, r0, #0x104\n"
++ " mcr p15, 0, r0, c1, c0, 1\n"
++ :
++ :
++ : "r0", "cc");
+
+}
+
+static const char *const hi3531a_compat[] __initconst = {
-+ "hisilicon,hi3531a",
-+ NULL,
++ "hisilicon,hi3531a",
++ NULL,
+};
+
+DT_MACHINE_START(HI3531A_DT, "Hisilicon Hi3531A (Flattened Device Tree)")
@@ -146819,77 +181352,77 @@ index 0000000..11c0911
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3531a-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3531a-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_A9_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_A9_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_A9_SRST_CRG);
-+ regval |= (WDG1_SRST_REQ | DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_A9_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_A9_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_A9_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_A9_SRST_CRG);
++ regval |= (WDG1_SRST_REQ | DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_A9_SRST_CRG));
++ }
+
-+ iounmap(crg_base);
++ iounmap(crg_base);
+}
+
+void hi35xx_secondary_init(unsigned int cpu)
+{
-+ /*
-+ * 1. enable L1 prefetch [2]
-+ * 2. enable L2 prefetch hint [1]a
-+ * 3. enable write full line of zeros mode. [3]a
-+ * 4. enable allocation in one cache way only. [8]
-+ * a: This feature must be enabled only when the slaves
-+ * connected on the Cortex-A17 AXI master port support it.
-+ */
-+ asm volatile (
-+ " mrc p15, 0, r0, c1, c0, 1\n"
-+ " orr r0, r0, #0x0104\n"
-+ " orr r0, r0, #0x02\n"
-+ " mcr p15, 0, r0, c1, c0, 1\n"
-+ :
-+ :
-+ : "r0", "cc");
++ /*
++ * 1. enable L1 prefetch [2]
++ * 2. enable L2 prefetch hint [1]a
++ * 3. enable write full line of zeros mode. [3]a
++ * 4. enable allocation in one cache way only. [8]
++ * a: This feature must be enabled only when the slaves
++ * connected on the Cortex-A17 AXI master port support it.
++ */
++ asm volatile (
++ " mrc p15, 0, r0, c1, c0, 1\n"
++ " orr r0, r0, #0x0104\n"
++ " orr r0, r0, #0x02\n"
++ " mcr p15, 0, r0, c1, c0, 1\n"
++ :
++ :
++ : "r0", "cc");
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+void hi35xx_cpu_die(unsigned int cpu)
+{
-+ flush_cache_all();
-+ hi35xx_set_cpu(cpu, false);
-+ BUG();
++ flush_cache_all();
++ hi35xx_set_cpu(cpu, false);
++ BUG();
+}
+
+int hi35xx_cpu_kill(unsigned int cpu)
+{
-+ return 0;
++ return 0;
+}
+#endif /* CONFIG_HOTPLUG_CPU */
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_secondary_init = hi35xx_secondary_init,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_secondary_init = hi35xx_secondary_init,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
-+ .cpu_die = hi35xx_cpu_die,
-+ .cpu_kill = hi35xx_cpu_kill,
++ .cpu_die = hi35xx_cpu_die,
++ .cpu_kill = hi35xx_cpu_kill,
+#endif
+};
+
@@ -146897,7 +181430,7 @@ index 0000000..11c0911
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3536dv100.c b/arch/arm/mach-hibvt/mach-hi3536dv100.c
new file mode 100644
-index 0000000..fd3cf27
+index 0000000..c729255
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3536dv100.c
@@ -0,0 +1,70 @@
@@ -146935,36 +181468,36 @@ index 0000000..fd3cf27
+ * IO space.
+ */
+static struct map_desc hi3536dv100_io_desc[] __initdata = {
-+ /* hi3536dv100_IOCH1 */
-+ {
-+ .virtual = HI3536DV100_IOCH1_VIRT,
-+ .pfn = __phys_to_pfn(HI3536DV100_IOCH1_PHYS),
-+ .length = HI3536DV100_IOCH1_SIZE,
-+ .type = MT_DEVICE
-+ },
-+ /* hi3536dv100_IOCH2 */
-+ {
-+ .virtual = HI3536DV100_IOCH2_VIRT,
-+ .pfn = __phys_to_pfn(HI3536DV100_IOCH2_PHYS),
-+ .length = HI3536DV100_IOCH2_SIZE,
-+ .type = MT_DEVICE
-+ },
-+ /* hi3536dv100_IOCH3 */
-+ {
-+ .virtual = HI3536DV100_IOCH3_VIRT,
-+ .pfn = __phys_to_pfn(HI3536DV100_IOCH3_PHYS),
-+ .length = HI3536DV100_IOCH3_SIZE,
-+ .type = MT_DEVICE
-+ },
++ /* hi3536dv100_IOCH1 */
++ {
++ .virtual = HI3536DV100_IOCH1_VIRT,
++ .pfn = __phys_to_pfn(HI3536DV100_IOCH1_PHYS),
++ .length = HI3536DV100_IOCH1_SIZE,
++ .type = MT_DEVICE
++ },
++ /* hi3536dv100_IOCH2 */
++ {
++ .virtual = HI3536DV100_IOCH2_VIRT,
++ .pfn = __phys_to_pfn(HI3536DV100_IOCH2_PHYS),
++ .length = HI3536DV100_IOCH2_SIZE,
++ .type = MT_DEVICE
++ },
++ /* hi3536dv100_IOCH3 */
++ {
++ .virtual = HI3536DV100_IOCH3_VIRT,
++ .pfn = __phys_to_pfn(HI3536DV100_IOCH3_PHYS),
++ .length = HI3536DV100_IOCH3_SIZE,
++ .type = MT_DEVICE
++ },
+};
+
+static void __init hi3536dv100_map_io(void)
+{
-+ iotable_init(hi3536dv100_io_desc, ARRAY_SIZE(hi3536dv100_io_desc));
++ iotable_init(hi3536dv100_io_desc, ARRAY_SIZE(hi3536dv100_io_desc));
+}
+static const char *const hi3536dv100_compat[] __initconst = {
-+ "hisilicon,hi3536dv100",
-+ NULL,
++ "hisilicon,hi3536dv100",
++ NULL,
+};
+
+DT_MACHINE_START(HI3536DV100_DT, "Hisilicon Hi3536DV100 (Flattened Device Tree)")
@@ -146973,7 +181506,7 @@ index 0000000..fd3cf27
+MACHINE_END
diff --git a/arch/arm/mach-hibvt/mach-hi3556av100.c b/arch/arm/mach-hibvt/mach-hi3556av100.c
new file mode 100644
-index 0000000..33cae5d
+index 0000000..00ff8a6
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3556av100.c
@@ -0,0 +1,93 @@
@@ -147008,24 +181541,24 @@ index 0000000..33cae5d
+
+void hi3556av100_set_cpu(int cpu, bool enable)
+{
-+ void *crg_base;
-+ unsigned int val;
++ void *crg_base;
++ unsigned int val;
+
-+ crg_base = ioremap_nocache(0x04510000, 0x1000);
++ crg_base = ioremap_nocache(0x04510000, 0x1000);
+
-+ if (enable) {
-+ val = readl_relaxed(crg_base + 0xcc);
-+ val &= ~((0x1 << 25) | (0x1 << 1));
-+ writel_relaxed(val, crg_base + 0xcc);
-+ }
++ if (enable) {
++ val = readl_relaxed(crg_base + 0xcc);
++ val &= ~((0x1 << 25) | (0x1 << 1));
++ writel_relaxed(val, crg_base + 0xcc);
++ }
+
-+ iounmap(crg_base);
-+ crg_base = NULL;
++ iounmap(crg_base);
++ crg_base = NULL;
+}
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ hi3556av100_set_cpu(cpu, enable);
++ hi3556av100_set_cpu(cpu, enable);
+}
+
+static void __init hi3556av100_smp_prepare_cpus(unsigned int max_cpus)
@@ -147034,37 +181567,37 @@ index 0000000..33cae5d
+
+static void hi3556av100_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
+{
-+ void __iomem *virt;
++ void __iomem *virt;
+
-+ /* virt = phys_to_virt(start_addr); */
-+ virt = ioremap_nocache(start_addr, 0x1000);
++ /* virt = phys_to_virt(start_addr); */
++ virt = ioremap_nocache(start_addr, 0x1000);
+
-+ writel_relaxed(0xe51ff004, virt);
-+ writel_relaxed(jump_addr, virt + 4);
++ writel_relaxed(0xe51ff004, virt);
++ writel_relaxed(jump_addr, virt + 4);
+
-+ iounmap(virt);
++ iounmap(virt);
+}
+
+static int hi3556av100_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
-+ phys_addr_t jumpaddr;
-+ unsigned int remap_reg_value = 0;
-+ struct device_node *node;
++ phys_addr_t jumpaddr;
++ unsigned int remap_reg_value = 0;
++ struct device_node *node = NULL;
+
-+ jumpaddr = virt_to_phys(secondary_startup);
-+ hi3556av100_set_boot_addr(0x04200000, jumpaddr);
++ jumpaddr = virt_to_phys(secondary_startup);
++ hi3556av100_set_boot_addr(0x04200000, jumpaddr);
+
-+ hi3556av100_set_cpu(cpu, true);
++ hi3556av100_set_cpu(cpu, true);
+
-+ return 0;
++ return 0;
+}
+
+static const struct smp_operations hi3556av100_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi3556av100_smp_prepare_cpus,
-+ .smp_boot_secondary = hi3556av100_boot_secondary,
++ .smp_prepare_cpus = hi3556av100_smp_prepare_cpus,
++ .smp_boot_secondary = hi3556av100_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
-+ // .cpu_die = hi3xxx_cpu_die,
-+ // .cpu_kill = hi3xxx_cpu_kill,
++ // .cpu_die = hi3xxx_cpu_die,
++ // .cpu_kill = hi3xxx_cpu_kill,
+#endif
+};
+
@@ -147072,10 +181605,10 @@ index 0000000..33cae5d
+#endif
diff --git a/arch/arm/mach-hibvt/mach-hi3556v200.c b/arch/arm/mach-hibvt/mach-hi3556v200.c
new file mode 100644
-index 0000000..72d7dff
+index 0000000..f1d42c5
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3556v200.c
-@@ -0,0 +1,66 @@
+@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -147107,47 +181640,48 @@ index 0000000..72d7dff
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3556v200-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3556v200-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
++ iounmap(crg_base);
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3556v200_smp, "hisilicon,hi3556v200", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/mach-hi3559v200.c b/arch/arm/mach-hibvt/mach-hi3559v200.c
new file mode 100644
-index 0000000..5cd596b
+index 0000000..36209e5
--- /dev/null
+++ b/arch/arm/mach-hibvt/mach-hi3559v200.c
-@@ -0,0 +1,66 @@
+@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -147179,44 +181713,45 @@ index 0000000..5cd596b
+
+void hi35xx_set_cpu(unsigned int cpu, bool enable)
+{
-+ struct device_node *np = NULL;
-+ unsigned int regval;
-+ void __iomem *crg_base;
++ struct device_node *np = NULL;
++ unsigned int regval;
++ void __iomem *crg_base;
+
-+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3559v200-clock");
-+ if (!np) {
-+ pr_err("failed to find hisilicon clock node\n");
-+ return;
-+ }
++ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3559v200-clock");
++ if (!np) {
++ pr_err("failed to find hisilicon clock node\n");
++ return;
++ }
+
-+ crg_base = of_iomap(np, 0);
-+ if (!crg_base) {
-+ pr_err("failed to map address\n");
-+ return;
-+ }
++ crg_base = of_iomap(np, 0);
++ if (!crg_base) {
++ pr_err("failed to map address\n");
++ return;
++ }
+
-+ if (enable) {
-+ /* clear the slave cpu reset */
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval &= ~CPU1_SRST_REQ;
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ } else {
-+ regval = readl(crg_base + REG_CPU_SRST_CRG);
-+ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
-+ writel(regval, (crg_base + REG_CPU_SRST_CRG));
-+ }
++ if (enable) {
++ /* clear the slave cpu reset */
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval &= ~CPU1_SRST_REQ;
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ } else {
++ regval = readl(crg_base + REG_CPU_SRST_CRG);
++ regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ);
++ writel(regval, (crg_base + REG_CPU_SRST_CRG));
++ }
++ iounmap(crg_base);
+}
+
+static const struct smp_operations hi35xx_smp_ops __initconst = {
-+ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
-+ .smp_boot_secondary = hi35xx_boot_secondary,
++ .smp_prepare_cpus = hi35xx_smp_prepare_cpus,
++ .smp_boot_secondary = hi35xx_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(hi3559v200_smp, "hisilicon,hi3559v200", &hi35xx_smp_ops);
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/mach-hibvt/platsmp.c b/arch/arm/mach-hibvt/platsmp.c
new file mode 100644
-index 0000000..a1c63e8
+index 0000000..a73be20
--- /dev/null
+++ b/arch/arm/mach-hibvt/platsmp.c
@@ -0,0 +1,62 @@
@@ -147240,46 +181775,46 @@ index 0000000..a1c63e8
+
+void __init hi35xx_smp_prepare_cpus(unsigned int max_cpus)
+{
-+ unsigned long base = 0;
-+ void __iomem *scu_base = NULL;
++ unsigned long base = 0;
++ void __iomem *scu_base = NULL;
+
-+ if (scu_a9_has_base()) {
-+ base = scu_a9_get_base();
-+ scu_base = ioremap(base, PAGE_SIZE);
-+ if (!scu_base) {
-+ pr_err("ioremap(scu_base) failed\n");
-+ return;
-+ }
++ if (scu_a9_has_base()) {
++ base = scu_a9_get_base();
++ scu_base = ioremap(base, PAGE_SIZE);
++ if (!scu_base) {
++ pr_err("ioremap(scu_base) failed\n");
++ return;
++ }
+
-+ scu_enable(scu_base);
-+ iounmap(scu_base);
-+ }
++ scu_enable(scu_base);
++ iounmap(scu_base);
++ }
+}
+
+void hi35xx_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
+{
-+ void __iomem *virt;
++ void __iomem *virt;
+
-+ virt = ioremap(start_addr, PAGE_SIZE);
-+ if (!virt) {
-+ pr_err("ioremap(start_addr) failed\n");
-+ return;
-+ }
++ virt = ioremap(start_addr, PAGE_SIZE);
++ if (!virt) {
++ pr_err("ioremap(start_addr) failed\n");
++ return;
++ }
+
-+ writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
-+ writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
-+ iounmap(virt);
++ writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
++ writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
++ iounmap(virt);
+}
+
+int hi35xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
-+ phys_addr_t jumpaddr;
++ phys_addr_t jumpaddr;
+
-+ jumpaddr = virt_to_phys(secondary_startup);
-+ hi35xx_set_scu_boot_addr(HI35XX_BOOT_ADDRESS, jumpaddr);
-+ hi35xx_set_cpu(cpu, true);
-+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
-+ return 0;
++ jumpaddr = virt_to_phys(secondary_startup);
++ hi35xx_set_scu_boot_addr(HI35XX_BOOT_ADDRESS, jumpaddr);
++ hi35xx_set_cpu(cpu, true);
++ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
++ return 0;
+}
+
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
@@ -147359,7 +181894,7 @@ index 0000000..d7c2d12
+
diff --git a/arch/arm/plat-hi3519av100/pll-trainning.c b/arch/arm/plat-hi3519av100/pll-trainning.c
new file mode 100644
-index 0000000..bab7ef2
+index 0000000..2d666ac
--- /dev/null
+++ b/arch/arm/plat-hi3519av100/pll-trainning.c
@@ -0,0 +1,1196 @@
@@ -147622,7 +182157,7 @@ index 0000000..bab7ef2
+static void save_pmx_ctrl(struct pinmux_control *pmx_ctrl)
+{
+ int i;
-+ struct pin_info *pin;
++ struct pin_info *pin = NULL;
+ for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
+ pin = &pmx_ctrl->pins[i];
+ save_one_pin(pin);
@@ -147632,7 +182167,7 @@ index 0000000..bab7ef2
+static void ptdev_pinmux_save(void)
+{
+ unsigned pmx_ctrl_nr = ARRAY_SIZE(pmx_ctrl_list);
-+ struct pinmux_control *pmx_ctrl;
++ struct pinmux_control *pmx_ctrl = NULL;
+ int i;
+
+ for (i = 0; i < pmx_ctrl_nr; i++) {
@@ -147657,7 +182192,7 @@ index 0000000..bab7ef2
+static void restore_pmx_ctrl(struct pinmux_control *pmx_ctrl)
+{
+ int i;
-+ struct pin_info *pin;
++ struct pin_info *pin = NULL;
+ for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
+ pin = &pmx_ctrl->pins[i];
+ restore_one_pin(pin);
@@ -147667,7 +182202,7 @@ index 0000000..bab7ef2
+static void ptdev_pinmux_restore(void)
+{
+ unsigned pmx_ctrl_nr = ARRAY_SIZE(pmx_ctrl_list);
-+ struct pinmux_control *pmx_ctrl;
++ struct pinmux_control *pmx_ctrl = NULL;
+ int i;
+
+ for (i = 0; i < pmx_ctrl_nr; i++) {
@@ -147791,7 +182326,7 @@ index 0000000..bab7ef2
+}
+
+static void uart_rx_dma_init(struct pll_trainning_dev *dev,
-+ unsigned int req_line)
++ unsigned int req_line)
+{
+ edma_apb_axi_clock_enable();
+ if (dev->dev_clock_enable) {
@@ -147852,7 +182387,7 @@ index 0000000..bab7ef2
+ * on -2, data err;
+ */
+static int do_uart_dma_rx_tst(struct pll_trainning_dev *dev,
-+ unsigned int req_line, int revert)
++ unsigned int req_line, int revert)
+{
+ unsigned int left = req_line % 2;
+ unsigned int result = req_line / 2;
@@ -147870,13 +182405,13 @@ index 0000000..bab7ef2
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->tx_dma_reqline_val << shift)
-+ | (dev->rx_dma_reqline_val << (shift + 8)));
++ | (dev->rx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ } else {
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->rx_dma_reqline_val << shift)
-+ | (dev->tx_dma_reqline_val << (shift + 8)));
++ | (dev->tx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ }
+
@@ -147951,7 +182486,7 @@ index 0000000..bab7ef2
+ if (ret) {
+ pass = 0;
+ pr_debug(" Dev[%s/%d]tx trainning failed!\n",
-+ pt_dev->name, i);
++ pt_dev->name, i);
+ break;
+ }
+ }
@@ -147960,7 +182495,7 @@ index 0000000..bab7ef2
+ if (ret) {
+ pass = 0;
+ pr_debug(" Dev[%s/%d]rx trainning failed!\n",
-+ pt_dev->name, i);
++ pt_dev->name, i);
+ break;
+ }
+ }
@@ -148043,13 +182578,13 @@ index 0000000..bab7ef2
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->tx_dma_reqline_val << shift)
-+ | (dev->rx_dma_reqline_val << (shift + 8)));
++ | (dev->rx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ } else {
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->rx_dma_reqline_val << shift)
-+ | (dev->tx_dma_reqline_val << (shift + 8)));
++ | (dev->tx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ }
+ for (i = 0; i < 1; i++) {
@@ -148323,24 +182858,24 @@ index 0000000..bab7ef2
+ }
+
+ if ((regulator->curr > 37) &&
-+ ((regulator->curr - 37) <= regulator->min)) {
++ ((regulator->curr - 37) <= regulator->min)) {
+ regulator->steps[4] = 0xffffffff;
+ regulator->steps[3] = regulator->min;
+ goto out1;
+ }
+ if ((regulator->curr > 74) &&
-+ ((regulator->curr - 74) <= regulator->min)) {
++ ((regulator->curr - 74) <= regulator->min)) {
+ regulator->steps[4] = regulator->min;
+ }
+
+out1:
+ regulator->max = ((regulator->curr + 74) < regulator->max)
-+ ? (regulator->curr + 74) : regulator->max;
++ ? (regulator->curr + 74) : regulator->max;
+ regulator->min = ((regulator->curr - 74) > regulator->min)
-+ ? (regulator->curr - 74) : regulator->min;
++ ? (regulator->curr - 74) : regulator->min;
+
+ pr_debug("svb voltage min/max[0x%x/0x%x] steps: ",
-+ regulator->min, regulator->max);
++ regulator->min, regulator->max);
+ for (i = 0; i < 5; i++) {
+ pr_debug(" 0x%x ", regulator->steps[i]);
+ }
@@ -148446,7 +182981,7 @@ index 0000000..bab7ef2
+
+ do {
+ pr_debug("### SSP pll reset count %d\n",
-+ (PLL_TEST_NR - pll_reset_counts));
++ (PLL_TEST_NR - pll_reset_counts));
+
+ for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
+ for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) && (trainning_pass == 1); i++) {
@@ -148488,7 +183023,7 @@ index 0000000..bab7ef2
+ pll_reset_counts = PLL_TEST_NR - 1;
+ do {
+ pr_debug("### UART pll reset count %d\n",
-+ (PLL_TEST_NR - pll_reset_counts));
++ (PLL_TEST_NR - pll_reset_counts));
+
+ for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
+ for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) && (trainning_pass == 1); i++) {
@@ -148574,7 +183109,7 @@ index 0000000..8c659c8
+
diff --git a/arch/arm/plat-hi3556av100/pll-trainning.c b/arch/arm/plat-hi3556av100/pll-trainning.c
new file mode 100644
-index 0000000..37bb66a
+index 0000000..aca388b
--- /dev/null
+++ b/arch/arm/plat-hi3556av100/pll-trainning.c
@@ -0,0 +1,1188 @@
@@ -148837,7 +183372,7 @@ index 0000000..37bb66a
+static void save_pmx_ctrl(struct pinmux_control *pmx_ctrl)
+{
+ int i;
-+ struct pin_info *pin;
++ struct pin_info *pin = NULL;
+ for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
+ pin = &pmx_ctrl->pins[i];
+ save_one_pin(pin);
@@ -148847,7 +183382,7 @@ index 0000000..37bb66a
+static void ptdev_pinmux_save(void)
+{
+ unsigned pmx_ctrl_nr = ARRAY_SIZE(pmx_ctrl_list);
-+ struct pinmux_control *pmx_ctrl;
++ struct pinmux_control *pmx_ctrl = NULL;
+ int i;
+
+ for (i = 0; i < pmx_ctrl_nr; i++) {
@@ -148872,7 +183407,7 @@ index 0000000..37bb66a
+static void restore_pmx_ctrl(struct pinmux_control *pmx_ctrl)
+{
+ int i;
-+ struct pin_info *pin;
++ struct pin_info *pin = NULL;
+ for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
+ pin = &pmx_ctrl->pins[i];
+ restore_one_pin(pin);
@@ -148882,7 +183417,7 @@ index 0000000..37bb66a
+static void ptdev_pinmux_restore(void)
+{
+ unsigned pmx_ctrl_nr = ARRAY_SIZE(pmx_ctrl_list);
-+ struct pinmux_control *pmx_ctrl;
++ struct pinmux_control *pmx_ctrl = NULL;
+ int i;
+
+ for (i = 0; i < pmx_ctrl_nr; i++) {
@@ -149006,7 +183541,7 @@ index 0000000..37bb66a
+}
+
+static void uart_rx_dma_init(struct pll_trainning_dev *dev,
-+ unsigned int req_line)
++ unsigned int req_line)
+{
+ edma_apb_axi_clock_enable();
+ if (dev->dev_clock_enable) {
@@ -149067,7 +183602,7 @@ index 0000000..37bb66a
+ * on -2, data err;
+ */
+static int do_uart_dma_rx_tst(struct pll_trainning_dev *dev,
-+ unsigned int req_line, int revert)
++ unsigned int req_line, int revert)
+{
+ unsigned int left = req_line % 2;
+ unsigned int result = req_line / 2;
@@ -149085,13 +183620,13 @@ index 0000000..37bb66a
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->tx_dma_reqline_val << shift)
-+ | (dev->rx_dma_reqline_val << (shift + 8)));
++ | (dev->rx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ } else {
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->rx_dma_reqline_val << shift)
-+ | (dev->tx_dma_reqline_val << (shift + 8)));
++ | (dev->tx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ }
+
@@ -149166,7 +183701,7 @@ index 0000000..37bb66a
+ if (ret) {
+ pass = 0;
+ pr_debug(" Dev[%s/%d]tx trainning failed!\n",
-+ pt_dev->name, i);
++ pt_dev->name, i);
+ break;
+ }
+ }
@@ -149175,7 +183710,7 @@ index 0000000..37bb66a
+ if (ret) {
+ pass = 0;
+ pr_debug(" Dev[%s/%d]rx trainning failed!\n",
-+ pt_dev->name, i);
++ pt_dev->name, i);
+ break;
+ }
+ }
@@ -149258,13 +183793,13 @@ index 0000000..37bb66a
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->tx_dma_reqline_val << shift)
-+ | (dev->rx_dma_reqline_val << (shift + 8)));
++ | (dev->rx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ } else {
+ shift = left * 16;
+ val &= ~(0xffff << shift);
+ val |= ((dev->rx_dma_reqline_val << shift)
-+ | (dev->tx_dma_reqline_val << (shift + 8)));
++ | (dev->tx_dma_reqline_val << (shift + 8)));
+ writel(val, addr + MISC_CTRL73 + result * 4);
+ }
+ for (i = 0; i < 1; i++) {
@@ -149542,12 +184077,12 @@ index 0000000..37bb66a
+ }
+
+ regulator->max = ((regulator->curr + 37) < regulator->max)
-+ ? (regulator->curr + 37) : regulator->max;
++ ? (regulator->curr + 37) : regulator->max;
+ regulator->min = ((regulator->curr - 111) > regulator->min)
-+ ? (regulator->curr - 111) : regulator->min;
++ ? (regulator->curr - 111) : regulator->min;
+
+ pr_warn("svb voltage min/max[0x%x/0x%x] steps: ",
-+ regulator->min, regulator->max);
++ regulator->min, regulator->max);
+ for (i = 0; i < 5; i++) {
+ pr_warn(" 0x%x ", regulator->steps[i]);
+ }
@@ -149653,7 +184188,7 @@ index 0000000..37bb66a
+
+ do {
+ pr_debug("### SSP pll reset count %d\n",
-+ (PLL_TEST_NR - pll_reset_counts));
++ (PLL_TEST_NR - pll_reset_counts));
+
+ for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
+ for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) && (trainning_pass == 1); i++) {
@@ -149695,7 +184230,7 @@ index 0000000..37bb66a
+ pll_reset_counts = PLL_TEST_NR - 1;
+ do {
+ pr_debug("### UART pll reset count %d\n",
-+ (PLL_TEST_NR - pll_reset_counts));
++ (PLL_TEST_NR - pll_reset_counts));
+
+ for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
+ for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) && (trainning_pass == 1); i++) {
@@ -149884,10 +184419,10 @@ index cf57a77..57012e0 100644
+
source "lib/Kconfig"
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
-index 101794f..6eeaa85 100644
+index 101794f..7af71ef 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
-@@ -81,6 +81,35 @@ config ARCH_HISI
+@@ -81,6 +81,44 @@ config ARCH_HISI
help
This enables support for Hisilicon ARMv8 SoC family
@@ -149908,17 +184443,26 @@ index 101794f..6eeaa85 100644
+ help
+ Support for Hisilicon Hi3559AV100 Soc family
+
++config ARCH_HI3569V100
++ bool "Hisilicon hi3569v100 family"
++ depends on ARCH_HISI_BVT
++ select ARM_TIMER_SP804
++ select HISILICON_IRQ_MBIGEN if PCI
++ select PINCTRL
++ help
++ Support for Hisilicon Hi3569V100 Soc family
++
+config ACCESS_M7_DEV
+ bool "Enable to access the devices of m7"
-+ depends on ARCH_HI3559AV100
++ depends on (ARCH_HI3559AV100 || ARCH_HI3569V100)
+ help
+ supprot to access the devices of M7
+
+config ARCH_HISI_BVT_AMP
+ bool "Hisilicon AMP solution"
-+ depends on ARCH_HI3559AV100
++ depends on (ARCH_HI3559AV100 || ARCH_HI3569V100)
+ help
-+ Support for Hisilicon Hi3559AV100 AMP
++ Support for Hisilicon Hi3559AV100 and Hi3569v100 AMP
+
config ARCH_MEDIATEK
bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
@@ -150076,16 +184620,19 @@ index 6684f97..b31e443 100644
+
+clean-files := dts/*.dtb *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
-index d5f43a0..b632070 100644
+index d5f43a0..3798647 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
-@@ -1,6 +1,9 @@
+@@ -1,6 +1,12 @@
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
+dtb-$(CONFIG_ARCH_HI3559AV100) += hi3559av100-demb-flash.dtb
+dtb-$(CONFIG_ARCH_HI3559AV100) += hi3559av100-demb-emmc.dtb
+dtb-$(CONFIG_ARCH_HI3559AV100) += hi3559av100-demb-ufs.dtb
++dtb-$(CONFIG_ARCH_HI3569V100) += hi3569v100-demb-flash.dtb
++dtb-$(CONFIG_ARCH_HI3569V100) += hi3569v100-demb-emmc.dtb
++dtb-$(CONFIG_ARCH_HI3569V100) += hi3569v100-demb-ufs.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
@@ -151468,10 +186015,10 @@ index 0000000..3b906be
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3559av100.dtsi b/arch/arm64/boot/dts/hisilicon/hi3559av100.dtsi
new file mode 100644
-index 0000000..5059ea6
+index 0000000..ca89e92
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3559av100.dtsi
-@@ -0,0 +1,1349 @@
+@@ -0,0 +1,1363 @@
+/* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
@@ -152229,6 +186776,10 @@ index 0000000..5059ea6
+ <0x12060000 0x10000>, <0X12030000 0x10000>;
+ reg-names = "crg", "sys", "ddr", "misc";
+ };
++
++ osal: osal {
++ compatible = "hisilicon,osal";
++ };
+
+ sysctrl: system-controller@00000000 {
+ compatible = "hisilicon,sysctrl";
@@ -152362,13 +186913,13 @@ index 0000000..5059ea6
+ /*USB DTS nodes*/
+ usb3_phy_0: phy3_0 {
+ compatible = "hisilicon,hisi-usb3-phy_0";
-+ reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12020000 0x10000>, <0x12300000 0x10000>;
++ reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12300000 0x10000>, <0x12020000 0x10000>;
+ phyid = <0>;
+ };
+
+ usb3_phy_1: phy3_1 {
+ compatible = "hisilicon,hisi-usb3-phy_1";
-+ reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12020000 0x10000>, <0x12310000 0x10000>;
++ reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12310000 0x10000>, <0x12020000 0x10000>;
+ phyid = <1>;
+ };
+
@@ -152377,6 +186928,7 @@ index 0000000..5059ea6
+ compatible = "generic-xhci";
+ reg = <0x12300000 0x10000>;
+ interrupts = <0 84 4>;
++ usb2-lpm-disable;
+ };
+#endif
+#ifdef CONFIG_USB_DRD1_IN_HOST
@@ -152384,6 +186936,7 @@ index 0000000..5059ea6
+ compatible = "generic-xhci";
+ reg = <0x12310000 0x10000>;
+ interrupts = <0 85 4>;
++ usb2-lpm-disable;
+ };
+#endif
+#ifdef CONFIG_USB_DRD0_IN_DEVICE
@@ -152395,6 +186948,8 @@ index 0000000..5059ea6
+ interrupt-names = "peripheral";
+ maximum-speed = "super-speed";
+ dr_mode = "peripheral";
++ snps,dis_initiate_u1;
++ snps,dis_initiate_u2;
+ };
+#endif
+#ifdef CONFIG_USB_DRD1_IN_DEVICE
@@ -152406,6 +186961,8 @@ index 0000000..5059ea6
+ interrupt-names = "peripheral";
+ maximum-speed = "super-speed";
+ dr_mode = "peripheral";
++ snps,dis_initiate_u1;
++ snps,dis_initiate_u2;
+ };
+#endif
+ /*EMMC/SD/SDIO DTS nodes*/
@@ -152655,13 +187212,17 @@ index 0000000..5059ea6
+ interrupt-names = "timer";
+ };
+
-+ venc: venc@0x11300000 {
++ vedu: vedu@0x11300000 {
+ compatible = "hisilicon,hisi-vedu";
+ reg = <0x11300000 0x10000>, <0x11310000 0x10000>,<0x11400000 0x10000>,<0x11320000 0x10000>;
+ reg-names = "vedu0", "vedu1","vedu2","jpge";
+ interrupts = <0 39 4>, <0 40 4>,<0 41 4>,<0 49 4>;
+ interrupt-names = "vedu0", "vedu1","vedu2","jpge";
+ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
+
+ vdh: vdh@0x11e10000 {
+ compatible = "hisilicon,hisi-vdh";
@@ -152821,6 +187382,2747 @@ index 0000000..5059ea6
+
+ };
+};
+diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-amp.dts b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-amp.dts
+new file mode 100644
+index 0000000..bbcd6a9
+--- /dev/null
++++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-amp.dts
+@@ -0,0 +1,596 @@
++/* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++/dts-v1/;
++/* reserved for warmreset */
++/* reserved for arm trustedfirmware */
++/* Modify this configuration according to the system framework */
++/memreserve/ 0x53000000 0x00200000;
++#include "hi3569v100.dtsi"
++
++/ {
++ model = "Hisilicon HI3569V100 DEMO Board";
++ compatible = "hisilicon,hi3569v100";
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
++ serial4 = &uart4;
++ serial5 = &uart5;
++ serial6 = &uart6;
++ serial7 = &uart7;
++ serial8 = &uart8;
++ serial9 = &uart9;
++
++ i2c0 = &i2c_bus0;
++ i2c1 = &i2c_bus1;
++ i2c2 = &i2c_bus2;
++ i2c3 = &i2c_bus3;
++ i2c4 = &i2c_bus4;
++ i2c5 = &i2c_bus5;
++ i2c6 = &i2c_bus6;
++ i2c7 = &i2c_bus7;
++ i2c8 = &i2c_bus8;
++ i2c9 = &i2c_bus9;
++ i2c10 = &i2c_bus10;
++ i2c11 = &i2c_bus11;
++ i2c12 = &i2c_bus12;
++ i2c13 = &i2c_bus13;
++ i2c14 = &i2c_bus14;
++ i2c15 = &i2c_bus15;
++ i2c16 = &i2c_bus16;
++ i2c17 = &i2c_bus17;
++ i2c18 = &i2c_bus18;
++ i2c19 = &i2c_bus19;
++
++ spi0 = &spi_bus0;
++ spi1 = &spi_bus1;
++ spi2 = &spi_bus2;
++ spi3 = &spi_bus3;
++ spi4 = &spi_bus4;
++ spi5 = &spi_bus5;
++ spi6 = &spi_bus6;
++ spi7 = &spi_bus7;
++
++ gpio0 = &gpio_chip0;
++ gpio1 = &gpio_chip1;
++ gpio2 = &gpio_chip2;
++ gpio3 = &gpio_chip3;
++ gpio4 = &gpio_chip4;
++ gpio5 = &gpio_chip5;
++ gpio6 = &gpio_chip6;
++ gpio7 = &gpio_chip7;
++ gpio8 = &gpio_chip8;
++ gpio9 = &gpio_chip9;
++ gpio10 = &gpio_chip10;
++ gpio11 = &gpio_chip11;
++ gpio12 = &gpio_chip12;
++ gpio13 = &gpio_chip13;
++ gpio14 = &gpio_chip14;
++ gpio15 = &gpio_chip15;
++ gpio16 = &gpio_chip16;
++ gpio17 = &gpio_chip17;
++ gpio18 = &gpio_chip18;
++ };
++
++ chosen {
++ bootargs = "mem=512M console=ttyAMA0,115200 clk_ignore_unused root=/dev/mtdblock2 rootfstype=yaffs2 rw mtdparts=hinand:1M(boot),9M(kernel),32M(rootfs),1M(this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!)";
++
++ linux,initrd-start = <0x60000040>;
++ linux,initrd-end = <0x61000000>;
++ };
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ compatible = "arm,cortex-a53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ enable-method = "psci";
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ };
++
++ cpu@1 {
++ compatible = "arm,cortex-a53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ enable-method = "psci";
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ };
++ cpu@2 {
++ compatible = "arm,cortex-a73";
++ device_type = "cpu";
++ reg = <0x0 0x100>;
++ enable-method = "psci";
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ };
++ cpu@3 {
++ compatible = "arm,cortex-a73";
++ device_type = "cpu";
++ reg = <0x0 0x101>;
++ enable-method = "psci";
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ };
++
++ };
++
++ memory {
++ device_type = "memory";
++ reg = <0x0 0x50000000 0x2 0x0>; /* system memory base */
++ };
++};
++
++&ipcm {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart1 {
++ status = "disabled";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&uart3 {
++ status = "okay";
++};
++
++&uart4 {
++ status = "okay";
++};
++
++&uart5 {
++ status = "disabled";
++};
++
++&uart6 {
++ status = "disabled";
++};
++
++&uart7 {
++ status = "disabled";
++};
++
++&uart8 {
++ status = "disabled";
++};
++
++&uart9 {
++ status = "disabled";
++};
++
++&i2c_bus0 {
++ status = "disabled";
++};
++
++&i2c_bus1 {
++ status = "disabled";
++};
++
++&i2c_bus2 {
++ status = "disabled";
++};
++
++&i2c_bus3 {
++ status = "disabled";
++};
++
++&i2c_bus4 {
++ status = "disabled";
++};
++
++&i2c_bus5 {
++ status = "disabled";
++};
++
++&i2c_bus6 {
++ status = "disabled";
++};
++
++&i2c_bus7 {
++ status = "disabled";
++};
++
++&i2c_bus8 {
++ status = "okay";
++};
++
++&i2c_bus9 {
++ status = "okay";
++};
++
++&i2c_bus10 {
++ status = "okay";
++};
++
++&i2c_bus11 {
++ status = "disabled";
++};
++
++&i2c_bus12 {
++ status = "disabled";
++};
++
++&i2c_bus13 {
++ status = "disabled";
++};
++
++&i2c_bus14 {
++ status = "disabled";
++};
++
++&i2c_bus15 {
++ status = "disabled";
++};
++
++&i2c_bus16 {
++ status = "disabled";
++};
++
++&i2c_bus17 {
++ status = "disabled";
++};
++
++&i2c_bus18 {
++ status = "disabled";
++};
++
++&i2c_bus19 {
++ status = "disabled";
++};
++
++&spi_bus0{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus1{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus2{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus3{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus4{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@2 {
++ compatible = "rohm,dh2228fv";
++ reg = <2>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@3 {
++ compatible = "rohm,dh2228fv";
++ reg = <3>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus5{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++ spidev@2 {
++ compatible = "rohm,dh2228fv";
++ reg = <2>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++};
++
++&spi_bus6{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++ spidev@2 {
++ compatible = "rohm,dh2228fv";
++ reg = <2>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++};
++
++&spi_bus7{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++};
++
++&gpio_chip0 {
++ status = "okay";
++};
++
++&gpio_chip1 {
++ status = "okay";
++};
++
++&gpio_chip2 {
++ status = "okay";
++};
++
++&gpio_chip3 {
++ status = "okay";
++};
++
++&gpio_chip4 {
++ status = "okay";
++};
++
++&gpio_chip5 {
++ status = "okay";
++};
++
++&gpio_chip6 {
++ status = "okay";
++};
++
++&gpio_chip7 {
++ status = "okay";
++};
++
++&gpio_chip8 {
++ status = "okay";
++};
++
++&gpio_chip9 {
++ status = "okay";
++};
++
++&gpio_chip10 {
++ status = "okay";
++};
++
++&gpio_chip11 {
++ status = "okay";
++};
++
++&gpio_chip12 {
++ status = "okay";
++};
++
++&gpio_chip13 {
++ status = "okay";
++};
++
++&gpio_chip14 {
++ status = "okay";
++};
++
++&gpio_chip15 {
++ status = "okay";
++};
++
++&gpio_chip16 {
++ status = "okay";
++};
++
++&gpio_chip17 {
++ status = "okay";
++};
++
++&gpio_chip18 {
++ status = "okay";
++};
++
++&rtc{
++ status = "okay";
++};
++
++&hisfc {
++ hi_sfc {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ m25p,fast-read;
++ };
++};
++
++&hisnfc {
++ hinand {
++ compatible = "jedec,spi-nand";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ };
++};
++
++&hinfc {
++ hinand {
++ compatible = "jedec,nand";
++ reg = <0>;
++ nand-max-frequency = <200000000>;
++ };
++};
++
++&mdio {
++ ethphy: ethernet-phy@1 {
++ reg = <1>;
++ };
++};
++
++#if 0
++&mdio1 {
++ ethphy1: ethernet-phy@3 {
++ reg = <3>;
++ };
++};
++#endif
++
++&higmac {
++ phy-handle = <ðphy>;
++ phy-mode = "rgmii";
++};
++
++#if 0
++&higmac1 {
++ phy-handle = <ðphy1>;
++ phy-mode = "rgmii";
++};
++#endif
++
++&mmc1 {
++ status = "okay";
++};
++
++&mmc2 {
++ status = "okay";
++};
++
++&mmc3 {
++ status = "disabled";
++};
++
++&hivdmac {
++ status = "disabled";
++};
++
++&hiedmacv310_1 {
++ status = "disabled";
++};
+diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-emmc.dts b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-emmc.dts
+new file mode 100644
+index 0000000..404342e
+--- /dev/null
++++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-emmc.dts
+@@ -0,0 +1,32 @@
++/* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++#include <../../../../../include/generated/autoconf.h>
++
++#ifdef CONFIG_ARCH_HISI_BVT_AMP
++#include "hi3569v100-demb-amp.dts"
++#else
++#include "hi3569v100-demb.dts"
++#endif
++
++&mmc0 {
++ status = "okay";
++};
++
++&ufs {
++ status = "disabled";
++};
++
+diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-flash.dts b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-flash.dts
+new file mode 100644
+index 0000000..e554fab
+--- /dev/null
++++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-flash.dts
+@@ -0,0 +1,32 @@
++/* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++#include <../../../../../include/generated/autoconf.h>
++
++#ifdef CONFIG_ARCH_HISI_BVT_AMP
++#include "hi3569v100-demb-amp.dts"
++#else
++#include "hi3569v100-demb.dts"
++#endif
++
++&mmc0 {
++ status = "disabled";
++};
++
++&ufs {
++ status = "disabled";
++};
++
+diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-ufs.dts b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-ufs.dts
+new file mode 100644
+index 0000000..b56098b
+--- /dev/null
++++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-ufs.dts
+@@ -0,0 +1,32 @@
++/* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++#include <../../../../../include/generated/autoconf.h>
++
++#ifdef CONFIG_ARCH_HISI_BVT_AMP
++#include "hi3569v100-demb-amp.dts"
++#else
++#include "hi3569v100-demb.dts"
++#endif
++
++&mmc0 {
++ status = "disabled";
++};
++
++&ufs {
++ status = "okay";
++};
++
+diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb.dts b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb.dts
+new file mode 100644
+index 0000000..7cb8b38
+--- /dev/null
++++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb.dts
+@@ -0,0 +1,655 @@
++/* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++/dts-v1/;
++/* reserved for warmreset */
++/* reserved for arm trustedfirmware */
++/* Modify this configuration according to the system framework */
++/memreserve/ 0x47000000 0x00200000;
++#include "hi3569v100.dtsi"
++
++/ {
++ model = "Hisilicon HI3569V100 DEMO Board";
++ compatible = "hisilicon,hi3569v100";
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
++ serial4 = &uart4;
++ serial5 = &uart5;
++ serial6 = &uart6;
++ serial7 = &uart7;
++ serial8 = &uart8;
++ serial9 = &uart9;
++
++ i2c0 = &i2c_bus0;
++ i2c1 = &i2c_bus1;
++ i2c2 = &i2c_bus2;
++ i2c3 = &i2c_bus3;
++ i2c4 = &i2c_bus4;
++ i2c5 = &i2c_bus5;
++ i2c6 = &i2c_bus6;
++ i2c7 = &i2c_bus7;
++ i2c8 = &i2c_bus8;
++ i2c9 = &i2c_bus9;
++ i2c10 = &i2c_bus10;
++ i2c11 = &i2c_bus11;
++ i2c12 = &i2c_bus12;
++ i2c13 = &i2c_bus13;
++ i2c14 = &i2c_bus14;
++ i2c15 = &i2c_bus15;
++ i2c16 = &i2c_bus16;
++ i2c17 = &i2c_bus17;
++ i2c18 = &i2c_bus18;
++ i2c19 = &i2c_bus19;
++
++ spi0 = &spi_bus0;
++ spi1 = &spi_bus1;
++ spi2 = &spi_bus2;
++ spi3 = &spi_bus3;
++ spi4 = &spi_bus4;
++ spi5 = &spi_bus5;
++ spi6 = &spi_bus6;
++ spi7 = &spi_bus7;
++
++ gpio0 = &gpio_chip0;
++ gpio1 = &gpio_chip1;
++ gpio2 = &gpio_chip2;
++ gpio3 = &gpio_chip3;
++ gpio4 = &gpio_chip4;
++ gpio5 = &gpio_chip5;
++ gpio6 = &gpio_chip6;
++ gpio7 = &gpio_chip7;
++ gpio8 = &gpio_chip8;
++ gpio9 = &gpio_chip9;
++ gpio10 = &gpio_chip10;
++ gpio11 = &gpio_chip11;
++ gpio12 = &gpio_chip12;
++ gpio13 = &gpio_chip13;
++ gpio14 = &gpio_chip14;
++ gpio15 = &gpio_chip15;
++ gpio16 = &gpio_chip16;
++ gpio17 = &gpio_chip17;
++ gpio18 = &gpio_chip18;
++ };
++
++ chosen {
++ bootargs = "mem=512M console=ttyAMA0,115200 clk_ignore_unused root=/dev/mtdblock2 rootfstype=yaffs2 rw mtdparts=hinand:1M(boot),9M(kernel),32M(rootfs),1M(this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!)";
++
++ linux,initrd-start = <0x60000040>;
++ linux,initrd-end = <0x61000000>;
++ };
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ compatible = "arm,cortex-a53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ enable-method = "psci";
++ clock-latency = <100000>; /* From legacy driver */
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ };
++
++ cpu@1 {
++ compatible = "arm,cortex-a53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ enable-method = "psci";
++ clock-latency = <200000>; /* From legacy driver */
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ };
++ cpu@2 {
++ compatible = "arm,cortex-a73";
++ device_type = "cpu";
++ reg = <0x0 0x100>;
++ enable-method = "psci";
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ vcc-supply = <&a73_regulator>;
++ };
++ cpu@3 {
++ compatible = "arm,cortex-a73";
++ device_type = "cpu";
++ reg = <0x0 0x101>;
++ enable-method = "psci";
++ operating-points = <
++ 792000 796000
++ 1296000 888000
++ 1608000 988000
++ >;
++ clocks = <&clock HI3559AV100_A73_MUX>,
++ <&clock HI3559AV100_FIXED_24M>,
++ <&clock HI3559AV100_APLL_CLK>,
++ <&clock HI3559AV100_FIXED_1000M>;
++ clock-names = "a73_mux","24m","apll","1000m";
++ clock-latency = <400000>; /* From legacy driver */
++ cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
++ vcc-supply = <&a73_regulator>;
++ };
++
++ };
++
++ avs {
++ compatible = "hi3559a,avs";
++ avs-num = <3>;
++ avs-name-array = "cpu-avs","media-avs","gpu-avs";
++ cpu_avs: cpu_avs{
++ avs-name = "cpu-avs";
++ opp-num = <6>;
++ opp-freq = <1250000 1150000 1000000 930000 792000 594000 >;
++ opp-volt-min = <870000 870000 800000 800000 740000 740000>;
++ opp-hpm = <310 310 280 280 250 250>;
++ opp-div = <24 22 19 18 15 11>;
++ opp-volt-max = <1060000>;
++ };
++
++ media_avs: media_avs{
++ avs-name = "media-avs";
++ opp-num = <4>;
++ opp-prof-num = <2>;
++ opp-temp-num = <2>;
++ opp-temp = <50 200>;
++ opp-freq = <1 2 3 4>;
++ opp-volt-min = <
++ /* profile2 profile3*/
++ 770000 770000
++ 770000 770000
++ >;
++ opp-hpm = <
++ /* profile2 profile3*/
++ 210 215
++ 190 215
++ >;
++ opp-div = <3 3 3 3>;
++ opp-volt-max = <
++ /* profile2 profile3*/
++ 977000 977000
++ 977000 977000
++ >;
++ };
++
++ gpu_avs: gpu_avs{
++ avs-name = "gpu-avs";
++ };
++
++ };
++ memory {
++ device_type = "memory";
++ reg = <0x0 0x44000000 0x2 0x0>; /* system memory base */
++ };
++};
++
++&ipcm {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart1 {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&uart3 {
++ status = "okay";
++};
++
++&uart4 {
++ status = "okay";
++};
++
++&uart5 {
++ status = "disabled";
++};
++
++&uart6 {
++ status = "disabled";
++};
++
++&uart7 {
++ status = "disabled";
++};
++
++&uart8 {
++ status = "disabled";
++};
++
++&uart9 {
++ status = "disabled";
++};
++
++&i2c_bus0 {
++ status = "okay";
++};
++
++&i2c_bus1 {
++ status = "okay";
++};
++
++&i2c_bus2 {
++ status = "okay";
++};
++
++&i2c_bus3 {
++ status = "okay";
++};
++
++&i2c_bus4 {
++ status = "okay";
++};
++
++&i2c_bus5 {
++ status = "okay";
++};
++
++&i2c_bus6 {
++ status = "okay";
++};
++
++&i2c_bus7 {
++ status = "okay";
++};
++
++&i2c_bus8 {
++ status = "okay";
++};
++
++&i2c_bus9 {
++ status = "okay";
++};
++
++&i2c_bus10 {
++ status = "okay";
++};
++
++&i2c_bus11 {
++ status = "okay";
++};
++
++&i2c_bus12 {
++ status = "disabled";
++};
++
++&i2c_bus13 {
++ status = "disabled";
++};
++
++&i2c_bus14 {
++ status = "disabled";
++};
++
++&i2c_bus15 {
++ status = "disabled";
++};
++
++&i2c_bus16 {
++ status = "disabled";
++};
++
++&i2c_bus17 {
++ status = "disabled";
++};
++
++&i2c_bus18 {
++ status = "disabled";
++};
++
++&i2c_bus19 {
++ status = "disabled";
++};
++
++&spi_bus0{
++ status = "okay";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus1{
++ status = "okay";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus2{
++ status = "okay";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus3{
++ status = "okay";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus4{
++ status = "okay";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@2 {
++ compatible = "rohm,dh2228fv";
++ reg = <2>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++
++ spidev@3 {
++ compatible = "rohm,dh2228fv";
++ reg = <3>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <24750000>;
++ };
++};
++
++&spi_bus5{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++ spidev@2 {
++ compatible = "rohm,dh2228fv";
++ reg = <2>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++};
++
++&spi_bus6{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++
++ spidev@1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++ spidev@2 {
++ compatible = "rohm,dh2228fv";
++ reg = <2>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++};
++
++&spi_bus7{
++ status = "disabled";
++
++ spidev@0 {
++ compatible = "rohm,dh2228fv";
++ reg = <0>;
++ pl022,interface = <0>;
++ pl022,com-mode = <0>;
++ spi-max-frequency = <48000000>;
++ };
++};
++
++&gpio_chip0 {
++ status = "okay";
++};
++
++&gpio_chip1 {
++ status = "okay";
++};
++
++&gpio_chip2 {
++ status = "okay";
++};
++
++&gpio_chip3 {
++ status = "okay";
++};
++
++&gpio_chip4 {
++ status = "okay";
++};
++
++&gpio_chip5 {
++ status = "okay";
++};
++
++&gpio_chip6 {
++ status = "okay";
++};
++
++&gpio_chip7 {
++ status = "okay";
++};
++
++&gpio_chip8 {
++ status = "okay";
++};
++
++&gpio_chip9 {
++ status = "okay";
++};
++
++&gpio_chip10 {
++ status = "okay";
++};
++
++&gpio_chip11 {
++ status = "okay";
++};
++
++&gpio_chip12 {
++ status = "okay";
++};
++
++&gpio_chip13 {
++ status = "okay";
++};
++
++&gpio_chip14 {
++ status = "okay";
++};
++
++&gpio_chip15 {
++ status = "okay";
++};
++
++&gpio_chip16 {
++ status = "okay";
++};
++
++&gpio_chip17 {
++ status = "okay";
++};
++
++&gpio_chip18 {
++ status = "okay";
++};
++
++&rtc{
++ status = "okay";
++};
++
++&hisfc {
++ hi_sfc {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ m25p,fast-read;
++ };
++};
++
++&hisnfc {
++ hinand {
++ compatible = "jedec,spi-nand";
++ reg = <0>;
++ spi-max-frequency = <160000000>;
++ };
++};
++
++&hinfc {
++ hinand {
++ compatible = "jedec,nand";
++ reg = <0>;
++ nand-max-frequency = <200000000>;
++ };
++};
++
++&mdio {
++ ethphy: ethernet-phy@1 {
++ reg = <1>;
++ };
++};
++
++&mdio1 {
++ ethphy1: ethernet-phy@3 {
++ reg = <3>;
++ };
++};
++
++&higmac {
++ phy-handle = <ðphy>;
++ phy-mode = "rgmii";
++};
++
++&higmac1 {
++ phy-handle = <ðphy1>;
++ phy-mode = "rgmii";
++};
++
++&mmc1 {
++ status = "okay";
++};
++
++&mmc2 {
++ status = "okay";
++};
++
++&mmc3 {
++ status = "disabled";
++};
++
++&hivdmac {
++ status = "disabled";
++};
++
++&hiedmacv310_1 {
++ status = "disabled";
++};
++
++&hiedmacv310_2 {
++ status = "disabled";
++};
+diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100.dtsi b/arch/arm64/boot/dts/hisilicon/hi3569v100.dtsi
+new file mode 100644
+index 0000000..f7a98a9
+--- /dev/null
++++ b/arch/arm64/boot/dts/hisilicon/hi3569v100.dtsi
+@@ -0,0 +1,1358 @@
++/* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++/* reserved for arm trustedfirmware */
++#include <dt-bindings/clock/hi3559av100-clock.h>
++#include <../../../../../include/generated/autoconf.h>
++/ {
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ interrupt-parent = <&gic>;
++
++ gic: interrupt-controller@1F100000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ /* gic dist base, gic cpu base */
++ reg = <0x0 0x1F101000 0x0 0x1000>, <0x0 0x1F102000 0x0 0x100>;
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ pmu {
++ compatible = "arm,armv8-pmuv3";
++ interrupts = <0 117 4>,
++ <0 118 4>,
++ <0 127 4>,
++ <0 128 4>;
++ };
++
++ clock: clock0 {
++ compatible = "hisilicon,hi3559av100-clock", "syscon";
++ #clock-cells = <1>;
++ #reset-cells = <2>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x0 0x12010000 0x0 0x10000>;
++ };
++ clock_shub: clock_shub0 {
++ compatible = "hisilicon,hi3559av100-shub-clock";
++ #clock-cells = <1>;
++ #reset-cells = <2>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x0 0x18020000 0x0 0x10000>;
++ };
++
++ idle-states {
++ entry-method = "arm,psci";
++
++ CPU_POWERDOWN: cpu-powerdown {
++ compatible = "arm,idle-state";
++ local-timer-stop;
++ arm,psci-suspend-param = <0x0010000>;
++ entry-latency-us = <20>;
++ exit-latency-us = <40>;
++ min-residency-us = <80>;
++ };
++ CPU_STANDBY: cpu-standby {
++ compatible = "arm,idle-state";
++ arm,psci-suspend-param = <0x0000000>;
++ entry-latency-us = <0x3fffffff>;
++ exit-latency-us = <0x40000000>;
++ min-residency-us = <0xffffffff>;
++ };
++ };
++ ipcm: ipcm@12090000 {
++ compatible = "hisilicon,ipcm-interrupt";
++ interrupt-parent = <&gic>;
++ interrupts = <0 211 4>, <0 212 4>;
++ reg = <0x0 0x12090000 0x0 0x1000>;
++ status = "disabled";
++ };
++ soc {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ device_type = "soc";
++ interrupt-parent = <&gic>;
++ ranges = <0x0 0x00000000 0x0 0xffffffff>;
++
++ clk_3m: clk_3m {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <3000000>;
++ };
++
++ amba {
++ compatible = "arm,amba-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ ranges;
++
++ arm-timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <1 13 0xf04>,
++ <1 14 0xf04>;
++ clock-frequency = <50000000>;
++ };
++
++ timer@12000000 {
++ compatible = "hisilicon,hisp804";
++ reg = <0x12000000 0x20>, /* clocksource */
++ <0x1d840000 0x20>, /* local timer for each cpu */
++ <0x1d840020 0x20>,
++ <0x1d850000 0x20>,
++ <0x1d850020 0x20>;
++ interrupts = <0 113 4>, /* irq of local timer0/1 */
++ <0 114 4>, /* irq of local timer2/3 */
++ <0 115 4>, /* irq of local timer4/5 */
++ <0 116 4>; /* irq of local timer6/7 */
++ clocks = <&clk_3m>;
++ clock-names = "apb_pclk";
++ };
++
++ uart0: uart@12100000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12100000 0x1000>;
++ interrupts = <0 6 4>;
++ clocks = <&clock HI3559AV100_UART0_CLK>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ uart1: uart@12101000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12101000 0x1000>;
++ interrupts = <0 7 4>;
++ clocks = <&clock HI3559AV100_UART1_CLK>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ uart2: uart@12102000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12102000 0x1000>;
++ interrupts = <0 8 4>;
++ clocks = <&clock HI3559AV100_UART2_CLK>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ uart3: uart@12103000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12103000 0x1000>;
++ interrupts = <0 9 4>;
++ clocks = <&clock HI3559AV100_UART3_CLK>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ uart4: uart@12104000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12104000 0x1000>;
++ interrupts = <0 10 4>;
++ clocks = <&clock HI3559AV100_UART4_CLK>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ uart5: uart@18060000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x18060000 0x1000>;
++ interrupts = <0 185 4>;
++ assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
++ assigned-clock-rates = <24000000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_UART0_CLK>;
++ clock-names = "apb_pclk";
++ dmas = <&hiedmacv310_2 11 11>, <&hiedmacv310_2 10 10>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ uart6: uart@18061000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x18061000 0x1000>;
++ interrupts = <0 186 4>;
++ assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
++ assigned-clock-rates = <24000000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_UART1_CLK>;
++ clock-names = "apb_pclk";
++ dmas = <&hiedmacv310_2 13 13>, <&hiedmacv310_2 12 12>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ uart7: uart@18062000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x18062000 0x1000>;
++ interrupts = <0 187 4>;
++ assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
++ assigned-clock-rates = <24000000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_UART2_CLK>;
++ clock-names = "apb_pclk";
++ dmas = <&hiedmacv310_2 15 15>, <&hiedmacv310_2 14 14>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ uart8: uart@18063000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x18063000 0x1000>;
++ interrupts = <0 188 4>;
++ assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
++ assigned-clock-rates = <24000000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_UART3_CLK>;
++ clock-names = "apb_pclk";
++ dmas = <&hiedmacv310_2 7 7>, <&hiedmacv310_2 6 6>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ uart9: uart@18064000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x18064000 0x1000>;
++ interrupts = <0 189 4>;
++ assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
++ assigned-clock-rates = <24000000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_UART4_CLK>;
++ clock-names = "apb_pclk";
++ dmas = <&hiedmacv310_2 17 17>, <&hiedmacv310_2 16 16>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus0: i2c@12110000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12110000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C0_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ dmas = <&hiedmacv310_1 0 10>, <&hiedmacv310_1 1 11>;
++ dma-names = "tx","rx";
++ };
++
++ i2c_bus1: i2c@12111000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12111000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C1_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 2 12>, <&hiedmacv310_1 3 13>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus2: i2c@12112000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12112000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C2_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 4 14>, <&hiedmacv310_1 5 15>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus3: i2c@12113000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12113000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C3_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 6 16>, <&hiedmacv310_1 7 17>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus4: i2c@12114000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12114000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C4_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 8 18>, <&hiedmacv310_1 9 19>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus5: i2c@12115000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12115000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C5_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 10 20>, <&hiedmacv310_1 11 21>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus6: i2c@12116000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12116000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C6_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 12 22>, <&hiedmacv310_1 13 23>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus7: i2c@12117000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12117000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C7_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 14 24>, <&hiedmacv310_1 15 25>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus8: i2c@12118000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12118000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C8_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 16 26>, <&hiedmacv310_1 17 27>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus9: i2c@12119000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x12119000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C9_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 18 28>, <&hiedmacv310_1 19 29>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus10: i2c@1211a000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x1211a000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C10_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 20 30>, <&hiedmacv310_1 21 31>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus11: i2c@1211b000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x1211b000 0x1000>;
++ clocks = <&clock HI3559AV100_I2C11_CLK>;
++ clock-frequency = <100000>;
++ dmas = <&hiedmacv310_1 22 32>, <&hiedmacv310_1 23 33>;
++ dma-names = "tx","rx";
++ status = "disabled";
++ };
++
++ i2c_bus12: i2c@18070000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18070000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C0_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ i2c_bus13: i2c@18071000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18071000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C1_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ i2c_bus14: i2c@18072000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18072000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C2_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ i2c_bus15: i2c@18073000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18073000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C3_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ i2c_bus16: i2c@18074000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18074000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C4_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ i2c_bus17: i2c@18075000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18075000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C5_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ i2c_bus18: i2c@18076000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18076000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C6_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ i2c_bus19: i2c@18077000 {
++ compatible = "hisilicon,hibvt-i2c";
++ reg = <0x18077000 0x1000>;
++ clocks = <&clock_shub HI3559AV100_SHUB_I2C7_CLK>;
++ clock-frequency = <100000>;
++ status = "disabled";
++ };
++
++ spi_bus0: spi@12120000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x12120000 0x1000>, <0x1203004c 0x4>;
++ interrupts = <0 31 4>;
++ clocks = <&clock HI3559AV100_SPI0_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <2>;
++ hisi,spi_cs_sb = <0>;
++ hisi,spi_cs_mask_bit = <1>;
++ };
++
++ spi_bus1: spi@12121000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x12121000 0x1000>, <0x12030050 0x4>;
++ interrupts = <0 32 4>;
++ clocks = <&clock HI3559AV100_SPI1_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <2>;
++ hisi,spi_cs_sb = <0>;
++ hisi,spi_cs_mask_bit = <1>;
++ };
++
++ spi_bus2: spi@12122000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x12122000 0x1000>, <0x12030054 0x4>;
++ interrupts = <0 33 4>;
++ clocks = <&clock HI3559AV100_SPI2_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <2>;
++ hisi,spi_cs_sb = <0>;
++ hisi,spi_cs_mask_bit = <1>;
++ };
++
++ spi_bus3: spi@12123000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x12123000 0x1000>, <0x12030058 0x4>;
++ interrupts = <0 34 4>;
++ clocks = <&clock HI3559AV100_SPI3_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <2>;
++ hisi,spi_cs_sb = <0>;
++ hisi,spi_cs_mask_bit = <1>;
++ };
++
++ spi_bus4: spi@12124000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x12124000 0x1000>, <0x1203005c 0x4>;
++ interrupts = <0 35 4>;
++ clocks = <&clock HI3559AV100_SPI4_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <4>;
++ hisi,spi_cs_sb = <0>;
++ hisi,spi_cs_mask_bit = <0x3>;
++ };
++
++ spi_bus5: spi@18080000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x18080000 0x1000>, <0x18030088 0x4>;
++ interrupts = <0 198 4>;
++ clocks = <&clock_shub HI3559AV100_SHUB_SPI0_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <3>;
++ dmas = <&hiedmacv310_2 1 1>, <&hiedmacv310_2 0 0>;
++ dma-names = "tx","rx";
++ hisi,spi_cs_sb = <0>;
++ hisi,spi_cs_mask_bit = <0x3>;
++ };
++
++ spi_bus6: spi@18081000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x18081000 0x1000>, <0x18030088 0x4>;
++ interrupts = <0 199 4>;
++ clocks = <&clock_shub HI3559AV100_SHUB_SPI1_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <3>;
++ dmas = <&hiedmacv310_2 3 3>, <&hiedmacv310_2 2 2>;
++ dma-names = "tx","rx";
++ hisi,spi_cs_sb = <2>;
++ hisi,spi_cs_mask_bit = <0x3>;
++ };
++
++ spi_bus7: spi@18082000 {
++ compatible = "arm,pl022", "arm,primecell";
++ arm,primecell-periphid = <0x00800022>;
++ reg = <0x18082000 0x1000>;
++ interrupts = <0 200 4>;
++ clocks = <&clock_shub HI3559AV100_SHUB_SPI2_CLK>;
++ clock-names = "apb_pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ num-cs = <1>;
++ dmas = <&hiedmacv310_2 5 5>, <&hiedmacv310_2 4 4>;
++ dma-names = "tx","rx";
++ hisi,spi_cs_sb = <4>;
++ hisi,spi_cs_mask_bit = <1>;
++ };
++
++ gpio_chip0: gpio_chip@12140000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12140000 0x1000>;
++ interrupts = <0 160 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip1: gpio_chip@12141000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12141000 0x1000>;
++ interrupts = <0 161 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip2: gpio_chip@12142000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12142000 0x1000>;
++ interrupts = <0 162 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip3: gpio_chip@12143000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12143000 0x1000>;
++ interrupts = <0 163 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip4: gpio_chip@12144000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12144000 0x1000>;
++ interrupts = <0 164 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip5: gpio_chip@12145000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12145000 0x1000>;
++ interrupts = <0 165 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip6: gpio_chip@12146000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12146000 0x1000>;
++ interrupts = <0 166 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip7: gpio_chip@12147000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12147000 0x1000>;
++ interrupts = <0 167 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip8: gpio_chip@12148000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12148000 0x1000>;
++ interrupts = <0 168 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip9: gpio_chip@12149000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12149000 0x1000>;
++ interrupts = <0 169 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip10: gpio_chip@1214a000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x1214a000 0x1000>;
++ interrupts = <0 170 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip11: gpio_chip@1214b000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x1214b000 0x1000>;
++ interrupts = <0 171 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip12: gpio_chip@1214c000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x1214c000 0x1000>;
++ interrupts = <0 172 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip13: gpio_chip@1214d000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x1214d000 0x1000>;
++ interrupts = <0 173 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip14: gpio_chip@1214e000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x1214e000 0x1000>;
++ interrupts = <0 174 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip15: gpio_chip@1214f000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x1214f000 0x1000>;
++ interrupts = <0 175 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip16: gpio_chip@12150000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12150000 0x1000>;
++ interrupts = <0 176 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip17: gpio_chip@12151000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12151000 0x1000>;
++ interrupts = <0 177 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ gpio_chip18: gpio_chip@12152000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x12152000 0x1000>;
++ interrupts = <0 178 4>;
++ #gpio-cells = <2>;
++ clocks = <&clock HI3559AV100_FIXED_50M>;
++ clock-names = "apb_pclk";
++ status = "disabled";
++ };
++
++ rtc: rtc@180b0000 {
++ compatible = "hisilicon,hi35xx-rtc";
++ reg = <0x180b0000 0x1000>;
++ interrupts = <0 11 4>;
++ };
++ };
++
++ sys: sys@12010000 {
++ compatible = "hisilicon,hisi-sys";
++ reg = <0x12010000 0x10000>, <0x12020000 0x10000>,
++ <0x12060000 0x10000>, <0X12030000 0x10000>;
++ reg-names = "crg", "sys", "ddr", "misc";
++ };
++
++ osal: osal {
++ compatible = "hisilicon,osal";
++ };
++
++ sysctrl: system-controller@00000000 {
++ compatible = "hisilicon,sysctrl";
++ reg = <0x12020000 0x1000>;
++ reboot-offset = <0x4>;
++ };
++
++ misc_ctrl: misc-controller@12030000 {
++ compatible = "hisilicon,hisi-miscctrl", "syscon";
++ reg = <0x12030000 0x10000>;
++ };
++
++ shub_sysctrl: shubsystem-controller@18030000 {
++ compatible = "hisilicon,shub_sysctrl", "syscon";
++ reg = <0x18030000 0x1000>;
++ };
++
++ ioconfig: ioconfig@1f000000 {
++ compatible = "hisilicon,hisi-ioconfig", "syscon";
++ reg = <0x1f000000 0x10000>;
++ };
++
++ /*FLASH DTS nodes*/
++ fmc: flash-memory-controller@10000000 {
++ compatible = "hisilicon,hisi-fmc";
++ reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
++ reg-names = "control", "memory";
++ clocks = <&clock HI3559AV100_FMC_CLK>;
++ max-dma-size = <0x2000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hisfc:spi_nor_controller {
++ compatible = "hisilicon,fmc-spi-nor";
++ assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
++ assigned-clock-rates = <24000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ hisnfc:spi_nand_controller {
++ compatible = "hisilicon,fmc-spi-nand";
++ assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
++ assigned-clock-rates = <24000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ hinfc:parallel-nand-controller {
++ compatible = "hisilicon,fmc-nand";
++ assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
++ assigned-clock-rates = <200000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
++ ufs: hiufs@0x10010000 {
++ compatible = "hiufs,hiufs_pltfm";
++ reg = <0x10010000 0x1000>, <0x12010180 4>, <0x12030044 4>; /*for asci versionUFSbase:0x10010000 ufsCRGbase:0x12010000+180 MISCbase:0x12030000+0x44 for fpga version ufs base :0x113a0000 */
++ interrupts = <0 83 4>; //after +32 == datasheet value
++ clocks = <&clock 40>;
++ clock-names = "clk";
++ lanes-per-direction = <2>;
++ power-mode = <1>; /* 1:F 2:S 4:FA 5:SA */
++ gear = <3>; /* 1:G1 2:G2 3:G3 4:G4 */
++ rate = <2>; /* 1:A 2:B */
++ cd-gpio = <&gpio_chip0 4 0>; /* card detect pin */
++ update-xfer-length;
++ };
++
++ /*ethernet DTS nodes*/
++ mdio: mdio@101c03c0 {
++ compatible = "hisilicon,hisi-gemac-mdio";
++ reg = <0x101c03c0 0x20>;
++ clocks = <&clock HI3559AV100_ETH_CLK>;
++ resets = <&clock 0x174 14>;
++ reset-names = "phy_reset";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ mdio1: mdio@101e03c0 {
++ compatible = "hisilicon,hisi-gemac-mdio";
++ reg = <0x101e03c0 0x20>;
++ clocks = <&clock HI3559AV100_ETH1_CLK>;
++ resets = <&clock 0x174 15>;
++ reset-names = "phy_reset";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++#endif
++ higmac: ethernet@101c0000 {
++ compatible = "hisilicon,higmac";
++ reg = <0x101c0000 0x1000>,<0x101c300c 0x4>;
++ interrupts = <0 36 4>;
++
++ clocks = <&clock HI3559AV100_ETH_CLK>,
++ <&clock HI3559AV100_ETH_MACIF_CLK>;
++ clock-names = "higmac_clk",
++ "macif_clk";
++
++ resets = <&clock 0x174 0>,
++ <&clock 0x174 4>;
++ reset-names = "port_reset",
++ "macif_reset";
++
++ mac-address = [00 00 00 00 00 00];
++ };
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ higmac1: ethernet@101e0000 {
++ compatible = "hisilicon,higmac";
++ reg = <0x101e0000 0x1000>,<0x101e300c 0x4>;
++ interrupts = <0 37 4>;
++
++ clocks = <&clock HI3559AV100_ETH1_CLK>,
++ <&clock HI3559AV100_ETH1_MACIF_CLK>;
++ clock-names = "higmac_clk",
++ "macif_clk";
++
++ resets = <&clock 0x174 2>,
++ <&clock 0x174 6>;
++ reset-names = "port_reset",
++ "macif_reset";
++
++ mac-address = [00 00 00 00 00 00];
++ };
++
++#endif
++ /*USB DTS nodes*/
++ usb3_phy_0: phy3_0 {
++ compatible = "hisilicon,hisi-usb3-phy_0";
++ reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12300000 0x10000>, <0x12020000 0x10000>;
++ phyid = <0>;
++ };
++
++ usb3_phy_1: phy3_1 {
++ compatible = "hisilicon,hisi-usb3-phy_1";
++ reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12310000 0x10000>, <0x12020000 0x10000>;
++ phyid = <1>;
++ };
++
++#ifdef CONFIG_USB_DRD0_IN_HOST
++ xhci_0:xhci_0@0x12300000 {
++ compatible = "generic-xhci";
++ reg = <0x12300000 0x10000>;
++ interrupts = <0 84 4>;
++ };
++#endif
++#ifdef CONFIG_USB_DRD1_IN_HOST
++ xhci_1:xhci_1@0x12310000 {
++ compatible = "generic-xhci";
++ reg = <0x12310000 0x10000>;
++ interrupts = <0 85 4>;
++ };
++#endif
++#ifdef CONFIG_USB_DRD0_IN_DEVICE
++ hidwc3_0:hiudc3_0@0x12300000 {
++ compatible = "snps,dwc3";
++ reg = <0x12300000 0x10000>, <0x12010000 0x1000>, <0x12020000 0x1000>;
++ interrupts = <0 84 4>;
++ port_speed = <0>;
++ interrupt-names = "peripheral";
++ maximum-speed = "super-speed";
++ dr_mode = "peripheral";
++ snps,dis_initiate_u1;
++ snps,dis_initiate_u2;
++ };
++#endif
++#ifdef CONFIG_USB_DRD1_IN_DEVICE
++ hidwc3_1:hiudc3_1@0x12310000 {
++ compatible = "snps,dwc3";
++ reg = <0x12310000 0x10000>, <0x12010000 0x1000>, <0x12020000 0x1000>;
++ interrupts = <0 85 4>;
++ port_speed = <1>;
++ interrupt-names = "peripheral";
++ maximum-speed = "super-speed";
++ dr_mode = "peripheral";
++ snps,dis_initiate_u1;
++ snps,dis_initiate_u2;
++ };
++#endif
++ /*EMMC/SD/SDIO DTS nodes*/
++ mmc0: eMMC@0x100f0000 {
++ compatible = "hisi-sdhci";
++ reg = <0x100f0000 0x1000>, <0x10290000 0x1000>;
++ interrupts = <0 26 4>;
++ clocks = <&clock HI3559AV100_MMC0_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x1a8 27>, <&clock 0x1a8 29>, <&clock 0x1a8 30>;
++ reset-names = "crg_reset", "dll_reset", "sampl_reset";
++ max-frequency = <198000000>;
++ crg_regmap = <&clock>;
++ non-removable;
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ mmc-hs400-1_8v;
++ mmc-hs400-enhanced-strobe;
++ cap-mmc-hw-reset;
++ devid = <0>;
++ status = "disabled";
++ };
++
++ mmc1: SD@0x10100000 {
++ compatible = "hisi-sdhci";
++ reg = <0x10100000 0x1000>;
++ interrupts = <0 74 4>;
++ clocks = <&clock HI3559AV100_MMC1_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x1ec 27>, <&clock 0x1ec 29>, <&clock 0x1ec 30>;
++ reset-names = "crg_reset", "dll_reset", "sampl_reset";
++ max-frequency = <198000000>;
++ crg_regmap = <&clock>;
++ misc_regmap = <&misc_ctrl>;
++ iocfg_regmap = <&ioconfig>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ sd-uhs-sdr104;
++ full-pwr-cycle;
++ devid = <1>;
++ status = "disabled";
++ };
++
++ mmc2: SD@0x10110000 {
++ compatible = "hisi-sdhci";
++ reg = <0x10110000 0x1000>;
++ interrupts = <0 75 4>;
++ clocks = <&clock HI3559AV100_MMC2_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x214 27>, <&clock 0x214 29>, <&clock 0x214 30>;
++ reset-names = "crg_reset", "dll_reset", "sampl_reset";
++ max-frequency = <49500000>;
++ crg_regmap = <&clock>;
++ misc_regmap = <&misc_ctrl>;
++ iocfg_regmap = <&ioconfig>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ full-pwr-cycle;
++ devid = <2>;
++ status = "disabled";
++ };
++
++ mmc3: SDIO@0x10120000 {
++ compatible = "hisi-sdhci";
++ reg = <0x10120000 0x1000>;
++ interrupts = <0 76 4>;
++ clocks = <&clock HI3559AV100_MMC3_CLK>;
++ clock-names = "mmc_clk";
++ resets = <&clock 0x23c 27>, <&clock 0x23c 29>, <&clock 0x23c 30>;
++ reset-names = "crg_reset", "dll_reset", "sampl_reset";
++ max-frequency = <198000000>;
++ crg_regmap = <&clock>;
++ misc_regmap = <&misc_ctrl>;
++ iocfg_regmap = <&ioconfig>;
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ sd-uhs-sdr104;
++ devid = <3>;
++ status = "disabled";
++ };
++
++ pcie0: pcie@0x12200000 {
++ device_type = "pci";
++ compatible = "hisilicon,hisi-pcie";
++ #size-cells = <2>;
++ #address-cells = <3>;
++ #interrupt-cells = <1>;
++ bus-range = <0x0 0xff>;
++ reg = <0x00 0x12200000 0x00 0x2000>;
++ ranges = <0x02000000 0x00 0x30000000 0x30000000 0x00 0xff00000>;
++ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
++ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 143 0x4
++ 0x0 0x0 0x0 0x2 &gic 0x0 144 0x4
++ 0x0 0x0 0x0 0x3 &gic 0x0 145 0x4
++ 0x0 0x0 0x0 0x4 &gic 0x0 146 0x4>;
++ pcie_controller = <0>;
++ dev_mem_size = <0x8000000>;
++ dev_conf_size = <0x8000000>;
++ sys_ctrl_base = <0x12020000>;
++ };
++ pcie_mcc: pcie_mcc@0x0 {
++ compatible = "hisilicon,pcie_mcc";
++ interrupts = <0 143 4>,<0 144 4>,< 0 145 4>
++ ,< 0 146 4>,< 0 147 4>,< 0 38 4>;
++ };
++
++ hivdmac: hivdma-controller@1f010000 {
++ compatible = "hisilicon,hisi-vdmac";
++ reg = <0x1f010000 0x1000>;
++ interrupts = <0 27 4>;
++ clocks = <&clock HI3559AV100_VDMAC_CLK>;
++ clock-names = "apb_pclk";
++ resets = <&clock 0x14c 4>;
++ reset-names = "dma-reset";
++ #dma-cells = <2>;
++ status = "disabled";
++ };
++
++ hiedmacv310_1: hiedma-controller@10040000 {
++ compatible = "hisilicon,hiedmacv310_n";
++ reg = <0x10040000 0x1000>;
++ misc_regmap = <&misc_ctrl>;
++ misc_ctrl_base = <0x144>;
++ interrupts = <0 82 4>;
++ clocks = <&clock HI3559AV100_EDMAC1_CLK>, <&clock HI3559AV100_EDMAC1_AXICLK>;
++ clock-names = "apb_pclk", "axi_aclk";
++ #clock-cells = <2>;
++ resets = <&clock 0x16c 7>;
++ reset-names = "dma-reset";
++ dma-requests = <32>;
++ dma-channels = <8>;
++ devid = <1>;
++ #dma-cells = <2>;
++ status = "disabled";
++ };
++
++
++ hiedmacv310_2: hiedma-controller@180f0000 {
++ compatible = "hisilicon,hiedmacv310";
++ reg = <0x180f0000 0x1000>;
++ misc_regmap = <&shub_sysctrl>;
++ misc_ctrl_base = <0x6c>;
++ interrupts = <0 202 4>;
++ clocks = <&clock_shub HI3559AV100_SHUB_EDMAC_CLK>, <&clock_shub HI3559AV100_SHUB_EDMAC_CLK>;
++ clock-names = "apb_pclk", "axi_aclk";
++ #clock-cells = <2>;
++ resets = <&clock_shub 0x24 0>;
++ reset-names = "dma-reset";
++ dma-requests = <32>;
++ dma-channels = <8>;
++ devid = <2>;
++ #dma-cells = <2>;
++ status = "disabled";
++ };
++
++ /*SDK DTS nodes*/
++ vi: vi@0x11800000 {
++ compatible = "hisilicon,hisi-vi";
++ reg = <0x11800000 0x30000>, <0x11a80000 0x40000>, <0x11ac0000 0x40000>;
++ reg-names = "VI_CAP0", "VI_PROC0", "VI_PROC1";
++ interrupts = <0 60 4>, <0 61 4>, <0 62 4>;
++ interrupt-names = "VI_CAP0", "VI_PROC0", "VI_PROC1";
++ };
++
++ isp: isp@0x11820000 {
++ compatible = "hisilicon,hisi-isp";
++ reg = <0x11820000 0x100000>;
++ reg-names = "ISP";
++ interrupts = <0 60 4>;
++ interrupt-names = "ISP";
++ };
++
++ mipi: mipi@0x11a00000 {
++ compatible = "hisilicon,hisi-mipi";
++ reg = <0x11a00000 0x20000>, <0x11a40000 0x10000>;
++ reg-names = "SLVS_EC0", "MIPI0";
++ interrupts = <0 86 4>, <0 88 4>;
++ interrupt-names = "SLVS_EC0", "MIPI0";
++ };
++
++ vpss: vpss@0x11420000 {
++ compatible = "hisilicon,hisi-vpss";
++ reg = <0x11420000 0x20000>, <0x11440000 0x20000>;
++ reg-names = "vpss0", "vpss1";
++ interrupts = <0 45 4>, <0 46 4>;
++ interrupt-names = "vpss0", "vpss1";
++ };
++
++ vgs: vgs@0x11E20000 {
++ compatible = "hisilicon,hisi-vgs";
++ reg = <0x11E20000 0x10000>, <0x11260000 0x10000>;
++ reg-names = "vgs0", "vgs1";
++ interrupts = <0 43 4>, <0 44 4>;
++ interrupt-names = "vgs0", "vgs1";
++ };
++
++ gdc: gdc@0x11240000 {
++ compatible = "hisilicon,hisi-gdc";
++ reg = <0x11240000 0x10000>, <0x11250000 0x10000>;
++ reg-names = "gdc0", "gdc1";
++ interrupts = <0 47 4>, <0 48 4>;
++ interrupt-names = "gdc0", "gdc1";
++ };
++
++ dis: dis@0x11200000 {
++ compatible = "hisilicon,hisi-dis";
++ reg = <0x11200000 0x10000>;
++ reg-names = "dis";
++ interrupts = <0 51 4>;
++ interrupt-names = "dis";
++ };
++
++ avs: avs@0x11d00000 {
++ compatible = "hisilicon,hisi-avs";
++ reg = <0x11d00000 0x10000>;
++ reg-names = "avs";
++ interrupts = <0 152 4>;
++ interrupt-names = "avs";
++ };
++
++ vo: vo@0x11100000 {
++ compatible = "hisilicon,hisi-vo";
++ reg = <0x11100000 0x20000>;
++ reg-names = "vo";
++ interrupts = <0 67 4>;
++ interrupt-names = "vo";
++ };
++ hifb: hifb@0x11100000 {
++ compatible = "hisilicon,hisi-hifb";
++ reg = <0x11100000 0x20000>;
++ reg-names = "hifb";
++ interrupts = <0 68 4>;
++ interrupt-names = "hifb";
++ };
++ mipi_tx: mipi_tx@0x11170000 {
++ compatible = "hisilicon,hisi-mipi_tx";
++ reg = <0x11170000 0x10000>;
++ reg-names = "mipi_tx";
++ interrupts = <0 63 4>;
++ interrupt-names = "mipi_tx";
++ };
++ hdmi: hdmi@0x11140000 {
++ compatible = "hisilicon,hisi-hdmi";
++ reg = <0x11140000 0x30000>, <0x12010000 0x10000>, <0x12000000 0x6000>;
++ reg-names = "hdmi0", "crg", "timer";
++ interrupts = <0 5 4>;
++ interrupt-names = "timer";
++ };
++
++ vedu: vedu@0x11300000 {
++ compatible = "hisilicon,hisi-vedu";
++ reg = <0x11300000 0x10000>, <0x11310000 0x10000>,<0x11400000 0x10000>,<0x11320000 0x10000>;
++ reg-names = "vedu0", "vedu1","vedu2","jpge";
++ interrupts = <0 39 4>, <0 40 4>,<0 41 4>,<0 49 4>;
++ interrupt-names = "vedu0", "vedu1","vedu2","jpge";
++ };
++
++ venc: venc {
++ compatible = "hisilicon,hisi-venc";
++ };
++
++ vdh: vdh@0x11e10000 {
++ compatible = "hisilicon,hisi-vdh";
++ reg = <0x11e10000 0x10000>;
++ reg-names = "vdh_scd" ;
++ interrupts = <0 91 4>,<0 92 4>,<0 94 4>;
++ interrupt-names = "vdh_olp","vdh_ilp","scd";
++ };
++
++ jpegd: jpegd@0x11210000 {
++ compatible = "hisilicon,hisi-jpegd";
++ reg = <0x11210000 0x10000>;
++ reg-names = "jpegd";
++ interrupts = <0 52 4>;
++ interrupt-names = "jpegd";
++ };
++
++ nnie: nnie@0x11500000 {
++ compatible = "hisilicon,hisi-nnie";
++ reg = <0x11500000 0x10000>,<0x11600000 0x10000>;
++ reg-names = "nnie0", "nnie1";
++ interrupts = <0 58 4>,<0 59 4>;
++ interrupt-names = "nnie0", "nnie1";
++ };
++ dpu_rect: dpu_rect@0x11630000 {
++ compatible = "hisilicon,hisi-dpu_rect";
++ reg = <0x11630000 0x10000>;
++ reg-names = "dpu_rect";
++ interrupts = <0 208 4>;
++ interrupt-names = "rect";
++ };
++ dpu_match: dpu_match@0x11630000 {
++ compatible = "hisilicon,hisi-dpu_match";
++ reg = <0x11630000 0x10000>;
++ reg-names = "dpu_match";
++ interrupts = <0 209 4>;
++ interrupt-names = "match";
++ };
++ dsp: dsp@0x11510000 {
++ compatible = "hisilicon,hisi-dsp";
++ reg = <0x11510000 0x10000>,<0x11520000 0x10000>,<0x11610000 0x10000>,<0x11620000 0x10000>;
++ reg-names = "dsp0","dsp1","dsp2","dsp3";
++ };
++ ive: ive@0x11530000 {
++ compatible = "hisilicon,hisi-ive";
++ reg = <0x11530000 0x10000>;
++ reg-names = "ive";
++ interrupts = <0 56 4>;
++ interrupt-names = "ive";
++ };
++ fd: fd@0x11E00000 {
++ compatible = "hisilicon,hisi-fd";
++ reg = <0x11E00000 0x10000>;
++ reg-names = "fd";
++ interrupts = <0 57 4>;
++ interrupt-names = "fd";
++ };
++ aiao: aiao@11180000 {
++ compatible = "hisilicon,hisi-aiao";
++ reg = <0x11180000 0x10000>,<0x11190000 0x10000>,<0x12010000 0x10000>;
++ reg-names = "acodec","aiao","crg";
++ interrupts = <0 69 4>,<0 102 4>;
++ interrupt-names = "AIO","VOIE";
++ };
++
++ tde: tde@0x11230000 {
++ compatible = "hisilicon,hisi-tde";
++ reg = <0x11230000 0x10000>;
++ reg-names = "tde";
++ interrupts = <0 53 4>;
++ interrupt-names = "tde_osr_isr";
++ };
++
++ vddgpu: regulator@0x12030064 {
++ compatible = "hisilicon,hi3559a-volt";
++ reg = <0x12030064 0x4>;
++ reg-names = "base-address";
++ regulator-name = "vdd-gpu";
++ regulator-min-microvolt = <600000>;
++ regulator-max-microvolt = <940000>;
++ regulator-always-on;
++ status = "okay";
++ };
++
++ regulators@12030000 {
++ compatible = "hi3559a,regulators";
++ reg = <0x12030000 0x1000>;
++ regulator-num = <3>;
++ regulator-name-array = "regulator-a73","regulator-gpu","regulator-media";
++
++ a73_regulator: a73_regulator{
++ regulator-name = "regulator-a73";
++ regulator-min-microvolt = <597000>;
++ regulator-max-microvolt = <1078000>;
++ regulator-always-on;
++ reg_offset = <0x6c>;
++ };
++
++ gpu_regulator: gpu_regulator{
++ regulator-name = "regulator-gpu";
++ regulator-min-microvolt = <603000>;
++ regulator-max-microvolt = <943000>;
++ regulator-always-on;
++ reg_offset = <0x64>;
++ };
++
++ media_regulator: media_regulator{
++ regulator-name = "regulator-media";
++ regulator-min-microvolt = <603000>;
++ regulator-max-microvolt = <935000>;
++ regulator-always-on;
++ reg_offset = <0x68>;
++ };
++
++ };
++
++ gpu:gpu@0x11C00000 {
++ compatible = "arm,malit6xx", "arm,mali-midgard";
++ reg = <0x11C00000 0x4000>;
++ interrupts = <0 102 4>, <0 103 4>, <0 101 4>;
++ interrupt-names = "JOB", "MMU", "GPU";
++
++ clocks = <&clock HI3559AV100_GPLL_CLK>;
++ clock-names = "clk_mali";
++ mali-supply = <&vddgpu>;
++ operating-points = <
++ 500000 880000>;
++
++ status = "okay";
++ };
++
++ cipher: cipher@0x10200000 {
++ compatible = "hisilicon,hisi-cipher";
++ reg = <0x10200000 0x10000>,<0x10220000 0x10000>;
++ reg-names = "cipher","rsa";
++ interrupts = <0 30 4>,<0 30 4>,<0 104 4>;
++ interrupt-names = "cipher","hash","rsa";
++ };
++
++ ir: ir@0x120F0000 {
++ compatible = "hisilicon,hi-ir";
++ reg = <0x120F0000 0x10000>;
++ reg-names = "hi-ir";
++ interrupts = <0 24 4>;
++ interrupt-names = "hi-ir";
++ };
++ wdg: wdg@0x12080000 {
++ compatible = "hisilicon,hi-wdg";
++ reg = <0x12080000 0x1000>,<0x12081000 0x1000>,<0x12082000 0x1000>;
++ reg-names = "hi-wdg0","hi-wdg1","hi-wdg2";
++ interrupts = <0 105 4>;
++ interrupt-names = "hi-wdg";
++ };
++
++ };
++};
diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_amp_defconfig b/arch/arm64/configs/hi3559av100_arm64_big_little_amp_defconfig
new file mode 100644
index 0000000..c73c4d2
@@ -183463,6 +220765,30694 @@ index 0000000..f321219
+CONFIG_SG_POOL=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_amp_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_amp_defconfig
+new file mode 100644
+index 0000000..3416154
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_amp_defconfig
+@@ -0,0 +1,3841 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++# CONFIG_IMG_GZ_DTB is not set
++CONFIG_IMG_DTB=y
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_FSL_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_SPI_NXP_SPIFI is not set
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_PCI is not set
++CONFIG_MMC_SDHCI_PLTFM=y
++# CONFIG_MMC_SDHCI_OF_ARASAN is not set
++# CONFIG_MMC_SDHCI_OF_AT91 is not set
++CONFIG_MMC_SDHCI_HISI=y
++# CONFIG_MMC_SDHCI_PXAV3 is not set
++# CONFIG_MMC_SDHCI_PXAV2 is not set
++# CONFIG_MMC_SDHCI_F_SDH30 is not set
++# CONFIG_MMC_SDHCI_IPROC is not set
++# CONFIG_MMC_OMAP_HS is not set
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_GOLDFISH is not set
++# CONFIG_MMC_SPI is not set
++# CONFIG_MMC_SDHI is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_SH_MMCIF is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_TOSHIBA_PCI is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_KS7010 is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3562V100 is not set
++# CONFIG_COMMON_CLK_HI3566V100 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++# CONFIG_COMMON_CLK_HI3559AV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_defconfig
+new file mode 100644
+index 0000000..38194c8
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_defconfig
+@@ -0,0 +1,3841 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++# CONFIG_IMG_GZ_DTB is not set
++CONFIG_IMG_DTB=y
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_FSL_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_SPI_NXP_SPIFI is not set
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_PCI is not set
++CONFIG_MMC_SDHCI_PLTFM=y
++# CONFIG_MMC_SDHCI_OF_ARASAN is not set
++# CONFIG_MMC_SDHCI_OF_AT91 is not set
++CONFIG_MMC_SDHCI_HISI=y
++# CONFIG_MMC_SDHCI_PXAV3 is not set
++# CONFIG_MMC_SDHCI_PXAV2 is not set
++# CONFIG_MMC_SDHCI_F_SDH30 is not set
++# CONFIG_MMC_SDHCI_IPROC is not set
++# CONFIG_MMC_OMAP_HS is not set
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_GOLDFISH is not set
++# CONFIG_MMC_SPI is not set
++# CONFIG_MMC_SDHI is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_SH_MMCIF is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_TOSHIBA_PCI is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_KS7010 is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3562V100 is not set
++# CONFIG_COMMON_CLK_HI3566V100 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++# CONFIG_COMMON_CLK_HI3559AV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_amp_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_amp_defconfig
+new file mode 100644
+index 0000000..0e3a331
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_amp_defconfig
+@@ -0,0 +1,3841 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++# CONFIG_IMG_GZ_DTB is not set
++CONFIG_IMG_DTB=y
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-emmc"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_FSL_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_SPI_NXP_SPIFI is not set
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_PCI is not set
++CONFIG_MMC_SDHCI_PLTFM=y
++# CONFIG_MMC_SDHCI_OF_ARASAN is not set
++# CONFIG_MMC_SDHCI_OF_AT91 is not set
++CONFIG_MMC_SDHCI_HISI=y
++# CONFIG_MMC_SDHCI_PXAV3 is not set
++# CONFIG_MMC_SDHCI_PXAV2 is not set
++# CONFIG_MMC_SDHCI_F_SDH30 is not set
++# CONFIG_MMC_SDHCI_IPROC is not set
++# CONFIG_MMC_OMAP_HS is not set
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_GOLDFISH is not set
++# CONFIG_MMC_SPI is not set
++# CONFIG_MMC_SDHI is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_SH_MMCIF is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_TOSHIBA_PCI is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_KS7010 is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3562V100 is not set
++# CONFIG_COMMON_CLK_HI3566V100 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++# CONFIG_COMMON_CLK_HI3559AV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_defconfig
+new file mode 100644
+index 0000000..6566869
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_defconfig
+@@ -0,0 +1,3841 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++# CONFIG_IMG_GZ_DTB is not set
++CONFIG_IMG_DTB=y
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-emmc"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_FSL_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_SPI_NXP_SPIFI is not set
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_PCI is not set
++CONFIG_MMC_SDHCI_PLTFM=y
++# CONFIG_MMC_SDHCI_OF_ARASAN is not set
++# CONFIG_MMC_SDHCI_OF_AT91 is not set
++CONFIG_MMC_SDHCI_HISI=y
++# CONFIG_MMC_SDHCI_PXAV3 is not set
++# CONFIG_MMC_SDHCI_PXAV2 is not set
++# CONFIG_MMC_SDHCI_F_SDH30 is not set
++# CONFIG_MMC_SDHCI_IPROC is not set
++# CONFIG_MMC_OMAP_HS is not set
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_GOLDFISH is not set
++# CONFIG_MMC_SPI is not set
++# CONFIG_MMC_SDHI is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_SH_MMCIF is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_TOSHIBA_PCI is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_KS7010 is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3562V100 is not set
++# CONFIG_COMMON_CLK_HI3566V100 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++# CONFIG_COMMON_CLK_HI3559AV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_nand_amp_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_nand_amp_defconfig
+new file mode 100644
+index 0000000..23eeeaa
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_nand_amp_defconfig
+@@ -0,0 +1,3836 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++# CONFIG_IMG_GZ_DTB is not set
++CONFIG_IMG_DTB=y
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++# CONFIG_MTD_SPI_NAND_HISI_BVT is not set
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_NAND_HIFMC100=y
++# CONFIG_HIFMC100_NAND_EDO_MODE is not set
++CONFIG_RW_H_WIDTH=10
++CONFIG_R_L_WIDTH=10
++CONFIG_W_L_WIDTH=10
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_SPI_NOR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_PCI is not set
++CONFIG_MMC_SDHCI_PLTFM=y
++# CONFIG_MMC_SDHCI_OF_ARASAN is not set
++# CONFIG_MMC_SDHCI_OF_AT91 is not set
++CONFIG_MMC_SDHCI_HISI=y
++# CONFIG_MMC_SDHCI_PXAV3 is not set
++# CONFIG_MMC_SDHCI_PXAV2 is not set
++# CONFIG_MMC_SDHCI_F_SDH30 is not set
++# CONFIG_MMC_SDHCI_IPROC is not set
++# CONFIG_MMC_OMAP_HS is not set
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_GOLDFISH is not set
++# CONFIG_MMC_SPI is not set
++# CONFIG_MMC_SDHI is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_SH_MMCIF is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_TOSHIBA_PCI is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_KS7010 is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3562V100 is not set
++# CONFIG_COMMON_CLK_HI3566V100 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++# CONFIG_COMMON_CLK_HI3559AV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_nand_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_nand_defconfig
+new file mode 100644
+index 0000000..2e10d2f
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_nand_defconfig
+@@ -0,0 +1,3836 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++# CONFIG_IMG_GZ_DTB is not set
++CONFIG_IMG_DTB=y
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++# CONFIG_MTD_SPI_NAND_HISI_BVT is not set
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_NAND_HIFMC100=y
++# CONFIG_HIFMC100_NAND_EDO_MODE is not set
++CONFIG_RW_H_WIDTH=10
++CONFIG_R_L_WIDTH=10
++CONFIG_W_L_WIDTH=10
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_SPI_NOR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_MQ_DEFAULT is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_PCI is not set
++CONFIG_MMC_SDHCI_PLTFM=y
++# CONFIG_MMC_SDHCI_OF_ARASAN is not set
++# CONFIG_MMC_SDHCI_OF_AT91 is not set
++CONFIG_MMC_SDHCI_HISI=y
++# CONFIG_MMC_SDHCI_PXAV3 is not set
++# CONFIG_MMC_SDHCI_PXAV2 is not set
++# CONFIG_MMC_SDHCI_F_SDH30 is not set
++# CONFIG_MMC_SDHCI_IPROC is not set
++# CONFIG_MMC_OMAP_HS is not set
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_GOLDFISH is not set
++# CONFIG_MMC_SPI is not set
++# CONFIG_MMC_SDHI is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_SH_MMCIF is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_TOSHIBA_PCI is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MMC_CQ_HCI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_KS7010 is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3562V100 is not set
++# CONFIG_COMMON_CLK_HI3566V100 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++# CONFIG_COMMON_CLK_HI3559AV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_ufs_amp_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_ufs_amp_defconfig
+new file mode 100644
+index 0000000..4345bd9
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_ufs_amp_defconfig
+@@ -0,0 +1,3803 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++CONFIG_ARCH_HISI_BVT_AMP=y
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++# CONFIG_IMG_GZ_DTB is not set
++CONFIG_IMG_DTB=y
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-ufs"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_FSL_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_SPI_NXP_SPIFI is not set
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_MQ_DEFAULT=y
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++CONFIG_SCSI_UFSHCD=y
++# CONFIG_SCSI_UFSHCD_PCI is not set
++CONFIG_SCSI_UFSHCD_PLATFORM=y
++CONFIG_SCSI_UFS_HI3559AV100=y
++# CONFIG_SCSI_UFS_CARD is not set
++# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++# CONFIG_MMC is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3562V100 is not set
++# CONFIG_COMMON_CLK_HI3566V100 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++# CONFIG_COMMON_CLK_HI3559AV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
+diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_ufs_defconfig b/arch/arm64/configs/hi3569v100_arm64_big_little_ufs_defconfig
+new file mode 100644
+index 0000000..0c4e3e4
+--- /dev/null
++++ b/arch/arm64/configs/hi3569v100_arm64_big_little_ufs_defconfig
+@@ -0,0 +1,3801 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm64 4.9.37 Kernel Configuration
++#
++CONFIG_ARM64=y
++CONFIG_64BIT=y
++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
++CONFIG_MMU=y
++CONFIG_DEBUG_RODATA=y
++CONFIG_ARM64_PAGE_SHIFT=12
++CONFIG_ARM64_CONT_SHIFT=4
++CONFIG_ARCH_MMAP_RND_BITS_MIN=18
++CONFIG_ARCH_MMAP_RND_BITS_MAX=24
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CSUM=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_HAVE_GENERIC_RCU_GUP=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_SMP=y
++CONFIG_SWIOTLB=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=3
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_EXTABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_COMPILE_TEST=y
++CONFIG_LOCALVERSION=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_FHANDLE is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++CONFIG_ARCH_CLOCKSOURCE_DATA=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_ARCH_HAS_TICK_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_HZ_PERIODIC=y
++# CONFIG_NO_HZ_IDLE is not set
++# CONFIG_NO_HZ_FULL is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++# CONFIG_TASKS_RCU is not set
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_TREE_RCU_TRACE=y
++# CONFIG_RCU_EXPEDITE_BOOT is not set
++# CONFIG_BUILD_BIN2C is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_GENERIC_SCHED_CLOCK=y
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++# CONFIG_CGROUPS is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++# CONFIG_USER_NS is not set
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++CONFIG_RELAY=y
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++# CONFIG_SGETMASK_SYSCALL is not set
++CONFIG_SYSFS_SYSCALL=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
++CONFIG_KALLSYMS_BASE_RELATIVE=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_USERFAULTFD=y
++CONFIG_PCI_QUIRKS=y
++CONFIG_MEMBARRIER=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SYSTEM_DATA_VERIFICATION is not set
++# CONFIG_PROFILING is not set
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++# CONFIG_UPROBES is not set
++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_GENERIC_IDLE_POLL_SETUP=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_RCU_TABLE_FREE=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_HAVE_CC_STACKPROTECTOR=y
++CONFIG_CC_STACKPROTECTOR=y
++# CONFIG_CC_STACKPROTECTOR_NONE is not set
++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
++CONFIG_CC_STACKPROTECTOR_STRONG=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_ARCH_MMAP_RND_BITS=18
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
++# CONFIG_HAVE_ARCH_HASH is not set
++# CONFIG_ISA_BUS_API is not set
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++# CONFIG_CPU_NO_EFFICIENT_FFS is not set
++# CONFIG_HAVE_ARCH_VMAP_STACK is not set
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++CONFIG_BLK_CMDLINE_PARSER=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_DEADLINE=y
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="deadline"
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# Platform selection
++#
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_ALPINE is not set
++# CONFIG_ARCH_BCM2835 is not set
++# CONFIG_ARCH_BCM_IPROC is not set
++# CONFIG_ARCH_BERLIN is not set
++# CONFIG_ARCH_BRCMSTB is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_LAYERSCAPE is not set
++# CONFIG_ARCH_LG1K is not set
++# CONFIG_ARCH_HISI is not set
++CONFIG_ARCH_HISI_BVT=y
++# CONFIG_ARCH_HI3559AV100 is not set
++CONFIG_ARCH_HI3569V100=y
++# CONFIG_ACCESS_M7_DEV is not set
++# CONFIG_ARCH_HISI_BVT_AMP is not set
++# CONFIG_ARCH_MEDIATEK is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_QCOM is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_SEATTLE is not set
++# CONFIG_ARCH_RENESAS is not set
++# CONFIG_ARCH_STRATIX10 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_SPRD is not set
++# CONFIG_ARCH_THUNDER is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_VULCAN is not set
++# CONFIG_ARCH_XGENE is not set
++# CONFIG_ARCH_ZX is not set
++# CONFIG_ARCH_ZYNQMP is not set
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_DOMAINS_GENERIC=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_PCIEPORTBUS=y
++# CONFIG_PCIEAER is not set
++# CONFIG_PCIEASPM is not set
++# CONFIG_PCIE_PME is not set
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_BUS_ADDR_T_64BIT=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI host controller drivers
++#
++# CONFIG_PCIE_DW_PLAT is not set
++# CONFIG_PCI_HOST_GENERIC is not set
++# CONFIG_PCI_HISI is not set
++# CONFIG_PCI_HOST_THUNDER_PEM is not set
++# CONFIG_PCI_HOST_THUNDER_ECAM is not set
++# CONFIG_HIPCIE is not set
++
++#
++# Kernel Features
++#
++
++#
++# ARM errata workarounds via the alternatives framework
++#
++CONFIG_ARM64_ERRATUM_826319=y
++CONFIG_ARM64_ERRATUM_827319=y
++CONFIG_ARM64_ERRATUM_824069=y
++CONFIG_ARM64_ERRATUM_819472=y
++CONFIG_ARM64_ERRATUM_832075=y
++CONFIG_ARM64_ERRATUM_845719=y
++CONFIG_ARM64_ERRATUM_843419=y
++CONFIG_CAVIUM_ERRATUM_22375=y
++CONFIG_CAVIUM_ERRATUM_23154=y
++CONFIG_CAVIUM_ERRATUM_27456=y
++CONFIG_QCOM_QDF2400_ERRATUM_0065=y
++CONFIG_ARM64_4K_PAGES=y
++# CONFIG_ARM64_16K_PAGES is not set
++# CONFIG_ARM64_64K_PAGES is not set
++CONFIG_ARM64_VA_BITS_39=y
++# CONFIG_ARM64_VA_BITS_48 is not set
++CONFIG_ARM64_VA_BITS=39
++# CONFIG_CPU_BIG_ENDIAN is not set
++CONFIG_SCHED_MC=y
++# CONFIG_SCHED_SMT is not set
++CONFIG_NR_CPUS=64
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_NUMA is not set
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=100
++# CONFIG_SCHED_HRTICK is not set
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_SYS_SUPPORTS_HUGETLBFS=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_HAVE_MEMORY_PRESENT=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_NO_BOOTMEM=y
++CONFIG_MEMORY_ISOLATION=y
++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_BOUNCE=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_TRANSPARENT_HUGEPAGE is not set
++# CONFIG_CLEANCACHE is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++# CONFIG_CMA_DEBUGFS is not set
++CONFIG_CMA_AREAS=7
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_SECCOMP is not set
++# CONFIG_PARAVIRT is not set
++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
++# CONFIG_KEXEC is not set
++# CONFIG_XEN is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_UNMAP_KERNEL_AT_EL0=y
++CONFIG_HARDEN_BRANCH_PREDICTOR=y
++# CONFIG_ARMV8_DEPRECATED is not set
++# CONFIG_ARM64_SW_TTBR0_PAN is not set
++
++#
++# ARMv8.1 architectural features
++#
++CONFIG_ARM64_HW_AFDBM=y
++CONFIG_ARM64_PAN=y
++# CONFIG_ARM64_LSE_ATOMICS is not set
++CONFIG_ARM64_VHE=y
++
++#
++# ARMv8.2 architectural features
++#
++CONFIG_ARM64_UAO=y
++CONFIG_ARM64_MODULE_CMODEL_LARGE=y
++# CONFIG_RANDOMIZE_BASE is not set
++
++#
++# Boot options
++#
++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox"
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_EFI is not set
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
++CONFIG_IMG_GZ_DTB=y
++# CONFIG_IMG_DTB is not set
++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-ufs"
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++CONFIG_COREDUMP=y
++CONFIG_COMPAT=y
++CONFIG_SYSVIPC_COMPAT=y
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_OPP=y
++CONFIG_PM_CLK=y
++CONFIG_PM_GENERIC_DOMAINS=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
++CONFIG_PM_GENERIC_DOMAINS_OF=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
++
++#
++# CPU frequency scaling drivers
++#
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPUFREQ_DT_PLATDEV=y
++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=m
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_UDP_TUNNEL is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_NET_FOU_IP_TUNNELS is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++CONFIG_IPV6_ROUTER_PREF=y
++# CONFIG_IPV6_ROUTE_INFO is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_ILA is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++# CONFIG_IPV6_VTI is not set
++CONFIG_IPV6_SIT=m
++# CONFIG_IPV6_SIT_6RD is not set
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_FOU is not set
++# CONFIG_IPV6_FOU_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NET_PTP_CLASSIFY is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE is not set
++# CONFIG_NETFILTER_NETLINK_LOG is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_TABLES is not set
++# CONFIG_NETFILTER_XTABLES is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# IPv6: Netfilter Configuration
++#
++# CONFIG_NF_DEFRAG_IPV6 is not set
++# CONFIG_NF_DUP_IPV6 is not set
++# CONFIG_NF_REJECT_IPV6 is not set
++# CONFIG_NF_LOG_IPV6 is not set
++# CONFIG_IP6_NF_IPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++# CONFIG_SOCK_CGROUP_DATA is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_STREAM_PARSER is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++# CONFIG_NET_DEVLINK is not set
++CONFIG_MAY_USE_DEVLINK=y
++CONFIG_HAVE_EBPF_JIT=y
++
++#
++# Device Drivers
++#
++CONFIG_ARM_AMBA=y
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
++CONFIG_ALLOW_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_FENCE_TRACE is not set
++CONFIG_DMA_CMA=y
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=4
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++
++#
++# Bus devices
++#
++# CONFIG_QCOM_EBI2 is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_VEXPRESS_CONFIG is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_BCM63XX_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++CONFIG_MTD_BLOCK2MTD=y
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_DENALI_PCI is not set
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_VF610_NFC is not set
++# CONFIG_MTD_NAND_SH_FLCTL is not set
++# CONFIG_MTD_NAND_HISI504 is not set
++# CONFIG_MTD_NAND_MTK is not set
++CONFIG_MTD_SPI_NAND_HISI_BVT=y
++# CONFIG_HISI_NAND_ECC_STATUS_REPORT is not set
++# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set
++CONFIG_MTD_SPI_NAND_HIFMC100=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_MT81xx_NOR is not set
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++# CONFIG_SPI_FSL_QUADSPI is not set
++CONFIG_SPI_HISI_SFC=y
++# CONFIG_SPI_NXP_SPIFI is not set
++# CONFIG_MTD_SPI_IDS is not set
++# CONFIG_CLOSE_SPI_8PIN_4IO is not set
++CONFIG_HISI_SPI_BLOCK_PROTECT=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++CONFIG_MTD_UBI_GLUEBI=y
++# CONFIG_MTD_UBI_BLOCK is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++# CONFIG_OF_ALL_DTBS is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_ADDRESS_PCI=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_MDIO=y
++CONFIG_OF_PCI=y
++CONFIG_OF_PCI_IRQ=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SKD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_TARGET is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_QCOM_COINCELL is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++
++#
++# Intel MIC Bus Driver
++#
++
++#
++# SCIF Bus Driver
++#
++
++#
++# VOP Bus Driver
++#
++
++#
++# Intel MIC Host Driver
++#
++
++#
++# Intel MIC Card Driver
++#
++
++#
++# SCIF Driver
++#
++
++#
++# Intel MIC Coprocessor State Management (COSM) Drivers
++#
++
++#
++# VOP Driver
++#
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_CXL_BASE is not set
++# CONFIG_CXL_AFU_DRIVER_OPS is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_MQ_DEFAULT=y
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_HISI_SAS is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_SCSI_ESAS2R is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT3SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_SMARTPQI is not set
++CONFIG_SCSI_UFSHCD=y
++# CONFIG_SCSI_UFSHCD_PCI is not set
++CONFIG_SCSI_UFSHCD_PLATFORM=y
++CONFIG_SCSI_UFS_HI3559AV100=y
++# CONFIG_SCSI_UFS_CARD is not set
++# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_SCSI_SNIC is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_AM53C974 is not set
++# CONFIG_SCSI_WD719X is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_HAVE_PATA_PLATFORM=y
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++
++#
++# Distributed Switch Architecture drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_AGERE=y
++# CONFIG_ET131X is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_XGENE is not set
++# CONFIG_NET_VENDOR_ARC is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++# CONFIG_ALX is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_CADENCE is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++# CONFIG_THUNDER_NIC_PF is not set
++# CONFIG_THUNDER_NIC_VF is not set
++# CONFIG_THUNDER_NIC_BGX is not set
++# CONFIG_THUNDER_NIC_RGX is not set
++# CONFIG_LIQUIDIO is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_HISILICON=y
++# CONFIG_HIX5HD2_GMAC is not set
++# CONFIG_HISI_FEMAC is not set
++# CONFIG_HIP04_ETH is not set
++# CONFIG_HNS is not set
++# CONFIG_HNS_DSAF is not set
++# CONFIG_HNS_ENET is not set
++CONFIG_HIETH_GMAC=y
++CONFIG_HIGMAC_DDR_64BIT=y
++CONFIG_HIGMAC_DESC_4WORD=y
++CONFIG_HIGMAC_RXCSUM=y
++CONFIG_RX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_SUPPORT=y
++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16
++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++# CONFIG_MLX5_CORE is not set
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++# CONFIG_QED is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TI_CPSW_ALE is not set
++# CONFIG_TLAN is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++
++#
++# MDIO bus device drivers
++#
++# CONFIG_MDIO_BCM_IPROC is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++CONFIG_MDIO_HISI_GEMAC=y
++# CONFIG_MDIO_OCTEON is not set
++# CONFIG_MDIO_THUNDER is not set
++# CONFIG_MDIO_XGENE is not set
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AT803X_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++CONFIG_FIXED_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++CONFIG_WLAN_VENDOR_ADMTEK=y
++CONFIG_WLAN_VENDOR_ATH=y
++# CONFIG_ATH_DEBUG is not set
++# CONFIG_ATH5K_PCI is not set
++CONFIG_WLAN_VENDOR_ATMEL=y
++CONFIG_WLAN_VENDOR_BROADCOM=y
++CONFIG_WLAN_VENDOR_CISCO=y
++CONFIG_WLAN_VENDOR_INTEL=y
++CONFIG_WLAN_VENDOR_INTERSIL=y
++# CONFIG_HOSTAP is not set
++# CONFIG_PRISM54 is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++CONFIG_WLAN_VENDOR_MEDIATEK=y
++CONFIG_WLAN_VENDOR_RALINK=y
++CONFIG_WLAN_VENDOR_REALTEK=y
++CONFIG_WLAN_VENDOR_RSI=y
++CONFIG_WLAN_VENDOR_ST=y
++CONFIG_WLAN_VENDOR_TI=y
++CONFIG_WLAN_VENDOR_ZYDAS=y
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++# CONFIG_NVM is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_CLPS711X is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_ST_KEYSCAN is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_BYD=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_CYPRESS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_FOCALTECH=y
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++# CONFIG_JOYSTICK_XPAD is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_MPU3050 is not set
++# CONFIG_INPUT_GP2A is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_DECODER is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++# CONFIG_INPUT_REGULATOR_HAPTIC is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_DRV260X_HAPTICS is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_INPUT_HISI_POWERKEY is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_SUN4I_PS2 is not set
++# CONFIG_USERIO is not set
++CONFIG_GAMEPORT=y
++# CONFIG_GAMEPORT_NS558 is not set
++# CONFIG_GAMEPORT_L4 is not set
++# CONFIG_GAMEPORT_EMU10K1 is not set
++# CONFIG_GAMEPORT_FM801 is not set
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
++# CONFIG_SERIAL_ATMEL is not set
++# CONFIG_SERIAL_CLPS711X is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_IMX is not set
++# CONFIG_SERIAL_UARTLITE is not set
++# CONFIG_SERIAL_SH_SCI is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_MXS_AUART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_MPS2_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_STM32 is not set
++# CONFIG_SERIAL_MVEBU_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_XILLYBUS is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_HIX5HD2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_AXXIA is not set
++# CONFIG_I2C_BCM_IPROC is not set
++# CONFIG_I2C_BRCMSTB is not set
++# CONFIG_I2C_CADENCE is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EFM32 is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_HIBVT=y
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_LPC2K is not set
++# CONFIG_I2C_MESON is not set
++# CONFIG_I2C_MT65XX is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_RIIC is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SH_MOBILE is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_SUN6I_P2WI is not set
++# CONFIG_I2C_UNIPHIER is not set
++# CONFIG_I2C_UNIPHIER_F is not set
++# CONFIG_I2C_VERSATILE is not set
++# CONFIG_I2C_THUNDERX is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_XLP9XX is not set
++# CONFIG_I2C_RCAR is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_DMA_MSG_MIN_LEN=5
++CONFIG_DMA_MSG_MAX_LEN=4090
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_ATMEL is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++# CONFIG_SPI_BCM2835 is not set
++# CONFIG_SPI_BCM2835AUX is not set
++# CONFIG_SPI_BCM63XX is not set
++# CONFIG_SPI_BCM63XX_HSSPI is not set
++# CONFIG_SPI_BCM_QSPI is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_CLPS711X is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_EP93XX is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_IMX is not set
++# CONFIG_SPI_JCORE is not set
++# CONFIG_SPI_LP8841_RTC is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_FSL_DSPI is not set
++# CONFIG_SPI_MESON_SPIFC is not set
++# CONFIG_SPI_MT65XX is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_OMAP24XX is not set
++# CONFIG_SPI_TI_QSPI is not set
++# CONFIG_SPI_OMAP_100K is not set
++# CONFIG_SPI_ORION is not set
++# CONFIG_SPI_PIC32 is not set
++# CONFIG_SPI_PIC32_SQI is not set
++CONFIG_SPI_PL022=y
++# CONFIG_SPI_PXA2XX is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_RSPI is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SH_MSIOF is not set
++# CONFIG_SPI_SH is not set
++# CONFIG_SPI_SH_HSPI is not set
++# CONFIG_SPI_ST_SSC4 is not set
++# CONFIG_SPI_SUN4I is not set
++# CONFIG_SPI_SUN6I is not set
++# CONFIG_SPI_TEGRA114 is not set
++# CONFIG_SPI_TEGRA20_SFLASH is not set
++# CONFIG_SPI_TEGRA20_SLINK is not set
++# CONFIG_SPI_THUNDERX is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_TXX9 is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_XLP is not set
++# CONFIG_SPI_XTENSA_XTFPGA is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# CONFIG_PTP_1588_CLOCK_PCH is not set
++CONFIG_PINCTRL=y
++
++#
++# Pin controllers
++#
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_AMD is not set
++# CONFIG_PINCTRL_LPC18XX is not set
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_ASPEED_G4 is not set
++# CONFIG_PINCTRL_ASPEED_G5 is not set
++# CONFIG_PINCTRL_BCM281XX is not set
++# CONFIG_PINCTRL_IPROC_GPIO is not set
++# CONFIG_PINCTRL_CYGNUS_MUX is not set
++# CONFIG_PINCTRL_NSP_GPIO is not set
++# CONFIG_PINCTRL_NS2_MUX is not set
++# CONFIG_PINCTRL_NSP_MUX is not set
++# CONFIG_PINCTRL_BERLIN_BG2 is not set
++# CONFIG_PINCTRL_BERLIN_BG2CD is not set
++# CONFIG_PINCTRL_BERLIN_BG2Q is not set
++# CONFIG_PINCTRL_BERLIN_BG4CT is not set
++# CONFIG_PINCTRL_PXA25X is not set
++# CONFIG_PINCTRL_PXA27X is not set
++# CONFIG_PINCTRL_APQ8064 is not set
++# CONFIG_PINCTRL_APQ8084 is not set
++# CONFIG_PINCTRL_IPQ4019 is not set
++# CONFIG_PINCTRL_IPQ8064 is not set
++# CONFIG_PINCTRL_MSM8660 is not set
++# CONFIG_PINCTRL_MSM8960 is not set
++# CONFIG_PINCTRL_MDM9615 is not set
++# CONFIG_PINCTRL_MSM8X74 is not set
++# CONFIG_PINCTRL_MSM8916 is not set
++# CONFIG_PINCTRL_MSM8996 is not set
++# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
++# CONFIG_PINCTRL_STM32F429 is not set
++# CONFIG_PINCTRL_STM32F746 is not set
++# CONFIG_PINCTRL_UNIPHIER is not set
++# CONFIG_PINCTRL_MT2701 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT8135 is not set
++# CONFIG_PINCTRL_MT8127 is not set
++# CONFIG_PINCTRL_MT8173 is not set
++# CONFIG_PINCTRL_MT6397 is not set
++CONFIG_GPIOLIB=y
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_GENERIC=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_ASPEED is not set
++# CONFIG_GPIO_ATH79 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_BRCMSTB is not set
++# CONFIG_GPIO_CLPS711X is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_ETRAXFS is not set
++CONFIG_GPIO_GENERIC_PLATFORM=y
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_IOP is not set
++# CONFIG_GPIO_LPC18XX is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_GPIO_MOXART is not set
++# CONFIG_GPIO_MPC8XXX is not set
++CONFIG_GPIO_PL061=y
++# CONFIG_GPIO_RCAR is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_TEGRA is not set
++# CONFIG_GPIO_TS4800 is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_XGENE is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_XLP is not set
++# CONFIG_GPIO_ZX is not set
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# CONFIG_GPIO_TS4900 is not set
++
++#
++# MFD GPIO expanders
++#
++
++#
++# PCI GPIO expanders
++#
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++
++#
++# SPI or I2C GPIO expanders
++#
++# CONFIG_GPIO_MCP23S08 is not set
++
++#
++# USB GPIO expanders
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_AVS is not set
++CONFIG_POWER_RESET=y
++# CONFIG_POWER_RESET_BRCMKONA is not set
++# CONFIG_POWER_RESET_BRCMSTB is not set
++# CONFIG_POWER_RESET_GPIO is not set
++# CONFIG_POWER_RESET_GPIO_RESTART is not set
++# CONFIG_POWER_RESET_HISI is not set
++# CONFIG_POWER_RESET_LTC2952 is not set
++# CONFIG_POWER_RESET_RESTART is not set
++# CONFIG_POWER_RESET_XGENE is not set
++# CONFIG_POWER_RESET_KEYSTONE is not set
++# CONFIG_POWER_RESET_SYSCON is not set
++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
++# CONFIG_POWER_RESET_RMOBILE is not set
++# CONFIG_POWER_RESET_ZX is not set
++# CONFIG_SYSCON_REBOOT_MODE is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_ACT8945A is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_MANAGER is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24257 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++# CONFIG_CHARGER_BQ25890 is not set
++# CONFIG_CHARGER_SMB347 is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_CHARGER_RT9455 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_EXYNOS_LPASS is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MX25_TSADC is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_MFD_HI655X_PMIC is not set
++CONFIG_MFD_HISI_FMC=y
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_INTEL_SOC_PMIC is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RTSX_PCI is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RTSX_USB is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SMSC is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_STW481X is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_ACT8865 is not set
++# CONFIG_REGULATOR_AD5398 is not set
++# CONFIG_REGULATOR_ANATOP is not set
++# CONFIG_REGULATOR_DA9210 is not set
++# CONFIG_REGULATOR_DA9211 is not set
++# CONFIG_REGULATOR_FAN53555 is not set
++# CONFIG_REGULATOR_GPIO is not set
++# CONFIG_REGULATOR_ISL9305 is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_LP872X is not set
++# CONFIG_REGULATOR_LP8755 is not set
++# CONFIG_REGULATOR_LTC3589 is not set
++# CONFIG_REGULATOR_LTC3676 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_MT6311 is not set
++# CONFIG_REGULATOR_PBIAS is not set
++# CONFIG_REGULATOR_PFUZE100 is not set
++# CONFIG_REGULATOR_PV88060 is not set
++# CONFIG_REGULATOR_PV88080 is not set
++# CONFIG_REGULATOR_PV88090 is not set
++# CONFIG_REGULATOR_QCOM_SPMI is not set
++# CONFIG_REGULATOR_STW481X_VMMC is not set
++# CONFIG_REGULATOR_TPS51632 is not set
++# CONFIG_REGULATOR_TPS62360 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++# CONFIG_MEDIA_SDR_SUPPORT is not set
++# CONFIG_MEDIA_RC_SUPPORT is not set
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++# CONFIG_TTPCI_EEPROM is not set
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_DTCS033 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STK1135 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TOUPTEK is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_MEDIA_PCI_SUPPORT is not set
++# CONFIG_V4L_PLATFORM_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++#
++# Supported MMC/SDIO adapters
++#
++# CONFIG_CYPRESS_FIRMWARE is not set
++
++#
++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
++#
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++
++#
++# I2C Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++
++#
++# Flash devices
++#
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++
++#
++# Sensors used on soc_camera driver
++#
++
++#
++# SPI helper chips
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++
++#
++# Graphics support
++#
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++# CONFIG_DRM is not set
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_CLPS711X is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_GOLDFISH is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_AUO_K190X is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# CONFIG_FB_SM712 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_VGASTATE is not set
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_A4TECH=y
++# CONFIG_HID_ACRUX is not set
++CONFIG_HID_APPLE=y
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_AUREAL is not set
++CONFIG_HID_BELKIN=y
++# CONFIG_HID_BETOP_FF is not set
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CP2112 is not set
++CONFIG_HID_CYPRESS=y
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++CONFIG_HID_EZKEY=y
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_TWINHAN is not set
++CONFIG_HID_KENSINGTON=y
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++# CONFIG_HID_LOGITECH_HIDPP is not set
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
++CONFIG_USB_XHCI_PLATFORM=y
++# CONFIG_USB_XHCI_MTK is not set
++# CONFIG_USB_XHCI_MVEBU is not set
++# CONFIG_USB_XHCI_RCAR is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_RENESAS_USBHS is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_MUSB_HDRC is not set
++CONFIG_USB_DWC3_HISI=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_HOST is not set
++CONFIG_USB_DWC3_GADGET=y
++# CONFIG_USB_DWC3_DUAL_ROLE is not set
++
++#
++# Platform Glue Driver Support
++#
++CONFIG_USB_DWC3_EXYNOS=y
++CONFIG_USB_DWC3_PCI=y
++CONFIG_USB_DWC3_KEYSTONE=y
++CONFIG_USB_DWC3_OF_SIMPLE=y
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_PHY is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_USB_ULPI is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_RENESAS_USB3 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_HIUSB_DEVICE2_0 is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_DUMMY_HCD is not set
++CONFIG_USB_LIBCOMPOSITE=m
++CONFIG_USB_F_MASS_STORAGE=m
++CONFIG_USB_F_UVC=m
++CONFIG_USB_CONFIGFS=m
++# CONFIG_USB_CONFIGFS_SERIAL is not set
++# CONFIG_USB_CONFIGFS_ACM is not set
++# CONFIG_USB_CONFIGFS_OBEX is not set
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++# CONFIG_USB_CONFIGFS_RNDIS is not set
++# CONFIG_USB_CONFIGFS_EEM is not set
++# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++# CONFIG_USB_CONFIGFS_F_FS is not set
++# CONFIG_USB_CONFIGFS_F_HID is not set
++CONFIG_USB_CONFIGFS_F_UVC=y
++# CONFIG_USB_CONFIGFS_F_PRINTER is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_UWB is not set
++# CONFIG_MMC is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++CONFIG_RTC_DRV_HIBVT=y
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_SPEAR is not set
++# CONFIG_RTC_DRV_NUC900 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_ASM9260 is not set
++# CONFIG_RTC_DRV_DAVINCI is not set
++# CONFIG_RTC_DRV_DIGICOLOR is not set
++# CONFIG_RTC_DRV_OMAP is not set
++# CONFIG_RTC_DRV_S3C is not set
++# CONFIG_RTC_DRV_EP93XX is not set
++# CONFIG_RTC_DRV_VR41XX is not set
++# CONFIG_RTC_DRV_PL030 is not set
++# CONFIG_RTC_DRV_PL031 is not set
++# CONFIG_RTC_DRV_AT32AP700X is not set
++# CONFIG_RTC_DRV_AT91RM9200 is not set
++# CONFIG_RTC_DRV_AT91SAM9 is not set
++# CONFIG_RTC_DRV_GENERIC is not set
++# CONFIG_RTC_DRV_VT8500 is not set
++# CONFIG_RTC_DRV_SUNXI is not set
++# CONFIG_RTC_DRV_MV is not set
++# CONFIG_RTC_DRV_ARMADA38X is not set
++# CONFIG_RTC_DRV_GEMINI is not set
++# CONFIG_RTC_DRV_COH901331 is not set
++# CONFIG_RTC_DRV_STMP is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_LPC24XX is not set
++# CONFIG_RTC_DRV_LPC32XX is not set
++# CONFIG_RTC_DRV_PM8XXX is not set
++# CONFIG_RTC_DRV_TEGRA is not set
++# CONFIG_RTC_DRV_SNVS is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_MT6397 is not set
++# CONFIG_RTC_DRV_XGENE is not set
++
++#
++# HID Sensor RTC drivers
++#
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_DMADEVICES is not set
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++CONFIG_STAGING=y
++# CONFIG_COMEDI is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_R8712U is not set
++# CONFIG_RTS5208 is not set
++# CONFIG_FB_SM750 is not set
++# CONFIG_FB_XGI is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
++CONFIG_ION=y
++# CONFIG_ION_TEST is not set
++# CONFIG_ION_DUMMY is not set
++# CONFIG_ION_OF is not set
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_MTD_SPINAND_MT29F is not set
++# CONFIG_LNET is not set
++# CONFIG_DGNC is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_FSL_MC_BUS is not set
++# CONFIG_MOST is not set
++# CONFIG_GREYBUS is not set
++# CONFIG_GOLDFISH is not set
++# CONFIG_CHROME_PLATFORMS is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Common Clock Framework
++#
++# CONFIG_COMMON_CLK_VERSATILE is not set
++# CONFIG_COMMON_CLK_SCPI is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
++# CONFIG_CLK_QORIQ is not set
++# CONFIG_COMMON_CLK_XGENE is not set
++# CONFIG_COMMON_CLK_KEYSTONE is not set
++# CONFIG_COMMON_CLK_NXP is not set
++# CONFIG_COMMON_CLK_PXA is not set
++# CONFIG_COMMON_CLK_PIC32 is not set
++# CONFIG_COMMON_CLK_OXNAS is not set
++# CONFIG_CLK_BCM_63XX is not set
++# CONFIG_CLK_BCM_KONA is not set
++# CONFIG_COMMON_CLK_IPROC is not set
++# CONFIG_COMMON_CLK_HI3519 is not set
++# CONFIG_COMMON_CLK_HI3516A is not set
++# CONFIG_COMMON_CLK_HI3516CV500 is not set
++# CONFIG_COMMON_CLK_HI3516EV200 is not set
++# CONFIG_COMMON_CLK_HI3516EV300 is not set
++# CONFIG_COMMON_CLK_HI3518EV300 is not set
++# CONFIG_COMMON_CLK_HI3516DV200 is not set
++# CONFIG_COMMON_CLK_HI3516DV300 is not set
++# CONFIG_COMMON_CLK_HI3556V200 is not set
++# CONFIG_COMMON_CLK_HI3559V200 is not set
++# CONFIG_COMMON_CLK_HI3518EV20X is not set
++# CONFIG_COMMON_CLK_HI3536DV100 is not set
++CONFIG_COMMON_CLK_HI3569V100=y
++# CONFIG_COMMON_CLK_HI3521A is not set
++# CONFIG_COMMON_CLK_HI3531A is not set
++# CONFIG_COMMON_CLK_HI3556AV100 is not set
++# CONFIG_COMMON_CLK_HI3519AV100 is not set
++# CONFIG_COMMON_CLK_HI6220 is not set
++CONFIG_RESET_HISI=y
++# CONFIG_COMMON_CLK_MT8135 is not set
++# CONFIG_COMMON_CLK_MT8173 is not set
++# CONFIG_COMMON_CLK_QCOM is not set
++# CONFIG_COMMON_CLK_SAMSUNG is not set
++# CONFIG_S3C2410_COMMON_CLK is not set
++# CONFIG_S3C2412_COMMON_CLK is not set
++# CONFIG_S3C2443_COMMON_CLK is not set
++# CONFIG_SUNXI_CCU is not set
++# CONFIG_COMMON_CLK_TI_ADPLL is not set
++# CONFIG_CLK_UNIPHIER is not set
++
++#
++# Hardware Spinlock drivers
++#
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKSRC_OF=y
++CONFIG_CLKSRC_PROBE=y
++CONFIG_CLKSRC_MMIO=y
++# CONFIG_BCM2835_TIMER is not set
++# CONFIG_BCM_KONA_TIMER is not set
++# CONFIG_DIGICOLOR_TIMER is not set
++# CONFIG_DW_APB_TIMER is not set
++# CONFIG_ROCKCHIP_TIMER is not set
++# CONFIG_MESON6_TIMER is not set
++# CONFIG_SUN4I_TIMER is not set
++# CONFIG_SUN5I_HSTIMER is not set
++# CONFIG_VT8500_TIMER is not set
++# CONFIG_CADENCE_TTC_TIMER is not set
++# CONFIG_ASM9260_TIMER is not set
++# CONFIG_CLKSRC_DBX500_PRCMU is not set
++# CONFIG_CLPS711X_TIMER is not set
++# CONFIG_ATLAS7_TIMER is not set
++# CONFIG_MOXART_TIMER is not set
++# CONFIG_MXS_TIMER is not set
++# CONFIG_PRIMA2_TIMER is not set
++# CONFIG_NSPIRE_TIMER is not set
++# CONFIG_KEYSTONE_TIMER is not set
++# CONFIG_INTEGRATOR_AP_TIMER is not set
++# CONFIG_CLKSRC_PISTACHIO is not set
++# CONFIG_CLKSRC_TI_32K is not set
++# CONFIG_CLKSRC_MPS2 is not set
++CONFIG_ARM_ARCH_TIMER=y
++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
++CONFIG_FSL_ERRATUM_A008585=y
++CONFIG_ARM_TIMER_SP804=y
++# CONFIG_TIMER_HISP804 is not set
++# CONFIG_ARMV7M_SYSTICK is not set
++# CONFIG_ATMEL_PIT is not set
++# CONFIG_ATMEL_ST is not set
++# CONFIG_CLKSRC_EXYNOS_MCT is not set
++# CONFIG_CLKSRC_SAMSUNG_PWM is not set
++# CONFIG_FSL_FTM_TIMER is not set
++# CONFIG_OXNAS_RPS_TIMER is not set
++# CONFIG_MTK_TIMER is not set
++# CONFIG_CLKSRC_JCORE_PIT is not set
++# CONFIG_SH_TIMER_CMT is not set
++# CONFIG_SH_TIMER_MTU2 is not set
++# CONFIG_SH_TIMER_TMU is not set
++# CONFIG_EM_TIMER_STI is not set
++# CONFIG_CLKSRC_VERSATILE is not set
++# CONFIG_CLKSRC_PXA is not set
++# CONFIG_H8300_TMR8 is not set
++# CONFIG_H8300_TMR16 is not set
++# CONFIG_H8300_TPU is not set
++# CONFIG_CLKSRC_ST_LPC is not set
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++#
++# Rpmsg drivers
++#
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Broadcom SoC drivers
++#
++# CONFIG_MTK_INFRACFG is not set
++# CONFIG_MTK_SCPSYS is not set
++# CONFIG_ROCKCHIP_PM_DOMAINS is not set
++# CONFIG_SOC_SAMSUNG is not set
++# CONFIG_SUNXI_SRAM is not set
++# CONFIG_SOC_TI is not set
++# CONFIG_UX500_SOC_ID is not set
++CONFIG_PM_DEVFREQ=y
++
++#
++# DEVFREQ Governors
++#
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
++# CONFIG_DEVFREQ_GOV_USERSPACE is not set
++# CONFIG_DEVFREQ_GOV_PASSIVE is not set
++
++#
++# DEVFREQ Drivers
++#
++# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
++# CONFIG_PM_DEVFREQ_EVENT is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARM_GIC_MAX_NR=1
++CONFIG_ARM_GIC_V2M=y
++CONFIG_ARM_GIC_V3=y
++CONFIG_ARM_GIC_V3_ITS=y
++CONFIG_HISILICON_IRQ_MBIGEN=y
++# CONFIG_JCORE_AIC is not set
++# CONFIG_TS4800_IRQ is not set
++CONFIG_PARTITION_PERCPU=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_RESET_ATH79 is not set
++# CONFIG_RESET_BERLIN is not set
++# CONFIG_RESET_LPC18XX is not set
++# CONFIG_RESET_MESON is not set
++# CONFIG_RESET_PISTACHIO is not set
++# CONFIG_RESET_SOCFPGA is not set
++# CONFIG_RESET_STM32 is not set
++# CONFIG_RESET_SUNXI is not set
++# CONFIG_TI_SYSCON_RESET is not set
++# CONFIG_RESET_UNIPHIER is not set
++# CONFIG_RESET_ZYNQ is not set
++CONFIG_COMMON_RESET_HI6220=y
++# CONFIG_FMC is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_PHY_BCM_NS_USB2 is not set
++# CONFIG_PHY_BCM_NS_USB3 is not set
++CONFIG_ARMADA375_USBCLUSTER_PHY=y
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_LPC18XX_USB_OTG is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_OMAP_CONTROL_PHY is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_HI6220_USB is not set
++# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
++# CONFIG_PHY_ROCKCHIP_PCIE is not set
++# CONFIG_PHY_ROCKCHIP_TYPEC is not set
++# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
++# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
++# CONFIG_PHY_XGENE is not set
++# CONFIG_PHY_STIH407_USB is not set
++# CONFIG_PHY_BRCM_SATA is not set
++# CONFIG_PHY_CYGNUS_PCIE is not set
++# CONFIG_PHY_HISI_USB2 is not set
++CONFIG_PHY_HISI_USB3=y
++# CONFIG_PHY_HISI_XVP_USB2 is not set
++CONFIG_USB_MODE_OPTION=y
++# CONFIG_USB_DRD0_IN_HOST is not set
++CONFIG_USB_DRD0_IN_DEVICE=y
++CONFIG_USB_DRD1_IN_HOST=y
++# CONFIG_USB_DRD1_IN_DEVICE is not set
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# CONFIG_RAS is not set
++# CONFIG_THUNDERBOLT is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++# CONFIG_ANDROID_BINDER_IPC is not set
++# CONFIG_LIBNVDIMM is not set
++# CONFIG_NVMEM is not set
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++
++#
++# FPGA Configuration Support
++#
++# CONFIG_FPGA is not set
++# CONFIG_HI_DMAC is not set
++# CONFIG_HIEDMAC is not set
++
++#
++# Hisilicon driver support
++#
++# CONFIG_CMA_MEM_SHARED is not set
++# CONFIG_CMA_ADVANCE_SHARE is not set
++
++#
++# Firmware Drivers
++#
++CONFIG_ARM_PSCI_FW=y
++CONFIG_ARM_SCPI_POWER_DOMAIN=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_HAVE_ARM_SMCCC=y
++# CONFIG_MESON_SM is not set
++# CONFIG_ACPI is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_FS_IOMAP=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_ENCRYPTION is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_CHECK=y
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_JFS_DEBUG=y
++CONFIG_JFS_STATISTICS=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_RT=y
++# CONFIG_XFS_WARN is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=m
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QUOTA_DEBUG is not set
++CONFIG_QUOTA_TREE=m
++CONFIG_QFMT_V1=m
++CONFIG_QFMT_V2=m
++CONFIG_QUOTACTL=y
++CONFIG_AUTOFS4_FS=m
++CONFIG_FUSE_FS=y
++# CONFIG_CUSE is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++CONFIG_UDF_FS=y
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_HUGETLBFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
++# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
++# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set
++CONFIG_YAFFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++# CONFIG_JFFS2_LZMA is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_ATIME_SUPPORT is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_CACHE=y
++# CONFIG_SQUASHFS_FILE_DIRECT is not set
++CONFIG_SQUASHFS_DECOMP_SINGLE=y
++# CONFIG_SQUASHFS_DECOMP_MULTI is not set
++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
++# CONFIG_SQUASHFS_XATTR is not set
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_LZ4 is not set
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=y
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_VIRTUALIZATION is not set
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++
++#
++# Compile-time checks and compiler options
++#
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_PAGE_OWNER is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++CONFIG_ARCH_WANT_FRAME_POINTERS=y
++CONFIG_FRAME_POINTER=y
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_DEBUG_KERNEL=y
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_ARCH_KASAN=y
++# CONFIG_KASAN is not set
++CONFIG_ARCH_HAS_KCOV=y
++# CONFIG_KCOV is not set
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Lockups and Hangs
++#
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++# CONFIG_WQ_WATCHDOG is not set
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_PANIC_ON_OOPS_VALUE=1
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHED_INFO=y
++CONFIG_SCHEDSTATS=y
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_TIMER_STATS is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_HAVE_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PI_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_PROVE_RCU is not set
++CONFIG_SPARSE_RCU_POINTER=y
++# CONFIG_TORTURE_TEST is not set
++# CONFIG_RCU_PERF_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++CONFIG_RCU_TRACE=y
++# CONFIG_RCU_EQS_DEBUG is not set
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACE_CLOCK=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++
++#
++# Runtime Testing
++#
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_MEMTEST is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
++# CONFIG_UBSAN is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++CONFIG_STRICT_DEVMEM=y
++# CONFIG_IO_STRICT_DEVMEM is not set
++# CONFIG_ARM64_PTDUMP is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
++# CONFIG_DEBUG_SET_MODULE_RONX is not set
++# CONFIG_DEBUG_ALIGN_RODATA is not set
++# CONFIG_CORESIGHT is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
++# CONFIG_HARDENED_USERCOPY is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=m
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_KPP2=y
++# CONFIG_CRYPTO_RSA is not set
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_MCRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++CONFIG_CRYPTO_CTR=m
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_CRCT10DIF is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=m
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=m
++CONFIG_CRYPTO_JITTERENTROPY=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_S5P is not set
++# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
++# CONFIG_CRYPTO_DEV_CCP is not set
++# CONFIG_CRYPTO_DEV_QCE is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_HISI_OTP is not set
++# CONFIG_CRYPTO_DEV_HISI_CIPHER is not set
++
++#
++# Certificates for signature checking
++#
++# CONFIG_ARM64_CRYPTO is not set
++# CONFIG_ARM64_HISI_LIB is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_HAVE_ARCH_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=m
++# CONFIG_CRC8 is not set
++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++CONFIG_XZ_DEC_POWERPC=y
++CONFIG_XZ_DEC_IA64=y
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++CONFIG_XZ_DEC_SPARC=y
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
++# CONFIG_IRQ_POLL is not set
++CONFIG_LIBFDT=y
++# CONFIG_SG_SPLIT is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_SG_CHAIN=y
++CONFIG_SBITMAP=y
diff --git a/arch/arm64/hisi-lib/Kconfig b/arch/arm64/hisi-lib/Kconfig
new file mode 100644
index 0000000..50855f6
@@ -183494,7 +251484,7 @@ index 0000000..e425d1c
+
diff --git a/arch/arm64/hisi-lib/sample_c.c b/arch/arm64/hisi-lib/sample_c.c
new file mode 100644
-index 0000000..bbb74b6
+index 0000000..a516def
--- /dev/null
+++ b/arch/arm64/hisi-lib/sample_c.c
@@ -0,0 +1,11 @@
@@ -183504,9 +251494,9 @@ index 0000000..bbb74b6
+extern void float_test(long long s64input, long long *ps64output);
+void floatTest(long long s64input, long long *ps64output)
+{
-+ kernel_neon_begin();
-+ float_test(s64input, ps64output);
-+ kernel_neon_end();
++ kernel_neon_begin();
++ float_test(s64input, ps64output);
++ kernel_neon_end();
+}
+EXPORT_SYMBOL_GPL(floatTest);
diff --git a/arch/arm64/hisi-lib/sample_s.S b/arch/arm64/hisi-lib/sample_s.S
@@ -183933,7 +251923,7 @@ index 26a68dd..ef7e683 100644
diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h
new file mode 100644
-index 0000000..59e66d7
+index 0000000..2d1f4ce
--- /dev/null
+++ b/arch/arm64/include/asm/daifflags.h
@@ -0,0 +1,72 @@
@@ -183964,10 +251954,10 @@ index 0000000..59e66d7
+static inline void local_daif_mask(void)
+{
+ asm volatile(
-+ "msr daifset, #0xf // local_daif_mask\n"
-+ :
-+ :
-+ : "memory");
++ "msr daifset, #0xf // local_daif_mask\n"
++ :
++ :
++ : "memory");
+ trace_hardirqs_off();
+}
+
@@ -183976,10 +251966,10 @@ index 0000000..59e66d7
+ unsigned long flags;
+
+ asm volatile(
-+ "mrs %0, daif // local_daif_save\n"
-+ : "=r" (flags)
-+ :
-+ : "memory");
++ "mrs %0, daif // local_daif_save\n"
++ : "=r" (flags)
++ :
++ : "memory");
+ local_daif_mask();
+
+ return flags;
@@ -183989,10 +251979,10 @@ index 0000000..59e66d7
+{
+ trace_hardirqs_on();
+ asm volatile(
-+ "msr daifclr, #0xf // local_daif_unmask"
-+ :
-+ :
-+ : "memory");
++ "msr daifclr, #0xf // local_daif_unmask"
++ :
++ :
++ : "memory");
+}
+
+static inline void local_daif_restore(unsigned long flags)
@@ -184000,10 +251990,10 @@ index 0000000..59e66d7
+ if (!arch_irqs_disabled_flags(flags))
+ trace_hardirqs_on();
+ asm volatile(
-+ "msr daif, %0 // local_daif_restore"
-+ :
-+ : "r" (flags)
-+ : "memory");
++ "msr daif, %0 // local_daif_restore"
++ :
++ : "r" (flags)
++ : "memory");
+ if (arch_irqs_disabled_flags(flags))
+ trace_hardirqs_off();
+}
@@ -185452,7 +253442,7 @@ index 0000000..20ef1f0
+#endif /* End of __HI_CHIP_REGS_H__ */
diff --git a/arch/arm64/include/mach/platform.h b/arch/arm64/include/mach/platform.h
new file mode 100644
-index 0000000..a7e457d
+index 0000000..7cd8dd2
--- /dev/null
+++ b/arch/arm64/include/mach/platform.h
@@ -0,0 +1,25 @@
@@ -185476,7 +253466,7 @@ index 0000000..a7e457d
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
-+#ifdef CONFIG_ARCH_HI3559AV100
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+#include "platform-hi3559av100.h"
+#endif
+
@@ -189450,7 +257440,7 @@ index 62a04c8..42938b4 100644
&ahci_platform_sht);
diff --git a/drivers/ata/hisi_sata_dbg.c b/drivers/ata/hisi_sata_dbg.c
new file mode 100644
-index 0000000..1d55650
+index 0000000..ee4265b
--- /dev/null
+++ b/drivers/ata/hisi_sata_dbg.c
@@ -0,0 +1,178 @@
@@ -189481,154 +257471,154 @@ index 0000000..1d55650
+
+void hisi_sata_mem_dump(unsigned int *addr, unsigned int size)
+{
-+ int ix;
++ int ix;
+
-+ for (ix = 0; ix < size; ix += 0x04, addr++) {
-+ if (!(ix & 0x0F)) {
-+ pr_debug("\n0x%08X: ",
-+ (unsigned int)virt_to_phys(addr));
-+ }
-+ pr_debug("%08X ", *addr);
-+ }
++ for (ix = 0; ix < size; ix += 0x04, addr++) {
++ if (!(ix & 0x0F)) {
++ pr_debug("\n0x%08X: ",
++ (unsigned int)virt_to_phys(addr));
++ }
++ pr_debug("%08X ", *addr);
++ }
+}
+EXPORT_SYMBOL(hisi_sata_mem_dump);
+
+void hisi_sata_phys_mem_dump(unsigned int addr, unsigned int size)
+{
-+ hisi_sata_mem_dump(phys_to_virt(addr), size);
++ hisi_sata_mem_dump(phys_to_virt(addr), size);
+}
+EXPORT_SYMBOL(hisi_sata_phys_mem_dump);
+
+void hisi_ahci_reg_dump(void)
+{
-+ int ix;
-+ unsigned int regbase;
++ int ix;
++ unsigned int regbase;
+
-+ regbase = CONFIG_HISI_SATA_IOBASE;
-+ pr_debug("AHCI GHC Register dump:");
-+ for (ix = 0; ix <= 0x28; ix += 0x04) {
-+ if (!(ix & 0x0F)) {
-+ pr_debug("\n0x%08X: ", (regbase + ix));
-+ }
-+ pr_debug("%08X ", readl(__io_address(regbase + ix)));
-+ }
-+ pr_debug("\n");
++ regbase = CONFIG_HISI_SATA_IOBASE;
++ pr_debug("AHCI GHC Register dump:");
++ for (ix = 0; ix <= 0x28; ix += 0x04) {
++ if (!(ix & 0x0F)) {
++ pr_debug("\n0x%08X: ", (regbase + ix));
++ }
++ pr_debug("%08X ", readl(__io_address(regbase + ix)));
++ }
++ pr_debug("\n");
+
-+ regbase = CONFIG_HISI_SATA_IOBASE + 0x0100;
-+ pr_debug("AHCI PORT 0 Register dump:");
-+ for (ix = 0; ix <= 0x7F; ix += 0x04) {
-+ if (!(ix & 0x0F)) {
-+ pr_debug("\n0x%08X: ", (regbase + ix));
-+ }
-+ pr_debug("%08X ", readl(__io_address(regbase + ix)));
-+ }
-+ pr_debug("\n");
++ regbase = CONFIG_HISI_SATA_IOBASE + 0x0100;
++ pr_debug("AHCI PORT 0 Register dump:");
++ for (ix = 0; ix <= 0x7F; ix += 0x04) {
++ if (!(ix & 0x0F)) {
++ pr_debug("\n0x%08X: ", (regbase + ix));
++ }
++ pr_debug("%08X ", readl(__io_address(regbase + ix)));
++ }
++ pr_debug("\n");
+}
+EXPORT_SYMBOL(hisi_ahci_reg_dump);
+
+void hisi_ahci_rx_fis_dump(struct ata_link *link, int pmp_port_num)
+{
-+ struct ahci_port_priv *pp = NULL;
++ struct ahci_port_priv *pp = NULL;
+
-+ pp = link->ap->private_data;
-+ if (NULL == pp) {
-+ pr_debug("Error: pp=NULL\n");
-+ return;
-+ }
-+ pr_debug("ACHI Received FIS:");
-+ hisi_sata_phys_mem_dump((unsigned int)(pp->rx_fis_dma),
-+ AHCI_RX_FIS_SZ * pmp_port_num);
-+ pr_debug("\n");
++ pp = link->ap->private_data;
++ if (NULL == pp) {
++ pr_debug("Error: pp=NULL\n");
++ return;
++ }
++ pr_debug("ACHI Received FIS:");
++ hisi_sata_phys_mem_dump((unsigned int)(pp->rx_fis_dma),
++ AHCI_RX_FIS_SZ * pmp_port_num);
++ pr_debug("\n");
+}
+EXPORT_SYMBOL_GPL(hisi_ahci_rx_fis_dump);
+
+void hisi_ata_taskfile_dump(struct ata_taskfile *tf)
+{
-+ if (NULL == tf) {
-+ pr_debug("Error: tf=NULL\n");
-+ return;
-+ }
++ if (NULL == tf) {
++ pr_debug("Error: tf=NULL\n");
++ return;
++ }
+
-+ pr_debug("Taskfile dump:\n");
-+ pr_debug("flags:0x%08lX, protocol:0x%02X, command:0x%02X, device:0x%02X, ctl:0x%02X\n",
-+ tf->flags, tf->protocol, tf->command, tf->device, tf->ctl);
-+ pr_debug("feature:0x%08X, nsect:0x%02X, lbal:0x%02X, lbam:0x%02X, lbah:0x%02X\n",
-+ tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
-+ pr_debug("hob_feature:0x%08X, hob_nsect:0x%02X, hob_lbal:0x%02X, hob_lbam:0x%02X, hob_lbah:0x%02X\n",
-+ tf->hob_feature, tf->hob_nsect, tf->hob_lbal,
-+ tf->hob_lbam, tf->hob_lbah);
++ pr_debug("Taskfile dump:\n");
++ pr_debug("flags:0x%08lX, protocol:0x%02X, command:0x%02X, device:0x%02X, ctl:0x%02X\n",
++ tf->flags, tf->protocol, tf->command, tf->device, tf->ctl);
++ pr_debug("feature:0x%08X, nsect:0x%02X, lbal:0x%02X, lbam:0x%02X, lbah:0x%02X\n",
++ tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
++ pr_debug("hob_feature:0x%08X, hob_nsect:0x%02X, hob_lbal:0x%02X, hob_lbam:0x%02X, hob_lbah:0x%02X\n",
++ tf->hob_feature, tf->hob_nsect, tf->hob_lbal,
++ tf->hob_lbam, tf->hob_lbah);
+}
+EXPORT_SYMBOL_GPL(hisi_ata_taskfile_dump);
+
+static void __hisi_ahci_st_md(void __iomem *addr)
+{
-+ unsigned int *addr_v;
-+ unsigned int *tmp;
-+ unsigned int i;
++ unsigned int *addr_v;
++ unsigned int *tmp = NULL;
++ unsigned int i;
+
-+ addr_v = (unsigned int *)addr;
++ addr_v = (unsigned int *)addr;
+
-+ pr_debug("\n\n");
-+ for (i = 0; i < 16; i++) {
-+ tmp = addr_v + i * 4;
-+ pr_debug("%8x: %8x %8x %8x %8x\n",
-+ (unsigned int)(addr + i * 16),
-+ *tmp, *(tmp + 1), *(tmp + 2), *(tmp + 3));
-+ }
++ pr_debug("\n\n");
++ for (i = 0; i < 16; i++) {
++ tmp = addr_v + i * 4;
++ pr_debug("%8x: %8x %8x %8x %8x\n",
++ (unsigned int)(addr + i * 16),
++ *tmp, *(tmp + 1), *(tmp + 2), *(tmp + 3));
++ }
+
-+ pr_debug("\n");
++ pr_debug("\n");
+}
+
+void hisi_ahci_st_dump(void __iomem *port_base)
+{
-+ unsigned int tmp;
++ unsigned int tmp;
+
-+ pr_debug("\n**********Dmac status**********\n");
-+ tmp = readl(port_base + 0x58);
-+ pr_debug("txdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
-+ tmp = readl(port_base + 0x64);
-+ pr_debug("rxdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
-+ tmp = readl(port_base + 0x70);
-+ pr_debug("dmac tx fifo:count-0x%x-empty-%x-ful-%x\n",
-+ (tmp >> 0) & 0xff,
-+ (tmp >> 16) & 0x1, (tmp >> 17) & 0x1);
-+ pr_debug("dmac rx fifo:count-0x%x-empty-%x-ful-%x\n",
-+ (tmp >> 8) & 0xff,
-+ (tmp >> 18) & 0x1, (tmp >> 19) & 0x1);
++ pr_debug("\n**********Dmac status**********\n");
++ tmp = readl(port_base + 0x58);
++ pr_debug("txdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
++ tmp = readl(port_base + 0x64);
++ pr_debug("rxdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
++ tmp = readl(port_base + 0x70);
++ pr_debug("dmac tx fifo:count-0x%x-empty-%x-ful-%x\n",
++ (tmp >> 0) & 0xff,
++ (tmp >> 16) & 0x1, (tmp >> 17) & 0x1);
++ pr_debug("dmac rx fifo:count-0x%x-empty-%x-ful-%x\n",
++ (tmp >> 8) & 0xff,
++ (tmp >> 18) & 0x1, (tmp >> 19) & 0x1);
+
-+ pr_debug("\n");
-+ pr_debug("**********HBA status**********\n");
-+ tmp = readl(port_base + 0x50);
-+ pr_debug("pxxx_curr_st:0x%2x ndrx_curr_st:0x%2x\n",
-+ (tmp >> 24) & 0xf,
-+ (tmp >> 16) & 0xff);
-+ pr_debug("cfis_curr_st:0x%2x piox_curr_st:0x%2x\n",
-+ (tmp >> 12) & 0xf,
-+ (tmp >> 8) & 0xf);
-+ pr_debug("pmxx_curr_st:0x%2x errx_curr_st:0x%2x\n",
-+ (tmp >> 4) & 0xf,
-+ (tmp >> 0) & 0xf);
++ pr_debug("\n");
++ pr_debug("**********HBA status**********\n");
++ tmp = readl(port_base + 0x50);
++ pr_debug("pxxx_curr_st:0x%2x ndrx_curr_st:0x%2x\n",
++ (tmp >> 24) & 0xf,
++ (tmp >> 16) & 0xff);
++ pr_debug("cfis_curr_st:0x%2x piox_curr_st:0x%2x\n",
++ (tmp >> 12) & 0xf,
++ (tmp >> 8) & 0xf);
++ pr_debug("pmxx_curr_st:0x%2x errx_curr_st:0x%2x\n",
++ (tmp >> 4) & 0xf,
++ (tmp >> 0) & 0xf);
+
-+ pr_debug("\n");
-+ pr_debug("**********Link status**********\n");
-+ tmp = readl(port_base + 0x54);
-+ pr_debug("link_curr_st:0x%2x\n", (tmp >> 24) & 0x1f);
-+ pr_debug("link tx fifo:count-0x%x-empty-%x-ful-%x\n",
-+ (tmp >> 0) & 0x1f,
-+ (tmp >> 5) & 0x1, (tmp >> 6) & 0x1);
-+ pr_debug("link rx fifo:count-0x%x-empty-%x-ful-%x\n",
-+ (tmp >> 8) & 0x1f,
-+ (tmp >> 13) & 0x1, (tmp >> 14) & 0x1);
-+ pr_debug("link df fifo:count-0x%x-empty-%x-ful-%x\n\n",
-+ (tmp >> 16) & 0x1f,
-+ (tmp >> 21) & 0x1, (tmp >> 22) & 0x1);
++ pr_debug("\n");
++ pr_debug("**********Link status**********\n");
++ tmp = readl(port_base + 0x54);
++ pr_debug("link_curr_st:0x%2x\n", (tmp >> 24) & 0x1f);
++ pr_debug("link tx fifo:count-0x%x-empty-%x-ful-%x\n",
++ (tmp >> 0) & 0x1f,
++ (tmp >> 5) & 0x1, (tmp >> 6) & 0x1);
++ pr_debug("link rx fifo:count-0x%x-empty-%x-ful-%x\n",
++ (tmp >> 8) & 0x1f,
++ (tmp >> 13) & 0x1, (tmp >> 14) & 0x1);
++ pr_debug("link df fifo:count-0x%x-empty-%x-ful-%x\n\n",
++ (tmp >> 16) & 0x1f,
++ (tmp >> 21) & 0x1, (tmp >> 22) & 0x1);
+
-+ pr_debug("**********CMD header**********\n");
-+ tmp = readl(port_base + 0x0);
-+ __hisi_ahci_st_md(phys_to_virt(tmp));
-+ __hisi_ahci_st_md(phys_to_virt(tmp + 0x100));
-+ __hisi_ahci_st_md(phys_to_virt(tmp + 0x200));
-+ __hisi_ahci_st_md(phys_to_virt(tmp + 0x300));
++ pr_debug("**********CMD header**********\n");
++ tmp = readl(port_base + 0x0);
++ __hisi_ahci_st_md(phys_to_virt(tmp));
++ __hisi_ahci_st_md(phys_to_virt(tmp + 0x100));
++ __hisi_ahci_st_md(phys_to_virt(tmp + 0x200));
++ __hisi_ahci_st_md(phys_to_virt(tmp + 0x300));
+}
+EXPORT_SYMBOL_GPL(hisi_ahci_st_dump);
+
@@ -190603,10 +258593,10 @@ index 727ed8e..719cf6f 100644
}
CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
-index 3f537a0..64a162d 100644
+index 3f537a0..67dcee3 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
-@@ -6,6 +6,134 @@ config COMMON_CLK_HI3519
+@@ -6,6 +6,158 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
@@ -190682,6 +258672,22 @@ index 3f537a0..64a162d 100644
+ help
+ Build the clock driver for hi3559V200.
+
++config COMMON_CLK_HI3562V100
++ tristate "Hi3562V100 Clock Driver"
++ depends on ARCH_HI3562V100 || COMPILE_TEST
++ select RESET_HISI
++ default ARCH_HISI_BVT
++ help
++ Build the clock driver for hi3562V100.
++
++config COMMON_CLK_HI3566V100
++ tristate "Hi3566V100 Clock Driver"
++ depends on ARCH_HI3566V100 || COMPILE_TEST
++ select RESET_HISI
++ default ARCH_HISI_BVT
++ help
++ Build the clock driver for hi3566V100.
++
+config COMMON_CLK_HI3518EV20X
+ tristate "Hi3518EV20X Clock Driver"
+ depends on ARCH_HI3518EV20X || COMPILE_TEST
@@ -190706,6 +258712,14 @@ index 3f537a0..64a162d 100644
+ help
+ Build the clock driver for hi3559av100.
+
++config COMMON_CLK_HI3569V100
++ tristate "Hi3569V100 Clock Driver"
++ depends on ARCH_Hi3569V100 || COMPILE_TEST
++ select RESET_HISI
++ default ARCH_HISI
++ help
++ Build the clock driver for hi3569v100.
++
+config COMMON_CLK_HI3521A
+ tristate "Hi3521A Clock Driver"
+ depends on ARCH_HI3521A || COMPILE_TEST
@@ -190741,7 +258755,7 @@ index 3f537a0..64a162d 100644
config COMMON_CLK_HI6220
bool "Hi6220 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
-@@ -15,7 +143,7 @@ config COMMON_CLK_HI6220
+@@ -15,7 +167,7 @@ config COMMON_CLK_HI6220
config RESET_HISI
bool "HiSilicon Reset Controller Driver"
@@ -190751,10 +258765,10 @@ index 3f537a0..64a162d 100644
help
Build reset controller driver for HiSilicon device chipsets.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
-index e169ec7..95fd27c 100644
+index e169ec7..a394173 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
-@@ -8,6 +8,22 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
+@@ -8,6 +8,25 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
@@ -190763,6 +258777,8 @@ index e169ec7..95fd27c 100644
+obj-$(CONFIG_COMMON_CLK_HI3516DV300) += clk-hi3516dv300.o
+obj-$(CONFIG_COMMON_CLK_HI3556V200) += clk-hi3556v200.o
+obj-$(CONFIG_COMMON_CLK_HI3559V200) += clk-hi3559v200.o
++obj-$(CONFIG_COMMON_CLK_HI3562V100) += clk-hi3559v200.o
++obj-$(CONFIG_COMMON_CLK_HI3566V100) += clk-hi3559v200.o
+obj-$(CONFIG_COMMON_CLK_HI3518EV20X) += clk-hi3518ev20x.o
+obj-$(CONFIG_COMMON_CLK_HI3536DV100) += clk-hi3536dv100.o
+obj-$(CONFIG_COMMON_CLK_HI3521A) += clk-hi3521a.o
@@ -190775,14 +258791,15 @@ index e169ec7..95fd27c 100644
+obj-$(CONFIG_COMMON_CLK_HI3516DV200) += clk-hi3516dv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
+obj-$(CONFIG_COMMON_CLK_HI3559AV100) += clk-hi3559av100.o
++obj-$(CONFIG_COMMON_CLK_HI3569V100) += clk-hi3559av100.o
obj-$(CONFIG_RESET_HISI) += reset.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
diff --git a/drivers/clk/hisilicon/clk-hi3516a.c b/drivers/clk/hisilicon/clk-hi3516a.c
new file mode 100644
-index 0000000..22f4fc1
+index 0000000..91a86fb
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3516a.c
-@@ -0,0 +1,463 @@
+@@ -0,0 +1,525 @@
+/*
+ * Hi3516A Clock Driver
+ *
@@ -190850,7 +258867,7 @@ index 0000000..22f4fc1
+};
+
+static const struct
-+hisi_fixed_rate_clock hi3516a_fixed_rate_clks_crg[] __initconst = {
++ hisi_fixed_rate_clock hi3516a_fixed_rate_clks_crg[] __initconst = {
+ { HI3516A_FIXED_3M, "3m", NULL, 0, 3000000, },
+ { HI3516A_FIXED_6M, "6m", NULL, 0, 6000000, },
+ { HI3516A_FIXED_13P5M, "13.5m", NULL, 0, 13500000, },
@@ -190907,91 +258924,145 @@ index 0000000..22f4fc1
+static u32 mmc_mux_table[] __initdata = {0, 1, 2, 3};
+
+static const struct hisi_mux_clock hi3516a_mux_clks_crg[] __initconst = {
-+ { HI3516A_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3516A_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x30, 3, 1, 0, sysaxi_mux_table, },
-+ { HI3516A_SNOR_MUX, "snor_mux", snor_mux_p, ARRAY_SIZE(snor_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, snor_mux_table, },
-+ { HI3516A_SNAND_MUX, "snand_mux", snand_mux_p, ARRAY_SIZE(snand_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc0, 6, 2, 0, snand_mux_table, },
-+ { HI3516A_NAND_MUX, "nand_mux", nand_mux_p, ARRAY_SIZE(nand_mux_p),
-+ CLK_SET_RATE_PARENT, 0xd0, 2, 1, 0, nand_mux_table, },
-+ { HI3516A_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc4, 2, 2, 0, mmc_mux_table, },
-+ { HI3516A_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc4, 10, 2, 0, mmc_mux_table, },
-+ { HI3516A_UART_MUX, "uart_mux", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x30, 3, 1, 0, sysaxi_mux_table,
++ },
++ {
++ HI3516A_SNOR_MUX, "snor_mux", snor_mux_p, ARRAY_SIZE(snor_mux_p),
++ CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, snor_mux_table,
++ },
++ {
++ HI3516A_SNAND_MUX, "snand_mux", snand_mux_p, ARRAY_SIZE(snand_mux_p),
++ CLK_SET_RATE_PARENT, 0xc0, 6, 2, 0, snand_mux_table,
++ },
++ {
++ HI3516A_NAND_MUX, "nand_mux", nand_mux_p, ARRAY_SIZE(nand_mux_p),
++ CLK_SET_RATE_PARENT, 0xd0, 2, 1, 0, nand_mux_table,
++ },
++ {
++ HI3516A_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0xc4, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516A_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0xc4, 10, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516A_UART_MUX, "uart_mux", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
-+ { HI3516A_ETH_PHY_MUX, "eth_phy_mux", eth_phy_mux_p,
++ CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516A_ETH_PHY_MUX, "eth_phy_mux", eth_phy_mux_p,
+ ARRAY_SIZE(eth_phy_mux_p), CLK_SET_RATE_PARENT,
-+ 0xcc, 6, 1, 0, eth_phy_mux_table, },
-+ { HI3516A_A7_MUX, "a7_mux", a7_mux_p, ARRAY_SIZE(a7_mux_p),
-+ CLK_SET_RATE_PARENT, 0x30, 8, 2, 0, a7_mux_table, },
++ 0xcc, 6, 1, 0, eth_phy_mux_table,
++ },
++ {
++ HI3516A_A7_MUX, "a7_mux", a7_mux_p, ARRAY_SIZE(a7_mux_p),
++ CLK_SET_RATE_PARENT, 0x30, 8, 2, 0, a7_mux_table,
++ },
+};
+
+/* fixed factor clocks */
+static struct hisi_fixed_factor_clock
-+ hi3516a_fixed_factor_clks[] __initdata = {
-+ { HI3516A_SYSAXI_CLK, "clk_sysapb", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT, },
++ hi3516a_fixed_factor_clks[] __initdata = {
++ {
++ HI3516A_SYSAXI_CLK, "clk_sysapb", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT,
++ },
+};
+
+static const struct hisi_gate_clock hi3516a_gate_clks[] __initconst = {
+ /* spi nor */
-+ { HI3516A_SNOR_CLK, "clk_snor", "snor_mux",
-+ CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
++ {
++ HI3516A_SNOR_CLK, "clk_snor", "snor_mux",
++ CLK_SET_RATE_PARENT, 0xc0, 1, 0,
++ },
+ /* spi nand */
-+ { HI3516A_SNAND_CLK, "clk_snand", "snand_mux",
-+ CLK_SET_RATE_PARENT, 0xc0, 5, 0, },
++ {
++ HI3516A_SNAND_CLK, "clk_snand", "snand_mux",
++ CLK_SET_RATE_PARENT, 0xc0, 5, 0,
++ },
+ /* nand */
-+ { HI3516A_NAND_CLK, "clk_nand", "nand_mux",
-+ CLK_SET_RATE_PARENT, 0xd8, 1, 0, },
++ {
++ HI3516A_NAND_CLK, "clk_nand", "nand_mux",
++ CLK_SET_RATE_PARENT, 0xd8, 1, 0,
++ },
+ /* mmc */
-+ { HI3516A_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0xc4, 1, 0, },
-+ { HI3516A_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0xc4, 9, 0, },
++ {
++ HI3516A_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0xc4, 1, 0,
++ },
++ {
++ HI3516A_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0xc4, 9, 0,
++ },
+
+ /* usb ctrl */
-+ { HI3516A_USB2_CTRL_UTMI0_REQ, "usb2_cttl_utmi0_req", NULL,
-+ CLK_SET_RATE_PARENT, 0xb4, 5, 1, },
-+ { HI3516A_USB2_HRST_REQ, "usb2_hrst_req", NULL,
-+ CLK_SET_RATE_PARENT, 0xb4, 0, 1, },
++ {
++ HI3516A_USB2_CTRL_UTMI0_REQ, "usb2_cttl_utmi0_req", NULL,
++ CLK_SET_RATE_PARENT, 0xb4, 5, 1,
++ },
++ {
++ HI3516A_USB2_HRST_REQ, "usb2_hrst_req", NULL,
++ CLK_SET_RATE_PARENT, 0xb4, 0, 1,
++ },
+
+ /* uart */
-+ { HI3516A_UART0_CLK, "clk_uart0", "50m",
-+ CLK_SET_RATE_PARENT, 0xe4, 15, 0, },
-+ { HI3516A_UART1_CLK, "clk_uart1", "50m",
-+ CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
-+ { HI3516A_UART2_CLK, "clk_uart2", "50m",
-+ CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
-+ { HI3516A_UART3_CLK, "clk_uart3", "50m",
-+ CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
++ {
++ HI3516A_UART0_CLK, "clk_uart0", "50m",
++ CLK_SET_RATE_PARENT, 0xe4, 15, 0,
++ },
++ {
++ HI3516A_UART1_CLK, "clk_uart1", "50m",
++ CLK_SET_RATE_PARENT, 0xe4, 16, 0,
++ },
++ {
++ HI3516A_UART2_CLK, "clk_uart2", "50m",
++ CLK_SET_RATE_PARENT, 0xe4, 17, 0,
++ },
++ {
++ HI3516A_UART3_CLK, "clk_uart3", "50m",
++ CLK_SET_RATE_PARENT, 0xe4, 18, 0,
++ },
+ /* ethernet mac */
-+ { HI3516A_ETH_CLK, "clk_eth", NULL,
-+ CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
-+ { HI3516A_ETH_MACIF_CLK, "clk_eth_macif", NULL,
-+ CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
++ {
++ HI3516A_ETH_CLK, "clk_eth", NULL,
++ CLK_SET_RATE_PARENT, 0xcc, 1, 0,
++ },
++ {
++ HI3516A_ETH_MACIF_CLK, "clk_eth_macif", NULL,
++ CLK_SET_RATE_PARENT, 0xcc, 3, 0,
++ },
+ /* spi */
-+ { HI3516A_SPI0_CLK, "clk_spi0", "clk_sysapb",
-+ CLK_SET_RATE_PARENT, 0xe4, 13, 0, },
-+ { HI3516A_SPI1_CLK, "clk_spi1", "clk_sysapb",
-+ CLK_SET_RATE_PARENT, 0xe4, 14, 0, },
++ {
++ HI3516A_SPI0_CLK, "clk_spi0", "clk_sysapb",
++ CLK_SET_RATE_PARENT, 0xe4, 13, 0,
++ },
++ {
++ HI3516A_SPI1_CLK, "clk_spi1", "clk_sysapb",
++ CLK_SET_RATE_PARENT, 0xe4, 14, 0,
++ },
+ /* dmac */
-+ { HI3516A_DMAC_CLK, "clk_dmac", "50m",
-+ CLK_SET_RATE_PARENT, 0xd8, 5, 0, },
++ {
++ HI3516A_DMAC_CLK, "clk_dmac", "50m",
++ CLK_SET_RATE_PARENT, 0xd8, 5, 0,
++ },
+};
+
+static struct hi3516a_pll_clock hi3516a_pll_clks[] __initdata = {
-+ { HI3516A_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
-+ 0x4, 0, 12, 12, 6},
++ {
++ HI3516A_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
++ 0x4, 0, 12, 12, 6
++ },
+};
+
+#define to_pll_clk(_hw) container_of(_hw, struct hi3516a_clk_pll, hw)
+
+static void __init hi3516a_calc_pll(u32 *frac_val, u32 *postdiv1_val, u32 *postdiv2_val,
-+ u32 *fbdiv_val, u32 *refdiv_val, u64 rate)
++ u32 *fbdiv_val, u32 *refdiv_val, u64 rate)
+{
+ u64 rem;
+ *frac_val = 0;
@@ -191004,8 +259075,8 @@ index 0000000..22f4fc1
+}
+
+static int __init clk_pll_set_rate(struct clk_hw *hw,
-+ unsigned long rate,
-+ unsigned long parent_rate)
++ unsigned long rate,
++ unsigned long parent_rate)
+{
+ struct hi3516a_clk_pll *clk = to_pll_clk(hw);
+ u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val;
@@ -191015,7 +259086,7 @@ index 0000000..22f4fc1
+ postdiv1_val = postdiv2_val = 0;
+
+ hi3516a_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val,
-+ &fbdiv_val, &refdiv_val, (u64)rate);
++ &fbdiv_val, &refdiv_val, (u64)rate);
+
+ val = readl_relaxed(clk->ctrl_reg1);
+ val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
@@ -191089,8 +259160,8 @@ index 0000000..22f4fc1
+ int i;
+
+ for (i = 0; i < nums; i++) {
-+ struct hi3516a_clk_pll *p_clk;
-+ struct clk *clk;
++ struct hi3516a_clk_pll *p_clk = NULL;
++ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
@@ -191123,7 +259194,7 @@ index 0000000..22f4fc1
+ if (IS_ERR(clk)) {
+ kfree(p_clk);
+ pr_err("%s: failed to register clock %s\n",
-+ __func__, clks[i].name);
++ __func__, clks[i].name);
+ continue;
+ }
+
@@ -191146,32 +259217,32 @@ index 0000000..22f4fc1
+ }
+
+ ret = hisi_clk_register_fixed_rate(hi3516a_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3516a_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3516a_fixed_rate_clks_crg), clk_data);
+ if (ret)
+ goto err;
+
+ ret = hi3516a_clk_register_pll(hi3516a_pll_clks,
-+ ARRAY_SIZE(hi3516a_pll_clks), clk_data);
++ ARRAY_SIZE(hi3516a_pll_clks), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_mux(hi3516a_mux_clks_crg,
-+ ARRAY_SIZE(hi3516a_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3516a_mux_clks_crg), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_fixed_factor(hi3516a_fixed_factor_clks,
-+ ARRAY_SIZE(hi3516a_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3516a_fixed_factor_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = hisi_clk_register_gate(hi3516a_gate_clks,
-+ ARRAY_SIZE(hi3516a_gate_clks), clk_data);
++ ARRAY_SIZE(hi3516a_gate_clks), clk_data);
+ if (ret)
+ goto unregister_factor;
+
+ ret = of_clk_add_provider(np,
-+ of_clk_src_onecell_get, &clk_data->clk_data);
++ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
@@ -191183,43 +259254,51 @@ index 0000000..22f4fc1
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3516a_gate_clks,
-+ ARRAY_SIZE(hi3516a_gate_clks), clk_data);
++ ARRAY_SIZE(hi3516a_gate_clks), clk_data);
+unregister_factor:
+ hisi_clk_unregister_fixed_factor(hi3516a_fixed_factor_clks,
-+ ARRAY_SIZE(hi3516a_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3516a_fixed_factor_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3516a_mux_clks_crg,
-+ ARRAY_SIZE(hi3516a_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3516a_mux_clks_crg), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3516a_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3516a_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3516a_fixed_rate_clks_crg), clk_data);
+err:
+ pr_err("%s: failed to init CRG clock\n", __func__);
+ return;
+}
+CLK_OF_DECLARE(hi3516a_clk_crg, "hisilicon,hi3516a-clock",
-+ hi3516a_clk_crg_init);
++ hi3516a_clk_crg_init);
+
+/* clock in system control */
+static const char *const timer_mux_p[] __initconst = {"3m", "clk_sysapb"};
+static u32 timer_mux_table[] __initdata = {0, 1};
+
+static const struct hisi_mux_clock hi3516a_mux_clks_sc_clk[] __initconst = {
-+ { HI3516A_TIME0_0_CLK, "timer00", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 16, 1, 0, timer_mux_table, },
++ {
++ HI3516A_TIME0_0_CLK, "timer00", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 16, 1, 0, timer_mux_table,
++ },
+
-+ { HI3516A_TIME0_1_CLK, "timer01", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 18, 1, 0, timer_mux_table, },
++ {
++ HI3516A_TIME0_1_CLK, "timer01", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 18, 1, 0, timer_mux_table,
++ },
+
-+ { HI3516A_TIME1_2_CLK, "timer12", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 20, 1, 0, timer_mux_table, },
++ {
++ HI3516A_TIME1_2_CLK, "timer12", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 20, 1, 0, timer_mux_table,
++ },
+
-+ { HI3516A_TIME1_3_CLK, "timer13", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 22, 1, 0, timer_mux_table, },
++ {
++ HI3516A_TIME1_3_CLK, "timer13", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 22, 1, 0, timer_mux_table,
++ },
+};
+
+static void __init hi3516a_sc_clk_init(struct device_node *np)
@@ -191230,28 +259309,28 @@ index 0000000..22f4fc1
+ clk_data = hisi_clk_init(np, HI3516A_SYS_NR_CLKS);
+ if (!clk_data) {
+ pr_err("%s: failed to allocate %s clock data\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+
+ ret = hisi_clk_register_mux(hi3516a_mux_clks_sc_clk,
-+ ARRAY_SIZE(hi3516a_mux_clks_sc_clk), clk_data);
++ ARRAY_SIZE(hi3516a_mux_clks_sc_clk), clk_data);
+ if (ret) {
+ pr_err("%s: failed to register %s mux clock\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+}
+
+CLK_OF_DECLARE(hi3516a_clk_sysctrl, "hisilicon,sysctrl",
-+ hi3516a_sc_clk_init);
++ hi3516a_sc_clk_init);
+
diff --git a/drivers/clk/hisilicon/clk-hi3516cv500.c b/drivers/clk/hisilicon/clk-hi3516cv500.c
new file mode 100644
-index 0000000..1bb8f16
+index 0000000..efb4e78
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3516cv500.c
-@@ -0,0 +1,189 @@
+@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -191311,12 +259390,14 @@ index 0000000..1bb8f16
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m", "300m"};
++ "24m", "200m", "300m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100m", "150m", "163m", "200m", "257m", "300m", "396m"};
+static const char *eth_mux_p[] __initconst = {"100m", "54m"};
+static const char *mmc_mux_p[] __initconst = {"100m", "50m", "25m"};
++static const char *pwm_mux_p[] __initconst = {"3m", "50m", "24m", "24m"};
+
+static u32 sysaxi_mux_table[] = {0, 1, 2};
+static u32 sysapb_mux_table[] = {0, 1};
@@ -191324,95 +259405,174 @@ index 0000000..1bb8f16
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+static u32 eth_mux_table[] = {0, 1};
+static u32 mmc_mux_table[] = {1, 2, 3};
++static u32 pwm_mux_table[] = {0, 1, 2, 3};
+
+static struct hisi_mux_clock hi3516cv500_mux_clks[] __initdata = {
-+ { HI3516CV500_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3516CV500_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table, },
-+ { HI3516CV500_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
++ },
++ {
++ HI3516CV500_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3516CV500_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3516CV500_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table, },
-+ { HI3516CV500_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table, },
-+ { HI3516CV500_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table, },
-+ { HI3516CV500_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3516CV500_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3516CV500_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516CV500_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516CV500_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516CV500_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ { HI3516CV500_UART1_MUX, "uart_mux1", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516CV500_UART1_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3516CV500_UART2_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516CV500_UART2_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3516CV500_UART4_MUX, "uart_mux4", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516CV500_UART4_MUX, "uart_mux4", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table, },
++ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
++ },
+ /* ethernet clock select */
-+ { HI3516CV500_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
++ {
++ HI3516CV500_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
++ { HI3516CV500_PWM_MUX, "pwm_mux", pwm_mux_p,
++ ARRAY_SIZE(pwm_mux_p),
++ CLK_SET_RATE_PARENT, 0x1bc, 8, 2, 0, pwm_mux_table,
++ },
++
+};
+
+static struct hisi_fixed_factor_clock hi3516cv500_fixed_factor_clks[] __initdata = {
-+ { HI3516CV500_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3516CV500_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3516cv500_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3516CV500_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3516CV500_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3516CV500_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x148, 1, 0, },
-+ { HI3516CV500_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x160, 1, 0, },
-+ { HI3516CV500_MMC2_CLK, "clk_mmc2", "mmc2_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 1, 0, },
++ {
++ HI3516CV500_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x148, 1, 0,
++ },
++ {
++ HI3516CV500_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x160, 1, 0,
++ },
++ {
++ HI3516CV500_MMC2_CLK, "clk_mmc2", "mmc2_mux",
++ CLK_SET_RATE_PARENT, 0x154, 1, 0,
++ },
+ /* uart */
-+ { HI3516CV500_UART0_CLK, "clk_uart0", "uart_mux0",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
-+ { HI3516CV500_UART1_CLK, "clk_uart1", "uart_mux1",
-+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3516CV500_UART2_CLK, "clk_uart2", "uart_mux2",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
-+ { HI3516CV500_UART4_CLK, "clk_uart4", "uart_mux4",
-+ CLK_SET_RATE_PARENT, 0x1b8, 4, 0, },
-+ /* i2c*/
-+ { HI3516CV500_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3516CV500_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3516CV500_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
-+ { HI3516CV500_I2C3_CLK, "clk_i2c3", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 14, 0, },
-+ { HI3516CV500_I2C4_CLK, "clk_i2c4", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 15, 0, },
-+ { HI3516CV500_I2C5_CLK, "clk_i2c5", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 16, 0, },
-+ { HI3516CV500_I2C6_CLK, "clk_i2c6", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 17, 0, },
-+ { HI3516CV500_I2C7_CLK, "clk_i2c7", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 18, 0, },
-+ /* spi */
-+ { HI3516CV500_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3516CV500_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
-+ { HI3516CV500_SPI2_CLK, "clk_spi2", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 14, 0, },
++ {
++ HI3516CV500_UART0_CLK, "clk_uart0", "uart_mux0",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
++ {
++ HI3516CV500_UART1_CLK, "clk_uart1", "uart_mux1",
++ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
++ },
++ {
++ HI3516CV500_UART2_CLK, "clk_uart2", "uart_mux2",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
++ {
++ HI3516CV500_UART4_CLK, "clk_uart4", "uart_mux4",
++ CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
++ },
++ /* i2c*/
++ {
++ HI3516CV500_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3516CV500_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3516CV500_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
++ {
++ HI3516CV500_I2C3_CLK, "clk_i2c3", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
++ },
++ {
++ HI3516CV500_I2C4_CLK, "clk_i2c4", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
++ },
++ {
++ HI3516CV500_I2C5_CLK, "clk_i2c5", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
++ },
++ {
++ HI3516CV500_I2C6_CLK, "clk_i2c6", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
++ },
++ {
++ HI3516CV500_I2C7_CLK, "clk_i2c7", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
++ },
++ /* spi */
++ {
++ HI3516CV500_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3516CV500_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
++ {
++ HI3516CV500_SPI2_CLK, "clk_spi2", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
++ },
+ /* ethernet mac */
-+ { HI3516CV500_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
-+ { HI3516CV500_DMAC_CLK, "clk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
-+ { HI3516CV500_DMAC_AXICLK, "axiclk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
++ {
++ HI3516CV500_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
++ {
++ HI3516CV500_DMAC_CLK, "clk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
++ {
++ HI3516CV500_DMAC_AXICLK, "axiclk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++ /*pwm*/
++ {
++ HI3516CV500_PWM_CLK, "clk_pwm", "pwm_mux",
++ CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
++ },
+};
+
+
@@ -191428,14 +259588,14 @@ index 0000000..1bb8f16
+ hibvt_reset_init(np, HI3516CV500_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3516cv500_fixed_rate_clks,
-+ ARRAY_SIZE(hi3516cv500_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3516cv500_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3516cv500_mux_clks, ARRAY_SIZE(hi3516cv500_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3516cv500_fixed_factor_clks,
-+ ARRAY_SIZE(hi3516cv500_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3516cv500_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3516cv500_gate_clks,
-+ ARRAY_SIZE(hi3516cv500_gate_clks), clk_data);
++ ARRAY_SIZE(hi3516cv500_gate_clks), clk_data);
+
+}
+
@@ -191443,10 +259603,10 @@ index 0000000..1bb8f16
+
diff --git a/drivers/clk/hisilicon/clk-hi3516dv200.c b/drivers/clk/hisilicon/clk-hi3516dv200.c
new file mode 100644
-index 0000000..39b5b93
+index 0000000..97b2070
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3516dv200.c
-@@ -0,0 +1,186 @@
+@@ -0,0 +1,250 @@
+/*
+ * Hi3516DV200 Clock Driver
+ *
@@ -191508,12 +259668,14 @@ index 0000000..39b5b93
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m"};
++ "24m", "200m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100", "150m", "200m", "300m", "360m"};
+static const char *mmc_mux_p[] __initdata = {
-+ "100k", "400k", "25m", "50m", "90m", "112m", "150m"};
++ "100k", "400k", "25m", "50m", "90m", "112m", "150m"
++};
+static const char *eth_mux_p[] __initconst = {"100m", "54m"};
+static const char *usb_mux_p[] __initdata = {"phy", "crg",};
+
@@ -191526,87 +259688,149 @@ index 0000000..39b5b93
+static u32 usb_mux_table[] = {0, 1};
+
+static struct hisi_mux_clock hi3516dv200_mux_clks[] __initdata = {
-+ { HI3516DV200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3516DV200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table, },
-+ { HI3516DV200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
++ },
++ {
++ HI3516DV200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3516DV200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3516DV200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table, },
-+ { HI3516DV200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table, },
-+ { HI3516DV200_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3516DV200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3516DV200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3516DV200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3516DV200_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ { HI3516DV200_UART_MUX, "uart_mux1", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516DV200_UART_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3516DV200_UART_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516DV200_UART_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3516DV200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
-+ { HI3516DV200_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table},
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516DV200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
++ {
++ HI3516DV200_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
++ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
++ },
+};
+
+static struct hisi_fixed_factor_clock hi3516dv200_fixed_factor_clks[] __initdata = {
-+ { HI3516DV200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3516DV200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3516dv200_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3516DV200_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3516DV200_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3516DV200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x1f4, 28, 0, },
-+ { HI3516DV200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x22c, 28, 0, },
++ {
++ HI3516DV200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
++ },
++ {
++ HI3516DV200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x22c, 28, 0,
++ },
+ /* uart */
-+ { HI3516DV200_UART0_CLK, "clk_uart0", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
-+ { HI3516DV200_UART1_CLK, "clk_uart1", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3516DV200_UART2_CLK, "clk_uart2", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
++ {
++ HI3516DV200_UART0_CLK, "clk_uart0", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
++ {
++ HI3516DV200_UART1_CLK, "clk_uart1", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
++ },
++ {
++ HI3516DV200_UART2_CLK, "clk_uart2", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
+ /* spi */
-+ { HI3516DV200_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3516DV200_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
++ {
++ HI3516DV200_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3516DV200_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
+ /* i2c */
-+ { HI3516DV200_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3516DV200_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3516DV200_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
++ {
++ HI3516DV200_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3516DV200_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3516DV200_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
+ /* ethernet mac */
-+ { HI3516DV200_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
++ {
++ HI3516DV200_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
+ /* edmac */
-+ { HI3516DV200_EDMAC_AXICLK, "axi_clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
-+ { HI3516DV200_EDMAC_CLK, "clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
++ {
++ HI3516DV200_EDMAC_AXICLK, "axi_clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++ {
++ HI3516DV200_EDMAC_CLK, "clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
+ /* usb */
-+ { HI3516DV200_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 8, 0, },
-+ { HI3516DV200_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 9, 0, },
-+ { HI3516DV200_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 12, 0, },
-+ { HI3516DV200_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 11, 0, },
-+ { HI3516DV200_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 4, 0, },
-+ { HI3516DV200_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 2, 0, },
++ {
++ HI3516DV200_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 8, 0,
++ },
++ {
++ HI3516DV200_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 9, 0,
++ },
++ {
++ HI3516DV200_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 12, 0,
++ },
++ {
++ HI3516DV200_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 11, 0,
++ },
++ {
++ HI3516DV200_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 4, 0,
++ },
++ {
++ HI3516DV200_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 2, 0,
++ },
+};
+
+static void __init hi3516dv200_clk_init(struct device_node *np)
@@ -191620,14 +259844,14 @@ index 0000000..39b5b93
+ hibvt_reset_init(np, HI3516DV200_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3516dv200_fixed_rate_clks,
-+ ARRAY_SIZE(hi3516dv200_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3516dv200_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3516dv200_mux_clks, ARRAY_SIZE(hi3516dv200_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3516dv200_fixed_factor_clks,
-+ ARRAY_SIZE(hi3516dv200_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3516dv200_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3516dv200_gate_clks,
-+ ARRAY_SIZE(hi3516dv200_gate_clks), clk_data);
++ ARRAY_SIZE(hi3516dv200_gate_clks), clk_data);
+
+}
+
@@ -191635,10 +259859,10 @@ index 0000000..39b5b93
+
diff --git a/drivers/clk/hisilicon/clk-hi3516dv300.c b/drivers/clk/hisilicon/clk-hi3516dv300.c
new file mode 100644
-index 0000000..9a8392f
+index 0000000..3fbe681
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3516dv300.c
-@@ -0,0 +1,194 @@
+@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -191698,12 +259922,14 @@ index 0000000..9a8392f
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m", "300m"};
++ "24m", "200m", "300m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100m", "150m", "163m", "200m", "257m", "300m", "396m"};
+static const char *eth_mux_p[] __initconst = {"100m", "54m"};
+static const char *mmc_mux_p[] __initconst = {"100m", "50m", "25m"};
++static const char *pwm_mux_p[] __initconst = {"3m", "50m", "24m", "24m"};
+
+static u32 sysaxi_mux_table[] = {0, 1, 2};
+static u32 sysapb_mux_table[] = {0, 1};
@@ -191711,100 +259937,181 @@ index 0000000..9a8392f
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+static u32 eth_mux_table[] = {0, 1};
+static u32 mmc_mux_table[] = {1, 2, 3};
++static u32 pwm_mux_table[] = {0, 1, 2, 3};
+
+static struct hisi_mux_clock hi3516dv300_mux_clks[] __initdata = {
-+ { HI3516DV300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3516DV300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table, },
-+ { HI3516DV300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
++ },
++ {
++ HI3516DV300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3516DV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3516DV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table, },
-+ { HI3516DV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table, },
-+ { HI3516DV300_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table, },
-+ { HI3516DV300_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3516DV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3516DV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516DV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516DV300_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3516DV300_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ { HI3516DV300_UART1_MUX, "uart_mux1", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516DV300_UART1_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3516DV300_UART2_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516DV300_UART2_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3516DV300_UART3_MUX, "uart_mux3", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516DV300_UART3_MUX, "uart_mux3", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table, },
-+ { HI3516DV300_UART4_MUX, "uart_mux4", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516DV300_UART4_MUX, "uart_mux4", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table, },
++ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
++ },
++ { HI3516DV300_PWM_MUX, "pwm_mux", pwm_mux_p,
++ ARRAY_SIZE(pwm_mux_p),
++ CLK_SET_RATE_PARENT, 0x1bc, 8, 2, 0, pwm_mux_table,
++ },
+ /* ethernet clock select */
-+ { HI3516DV300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
++ {
++ HI3516DV300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
+};
+
+static struct hisi_fixed_factor_clock hi3516dv300_fixed_factor_clks[] __initdata = {
-+ { HI3516DV300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3516DV300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3516dv300_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3516DV300_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3516DV300_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3516DV300_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x148, 1, 0, },
-+ { HI3516DV300_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x160, 1, 0, },
-+ { HI3516DV300_MMC2_CLK, "clk_mmc2", "mmc2_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 1, 0, },
++ {
++ HI3516DV300_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x148, 1, 0,
++ },
++ {
++ HI3516DV300_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x160, 1, 0,
++ },
++ {
++ HI3516DV300_MMC2_CLK, "clk_mmc2", "mmc2_mux",
++ CLK_SET_RATE_PARENT, 0x154, 1, 0,
++ },
+ /* uart */
-+ { HI3516DV300_UART0_CLK, "clk_uart0", "uart_mux0",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
-+ { HI3516DV300_UART1_CLK, "clk_uart1", "uart_mux1",
-+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3516DV300_UART2_CLK, "clk_uart2", "uart_mux2",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
-+ { HI3516DV300_UART3_CLK, "clk_uart3", "uart_mux3",
-+ CLK_SET_RATE_PARENT, 0x1b8, 3, 0, },
-+ { HI3516DV300_UART4_CLK, "clk_uart4", "uart_mux4",
-+ CLK_SET_RATE_PARENT, 0x1b8, 4, 0, },
-+ /* i2c*/
-+ { HI3516DV300_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3516DV300_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3516DV300_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
-+ { HI3516DV300_I2C3_CLK, "clk_i2c3", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 14, 0, },
-+ { HI3516DV300_I2C4_CLK, "clk_i2c4", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 15, 0, },
-+ { HI3516DV300_I2C5_CLK, "clk_i2c5", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 16, 0, },
-+ { HI3516DV300_I2C6_CLK, "clk_i2c6", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 17, 0, },
-+ { HI3516DV300_I2C7_CLK, "clk_i2c7", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 18, 0, },
-+ /* spi */
-+ { HI3516DV300_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3516DV300_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
-+ { HI3516DV300_SPI2_CLK, "clk_spi2", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 14, 0, },
++ {
++ HI3516DV300_UART0_CLK, "clk_uart0", "uart_mux0",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
++ {
++ HI3516DV300_UART1_CLK, "clk_uart1", "uart_mux1",
++ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
++ },
++ {
++ HI3516DV300_UART2_CLK, "clk_uart2", "uart_mux2",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
++ {
++ HI3516DV300_UART3_CLK, "clk_uart3", "uart_mux3",
++ CLK_SET_RATE_PARENT, 0x1b8, 3, 0,
++ },
++ {
++ HI3516DV300_UART4_CLK, "clk_uart4", "uart_mux4",
++ CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
++ },
++ /* i2c*/
++ {
++ HI3516DV300_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3516DV300_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3516DV300_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
++ {
++ HI3516DV300_I2C3_CLK, "clk_i2c3", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
++ },
++ {
++ HI3516DV300_I2C4_CLK, "clk_i2c4", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
++ },
++ {
++ HI3516DV300_I2C5_CLK, "clk_i2c5", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
++ },
++ {
++ HI3516DV300_I2C6_CLK, "clk_i2c6", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
++ },
++ {
++ HI3516DV300_I2C7_CLK, "clk_i2c7", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
++ },
++ /* spi */
++ {
++ HI3516DV300_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3516DV300_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
++ {
++ HI3516DV300_SPI2_CLK, "clk_spi2", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
++ },
+ /* ethernet mac */
-+ { HI3516DV300_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
-+ { HI3516DV300_DMAC_CLK, "clk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
-+ { HI3516DV300_DMAC_AXICLK, "axiclk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
++ {
++ HI3516DV300_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
++ {
++ HI3516DV300_DMAC_CLK, "clk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
++ {
++ HI3516DV300_DMAC_AXICLK, "axiclk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++ /*pwm*/
++ { HI3516DV300_PWM_CLK, "clk_pwm", "pwm_mux",
++ CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
++ },
+};
+
+
@@ -191820,14 +260127,14 @@ index 0000000..9a8392f
+ hibvt_reset_init(np, HI3516DV300_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3516dv300_fixed_rate_clks,
-+ ARRAY_SIZE(hi3516dv300_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3516dv300_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3516dv300_mux_clks, ARRAY_SIZE(hi3516dv300_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3516dv300_fixed_factor_clks,
-+ ARRAY_SIZE(hi3516dv300_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3516dv300_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3516dv300_gate_clks,
-+ ARRAY_SIZE(hi3516dv300_gate_clks), clk_data);
++ ARRAY_SIZE(hi3516dv300_gate_clks), clk_data);
+
+}
+
@@ -191835,10 +260142,10 @@ index 0000000..9a8392f
+
diff --git a/drivers/clk/hisilicon/clk-hi3516ev200.c b/drivers/clk/hisilicon/clk-hi3516ev200.c
new file mode 100644
-index 0000000..5e6293e
+index 0000000..5b27dd2
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3516ev200.c
-@@ -0,0 +1,188 @@
+@@ -0,0 +1,252 @@
+/*
+ * Hi3516EV200 Clock Driver
+ *
@@ -191900,12 +260207,14 @@ index 0000000..5e6293e
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m"};
++ "24m", "200m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100", "150m", "200m", "300m", "360m"};
+static const char *mmc_mux_p[] __initdata = {
-+ "100k", "400k", "25m", "50m", "90m", "112m", "150m"};
++ "100k", "400k", "25m", "50m", "90m", "112m", "150m"
++};
+static const char *eth_mux_p[] __initconst = {"100m", "54m"};
+static const char *usb_mux_p[] __initdata = {"phy", "crg",};
+
@@ -191918,89 +260227,151 @@ index 0000000..5e6293e
+static u32 usb_mux_table[] = {0, 1};
+
+static struct hisi_mux_clock hi3516ev200_mux_clks[] __initdata = {
-+ { HI3516EV200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3516EV200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table, },
-+ { HI3516EV200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
++ },
++ {
++ HI3516EV200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3516EV200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3516EV200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table, },
-+ { HI3516EV200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table, },
-+ { HI3516EV200_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3516EV200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3516EV200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3516EV200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3516EV200_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ { HI3516EV200_UART_MUX, "uart_mux1", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516EV200_UART_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3516EV200_UART_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516EV200_UART_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3516EV200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
-+ { HI3516EV200_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table},
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516EV200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
++ {
++ HI3516EV200_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
++ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
++ },
+};
+
+#if 1
+static struct hisi_fixed_factor_clock hi3516ev200_fixed_factor_clks[] __initdata = {
-+ { HI3516EV200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3516EV200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+#endif
+
+static struct hisi_gate_clock hi3516ev200_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3516EV200_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3516EV200_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3516EV200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x1f4, 28, 0, },
-+ { HI3516EV200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x22c, 28, 0, },
++ {
++ HI3516EV200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
++ },
++ {
++ HI3516EV200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x22c, 28, 0,
++ },
+ /* uart */
-+ { HI3516EV200_UART0_CLK, "clk_uart0", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
-+ { HI3516EV200_UART1_CLK, "clk_uart1", "uart_mux1",
-+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3516EV200_UART2_CLK, "clk_uart2", "uart_mux2",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
++ {
++ HI3516EV200_UART0_CLK, "clk_uart0", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
++ {
++ HI3516EV200_UART1_CLK, "clk_uart1", "uart_mux1",
++ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
++ },
++ {
++ HI3516EV200_UART2_CLK, "clk_uart2", "uart_mux2",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
+ /* spi */
-+ { HI3516EV200_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3516EV200_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
++ {
++ HI3516EV200_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3516EV200_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
+ /* i2c */
-+ { HI3516EV200_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3516EV200_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3516EV200_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
++ {
++ HI3516EV200_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3516EV200_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3516EV200_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
+ /* ethernet mac */
-+ { HI3516EV200_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
++ {
++ HI3516EV200_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
+ /* edmac */
-+ { HI3516EV200_EDMAC_AXICLK, "axi_clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
-+ { HI3516EV200_EDMAC_CLK, "clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
++ {
++ HI3516EV200_EDMAC_AXICLK, "axi_clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++ {
++ HI3516EV200_EDMAC_CLK, "clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
+ /* usb */
-+ { HI3516EV200_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 8, 0, },
-+ { HI3516EV200_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 9, 0, },
-+ { HI3516EV200_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 12, 0, },
-+ { HI3516EV200_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 11, 0, },
-+ { HI3516EV200_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 4, 0, },
-+ { HI3516EV200_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 2, 0, },
++ {
++ HI3516EV200_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 8, 0,
++ },
++ {
++ HI3516EV200_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 9, 0,
++ },
++ {
++ HI3516EV200_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 12, 0,
++ },
++ {
++ HI3516EV200_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 11, 0,
++ },
++ {
++ HI3516EV200_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 4, 0,
++ },
++ {
++ HI3516EV200_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 2, 0,
++ },
+};
+
+static void __init hi3516ev200_clk_init(struct device_node *np)
@@ -192014,14 +260385,14 @@ index 0000000..5e6293e
+ hibvt_reset_init(np, HI3516EV200_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3516ev200_fixed_rate_clks,
-+ ARRAY_SIZE(hi3516ev200_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3516ev200_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3516ev200_mux_clks, ARRAY_SIZE(hi3516ev200_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3516ev200_fixed_factor_clks,
-+ ARRAY_SIZE(hi3516ev200_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3516ev200_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3516ev200_gate_clks,
-+ ARRAY_SIZE(hi3516ev200_gate_clks), clk_data);
++ ARRAY_SIZE(hi3516ev200_gate_clks), clk_data);
+
+}
+
@@ -192029,10 +260400,10 @@ index 0000000..5e6293e
+
diff --git a/drivers/clk/hisilicon/clk-hi3516ev300.c b/drivers/clk/hisilicon/clk-hi3516ev300.c
new file mode 100644
-index 0000000..de1f61a
+index 0000000..4ff3ab5
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3516ev300.c
-@@ -0,0 +1,186 @@
+@@ -0,0 +1,250 @@
+/*
+ * Hi3516EV300 Clock Driver
+ *
@@ -192094,12 +260465,14 @@ index 0000000..de1f61a
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m"};
++ "24m", "200m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100", "150m", "200m", "300m", "360m"};
+static const char *mmc_mux_p[] __initdata = {
-+ "100k", "400k", "25m", "50m", "90m", "112m", "150m"};
++ "100k", "400k", "25m", "50m", "90m", "112m", "150m"
++};
+static const char *eth_mux_p[] __initconst = {"100m", "54m"};
+static const char *usb_mux_p[] __initdata = {"phy", "crg",};
+
@@ -192112,87 +260485,149 @@ index 0000000..de1f61a
+static u32 usb_mux_table[] = {0, 1};
+
+static struct hisi_mux_clock hi3516ev300_mux_clks[] __initdata = {
-+ { HI3516EV300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3516EV300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table, },
-+ { HI3516EV300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
++ },
++ {
++ HI3516EV300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3516EV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3516EV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table, },
-+ { HI3516EV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table, },
-+ { HI3516EV300_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3516EV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3516EV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3516EV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3516EV300_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ { HI3516EV300_UART_MUX, "uart_mux1", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516EV300_UART_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3516EV300_UART_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516EV300_UART_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3516EV300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
-+ { HI3516EV300_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table},
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3516EV300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
++ {
++ HI3516EV300_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
++ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
++ },
+};
+
+static struct hisi_fixed_factor_clock hi3516ev300_fixed_factor_clks[] __initdata = {
-+ { HI3516EV300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3516EV300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3516ev300_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3516EV300_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3516EV300_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3516EV300_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x1f4, 28, 0, },
-+ { HI3516EV300_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x22c, 28, 0, },
++ {
++ HI3516EV300_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
++ },
++ {
++ HI3516EV300_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x22c, 28, 0,
++ },
+ /* uart */
-+ { HI3516EV300_UART0_CLK, "clk_uart0", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
-+ { HI3516EV300_UART1_CLK, "clk_uart1", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3516EV300_UART2_CLK, "clk_uart2", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
++ {
++ HI3516EV300_UART0_CLK, "clk_uart0", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
++ {
++ HI3516EV300_UART1_CLK, "clk_uart1", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
++ },
++ {
++ HI3516EV300_UART2_CLK, "clk_uart2", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
+ /* spi */
-+ { HI3516EV300_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3516EV300_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
++ {
++ HI3516EV300_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3516EV300_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
+ /* i2c */
-+ { HI3516EV300_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3516EV300_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3516EV300_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
++ {
++ HI3516EV300_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3516EV300_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3516EV300_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
+ /* ethernet mac */
-+ { HI3516EV300_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
++ {
++ HI3516EV300_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
+ /* edmac */
-+ { HI3516EV300_EDMAC_AXICLK, "axi_clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
-+ { HI3516EV300_EDMAC_CLK, "clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
++ {
++ HI3516EV300_EDMAC_AXICLK, "axi_clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++ {
++ HI3516EV300_EDMAC_CLK, "clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
+ /* usb */
-+ { HI3516EV300_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 8, 0, },
-+ { HI3516EV300_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 9, 0, },
-+ { HI3516EV300_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 12, 0, },
-+ { HI3516EV300_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 11, 0, },
-+ { HI3516EV300_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 4, 0, },
-+ { HI3516EV300_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 2, 0, },
++ {
++ HI3516EV300_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 8, 0,
++ },
++ {
++ HI3516EV300_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 9, 0,
++ },
++ {
++ HI3516EV300_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 12, 0,
++ },
++ {
++ HI3516EV300_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 11, 0,
++ },
++ {
++ HI3516EV300_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 4, 0,
++ },
++ {
++ HI3516EV300_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 2, 0,
++ },
+};
+
+static void __init hi3516ev300_clk_init(struct device_node *np)
@@ -192206,14 +260641,14 @@ index 0000000..de1f61a
+ hibvt_reset_init(np, HI3516EV300_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3516ev300_fixed_rate_clks,
-+ ARRAY_SIZE(hi3516ev300_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3516ev300_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3516ev300_mux_clks, ARRAY_SIZE(hi3516ev300_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3516ev300_fixed_factor_clks,
-+ ARRAY_SIZE(hi3516ev300_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3516ev300_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3516ev300_gate_clks,
-+ ARRAY_SIZE(hi3516ev300_gate_clks), clk_data);
++ ARRAY_SIZE(hi3516ev300_gate_clks), clk_data);
+
+}
+
@@ -192221,10 +260656,10 @@ index 0000000..de1f61a
+
diff --git a/drivers/clk/hisilicon/clk-hi3518ev20x.c b/drivers/clk/hisilicon/clk-hi3518ev20x.c
new file mode 100644
-index 0000000..100bc10
+index 0000000..9b53206
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3518ev20x.c
-@@ -0,0 +1,245 @@
+@@ -0,0 +1,291 @@
+/*
+ * Hi3518ev20x Clock Driver
+ *
@@ -192257,7 +260692,7 @@ index 0000000..100bc10
+#include "reset.h"
+
+static const struct
-+hisi_fixed_rate_clock hi3518ev20x_fixed_rate_clks_crg[] __initconst = {
++ hisi_fixed_rate_clock hi3518ev20x_fixed_rate_clks_crg[] __initconst = {
+ { HI3518EV20X_FIXED_3M, "3m", NULL, 0, 3000000, },
+ { HI3518EV20X_FIXED_6M, "6m", NULL, 0, 6000000, },
+ { HI3518EV20X_FIXED_24M, "24m", NULL, 0, 24000000, },
@@ -192300,67 +260735,105 @@ index 0000000..100bc10
+static u32 mmc1_mux_table[] = {0};
+
+static const struct hisi_mux_clock hi3518ev20x_mux_clks_crg[] __initconst = {
-+ { HI3518EV20X_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ {
++ HI3518EV20X_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x30, 0, 1, 0, sysapb_mux_table, },
-+ { HI3518EV20X_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, fmc_mux_table, },
-+ { HI3518EV20X_UART_MUX, "uart_mux", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x30, 0, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3518EV20X_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, fmc_mux_table,
++ },
++ {
++ HI3518EV20X_UART_MUX, "uart_mux", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
++ CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table,
++ },
+ /* ethernet clock select */
-+ { HI3518EV20X_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0xec, 7, 0, 0, eth_mux_table, },
++ {
++ HI3518EV20X_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0xec, 7, 0, 0, eth_mux_table,
++ },
+ /* MMC0 clock select */
-+ { HI3518EV20X_MMC0_MUX, "mmc0_mux", mmc0_mux_p, ARRAY_SIZE(mmc0_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc4, 10, 2, 0, mmc0_mux_table, },
++ {
++ HI3518EV20X_MMC0_MUX, "mmc0_mux", mmc0_mux_p, ARRAY_SIZE(mmc0_mux_p),
++ CLK_SET_RATE_PARENT, 0xc4, 10, 2, 0, mmc0_mux_table,
++ },
+ /* MMC1 clock select */
-+ { HI3518EV20X_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc4, 2, 2, 0, mmc1_mux_table, },
++ {
++ HI3518EV20X_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p),
++ CLK_SET_RATE_PARENT, 0xc4, 2, 2, 0, mmc1_mux_table,
++ },
+};
+
+/* fixed factor clocks */
+static struct hisi_fixed_factor_clock
-+ hi3518ev20x_fixed_factor_clks[] __initdata = {
-+ { HI3518EV20X_SYSAPB_CLK, "sysapb", "sysapb_mux", 1, 4,
-+ CLK_SET_RATE_PARENT, },
++ hi3518ev20x_fixed_factor_clks[] __initdata = {
++ {
++ HI3518EV20X_SYSAPB_CLK, "sysapb", "sysapb_mux", 1, 4,
++ CLK_SET_RATE_PARENT,
++ },
+};
+
+static const struct hisi_gate_clock hi3518ev20x_gate_clks[] __initconst = {
+ /* fmc */
-+ { HI3518EV20X_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
++ {
++ HI3518EV20X_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0xc0, 1, 0,
++ },
+
+ /* usb ctrl */
-+ { HI3518EV20X_USB2_CTRL_UTMI0_REQ, "usb2_cttl_utmi0_req", NULL,
-+ CLK_SET_RATE_PARENT, 0xb4, 5, 1, },
-+ { HI3518EV20X_USB2_HRST_REQ, "usb2_hrst_req", NULL,
-+ CLK_SET_RATE_PARENT, 0xb4, 0, 1, },
++ {
++ HI3518EV20X_USB2_CTRL_UTMI0_REQ, "usb2_cttl_utmi0_req", NULL,
++ CLK_SET_RATE_PARENT, 0xb4, 5, 1,
++ },
++ {
++ HI3518EV20X_USB2_HRST_REQ, "usb2_hrst_req", NULL,
++ CLK_SET_RATE_PARENT, 0xb4, 0, 1,
++ },
+
+ /* uart */
-+ { HI3518EV20X_UART0_CLK, "clk_uart0", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0xe4, 15, 0, },
-+ { HI3518EV20X_UART1_CLK, "clk_uart1", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
-+ { HI3518EV20X_UART2_CLK, "clk_uart2", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
++ {
++ HI3518EV20X_UART0_CLK, "clk_uart0", "uart_mux",
++ CLK_SET_RATE_PARENT, 0xe4, 15, 0,
++ },
++ {
++ HI3518EV20X_UART1_CLK, "clk_uart1", "uart_mux",
++ CLK_SET_RATE_PARENT, 0xe4, 16, 0,
++ },
++ {
++ HI3518EV20X_UART2_CLK, "clk_uart2", "uart_mux",
++ CLK_SET_RATE_PARENT, 0xe4, 17, 0,
++ },
+ /* ethernet */
-+ { HI3518EV20X_ETH_CLK, "clk_eth", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0xec, 1, 0, },
++ {
++ HI3518EV20X_ETH_CLK, "clk_eth", "eth_mux",
++ CLK_SET_RATE_PARENT, 0xec, 1, 0,
++ },
+ /* mmc0 */
-+ { HI3518EV20X_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0xc4, 9, 0, },
++ {
++ HI3518EV20X_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0xc4, 9, 0,
++ },
+ /* mmc1 */
-+ { HI3518EV20X_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0xc4, 1, 0, },
++ {
++ HI3518EV20X_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0xc4, 1, 0,
++ },
+ /* spi */
-+ { HI3518EV20X_SPI0_CLK, "clk_spi0", "sysapb_mux",
-+ CLK_SET_RATE_PARENT, 0xe4, 13, 0, },
-+ { HI3518EV20X_SPI1_CLK, "clk_spi1", "sysapb_mux",
-+ CLK_SET_RATE_PARENT, 0xe4, 14, 0, },
++ {
++ HI3518EV20X_SPI0_CLK, "clk_spi0", "sysapb_mux",
++ CLK_SET_RATE_PARENT, 0xe4, 13, 0,
++ },
++ {
++ HI3518EV20X_SPI1_CLK, "clk_spi1", "sysapb_mux",
++ CLK_SET_RATE_PARENT, 0xe4, 14, 0,
++ },
+ /* dmac */
-+ { HI3518EV20X_DMAC_CLK, "clk_dmac", "50m",
-+ CLK_SET_RATE_PARENT, 0xd8, 5, 0, },
++ {
++ HI3518EV20X_DMAC_CLK, "clk_dmac", "50m",
++ CLK_SET_RATE_PARENT, 0xd8, 5, 0,
++ },
+};
+
+static void __init hi3518ev20x_clk_crg_init(struct device_node *np)
@@ -192376,27 +260849,27 @@ index 0000000..100bc10
+ }
+
+ ret = hisi_clk_register_fixed_rate(hi3518ev20x_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3518ev20x_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3518ev20x_fixed_rate_clks_crg), clk_data);
+ if (ret)
+ goto err;
+
+ ret = hisi_clk_register_mux(hi3518ev20x_mux_clks_crg,
-+ ARRAY_SIZE(hi3518ev20x_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3518ev20x_mux_clks_crg), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_fixed_factor(hi3518ev20x_fixed_factor_clks,
-+ ARRAY_SIZE(hi3518ev20x_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3518ev20x_fixed_factor_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = hisi_clk_register_gate(hi3518ev20x_gate_clks,
-+ ARRAY_SIZE(hi3518ev20x_gate_clks), clk_data);
++ ARRAY_SIZE(hi3518ev20x_gate_clks), clk_data);
+ if (ret)
+ goto unregister_factor;
+
+ ret = of_clk_add_provider(np,
-+ of_clk_src_onecell_get, &clk_data->clk_data);
++ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
@@ -192408,43 +260881,51 @@ index 0000000..100bc10
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3518ev20x_gate_clks,
-+ ARRAY_SIZE(hi3518ev20x_gate_clks), clk_data);
++ ARRAY_SIZE(hi3518ev20x_gate_clks), clk_data);
+unregister_factor:
+ hisi_clk_unregister_fixed_factor(hi3518ev20x_fixed_factor_clks,
-+ ARRAY_SIZE(hi3518ev20x_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3518ev20x_fixed_factor_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3518ev20x_mux_clks_crg,
-+ ARRAY_SIZE(hi3518ev20x_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3518ev20x_mux_clks_crg), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3518ev20x_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3518ev20x_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3518ev20x_fixed_rate_clks_crg), clk_data);
+err:
+ pr_err("%s: failed to init CRG clock\n", __func__);
+ return;
+}
+CLK_OF_DECLARE(hi3518ev20x_clk_crg, "hisilicon,hi3518ev20x-clock",
-+ hi3518ev20x_clk_crg_init);
++ hi3518ev20x_clk_crg_init);
+
+/* clock in system control */
+static const char *const timer_mux_p[] __initconst = {"3m", "sysapb"};
+static u32 timer_mux_table[] __initdata = {0, 1};
+
+static const struct hisi_mux_clock hi3518ev20x_mux_clks_sc_clk[] __initconst = {
-+ { HI3518EV20X_TIME0_0_CLK, "timer00", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 16, 1, 0, timer_mux_table, },
++ {
++ HI3518EV20X_TIME0_0_CLK, "timer00", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 16, 1, 0, timer_mux_table,
++ },
+
-+ { HI3518EV20X_TIME0_1_CLK, "timer01", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 18, 1, 0, timer_mux_table, },
++ {
++ HI3518EV20X_TIME0_1_CLK, "timer01", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 18, 1, 0, timer_mux_table,
++ },
+
-+ { HI3518EV20X_TIME1_2_CLK, "timer12", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 20, 1, 0, timer_mux_table, },
++ {
++ HI3518EV20X_TIME1_2_CLK, "timer12", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 20, 1, 0, timer_mux_table,
++ },
+
-+ { HI3518EV20X_TIME1_3_CLK, "timer13", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 22, 1, 0, timer_mux_table, },
++ {
++ HI3518EV20X_TIME1_3_CLK, "timer13", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 22, 1, 0, timer_mux_table,
++ },
+};
+
+static void __init hi3518ev20x_sc_clk_init(struct device_node *np)
@@ -192455,27 +260936,27 @@ index 0000000..100bc10
+ clk_data = hisi_clk_init(np, HI3518EV20X_SC_NR_CLKS);
+ if (!clk_data) {
+ pr_err("%s: failed to allocate %s clock data\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+
+ ret = hisi_clk_register_mux(hi3518ev20x_mux_clks_sc_clk,
-+ ARRAY_SIZE(hi3518ev20x_mux_clks_sc_clk), clk_data);
++ ARRAY_SIZE(hi3518ev20x_mux_clks_sc_clk), clk_data);
+ if (ret) {
+ pr_err("%s: failed to register %s mux clock\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+}
+
+CLK_OF_DECLARE(hi3518ev20x_clk_sysctrl, "hisilicon,sysctrl",
-+ hi3518ev20x_sc_clk_init);
++ hi3518ev20x_sc_clk_init);
diff --git a/drivers/clk/hisilicon/clk-hi3518ev300.c b/drivers/clk/hisilicon/clk-hi3518ev300.c
new file mode 100644
-index 0000000..14c00a2
+index 0000000..02f672a
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3518ev300.c
-@@ -0,0 +1,186 @@
+@@ -0,0 +1,250 @@
+/*
+ * Hi3518EV300 Clock Driver
+ *
@@ -192537,12 +261018,14 @@ index 0000000..14c00a2
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m"};
++ "24m", "200m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100", "150m", "200m", "300m", "360m"};
+static const char *mmc_mux_p[] __initdata = {
-+ "100k", "400k", "25m", "50m", "90m", "112m", "150m"};
++ "100k", "400k", "25m", "50m", "90m", "112m", "150m"
++};
+static const char *eth_mux_p[] __initconst = {"100m", "54m"};
+static const char *usb_mux_p[] __initdata = {"phy", "crg",};
+
@@ -192555,87 +261038,149 @@ index 0000000..14c00a2
+static u32 usb_mux_table[] = {0, 1};
+
+static struct hisi_mux_clock hi3518ev300_mux_clks[] __initdata = {
-+ { HI3518EV300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3518EV300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table, },
-+ { HI3518EV300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
++ },
++ {
++ HI3518EV300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3518EV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3518EV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table, },
-+ { HI3518EV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table, },
-+ { HI3518EV300_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3518EV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3518EV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3518EV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
++ },
++ {
++ HI3518EV300_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ { HI3518EV300_UART_MUX, "uart_mux1", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++ {
++ HI3518EV300_UART_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3518EV300_UART_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
++ },
++ {
++ HI3518EV300_UART_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3518EV300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
-+ { HI3518EV300_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table},
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3518EV300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
++ {
++ HI3518EV300_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
++ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
++ },
+};
+
+static struct hisi_fixed_factor_clock hi3518ev300_fixed_factor_clks[] __initdata = {
-+ { HI3518EV300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3518EV300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3518ev300_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3518EV300_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3518EV300_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3518EV300_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x1f4, 28, 0, },
-+ { HI3518EV300_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x22c, 28, 0, },
++ {
++ HI3518EV300_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
++ },
++ {
++ HI3518EV300_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x22c, 28, 0,
++ },
+ /* uart */
-+ { HI3518EV300_UART0_CLK, "clk_uart0", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
-+ { HI3518EV300_UART1_CLK, "clk_uart1", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3518EV300_UART2_CLK, "clk_uart2", "24m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
++ {
++ HI3518EV300_UART0_CLK, "clk_uart0", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
++ {
++ HI3518EV300_UART1_CLK, "clk_uart1", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
++ },
++ {
++ HI3518EV300_UART2_CLK, "clk_uart2", "24m",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
+ /* spi */
-+ { HI3518EV300_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3518EV300_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
++ {
++ HI3518EV300_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3518EV300_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
+ /* i2c */
-+ { HI3518EV300_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3518EV300_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3518EV300_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
++ {
++ HI3518EV300_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3518EV300_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3518EV300_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
+ /* ethernet mac */
-+ { HI3518EV300_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
++ {
++ HI3518EV300_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
+ /* edmac */
-+ { HI3518EV300_EDMAC_AXICLK, "axi_clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
-+ { HI3518EV300_EDMAC_CLK, "clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
++ {
++ HI3518EV300_EDMAC_AXICLK, "axi_clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++ {
++ HI3518EV300_EDMAC_CLK, "clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
+ /* usb */
-+ { HI3518EV300_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 8, 0, },
-+ { HI3518EV300_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 9, 0, },
-+ { HI3518EV300_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
-+ CLK_SET_RATE_PARENT, 0x140, 12, 0, },
-+ { HI3518EV300_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 11, 0, },
-+ { HI3518EV300_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 4, 0, },
-+ { HI3518EV300_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
-+ CLK_SET_RATE_PARENT, 0x140, 2, 0, },
++ {
++ HI3518EV300_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 8, 0,
++ },
++ {
++ HI3518EV300_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 9, 0,
++ },
++ {
++ HI3518EV300_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
++ CLK_SET_RATE_PARENT, 0x140, 12, 0,
++ },
++ {
++ HI3518EV300_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 11, 0,
++ },
++ {
++ HI3518EV300_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 4, 0,
++ },
++ {
++ HI3518EV300_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
++ CLK_SET_RATE_PARENT, 0x140, 2, 0,
++ },
+};
+
+static void __init hi3518ev300_clk_init(struct device_node *np)
@@ -192649,14 +261194,14 @@ index 0000000..14c00a2
+ hibvt_reset_init(np, HI3518EV300_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3518ev300_fixed_rate_clks,
-+ ARRAY_SIZE(hi3518ev300_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3518ev300_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3518ev300_mux_clks, ARRAY_SIZE(hi3518ev300_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3518ev300_fixed_factor_clks,
-+ ARRAY_SIZE(hi3518ev300_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3518ev300_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3518ev300_gate_clks,
-+ ARRAY_SIZE(hi3518ev300_gate_clks), clk_data);
++ ARRAY_SIZE(hi3518ev300_gate_clks), clk_data);
+
+}
+
@@ -192664,10 +261209,10 @@ index 0000000..14c00a2
+
diff --git a/drivers/clk/hisilicon/clk-hi3519av100.c b/drivers/clk/hisilicon/clk-hi3519av100.c
new file mode 100644
-index 0000000..2294f3f
+index 0000000..77f9e48
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3519av100.c
-@@ -0,0 +1,454 @@
+@@ -0,0 +1,571 @@
+/*
+ * Hi3519A Clock Driver
+ *
@@ -192731,8 +261276,10 @@ index 0000000..2294f3f
+};
+
+static struct hi3519av100_pll_clock hi3519av100_pll_clks[] __initdata = {
-+ { HI3519AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
-+ 0x4, 0, 12, 12, 6},
++ {
++ HI3519AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
++ 0x4, 0, 12, 12, 6
++ },
+};
+
+#define to_pll_clk(_hw) container_of(_hw, struct hi3519av100_clk_pll, hw)
@@ -192783,76 +261330,113 @@ index 0000000..2294f3f
+
+
+static const char *fmc_mux_p[] __initdata = {
-+ "24m", "100m", "150m", "198m", "250m", "300m", "396m"};
++ "24m", "100m", "150m", "198m", "250m", "300m", "396m"
++};
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
+
+static const char *mmc_mux_p[] __initdata = {
-+ "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"};
++ "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"
++};
+static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static const char *sysapb_mux_p[] __initdata = {
-+ "24m", "50m",};
++ "24m", "50m",
++};
+static u32 sysapb_mux_table[] = {0, 1};
+
+static const char *sysbus_mux_p[] __initdata = {
-+ "24m", "300m"};
++ "24m", "300m"
++};
+static u32 sysbus_mux_table[] = {0, 1};
+
+static const char *uart_mux_p[] __initdata = {"50m", "24m", "3m"};
+static u32 uart_mux_table[] = {0, 1, 2};
+
+static const char *a53_1_clksel_mux_p[] __initdata = {
-+ "24m", "apll", "vpll", "792m"};
++ "24m", "apll", "vpll", "792m"
++};
+static u32 a53_1_clksel_mux_table[] = {0, 1, 2, 3};
+
+static struct hisi_mux_clock hi3519av100_mux_clks[] __initdata = {
-+ { HI3519AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table, },
++ {
++ HI3519AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
++ },
+
-+ { HI3519AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3519AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3519AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3519AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3519AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3519AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3519AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table},
++ {
++ HI3519AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
++ CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
++ },
+
-+ { HI3519AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table},
++ {
++ HI3519AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
++ CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table
++ },
+
-+ { HI3519AV100_UART0_MUX, "uart0_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART1_MUX, "uart1_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART2_MUX, "uart2_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART3_MUX, "uart3_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART4_MUX, "uart4_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART5_MUX, "uart5_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART6_MUX, "uart6_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART7_MUX, "uart7_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_UART8_MUX, "uart8_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table},
-+
-+ { HI3519AV100_A53_1_MUX, "a53_1_mux", a53_1_clksel_mux_p, ARRAY_SIZE(a53_1_clksel_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table},
++ {
++ HI3519AV100_UART0_MUX, "uart0_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART1_MUX, "uart1_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART2_MUX, "uart2_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART3_MUX, "uart3_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART4_MUX, "uart4_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART5_MUX, "uart5_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART6_MUX, "uart6_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART7_MUX, "uart7_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_UART8_MUX, "uart8_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3519AV100_A53_1_MUX, "a53_1_mux", a53_1_clksel_mux_p, ARRAY_SIZE(a53_1_clksel_mux_p),
++ CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table
++ },
+
+};
+
@@ -192863,100 +261447,178 @@ index 0000000..2294f3f
+
+static struct hisi_gate_clock hi3519av100_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3519AV100_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x170, 1, 0, },
++ {
++ HI3519AV100_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x170, 1, 0,
++ },
+ /* mmc */
-+ { HI3519AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x1a8, 28, 0, },
-+ { HI3519AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x1ec, 28, 0, },
-+ { HI3519AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
-+ CLK_SET_RATE_PARENT, 0x214, 28, 0, },
++ {
++ HI3519AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
++ },
++ {
++ HI3519AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
++ },
++ {
++ HI3519AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
++ CLK_SET_RATE_PARENT, 0x214, 28, 0,
++ },
+ /* uart */
-+ { HI3519AV100_UART0_CLK, "clk_uart0", "uart0_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 16, 0, },
-+ { HI3519AV100_UART1_CLK, "clk_uart1", "uart1_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 17, 0, },
-+ { HI3519AV100_UART2_CLK, "clk_uart2", "uart2_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 18, 0, },
-+ { HI3519AV100_UART3_CLK, "clk_uart3", "uart3_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 19, 0, },
-+ { HI3519AV100_UART4_CLK, "clk_uart4", "uart4_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 20, 0, },
-+ { HI3519AV100_UART5_CLK, "clk_uart5", "uart5_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 21, 0, },
-+ { HI3519AV100_UART6_CLK, "clk_uart6", "uart6_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 22, 0, },
-+ { HI3519AV100_UART7_CLK, "clk_uart7", "uart7_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 23, 0, },
-+ { HI3519AV100_UART8_CLK, "clk_uart8", "uart8_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 29, 0, },
++ {
++ HI3519AV100_UART0_CLK, "clk_uart0", "uart0_mux",
++ CLK_SET_RATE_PARENT, 0x198, 16, 0,
++ },
++ {
++ HI3519AV100_UART1_CLK, "clk_uart1", "uart1_mux",
++ CLK_SET_RATE_PARENT, 0x198, 17, 0,
++ },
++ {
++ HI3519AV100_UART2_CLK, "clk_uart2", "uart2_mux",
++ CLK_SET_RATE_PARENT, 0x198, 18, 0,
++ },
++ {
++ HI3519AV100_UART3_CLK, "clk_uart3", "uart3_mux",
++ CLK_SET_RATE_PARENT, 0x198, 19, 0,
++ },
++ {
++ HI3519AV100_UART4_CLK, "clk_uart4", "uart4_mux",
++ CLK_SET_RATE_PARENT, 0x198, 20, 0,
++ },
++ {
++ HI3519AV100_UART5_CLK, "clk_uart5", "uart5_mux",
++ CLK_SET_RATE_PARENT, 0x198, 21, 0,
++ },
++ {
++ HI3519AV100_UART6_CLK, "clk_uart6", "uart6_mux",
++ CLK_SET_RATE_PARENT, 0x198, 22, 0,
++ },
++ {
++ HI3519AV100_UART7_CLK, "clk_uart7", "uart7_mux",
++ CLK_SET_RATE_PARENT, 0x198, 23, 0,
++ },
++ {
++ HI3519AV100_UART8_CLK, "clk_uart8", "uart8_mux",
++ CLK_SET_RATE_PARENT, 0x198, 29, 0,
++ },
+ /* ethernet mac */
-+ { HI3519AV100_ETH_CLK, "clk_eth", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 1, 0, },
-+ { HI3519AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 5, 0, },
++ {
++ HI3519AV100_ETH_CLK, "clk_eth", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 1, 0,
++ },
++ {
++ HI3519AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 5, 0,
++ },
+ /* i2c */
-+ { HI3519AV100_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 16, 0, },
-+ { HI3519AV100_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 17, 0, },
-+ { HI3519AV100_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 18, 0, },
-+ { HI3519AV100_I2C3_CLK, "clk_i2c3", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 19, 0, },
-+ { HI3519AV100_I2C4_CLK, "clk_i2c4", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 20, 0, },
-+ { HI3519AV100_I2C5_CLK, "clk_i2c5", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 21, 0, },
-+ { HI3519AV100_I2C6_CLK, "clk_i2c6", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 22, 0, },
-+ { HI3519AV100_I2C7_CLK, "clk_i2c7", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 23, 0, },
-+ { HI3519AV100_I2C8_CLK, "clk_i2c8", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 24, 0, },
-+ { HI3519AV100_I2C9_CLK, "clk_i2c9", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 25, 0, },
++ {
++ HI3519AV100_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
++ },
++ {
++ HI3519AV100_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
++ },
++ {
++ HI3519AV100_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
++ },
++ {
++ HI3519AV100_I2C3_CLK, "clk_i2c3", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
++ },
++ {
++ HI3519AV100_I2C4_CLK, "clk_i2c4", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
++ },
++ {
++ HI3519AV100_I2C5_CLK, "clk_i2c5", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
++ },
++ {
++ HI3519AV100_I2C6_CLK, "clk_i2c6", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
++ },
++ {
++ HI3519AV100_I2C7_CLK, "clk_i2c7", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
++ },
++ {
++ HI3519AV100_I2C8_CLK, "clk_i2c8", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
++ },
++ {
++ HI3519AV100_I2C9_CLK, "clk_i2c9", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
++ },
+ /* spi */
-+ { HI3519AV100_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 24, 0, },
-+ { HI3519AV100_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 25, 0, },
-+ { HI3519AV100_SPI2_CLK, "clk_spi2", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 26, 0, },
-+ { HI3519AV100_SPI3_CLK, "clk_spi3", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 27, 0, },
-+ { HI3519AV100_SPI4_CLK, "clk_spi4", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 28, 0, },
++ {
++ HI3519AV100_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 24, 0,
++ },
++ {
++ HI3519AV100_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 25, 0,
++ },
++ {
++ HI3519AV100_SPI2_CLK, "clk_spi2", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 26, 0,
++ },
++ {
++ HI3519AV100_SPI3_CLK, "clk_spi3", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 27, 0,
++ },
++ {
++ HI3519AV100_SPI4_CLK, "clk_spi4", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 28, 0,
++ },
+ /* edmac */
-+ { HI3519AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 6, 0, },
-+ { HI3519AV100_EDMAC_CLK, "clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 5, 0, },
-+ { HI3519AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 9, 0, },
-+ { HI3519AV100_EDMAC1_CLK, "clk_edmac1", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 8, 0, },
++ {
++ HI3519AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 6, 0,
++ },
++ {
++ HI3519AV100_EDMAC_CLK, "clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 5, 0,
++ },
++ {
++ HI3519AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 9, 0,
++ },
++ {
++ HI3519AV100_EDMAC1_CLK, "clk_edmac1", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 8, 0,
++ },
+ /* vdmac */
-+ { HI3519AV100_VDMAC_CLK, "clk_vdmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x14c, 5, 0, },
++ {
++ HI3519AV100_VDMAC_CLK, "clk_vdmac", NULL,
++ CLK_SET_RATE_PARENT, 0x14c, 5, 0,
++ },
+ /* dmac */
-+ { HI3519AV100_DMAC0_APB_CLK, "clk_dmac0_apb", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 5, 0, },
-+ { HI3519AV100_DMAC0_AXI_CLK, "clk_dmac0_axi", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 6, 0, },
-+ { HI3519AV100_DMAC1_APB_CLK, "clk_dmac1_apb", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 8, 0, },
-+ { HI3519AV100_DMAC1_AXI_CLK, "clk_dmac1_axi", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 9, 0, },
++ {
++ HI3519AV100_DMAC0_APB_CLK, "clk_dmac0_apb", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 5, 0,
++ },
++ {
++ HI3519AV100_DMAC0_AXI_CLK, "clk_dmac0_axi", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 6, 0,
++ },
++ {
++ HI3519AV100_DMAC1_APB_CLK, "clk_dmac1_apb", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 8, 0,
++ },
++ {
++ HI3519AV100_DMAC1_AXI_CLK, "clk_dmac1_axi", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 9, 0,
++ },
+};
+
+static void hi3519av100_calc_pll(u32 *frac_val,
-+ u32 *postdiv1_val,
-+ u32 *postdiv2_val,
-+ u32 *fbdiv_val,
-+ u32 *refdiv_val,
-+ u64 rate)
++ u32 *postdiv1_val,
++ u32 *postdiv2_val,
++ u32 *fbdiv_val,
++ u32 *refdiv_val,
++ u64 rate)
+{
+ u64 rem;
+ *frac_val = 0;
@@ -192969,8 +261631,8 @@ index 0000000..2294f3f
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw,
-+ unsigned long rate,
-+ unsigned long parent_rate)
++ unsigned long rate,
++ unsigned long parent_rate)
+{
+ struct hi3519av100_clk_pll *clk = to_pll_clk(hw);
+ u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val;
@@ -192980,7 +261642,7 @@ index 0000000..2294f3f
+ postdiv1_val = postdiv2_val = 0;
+
+ hi3519av100_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val,
-+ &fbdiv_val, &refdiv_val, rate);
++ &fbdiv_val, &refdiv_val, rate);
+
+ val = readl_relaxed(clk->ctrl_reg1);
+ val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
@@ -193037,7 +261699,7 @@ index 0000000..2294f3f
+}
+
+static int clk_pll_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
++ struct clk_rate_request *req)
+{
+ return req->rate;
+}
@@ -193055,8 +261717,8 @@ index 0000000..2294f3f
+ int i;
+
+ for (i = 0; i < nums; i++) {
-+ struct hi3519av100_clk_pll *p_clk;
-+ struct clk *clk;
++ struct hi3519av100_clk_pll *p_clk = NULL;
++ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
@@ -193089,7 +261751,7 @@ index 0000000..2294f3f
+ if (IS_ERR(clk)) {
+ kfree(p_clk);
+ pr_err("%s: failed to register clock %s\n",
-+ __func__, clks[i].name);
++ __func__, clks[i].name);
+ continue;
+ }
+
@@ -193108,26 +261770,26 @@ index 0000000..2294f3f
+ hibvt_reset_init(np, HI3519AV100_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3519av100_fixed_rate_clks,
-+ ARRAY_SIZE(hi3519av100_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3519av100_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3519av100_mux_clks, ARRAY_SIZE(hi3519av100_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3519av100_fixed_factor_clks,
-+ ARRAY_SIZE(hi3519av100_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3519av100_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3519av100_gate_clks,
-+ ARRAY_SIZE(hi3519av100_gate_clks), clk_data);
++ ARRAY_SIZE(hi3519av100_gate_clks), clk_data);
+
+ hi3519av100_clk_register_pll(hi3519av100_pll_clks,
-+ ARRAY_SIZE(hi3519av100_pll_clks), clk_data);
++ ARRAY_SIZE(hi3519av100_pll_clks), clk_data);
+}
+
+CLK_OF_DECLARE(hi3519av100_clk, "hisilicon,hi3519av100-clock", hi3519av100_clk_init);
diff --git a/drivers/clk/hisilicon/clk-hi3521a.c b/drivers/clk/hisilicon/clk-hi3521a.c
new file mode 100644
-index 0000000..c94e23d
+index 0000000..85f5636
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3521a.c
-@@ -0,0 +1,246 @@
+@@ -0,0 +1,288 @@
+/*
+ * Hi3521a Clock Driver
+ *
@@ -193160,7 +261822,7 @@ index 0000000..c94e23d
+#include "reset.h"
+
+static const struct
-+hisi_fixed_rate_clock hi3521a_fixed_rate_clks_crg[] __initconst = {
++ hisi_fixed_rate_clock hi3521a_fixed_rate_clks_crg[] __initconst = {
+ { HI3521A_FIXED_2M, "2m", NULL, 0, 2000000, },
+ { HI3521A_FIXED_2P2M, "2.2m", NULL, 0, 2200000, },
+ { HI3521A_FIXED_2P5M, "2.5m", NULL, 0, 2500000, },
@@ -193207,48 +261869,74 @@ index 0000000..c94e23d
+static u32 eth_phy_mux_table[] __initdata = {0, 1};
+
+static const struct hisi_mux_clock hi3521a_mux_clks_crg[] __initconst = {
-+ { HI3521A_SYSAPB_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3521A_SYSAPB_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x34, 12, 2, 0, sysaxi_mux_table, },
-+ { HI3521A_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x74, 2, 2, 0, fmc_mux_table, },
-+ { HI3521A_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x84, 18, 2, 0, uart_mux_table, },
-+ { HI3521A_ETH_PHY_MUX, "eth_phy_mux", eth_phy_mux_p,
++ CLK_SET_RATE_PARENT, 0x34, 12, 2, 0, sysaxi_mux_table,
++ },
++ {
++ HI3521A_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x74, 2, 2, 0, fmc_mux_table,
++ },
++ {
++ HI3521A_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x84, 18, 2, 0, uart_mux_table,
++ },
++ {
++ HI3521A_ETH_PHY_MUX, "eth_phy_mux", eth_phy_mux_p,
+ ARRAY_SIZE(eth_phy_mux_p),
-+ CLK_SET_RATE_PARENT, 0x78, 6, 1, 0, eth_phy_mux_table, },
++ CLK_SET_RATE_PARENT, 0x78, 6, 1, 0, eth_phy_mux_table,
++ },
+};
+
+/* fixed factor clocks */
+static struct hisi_fixed_factor_clock
-+ hi3521a_fixed_factor_clks[] __initdata = {
-+ { HI3521A_SYSAPB_CLK, "clk_sysapb", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT, },
++ hi3521a_fixed_factor_clks[] __initdata = {
++ {
++ HI3521A_SYSAPB_CLK, "clk_sysapb", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT,
++ },
+};
+
+static const struct hisi_gate_clock hi3521a_gate_clks[] __initconst = {
+ /* fmc */
-+ { HI3521A_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x74, 1, 0, },
++ {
++ HI3521A_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x74, 1, 0,
++ },
+
+ /* uart */
-+ { HI3521A_UART0_CLK, "clk_uart0", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x84, 15, 0, },
-+ { HI3521A_UART1_CLK, "clk_uart1", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x84, 16, 0, },
-+ { HI3521A_UART2_CLK, "clk_uart2", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x84, 17, 0, },
++ {
++ HI3521A_UART0_CLK, "clk_uart0", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x84, 15, 0,
++ },
++ {
++ HI3521A_UART1_CLK, "clk_uart1", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x84, 16, 0,
++ },
++ {
++ HI3521A_UART2_CLK, "clk_uart2", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x84, 17, 0,
++ },
+ /* ethernet */
-+ { HI3521A_ETH_CLK, "clk_eth", NULL,
-+ CLK_SET_RATE_PARENT, 0x78, 1, 0, },
-+ { HI3521A_ETH_MACIF_CLK, "clk_eth_macif", NULL,
-+ CLK_SET_RATE_PARENT, 0x78, 3, 0, },
++ {
++ HI3521A_ETH_CLK, "clk_eth", NULL,
++ CLK_SET_RATE_PARENT, 0x78, 1, 0,
++ },
++ {
++ HI3521A_ETH_MACIF_CLK, "clk_eth_macif", NULL,
++ CLK_SET_RATE_PARENT, 0x78, 3, 0,
++ },
+ /* spi */
-+ { HI3521A_SPI0_CLK, "clk_spi0", "sysaxi_mux",
-+ CLK_SET_RATE_PARENT, 0x84, 13, 0, },
++ {
++ HI3521A_SPI0_CLK, "clk_spi0", "sysaxi_mux",
++ CLK_SET_RATE_PARENT, 0x84, 13, 0,
++ },
+ /* dmac */
-+ { HI3521A_DMAC_CLK, "clk_dmac", "50m",
-+ CLK_SET_RATE_PARENT, 0x80, 5, 0, },
++ {
++ HI3521A_DMAC_CLK, "clk_dmac", "50m",
++ CLK_SET_RATE_PARENT, 0x80, 5, 0,
++ },
+};
+
+static void __init hi3521a_clk_crg_init(struct device_node *np)
@@ -193264,27 +261952,27 @@ index 0000000..c94e23d
+ }
+
+ ret = hisi_clk_register_fixed_rate(hi3521a_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3521a_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3521a_fixed_rate_clks_crg), clk_data);
+ if (ret)
+ goto err;
+
+ ret = hisi_clk_register_mux(hi3521a_mux_clks_crg,
-+ ARRAY_SIZE(hi3521a_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3521a_mux_clks_crg), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_fixed_factor(hi3521a_fixed_factor_clks,
-+ ARRAY_SIZE(hi3521a_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3521a_fixed_factor_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = hisi_clk_register_gate(hi3521a_gate_clks,
-+ ARRAY_SIZE(hi3521a_gate_clks), clk_data);
++ ARRAY_SIZE(hi3521a_gate_clks), clk_data);
+ if (ret)
+ goto unregister_factor;
+
+ ret = of_clk_add_provider(np,
-+ of_clk_src_onecell_get, &clk_data->clk_data);
++ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
@@ -193296,59 +261984,75 @@ index 0000000..c94e23d
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3521a_gate_clks,
-+ ARRAY_SIZE(hi3521a_gate_clks), clk_data);
++ ARRAY_SIZE(hi3521a_gate_clks), clk_data);
+unregister_factor:
+ hisi_clk_unregister_fixed_factor(hi3521a_fixed_factor_clks,
-+ ARRAY_SIZE(hi3521a_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3521a_fixed_factor_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3521a_mux_clks_crg,
-+ ARRAY_SIZE(hi3521a_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3521a_mux_clks_crg), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3521a_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3521a_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3521a_fixed_rate_clks_crg), clk_data);
+err:
+ pr_err("%s: failed to init CRG clock\n", __func__);
+ return;
+}
+CLK_OF_DECLARE(hi3521a_clk_crg, "hisilicon,hi3521a-clock",
-+ hi3521a_clk_crg_init);
++ hi3521a_clk_crg_init);
+
+/* clock in system control */
+static const char *const timer_mux_p[] __initconst = {"3m", "clk_sysapb"};
+static u32 timer_mux_table[] __initdata = {0, 1};
+
+static const struct hisi_mux_clock hi3521a_mux_clks_sc_clk[] __initconst = {
-+ { HI3521A_TIME0_0_CLK, "timer00", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 16, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME0_0_CLK, "timer00", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 16, 1, 0, timer_mux_table,
++ },
+
-+ { HI3521A_TIME0_1_CLK, "timer01", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 18, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME0_1_CLK, "timer01", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 18, 1, 0, timer_mux_table,
++ },
+
-+ { HI3521A_TIME1_2_CLK, "timer12", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 20, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME1_2_CLK, "timer12", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 20, 1, 0, timer_mux_table,
++ },
+
-+ { HI3521A_TIME1_3_CLK, "timer13", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 22, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME1_3_CLK, "timer13", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 22, 1, 0, timer_mux_table,
++ },
+
-+ { HI3521A_TIME2_4_CLK, "timer24", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 25, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME2_4_CLK, "timer24", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 25, 1, 0, timer_mux_table,
++ },
+
-+ { HI3521A_TIME2_5_CLK, "timer25", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 27, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME2_5_CLK, "timer25", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 27, 1, 0, timer_mux_table,
++ },
+
-+ { HI3521A_TIME3_6_CLK, "timer36", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 29, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME3_6_CLK, "timer36", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 29, 1, 0, timer_mux_table,
++ },
+
-+ { HI3521A_TIME3_7_CLK, "timer37", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 31, 1, 0, timer_mux_table, },
++ {
++ HI3521A_TIME3_7_CLK, "timer37", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 31, 1, 0, timer_mux_table,
++ },
+};
+
+static void __init hi3521a_sc_clk_init(struct device_node *np)
@@ -193359,27 +262063,27 @@ index 0000000..c94e23d
+ clk_data = hisi_clk_init(np, HI3521A_SC_NR_CLKS);
+ if (!clk_data) {
+ pr_err("%s: failed to allocate %s clock data\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+
+ ret = hisi_clk_register_mux(hi3521a_mux_clks_sc_clk,
-+ ARRAY_SIZE(hi3521a_mux_clks_sc_clk), clk_data);
++ ARRAY_SIZE(hi3521a_mux_clks_sc_clk), clk_data);
+ if (ret) {
+ pr_err("%s: failed to register %s mux clock\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+}
+
+CLK_OF_DECLARE(hi3521a_clk_sysctrl, "hisilicon,sysctrl",
-+ hi3521a_sc_clk_init);
++ hi3521a_sc_clk_init);
diff --git a/drivers/clk/hisilicon/clk-hi3531a.c b/drivers/clk/hisilicon/clk-hi3531a.c
new file mode 100644
-index 0000000..ddf4c8d
+index 0000000..edccb9a
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3531a.c
-@@ -0,0 +1,271 @@
+@@ -0,0 +1,323 @@
+/*
+ * Hi3531a Clock Driver
+ *
@@ -193412,7 +262116,7 @@ index 0000000..ddf4c8d
+#include "reset.h"
+
+static const struct
-+hisi_fixed_rate_clock hi3531a_fixed_rate_clks_crg[] __initconst = {
++ hisi_fixed_rate_clock hi3531a_fixed_rate_clks_crg[] __initconst = {
+ { HI3531A_FIXED_2M, "2m", NULL, 0, 2000000, },
+ { HI3531A_FIXED_2P02M, "2.02m", NULL, 0, 2020000, },
+ { HI3531A_FIXED_2P5M, "2.5m", NULL, 0, 2500000, },
@@ -193467,65 +262171,101 @@ index 0000000..ddf4c8d
+
+static const struct hisi_mux_clock hi3531a_mux_clks_crg[] __initconst = {
+ /* bus mux clock */
-+ { HI3531A_PERIAXI_CLK, "periaxi_mux", periaxi_mux_p,
++ {
++ HI3531A_PERIAXI_CLK, "periaxi_mux", periaxi_mux_p,
+ ARRAY_SIZE(periaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x50, 0, 2, 0, periaxi_mux_table, },
-+ { HI3531A_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ CLK_SET_RATE_PARENT, 0x50, 0, 2, 0, periaxi_mux_table,
++ },
++ {
++ HI3531A_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x50, 2, 2, 0, sysaxi_mux_table, },
++ CLK_SET_RATE_PARENT, 0x50, 2, 2, 0, sysaxi_mux_table,
++ },
+ /* fmc(spi nor and spi nand) mux clock */
-+ { HI3531A_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, fmc_mux_table, },
++ {
++ HI3531A_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, fmc_mux_table,
++ },
+ /* parallel nand mux clock */
-+ { HI3531A_NFC_MUX, "nfc_mux", nfc_mux_p, ARRAY_SIZE(nfc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x13c, 2, 1, 0, nfc_mux_table, },
++ {
++ HI3531A_NFC_MUX, "nfc_mux", nfc_mux_p, ARRAY_SIZE(nfc_mux_p),
++ CLK_SET_RATE_PARENT, 0x13c, 2, 1, 0, nfc_mux_table,
++ },
+ /* uart mux clock */
-+ { HI3531A_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x154, 19, 2, 0, uart_mux_table, },
++ {
++ HI3531A_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x154, 19, 2, 0, uart_mux_table,
++ },
+ /* ethernet PHY clock */
-+ { HI3531A_ETH_PHY_MUX, "eth_phy_mux", eth_phy_mux_p,
++ {
++ HI3531A_ETH_PHY_MUX, "eth_phy_mux", eth_phy_mux_p,
+ ARRAY_SIZE(eth_phy_mux_p),
-+ CLK_SET_RATE_PARENT, 0x14c, 6, 1, 0, eth_phy_mux_table, },
++ CLK_SET_RATE_PARENT, 0x14c, 6, 1, 0, eth_phy_mux_table,
++ },
+};
+
+/* fixed factor clocks */
+static struct hisi_fixed_factor_clock
-+ hi3531a_fixed_factor_clks[] __initdata = {
-+ { HI3531A_SYSAXI_CLK, "clk_sysapb", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT, },
-+ { HI3531A_PERIAXI_CLK, "clk_periaxi", "periaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT, },
++ hi3531a_fixed_factor_clks[] __initdata = {
++ {
++ HI3531A_SYSAXI_CLK, "clk_sysapb", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT,
++ },
++ {
++ HI3531A_PERIAXI_CLK, "clk_periaxi", "periaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT,
++ },
+};
+
+static const struct hisi_gate_clock hi3531a_gate_clks[] __initconst = {
+ /* fmc */
-+ { HI3531A_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x148, 1, 0, },
++ {
++ HI3531A_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x148, 1, 0,
++ },
+
+ /* nfc */
-+ { HI3531A_NFC_CLK, "clk_nfc", "nfc_mux",
-+ CLK_SET_RATE_PARENT, 0x13c, 1, 0, },
++ {
++ HI3531A_NFC_CLK, "clk_nfc", "nfc_mux",
++ CLK_SET_RATE_PARENT, 0x13c, 1, 0,
++ },
+
+ /* uart */
-+ { HI3531A_UART0_CLK, "clk_uart0", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 15, 0, },
-+ { HI3531A_UART1_CLK, "clk_uart1", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 16, 0, },
-+ { HI3531A_UART2_CLK, "clk_uart2", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 17, 0, },
-+ { HI3531A_UART2_CLK, "clk_uart3", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 18, 0, },
++ {
++ HI3531A_UART0_CLK, "clk_uart0", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x154, 15, 0,
++ },
++ {
++ HI3531A_UART1_CLK, "clk_uart1", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x154, 16, 0,
++ },
++ {
++ HI3531A_UART2_CLK, "clk_uart2", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x154, 17, 0,
++ },
++ {
++ HI3531A_UART2_CLK, "clk_uart3", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x154, 18, 0,
++ },
+ /* ethernet */
-+ { HI3531A_ETH_CLK, "clk_eth", NULL,
-+ CLK_SET_RATE_PARENT, 0x14c, 1, 0, },
-+ { HI3531A_ETH_MACIF_CLK, "clk_eth_macif", NULL,
-+ CLK_SET_RATE_PARENT, 0x14c, 3, 0, },
++ {
++ HI3531A_ETH_CLK, "clk_eth", NULL,
++ CLK_SET_RATE_PARENT, 0x14c, 1, 0,
++ },
++ {
++ HI3531A_ETH_MACIF_CLK, "clk_eth_macif", NULL,
++ CLK_SET_RATE_PARENT, 0x14c, 3, 0,
++ },
+ /* spi */
-+ { HI3531A_SPI0_CLK, "clk_spi0", "periaxi_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 13, 0, },
++ {
++ HI3531A_SPI0_CLK, "clk_spi0", "periaxi_mux",
++ CLK_SET_RATE_PARENT, 0x154, 13, 0,
++ },
+ /* dmac */
-+ { HI3531A_DMAC_CLK, "clk_dmac", "50m",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3531A_DMAC_CLK, "clk_dmac", "50m",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+};
+
+static void __init hi3531a_clk_crg_init(struct device_node *np)
@@ -193541,27 +262281,27 @@ index 0000000..ddf4c8d
+ }
+
+ ret = hisi_clk_register_fixed_rate(hi3531a_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3531a_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3531a_fixed_rate_clks_crg), clk_data);
+ if (ret)
+ goto err;
+
+ ret = hisi_clk_register_mux(hi3531a_mux_clks_crg,
-+ ARRAY_SIZE(hi3531a_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3531a_mux_clks_crg), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_fixed_factor(hi3531a_fixed_factor_clks,
-+ ARRAY_SIZE(hi3531a_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3531a_fixed_factor_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = hisi_clk_register_gate(hi3531a_gate_clks,
-+ ARRAY_SIZE(hi3531a_gate_clks), clk_data);
++ ARRAY_SIZE(hi3531a_gate_clks), clk_data);
+ if (ret)
+ goto unregister_factor;
+
+ ret = of_clk_add_provider(np,
-+ of_clk_src_onecell_get, &clk_data->clk_data);
++ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
@@ -193573,59 +262313,75 @@ index 0000000..ddf4c8d
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3531a_gate_clks,
-+ ARRAY_SIZE(hi3531a_gate_clks), clk_data);
++ ARRAY_SIZE(hi3531a_gate_clks), clk_data);
+unregister_factor:
+ hisi_clk_unregister_fixed_factor(hi3531a_fixed_factor_clks,
-+ ARRAY_SIZE(hi3531a_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3531a_fixed_factor_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3531a_mux_clks_crg,
-+ ARRAY_SIZE(hi3531a_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3531a_mux_clks_crg), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3531a_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3531a_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3531a_fixed_rate_clks_crg), clk_data);
+err:
+ pr_err("%s: failed to init CRG clock\n", __func__);
+ return;
+}
+CLK_OF_DECLARE(hi3531a_clk_crg, "hisilicon,hi3531a-clock",
-+ hi3531a_clk_crg_init);
++ hi3531a_clk_crg_init);
+
+/* clock in system control */
+static const char *const timer_mux_p[] __initconst = {"3m", "clk_periaxi"};
+static u32 timer_mux_table[] __initdata = {0, 1};
+
+static const struct hisi_mux_clock hi3531a_mux_clks_sc_clk[] __initconst = {
-+ { HI3531A_TIME0_0_CLK, "timer00", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 16, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME0_0_CLK, "timer00", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 16, 1, 0, timer_mux_table,
++ },
+
-+ { HI3531A_TIME0_1_CLK, "timer01", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 18, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME0_1_CLK, "timer01", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 18, 1, 0, timer_mux_table,
++ },
+
-+ { HI3531A_TIME1_2_CLK, "timer12", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 20, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME1_2_CLK, "timer12", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 20, 1, 0, timer_mux_table,
++ },
+
-+ { HI3531A_TIME1_3_CLK, "timer13", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 22, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME1_3_CLK, "timer13", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 22, 1, 0, timer_mux_table,
++ },
+
-+ { HI3531A_TIME2_4_CLK, "timer24", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 25, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME2_4_CLK, "timer24", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 25, 1, 0, timer_mux_table,
++ },
+
-+ { HI3531A_TIME2_5_CLK, "timer25", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 27, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME2_5_CLK, "timer25", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 27, 1, 0, timer_mux_table,
++ },
+
-+ { HI3531A_TIME3_6_CLK, "timer36", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 29, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME3_6_CLK, "timer36", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 29, 1, 0, timer_mux_table,
++ },
+
-+ { HI3531A_TIME3_7_CLK, "timer37", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 31, 1, 0, timer_mux_table, },
++ {
++ HI3531A_TIME3_7_CLK, "timer37", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 31, 1, 0, timer_mux_table,
++ },
+};
+
+static void __init hi3531a_sc_clk_init(struct device_node *np)
@@ -193636,27 +262392,27 @@ index 0000000..ddf4c8d
+ clk_data = hisi_clk_init(np, HI3531A_SYS_NR_CLKS);
+ if (!clk_data) {
+ pr_err("%s: failed to allocate %s clock data\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+
+ ret = hisi_clk_register_mux(hi3531a_mux_clks_sc_clk,
-+ ARRAY_SIZE(hi3531a_mux_clks_sc_clk), clk_data);
++ ARRAY_SIZE(hi3531a_mux_clks_sc_clk), clk_data);
+ if (ret) {
+ pr_err("%s: failed to register %s mux clock\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+}
+
+CLK_OF_DECLARE(hi3531a_clk_sysctrl, "hisilicon,sysctrl",
-+ hi3531a_sc_clk_init);
++ hi3531a_sc_clk_init);
diff --git a/drivers/clk/hisilicon/clk-hi3536dv100.c b/drivers/clk/hisilicon/clk-hi3536dv100.c
new file mode 100644
-index 0000000..9b733db
+index 0000000..2a597fc
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3536dv100.c
-@@ -0,0 +1,229 @@
+@@ -0,0 +1,270 @@
+/*
+ * Hi3536DV100 Clock Driver
+ *
@@ -193687,7 +262443,7 @@ index 0000000..9b733db
+#include "reset.h"
+
+static const struct
-+hisi_fixed_rate_clock hi3536dv100_fixed_rate_clks_crg[] __initconst = {
++ hisi_fixed_rate_clock hi3536dv100_fixed_rate_clks_crg[] __initconst = {
+ { HI3536DV100_FIXED_3M, "3m", NULL, 0, 3000000, },
+ { HI3536DV100_FIXED_6M, "6m", NULL, 0, 6000000, },
+ { HI3536DV100_FIXED_12M, "12m", NULL, 0, 12000000, },
@@ -193713,7 +262469,8 @@ index 0000000..9b733db
+};
+
+static const char *const sysaxi_mux_p[] __initconst = {
-+ "24m", "250m", "200m", "300m"};
++ "24m", "250m", "200m", "300m"
++};
+static const char *const sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *const uart_mux_p[] __initconst = {"sysapb_mux", "24m", "2m"};
+static const char *const fmc_mux_p[] __initconst = {"24m", "83.3m", "150m"};
@@ -193724,43 +262481,67 @@ index 0000000..9b733db
+static u32 fmc_mux_table[] __initdata = {0, 1, 2};
+
+static struct hisi_mux_clock hi3536dv100_mux_clks_crg[] __initdata = {
-+ { HI3536DV100_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3536DV100_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x50, 2, 2, 0, sysaxi_mux_table, },
-+ { HI3536DV100_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x50, 2, 2, 0, sysaxi_mux_table,
++ },
++ {
++ HI3536DV100_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x50, 0, 1, 0, sysapb_mux_table, },
-+ { HI3536DV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, fmc_mux_table, },
-+ { HI3536DV100_UART_MUX, "uart_mux", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x50, 0, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3536DV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, fmc_mux_table,
++ },
++ {
++ HI3536DV100_UART_MUX, "uart_mux", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0xcc, 18, 2, 0, uart_mux_table, },
++ CLK_SET_RATE_PARENT, 0xcc, 18, 2, 0, uart_mux_table,
++ },
+};
+
+static struct hisi_fixed_factor_clock
-+ hi3536dv100_fixed_factor_clks[] __initdata = {
-+ { HI3536DV100_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ hi3536dv100_fixed_factor_clks[] __initdata = {
++ {
++ HI3536DV100_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3536dv100_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3536DV100_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
++ {
++ HI3536DV100_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0xc0, 1, 0,
++ },
+ /* uart */
-+ { HI3536DV100_UART0_CLK, "clk_uart0", "24m",
-+ CLK_SET_RATE_PARENT, 0xcc, 15, 0, },
-+ { HI3536DV100_UART1_CLK, "clk_uart1", "24m",
-+ CLK_SET_RATE_PARENT, 0xcc, 16, 0, },
-+ { HI3536DV100_UART2_CLK, "clk_uart2", "24m",
-+ CLK_SET_RATE_PARENT, 0xcc, 17, 0, },
++ {
++ HI3536DV100_UART0_CLK, "clk_uart0", "24m",
++ CLK_SET_RATE_PARENT, 0xcc, 15, 0,
++ },
++ {
++ HI3536DV100_UART1_CLK, "clk_uart1", "24m",
++ CLK_SET_RATE_PARENT, 0xcc, 16, 0,
++ },
++ {
++ HI3536DV100_UART2_CLK, "clk_uart2", "24m",
++ CLK_SET_RATE_PARENT, 0xcc, 17, 0,
++ },
+ /* ethernet mac */
-+ { HI3536DV100_ETH0_CLK, "clk_eth0", NULL,
-+ CLK_SET_RATE_PARENT, 0xc4, 1, 0, },
-+ { HI3536DV100_ETH0_PHY_CLK, "clk_eth0_phy", NULL,
-+ CLK_SET_RATE_PARENT, 0xc4, 10, 0, },
-+ { HI3536DV100_DMAC_CLK, "clk_dmac", "50m",
-+ CLK_SET_RATE_PARENT, 0xc8, 5, 0, },
++ {
++ HI3536DV100_ETH0_CLK, "clk_eth0", NULL,
++ CLK_SET_RATE_PARENT, 0xc4, 1, 0,
++ },
++ {
++ HI3536DV100_ETH0_PHY_CLK, "clk_eth0_phy", NULL,
++ CLK_SET_RATE_PARENT, 0xc4, 10, 0,
++ },
++ {
++ HI3536DV100_DMAC_CLK, "clk_dmac", "50m",
++ CLK_SET_RATE_PARENT, 0xc8, 5, 0,
++ },
+};
+
+static void __init hi3536dv100_clk_crg_init(struct device_node *np)
@@ -193776,27 +262557,27 @@ index 0000000..9b733db
+ }
+
+ ret = hisi_clk_register_fixed_rate(hi3536dv100_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3536dv100_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3536dv100_fixed_rate_clks_crg), clk_data);
+ if (ret)
+ goto err;
+
+ ret = hisi_clk_register_mux(hi3536dv100_mux_clks_crg,
-+ ARRAY_SIZE(hi3536dv100_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3536dv100_mux_clks_crg), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_fixed_factor(hi3536dv100_fixed_factor_clks,
-+ ARRAY_SIZE(hi3536dv100_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3536dv100_fixed_factor_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = hisi_clk_register_gate(hi3536dv100_gate_clks,
-+ ARRAY_SIZE(hi3536dv100_gate_clks), clk_data);
++ ARRAY_SIZE(hi3536dv100_gate_clks), clk_data);
+ if (ret)
+ goto unregister_factor;
+
+ ret = of_clk_add_provider(np,
-+ of_clk_src_onecell_get, &clk_data->clk_data);
++ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
@@ -193808,59 +262589,75 @@ index 0000000..9b733db
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3536dv100_gate_clks,
-+ ARRAY_SIZE(hi3536dv100_gate_clks), clk_data);
++ ARRAY_SIZE(hi3536dv100_gate_clks), clk_data);
+unregister_factor:
+ hisi_clk_unregister_fixed_factor(hi3536dv100_fixed_factor_clks,
-+ ARRAY_SIZE(hi3536dv100_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3536dv100_fixed_factor_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3536dv100_mux_clks_crg,
-+ ARRAY_SIZE(hi3536dv100_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3536dv100_mux_clks_crg), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3536dv100_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3536dv100_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3536dv100_fixed_rate_clks_crg), clk_data);
+err:
+ pr_err("%s: failed to init CRG clock\n", __func__);
+ return;
+}
+CLK_OF_DECLARE(hi3536dv100_clk_crg, "hisilicon,hi3536dv100-clock",
-+ hi3536dv100_clk_crg_init);
++ hi3536dv100_clk_crg_init);
+
+/* clock in system control */
+static const char *const timer_mux_p[] __initconst = {"3m", "sysapb_mux"};
+static u32 timer_mux_table[] __initdata = {0, 1};
+
+static const struct hisi_mux_clock hi3536dv100_mux_clks_sc_clk[] __initconst = {
-+ { HI3536DV100_TIME0_0_CLK, "timer00", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 16, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME0_0_CLK, "timer00", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 16, 1, 0, timer_mux_table,
++ },
+
-+ { HI3536DV100_TIME0_1_CLK, "timer01", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 18, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME0_1_CLK, "timer01", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 18, 1, 0, timer_mux_table,
++ },
+
-+ { HI3536DV100_TIME1_2_CLK, "timer12", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 20, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME1_2_CLK, "timer12", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 20, 1, 0, timer_mux_table,
++ },
+
-+ { HI3536DV100_TIME1_3_CLK, "timer13", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 22, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME1_3_CLK, "timer13", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 22, 1, 0, timer_mux_table,
++ },
+
-+ { HI3536DV100_TIME2_4_CLK, "timer24", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 25, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME2_4_CLK, "timer24", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 25, 1, 0, timer_mux_table,
++ },
+
-+ { HI3536DV100_TIME2_5_CLK, "timer25", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 27, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME2_5_CLK, "timer25", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 27, 1, 0, timer_mux_table,
++ },
+
-+ { HI3536DV100_TIME3_6_CLK, "timer36", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 29, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME3_6_CLK, "timer36", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 29, 1, 0, timer_mux_table,
++ },
+
-+ { HI3536DV100_TIME3_7_CLK, "timer37", timer_mux_p,
-+ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
-+ 0x0, 31, 1, 0, timer_mux_table, },
++ {
++ HI3536DV100_TIME3_7_CLK, "timer37", timer_mux_p,
++ ARRAY_SIZE(timer_mux_p), CLK_SET_RATE_PARENT,
++ 0x0, 31, 1, 0, timer_mux_table,
++ },
+};
+
+static void __init hi3536dv100_sc_clk_init(struct device_node *np)
@@ -193871,27 +262668,27 @@ index 0000000..9b733db
+ clk_data = hisi_clk_init(np, HI3536DV100_SC_NR_CLKS);
+ if (!clk_data) {
+ pr_err("%s: failed to allocate %s clock data\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+
+ ret = hisi_clk_register_mux(hi3536dv100_mux_clks_sc_clk,
-+ ARRAY_SIZE(hi3536dv100_mux_clks_sc_clk), clk_data);
++ ARRAY_SIZE(hi3536dv100_mux_clks_sc_clk), clk_data);
+ if (ret) {
+ pr_err("%s: failed to register %s mux clock\n",
-+ __func__, np->name);
++ __func__, np->name);
+ return;
+ }
+}
+
+CLK_OF_DECLARE(hi3536dv100_clk_sysctrl, "hisilicon,sysctrl",
-+ hi3536dv100_sc_clk_init);
++ hi3536dv100_sc_clk_init);
diff --git a/drivers/clk/hisilicon/clk-hi3556av100.c b/drivers/clk/hisilicon/clk-hi3556av100.c
new file mode 100644
-index 0000000..fae848f
+index 0000000..e4201d7
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3556av100.c
-@@ -0,0 +1,445 @@
+@@ -0,0 +1,554 @@
+/*
+ * Hi3556A Clock Driver
+ *
@@ -193955,8 +262752,10 @@ index 0000000..fae848f
+};
+
+static struct hi3556av100_pll_clock hi3556av100_pll_clks[] __initdata = {
-+ { HI3556AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
-+ 0x4, 0, 12, 12, 6},
++ {
++ HI3556AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
++ 0x4, 0, 12, 12, 6
++ },
+};
+
+#define to_pll_clk(_hw) container_of(_hw, struct hi3556av100_clk_pll, hw)
@@ -194007,76 +262806,113 @@ index 0000000..fae848f
+
+
+static const char *fmc_mux_p[] __initdata = {
-+ "24m", "100m", "150m", "198m", "250m", "300m", "396m"};
++ "24m", "100m", "150m", "198m", "250m", "300m", "396m"
++};
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
+
+static const char *mmc_mux_p[] __initdata = {
-+ "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"};
++ "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"
++};
+static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static const char *sysapb_mux_p[] __initdata = {
-+ "24m", "50m",};
++ "24m", "50m",
++};
+static u32 sysapb_mux_table[] = {0, 1};
+
+static const char *sysbus_mux_p[] __initdata = {
-+ "24m", "300m"};
++ "24m", "300m"
++};
+static u32 sysbus_mux_table[] = {0, 1};
+
+static const char *uart_mux_p[] __initdata = {"50m", "24m", "3m"};
+static u32 uart_mux_table[] = {0, 1, 2};
+
+static const char *a53_1_clksel_mux_p[] __initdata = {
-+ "24m", "apll", "vpll", "792m"};
++ "24m", "apll", "vpll", "792m"
++};
+static u32 a53_1_clksel_mux_table[] = {0, 1, 2, 3};
+
+static struct hisi_mux_clock hi3556av100_mux_clks[] __initdata = {
-+ { HI3556AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table, },
++ {
++ HI3556AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
++ },
+
-+ { HI3556AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3556AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3556AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3556AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3556AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3556AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3556AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table},
++ {
++ HI3556AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
++ CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
++ },
+
-+ { HI3556AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table},
++ {
++ HI3556AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
++ CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table
++ },
+
-+ { HI3556AV100_UART0_MUX, "uart0_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART1_MUX, "uart1_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART2_MUX, "uart2_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART3_MUX, "uart3_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART4_MUX, "uart4_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART5_MUX, "uart5_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART6_MUX, "uart6_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART7_MUX, "uart7_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_UART8_MUX, "uart8_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table},
-+
-+ { HI3556AV100_A53_1_MUX, "a53_1_mux", a53_1_clksel_mux_p, ARRAY_SIZE(a53_1_clksel_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table},
++ {
++ HI3556AV100_UART0_MUX, "uart0_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART1_MUX, "uart1_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART2_MUX, "uart2_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART3_MUX, "uart3_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART4_MUX, "uart4_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART5_MUX, "uart5_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART6_MUX, "uart6_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART7_MUX, "uart7_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_UART8_MUX, "uart8_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table
++ },
++
++ {
++ HI3556AV100_A53_1_MUX, "a53_1_mux", a53_1_clksel_mux_p, ARRAY_SIZE(a53_1_clksel_mux_p),
++ CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table
++ },
+
+};
+
@@ -194087,91 +262923,161 @@ index 0000000..fae848f
+
+static struct hisi_gate_clock hi3556av100_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3556AV100_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x170, 1, 0, },
++ {
++ HI3556AV100_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x170, 1, 0,
++ },
+ /* mmc */
-+ { HI3556AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x1a8, 28, 0, },
-+ { HI3556AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x1ec, 28, 0, },
-+ { HI3556AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
-+ CLK_SET_RATE_PARENT, 0x214, 28, 0, },
++ {
++ HI3556AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
++ },
++ {
++ HI3556AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
++ },
++ {
++ HI3556AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
++ CLK_SET_RATE_PARENT, 0x214, 28, 0,
++ },
+ /* uart */
-+ { HI3556AV100_UART0_CLK, "clk_uart0", "uart0_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 16, 0, },
-+ { HI3556AV100_UART1_CLK, "clk_uart1", "uart1_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 17, 0, },
-+ { HI3556AV100_UART2_CLK, "clk_uart2", "uart2_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 18, 0, },
-+ { HI3556AV100_UART3_CLK, "clk_uart3", "uart3_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 19, 0, },
-+ { HI3556AV100_UART4_CLK, "clk_uart4", "uart4_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 20, 0, },
-+ { HI3556AV100_UART5_CLK, "clk_uart5", "uart5_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 21, 0, },
-+ { HI3556AV100_UART6_CLK, "clk_uart6", "uart6_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 22, 0, },
-+ { HI3556AV100_UART7_CLK, "clk_uart7", "uart7_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 23, 0, },
-+ { HI3556AV100_UART8_CLK, "clk_uart8", "uart8_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 29, 0, },
++ {
++ HI3556AV100_UART0_CLK, "clk_uart0", "uart0_mux",
++ CLK_SET_RATE_PARENT, 0x198, 16, 0,
++ },
++ {
++ HI3556AV100_UART1_CLK, "clk_uart1", "uart1_mux",
++ CLK_SET_RATE_PARENT, 0x198, 17, 0,
++ },
++ {
++ HI3556AV100_UART2_CLK, "clk_uart2", "uart2_mux",
++ CLK_SET_RATE_PARENT, 0x198, 18, 0,
++ },
++ {
++ HI3556AV100_UART3_CLK, "clk_uart3", "uart3_mux",
++ CLK_SET_RATE_PARENT, 0x198, 19, 0,
++ },
++ {
++ HI3556AV100_UART4_CLK, "clk_uart4", "uart4_mux",
++ CLK_SET_RATE_PARENT, 0x198, 20, 0,
++ },
++ {
++ HI3556AV100_UART5_CLK, "clk_uart5", "uart5_mux",
++ CLK_SET_RATE_PARENT, 0x198, 21, 0,
++ },
++ {
++ HI3556AV100_UART6_CLK, "clk_uart6", "uart6_mux",
++ CLK_SET_RATE_PARENT, 0x198, 22, 0,
++ },
++ {
++ HI3556AV100_UART7_CLK, "clk_uart7", "uart7_mux",
++ CLK_SET_RATE_PARENT, 0x198, 23, 0,
++ },
++ {
++ HI3556AV100_UART8_CLK, "clk_uart8", "uart8_mux",
++ CLK_SET_RATE_PARENT, 0x198, 29, 0,
++ },
+ /* ethernet mac */
-+ { HI3556AV100_ETH_CLK, "clk_eth", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 1, 0, },
-+ { HI3556AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 5, 0, },
++ {
++ HI3556AV100_ETH_CLK, "clk_eth", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 1, 0,
++ },
++ {
++ HI3556AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 5, 0,
++ },
+ /* i2c */
-+ { HI3556AV100_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 16, 0, },
-+ { HI3556AV100_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 17, 0, },
-+ { HI3556AV100_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 18, 0, },
-+ { HI3556AV100_I2C3_CLK, "clk_i2c3", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 19, 0, },
-+ { HI3556AV100_I2C4_CLK, "clk_i2c4", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 20, 0, },
-+ { HI3556AV100_I2C5_CLK, "clk_i2c5", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 21, 0, },
-+ { HI3556AV100_I2C6_CLK, "clk_i2c6", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 22, 0, },
-+ { HI3556AV100_I2C7_CLK, "clk_i2c7", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 23, 0, },
-+ { HI3556AV100_I2C8_CLK, "clk_i2c8", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 24, 0, },
-+ { HI3556AV100_I2C9_CLK, "clk_i2c9", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 25, 0, },
++ {
++ HI3556AV100_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
++ },
++ {
++ HI3556AV100_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
++ },
++ {
++ HI3556AV100_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
++ },
++ {
++ HI3556AV100_I2C3_CLK, "clk_i2c3", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
++ },
++ {
++ HI3556AV100_I2C4_CLK, "clk_i2c4", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
++ },
++ {
++ HI3556AV100_I2C5_CLK, "clk_i2c5", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
++ },
++ {
++ HI3556AV100_I2C6_CLK, "clk_i2c6", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
++ },
++ {
++ HI3556AV100_I2C7_CLK, "clk_i2c7", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
++ },
++ {
++ HI3556AV100_I2C8_CLK, "clk_i2c8", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
++ },
++ {
++ HI3556AV100_I2C9_CLK, "clk_i2c9", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
++ },
+ /* spi */
-+ { HI3556AV100_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 24, 0, },
-+ { HI3556AV100_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 25, 0, },
-+ { HI3556AV100_SPI2_CLK, "clk_spi2", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 26, 0, },
-+ { HI3556AV100_SPI3_CLK, "clk_spi3", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 27, 0, },
-+ { HI3556AV100_SPI4_CLK, "clk_spi4", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 28, 0, },
++ {
++ HI3556AV100_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 24, 0,
++ },
++ {
++ HI3556AV100_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 25, 0,
++ },
++ {
++ HI3556AV100_SPI2_CLK, "clk_spi2", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 26, 0,
++ },
++ {
++ HI3556AV100_SPI3_CLK, "clk_spi3", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 27, 0,
++ },
++ {
++ HI3556AV100_SPI4_CLK, "clk_spi4", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 28, 0,
++ },
+ /* vdmac */
-+ { HI3556AV100_VDMAC_CLK, "clk_vdmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x14c, 5, 0, },
++ {
++ HI3556AV100_VDMAC_CLK, "clk_vdmac", NULL,
++ CLK_SET_RATE_PARENT, 0x14c, 5, 0,
++ },
+ /* dmac */
-+ { HI3556AV100_DMAC0_APB_CLK, "clk_dmac0_apb", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 5, 0, },
-+ { HI3556AV100_DMAC0_AXI_CLK, "clk_dmac0_axi", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 6, 0, },
-+ { HI3556AV100_DMAC1_APB_CLK, "clk_dmac1_apb", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 8, 0, },
-+ { HI3556AV100_DMAC1_AXI_CLK, "clk_dmac1_axi", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 9, 0, },
++ {
++ HI3556AV100_DMAC0_APB_CLK, "clk_dmac0_apb", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 5, 0,
++ },
++ {
++ HI3556AV100_DMAC0_AXI_CLK, "clk_dmac0_axi", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 6, 0,
++ },
++ {
++ HI3556AV100_DMAC1_APB_CLK, "clk_dmac1_apb", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 8, 0,
++ },
++ {
++ HI3556AV100_DMAC1_AXI_CLK, "clk_dmac1_axi", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 9, 0,
++ },
+};
+
+static void hi3556av100_calc_pll(u32 *frac_val,
-+ u32 *postdiv1_val,
-+ u32 *postdiv2_val,
-+ u32 *fbdiv_val,
-+ u32 *refdiv_val,
-+ u64 rate)
++ u32 *postdiv1_val,
++ u32 *postdiv2_val,
++ u32 *fbdiv_val,
++ u32 *refdiv_val,
++ u64 rate)
+{
+ u64 rem;
+ *frac_val = 0;
@@ -194184,8 +263090,8 @@ index 0000000..fae848f
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw,
-+ unsigned long rate,
-+ unsigned long parent_rate)
++ unsigned long rate,
++ unsigned long parent_rate)
+{
+ struct hi3556av100_clk_pll *clk = to_pll_clk(hw);
+ u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val;
@@ -194195,7 +263101,7 @@ index 0000000..fae848f
+ postdiv1_val = postdiv2_val = 0;
+
+ hi3556av100_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val,
-+ &fbdiv_val, &refdiv_val, rate);
++ &fbdiv_val, &refdiv_val, rate);
+
+ val = readl_relaxed(clk->ctrl_reg1);
+ val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
@@ -194252,7 +263158,7 @@ index 0000000..fae848f
+}
+
+static int clk_pll_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
++ struct clk_rate_request *req)
+{
+ return req->rate;
+}
@@ -194270,8 +263176,8 @@ index 0000000..fae848f
+ int i;
+
+ for (i = 0; i < nums; i++) {
-+ struct hi3556av100_clk_pll *p_clk;
-+ struct clk *clk;
++ struct hi3556av100_clk_pll *p_clk = NULL;
++ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
@@ -194304,7 +263210,7 @@ index 0000000..fae848f
+ if (IS_ERR(clk)) {
+ kfree(p_clk);
+ pr_err("%s: failed to register clock %s\n",
-+ __func__, clks[i].name);
++ __func__, clks[i].name);
+ continue;
+ }
+
@@ -194323,26 +263229,26 @@ index 0000000..fae848f
+ hibvt_reset_init(np, HI3556AV100_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3556av100_fixed_rate_clks,
-+ ARRAY_SIZE(hi3556av100_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3556av100_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3556av100_mux_clks, ARRAY_SIZE(hi3556av100_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3556av100_fixed_factor_clks,
-+ ARRAY_SIZE(hi3556av100_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3556av100_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3556av100_gate_clks,
-+ ARRAY_SIZE(hi3556av100_gate_clks), clk_data);
++ ARRAY_SIZE(hi3556av100_gate_clks), clk_data);
+
+ hi3556av100_clk_register_pll(hi3556av100_pll_clks,
-+ ARRAY_SIZE(hi3556av100_pll_clks), clk_data);
++ ARRAY_SIZE(hi3556av100_pll_clks), clk_data);
+}
+
+CLK_OF_DECLARE(hi3556av100_clk, "hisilicon,hi3556av100-clock", hi3556av100_clk_init);
diff --git a/drivers/clk/hisilicon/clk-hi3556v200.c b/drivers/clk/hisilicon/clk-hi3556v200.c
new file mode 100644
-index 0000000..da56b65
+index 0000000..ef60ab4
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3556v200.c
-@@ -0,0 +1,202 @@
+@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -194402,7 +263308,8 @@ index 0000000..da56b65
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m", "300m"};
++ "24m", "200m", "300m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100m", "150m", "163m", "200m", "257m", "300m", "396m"};
@@ -194421,102 +263328,179 @@ index 0000000..da56b65
+static u32 mmc_mux_table[] = {0, 1, 2, 3};
+
+static struct hisi_mux_clock hi3556v200_mux_clks[] __initdata = {
-+ { HI3556V200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3556V200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table, },
-+ { HI3556V200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
++ },
++ {
++ HI3556V200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3556V200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3556V200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table, },
-+ { HI3556V200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table, },
-+ { HI3556V200_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table, },
-+ { HI3556V200_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3556V200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3556V200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3556V200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3556V200_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3556V200_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ //{ HI3556V200_UART1_MUX, "uart_mux1", uart_mux_p,
-+ // ARRAY_SIZE(uart_mux_p),
-+ // CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3556V200_UART2_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ { HI3556V200_UART1_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3556V200_UART3_MUX, "uart_mux3", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
++#endif
++ {
++ HI3556V200_UART2_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table, },
-+ { HI3556V200_UART4_MUX, "uart_mux4", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3556V200_UART3_MUX, "uart_mux3", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table, },
++ CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table,
++ },
++ {
++ HI3556V200_UART4_MUX, "uart_mux4", uart_mux_p,
++ ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
++ },
+#ifdef CONFIG_HISI_FEMAC
+ /* ethernet clock select */
-+ { HI3556V200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
++ {
++ HI3556V200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
+#endif
+};
+
+static struct hisi_fixed_factor_clock hi3556v200_fixed_factor_clks[] __initdata = {
-+ { HI3556V200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3556V200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3556v200_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3556V200_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3556V200_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3556V200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x148, 1, 0, },
-+ { HI3556V200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x160, 1, 0, },
-+ { HI3556V200_MMC2_CLK, "clk_mmc2", "mmc2_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 1, 0, },
++ {
++ HI3556V200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x148, 1, 0,
++ },
++ {
++ HI3556V200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x160, 1, 0,
++ },
++ {
++ HI3556V200_MMC2_CLK, "clk_mmc2", "mmc2_mux",
++ CLK_SET_RATE_PARENT, 0x154, 1, 0,
++ },
+ /* uart */
-+ { HI3556V200_UART0_CLK, "clk_uart0", "uart_mux0",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
-+ { HI3556V200_UART1_CLK, "clk_uart1", "uart_mux1",
-+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3556V200_UART2_CLK, "clk_uart2", "uart_mux2",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
-+ { HI3556V200_UART3_CLK, "clk_uart3", "uart_mux3",
-+ CLK_SET_RATE_PARENT, 0x1b8, 3, 0, },
-+ { HI3556V200_UART4_CLK, "clk_uart4", "uart_mux4",
-+ CLK_SET_RATE_PARENT, 0x1b8, 4, 0, },
-+ /* i2c*/
-+ { HI3556V200_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3556V200_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3556V200_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
-+ { HI3556V200_I2C3_CLK, "clk_i2c3", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 14, 0, },
-+ { HI3556V200_I2C4_CLK, "clk_i2c4", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 15, 0, },
-+ { HI3556V200_I2C5_CLK, "clk_i2c5", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 16, 0, },
-+ { HI3556V200_I2C6_CLK, "clk_i2c6", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 17, 0, },
-+ { HI3556V200_I2C7_CLK, "clk_i2c7", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 18, 0, },
-+ /* spi */
-+ { HI3556V200_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3556V200_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
-+ { HI3556V200_SPI2_CLK, "clk_spi2", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 14, 0, },
++ {
++ HI3556V200_UART0_CLK, "clk_uart0", "uart_mux0",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
++ {
++ HI3556V200_UART1_CLK, "clk_uart1", "uart_mux1",
++ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
++ },
++ {
++ HI3556V200_UART2_CLK, "clk_uart2", "uart_mux2",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
++ {
++ HI3556V200_UART3_CLK, "clk_uart3", "uart_mux3",
++ CLK_SET_RATE_PARENT, 0x1b8, 3, 0,
++ },
++ {
++ HI3556V200_UART4_CLK, "clk_uart4", "uart_mux4",
++ CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
++ },
++ /* i2c*/
++ {
++ HI3556V200_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3556V200_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3556V200_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
++ {
++ HI3556V200_I2C3_CLK, "clk_i2c3", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
++ },
++ {
++ HI3556V200_I2C4_CLK, "clk_i2c4", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
++ },
++ {
++ HI3556V200_I2C5_CLK, "clk_i2c5", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
++ },
++ {
++ HI3556V200_I2C6_CLK, "clk_i2c6", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
++ },
++ {
++ HI3556V200_I2C7_CLK, "clk_i2c7", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
++ },
++ /* spi */
++ {
++ HI3556V200_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3556V200_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
++ {
++ HI3556V200_SPI2_CLK, "clk_spi2", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
++ },
+#ifdef CONFIG_HISI_FEMAC
+ /* ethernet mac */
-+ { HI3556V200_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
++ {
++ HI3556V200_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
+#endif
-+ { HI3556V200_DMAC_CLK, "clk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
-+ { HI3556V200_DMAC_CLK, "axiclk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
++ {
++ HI3556V200_DMAC_CLK, "clk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
++ {
++ HI3556V200_DMAC_CLK, "axiclk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ { HI3556V200_PWM_CLK, "clk_pwm", "pwm_mux",
++ CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
++ },
++#endif
+};
+
+
@@ -194532,14 +263516,14 @@ index 0000000..da56b65
+ hibvt_reset_init(np, HI3556V200_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3556v200_fixed_rate_clks,
-+ ARRAY_SIZE(hi3556v200_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3556v200_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3556v200_mux_clks, ARRAY_SIZE(hi3556v200_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3556v200_fixed_factor_clks,
-+ ARRAY_SIZE(hi3556v200_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3556v200_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3556v200_gate_clks,
-+ ARRAY_SIZE(hi3556v200_gate_clks), clk_data);
++ ARRAY_SIZE(hi3556v200_gate_clks), clk_data);
+
+}
+
@@ -194547,10 +263531,10 @@ index 0000000..da56b65
+
diff --git a/drivers/clk/hisilicon/clk-hi3559av100.c b/drivers/clk/hisilicon/clk-hi3559av100.c
new file mode 100644
-index 0000000..9d72a04
+index 0000000..26fedec
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3559av100.c
-@@ -0,0 +1,728 @@
+@@ -0,0 +1,882 @@
+/*
+ * Hi3559AV100 Clock Driver
+ *
@@ -194619,104 +263603,127 @@ index 0000000..9d72a04
+
+/* soc clk config */
+static const struct hisi_fixed_rate_clock hi3559av100_fixed_rate_clks_crg[] = {
-+ { HI3559AV100_FIXED_1188M , "1188m", NULL, 0, 1188000000, },
-+ { HI3559AV100_FIXED_1000M , "1000m", NULL, 0, 1000000000, },
-+ { HI3559AV100_FIXED_842M , "842m", NULL, 0, 842000000, },
-+ { HI3559AV100_FIXED_792M , "792m", NULL, 0, 792000000, },
-+ { HI3559AV100_FIXED_750M , "750m", NULL, 0, 750000000, },
-+ { HI3559AV100_FIXED_710M , "710m", NULL, 0, 710000000, },
-+ { HI3559AV100_FIXED_680M , "680m", NULL, 0, 680000000, },
-+ { HI3559AV100_FIXED_667M , "667m", NULL, 0, 667000000, },
-+ { HI3559AV100_FIXED_631M , "631m", NULL, 0, 631000000, },
-+ { HI3559AV100_FIXED_600M , "600m", NULL, 0, 600000000, },
-+ { HI3559AV100_FIXED_568M , "568m", NULL, 0, 568000000, },
-+ { HI3559AV100_FIXED_500M , "500m", NULL, 0, 500000000, },
-+ { HI3559AV100_FIXED_475M , "475m", NULL, 0, 475000000, },
-+ { HI3559AV100_FIXED_428M , "428m", NULL, 0, 428000000, },
-+ { HI3559AV100_FIXED_400M , "400m", NULL, 0, 400000000, },
-+ { HI3559AV100_FIXED_396M , "396m", NULL, 0, 396000000, },
-+ { HI3559AV100_FIXED_300M , "300m", NULL, 0, 300000000, },
-+ { HI3559AV100_FIXED_250M , "250m", NULL, 0, 250000000, },
-+ { HI3559AV100_FIXED_200M , "200m", NULL, 0, 200000000, },
-+ { HI3559AV100_FIXED_198M , "198m", NULL, 0, 198000000, },
-+ { HI3559AV100_FIXED_187p5M , "187p5m", NULL, 0, 187500000, },
-+ { HI3559AV100_FIXED_150M , "150m", NULL, 0, 150000000, },
-+ { HI3559AV100_FIXED_148p5M , "148p5m", NULL, 0, 1485000000, },
-+ { HI3559AV100_FIXED_125M , "125m", NULL, 0, 125000000, },
-+ { HI3559AV100_FIXED_107M , "107m", NULL, 0, 107000000, },
-+ { HI3559AV100_FIXED_100M , "100m", NULL, 0, 100000000, },
-+ { HI3559AV100_FIXED_99M , "99m", NULL, 0, 99000000, },
-+ { HI3559AV100_FIXED_75M , "75m" , NULL, 0, 75000000, },
-+ { HI3559AV100_FIXED_74p25M , "74p25m", NULL, 0, 74250000, },
-+ { HI3559AV100_FIXED_72M , "72m", NULL, 0, 72000000, },
-+ { HI3559AV100_FIXED_60M , "60m", NULL, 0, 60000000, },
-+ { HI3559AV100_FIXED_54M , "54m", NULL, 0, 54000000, },
-+ { HI3559AV100_FIXED_50M , "50m", NULL, 0, 50000000, },
-+ { HI3559AV100_FIXED_49p5M , "49p5m", NULL, 0, 49500000, },
-+ { HI3559AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
-+ { HI3559AV100_FIXED_36M , "36m", NULL, 0, 36000000, },
-+ { HI3559AV100_FIXED_32p4M , "32p4m", NULL, 0, 32400000, },
-+ { HI3559AV100_FIXED_27M , "27m", NULL, 0, 27000000, },
-+ { HI3559AV100_FIXED_25M , "25m", NULL, 0, 25000000, },
-+ { HI3559AV100_FIXED_24M , "24m", NULL, 0, 24000000, },
-+ { HI3559AV100_FIXED_12M , "12m", NULL, 0, 12000000, },
-+ { HI3559AV100_FIXED_3M , "3m", NULL, 0, 3000000, },
-+ { HI3559AV100_FIXED_1p6M , "1p6m", NULL, 0, 1600000, },
-+ { HI3559AV100_FIXED_400K , "400k", NULL, 0, 400000, },
-+ { HI3559AV100_FIXED_100K , "100k", NULL, 0, 100000, },
++ { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
++ { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
++ { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
++ { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
++ { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
++ { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
++ { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
++ { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
++ { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
++ { HI3559AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
++ { HI3559AV100_FIXED_568M, "568m", NULL, 0, 568000000, },
++ { HI3559AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
++ { HI3559AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
++ { HI3559AV100_FIXED_428M, "428m", NULL, 0, 428000000, },
++ { HI3559AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
++ { HI3559AV100_FIXED_396M, "396m", NULL, 0, 396000000, },
++ { HI3559AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
++ { HI3559AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
++ { HI3559AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
++ { HI3559AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
++ { HI3559AV100_FIXED_187p5M, "187p5m", NULL, 0, 187500000, },
++ { HI3559AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
++ { HI3559AV100_FIXED_148p5M, "148p5m", NULL, 0, 1485000000, },
++ { HI3559AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
++ { HI3559AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
++ { HI3559AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
++ { HI3559AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
++ { HI3559AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
++ { HI3559AV100_FIXED_74p25M, "74p25m", NULL, 0, 74250000, },
++ { HI3559AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
++ { HI3559AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
++ { HI3559AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
++ { HI3559AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
++ { HI3559AV100_FIXED_49p5M, "49p5m", NULL, 0, 49500000, },
++ { HI3559AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
++ { HI3559AV100_FIXED_36M, "36m", NULL, 0, 36000000, },
++ { HI3559AV100_FIXED_32p4M, "32p4m", NULL, 0, 32400000, },
++ { HI3559AV100_FIXED_27M, "27m", NULL, 0, 27000000, },
++ { HI3559AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
++ { HI3559AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
++ { HI3559AV100_FIXED_12M, "12m", NULL, 0, 12000000, },
++ { HI3559AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
++ { HI3559AV100_FIXED_1p6M, "1p6m", NULL, 0, 1600000, },
++ { HI3559AV100_FIXED_400K, "400k", NULL, 0, 400000, },
++ { HI3559AV100_FIXED_100K, "100k", NULL, 0, 100000, },
+};
+
+
+static const char *fmc_mux_p[] __initdata = {
-+ "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m"};
++ "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m"
++};
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static const char *mmc_mux_p[] __initdata = {
-+ "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"};
++ "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"
++};
+static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static const char *sysapb_mux_p[] __initdata = {
-+ "24m", "50m",};
++ "24m", "50m",
++};
+static u32 sysapb_mux_table[] = {0, 1};
+
+static const char *sysbus_mux_p[] __initdata = {
-+ "24m", "300m"};
++ "24m", "300m"
++};
+static u32 sysbus_mux_table[] = {0, 1};
+
+static const char *uart_mux_p[] __initdata = {"50m", "24m", "3m"};
+static u32 uart_mux_table[] = {0, 1, 2};
+
+static const char *a73_clksel_mux_p[] __initdata = {
-+ "24m", "apll", "1000m"};
++ "24m", "apll", "1000m"
++};
+static u32 a73_clksel_mux_table[] = {0, 1, 2};
+
+static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = {
-+ { HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table, },
++ {
++ HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
++ },
+
-+ { HI3559AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3559AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3559AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3559AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3559AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3559AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3559AV100_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table, },
++ {
++ HI3559AV100_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
++ },
+
-+ { HI3559AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table},
++ {
++ HI3559AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
++ CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
++ },
+
-+ { HI3559AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table},
++ {
++ HI3559AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
++ CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
++ },
+
-+ { HI3559AV100_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table},
++ {
++ HI3559AV100_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
++ },
+
-+ { HI3559AV100_A73_MUX, "a73_mux", a73_clksel_mux_p, ARRAY_SIZE(a73_clksel_mux_p),
-+ CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table},
++ {
++ HI3559AV100_A73_MUX, "a73_mux", a73_clksel_mux_p, ARRAY_SIZE(a73_clksel_mux_p),
++ CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
++ },
+};
+
+static struct hisi_fixed_factor_clock hi3559av100_fixed_factor_clks[] __initdata = {
@@ -194724,101 +263731,181 @@ index 0000000..9d72a04
+
+static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x170, 1, 0, },
++ {
++ HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x170, 1, 0,
++ },
+ /* mmc */
-+ { HI3559AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x1a8, 28, 0, },
-+ { HI3559AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x1ec, 28, 0, },
-+ { HI3559AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
-+ CLK_SET_RATE_PARENT, 0x214, 28, 0, },
-+ { HI3559AV100_MMC3_CLK, "clk_mmc3", "mmc3_mux",
-+ CLK_SET_RATE_PARENT, 0x23c, 28, 0, },
++ {
++ HI3559AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
++ },
++ {
++ HI3559AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
++ },
++ {
++ HI3559AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
++ CLK_SET_RATE_PARENT, 0x214, 28, 0,
++ },
++ {
++ HI3559AV100_MMC3_CLK, "clk_mmc3", "mmc3_mux",
++ CLK_SET_RATE_PARENT, 0x23c, 28, 0,
++ },
+ /* uart */
-+ { HI3559AV100_UART0_CLK, "clk_uart0", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 23, 0, },
-+ { HI3559AV100_UART1_CLK, "clk_uart1", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 24, 0, },
-+ { HI3559AV100_UART2_CLK, "clk_uart2", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 25, 0, },
-+ { HI3559AV100_UART3_CLK, "clk_uart3", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 26, 0, },
-+ { HI3559AV100_UART4_CLK, "clk_uart4", "uart_mux",
-+ CLK_SET_RATE_PARENT, 0x198, 27, 0, },
++ {
++ HI3559AV100_UART0_CLK, "clk_uart0", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x198, 23, 0,
++ },
++ {
++ HI3559AV100_UART1_CLK, "clk_uart1", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x198, 24, 0,
++ },
++ {
++ HI3559AV100_UART2_CLK, "clk_uart2", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x198, 25, 0,
++ },
++ {
++ HI3559AV100_UART3_CLK, "clk_uart3", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x198, 26, 0,
++ },
++ {
++ HI3559AV100_UART4_CLK, "clk_uart4", "uart_mux",
++ CLK_SET_RATE_PARENT, 0x198, 27, 0,
++ },
+ /* ethernet mac */
-+ { HI3559AV100_ETH_CLK, "clk_eth", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 1, 0, },
-+ { HI3559AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 5, 0, },
-+ { HI3559AV100_ETH1_CLK, "clk_eth1", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 3, 0, },
-+ { HI3559AV100_ETH1_MACIF_CLK, "clk_eth1_macif", NULL,
-+ CLK_SET_RATE_PARENT, 0x0174, 7, 0, },
++ {
++ HI3559AV100_ETH_CLK, "clk_eth", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 1, 0,
++ },
++ {
++ HI3559AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 5, 0,
++ },
++ {
++ HI3559AV100_ETH1_CLK, "clk_eth1", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 3, 0,
++ },
++ {
++ HI3559AV100_ETH1_MACIF_CLK, "clk_eth1_macif", NULL,
++ CLK_SET_RATE_PARENT, 0x0174, 7, 0,
++ },
+ /* i2c */
-+ { HI3559AV100_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 16, 0, },
-+ { HI3559AV100_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 17, 0, },
-+ { HI3559AV100_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 18, 0, },
-+ { HI3559AV100_I2C3_CLK, "clk_i2c3", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 19, 0, },
-+ { HI3559AV100_I2C4_CLK, "clk_i2c4", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 20, 0, },
-+ { HI3559AV100_I2C5_CLK, "clk_i2c5", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 21, 0, },
-+ { HI3559AV100_I2C6_CLK, "clk_i2c6", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 22, 0, },
-+ { HI3559AV100_I2C7_CLK, "clk_i2c7", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 23, 0, },
-+ { HI3559AV100_I2C8_CLK, "clk_i2c8", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 24, 0, },
-+ { HI3559AV100_I2C9_CLK, "clk_i2c9", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 25, 0, },
-+ { HI3559AV100_I2C10_CLK, "clk_i2c10", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 26, 0, },
-+ { HI3559AV100_I2C11_CLK, "clk_i2c11", "50m",
-+ CLK_SET_RATE_PARENT, 0x01a0, 27, 0, },
++ {
++ HI3559AV100_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
++ },
++ {
++ HI3559AV100_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
++ },
++ {
++ HI3559AV100_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
++ },
++ {
++ HI3559AV100_I2C3_CLK, "clk_i2c3", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
++ },
++ {
++ HI3559AV100_I2C4_CLK, "clk_i2c4", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
++ },
++ {
++ HI3559AV100_I2C5_CLK, "clk_i2c5", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
++ },
++ {
++ HI3559AV100_I2C6_CLK, "clk_i2c6", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
++ },
++ {
++ HI3559AV100_I2C7_CLK, "clk_i2c7", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
++ },
++ {
++ HI3559AV100_I2C8_CLK, "clk_i2c8", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
++ },
++ {
++ HI3559AV100_I2C9_CLK, "clk_i2c9", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
++ },
++ {
++ HI3559AV100_I2C10_CLK, "clk_i2c10", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 26, 0,
++ },
++ {
++ HI3559AV100_I2C11_CLK, "clk_i2c11", "50m",
++ CLK_SET_RATE_PARENT, 0x01a0, 27, 0,
++ },
+ /* spi */
-+ { HI3559AV100_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 16, 0, },
-+ { HI3559AV100_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 17, 0, },
-+ { HI3559AV100_SPI2_CLK, "clk_spi2", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 18, 0, },
-+ { HI3559AV100_SPI3_CLK, "clk_spi3", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 19, 0, },
-+ { HI3559AV100_SPI4_CLK, "clk_spi4", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 20, 0, },
-+ { HI3559AV100_SPI5_CLK, "clk_spi5", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 21, 0, },
-+ { HI3559AV100_SPI6_CLK, "clk_spi6", "100m",
-+ CLK_SET_RATE_PARENT, 0x0198, 22, 0, },
++ {
++ HI3559AV100_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 16, 0,
++ },
++ {
++ HI3559AV100_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 17, 0,
++ },
++ {
++ HI3559AV100_SPI2_CLK, "clk_spi2", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 18, 0,
++ },
++ {
++ HI3559AV100_SPI3_CLK, "clk_spi3", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 19, 0,
++ },
++ {
++ HI3559AV100_SPI4_CLK, "clk_spi4", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 20, 0,
++ },
++ {
++ HI3559AV100_SPI5_CLK, "clk_spi5", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 21, 0,
++ },
++ {
++ HI3559AV100_SPI6_CLK, "clk_spi6", "100m",
++ CLK_SET_RATE_PARENT, 0x0198, 22, 0,
++ },
+ /* edmac */
-+ { HI3559AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 6, 0, },
-+ { HI3559AV100_EDMAC_CLK, "clk_edmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 5, 0, },
-+ { HI3559AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 9, 0, },
-+ { HI3559AV100_EDMAC1_CLK, "clk_edmac1", NULL,
-+ CLK_SET_RATE_PARENT, 0x16c, 8, 0, },
++ {
++ HI3559AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 6, 0,
++ },
++ {
++ HI3559AV100_EDMAC_CLK, "clk_edmac", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 5, 0,
++ },
++ {
++ HI3559AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 9, 0,
++ },
++ {
++ HI3559AV100_EDMAC1_CLK, "clk_edmac1", NULL,
++ CLK_SET_RATE_PARENT, 0x16c, 8, 0,
++ },
+ /* vdmac */
-+ { HI3559AV100_VDMAC_CLK, "clk_vdmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x14c, 5, 0, },
++ {
++ HI3559AV100_VDMAC_CLK, "clk_vdmac", NULL,
++ CLK_SET_RATE_PARENT, 0x14c, 5, 0,
++ },
+};
+
+static struct hi3559av100_pll_clock hi3559av100_pll_clks[] __initdata = {
-+ { HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
-+ 0x4, 0, 12, 12, 6},
-+ { HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
-+ 0x24, 0, 12, 12, 6},
++ {
++ HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
++ 0x4, 0, 12, 12, 6
++ },
++ {
++ HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
++ 0x24, 0, 12, 12, 6
++ },
+};
+
+#define to_pll_clk(_hw) container_of(_hw, struct hi3559av100_clk_pll, hw)
+static void hi3559av100_calc_pll(u32 *frac_val, u32 *postdiv1_val, u32 *postdiv2_val,
-+ u32 *fbdiv_val, u32 *refdiv_val, u64 rate)
++ u32 *fbdiv_val, u32 *refdiv_val, u64 rate)
+{
+ u64 rem;
+
@@ -194838,8 +263925,8 @@ index 0000000..9d72a04
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw,
-+ unsigned long rate,
-+ unsigned long parent_rate)
++ unsigned long rate,
++ unsigned long parent_rate)
+{
+ struct hi3559av100_clk_pll *clk = to_pll_clk(hw);
+ u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val;
@@ -194849,7 +263936,7 @@ index 0000000..9d72a04
+ postdiv1_val = postdiv2_val = 0;
+
+ hi3559av100_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val,
-+ &fbdiv_val, &refdiv_val, (u64)rate);
++ &fbdiv_val, &refdiv_val, (u64)rate);
+
+ val = readl_relaxed(clk->ctrl_reg1);
+ val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
@@ -194917,7 +264004,7 @@ index 0000000..9d72a04
+}
+
+static int clk_pll_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
++ struct clk_rate_request *req)
+{
+ return req->rate;
+}
@@ -194929,14 +264016,14 @@ index 0000000..9d72a04
+};
+
+void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
-+ int nums, struct hisi_clock_data *data)
++ int nums, struct hisi_clock_data *data)
+{
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
-+ struct hi3559av100_clk_pll *p_clk;
-+ struct clk *clk;
++ struct hi3559av100_clk_pll *p_clk = NULL;
++ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
@@ -194969,7 +264056,7 @@ index 0000000..9d72a04
+ if (IS_ERR(clk)) {
+ kfree(p_clk);
+ pr_err("%s: failed to register clock %s\n",
-+ __func__, clks[i].name);
++ __func__, clks[i].name);
+ continue;
+ }
+
@@ -194978,7 +264065,7 @@ index 0000000..9d72a04
+}
+
+static __init struct hisi_clock_data *hi3559av100_clk_register(
-+ struct platform_device *pdev)
++ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
@@ -194988,30 +264075,30 @@ index 0000000..9d72a04
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ hisi_clk_register_pll(hi3559av100_pll_clks,
-+ ARRAY_SIZE(hi3559av100_pll_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_pll_clks), clk_data);
+
+ ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg,
-+ ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_fixed_factor(hi3559av100_fixed_factor_clks,
-+ ARRAY_SIZE(hi3559av100_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_fixed_factor_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = hisi_clk_register_gate(hi3559av100_gate_clks,
-+ ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
+ if (ret)
+ goto unregister_factor;
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
-+ of_clk_src_onecell_get, &clk_data->clk_data);
++ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
@@ -195019,16 +264106,16 @@ index 0000000..9d72a04
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3559av100_gate_clks,
-+ ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
+unregister_factor:
+ hisi_clk_unregister_fixed_factor(hi3559av100_fixed_factor_clks,
-+ ARRAY_SIZE(hi3559av100_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_fixed_factor_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
-+ ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
++ ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
++ ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
+ return ERR_PTR(ret);
+}
+
@@ -195039,13 +264126,13 @@ index 0000000..9d72a04
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3559av100_gate_clks,
-+ ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);
+ hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
-+ ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);
+ hisi_clk_unregister_fixed_factor(hi3559av100_fixed_factor_clks,
-+ ARRAY_SIZE(hi3559av100_fixed_factor_clks), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_fixed_factor_clks), crg->clk_data);
+ hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
-+ ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3559av100_crg_funcs = {
@@ -195055,38 +264142,42 @@ index 0000000..9d72a04
+
+#ifdef CONFIG_ACCESS_M7_DEV
+static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] __initdata = {
-+ { HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
-+ { HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
-+ { HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
-+ { HI3559AV100_SHUB_SOURCE_PLL, "clk_source_PLL", NULL, 0, 192000000UL, },
-+ { HI3559AV100_SHUB_I2C0_CLK, "clk_shub_i2c0", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_I2C1_CLK, "clk_shub_i2c1", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_I2C2_CLK, "clk_shub_i2c2", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_I2C3_CLK, "clk_shub_i2c3", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_I2C4_CLK, "clk_shub_i2c4", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_I2C5_CLK, "clk_shub_i2c5", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_I2C6_CLK, "clk_shub_i2c6", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_I2C7_CLK, "clk_shub_i2c7", NULL, 0, 48000000UL, },
-+ { HI3559AV100_SHUB_UART_CLK_32K , "clk_uart_32K", NULL, 0, 32000UL, },
++ { HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
++ { HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
++ { HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
++ { HI3559AV100_SHUB_SOURCE_PLL, "clk_source_PLL", NULL, 0, 192000000UL, },
++ { HI3559AV100_SHUB_I2C0_CLK, "clk_shub_i2c0", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_I2C1_CLK, "clk_shub_i2c1", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_I2C2_CLK, "clk_shub_i2c2", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_I2C3_CLK, "clk_shub_i2c3", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_I2C4_CLK, "clk_shub_i2c4", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_I2C5_CLK, "clk_shub_i2c5", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_I2C6_CLK, "clk_shub_i2c6", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_I2C7_CLK, "clk_shub_i2c7", NULL, 0, 48000000UL, },
++ { HI3559AV100_SHUB_UART_CLK_32K, "clk_uart_32K", NULL, 0, 32000UL, },
+};
+
+/* shub mux clk */
+static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3};
+static const char *shub_source_clk_mux_p[] __initdata = {
-+ "clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL"
++ "clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL"
+};
+
+static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3};
+static const char *shub_uart_source_clk_mux_p[] __initdata = {
-+ "clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M"
++ "clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M"
+};
+
+static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = {
-+ { HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p, ARRAY_SIZE(shub_source_clk_mux_p),
-+ 0, 0x0, 0, 2, 0, shub_source_clk_mux_table, },
++ {
++ HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p, ARRAY_SIZE(shub_source_clk_mux_p),
++ 0, 0x0, 0, 2, 0, shub_source_clk_mux_table,
++ },
+
-+ { HI3559AV100_SHUB_UART_SOURCE_CLK, "shub_uart_source_clk", shub_uart_source_clk_mux_p , ARRAY_SIZE(shub_uart_source_clk_mux_p),
-+ 0, 0x1c, 28, 2, 0, shub_uart_source_clk_mux_table, },
++ {
++ HI3559AV100_SHUB_UART_SOURCE_CLK, "shub_uart_source_clk", shub_uart_source_clk_mux_p, ARRAY_SIZE(shub_uart_source_clk_mux_p),
++ 0, 0x1c, 28, 2, 0, shub_uart_source_clk_mux_table,
++ },
+};
+
+
@@ -195096,71 +264187,118 @@ index 0000000..9d72a04
+struct clk_div_table shub_uart_div_clk_table[] = {{1, 8},{2, 4}};
+
+struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = {
-+ { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2, CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table, },
-+ { HI3559AV100_SHUB_UART_DIV_CLK, "clk_uart_div_clk", "shub_clk", 0, 0x1c, 28, 2, CLK_DIVIDER_ALLOW_ZERO, shub_uart_div_clk_table, },
++ { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2, CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table, },
++ { HI3559AV100_SHUB_UART_DIV_CLK, "clk_uart_div_clk", "shub_clk", 0, 0x1c, 28, 2, CLK_DIVIDER_ALLOW_ZERO, shub_uart_div_clk_table, },
+};
+
+
+/* shub gate clk */
+static struct hisi_gate_clock hi3559av100_shub_gate_clks[] __initdata = {
-+ { HI3559AV100_SHUB_SPI0_CLK , "clk_shub_spi0", "clk_spi_clk",
-+ 0, 0x20, 1, 0, },
-+ { HI3559AV100_SHUB_SPI1_CLK , "clk_shub_spi1", "clk_spi_clk",
-+ 0, 0x20, 5, 0, },
-+ { HI3559AV100_SHUB_SPI2_CLK , "clk_shub_spi2", "clk_spi_clk",
-+ 0, 0x20, 9, 0, },
++ {
++ HI3559AV100_SHUB_SPI0_CLK, "clk_shub_spi0", "clk_spi_clk",
++ 0, 0x20, 1, 0,
++ },
++ {
++ HI3559AV100_SHUB_SPI1_CLK, "clk_shub_spi1", "clk_spi_clk",
++ 0, 0x20, 5, 0,
++ },
++ {
++ HI3559AV100_SHUB_SPI2_CLK, "clk_shub_spi2", "clk_spi_clk",
++ 0, 0x20, 9, 0,
++ },
+
-+ { HI3559AV100_SHUB_UART0_CLK, "clk_shub_uart0", "shub_uart_source_clk",
-+ 0, 0x1c, 1, 0, },
-+ { HI3559AV100_SHUB_UART1_CLK, "clk_shub_uart1", "shub_uart_source_clk",
-+ 0, 0x1c, 5, 0, },
-+ { HI3559AV100_SHUB_UART2_CLK, "clk_shub_uart2", "shub_uart_source_clk",
-+ 0, 0x1c, 9, 0, },
-+ { HI3559AV100_SHUB_UART3_CLK, "clk_shub_uart3", "shub_uart_source_clk",
-+ 0, 0x1c, 13, 0, },
-+ { HI3559AV100_SHUB_UART4_CLK, "clk_shub_uart4", "shub_uart_source_clk",
-+ 0, 0x1c, 17, 0, },
-+ { HI3559AV100_SHUB_UART5_CLK, "clk_shub_uart5", "shub_uart_source_clk",
-+ 0, 0x1c, 21, 0, },
-+ { HI3559AV100_SHUB_UART6_CLK, "clk_shub_uart6", "shub_uart_source_clk",
-+ 0, 0x1c, 25, 0, },
++ {
++ HI3559AV100_SHUB_UART0_CLK, "clk_shub_uart0", "shub_uart_source_clk",
++ 0, 0x1c, 1, 0,
++ },
++ {
++ HI3559AV100_SHUB_UART1_CLK, "clk_shub_uart1", "shub_uart_source_clk",
++ 0, 0x1c, 5, 0,
++ },
++ {
++ HI3559AV100_SHUB_UART2_CLK, "clk_shub_uart2", "shub_uart_source_clk",
++ 0, 0x1c, 9, 0,
++ },
++ {
++ HI3559AV100_SHUB_UART3_CLK, "clk_shub_uart3", "shub_uart_source_clk",
++ 0, 0x1c, 13, 0,
++ },
++ {
++ HI3559AV100_SHUB_UART4_CLK, "clk_shub_uart4", "shub_uart_source_clk",
++ 0, 0x1c, 17, 0,
++ },
++ {
++ HI3559AV100_SHUB_UART5_CLK, "clk_shub_uart5", "shub_uart_source_clk",
++ 0, 0x1c, 21, 0,
++ },
++ {
++ HI3559AV100_SHUB_UART6_CLK, "clk_shub_uart6", "shub_uart_source_clk",
++ 0, 0x1c, 25, 0,
++ },
+
-+ { HI3559AV100_SHUB_EDMAC_CLK, "clk_shub_dmac", "shub_clk",
-+ 0, 0x24, 4, 0, },
++ {
++ HI3559AV100_SHUB_EDMAC_CLK, "clk_shub_dmac", "shub_clk",
++ 0, 0x24, 4, 0,
++ },
+};
+
-+static __init struct hisi_clock_data *hi3559av100_shub_clk_register(
-+ struct platform_device *pdev)
++static int hi3559av100_shub_default_clk_set(void)
+{
-+ struct hisi_clock_data *clk_data;
++ void *crg_base;
++ unsigned int val;
++
++ crg_base = ioremap_nocache(0x18020000, 0x1000);
++
++ /* SSP: 192M/2 */
++ val = readl_relaxed(crg_base + 0x20);
++ val |= (0x2 << 24);
++ writel_relaxed(val, crg_base + 0x20);
++
++ /* UART: 192M/8 */
++ val = readl_relaxed(crg_base + 0x1C);
++ val |= (0x1 << 28);
++ writel_relaxed(val, crg_base + 0x1C);
++
++ iounmap(crg_base);
++ crg_base = NULL;
++
++ return 0;
++}
++
++static __init struct hisi_clock_data *hi3559av100_shub_clk_register(
++ struct platform_device *pdev)
++{
++ struct hisi_clock_data *clk_data = NULL;
+ int ret;
+
++ hi3559av100_shub_default_clk_set();
++
+ clk_data = hisi_clk_alloc(pdev, HI3559AV100_SHUB_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks,
-+ ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = hisi_clk_register_mux(hi3559av100_shub_mux_clks,
-+ ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
-+ ret = hisi_clk_register_divider(hi3559av100_shub_div_clks,
-+ ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
-+ if (ret)
++ ret = hisi_clk_register_divider(hi3559av100_shub_div_clks,
++ ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
++ if (ret)
+ goto unregister_mux;
+
+ ret = hisi_clk_register_gate(hi3559av100_shub_gate_clks,
-+ ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
+ if (ret)
+ goto unregister_factor;
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
-+ of_clk_src_onecell_get, &clk_data->clk_data);
++ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
@@ -195168,16 +264306,16 @@ index 0000000..9d72a04
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
-+ ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
+unregister_factor:
+ hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
-+ ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
-+ ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
-+ ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
++ ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
+ return ERR_PTR(ret);
+}
+
@@ -195188,13 +264326,13 @@ index 0000000..9d72a04
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
-+ ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);
+ hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
-+ ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);
+ hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
-+ ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);
+ hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
-+ ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);
++ ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs = {
@@ -195281,10 +264419,10 @@ index 0000000..9d72a04
+
diff --git a/drivers/clk/hisilicon/clk-hi3559v200.c b/drivers/clk/hisilicon/clk-hi3559v200.c
new file mode 100644
-index 0000000..9bd22c1
+index 0000000..c9d9c55
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3559v200.c
-@@ -0,0 +1,202 @@
+@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -195344,7 +264482,8 @@ index 0000000..9bd22c1
+};
+
+static const char *sysaxi_mux_p[] __initconst = {
-+ "24m", "200m", "300m"};
++ "24m", "200m", "300m"
++};
+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
+static const char *fmc_mux_p[] __initconst = {"24m", "100m", "150m", "163m", "200m", "257m", "300m", "396m"};
@@ -195363,102 +264502,177 @@ index 0000000..9bd22c1
+static u32 mmc_mux_table[] = {0, 1, 2, 3};
+
+static struct hisi_mux_clock hi3559v200_mux_clks[] __initdata = {
-+ { HI3559V200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
++ {
++ HI3559V200_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
+ ARRAY_SIZE(sysaxi_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table, },
-+ { HI3559V200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
++ },
++ {
++ HI3559V200_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
+ ARRAY_SIZE(sysapb_mux_p),
-+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, },
-+ { HI3559V200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, },
-+ { HI3559V200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table, },
-+ { HI3559V200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table, },
-+ { HI3559V200_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
-+ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table, },
-+ { HI3559V200_UART_MUX, "uart_mux0", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
++ },
++ {
++ HI3559V200_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
++ },
++ {
++ HI3559V200_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3559V200_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3559V200_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
++ CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
++ },
++ {
++ HI3559V200_UART_MUX, "uart_mux0", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, },
-+ //{ HI3559V200_UART1_MUX, "uart_mux1", uart_mux_p,
-+ // ARRAY_SIZE(uart_mux_p),
-+ // CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
-+ { HI3559V200_UART2_MUX, "uart_mux2", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
++ },
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ { HI3559V200_UART1_MUX, "uart_mux1", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, },
-+ { HI3559V200_UART3_MUX, "uart_mux3", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, },
++#endif
++ {
++ HI3559V200_UART2_MUX, "uart_mux2", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table, },
-+ { HI3559V200_UART4_MUX, "uart_mux4", uart_mux_p,
++ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
++ },
++ {
++ HI3559V200_UART3_MUX, "uart_mux3", uart_mux_p,
+ ARRAY_SIZE(uart_mux_p),
-+ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table, },
++ CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table,
++ },
++ {
++ HI3559V200_UART4_MUX, "uart_mux4", uart_mux_p,
++ ARRAY_SIZE(uart_mux_p),
++ CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
++ },
+#ifdef CONFIG_HISI_FEMAC
+ /* ethernet clock select */
-+ { HI3559V200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
-+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, },
++ {
++ HI3559V200_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
++ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
++ },
+#endif
+};
+
+static struct hisi_fixed_factor_clock hi3559v200_fixed_factor_clks[] __initdata = {
-+ { HI3559V200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
-+ CLK_SET_RATE_PARENT},
++ {
++ HI3559V200_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
++ CLK_SET_RATE_PARENT
++ },
+};
+
+static struct hisi_gate_clock hi3559v200_gate_clks[] __initdata = {
+ /* fmc */
-+ { HI3559V200_FMC_CLK, "clk_fmc", "fmc_mux",
-+ CLK_SET_RATE_PARENT, 0x144, 1, 0, },
++ {
++ HI3559V200_FMC_CLK, "clk_fmc", "fmc_mux",
++ CLK_SET_RATE_PARENT, 0x144, 1, 0,
++ },
+ /* mmc */
-+ { HI3559V200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
-+ CLK_SET_RATE_PARENT, 0x148, 1, 0, },
-+ { HI3559V200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
-+ CLK_SET_RATE_PARENT, 0x160, 1, 0, },
-+ { HI3559V200_MMC2_CLK, "clk_mmc2", "mmc2_mux",
-+ CLK_SET_RATE_PARENT, 0x154, 1, 0, },
++ {
++ HI3559V200_MMC0_CLK, "clk_mmc0", "mmc0_mux",
++ CLK_SET_RATE_PARENT, 0x148, 1, 0,
++ },
++ {
++ HI3559V200_MMC1_CLK, "clk_mmc1", "mmc1_mux",
++ CLK_SET_RATE_PARENT, 0x160, 1, 0,
++ },
++ {
++ HI3559V200_MMC2_CLK, "clk_mmc2", "mmc2_mux",
++ CLK_SET_RATE_PARENT, 0x154, 1, 0,
++ },
+ /* uart */
-+ { HI3559V200_UART0_CLK, "clk_uart0", "uart_mux0",
-+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0, },
++ {
++ HI3559V200_UART0_CLK, "clk_uart0", "uart_mux0",
++ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
++ },
+ //{ HI3559V200_UART1_CLK, "clk_uart1", "uart_mux1",
+ // CLK_SET_RATE_PARENT, 0x1b8, 1, 0, },
-+ { HI3559V200_UART2_CLK, "clk_uart2", "uart_mux2",
-+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0, },
-+ { HI3559V200_UART3_CLK, "clk_uart3", "uart_mux3",
-+ CLK_SET_RATE_PARENT, 0x1b8, 3, 0, },
-+ { HI3559V200_UART4_CLK, "clk_uart4", "uart_mux4",
-+ CLK_SET_RATE_PARENT, 0x1b8, 4, 0, },
-+ /* i2c*/
-+ { HI3559V200_I2C0_CLK, "clk_i2c0", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0, },
-+ { HI3559V200_I2C1_CLK, "clk_i2c1", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0, },
-+ { HI3559V200_I2C2_CLK, "clk_i2c2", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0, },
-+ { HI3559V200_I2C3_CLK, "clk_i2c3", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 14, 0, },
-+ { HI3559V200_I2C4_CLK, "clk_i2c4", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 15, 0, },
-+ { HI3559V200_I2C5_CLK, "clk_i2c5", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 16, 0, },
-+ { HI3559V200_I2C6_CLK, "clk_i2c6", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 17, 0, },
-+ { HI3559V200_I2C7_CLK, "clk_i2c7", "50m",
-+ CLK_SET_RATE_PARENT, 0x1b8, 18, 0, },
-+ /* spi */
-+ { HI3559V200_SPI0_CLK, "clk_spi0", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0, },
-+ { HI3559V200_SPI1_CLK, "clk_spi1", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0, },
-+ { HI3559V200_SPI2_CLK, "clk_spi2", "100m",
-+ CLK_SET_RATE_PARENT, 0x1bc, 14, 0, },
++ {
++ HI3559V200_UART2_CLK, "clk_uart2", "uart_mux2",
++ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
++ },
++ {
++ HI3559V200_UART3_CLK, "clk_uart3", "uart_mux3",
++ CLK_SET_RATE_PARENT, 0x1b8, 3, 0,
++ },
++ {
++ HI3559V200_UART4_CLK, "clk_uart4", "uart_mux4",
++ CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
++ },
++ /* i2c*/
++ {
++ HI3559V200_I2C0_CLK, "clk_i2c0", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
++ },
++ {
++ HI3559V200_I2C1_CLK, "clk_i2c1", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
++ },
++ {
++ HI3559V200_I2C2_CLK, "clk_i2c2", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
++ },
++ {
++ HI3559V200_I2C3_CLK, "clk_i2c3", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
++ },
++ {
++ HI3559V200_I2C4_CLK, "clk_i2c4", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
++ },
++ {
++ HI3559V200_I2C5_CLK, "clk_i2c5", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
++ },
++ {
++ HI3559V200_I2C6_CLK, "clk_i2c6", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
++ },
++ {
++ HI3559V200_I2C7_CLK, "clk_i2c7", "50m",
++ CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
++ },
++ /* spi */
++ {
++ HI3559V200_SPI0_CLK, "clk_spi0", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
++ },
++ {
++ HI3559V200_SPI1_CLK, "clk_spi1", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
++ },
++ {
++ HI3559V200_SPI2_CLK, "clk_spi2", "100m",
++ CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
++ },
+#ifdef CONFIG_HISI_FEMAC
+ /* ethernet mac */
-+ { HI3559V200_ETH0_CLK, "clk_eth0", "eth_mux",
-+ CLK_SET_RATE_PARENT, 0x16c, 1, 0, },
++ {
++ HI3559V200_ETH0_CLK, "clk_eth0", "eth_mux",
++ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
++ },
+#endif
-+ { HI3559V200_DMAC_CLK, "clk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 1, 0, },
-+ { HI3559V200_DMAC_CLK, "axiclk_dmac", NULL,
-+ CLK_SET_RATE_PARENT, 0x194, 2, 0, },
++ {
++ HI3559V200_DMAC_CLK, "clk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 1, 0,
++ },
++ {
++ HI3559V200_DMAC_CLK, "axiclk_dmac", NULL,
++ CLK_SET_RATE_PARENT, 0x194, 2, 0,
++ },
++#ifndef CONFIG_ARCH_HISI_BVT_AMP
++ { HI3559V200_PWM_CLK, "clk_pwm", "pwm_mux",
++ CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
++ },
++#endif
+};
+
+
@@ -195474,14 +264688,14 @@ index 0000000..9bd22c1
+ hibvt_reset_init(np, HI3559V200_NR_RSTS);
+
+ hisi_clk_register_fixed_rate(hi3559v200_fixed_rate_clks,
-+ ARRAY_SIZE(hi3559v200_fixed_rate_clks),
-+ clk_data);
++ ARRAY_SIZE(hi3559v200_fixed_rate_clks),
++ clk_data);
+ hisi_clk_register_mux(hi3559v200_mux_clks, ARRAY_SIZE(hi3559v200_mux_clks),
-+ clk_data);
++ clk_data);
+ hisi_clk_register_fixed_factor(hi3559v200_fixed_factor_clks,
-+ ARRAY_SIZE(hi3559v200_fixed_factor_clks), clk_data);
++ ARRAY_SIZE(hi3559v200_fixed_factor_clks), clk_data);
+ hisi_clk_register_gate(hi3559v200_gate_clks,
-+ ARRAY_SIZE(hi3559v200_gate_clks), clk_data);
++ ARRAY_SIZE(hi3559v200_gate_clks), clk_data);
+
+}
+
@@ -195672,7 +264886,7 @@ index a2503db..e3bc592 100644
}
diff --git a/drivers/clocksource/timer-hisp804.c b/drivers/clocksource/timer-hisp804.c
new file mode 100644
-index 0000000..b215a37
+index 0000000..dc5bb17
--- /dev/null
+++ b/drivers/clocksource/timer-hisp804.c
@@ -0,0 +1,374 @@
@@ -195728,8 +264942,8 @@ index 0000000..b215a37
+#define TIMER_BGLOAD 0x18 /* CVR rw */
+
+struct hisp804_clocksource {
-+ void __iomem *base;
-+ struct clocksource clksrc;
++ void __iomem *base;
++ struct clocksource clksrc;
+};
+
+#define to_hiclksrc(e) \
@@ -195740,12 +264954,12 @@ index 0000000..b215a37
+static void __iomem *hisp804_sched_clock_base;
+
+struct hisp804_clockevent_device {
-+ struct clock_event_device clkevt;
-+ struct irqaction action;
-+ void __iomem *base;
-+ unsigned long rate;
-+ unsigned long reload;
-+ char name[16];
++ struct clock_event_device clkevt;
++ struct irqaction action;
++ void __iomem *base;
++ unsigned long rate;
++ unsigned long reload;
++ char name[16];
+};
+
+#define to_hiclkevt(e) \
@@ -195757,296 +264971,296 @@ index 0000000..b215a37
+
+static void hisp804_clocksource_enable(void __iomem *base)
+{
-+ writel(0, base + TIMER_CTRL);
-+ writel(0xffffffff, base + TIMER_LOAD);
-+ writel(0xffffffff, base + TIMER_VALUE);
-+ writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
-+ base + TIMER_CTRL);
++ writel(0, base + TIMER_CTRL);
++ writel(0xffffffff, base + TIMER_LOAD);
++ writel(0xffffffff, base + TIMER_VALUE);
++ writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
++ base + TIMER_CTRL);
+}
+/******************************************************************************/
+
+static void hisp804_clocksource_resume(struct clocksource *cs)
+{
-+ hisp804_clocksource_enable(to_hiclksrc(cs)->base);
++ hisp804_clocksource_enable(to_hiclksrc(cs)->base);
+}
+/******************************************************************************/
+
+static u64 notrace hisp804_sched_clock_read(void)
+{
-+ return ~readl_relaxed(hisp804_sched_clock_base + TIMER_VALUE);
++ return ~readl_relaxed(hisp804_sched_clock_base + TIMER_VALUE);
+}
+/******************************************************************************/
+
+static cycle_t hisp804_clocksource_read(struct clocksource *cs)
+{
-+ return ~(cycle_t)readl_relaxed(to_hiclksrc(cs)->base + TIMER_VALUE);
++ return ~(cycle_t)readl_relaxed(to_hiclksrc(cs)->base + TIMER_VALUE);
+}
+/******************************************************************************/
+
+static void __init hisp804_clocksource_init(void __iomem *base,
-+ unsigned long rate)
++ unsigned long rate)
+{
-+ hisp804_clksrc.base = base;
-+ hisp804_clksrc.clksrc.name = "hisp804";
-+ hisp804_clksrc.clksrc.rating = 499;
-+ hisp804_clksrc.clksrc.read = hisp804_clocksource_read;
-+ hisp804_clksrc.clksrc.resume = hisp804_clocksource_resume;
-+ hisp804_clksrc.clksrc.mask = CLOCKSOURCE_MASK(32);
-+ hisp804_clksrc.clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
++ hisp804_clksrc.base = base;
++ hisp804_clksrc.clksrc.name = "hisp804";
++ hisp804_clksrc.clksrc.rating = 499;
++ hisp804_clksrc.clksrc.read = hisp804_clocksource_read;
++ hisp804_clksrc.clksrc.resume = hisp804_clocksource_resume;
++ hisp804_clksrc.clksrc.mask = CLOCKSOURCE_MASK(32);
++ hisp804_clksrc.clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
+
-+ hisp804_clocksource_enable(base);
++ hisp804_clocksource_enable(base);
+
-+ clocksource_register_hz(&hisp804_clksrc.clksrc, rate);
++ clocksource_register_hz(&hisp804_clksrc.clksrc, rate);
+
-+ hisp804_sched_clock_base = base;
-+ sched_clock_register(hisp804_sched_clock_read, 32, rate);
++ hisp804_sched_clock_base = base;
++ sched_clock_register(hisp804_sched_clock_read, 32, rate);
+}
+/******************************************************************************/
+
+static int hisp804_clockevent_shutdown(struct clock_event_device *clkevt)
+{
-+ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
++ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
+
-+ writel(0, hiclkevt->base + TIMER_CTRL);
++ writel(0, hiclkevt->base + TIMER_CTRL);
+
-+ return 0;
++ return 0;
+}
+/******************************************************************************/
+
+static int hisp804_clockevent_set_next_event(unsigned long next,
-+ struct clock_event_device *clkevt)
++ struct clock_event_device *clkevt)
+{
-+ unsigned long ctrl;
-+ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
++ unsigned long ctrl;
++ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
+
-+ writel(TIMER_CTRL_32BIT, hiclkevt->base + TIMER_CTRL);
++ writel(TIMER_CTRL_32BIT, hiclkevt->base + TIMER_CTRL);
+
-+ writel(next, hiclkevt->base + TIMER_LOAD);
-+ writel(next, hiclkevt->base + TIMER_LOAD);
++ writel(next, hiclkevt->base + TIMER_LOAD);
++ writel(next, hiclkevt->base + TIMER_LOAD);
+
-+ ctrl = TIMER_CTRL_32BIT |
-+ TIMER_CTRL_IE |
-+ TIMER_CTRL_ONESHOT |
-+ TIMER_CTRL_ENABLE;
-+ writel(ctrl, hiclkevt->base + TIMER_CTRL);
++ ctrl = TIMER_CTRL_32BIT |
++ TIMER_CTRL_IE |
++ TIMER_CTRL_ONESHOT |
++ TIMER_CTRL_ENABLE;
++ writel(ctrl, hiclkevt->base + TIMER_CTRL);
+
-+ return 0;
++ return 0;
+}
+/******************************************************************************/
+
+static int sp804_clockevent_set_periodic(struct clock_event_device *clkevt)
+{
-+ unsigned long ctrl;
-+ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
++ unsigned long ctrl;
++ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
+
-+ writel(TIMER_CTRL_32BIT, hiclkevt->base + TIMER_CTRL);
++ writel(TIMER_CTRL_32BIT, hiclkevt->base + TIMER_CTRL);
+
-+ writel(hiclkevt->reload, hiclkevt->base + TIMER_LOAD);
-+ writel(hiclkevt->reload, hiclkevt->base + TIMER_LOAD);
++ writel(hiclkevt->reload, hiclkevt->base + TIMER_LOAD);
++ writel(hiclkevt->reload, hiclkevt->base + TIMER_LOAD);
+
-+ ctrl = TIMER_CTRL_32BIT |
-+ TIMER_CTRL_IE |
-+ TIMER_CTRL_PERIODIC |
-+ TIMER_CTRL_ENABLE;
-+ writel(ctrl, hiclkevt->base + TIMER_CTRL);
++ ctrl = TIMER_CTRL_32BIT |
++ TIMER_CTRL_IE |
++ TIMER_CTRL_PERIODIC |
++ TIMER_CTRL_ENABLE;
++ writel(ctrl, hiclkevt->base + TIMER_CTRL);
+
-+ return 0;
++ return 0;
+}
+/******************************************************************************/
+
+static irqreturn_t hisp804_clockevent_timer_interrupt(int irq, void *dev_id)
+{
-+ struct clock_event_device *clkevt = dev_id;
-+ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
++ struct clock_event_device *clkevt = dev_id;
++ struct hisp804_clockevent_device *hiclkevt = to_hiclkevt(clkevt);
+
-+ /* clear the interrupt */
-+ writel(1, hiclkevt->base + TIMER_INTCLR);
++ /* clear the interrupt */
++ writel(1, hiclkevt->base + TIMER_INTCLR);
+
-+ clkevt->event_handler(clkevt);
++ clkevt->event_handler(clkevt);
+
-+ return IRQ_HANDLED;
++ return IRQ_HANDLED;
+}
+/******************************************************************************/
+
+static int hisp804_clockevent_setup(struct hisp804_clockevent_device *hiclkevt)
+{
-+ struct clock_event_device *clkevt = &hiclkevt->clkevt;
++ struct clock_event_device *clkevt = &hiclkevt->clkevt;
+
-+ writel(0, hiclkevt->base + TIMER_CTRL);
++ writel(0, hiclkevt->base + TIMER_CTRL);
+
-+ BUG_ON(setup_irq(clkevt->irq, &hiclkevt->action));
++ BUG_ON(setup_irq(clkevt->irq, &hiclkevt->action));
+
-+ irq_force_affinity(clkevt->irq, clkevt->cpumask);
++ irq_force_affinity(clkevt->irq, clkevt->cpumask);
+
-+ clockevents_config_and_register(clkevt, hiclkevt->rate, 0xf,
-+ 0x7fffffff);
++ clockevents_config_and_register(clkevt, hiclkevt->rate, 0xf,
++ 0x7fffffff);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static void hisp804_clockevent_stop(struct hisp804_clockevent_device *hiclkevt)
+{
-+ struct clock_event_device *clkevt = &hiclkevt->clkevt;
++ struct clock_event_device *clkevt = &hiclkevt->clkevt;
+
-+ pr_info("disable IRQ%d cpu #%d\n", clkevt->irq, smp_processor_id());
++ pr_info("disable IRQ%d cpu #%d\n", clkevt->irq, smp_processor_id());
+
-+ disable_irq(clkevt->irq);
++ disable_irq(clkevt->irq);
+
-+ remove_irq(clkevt->irq, &hiclkevt->action);
++ remove_irq(clkevt->irq, &hiclkevt->action);
+
-+ clkevt->set_state_shutdown(clkevt);
++ clkevt->set_state_shutdown(clkevt);
+}
+/******************************************************************************/
+
+static int hisp804_clockevent_cpu_notify(struct notifier_block *self,
-+ unsigned long action, void *hcpu)
++ unsigned long action, void *hcpu)
+{
-+ /*
-+ * Grab cpu pointer in each case to avoid spurious
-+ * preemptible warnings
-+ */
-+ switch (action & ~CPU_TASKS_FROZEN) {
-+ case CPU_ONLINE:
-+ hisp804_clockevent_setup(this_cpu_ptr(hisp804_clkevt));
-+ break;
-+ case CPU_DEAD:
-+ hisp804_clockevent_stop(this_cpu_ptr(hisp804_clkevt));
-+ break;
-+ }
++ /*
++ * Grab cpu pointer in each case to avoid spurious
++ * preemptible warnings
++ */
++ switch (action & ~CPU_TASKS_FROZEN) {
++ case CPU_ONLINE:
++ hisp804_clockevent_setup(this_cpu_ptr(hisp804_clkevt));
++ break;
++ case CPU_DEAD:
++ hisp804_clockevent_stop(this_cpu_ptr(hisp804_clkevt));
++ break;
++ }
+
-+ return NOTIFY_OK;
++ return NOTIFY_OK;
+}
+/*****************************************************************************/
+
+static struct notifier_block hisp804_clockevent_cpu_nb = {
-+ .notifier_call = hisp804_clockevent_cpu_notify,
++ .notifier_call = hisp804_clockevent_cpu_notify,
+};
+/*****************************************************************************/
+
+static void __init clockevent_init(struct hisp804_clockevent_device *hiclkevt,
-+ void __iomem *base, int irq, int cpu,
-+ unsigned long rate, unsigned long reload)
++ void __iomem *base, int irq, int cpu,
++ unsigned long rate, unsigned long reload)
+{
-+ struct irqaction *action;
-+ struct clock_event_device *clkevt;
++ struct irqaction *action;
++ struct clock_event_device *clkevt;
+
-+ hiclkevt->base = base;
-+ hiclkevt->rate = rate;
-+ hiclkevt->reload = reload;
-+ snprintf(hiclkevt->name, sizeof(hiclkevt->name), "clockevent %d", cpu);
++ hiclkevt->base = base;
++ hiclkevt->rate = rate;
++ hiclkevt->reload = reload;
++ snprintf(hiclkevt->name, sizeof(hiclkevt->name), "clockevent %d", cpu);
+
-+ clkevt = &hiclkevt->clkevt;
++ clkevt = &hiclkevt->clkevt;
+
-+ clkevt->name = hiclkevt->name;
-+ clkevt->cpumask = cpumask_of(cpu);
-+ clkevt->irq = irq;
-+ clkevt->set_next_event = hisp804_clockevent_set_next_event;
-+ clkevt->set_state_shutdown = hisp804_clockevent_shutdown;
-+ clkevt->set_state_periodic = sp804_clockevent_set_periodic;
-+ clkevt->features = CLOCK_EVT_FEAT_PERIODIC |
-+ CLOCK_EVT_FEAT_ONESHOT |
-+ CLOCK_EVT_FEAT_DYNIRQ;
-+ clkevt->rating = 400;
++ clkevt->name = hiclkevt->name;
++ clkevt->cpumask = cpumask_of(cpu);
++ clkevt->irq = irq;
++ clkevt->set_next_event = hisp804_clockevent_set_next_event;
++ clkevt->set_state_shutdown = hisp804_clockevent_shutdown;
++ clkevt->set_state_periodic = sp804_clockevent_set_periodic;
++ clkevt->features = CLOCK_EVT_FEAT_PERIODIC |
++ CLOCK_EVT_FEAT_ONESHOT |
++ CLOCK_EVT_FEAT_DYNIRQ;
++ clkevt->rating = 400;
+
-+ action = &hiclkevt->action;
++ action = &hiclkevt->action;
+
-+ action->name = hiclkevt->name;
-+ action->dev_id = hiclkevt;
-+ action->irq = irq;
-+ action->flags = IRQF_TIMER | IRQF_NOBALANCING;
-+ action->handler = hisp804_clockevent_timer_interrupt;
++ action->name = hiclkevt->name;
++ action->dev_id = hiclkevt;
++ action->irq = irq;
++ action->flags = IRQF_TIMER | IRQF_NOBALANCING;
++ action->handler = hisp804_clockevent_timer_interrupt;
+}
+/******************************************************************************/
+
+static int __init hisp804_timer_init(struct device_node *node)
+{
-+ int ret, irq, ix, nr_cpus;
-+ struct clk *clk1, *clk2;
-+ void __iomem *base;
-+ unsigned long rate1, rate2, reload1, reload2;
++ int ret, irq, ix, nr_cpus;
++ struct clk *clk1, *clk2;
++ void __iomem *base;
++ unsigned long rate1, rate2, reload1, reload2;
+
-+ hisp804_clkevt = alloc_percpu(struct hisp804_clockevent_device);
-+ if (!hisp804_clkevt) {
-+ pr_err("can't alloc memory.\n");
-+ goto out;
-+ }
++ hisp804_clkevt = alloc_percpu(struct hisp804_clockevent_device);
++ if (!hisp804_clkevt) {
++ pr_err("can't alloc memory.\n");
++ goto out;
++ }
+
-+ clk1 = of_clk_get(node, 0);
-+ if (IS_ERR(clk1)) {
-+ goto out_free;
-+ }
++ clk1 = of_clk_get(node, 0);
++ if (IS_ERR(clk1)) {
++ goto out_free;
++ }
+
-+ clk_prepare_enable(clk1);
++ clk_prepare_enable(clk1);
+
-+ rate1 = clk_get_rate(clk1);
-+ reload1 = DIV_ROUND_CLOSEST(rate1, HZ);
++ rate1 = clk_get_rate(clk1);
++ reload1 = DIV_ROUND_CLOSEST(rate1, HZ);
+
-+ /* Get the 2nd clock if the timer has 3 timer clocks */
-+ if (of_count_phandle_with_args(node, "clocks", "#clock-cells") == 3) {
-+ clk2 = of_clk_get(node, 1);
-+ if (IS_ERR(clk2)) {
-+ pr_err("hisp804: %s clock not found: %d\n", node->name,
-+ (int)PTR_ERR(clk2));
-+ goto out_free;
-+ }
-+ clk_prepare_enable(clk2);
-+ rate2 = clk_get_rate(clk2);
-+ reload2 = DIV_ROUND_CLOSEST(rate2, HZ);
-+ } else {
-+ /* clk2 = clk1; */
-+ rate2 = rate1;
-+ reload2 = rate2;
-+ }
++ /* Get the 2nd clock if the timer has 3 timer clocks */
++ if (of_count_phandle_with_args(node, "clocks", "#clock-cells") == 3) {
++ clk2 = of_clk_get(node, 1);
++ if (IS_ERR(clk2)) {
++ pr_err("hisp804: %s clock not found: %d\n", node->name,
++ (int)PTR_ERR(clk2));
++ goto out_free;
++ }
++ clk_prepare_enable(clk2);
++ rate2 = clk_get_rate(clk2);
++ reload2 = DIV_ROUND_CLOSEST(rate2, HZ);
++ } else {
++ /* clk2 = clk1; */
++ rate2 = rate1;
++ reload2 = rate2;
++ }
+
-+ nr_cpus = of_irq_count(node);
-+ if (nr_cpus > num_possible_cpus()) {
-+ nr_cpus = num_possible_cpus();
-+ }
++ nr_cpus = of_irq_count(node);
++ if (nr_cpus > num_possible_cpus()) {
++ nr_cpus = num_possible_cpus();
++ }
+
-+ /* local timer for each CPU */
-+ for (ix = 0; ix < nr_cpus; ix++) {
-+ irq = irq_of_parse_and_map(node, ix);
-+ base = of_iomap(node, ix + 1);
-+ if (!base) {
-+ pr_err("can't iomap timer %d\n", ix);
-+ while (--ix >= 0) {
-+ iounmap(per_cpu_ptr(hisp804_clkevt, ix)->base);
-+ }
-+ goto out_free;
-+ }
++ /* local timer for each CPU */
++ for (ix = 0; ix < nr_cpus; ix++) {
++ irq = irq_of_parse_and_map(node, ix);
++ base = of_iomap(node, ix + 1);
++ if (!base) {
++ pr_err("can't iomap timer %d\n", ix);
++ while (--ix >= 0) {
++ iounmap(per_cpu_ptr(hisp804_clkevt, ix)->base);
++ }
++ goto out_free;
++ }
+
-+ clockevent_init(per_cpu_ptr(hisp804_clkevt, ix), base, irq,
-+ ix, rate2, reload2);
-+ }
++ clockevent_init(per_cpu_ptr(hisp804_clkevt, ix), base, irq,
++ ix, rate2, reload2);
++ }
+
-+ base = of_iomap(node, 0);
-+ if (!base) {
-+ pr_err("can't iomap timer %d\n", 0);
-+ goto out_unmap;
-+ }
++ base = of_iomap(node, 0);
++ if (!base) {
++ pr_err("can't iomap timer %d\n", 0);
++ goto out_unmap;
++ }
+
-+ hisp804_clocksource_init(base, rate1);
++ hisp804_clocksource_init(base, rate1);
+
-+ ret = register_cpu_notifier(&hisp804_clockevent_cpu_nb);
-+ if (ret) {
-+ goto out_notifier;
-+ }
++ ret = register_cpu_notifier(&hisp804_clockevent_cpu_nb);
++ if (ret) {
++ goto out_notifier;
++ }
+
-+ hisp804_clockevent_setup(this_cpu_ptr(hisp804_clkevt));
++ hisp804_clockevent_setup(this_cpu_ptr(hisp804_clkevt));
+
-+ return 0;
++ return 0;
+
+out_notifier:
-+ iounmap(base);
++ iounmap(base);
+out_unmap:
-+ for (ix = 0; ix < nr_irqs; ix++) {
-+ iounmap(per_cpu_ptr(hisp804_clkevt, ix)->base);
-+ }
++ for (ix = 0; ix < nr_irqs; ix++) {
++ iounmap(per_cpu_ptr(hisp804_clkevt, ix)->base);
++ }
+out_free:
-+ free_percpu(hisp804_clkevt);
++ free_percpu(hisp804_clkevt);
+out:
-+ return -ENODEV;
++ return -ENODEV;
+}
+CLOCKSOURCE_OF_DECLARE(hisp804, "hisilicon,hisp804", hisp804_timer_init);
+
@@ -196130,7 +265344,7 @@ index 3ba81b1..1ddd16e 100644
obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o
diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
new file mode 100644
-index 0000000..ccc3288
+index 0000000..ab9ecdf
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-arm64.c
@@ -0,0 +1,244 @@
@@ -196185,54 +265399,54 @@ index 0000000..ccc3288
+#ifdef ARM64_PMC_PWRDN_DEBUG
+static void arm64_cpu_pmc_display_counter(void)
+{
-+ int cpu = smp_processor_id();
-+ unsigned int cluster = cpu >> 1;
-+ unsigned int cpu_pwrdn_cnt;
-+ unsigned int cpu_pwron_cnt;
-+ unsigned int cpu_pwrdn_done_cnt;
-+ unsigned int cluster_pwrdn_cnt = 0;
-+ unsigned int cluster_pwron_cnt = 0;
-+ unsigned int cluster_pwrdn_done_cnt = 0;
-+ static int counter_cpu[4];
-+ static int counter_cluster[4];
-+ void __iomem *pmc_virt = ioremap(CPU_PMC_BASE, PAGE_SIZE * 2);
++ int cpu = smp_processor_id();
++ unsigned int cluster = cpu >> 1;
++ unsigned int cpu_pwrdn_cnt;
++ unsigned int cpu_pwron_cnt;
++ unsigned int cpu_pwrdn_done_cnt;
++ unsigned int cluster_pwrdn_cnt = 0;
++ unsigned int cluster_pwron_cnt = 0;
++ unsigned int cluster_pwrdn_done_cnt = 0;
++ static int counter_cpu[4];
++ static int counter_cluster[4];
++ void __iomem *pmc_virt = ioremap(CPU_PMC_BASE, PAGE_SIZE * 2);
+
-+ writel(0x0, pmc_virt + PMC_CORE_PWRDN_CNT_EN(cpu)); /* disable cpu power on/down counter */
++ writel(0x0, pmc_virt + PMC_CORE_PWRDN_CNT_EN(cpu)); /* disable cpu power on/down counter */
+
-+ cpu_pwrdn_cnt = readl(pmc_virt + PMC_CORE_PWRDN_CNT(cpu));
-+ cpu_pwron_cnt = readl(pmc_virt + PMC_CORE_PWRON_CNT(cpu));
-+ cpu_pwrdn_done_cnt = readl(pmc_virt + PMC_CORE_PWRDN_DONE_CNT(cpu));
++ cpu_pwrdn_cnt = readl(pmc_virt + PMC_CORE_PWRDN_CNT(cpu));
++ cpu_pwron_cnt = readl(pmc_virt + PMC_CORE_PWRON_CNT(cpu));
++ cpu_pwrdn_done_cnt = readl(pmc_virt + PMC_CORE_PWRDN_DONE_CNT(cpu));
+
-+ writel(0x0, pmc_virt + PMC_CORE_PWRDN_CNT(cpu)); /* clean counter */
-+ writel(0x0, pmc_virt + PMC_CORE_PWRON_CNT(cpu));
-+ writel(0x0, pmc_virt + PMC_CORE_PWRDN_DONE_CNT(cpu));
++ writel(0x0, pmc_virt + PMC_CORE_PWRDN_CNT(cpu)); /* clean counter */
++ writel(0x0, pmc_virt + PMC_CORE_PWRON_CNT(cpu));
++ writel(0x0, pmc_virt + PMC_CORE_PWRDN_DONE_CNT(cpu));
+
-+ if (counter_cpu[cpu % 4] % 2000 == 0) {
-+ printk("[%s][%d] cpu[%d] pwrdn_cnt[%8d]us pwron_cnt[%8d]us pwrdn_done_cnt[%8d]us count[%8d][%8d][%8d][%8d]\n", __func__, __LINE__,
-+ cpu, cpu_pwrdn_cnt * 5, cpu_pwron_cnt * 5, cpu_pwrdn_done_cnt * 5,
-+ counter_cpu[0], counter_cpu[1], counter_cpu[2], counter_cpu[3]);
-+ }
-+ counter_cpu[cpu % 4]++;
++ if (counter_cpu[cpu % 4] % 2000 == 0) {
++ printk("[%s][%d] cpu[%d] pwrdn_cnt[%8d]us pwron_cnt[%8d]us pwrdn_done_cnt[%8d]us count[%8d][%8d][%8d][%8d]\n", __func__, __LINE__,
++ cpu, cpu_pwrdn_cnt * 5, cpu_pwron_cnt * 5, cpu_pwrdn_done_cnt * 5,
++ counter_cpu[0], counter_cpu[1], counter_cpu[2], counter_cpu[3]);
++ }
++ counter_cpu[cpu % 4]++;
+
-+ if (readl(pmc_virt + PMC_CLUSTER_PWRDN_CNT_EN(cluster))) {
-+ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_CNT_EN(cluster)); /* disable cluster power on/down counter */
-+ cluster_pwrdn_cnt = readl(pmc_virt + PMC_CLUSTER_PWRDN_CNT(cluster));
-+ cluster_pwron_cnt = readl(pmc_virt + PMC_CLUSTER_PWRON_CNT(cluster));
-+ cluster_pwrdn_done_cnt = readl(pmc_virt + PMC_CLUSTER_PWRDN_DONE_CNT(cluster));
++ if (readl(pmc_virt + PMC_CLUSTER_PWRDN_CNT_EN(cluster))) {
++ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_CNT_EN(cluster)); /* disable cluster power on/down counter */
++ cluster_pwrdn_cnt = readl(pmc_virt + PMC_CLUSTER_PWRDN_CNT(cluster));
++ cluster_pwron_cnt = readl(pmc_virt + PMC_CLUSTER_PWRON_CNT(cluster));
++ cluster_pwrdn_done_cnt = readl(pmc_virt + PMC_CLUSTER_PWRDN_DONE_CNT(cluster));
+
-+ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_CNT(cluster)); /* clean counter */
-+ writel(0x0, pmc_virt + PMC_CLUSTER_PWRON_CNT(cluster));
-+ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_DONE_CNT(cluster));
++ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_CNT(cluster)); /* clean counter */
++ writel(0x0, pmc_virt + PMC_CLUSTER_PWRON_CNT(cluster));
++ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_DONE_CNT(cluster));
+
-+ if (counter_cluster[cluster % 2] % 2000 == 0) {
-+ printk("[%s][%d] cluster[%d] pwrdn_cnt[%8d]us pwron_cnt[%8d]us pwrdn_done_cnt[%8d]us count[%8d][%8d]\n", __func__, __LINE__,
-+ cluster, cluster_pwrdn_cnt * 5, cluster_pwron_cnt * 5, cluster_pwrdn_done_cnt * 5,
-+ counter_cluster[0], counter_cluster[1]);
-+ }
-+ counter_cluster[cluster % 2]++;
-+ }
++ if (counter_cluster[cluster % 2] % 2000 == 0) {
++ printk("[%s][%d] cluster[%d] pwrdn_cnt[%8d]us pwron_cnt[%8d]us pwrdn_done_cnt[%8d]us count[%8d][%8d]\n", __func__, __LINE__,
++ cluster, cluster_pwrdn_cnt * 5, cluster_pwron_cnt * 5, cluster_pwrdn_done_cnt * 5,
++ counter_cluster[0], counter_cluster[1]);
++ }
++ counter_cluster[cluster % 2]++;
++ }
+
-+ iounmap(pmc_virt);
++ iounmap(pmc_virt);
+}
+#endif
+
@@ -196248,84 +265462,84 @@ index 0000000..ccc3288
+ * specified target state selected by the governor.
+ */
+static int arm64_enter_idle_state(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int idx)
++ struct cpuidle_driver *drv, int idx)
+{
-+ int ret;
++ int ret;
+
-+ if (!idx) {
-+ cpu_do_idle();
-+ return idx;
-+ }
++ if (!idx) {
++ cpu_do_idle();
++ return idx;
++ }
+
-+ ret = cpu_pm_enter();
-+ if (!ret) {
-+ /*
-+ * Pass idle state index to cpu_suspend which in turn will
-+ * call the CPU ops suspend protocol with idle index as a
-+ * parameter.
-+ */
-+ ret = arm_cpuidle_suspend(idx);
++ ret = cpu_pm_enter();
++ if (!ret) {
++ /*
++ * Pass idle state index to cpu_suspend which in turn will
++ * call the CPU ops suspend protocol with idle index as a
++ * parameter.
++ */
++ ret = arm_cpuidle_suspend(idx);
+
-+ cpu_pm_exit();
++ cpu_pm_exit();
+
+#ifdef ARM64_PMC_PWRDN_DEBUG
-+ arm64_cpu_pmc_display_counter();
++ arm64_cpu_pmc_display_counter();
+#endif
-+ }
++ }
+
-+ return ret ? -1 : idx;
++ return ret ? -1 : idx;
+}
+
+static struct cpuidle_driver arm64_idle_driver = {
-+ .name = "arm64_idle",
-+ .owner = THIS_MODULE,
-+ /*
-+ * State at index 0 is standby wfi and considered standard
-+ * on all ARM platforms. If in some platforms simple wfi
-+ * can't be used as "state 0", DT bindings must be implemented
-+ * to work around this issue and allow installing a special
-+ * handler for idle state index 0.
-+ */
-+ .states[0] = {
-+ .enter = arm64_enter_idle_state,
-+ .exit_latency = 1,
-+ .target_residency = 1,
-+ .power_usage = UINT_MAX,
-+ .flags = CPUIDLE_FLAG_TIME_VALID,
-+ .name = "WFI",
-+ .desc = "ARM64 WFI",
-+ },
++ .name = "arm64_idle",
++ .owner = THIS_MODULE,
++ /*
++ * State at index 0 is standby wfi and considered standard
++ * on all ARM platforms. If in some platforms simple wfi
++ * can't be used as "state 0", DT bindings must be implemented
++ * to work around this issue and allow installing a special
++ * handler for idle state index 0.
++ */
++ .states[0] = {
++ .enter = arm64_enter_idle_state,
++ .exit_latency = 1,
++ .target_residency = 1,
++ .power_usage = UINT_MAX,
++ .flags = CPUIDLE_FLAG_TIME_VALID,
++ .name = "WFI",
++ .desc = "ARM64 WFI",
++ },
+};
+
+static const struct of_device_id arm64_idle_state_match[] __initconst = {
-+ {
-+ .compatible = "arm,idle-state",
-+ .data = arm64_enter_idle_state
-+ },
-+ { },
++ {
++ .compatible = "arm,idle-state",
++ .data = arm64_enter_idle_state
++ },
++ { },
+};
+
+static void arm64_cpu_pmc_init(int cpu)
+{
-+ void __iomem *pmc_virt = ioremap(CPU_PMC_BASE, PAGE_SIZE * 2);
-+ unsigned int cluster = cpu >> 1;
-+ unsigned int cpu_param = readl(pmc_virt + PMC_CORE_PWRDN_PARAM(cpu));
-+ unsigned int cluster_param = readl(pmc_virt + PMC_CLUSTER_PWRDN_PARAM(cluster));
++ void __iomem *pmc_virt = ioremap(CPU_PMC_BASE, PAGE_SIZE * 2);
++ unsigned int cluster = cpu >> 1;
++ unsigned int cpu_param = readl(pmc_virt + PMC_CORE_PWRDN_PARAM(cpu));
++ unsigned int cluster_param = readl(pmc_virt + PMC_CLUSTER_PWRDN_PARAM(cluster));
+
-+ printk("%s cpu:%d enter\n", __func__, cpu);
++ printk("%s cpu:%d enter\n", __func__, cpu);
+
-+ /* cpu */
-+ cpu_param = (cpu_param & 0xffff) | 0x80800000;
-+ writel(cpu_param, pmc_virt + PMC_CORE_PWRDN_PARAM(cpu)); /* power down/on wait 128ns */
-+ writel(readl(pmc_virt + PMC_CORE_PWRDN_MODE(cpu)) | 0x1, pmc_virt + PMC_CORE_PWRDN_MODE(cpu)); /* cpu auto power off mode */
++ /* cpu */
++ cpu_param = (cpu_param & 0xffff) | 0x80800000;
++ writel(cpu_param, pmc_virt + PMC_CORE_PWRDN_PARAM(cpu)); /* power down/on wait 128ns */
++ writel(readl(pmc_virt + PMC_CORE_PWRDN_MODE(cpu)) | 0x1, pmc_virt + PMC_CORE_PWRDN_MODE(cpu)); /* cpu auto power off mode */
+
-+ /* cluster */
-+ cluster_param = (cluster_param & 0xffff) | 0x01010000;
-+ writel(cluster_param, pmc_virt + PMC_CLUSTER_PWRDN_PARAM(cluster)); /* power down/on wait 100ns */
-+ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_CNT(cluster)); /* clean counter */
-+ writel(readl(pmc_virt + PMC_CLUSTER_PWRDN_MODE(cluster)) | 0x1, pmc_virt + PMC_CLUSTER_PWRDN_MODE(cluster)); /* cluster auto power off mode */
++ /* cluster */
++ cluster_param = (cluster_param & 0xffff) | 0x01010000;
++ writel(cluster_param, pmc_virt + PMC_CLUSTER_PWRDN_PARAM(cluster)); /* power down/on wait 100ns */
++ writel(0x0, pmc_virt + PMC_CLUSTER_PWRDN_CNT(cluster)); /* clean counter */
++ writel(readl(pmc_virt + PMC_CLUSTER_PWRDN_MODE(cluster)) | 0x1, pmc_virt + PMC_CLUSTER_PWRDN_MODE(cluster)); /* cluster auto power off mode */
+
-+ iounmap(pmc_virt);
++ iounmap(pmc_virt);
+}
+
+/*
@@ -196337,50 +265551,50 @@ index 0000000..ccc3288
+ */
+static int __init arm64_idle_init(void)
+{
-+ int cpu, ret;
-+ struct cpuidle_driver *drv = &arm64_idle_driver;
++ int cpu, ret;
++ struct cpuidle_driver *drv = &arm64_idle_driver;
+
-+ /*
-+ * Initialize idle states data, starting at index 1.
-+ * This driver is DT only, if no DT idle states are detected (ret == 0)
-+ * let the driver initialization fail accordingly since there is no
-+ * reason to initialize the idle driver if only wfi is supported.
-+ */
-+ ret = dt_init_idle_driver(drv, arm64_idle_state_match, 1);
-+ if (ret <= 0) {
-+ if (ret) {
-+ pr_err("failed to initialize idle states\n");
-+ }
-+ return ret ? : -ENODEV;
-+ }
++ /*
++ * Initialize idle states data, starting at index 1.
++ * This driver is DT only, if no DT idle states are detected (ret == 0)
++ * let the driver initialization fail accordingly since there is no
++ * reason to initialize the idle driver if only wfi is supported.
++ */
++ ret = dt_init_idle_driver(drv, arm64_idle_state_match, 1);
++ if (ret <= 0) {
++ if (ret) {
++ pr_err("failed to initialize idle states\n");
++ }
++ return ret ? : -ENODEV;
++ }
+
-+ /*
-+ * Call arch CPU operations in order to initialize
-+ * idle states suspend back-end specific data
-+ */
-+ for_each_possible_cpu(cpu) {
++ /*
++ * Call arch CPU operations in order to initialize
++ * idle states suspend back-end specific data
++ */
++ for_each_possible_cpu(cpu) {
+
-+ ret = arm_cpuidle_init(cpu);
-+ if (ret) {
-+ pr_err("CPU %d failed to init idle CPU ops\n", cpu);
-+ return ret;
-+ }
++ ret = arm_cpuidle_init(cpu);
++ if (ret) {
++ pr_err("CPU %d failed to init idle CPU ops\n", cpu);
++ return ret;
++ }
+
-+ arm64_cpu_pmc_init(cpu);
-+ }
++ arm64_cpu_pmc_init(cpu);
++ }
+
-+ ret = cpuidle_register(drv, NULL);
-+ if (ret) {
-+ pr_err("failed to register cpuidle driver\n");
-+ return ret;
-+ }
++ ret = cpuidle_register(drv, NULL);
++ if (ret) {
++ pr_err("failed to register cpuidle driver\n");
++ return ret;
++ }
+
-+ return 0;
++ return 0;
+}
+device_initcall(arm64_idle_init);
diff --git a/drivers/cpuidle/cpuidle-hi3519av100.c b/drivers/cpuidle/cpuidle-hi3519av100.c
new file mode 100644
-index 0000000..8071690
+index 0000000..9908c55
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-hi3519av100.c
@@ -0,0 +1,270 @@
@@ -196439,141 +265653,141 @@ index 0000000..8071690
+extern void hi_pmc_power_up_done(void);
+
+static int bl_cpuidle_simple_enter(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int index);
++ struct cpuidle_driver *drv, int index);
+
+int bl_cpuidle_simple_enter(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int index)
++ struct cpuidle_driver *drv, int index)
+{
+#if defined(CPUIDLE_DEBUG)
-+ int cpuid = smp_processor_id();
-+ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
++ int cpuid = smp_processor_id();
++ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
+#endif
-+ cpu_do_idle();
-+ return index;
++ cpu_do_idle();
++ return index;
+}
+
+static int bl_enter_cpu_powerdown(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int idx);
++ struct cpuidle_driver *drv, int idx);
+
+
+static struct cpuidle_state bl_cpuidle_set[] __initdata = {
-+ [0] = {
-+ .enter = bl_cpuidle_simple_enter,
-+ .exit_latency = 1,
-+ .target_residency = 1,
-+ .power_usage = UINT_MAX,
-+ .flags = CPUIDLE_FLAG_TIME_VALID,
-+ .name = "WFI",
-+ .desc = "ARM WFI",
-+ },
-+ [1] = {
-+ .enter = bl_enter_cpu_powerdown,
-+ .exit_latency = 500,
-+ .target_residency = 1000,
-+ .flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_TIMER_STOP,
-+ .name = "C1",
-+ .desc = "ARM cpu A17 Cluster power down",
-+ },
++ [0] = {
++ .enter = bl_cpuidle_simple_enter,
++ .exit_latency = 1,
++ .target_residency = 1,
++ .power_usage = UINT_MAX,
++ .flags = CPUIDLE_FLAG_TIME_VALID,
++ .name = "WFI",
++ .desc = "ARM WFI",
++ },
++ [1] = {
++ .enter = bl_enter_cpu_powerdown,
++ .exit_latency = 500,
++ .target_residency = 1000,
++ .flags = CPUIDLE_FLAG_TIME_VALID |
++ CPUIDLE_FLAG_TIMER_STOP,
++ .name = "C1",
++ .desc = "ARM cpu A17 Cluster power down",
++ },
+};
+
+static struct cpuidle_driver bl_idle_driver = {
-+ .name = "bl_idle",
-+ .owner = THIS_MODULE,
-+ .safe_state_index = 0
++ .name = "bl_idle",
++ .owner = THIS_MODULE,
++ .safe_state_index = 0
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, bl_idle_dev);
+
+static void bl_cpu_smp_disable(void)
+{
-+ /* Set ACTLR.SMP to 0, AMP -> SMP */
-+ asm volatile (
-+ " mrc p15, 0, r0, c1, c0, 1\n"
-+ " bic r0, #0x40\n"
-+ " mcr p15, 0, r0, c1, c0, 1\n"
-+ :
-+ :
-+ : "r0", "cc");
++ /* Set ACTLR.SMP to 0, AMP -> SMP */
++ asm volatile (
++ " mrc p15, 0, r0, c1, c0, 1\n"
++ " bic r0, #0x40\n"
++ " mcr p15, 0, r0, c1, c0, 1\n"
++ :
++ :
++ : "r0", "cc");
+}
+
+static void bl_cpu_powerdown(u64 expected_residency)
+{
-+ int cpu = smp_processor_id();
-+ /* disable irq */
-+ if (WARN(!irqs_disabled(), "Interrupts should be disabled\n")) {
-+ local_irq_disable();
-+ }
++ int cpu = smp_processor_id();
++ /* disable irq */
++ if (WARN(!irqs_disabled(), "Interrupts should be disabled\n")) {
++ local_irq_disable();
++ }
+
-+ /* move the power code here to measure the idle enter time */
-+ hi_pmc_automode_power_down();
++ /* move the power code here to measure the idle enter time */
++ hi_pmc_automode_power_down();
+
-+ gic_cpu_if_down();
++ gic_cpu_if_down();
+
-+ /* close Dcache */
-+ set_cr(get_cr() & ~CR_C);
-+ /* CLREX */
-+ asm volatile ("clrex");
++ /* close Dcache */
++ set_cr(get_cr() & ~CR_C);
++ /* CLREX */
++ asm volatile ("clrex");
+
-+ /* Clean & Invalidata L1 Data Cache, L2 Cache */
-+ /* for cortex a17 just one single instruction is enough
-+ flush_cache_all();
-+ */
-+ /* clean&invalidate l1 cache */
-+ asm volatile("mov r0, #0\n");
-+ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
-+ asm volatile("dsb \n");
++ /* Clean & Invalidata L1 Data Cache, L2 Cache */
++ /* for cortex a17 just one single instruction is enough
++ flush_cache_all();
++ */
++ /* clean&invalidate l1 cache */
++ asm volatile("mov r0, #0\n");
++ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
++ asm volatile("dsb \n");
+
-+ /* clean&invalidate l2 cache */
-+ asm volatile("mov r0, #2\n");
-+ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
-+ asm volatile("dsb \n");
++ /* clean&invalidate l2 cache */
++ asm volatile("mov r0, #2\n");
++ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
++ asm volatile("dsb \n");
+
-+ /* switch SMP to AMP(ACTLR.SMP->1'b0) */
-+ bl_cpu_smp_disable();
++ /* switch SMP to AMP(ACTLR.SMP->1'b0) */
++ bl_cpu_smp_disable();
+
-+ /* disable cci snoop */
-+ cci_disable_port_by_cpu(cpu_logical_map(cpu));
++ /* disable cci snoop */
++ cci_disable_port_by_cpu(cpu_logical_map(cpu));
+
-+ /* config DBGOSDLR register(cp14) DLK bit to 1, avoid debug event wake up cpu */
-+ /* asm volatile("mcr p14, 0, %0, c1, c3, 0" : : "r" (1)); */
++ /* config DBGOSDLR register(cp14) DLK bit to 1, avoid debug event wake up cpu */
++ /* asm volatile("mcr p14, 0, %0, c1, c3, 0" : : "r" (1)); */
+
-+ /* ISB & DSB */
-+ isb();
-+ dsb();
++ /* ISB & DSB */
++ isb();
++ dsb();
+
-+ hi_pmc_set_ac_inactive();
-+ /*
-+ hi_pmc_automode_power_down();
-+ */
-+ dsb();
-+ /* WFI */
-+ while (1) {
-+ wfi();
-+ }
++ hi_pmc_set_ac_inactive();
++ /*
++ hi_pmc_automode_power_down();
++ */
++ dsb();
++ /* WFI */
++ while (1) {
++ wfi();
++ }
+
-+ BUG();
++ BUG();
+}
+
+static int bl_cpu_powered_up(void)
+{
-+ /*dcache enble*/
-+ set_cr(get_cr() | CR_C);
++ /*dcache enble*/
++ set_cr(get_cr() | CR_C);
+
-+ hi_pmc_power_up_done();
++ hi_pmc_power_up_done();
+
-+ return 0;
++ return 0;
+}
+
+
+static int notrace bl_cpu_powerdown_finisher(unsigned long arg)
+{
-+ hi3519av100_set_cpu_jump(smp_processor_id(),
-+ (phys_addr_t)virt_to_phys(hi3519av100_cpu_resume));
++ hi3519av100_set_cpu_jump(smp_processor_id(),
++ (phys_addr_t)virt_to_phys(hi3519av100_cpu_resume));
+
-+ bl_cpu_powerdown(0);
++ bl_cpu_powerdown(0);
+
-+ return 1;
++ return 1;
+}
+
+/*
@@ -196586,29 +265800,29 @@ index 0000000..8071690
+ * specified target state selected by the governor.
+ */
+int bl_enter_cpu_powerdown(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int idx)
++ struct cpuidle_driver *drv, int idx)
+{
-+ int cpuid = smp_processor_id();
++ int cpuid = smp_processor_id();
+
-+ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
++ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
+
-+ /* A7 can not power down */
-+ if (cpuid == 0) {
-+ cpu_do_idle();
-+ return idx;
-+ }
++ /* A7 can not power down */
++ if (cpuid == 0) {
++ cpu_do_idle();
++ return idx;
++ }
+
-+ BUG_ON(!irqs_disabled());
++ BUG_ON(!irqs_disabled());
+
-+ cpu_pm_enter();
++ cpu_pm_enter();
+
-+ cpu_suspend((unsigned long) dev, bl_cpu_powerdown_finisher);
++ cpu_suspend((uintptr_t) dev, bl_cpu_powerdown_finisher);
+
-+ bl_cpu_powered_up();
++ bl_cpu_powered_up();
+
-+ cpu_pm_exit();
++ cpu_pm_exit();
+
-+ return idx;
++ return idx;
+}
+/*
+ * bl_idle_init
@@ -196619,44 +265833,44 @@ index 0000000..8071690
+
+static int __init bl_idle_init(void)
+{
-+ struct cpuidle_device *dev;
-+ int i, cpu_id;
-+ struct cpuidle_driver *drv = &bl_idle_driver;
++ struct cpuidle_device *dev = NULL;
++ int i, cpu_id;
++ struct cpuidle_driver *drv = &bl_idle_driver;
+
-+ drv->state_count = (sizeof(bl_cpuidle_set) /
-+ sizeof(struct cpuidle_state));
++ drv->state_count = (sizeof(bl_cpuidle_set) /
++ sizeof(struct cpuidle_state));
+
+
-+ for (i = 0; i < drv->state_count; i++) {
-+ memcpy(&drv->states[i], &bl_cpuidle_set[i],
-+ sizeof(struct cpuidle_state));
-+ }
-+ cpuidle_register_driver(drv);
++ for (i = 0; i < drv->state_count; i++) {
++ memcpy(&drv->states[i], &bl_cpuidle_set[i],
++ sizeof(struct cpuidle_state));
++ }
++ cpuidle_register_driver(drv);
+
-+ for_each_cpu(cpu_id, cpu_online_mask) {
-+ /* cpu 0 use default idle */
-+ if (cpu_id == 0) {
-+ continue;
-+ }
-+ pr_err("CPUidle for CPU%d registered\n", cpu_id);
-+ dev = &per_cpu(bl_idle_dev, cpu_id);
-+ dev->cpu = cpu_id;
++ for_each_cpu(cpu_id, cpu_online_mask) {
++ /* cpu 0 use default idle */
++ if (cpu_id == 0) {
++ continue;
++ }
++ pr_err("CPUidle for CPU%d registered\n", cpu_id);
++ dev = &per_cpu(bl_idle_dev, cpu_id);
++ dev->cpu = cpu_id;
+
-+ if (cpuidle_register_device(dev)) {
-+ printk(KERN_ERR "%s: Cpuidle register device failed\n",
-+ __func__);
-+ return -EIO;
-+ }
-+ }
++ if (cpuidle_register_device(dev)) {
++ printk(KERN_ERR "%s: Cpuidle register device failed\n",
++ __func__);
++ return -EIO;
++ }
++ }
+
+
-+ return 0;
++ return 0;
+}
+
+device_initcall(bl_idle_init);
diff --git a/drivers/cpuidle/cpuidle-hi3556av100.c b/drivers/cpuidle/cpuidle-hi3556av100.c
new file mode 100644
-index 0000000..8b25a74
+index 0000000..ab4b4dd
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-hi3556av100.c
@@ -0,0 +1,270 @@
@@ -196715,141 +265929,141 @@ index 0000000..8b25a74
+extern void hi_pmc_power_up_done(void);
+
+static int bl_cpuidle_simple_enter(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int index);
++ struct cpuidle_driver *drv, int index);
+
+int bl_cpuidle_simple_enter(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int index)
++ struct cpuidle_driver *drv, int index)
+{
+#if defined(CPUIDLE_DEBUG)
-+ int cpuid = smp_processor_id();
-+ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
++ int cpuid = smp_processor_id();
++ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
+#endif
-+ cpu_do_idle();
-+ return index;
++ cpu_do_idle();
++ return index;
+}
+
+static int bl_enter_cpu_powerdown(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int idx);
++ struct cpuidle_driver *drv, int idx);
+
+
+static struct cpuidle_state bl_cpuidle_set[] __initdata = {
-+ [0] = {
-+ .enter = bl_cpuidle_simple_enter,
-+ .exit_latency = 1,
-+ .target_residency = 1,
-+ .power_usage = UINT_MAX,
-+ .flags = CPUIDLE_FLAG_TIME_VALID,
-+ .name = "WFI",
-+ .desc = "ARM WFI",
-+ },
-+ [1] = {
-+ .enter = bl_enter_cpu_powerdown,
-+ .exit_latency = 500,
-+ .target_residency = 1000,
-+ .flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_TIMER_STOP,
-+ .name = "C1",
-+ .desc = "ARM cpu A17 Cluster power down",
-+ },
++ [0] = {
++ .enter = bl_cpuidle_simple_enter,
++ .exit_latency = 1,
++ .target_residency = 1,
++ .power_usage = UINT_MAX,
++ .flags = CPUIDLE_FLAG_TIME_VALID,
++ .name = "WFI",
++ .desc = "ARM WFI",
++ },
++ [1] = {
++ .enter = bl_enter_cpu_powerdown,
++ .exit_latency = 500,
++ .target_residency = 1000,
++ .flags = CPUIDLE_FLAG_TIME_VALID |
++ CPUIDLE_FLAG_TIMER_STOP,
++ .name = "C1",
++ .desc = "ARM cpu A17 Cluster power down",
++ },
+};
+
+static struct cpuidle_driver bl_idle_driver = {
-+ .name = "bl_idle",
-+ .owner = THIS_MODULE,
-+ .safe_state_index = 0
++ .name = "bl_idle",
++ .owner = THIS_MODULE,
++ .safe_state_index = 0
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, bl_idle_dev);
+
+static void bl_cpu_smp_disable(void)
+{
-+ /* Set ACTLR.SMP to 0, AMP -> SMP */
-+ asm volatile (
-+ " mrc p15, 0, r0, c1, c0, 1\n"
-+ " bic r0, #0x40\n"
-+ " mcr p15, 0, r0, c1, c0, 1\n"
-+ :
-+ :
-+ : "r0", "cc");
++ /* Set ACTLR.SMP to 0, AMP -> SMP */
++ asm volatile (
++ " mrc p15, 0, r0, c1, c0, 1\n"
++ " bic r0, #0x40\n"
++ " mcr p15, 0, r0, c1, c0, 1\n"
++ :
++ :
++ : "r0", "cc");
+}
+
+static void bl_cpu_powerdown(u64 expected_residency)
+{
-+ int cpu = smp_processor_id();
-+ /* disable irq */
-+ if (WARN(!irqs_disabled(), "Interrupts should be disabled\n")) {
-+ local_irq_disable();
-+ }
++ int cpu = smp_processor_id();
++ /* disable irq */
++ if (WARN(!irqs_disabled(), "Interrupts should be disabled\n")) {
++ local_irq_disable();
++ }
+
-+ /* move the power code here to measure the idle enter time */
-+ hi_pmc_automode_power_down();
++ /* move the power code here to measure the idle enter time */
++ hi_pmc_automode_power_down();
+
-+ gic_cpu_if_down();
++ gic_cpu_if_down();
+
-+ /* close Dcache */
-+ set_cr(get_cr() & ~CR_C);
-+ /* CLREX */
-+ asm volatile ("clrex");
++ /* close Dcache */
++ set_cr(get_cr() & ~CR_C);
++ /* CLREX */
++ asm volatile ("clrex");
+
-+ /* Clean & Invalidata L1 Data Cache, L2 Cache */
-+ /* for cortex a17 just one single instruction is enough
-+ flush_cache_all();
-+ */
-+ /* clean&invalidate l1 cache */
-+ asm volatile("mov r0, #0\n");
-+ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
-+ asm volatile("dsb \n");
++ /* Clean & Invalidata L1 Data Cache, L2 Cache */
++ /* for cortex a17 just one single instruction is enough
++ flush_cache_all();
++ */
++ /* clean&invalidate l1 cache */
++ asm volatile("mov r0, #0\n");
++ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
++ asm volatile("dsb \n");
+
-+ /* clean&invalidate l2 cache */
-+ asm volatile("mov r0, #2\n");
-+ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
-+ asm volatile("dsb \n");
++ /* clean&invalidate l2 cache */
++ asm volatile("mov r0, #2\n");
++ asm volatile("mcr p15, 1, r0, c15, c14, 0 \n");
++ asm volatile("dsb \n");
+
-+ /* switch SMP to AMP(ACTLR.SMP->1'b0) */
-+ bl_cpu_smp_disable();
++ /* switch SMP to AMP(ACTLR.SMP->1'b0) */
++ bl_cpu_smp_disable();
+
-+ /* disable cci snoop */
-+ cci_disable_port_by_cpu(cpu_logical_map(cpu));
++ /* disable cci snoop */
++ cci_disable_port_by_cpu(cpu_logical_map(cpu));
+
-+ /* config DBGOSDLR register(cp14) DLK bit to 1, avoid debug event wake up cpu */
-+ /* asm volatile("mcr p14, 0, %0, c1, c3, 0" : : "r" (1)); */
++ /* config DBGOSDLR register(cp14) DLK bit to 1, avoid debug event wake up cpu */
++ /* asm volatile("mcr p14, 0, %0, c1, c3, 0" : : "r" (1)); */
+
-+ /* ISB & DSB */
-+ isb();
-+ dsb();
++ /* ISB & DSB */
++ isb();
++ dsb();
+
-+ hi_pmc_set_ac_inactive();
-+ /*
-+ hi_pmc_automode_power_down();
-+ */
-+ dsb();
-+ /* WFI */
-+ while (1) {
-+ wfi();
-+ }
++ hi_pmc_set_ac_inactive();
++ /*
++ hi_pmc_automode_power_down();
++ */
++ dsb();
++ /* WFI */
++ while (1) {
++ wfi();
++ }
+
-+ BUG();
++ BUG();
+}
+
+static int bl_cpu_powered_up(void)
+{
-+ /*dcache enble*/
-+ set_cr(get_cr() | CR_C);
++ /*dcache enble*/
++ set_cr(get_cr() | CR_C);
+
-+ hi_pmc_power_up_done();
++ hi_pmc_power_up_done();
+
-+ return 0;
++ return 0;
+}
+
+
+static int notrace bl_cpu_powerdown_finisher(unsigned long arg)
+{
-+ hi3556av100_set_cpu_jump(smp_processor_id(),
-+ (phys_addr_t)virt_to_phys(hi3556av100_cpu_resume));
++ hi3556av100_set_cpu_jump(smp_processor_id(),
++ (phys_addr_t)virt_to_phys(hi3556av100_cpu_resume));
+
-+ bl_cpu_powerdown(0);
++ bl_cpu_powerdown(0);
+
-+ return 1;
++ return 1;
+}
+
+/*
@@ -196862,29 +266076,29 @@ index 0000000..8b25a74
+ * specified target state selected by the governor.
+ */
+int bl_enter_cpu_powerdown(struct cpuidle_device *dev,
-+ struct cpuidle_driver *drv, int idx)
++ struct cpuidle_driver *drv, int idx)
+{
-+ int cpuid = smp_processor_id();
++ int cpuid = smp_processor_id();
+
-+ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
++ printk(KERN_DEBUG"%s cpu:%d enter\n", __func__, cpuid);
+
-+ /* A7 can not power down */
-+ if (cpuid == 0) {
-+ cpu_do_idle();
-+ return idx;
-+ }
++ /* A7 can not power down */
++ if (cpuid == 0) {
++ cpu_do_idle();
++ return idx;
++ }
+
-+ BUG_ON(!irqs_disabled());
++ BUG_ON(!irqs_disabled());
+
-+ cpu_pm_enter();
++ cpu_pm_enter();
+
-+ cpu_suspend((unsigned long) dev, bl_cpu_powerdown_finisher);
++ cpu_suspend((uintptr_t) dev, bl_cpu_powerdown_finisher);
+
-+ bl_cpu_powered_up();
++ bl_cpu_powered_up();
+
-+ cpu_pm_exit();
++ cpu_pm_exit();
+
-+ return idx;
++ return idx;
+}
+/*
+ * bl_idle_init
@@ -196895,63 +266109,61 @@ index 0000000..8b25a74
+
+static int __init bl_idle_init(void)
+{
-+ struct cpuidle_device *dev;
-+ int i, cpu_id;
-+ struct cpuidle_driver *drv = &bl_idle_driver;
++ struct cpuidle_device *dev = NULL;
++ int i, cpu_id;
++ struct cpuidle_driver *drv = &bl_idle_driver;
+
-+ drv->state_count = (sizeof(bl_cpuidle_set) /
-+ sizeof(struct cpuidle_state));
++ drv->state_count = (sizeof(bl_cpuidle_set) /
++ sizeof(struct cpuidle_state));
+
+
-+ for (i = 0; i < drv->state_count; i++) {
-+ memcpy(&drv->states[i], &bl_cpuidle_set[i],
-+ sizeof(struct cpuidle_state));
-+ }
-+ cpuidle_register_driver(drv);
++ for (i = 0; i < drv->state_count; i++) {
++ memcpy(&drv->states[i], &bl_cpuidle_set[i],
++ sizeof(struct cpuidle_state));
++ }
++ cpuidle_register_driver(drv);
+
-+ for_each_cpu(cpu_id, cpu_online_mask) {
-+ /* cpu 0 use default idle */
-+ if (cpu_id == 0) {
-+ continue;
-+ }
-+ pr_err("CPUidle for CPU%d registered\n", cpu_id);
-+ dev = &per_cpu(bl_idle_dev, cpu_id);
-+ dev->cpu = cpu_id;
++ for_each_cpu(cpu_id, cpu_online_mask) {
++ /* cpu 0 use default idle */
++ if (cpu_id == 0) {
++ continue;
++ }
++ pr_err("CPUidle for CPU%d registered\n", cpu_id);
++ dev = &per_cpu(bl_idle_dev, cpu_id);
++ dev->cpu = cpu_id;
+
-+ if (cpuidle_register_device(dev)) {
-+ printk(KERN_ERR "%s: Cpuidle register device failed\n",
-+ __func__);
-+ return -EIO;
-+ }
-+ }
++ if (cpuidle_register_device(dev)) {
++ printk(KERN_ERR "%s: Cpuidle register device failed\n",
++ __func__);
++ return -EIO;
++ }
++ }
+
+
-+ return 0;
++ return 0;
+}
+
+device_initcall(bl_idle_init);
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
-index 4d2b81f..7e3d747 100644
+index 4d2b81f..693f7e3 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
-@@ -555,4 +555,7 @@ config CRYPTO_DEV_ROCKCHIP
+@@ -555,4 +555,6 @@ config CRYPTO_DEV_ROCKCHIP
source "drivers/crypto/chelsio/Kconfig"
-+source "drivers/crypto/hisi-otp/Kconfig"
+source "drivers/crypto/hisi-cipher/Kconfig"
+
endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
-index ad7250f..a3bc9cd 100644
+index ad7250f..9ecda9e 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
-@@ -32,3 +32,5 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
+@@ -32,3 +32,4 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
+obj-$(CONFIG_CRYPTO_DEV_HISI_CIPHER) += hisi-cipher/
-+obj-$(CONFIG_CRYPTO_DEV_HISI_OTP) += hisi-otp/
diff --git a/drivers/crypto/hisi-cipher/Kconfig b/drivers/crypto/hisi-cipher/Kconfig
new file mode 100644
index 0000000..1afd36a
@@ -196983,36 +266195,25 @@ index 0000000..dffde46
+obj-y += src/
diff --git a/drivers/crypto/hisi-cipher/include/drv_cipher_kapi.h b/drivers/crypto/hisi-cipher/include/drv_cipher_kapi.h
new file mode 100644
-index 0000000..5893c9d
+index 0000000..50fb6ce
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/include/drv_cipher_kapi.h
-@@ -0,0 +1,721 @@
+@@ -0,0 +1,610 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (C), Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv cipher kapi.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __TEE_DRV_CIPHER_KAPI_H__
+#define __TEE_DRV_CIPHER_KAPI_H__
+
++#include "drv_cipher_define.h"
+#ifdef HI_PLATFORM_TYPE_TEE
+#include "hi_tee_cipher.h"
+#include "tee_drv_cipher_compat.h"
+#else
-+#include "hi_unf_cipher.h"
+#include "hi_common_cipher.h"
+#include "hi_cipher_compat.h"
+#endif
@@ -197021,46 +266222,34 @@ index 0000000..5893c9d
+extern "C" {
+#endif /* __cplusplus */
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup crypto */
-+
-+/*! \success */
++/* success. */
+#undef HI_SUCCESS
-+#define HI_SUCCESS (0)
++#define HI_SUCCESS 0
+
-+/*! \failure */
++/* failure. */
+#undef HI_FAILURE
+#define HI_FAILURE (-1)
+
-+#ifndef MAX
-+#define MAX(a, b) ((a) > (b) ? (a) : (b))
-+#endif
-+#ifndef MIN
-+#define MIN(a, b) ((a) < (b) ? (a) : (b))
-+#endif
++#define crypto_max(a, b) ((a) > (b) ? (a) : (b))
+
-+/*width of word*/
-+#define WORD_WIDTH (4)
-+#define WORD_BIT_WIDTH (32)
-+#define U32_MAX_SIZE (0xFFFFFFFF)
-+
-+/*width of double word*/
-+#define DOUBLE_WORD_WIDTH (8)
++#define crypto_min(a, b) ((a) < (b) ? (a) : (b))
+
+#ifndef SM2_LEN_IN_WROD
-+#define SM2_LEN_IN_WROD (8)
-+#define SM2_LEN_IN_BYTE (32)
++#define SM2_LEN_IN_WROD 8
++#define SM2_LEN_IN_BYTE 32
+#endif
+
-+/*! \big coding transform to litte coding*/
-+#define CPU_TO_BE16(v) (((v)<< 8) | ((v)>>8))
++/* big coding transform to litte coding. */
++#define crypto_cpu_to_be16(v) (((v) << 8) | ((v) >> 8))
+
-+#define CPU_TO_BE32(v) ((((hi_u32)(v))>>24) | \
-+ ((((hi_u32)(v))>>8)&0xff00) | \
-+ ((((hi_u32)(v))<<8)&0xff0000) | \
-+ (((hi_u32)(v))<<24))
++#define crypto_cpu_to_be32(v) \
++ ((((hi_u32)(v)) >> 24) | \
++ ((((hi_u32)(v)) >> 8) & 0xff00) | \
++ ((((hi_u32)(v)) << 8) & 0xff0000) | \
++ (((hi_u32)(v)) << 24))
+
-+#define CPU_TO_BE64(x) ((hi_u64)( \
++#define crypto_cpu_to_be64(x) \
++ ((hi_u64)( \
+ (((hi_u64)(x) & (hi_u64)0x00000000000000ffULL) << 56) | \
+ (((hi_u64)(x) & (hi_u64)0x000000000000ff00ULL) << 40) | \
+ (((hi_u64)(x) & (hi_u64)0x0000000000ff0000ULL) << 24) | \
@@ -197070,221 +266259,200 @@ index 0000000..5893c9d
+ (((hi_u64)(x) & (hi_u64)0x00ff000000000000ULL) >> 40) | \
+ (((hi_u64)(x) & (hi_u64)0xff00000000000000ULL) >> 56)))
+
-+/*! \defined the base error code */
-+#define HI_BASE_ERR_BASE (0x400)
++/* defined the base error code. */
++#define HI_BASE_ERR_BASE 0x400
+#define HI_BASE_ERR_BASE_SYMC (HI_BASE_ERR_BASE + 0x100)
+#define HI_BASE_ERR_BASE_HASH (HI_BASE_ERR_BASE + 0x200)
+#define HI_BASE_ERR_BASE_RSA (HI_BASE_ERR_BASE + 0x300)
+#define HI_BASE_ERR_BASE_TRNG (HI_BASE_ERR_BASE + 0x400)
+#define HI_BASE_ERR_BASE_SM2 (HI_BASE_ERR_BASE + 0x500)
+
-+#define CRYPTO_MAGIC_NUM (0xc0704d19)
++#define CRYPTO_MAGIC_NUM 0xc0704d19
+
-+/*! \enumeration module_id*/
++/* enumeration module_id. */
+typedef enum {
-+ CRYPTO_MODULE_ID_SYMC, /*!< Symmetric Cipher */
-+ CRYPTO_MODULE_ID_SYMC_KEY, /*!< Symmetric Cipher key */
-+ CRYPTO_MODULE_ID_HASH, /*!< Message Digest */
-+ CRYPTO_MODULE_ID_IFEP_RSA, /*!< Asymmetric developed by IFEP */
-+ CRYPTO_MODULE_ID_SIC_RSA, /*!< Asymmetric developed by SIC */
-+ CRYPTO_MODULE_ID_TRNG, /*!< Random Data Generation */
-+ CRYPTO_MODULE_ID_SM2, /*!< Public Key Cryptographic Algorithm Based on Elliptic Curves */
-+ CRYPTO_MODULE_ID_SM4, /*!< SM4 */
-+ CRYPTO_MODULE_ID_SMMU, /*!< SMMU */
-+ CRYPTO_MODULE_ID_CNT, /*!< Count of module id */
++ CRYPTO_MODULE_ID_SYMC, /* Symmetric Cipher */
++ CRYPTO_MODULE_ID_SYMC_KEY, /* Symmetric Cipher key */
++ CRYPTO_MODULE_ID_HASH, /* Message Digest */
++ CRYPTO_MODULE_ID_IFEP_RSA, /* Asymmetric developed by IFEP */
++ CRYPTO_MODULE_ID_SIC_RSA, /* Asymmetric developed by SIC */
++ CRYPTO_MODULE_ID_TRNG, /* Random Data Generation */
++ CRYPTO_MODULE_ID_SM2, /* Public Key Cryptographic Algorithm Based on Elliptic Curves */
++ CRYPTO_MODULE_ID_SM4, /* SM4 */
++ CRYPTO_MODULE_ID_SMMU, /* SMMU */
++ CRYPTO_MODULE_ID_CNT, /* Count of module id */
+} module_id;
+
-+#define CRYPTO_UNUSED(x) ((x)=(x))
++#define crypto_unused(x) ((x) = (x))
+
-+#define HASH_BLOCK_SIZE (64)
++#define HASH_BLOCK_SIZE 64
+
-+#define CRYPTO_IOC_NA (0U)
-+#define CRYPTO_IOC_W (1U)
-+#define CRYPTO_IOC_R (2U)
-+#define CRYPTO_IOC_RW (3U)
++#define CRYPTO_IOC_NA 0U
++#define CRYPTO_IOC_W 1U
++#define CRYPTO_IOC_R 2U
++#define CRYPTO_IOC_RW 3U
+
-+#define HI_ID_CIPHER (0x4D)
++#define HI_ID_CIPHER 0x4D
+
+#define CIPHER_NAME "HI_CIPHER"
+#define UMAP_DEVNAME_CIPHER "cipher"
-+#define UMAP_MIN_MINOR_CIPHER (50)
++#define UMAP_MIN_MINOR_CIPHER 50
+
-+#define CRYPTO_IOC(dir,type,nr,size) \
++#define crypto_ioc(dir, type, nr, size) \
+ (((dir) << 30) | ((size) << 16) | ((type) << 8) | ((nr) << 0))
+
-+#define CRYPTO_IOR(nr,size) CRYPTO_IOC(CRYPTO_IOC_R, HI_ID_CIPHER,(nr), size)
-+#define CRYPTO_IOW(nr,size) CRYPTO_IOC(CRYPTO_IOC_W, HI_ID_CIPHER,(nr), size)
-+#define CRYPTO_IOWR(nr,size) CRYPTO_IOC(CRYPTO_IOC_RW, HI_ID_CIPHER,(nr),size)
++#define crypto_ior(nr, size) crypto_ioc(CRYPTO_IOC_R, HI_ID_CIPHER, (nr), size)
++#define crypto_iow(nr, size) crypto_ioc(CRYPTO_IOC_W, HI_ID_CIPHER, (nr), size)
++#define crypto_iowr(nr, size) crypto_ioc(CRYPTO_IOC_RW, HI_ID_CIPHER, (nr), size)
+
-+#define CRYPTO_IOC_DIR(cmd) (((cmd) >> 30) & 0x03)
-+#define CRYPTO_IOC_TYPE(cmd) (((cmd) >> 8) & 0xFF)
-+#define CRYPTO_IOC_NR(cmd) (((cmd) >> 0) & 0xFF)
-+#define CRYPTO_IOC_SIZE(cmd) (((cmd) >> 16) & 0x3FFF)
++#define crypto_ioc_dir(cmd) (((cmd) >> 30) & 0x03)
++#define crypto_ioc_type(cmd) (((cmd) >> 8) & 0xFF)
++#define crypto_ioc_nr(cmd) (((cmd) >> 0) & 0xFF)
++#define crypto_ioc_size(cmd) (((cmd) >> 16) & 0x3FFF)
+
-+#define CRYPTO_CMD_SYMC_CREATEHANDLE CRYPTO_IOR(0x00, sizeof(symc_create_t))
-+#define CRYPTO_CMD_SYMC_DESTROYHANDLE CRYPTO_IOW (0x01, sizeof(symc_destroy_t))
-+#define CRYPTO_CMD_SYMC_CONFIGHANDLE CRYPTO_IOW (0x02, sizeof(symc_config_t))
-+#define CRYPTO_CMD_SYMC_ENCRYPT CRYPTO_IOW (0x03, sizeof(symc_encrypt_t))
-+#define CRYPTO_CMD_SYMC_ENCRYPTMULTI CRYPTO_IOW (0x04, sizeof(symc_encrypt_multi_t))
-+#define CRYPTO_CMD_SYMC_GETTAG CRYPTO_IOWR(0x05, sizeof(aead_tag_t))
-+#define CRYPTO_CMD_HASH_START CRYPTO_IOWR(0x06, sizeof(hash_start_t))
-+#define CRYPTO_CMD_HASH_UPDATE CRYPTO_IOW (0x07, sizeof(hash_update_t))
-+#define CRYPTO_CMD_HASH_FINISH CRYPTO_IOWR(0x08, sizeof(hash_finish_t))
-+#define CRYPTO_CMD_RSA_ENC CRYPTO_IOWR(0x09, sizeof(rsa_info_t))
-+#define CRYPTO_CMD_RSA_DEC CRYPTO_IOWR(0x0a, sizeof(rsa_info_t))
-+#define CRYPTO_CMD_RSA_SIGN CRYPTO_IOWR(0x0b, sizeof(rsa_info_t))
-+#define CRYPTO_CMD_RSA_VERIFY CRYPTO_IOWR(0x0c, sizeof(rsa_info_t))
-+#define CRYPTO_CMD_TRNG CRYPTO_IOWR(0x0d, sizeof(trng_t))
-+#define CRYPTO_CMD_SYMC_GET_CONFIG CRYPTO_IOWR(0x0e, sizeof(symc_get_config_t))
-+#define CRYPTO_CMD_KLAD_KEY CRYPTO_IOWR(0x0f, sizeof(klad_key_t))
++#define CRYPTO_CMD_SYMC_CREATEHANDLE crypto_ior(0x00, sizeof(symc_create_t))
++#define CRYPTO_CMD_SYMC_DESTROYHANDLE crypto_iow (0x01, sizeof(symc_destroy_t))
++#define CRYPTO_CMD_SYMC_CONFIGHANDLE crypto_iow (0x02, sizeof(symc_cfg_t))
++#define CRYPTO_CMD_SYMC_ENCRYPT crypto_iow (0x03, sizeof(symc_encrypt_t))
++#define CRYPTO_CMD_SYMC_ENCRYPTMULTI crypto_iow (0x04, sizeof(symc_encrypt_multi_t))
++#define CRYPTO_CMD_SYMC_GETTAG crypto_iowr(0x05, sizeof(aead_tag_t))
++#define CRYPTO_CMD_HASH_START crypto_iowr(0x06, sizeof(hash_start_t))
++#define CRYPTO_CMD_HASH_UPDATE crypto_iow (0x07, sizeof(hash_update_t))
++#define CRYPTO_CMD_HASH_FINISH crypto_iowr(0x08, sizeof(hash_finish_t))
++#define CRYPTO_CMD_RSA_ENC crypto_iowr(0x09, sizeof(rsa_info_t))
++#define CRYPTO_CMD_RSA_DEC crypto_iowr(0x0a, sizeof(rsa_info_t))
++#define CRYPTO_CMD_RSA_SIGN crypto_iowr(0x0b, sizeof(rsa_info_t))
++#define CRYPTO_CMD_RSA_VERIFY crypto_iowr(0x0c, sizeof(rsa_info_t))
++#define CRYPTO_CMD_TRNG crypto_iowr(0x0d, sizeof(trng_t))
++#define CRYPTO_CMD_SYMC_GET_CONFIG crypto_iowr(0x0e, sizeof(symc_get_cfg_t))
++#define CRYPTO_CMD_KLAD_KEY crypto_iowr(0x0f, sizeof(klad_key_t))
+#define CRYPTO_CMD_COUNT 0x10
+
-+#define CHECK_EXIT(_expr) \
++#define crypto_chk_err_exit(_expr) \
+ do { \
+ if ((ret = (_expr)) != HI_SUCCESS) { \
-+ HI_LOG_PRINT_FUNC_ERR((_expr), ret); \
++ hi_log_print_func_err((_expr), ret); \
+ goto exit__; \
+ } \
+ } while (0)
+
-+#ifdef CIPHER_DEBUG_TEST_SUPPORT
-+#define HI_PRINT_HEX(name, str, len) \
-+ {\
-+ hi_u32 _i = 0;\
-+ hi_u8 *_str; \
-+ _str = (hi_u8*)(str); \
-+ HI_PRINT("[%s]:\n", (name));\
-+ for ( _i = 0 ; _i < (len); _i++ )\
-+ {\
-+ if( (_i % 16 == 0) && (_i != 0)) HI_PRINT("\n");\
-+ HI_PRINT("\\x%02x", *((_str)+_i));\
-+ }\
-+ HI_PRINT("\n");\
-+ }
-+#else
-+#define HI_PRINT_HEX print_string
-+#endif
++/* AES KEY size */
++#define SYMC_KEY_SIZE 32
+
-+/*! \AES KEY size */
-+#define SYMC_KEY_SIZE (32)
++/* SM1 SK size */
++#define SYMC_SM1_SK_SIZE 16
+
-+/*! \SM1 SK size */
-+#define SYMC_SM1_SK_SIZE (16)
++/* AES IV size */
++#define AES_IV_SIZE 16
+
-+/*! \AES IV size */
-+#define AES_IV_SIZE (16)
++/* AES BLOCK size */
++#define AES_BLOCK_SIZE 16
+
-+/*! \AES BLOCK size */
-+#define AES_BLOCK_SIZE (16)
++/* DES IV size */
++#define DES_IV_SIZE 8
+
-+/*! \DES IV size */
-+#define DES_IV_SIZE (8)
++/* aead tag length */
++#define AEAD_TAG_SIZE 16
++#define AEAD_TAG_SIZE_IN_WORD 4
+
-+/*! \aead tag length */
-+#define AEAD_TAG_SIZE (16)
-+#define AEAD_TAG_SIZE_IN_WORD (4)
++/* bits in a byte */
++#define BITS_IN_BYTE 8
+
-+/*! \bits in a byte */
-+#define BITS_IN_BYTE (8)
-+
-+/*! \hash result max size */
-+#define HASH_RESULT_MAX_SIZE (64)
++/* hash result max size */
++#define HASH_RESULT_MAX_SIZE 64
+
+#ifndef CHIP_TYPE_hi3516ev200
-+/*! \hash result max size in word */
-+#define HASH_RESULT_MAX_SIZE_IN_WORD (16)
++/* hash result max size in word */
++#define HASH_RESULT_MAX_SIZE_IN_WORD 16
+#else
-+/*! \hash result max size in word */
-+#define HASH_RESULT_MAX_SIZE_IN_WORD (8)
++/* hash result max size in word */
++#define HASH_RESULT_MAX_SIZE_IN_WORD 8
+#endif
+
+/*! capacity upport */
-+#define CRYPTO_CAPACITY_SUPPORT (1)
-+#define CRYPTO_CAPACITY_NONSUPPORT (0)
++#define CRYPTO_CAPACITY_SUPPORT 1
++#define CRYPTO_CAPACITY_NONSUPPORT 0
+
+/* max length of SM2 ID */
-+#define SM2_ID_MAX_LEN (0x1FFF)
++#define SM2_ID_MAX_LEN 0x1FFF
+
-+/*! Define the time out */
-+#define CRYPTO_TIME_OUT (6000)
-+#define MS_TO_US (1000)
++/* Define the time out */
++#define CRYPTO_TIME_OUT 6000
++#define MS_TO_US 1000
+
+/* result size */
-+#define SHA1_RESULT_SIZE (20) /* SHA1 */
-+#define SHA224_RESULT_SIZE (28) /* SHA224 */
-+#define SHA256_RESULT_SIZE (32) /* SHA256 */
-+#define SHA384_RESULT_SIZE (48) /* SHA384 */
-+#define SHA512_RESULT_SIZE (64) /* SHA512 */
-+#define SM3_RESULT_SIZE (32) /* SM3 */
-+
++#define SHA1_RESULT_SIZE 20
++#define SHA224_RESULT_SIZE 28
++#define SHA256_RESULT_SIZE 32
++#define SHA384_RESULT_SIZE 48
++#define SHA512_RESULT_SIZE 64
++#define SM3_RESULT_SIZE 32
+/* rsa key length */
-+#define RSA_MIN_KEY_LEN (128)
-+#define RSA_MAX_KEY_LEN (512)
-+#define RSA_KEY_BITWIDTH_1024 (128)
-+#define RSA_KEY_BITWIDTH_2048 (256)
-+#define RSA_KEY_BITWIDTH_3072 (384)
-+#define RSA_KEY_BITWIDTH_4096 (512)
-+#define RSA_KEY_EXPONENT_VALUE1 (0X3)
-+#define RSA_KEY_EXPONENT_VALUE2 (0X10001)
++#define RSA_MIN_KEY_LEN 128
++#define RSA_MAX_KEY_LEN 512
++#define RSA_KEY_BITWIDTH_1024 128
++#define RSA_KEY_BITWIDTH_2048 256
++#define RSA_KEY_BITWIDTH_3072 384
++#define RSA_KEY_BITWIDTH_4096 512
++#define RSA_KEY_EXPONENT_VALUE1 0X3
++#define RSA_KEY_EXPONENT_VALUE2 0X10001
+
-+/*! \the source of hash message */
++/* the source of hash message */
+typedef enum {
-+ HASH_CHUNCK_SRC_LOCAL, /*!< Local buffer, e.g. Kernel */
-+ HASH_CHUNCK_SRC_USER, /*!< User buffer, use copy_from_user to read data */
++ HASH_CHUNCK_SRC_LOCAL, /* Local buffer, e.g. Kernel */
++ HASH_CHUNCK_SRC_USER, /* User buffer, use copy_from_user to read data */
+} hash_chunk_src;
+
-+/*! \union of compat addr*/
++/* union of compat addr */
+typedef union {
-+ hi_void *p; /*!< virtual address */
-+ const hi_void *cp; /*!< const virtual address */
-+ unsigned long long phy; /*!< physical address */
-+ unsigned int word[2]; /*!< double word of address */
++ hi_void *p; /* virtual address */
++ const hi_void *cp; /* const virtual address */
++ unsigned long long phy; /* physical address */
++ unsigned int word[MUL_VAL_2]; /* double word of address */
+} compat_addr;
+
-+extern compat_addr compat_addr_zero;
-+#define ADDR_H32(addr) addr.word[1] /*!< High 32 bit of hi_u64 */
-+#define ADDR_L32(addr) addr.word[0] /*!< Low 32 bit of hi_u64 */
-+#define ADDR_U64(addr) addr.phy /*!< 64 bit of hi_u64 */
-+#define ADDR_VIA(addr) addr.p /*!< buffer point */
-+#define ADDR_VIA_CONST(addr) addr.cp /*!< const buffer point */
-+#define ADDR_NULL compat_addr_zero /*!< buffer point */
++#define addr_h32(addr) addr.word[WORD_IDX_1] /* High 32 bit of hi_u64 */
++#define addr_l32(addr) addr.word[WORD_IDX_0] /* Low 32 bit of hi_u64 */
++#define addr_u64(addr) addr.phy /* 64 bit of hi_u64 */
++#define addr_via(addr) addr.p /* buffer point */
++#define addr_via_const(addr) addr.cp /* const buffer point */
+
-+#define ADDR_P_H32(addr) addr->word[1] /*!< High 32 bit of hi_u64 */
-+#define ADDR_P_L32(addr) addr->word[0] /*!< Low 32 bit of hi_u64 */
-+#define ADDR_P_U64(addr) addr->phy /*!< 64 bit of hi_u64 */
-+#define ADDR_P_VIA(addr) addr->p /*!< buffer point */
++#define addr_p_h32(addr) addr->word[WORD_IDX_1] /* High 32 bit of hi_u64 */
++#define addr_p_l32(addr) addr->word[WORD_IDX_0] /* Low 32 bit of hi_u64 */
++#define addr_p_u64(addr) addr->phy /* 64 bit of hi_u64 */
++#define addr_p_via(addr) addr->p /* buffer point */
+
-+/*! \struct of Symmetric cipher create */
++/* struct of Symmetric cipher create */
+typedef struct {
-+ hi_u32 id; /*!< to store the id of soft channel */
-+ hi_u32 reserve; /*!< reserve to make align at 64bit */
++ hi_u32 id; /* to store the id of soft channel */
++ hi_u32 reserve; /* reserve to make align at 64bit */
+} symc_create_t;
+
-+/*! \struct of Symmetric cipher destroy */
++/* struct of Symmetric cipher destroy */
+typedef struct {
-+ hi_u32 id; /*!< id of soft channel */
-+ hi_u32 reserve; /*!< reserve to make align at 64bit */
++ hi_u32 id; /* id of soft channel */
++ hi_u32 reserve; /* reserve to make align at 64bit */
+} symc_destroy_t;
+
-+/*! \struct of Symmetric cipher configure infomation */
++/* struct of Symmetric cipher configure infomation */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ hi_u32 hard_key; /*!< Use hard key or not */
-+ hi_cipher_alg alg; /*!< Symmetric cipher algorithm */
-+ hi_cipher_work_mode mode; /*!< Symmetric cipher algorithm */
-+ hi_cipher_bit_width width; /*!< Symmetric cipher bit width */
-+ hi_cipher_key_length klen; /*!< Symmetric cipher key length */
-+ hi_cipher_sm1_round sm1_round_num; /*!< The round number of sm1 */
-+ hi_u8 fkey[SYMC_KEY_SIZE]; /*!< first key buffer, defualt */
-+ hi_u8 skey[SYMC_KEY_SIZE]; /*!< second key buffer */
-+ hi_u8 iv[AES_IV_SIZE]; /*!< IV buffer */
-+ hi_u32 ivlen; /*!< IV length */
-+ hi_u32 iv_usage; /*!< Usage of IV */
-+ hi_u32 reserve; /*!< reserve to make align at 64bit */
-+ compat_addr aad; /*!< Associated Data */
-+ hi_u32 alen; /*!< Associated Data Length */
-+ hi_u32 tlen; /*!< Tag length */
-+} symc_config_t;
++ hi_u32 id; /* Id of soft channel */
++ hi_u32 hard_key; /* Use hard key or not */
++ hi_cipher_alg alg; /* Symmetric cipher algorithm */
++ hi_cipher_work_mode mode; /* Symmetric cipher algorithm */
++ hi_cipher_bit_width width; /* Symmetric cipher bit width */
++ hi_cipher_key_len klen; /* Symmetric cipher key length */
++ hi_cipher_sm1_round sm1_round_num; /* The round number of sm1 */
++ hi_u8 fkey[SYMC_KEY_SIZE]; /* first key buffer, defualt */
++ hi_u8 skey[SYMC_KEY_SIZE]; /* second key buffer */
++ hi_u8 iv[AES_IV_SIZE]; /* IV buffer */
++ hi_u32 ivlen; /* IV length */
++ hi_u32 iv_usage; /* Usage of IV */
++ hi_u32 reserve; /* reserve to make align at 64bit */
++ compat_addr aad; /* Associated Data */
++ hi_u32 alen; /* Associated Data Length */
++ hi_u32 tlen; /* Tag length */
++} symc_cfg_t;
+
+typedef enum {
+ SYMC_OPERATION_ENCRYPT = 0,
@@ -197293,443 +266461,365 @@ index 0000000..5893c9d
+ SYMC_OPERATION_DECRYPT_VIA = 0x11,
+} symc_operation_type;
+
-+/*! \struct of Symmetric cipher encrypt/decrypt */
++/* struct of Symmetric cipher encrypt/decrypt */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ hi_u32 length; /*!< Length of the encrypted data */
-+ hi_u32 operation; /*!< operation type*/
-+ hi_u32 last; /*!< last or not */
-+ compat_addr input; /*!< Physical address of the input data */
-+ compat_addr output; /*!< Physical address of the output data */
++ hi_u32 id; /* Id of soft channel */
++ hi_u32 len; /* Length of the encrypted data */
++ hi_u32 operation; /* operation type */
++ hi_u32 last; /* last or not */
++ compat_addr in; /* Physical address of the input data */
++ compat_addr out; /* Physical address of the output data */
+} symc_encrypt_t;
+
-+/*! \struct of Symmetric cipher multiple encrypt/decrypt */
++/* struct of Symmetric cipher multiple encrypt/decrypt */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ compat_addr pkg; /*!< Buffer of package infomation */
-+ hi_u32 pkg_num; /*!< Number of package infomation */
-+ hi_u32 operation; /*!< Decrypt or encrypt */
++ hi_u32 id; /* Id of soft channel */
++ compat_addr pack; /* Buffer of package infomation */
++ hi_u32 pack_num; /* Number of package infomation */
++ hi_u32 operation; /* Decrypt or encrypt */
+} symc_encrypt_multi_t;
+
-+/*! \struct of Symmetric cipher get tag */
++/* struct of Symmetric cipher get tag */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ hi_u32 tag[AEAD_TAG_SIZE_IN_WORD]; /*!< Buffer of tag */
-+ hi_u32 taglen ; /*!< Length of tag */
++ hi_u32 id; /* Id of soft channel */
++ hi_u32 tag[AEAD_TAG_SIZE_IN_WORD]; /* Buffer of tag */
++ hi_u32 taglen ; /* Length of tag */
+} aead_tag_t;
+
-+/*! \struct of Symmetric cipher get ctrl */
++/* struct of Symmetric cipher get ctrl */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ hi_cipher_ctrl ctrl; /*!< control infomation */
-+} symc_get_config_t;
++ hi_u32 id; /* Id of soft channel */
++ hi_cipher_ctrl ctrl; /* control infomation */
++} symc_get_cfg_t;
+
-+/*! \struct of Hash start */
++/* struct of Hash start */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ hi_cipher_hash_type type; /*!< HASH type */
-+ compat_addr key; /*!< HMAC key */
-+ hi_u32 keylen; /*!< HMAC key */
-+ hi_u32 reserve; /*!< reserve for align at 64bit */
++ hi_u32 id; /* Id of soft channel */
++ hi_cipher_hash_type type; /* HASH type */
++ compat_addr key; /* HMAC key */
++ hi_u32 keylen; /* HMAC key */
++ hi_u32 reserve; /* reserve for align at 64bit */
+} hash_start_t;
+
-+/*! \struct of Hash update */
++/* struct of Hash update */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ hi_u32 length; /*!< Length of the message */
-+ compat_addr input; /*!< Message data buffer */
-+ hash_chunk_src src; /*!< source of hash message */
-+ hi_u32 reserve; /*!< reserve for align at 64bit */
++ hi_u32 id; /* Id of soft channel */
++ hi_u32 length; /* Length of the message */
++ compat_addr input; /* Message data buffer */
++ hash_chunk_src src; /* source of hash message */
++ hi_u32 reserve; /* reserve for align at 64bit */
+} hash_update_t;
+
-+/*! \struct of Hash update */
++/* struct of Hash update */
+typedef struct {
-+ hi_u32 id; /*!< Id of soft channel */
-+ hi_u32 hash[HASH_RESULT_MAX_SIZE_IN_WORD]; /*!< buffer holding the hash data */
-+ hi_u32 hashlen; /*!< length of the hash data */
-+ hi_u32 reserve; /*!< reserve for align at 64bit */
++ hi_u32 id; /* Id of soft channel */
++ hi_u32 hash[HASH_RESULT_MAX_SIZE_IN_WORD]; /* buffer holding the hash data */
++ hi_u32 hashlen; /* length of the hash data */
++ hi_u32 reserve; /* reserve for align at 64bit */
+} hash_finish_t;
+
-+/*! \struct of rsa encrypt/decrypt */
++/* struct of rsa encrypt/decrypt */
+typedef struct {
-+ hi_cipher_rsa_enc_scheme scheme; /*!< RSA encryption scheme */
-+ hi_u16 public; /** Type of key, true-public or false-private */
-+ hi_u16 ca_type; /** ca Type of key */
-+ hi_u32 klen; /*!< length of rsa key */
-+ hi_u32 e; /*!< The public exponent */
-+ compat_addr d; /*!< The private exponent */
-+ compat_addr n; /*!< The modulus */
-+ compat_addr p; /*!< The p factor of N */
-+ compat_addr q; /*!< The q factor of N */
-+ compat_addr qp; /*!< The 1/q mod p CRT param */
-+ compat_addr dp; /*!< The d mod (p - 1) CRT param */
-+ compat_addr dq; /*!< The d mod (q - 1) CRT param */
-+ compat_addr in; /*!< input data to be encryption */
-+ compat_addr out; /*!< output data of encryption */
-+ hi_u32 inlen; /*!< length of input data to be encryption */
-+ hi_u32 outlen; /*!< length of output data */
++ hi_cipher_rsa_encrypt_scheme scheme; /* RSA encryption scheme */
++ hi_u16 public; /* Type of key, true-public or false-private */
++ hi_u16 ca_type; /* ca Type of key */
++ hi_u32 klen; /* length of rsa key */
++ hi_u32 e; /* The public exponent */
++ compat_addr d; /* The private exponent */
++ compat_addr n; /* The modulus */
++ compat_addr p; /* The p factor of N */
++ compat_addr q; /* The q factor of N */
++ compat_addr qp; /* The 1/q mod p CRT param */
++ compat_addr dp; /* The d mod (p - 1) CRT param */
++ compat_addr dq; /* The d mod (q - 1) CRT param */
++ compat_addr in; /* input data to be encryption */
++ compat_addr out; /* output data of encryption */
++ hi_u32 inlen; /* length of input data to be encryption */
++ hi_u32 outlen; /* length of output data */
+} rsa_info_t;
+
-+/** RSA PKCS style key */
++/* RSA PKCS style key */
+typedef struct {
-+ /** Type of key, true-public or false-private */
-+ hi_u8 public;
-+ /** The key source */
-+ hi_u8 ca_type;
-+ /** The key length */
-+ hi_u16 klen;
-+ /** The public exponent */
-+ hi_u32 e;
-+ /** The private exponent */
-+ hi_u8 *d;
-+ /** The modulus */
-+ hi_u8 *n;
-+ /** The p factor of n */
-+ hi_u8 *p;
-+ /** The q factor of n */
-+ hi_u8 *q;
-+ /** The 1/q mod p CRT param */
-+ hi_u8 *qp;
-+ /** The d mod (p - 1) CRT param */
-+ hi_u8 *dp;
-+ /** The d mod (q - 1) CRT param */
-+ hi_u8 *dq;
-+ /** The buffer size alloc for n */
-+ hi_u32 bufsize;
++ hi_u8 public; /* Type of key, true-public or false-private */
++ hi_u8 ca_type; /* The key source */
++ hi_u16 klen; /* The key length */
++ hi_u32 e; /* The public exponent */
++ hi_u8 *d; /* The private exponent */
++ hi_u8 *n; /* The modulus */
++ hi_u8 *p; /* The p factor of n */
++ hi_u8 *q; /* The q factor of n */
++ hi_u8 *qp; /* The 1/q mod p CRT param */
++ hi_u8 *dp; /* The d mod (p - 1) CRT param */
++ hi_u8 *dq; /* The d mod (q - 1) CRT param */
++ hi_u32 bufsize; /* The buffer size alloc for n */
+} cryp_rsa_key;
+
-+/*! \struct of klad key */
++/* struct of rsa crypt input and output data. */
++typedef struct {
++ hi_cipher_rsa_encrypt_scheme scheme;
++ hi_u8 *in;
++ hi_u32 in_len;
++ hi_u8 *out;
++ hi_u32 out_len;
++} cryp_rsa_crypt_data;
++
++/* struct of rsa sign or verify data. */
++typedef struct {
++ hi_cipher_rsa_sign_scheme scheme;
++ hi_u8 *in;
++ hi_u32 in_len;
++ hi_u8 *out;
++ hi_u32 out_len;
++} cryp_rsa_sign_data;
++
++/* struct of klad key */
+typedef struct {
+ hi_u32 keysel;
+ hi_u32 target;
-+ hi_u32 clear[AES_BLOCK_SIZE / WORD_WIDTH];
-+ hi_u32 encrypt[AES_BLOCK_SIZE / WORD_WIDTH];
++ hi_u8 clear[AES_BLOCK_SIZE];
++ hi_u8 encrypt[AES_BLOCK_SIZE];
+} klad_key_t;
+
-+/*! \struct of trng */
++/* struct of trng */
+typedef struct {
-+ hi_u32 randnum; /*!< randnum rand number */
-+ hi_u32 timeout; /*!< time out */
++ hi_u32 randnum; /* randnum rand number */
++ hi_u32 timeout; /* time out */
+} trng_t;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup crypto*/
-+/** @{*/ /** <!-- [link]*/
-+
-+/**
-+\brief Kapi Init.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi Init.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_symc_init(hi_void);
+
-+/**
-+\brief Kapi Deinit.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi Deinit.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_symc_deinit(hi_void);
+
-+/**
-+\brief Kapi release.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi release.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_symc_release(hi_void);
+
-+/**
-+\brief Create symc handle.
-+\param[in] id The channel number.
-+\param[in] uuid The user identification.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Create symc handle.
++ * param[in] id The channel number.
++ * param[in] uuid The user identification.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_symc_create(hi_u32 *id);
+
-+/**
-+\brief Destroy symc handle.
-+\param[in] id The channel number.
-+\param[in] uuid The user identification.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Destroy symc handle.
++ * param[in] id The channel number.
++ * param[in] uuid The user identification.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_symc_destroy(hi_u32 id);
+
-+/**
-+\brief set work params.
-+* \param[in] id The channel number.
-+* \param[in] hard_key whether use the hard key or not.
-+* \param[in] alg The symmetric cipher algorithm.
-+* \param[in] mode The symmetric cipher mode.
-+* \param[in] sm1_round_num The round number of sm1.
-+* \param[in] fkey first key buffer, defualt
-+* \param[in] skey second key buffer, expand
-+* \param[in] klen The key length.
-+* \param[in] aad Associated Data
-+* \param[in] alen Associated Data Length
-+* \param[in] tlen Tag length
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 kapi_symc_config(hi_u32 id,
-+ hi_u32 hard_key,
-+ hi_cipher_alg alg,
-+ hi_cipher_work_mode work_mode,
-+ hi_cipher_bit_width bit_width,
-+ hi_cipher_key_length key_len,
-+ hi_cipher_sm1_round sm1_round_num,
-+ hi_u8 *fkey, hi_u8 *skey,
-+ hi_u8 *iv, hi_u32 ivlen, hi_u32 iv_usage,
-+ compat_addr aad, hi_u32 alen, hi_u32 tlen);
++/*
++ * brief set work params.
++ * param[in] cfg config information.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 kapi_symc_cfg(symc_cfg_t *cfg);
+
-+/**
-+\brief get work params.
-+* \param[in] id The channel number.
-+* \param[out] ctrl infomation.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 kapi_symc_get_config(hi_u32 id, hi_cipher_ctrl *ctrl);
++/*
++ * brief get work params.
++ * param[in] id The channel number.
++ * param[out] ctrl infomation.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 kapi_symc_get_cfg(hi_u32 id, hi_cipher_ctrl *ctrl);
+
-+/**
-+ * \brief SYMC buffer encryption/decryption.
++/*
++ * brief SYMC buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param[in] id The channel number.
-+ * \param input buffer holding the input data
-+ * \param output buffer holding the output data
-+ * \param length length of the input data
-+ * \param operation decrypt or encrypt
++ * param[in] crypt The symc info data.
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 kapi_symc_crypto(hi_u32 id, compat_addr input,
-+ compat_addr output, hi_u32 length,
-+ hi_u32 operation, hi_u32 last);
++hi_s32 kapi_symc_crypto(symc_encrypt_t *crypt);
+
-+/**
-+ * \brief SYMC via buffer encryption/decryption.
++/*
++ * brief SYMC via buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param[in] id The channel number.
-+ * \param input buffer holding the input data
-+ * \param output buffer holding the output data
-+ * \param length length of the input data
-+ * \param operation decrypt or encrypt
++ * param[in] crypt The symc info data.
++ * param[in] is_from_user input and output virtual address is from user or kapi.
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 kapi_symc_crypto_via(hi_u32 id, compat_addr input,
-+ compat_addr output, hi_u32 length,
-+ hi_u32 operation, hi_u32 last,
-+ hi_u32 is_from_user);
++hi_s32 kapi_symc_crypto_via(symc_encrypt_t *crypt, hi_u32 is_from_user);
+
-+/**
-+ * \brief SYMC multiple buffer encryption/decryption.
++/*
++ * brief SYMC multiple buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param[in] id The channel number.
-+ * \param pkg Buffer of package infomation
-+ * \param pkg_num Number of package infomation
-+ * \param operation decrypt or encrypt
-+ * \param last last or not
++ * param[in] id The channel number.
++ * param pack Buffer of package infomation
++ * param pack_num Number of package infomation
++ * param operation decrypt or encrypt
++ * param last last or not
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 kapi_symc_crypto_multi(hi_u32 id, const hi_void *pkg,
-+ hi_u32 pkg_num, hi_u32 operation,
-+ hi_u32 last);
++hi_s32 kapi_symc_crypto_multi(hi_u32 id, const hi_void *pack, hi_u32 pack_num, hi_u32 operation, hi_u32 last);
+
-+/**
-+ * \brief SYMC multiple buffer encryption/decryption.
-+ * \param[in] id The channel number.
-+ * \param[in] tag tag data of CCM/GCM
++/*
++ * brief SYMC multiple buffer encryption/decryption.
++ * param[in] id The channel number.
++ * param[in] tag tag data of CCM/GCM
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
+hi_s32 kapi_aead_get_tag(hi_u32 id, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen);
+
-+/**
-+\brief Kapi Init.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi Init.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_hash_init(hi_void);
+
-+/**
-+\brief Kapi Deinit.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi Deinit.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_hash_deinit(hi_void);
+
-+/**
-+ * \brief HASH context setup.
++/*
++ * brief HASH context setup.
+ *
+ *
-+ * \param[out] id The channel number.
-+ * \param[in] type Hash type
-+ * \param[in] key hmac key
-+ * \param[in] keylen hmac key length
++ * param[out] id The channel number.
++ * param[in] type Hash type
++ * param[in] key hmac key
++ * param[in] keylen hmac key length
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 kapi_hash_start(hi_u32 *id, hi_cipher_hash_type type,
-+ hi_u8 *key, hi_u32 keylen);
++hi_s32 kapi_hash_start(hi_u32 *id, hi_cipher_hash_type type, hi_u8 *key, hi_u32 keylen);
+
-+/**
-+ * \brief HASH process buffer.
++/*
++ * brief HASH process buffer.
+ *
-+ * \param[in] id The channel number.
-+ * \param[in] input buffer holding the input data
-+ * \param[in] length length of the input data
-+ * \param[in] src source of hash message
++ * param[in] id The channel number.
++ * param[in] input buffer holding the input data
++ * param[in] length length of the input data
++ * param[in] src source of hash message
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 kapi_hash_update(hi_u32 id, hi_u8 *input, hi_u32 length,
-+ hash_chunk_src src);
++hi_s32 kapi_hash_update(hi_u32 id, hi_u8 *input, hi_u32 length, hash_chunk_src src);
+
-+/**
-+ * \brief HASH final digest.
++/*
++ * brief HASH final digest.
+ *
-+ * \param[in] id The channel number.
-+ * \param[out] hash buffer holding the hash data
-+ * \param[out] hashlen length of the hash data
++ * param[in] id The channel number.
++ * param[out] hash buffer holding the hash data_type_t
++ * param[in] hash_buf_len buffer length of holding the hash data
++ * param[out] hashlen length of the hash data
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 kapi_hash_finish(hi_u32 id, hi_u8 *hash, hi_u32 *hashlen);
++hi_s32 kapi_hash_finish(hi_u32 id, hi_u8 *hash, hi_u32 hash_buf_len, hi_u32 *hashlen);
+
-+/**
-+\brief hash release.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief hash release.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_hash_release(hi_void);
+
-+/**
-+\brief Kapi Init.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi Init.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_rsa_init(hi_void);
+
-+/**
-+\brief Kapi Deinitialize.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi Deinitialize.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_rsa_deinit(hi_void);
+
-+/**
-+* \brief RSA encryption a plaintext with a RSA private key.
-+*
-+* \param[in] key: rsa key struct.
-+* \param[in] scheme: rsa encrypt/decrypt scheme.
-+* \param[in] in: input data to be encryption
-+* \param[out] inlen: length of input data to be encryption
-+* \param[out] out: output data of encryption
-+* \param[out] outlen: length of output data to be encryption
-+* \retval ::HI_SUCCESS Call this API successful
-+* \retval ::HI_FAILURE Call this API fails.
-+*/
-+hi_s32 kapi_rsa_encrypt(cryp_rsa_key *key,
-+ hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen);
++/*
++ * brief RSA encryption a plaintext with a RSA private key.
++ *
++ * param[in] key: rsa key struct.
++ * param[in/out] rsa: rsa encrypt/decrypt data.
++ * retval ::HI_SUCCESS Call this API successful
++ * retval ::HI_FAILURE Call this API fails.
++ */
++hi_s32 kapi_rsa_encrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa);
+
-+/**
-+* \brief RSA decryption a ciphertext with a RSA public key.
-+*
-+* \param[in] key: rsa key struct.
-+* \param[in] scheme: rsa encrypt/decrypt scheme.
-+* \param[in] in: input data to be encryption
-+* \param[in] inlen: length of input data to be encryption
-+* \param[out] out: output data to be encryption
-+* \param[out] outlen: length of output data to be encryption
-+* \retval ::HI_SUCCESS Call this API successful
-+* \retval ::HI_FAILURE Call this API fails.
-+*/
-+hi_s32 kapi_rsa_decrypt(cryp_rsa_key *key,
-+ hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen);
++/*
++ * brief RSA decryption a ciphertext with a RSA public key.
++ *
++ * param[in] key: rsa key struct.
++ * param[in/out] rsa: rsa encrypt/decrypt data.
++ * retval ::HI_SUCCESS Call this API successful
++ * retval ::HI_FAILURE Call this API fails.
++ */
++hi_s32 kapi_rsa_decrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa);
+
-+/**
-+* \brief RSA signature a context with appendix, where a signer's RSA private key is used.
-+*
-+* \param[in] key: rsa key struct.
-+* \param[in] scheme: rsa signature/verify scheme.
-+* \param[in] in: input data to be encryption
-+* \param[in] inlen: length of input data to be encryption
-+* \param[in] hash: hash value of context,if NULL, let hash = Hash(context) automatically
-+* \param[out] out: output data to be encryption
-+* \param[out] outlen: length of output data to be encryption
-+* \param[in] src source of hash message
-+* \param[in] uuid uuid The user identification.
-+* \retval ::HI_SUCCESS Call this API successful
-+* \retval ::HI_FAILURE Call this API fails.
-+*/
-+hi_s32 kapi_rsa_sign_hash(cryp_rsa_key *key,
-+ hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *hash, hi_u32 hlen,
-+ hi_u8 *sign, hi_u32 *signlen);
++/*
++ * brief RSA signature a context with appendix, where a signer's RSA private key is used.
++ *
++ * param[in] key: rsa key struct.
++ * param[in/out] rsa: rsa signature data.
++ * retval ::HI_SUCCESS Call this API successful
++ * retval ::HI_FAILURE Call this API fails.
++ */
++hi_s32 kapi_rsa_sign_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa);
+
-+/**
-+* \brief RSA verify a ciphertext with a RSA public key.
-+*
-+* \param[in] key_info: encryption struct.
-+* \param[in] in: input data to be encryption
-+* \param[out] inlen: length of input data to be encryption
-+* \param[in] hash: hash value of context,if NULL, let hash = Hash(context) automatically
-+* \param[out] out: output data to be encryption
-+* \param[out] outlen: length of output data to be encryption
-+* \param[in] src source of hash message
-+* \retval ::HI_SUCCESS Call this API successful
-+* \retval ::HI_FAILURE Call this API fails.
-+*/
-+hi_s32 kapi_rsa_verify_hash(cryp_rsa_key *key,
-+ hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *hash, hi_u32 hlen,
-+ hi_u8 *sign, hi_u32 signlen);
++/*
++ * brief RSA verify a ciphertext with a RSA public key.
++ *
++ * param[in] key: rsa key struct.
++ * param[in/out] rsa: rsa verify data.
++ * retval ::HI_SUCCESS Call this API successful
++ * retval ::HI_FAILURE Call this API fails.
++ */
++hi_s32 kapi_rsa_verify_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa);
+
-+/**
-+\brief get rand number.
-+\param[out] randnum rand number.
-+\param[in] timeout time out.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief get rand number.
++ * param[out] randnum rand number.
++ * param[in] timeout time out.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_trng_get_random(hi_u32 *randnum, hi_u32 timeout);
+
-+/* cipher kapi_test */
-+hi_void kapi_test(hi_void);
++/* cipher kapi_test_main */
++hi_void kapi_test_main(hi_void);
+
-+/** @}*/ /** <!-- ==== API Code end ====*/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
-+#endif /* End of #ifndef __DRV_CIPHER_KAPI_H__*/
++#endif /* End of #ifndef __DRV_CIPHER_KAPI_H__ */
diff --git a/drivers/crypto/hisi-cipher/include/hi_cipher_compat.h b/drivers/crypto/hisi-cipher/include/hi_cipher_compat.h
new file mode 100644
-index 0000000..bc83176
+index 0000000..fb3a7b7
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/include/hi_cipher_compat.h
-@@ -0,0 +1,344 @@
+@@ -0,0 +1,378 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (C), Hisilicon Technologies Co., Ltd. 2019-2019. All rights reserved.
++ * Description : head file for cipher compat.
++ * Author : Hisilicon multimedia software group
++ * Create : 2019-3-10
+ */
+
+#ifndef __HI_CIPHER_COMPAT_H__
@@ -197743,91 +266833,108 @@ index 0000000..bc83176
+#endif
+#endif /* __cplusplus */
+
++#define HI_CIPHER_DES_IV_SIZE_IN_WORD 2
++#define HI_CIPHER_IV_SIZE_IN_WORD 4
++#define HI_CIPHER_DES_KEY_SIZE_IN_WORD 2
++#define HI_CIPHER_TDES_KEY_SIZE_IN_WORD 6
++#define HI_CIPHER_AES_KEY_SIZE_IN_WORD 8
++#define HI_CIPHER_SM1_KEY_SIZE_IN_WORD 4
++#define HI_CIPHER_SM4_KEY_SIZE_IN_WORD 4
++
++/* CIPHER set IV for first package */
++#define HI_CIPHER_IV_CHG_ONE_PACK 1
++
++/* CIPHER set IV for first package */
++#define HI_CIPHER_IV_CHG_ALL_PACK 2
++
++#define HI_ERR_CIPHER_INVALID_PARAM 0x804D0004
++#define HI_ERR_CIPHER_INVALID_LEN 0x804D0018
++
+/* enum typedef */
-+/* Cipher work mode */
++/* Cipher work mode. */
+typedef enum {
+ HI_CIPHER_WORK_MODE_ECB = 0x0, /* Electronic codebook (ECB) mode, ECB has been considered insecure and it is
-+ recommended not to use it.*/
-+ HI_CIPHER_WORK_MODE_CBC, /* Cipher block chaining (CBC) mode*/
-+ HI_CIPHER_WORK_MODE_CFB, /* Cipher feedback (CFB) mode*/
-+ HI_CIPHER_WORK_MODE_OFB, /* Output feedback (OFB) mode*/
-+ HI_CIPHER_WORK_MODE_CTR, /* Counter (CTR) mode*/
-+ HI_CIPHER_WORK_MODE_CCM, /* Counter (CCM) mode*/
-+ HI_CIPHER_WORK_MODE_GCM, /* Counter (GCM) mode*/
-+ HI_CIPHER_WORK_MODE_CBC_CTS, /* Cipher block chaining CipherStealing mode*/
++ recommended not to use it. */
++ HI_CIPHER_WORK_MODE_CBC, /* Cipher block chaining (CBC) mode. */
++ HI_CIPHER_WORK_MODE_CFB, /* Cipher feedback (CFB) mode. */
++ HI_CIPHER_WORK_MODE_OFB, /* Output feedback (OFB) mode. */
++ HI_CIPHER_WORK_MODE_CTR, /* Counter (CTR) mode. */
++ HI_CIPHER_WORK_MODE_CCM, /* Counter (CCM) mode. */
++ HI_CIPHER_WORK_MODE_GCM, /* Counter (GCM) mode. */
++ HI_CIPHER_WORK_MODE_CBC_CTS, /* Cipher block chaining CipherStealing mode. */
+ HI_CIPHER_WORK_MODE_BUTT,
+ HI_CIPHER_WORK_MODE_INVALID = 0xffffffff,
-+}hi_cipher_work_mode;
++} hi_cipher_work_mode;
+
-+/* Cipher algorithm */
++/* Cipher algorithm. */
+typedef enum {
-+ HI_CIPHER_ALG_DES = 0x0, /* Data encryption standard (DES) algorithm,DES has been considered
++ HI_CIPHER_ALG_DES = 0x0, /* Data encryption standard (DES) algorithm, DES has been considered
+ insecure and it is recommended not to use it. */
-+ HI_CIPHER_ALG_3DES = 0x1, /* 3DES algorithm */
-+ HI_CIPHER_ALG_AES = 0x2, /* Advanced encryption standard (AES) algorithm */
-+ HI_CIPHER_ALG_SM1 = 0x3, /* SM1 algorithm*/
-+ HI_CIPHER_ALG_SM4 = 0x4, /* SM4 algorithm*/
-+ HI_CIPHER_ALG_DMA = 0x5, /* DMA copy*/
++ HI_CIPHER_ALG_3DES = 0x1, /* 3DES algorithm. */
++ HI_CIPHER_ALG_AES = 0x2, /* Advanced encryption standard (AES) algorithm. */
++ HI_CIPHER_ALG_SM1 = 0x3, /* SM1 algorithm. */
++ HI_CIPHER_ALG_SM4 = 0x4, /* SM4 algorithm. */
++ HI_CIPHER_ALG_DMA = 0x5, /* DMA copy. */
+ HI_CIPHER_ALG_BUTT = 0x6,
+ HI_CIPHER_ALG_INVALID = 0xffffffff,
-+}hi_cipher_alg;
++} hi_cipher_alg;
+
-+/* Key length */
++/* Key length. */
+typedef enum {
-+ HI_CIPHER_KEY_AES_128BIT = 0x0, /* 128-bit key for the AES algorithm */
-+ HI_CIPHER_KEY_AES_192BIT = 0x1, /* 192-bit key for the AES algorithm */
-+ HI_CIPHER_KEY_AES_256BIT = 0x2, /* 256-bit key for the AES algorithm */
-+ HI_CIPHER_KEY_DES_3KEY = 0x2, /* Three keys for the DES algorithm */
-+ HI_CIPHER_KEY_DES_2KEY = 0x3, /* Two keys for the DES algorithm */
-+ HI_CIPHER_KEY_DEFAULT = 0x0, /* Default key length, DES-8, SM1-48, SM4-16 */
++ HI_CIPHER_KEY_AES_128BIT = 0x0, /* 128-bit key for the AES algorithm. */
++ HI_CIPHER_KEY_AES_192BIT = 0x1, /* 192-bit key for the AES algorithm. */
++ HI_CIPHER_KEY_AES_256BIT = 0x2, /* 256-bit key for the AES algorithm. */
++ HI_CIPHER_KEY_DES_3KEY = 0x2, /* Three keys for the DES algorithm. */
++ HI_CIPHER_KEY_DES_2KEY = 0x3, /* Two keys for the DES algorithm. */
++ HI_CIPHER_KEY_DEFAULT = 0x0, /* Default key length, DES-8, SM1-48, SM4-16. */
+ HI_CIPHER_KEY_INVALID = 0xffffffff,
-+}hi_cipher_key_length;
++} hi_cipher_key_len;
+
-+/* Cipher bit width */
++/* Cipher bit width. */
+typedef enum {
+ HI_CIPHER_BIT_WIDTH_64BIT = 0x0, /* 64-bit width */
+ HI_CIPHER_BIT_WIDTH_8BIT = 0x1, /* 8-bit width */
+ HI_CIPHER_BIT_WIDTH_1BIT = 0x2, /* 1-bit width */
+ HI_CIPHER_BIT_WIDTH_128BIT = 0x3, /* 128-bit width */
+ HI_CIPHER_BIT_WIDTH_INVALID = 0xffffffff,
-+}hi_cipher_bit_width;
++} hi_cipher_bit_width;
+
-+/* Key ladder selecting parameters */
++/* Key ladder selecting parameters. */
+typedef enum {
-+ HI_CIPHER_KEY_SRC_USER = 0x0, /**< User Key*/
-+ HI_CIPHER_KEY_SRC_KLAD_1, /**< KLAD Key 1*/
-+ HI_CIPHER_KEY_SRC_KLAD_2, /**< KLAD Key 2*/
-+ HI_CIPHER_KEY_SRC_KLAD_3, /**< KLAD Key 3*/
++ HI_CIPHER_KEY_SRC_USER = 0x0, /* User Key. */
++ HI_CIPHER_KEY_SRC_KLAD_1, /* KLAD Key 1. */
++ HI_CIPHER_KEY_SRC_KLAD_2, /* KLAD Key 2. */
++ HI_CIPHER_KEY_SRC_KLAD_3, /* KLAD Key 3. */
+ HI_CIPHER_KEY_SRC_BUTT,
+ HI_CIPHER_KEY_SRC_INVALID = 0xffffffff,
-+}hi_cipher_ca_type;
++} hi_cipher_ca_type;
+
-+/** Klad target */
++/** Klad target. */
+typedef enum {
-+ HI_CIPHER_KLAD_TARGET_AES = 0x0, /**< Klad for AES*/
-+ HI_CIPHER_KLAD_TARGET_RSA, /**< Klad for RSA*/
++ HI_CIPHER_KLAD_TARGET_AES = 0x0, /* Klad for AES. */
++ HI_CIPHER_KLAD_TARGET_RSA, /* Klad for RSA. */
+ HI_CIPHER_KLAD_TARGET_BUTT,
+} hi_cipher_klad_target;
+
-+/* Encryption/Decryption type selecting */
++/* Encryption/Decryption type selecting. */
+typedef enum {
+ HI_CIPHER_TYPE_NORMAL = 0x0,
+ HI_CIPHER_TYPE_COPY_AVOID,
+ HI_CIPHER_TYPE_BUTT,
+ HI_CIPHER_TYPE_INVALID = 0xffffffff,
-+}hi_cipher_type;
++} hi_cipher_type;
+
+/* SM1 round config */
+typedef enum {
-+ HI_CIPHER_SM1_ROUND_08 = 0x00, /* SM1 round 08 */
-+ HI_CIPHER_SM1_ROUND_10 = 0x01, /* SM1 round 10 */
-+ HI_CIPHER_SM1_ROUND_12 = 0x02, /* SM1 round 12 */
-+ HI_CIPHER_SM1_ROUND_14 = 0x03, /* SM1 round 14 */
++ HI_CIPHER_SM1_ROUND_08 = 0x00, /* SM1 round 08. */
++ HI_CIPHER_SM1_ROUND_10 = 0x01, /* SM1 round 10. */
++ HI_CIPHER_SM1_ROUND_12 = 0x02, /* SM1 round 12. */
++ HI_CIPHER_SM1_ROUND_14 = 0x03, /* SM1 round 14. */
+ HI_CIPHER_SM1_ROUND_BUTT,
+ HI_CIPHER_SM1_ROUND_INVALID = 0xffffffff,
-+}hi_cipher_sm1_round;
++} hi_cipher_sm1_round;
+
-+/* Hash algrithm type */
++/* Hash algrithm type. */
+typedef enum {
+ HI_CIPHER_HASH_TYPE_SHA1,
+ HI_CIPHER_HASH_TYPE_SHA224,
@@ -197842,151 +266949,152 @@ index 0000000..bc83176
+ HI_CIPHER_HASH_TYPE_SM3,
+ HI_CIPHER_HASH_TYPE_BUTT,
+ HI_CIPHER_HASH_TYPE_INVALID = 0xffffffff,
-+}hi_cipher_hash_type;
++} hi_cipher_hash_type;
+
-+/* Rsa encrypt and decrypt scheme */
++/* Rsa encrypt and decrypt scheme. */
+typedef enum {
-+ HI_CIPHER_RSA_ENC_SCHEME_NO_PADDING = 0x00, /* without padding */
-+ HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0, /* PKCS#1 block type 0 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_1, /* PKCS#1 block type 1padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_2, /* PKCS#1 block type 2 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA1, /* PKCS#1 RSAES-OAEP-SHA1 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA224, /* PKCS#1 RSAES-OAEP-SHA224 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA256, /* PKCS#1 RSAES-OAEP-SHA256 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA384, /* PKCS#1 RSAES-OAEP-SHA384 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA512, /* PKCS#1 RSAES-OAEP-SHA512 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_RSAES_PKCS1_V1_5, /* PKCS#1 RSAES-PKCS1_V1_5 padding*/
-+ HI_CIPHER_RSA_ENC_SCHEME_BUTT,
-+ HI_CIPHER_RSA_ENC_SCHEME_INVALID = 0xffffffff,
-+}hi_cipher_rsa_enc_scheme;
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_NO_PADDING = 0x00, /* without padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_0, /* PKCS#1 block type 0 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_1, /* PKCS#1 block type 1padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_2, /* PKCS#1 block type 2 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA1, /* PKCS#1 RSAES-OAEP-SHA1 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA224, /* PKCS#1 RSAES-OAEP-SHA224 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA256, /* PKCS#1 RSAES-OAEP-SHA256 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA384, /* PKCS#1 RSAES-OAEP-SHA384 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA512, /* PKCS#1 RSAES-OAEP-SHA512 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_PKCS1_V1_5, /* PKCS#1 RSAES-PKCS1_V1_5 padding. */
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_BUTT,
++ HI_CIPHER_RSA_ENCRYPT_SCHEME_INVALID = 0xffffffff,
++} hi_cipher_rsa_encrypt_scheme;
+
-+/* Rsa sign and verify scheme */
++/* Rsa sign and verify scheme. */
+typedef enum {
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA1 = 0x100, /* PKCS#1 RSASSA_PKCS1_V15_SHA1 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA224, /* PKCS#1 RSASSA_PKCS1_V15_SHA224 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA256, /* PKCS#1 RSASSA_PKCS1_V15_SHA256 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA384, /* PKCS#1 RSASSA_PKCS1_V15_SHA384 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA512, /* PKCS#1 RSASSA_PKCS1_V15_SHA512 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA1, /* PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA224, /* PKCS#1 RSASSA_PKCS1_PSS_SHA224 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA256, /* PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA384, /* PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature*/
-+ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA512, /* PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature*/
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA1 = 0x100, /* PKCS#1 RSASSA_PKCS1_V15_SHA1 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA224, /* PKCS#1 RSASSA_PKCS1_V15_SHA224 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA256, /* PKCS#1 RSASSA_PKCS1_V15_SHA256 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA384, /* PKCS#1 RSASSA_PKCS1_V15_SHA384 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA512, /* PKCS#1 RSASSA_PKCS1_V15_SHA512 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA1, /* PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA224, /* PKCS#1 RSASSA_PKCS1_PSS_SHA224 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA256, /* PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA384, /* PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature. */
++ HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA512, /* PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature. */
+ HI_CIPHER_RSA_SIGN_SCHEME_BUTT,
+ HI_CIPHER_RSA_SIGN_SCHEME_INVALID = 0xffffffff,
-+}hi_cipher_rsa_sign_scheme;
++} hi_cipher_rsa_sign_scheme;
+
-+/* struct define */
-+/* Cipher control parameters */
++/* struct define. */
++/* Cipher control parameters. */
+typedef struct {
-+ hi_u32 bit1_iv : 2; /* Initial Vector change flag, 0-don't set, 1-set IV for first package, 2-set
-+ IV for each package */
-+ hi_u32 bits_reserve: 30; /* Reserved */
-+}hi_cipher_ctrl_change_flag;
++ hi_u32 bits_iv : 2; /* Initial Vector change flag, 0-don't set, 1-set IV for first package, 2-set
++ IV for each package. */
++ hi_u32 bits_resv : 30; /* Reserved. */
++} hi_cipher_ctrl_chg_flag;
+
+/* Structure of the cipher type */
+typedef struct {
+ hi_cipher_type cipher_type;
-+}hi_cipher_atts;
++} hi_cipher_attr;
+
+/* Structure of the cipher control information */
+typedef struct {
-+ hi_u32 key[8]; /* Key input */
-+ hi_u32 iv[4]; /* Initialization vector (IV) */
++ hi_u32 key[HI_CIPHER_AES_KEY_SIZE_IN_WORD]; /* Key input */
++ hi_u32 iv[HI_CIPHER_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
+ hi_bool key_by_ca; /* Encryption using advanced conditional access (CA) or decryption using keys */
+ hi_cipher_ca_type ca_type; /* Select keyladder type when using advanced CA */
+ hi_cipher_alg alg; /* Cipher algorithm */
+ hi_cipher_bit_width bit_width; /* Bit width for encryption or decryption */
+ hi_cipher_work_mode work_mode; /* Operating mode */
-+ hi_cipher_key_length key_len; /* Key length */
-+ hi_cipher_ctrl_change_flag change_flags; /* control information exchange choices, we default all woulde be change
-+ except they have been in the choices */
++ hi_cipher_key_len key_len; /* Key length */
++ hi_cipher_ctrl_chg_flag chg_flags; /* control information exchange choices, we default all woulde be change
++ except they have been in the choices */
+} hi_cipher_ctrl;
+
+/* Structure of the cipher AES control information */
+typedef struct {
-+ hi_u32 even_key[8]; /* Key input, default use this key*/
-+ hi_u32 odd_key[8]; /* Key input, only valid for Multi encrypt/decrypt*/
-+ hi_u32 iv[4]; /* Initialization vector (IV) */
-+ hi_cipher_bit_width bit_width; /* Bit width for encryption or decryption */
-+ hi_cipher_key_length key_len; /* Key length */
-+ hi_cipher_ctrl_change_flag change_flags; /* control information exchange choices, we default all woulde be change
-+ except they have been in the choices */
++ hi_u32 even_key[HI_CIPHER_AES_KEY_SIZE_IN_WORD]; /* Key input, default use this key. */
++ hi_u32 odd_key[HI_CIPHER_AES_KEY_SIZE_IN_WORD]; /* Key input, only valid for Multi encrypt/decrypt. */
++ hi_u32 iv[HI_CIPHER_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ hi_cipher_bit_width bit_width; /* Bit width for encryption or decryption */
++ hi_cipher_key_len key_len; /* Key length */
++ hi_cipher_ctrl_chg_flag chg_flags; /* control information exchange choices, we default all woulde be change
++ except they have been in the choices */
+} hi_cipher_ctrl_aes;
+
+/* Structure of the cipher AES CCM/GCM control information */
+typedef struct {
-+ hi_u32 key[8]; /* Key input */
-+ hi_u32 iv[4]; /* Initialization vector (IV) */
-+ hi_cipher_key_length key_len; /* Key length */
++ hi_u32 key[HI_CIPHER_AES_KEY_SIZE_IN_WORD]; /* Key input */
++ hi_u32 iv[HI_CIPHER_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ hi_cipher_key_len key_len; /* Key length */
+ hi_u32 iv_len; /* IV lenght for CCM/GCM, which is an element of {7, 8, 9, 10, 11, 12, 13}
-+ for CCM, and is an element of [1-16] for GCM*/
-+ hi_u32 tag_len; /* Tag lenght for CCM which is an element of {4,6,8,10,12,14,16}*/
-+ hi_u32 a_len; /* Associated data for CCM and GCM*/
-+ hi_size_t a_phy_addr; /* Physical address of Associated data for CCM and GCM*/
++ for CCM, and is an element of [1-16] for GCM. */
++ hi_u32 tag_len; /* Tag lenght for CCM which is an element of {4,6,8,10,12,14,16}. */
++ hi_u32 aad_len; /* Associated data for CCM and GCM. */
++ hi_phys_addr_t aad_phys_addr; /* Physical address of Associated data for CCM and GCM. */
+} hi_cipher_ctrl_aes_ccm_gcm;
+
+/* Structure of the cipher DES control information */
+typedef struct {
-+ hi_u32 key[2]; /* Key input */
-+ hi_u32 iv[2]; /* Initialization vector (IV) */
++ hi_u32 key[HI_CIPHER_DES_KEY_SIZE_IN_WORD]; /* Key input */
++ hi_u32 iv[HI_CIPHER_DES_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
+ hi_cipher_bit_width bit_width; /* Bit width for encryption or decryption */
-+ hi_cipher_ctrl_change_flag change_flags; /* Control information exchange choices, we default all woulde be change
++ hi_cipher_ctrl_chg_flag chg_flags; /* Control information exchange choices, we default all woulde be change
+ except they have been in the choices */
+} hi_cipher_ctrl_des;
+
+/* Structure of the cipher 3DES control information */
+typedef struct {
-+ hi_u32 key[6];
-+ hi_u32 iv[2]; /* Initialization vector (IV) */
-+ hi_cipher_bit_width bit_width; /* Bit width for encryption or decryption */
-+ hi_cipher_key_length key_len; /* Key length */
-+ hi_cipher_ctrl_change_flag change_flags; /* control information exchange choices, we default all woulde be change
-+ except they have been in the choices */
++ hi_u32 key[HI_CIPHER_TDES_KEY_SIZE_IN_WORD];
++ hi_u32 iv[HI_CIPHER_DES_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ hi_cipher_bit_width bit_width; /* Bit width for encryption or decryption */
++ hi_cipher_key_len key_len; /* Key length */
++ hi_cipher_ctrl_chg_flag chg_flags; /* control information exchange choices, we default all woulde be change
++ except they have been in the choices */
+} hi_cipher_ctrl_3des;
+
+/* Structure of the cipher SM1 control information */
+typedef struct {
-+ hi_u32 ek[4]; /* Key of EK input */
-+ hi_u32 ak[4]; /* Key of AK input */
-+ hi_u32 sk[4]; /* Key of SK input */
-+ hi_u32 iv[4]; /* Initialization vector (IV) */
++ hi_u32 ek[HI_CIPHER_SM1_KEY_SIZE_IN_WORD]; /* Key of EK input */
++ hi_u32 ak[HI_CIPHER_SM1_KEY_SIZE_IN_WORD]; /* Key of AK input */
++ hi_u32 sk[HI_CIPHER_SM1_KEY_SIZE_IN_WORD]; /* Key of SK input */
++ hi_u32 iv[HI_CIPHER_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
+ hi_cipher_bit_width bit_width; /* Bit width for encryption or decryption */
-+ hi_cipher_sm1_round sm1_round; /* SM1 round number, should be 8, 10, 12 or 14*/
-+ hi_cipher_ctrl_change_flag change_flags; /* control information exchange choices, we default all woulde be change
++ hi_cipher_sm1_round sm1_round; /* SM1 round number, should be 8, 10, 12 or 14. */
++ hi_cipher_ctrl_chg_flag chg_flags; /* control information exchange choices, we default all woulde be change
+ except they have been in the choices */
+} hi_cipher_ctrl_sm1;
+
+/* Structure of the cipher SM4 control information */
+typedef struct {
-+ hi_u32 key[4]; /* Key input */
-+ hi_u32 iv[4]; /* Initialization vector (IV) */
-+ hi_cipher_ctrl_change_flag change_flags; /* control information exchange choices, we default all woulde be change
++ hi_u32 key[HI_CIPHER_SM4_KEY_SIZE_IN_WORD]; /* Key input */
++ hi_u32 iv[HI_CIPHER_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ hi_cipher_ctrl_chg_flag chg_flags; /* control information exchange choices, we default all woulde be change
+ except they have been in the choices */
+} hi_cipher_ctrl_sm4;
+
+/* Expand Structure of the cipher control information */
+typedef struct {
-+ hi_cipher_alg alg; /* Cipher algorithm */
-+ hi_cipher_work_mode work_mode; /* Operating mode */
-+ hi_bool key_by_ca; /* Encryption using advanced conditional access (CA) or decryption using keys */
-+ /* Parameter for special algorithm
-+ for AES, the pointer should point to hi_cipher_ctrl_aes;
-+ for AES_CCM or AES_GCM, the pointer should point to hi_cipher_ctrl_aes_ccm_gcm;
-+ for DES, the pointer should point to hi_cipher_ctrl_des;
-+ for 3DES, the pointer should point to hi_cipher_ctrl_3des;
-+ for SM1, the pointer should point to hi_cipher_ctrl_sm1;
-+ for SM4, the pointer should point to hi_cipher_ctrl_sm4;
-+ */
++ hi_cipher_alg alg; /* Cipher algorithm. */
++ hi_cipher_work_mode work_mode; /* Operating mode. */
++ hi_bool key_by_ca; /* Encryption using advanced conditional access (CA) or decryption using keys. */
++
++ /* Parameter for special algorithm
++ * for AES, the pointer should point to hi_cipher_ctrl_aes;
++ * for AES_CCM or AES_GCM, the pointer should point to hi_cipher_ctrl_aes_ccm_gcm;
++ * for DES, the pointer should point to hi_cipher_ctrl_des;
++ * for 3DES, the pointer should point to hi_cipher_ctrl_3des;
++ * for SM1, the pointer should point to hi_cipher_ctrl_sm1;
++ * for SM4, the pointer should point to hi_cipher_ctrl_sm4;
++ */
+ hi_void *param;
+} hi_cipher_ctrl_ex;
+
+/* Cipher data */
+typedef struct {
-+ hi_size_t src_phy_addr; /* phy address of the original data */
-+ hi_size_t dest_phy_addr; /* phy address of the purpose data */
-+ hi_u32 byte_length; /* Cigher data length*/
-+ hi_bool odd_key; /* Use odd key or even key*/
++ hi_phys_addr_t src_phys_addr; /* phy address of the original data. */
++ hi_phys_addr_t dst_phys_addr; /* phy address of the purpose data. */
++ hi_u32 byte_len; /* Cigher data length. */
++ hi_bool odd_key; /* Use odd key or even key. */
+} hi_cipher_data;
+
+/* Hash init struct input */
@@ -197994,62 +267102,89 @@ index 0000000..bc83176
+ hi_u8 *hmac_key;
+ hi_u32 hmac_key_len;
+ hi_cipher_hash_type sha_type;
-+}hi_cipher_hash_atts;
++} hi_cipher_hash_attr;
+
+/* RSA public key struct */
+typedef struct {
-+ hi_u8 *n; /* Point to public modulus */
-+ hi_u8 *e; /* Point to public exponent */
-+ hi_u16 n_len; /* Length of public modulus, max value is 512Byte*/
-+ hi_u16 e_len; /* Length of public exponent, max value is 512Byte*/
-+}hi_cipher_rsa_pub_key;
++ hi_u8 *n; /* Point to public modulus. */
++ hi_u8 *e; /* Point to public exponent. */
++ hi_u16 n_len; /* Length of public modulus, max value is 512Byte. */
++ hi_u16 e_len; /* Length of public exponent, max value is 512Byte. */
++} hi_cipher_rsa_pub_key;
+
+/* RSA private key struct */
+typedef struct {
-+ hi_u8 *n; /* Public modulus */
-+ hi_u8 *e; /* Public exponent */
-+ hi_u8 *d; /* Private exponent */
-+ hi_u8 *p; /* 1st prime factor */
-+ hi_u8 *q; /* 2nd prime factor */
-+ hi_u8 *dp; /* d % (p - 1) */
-+ hi_u8 *dq; /* d % (q - 1) */
-+ hi_u8 *qp; /* 1 / (q % p) */
++ hi_u8 *n; /* Public modulus N. */
++ hi_u8 *e; /* Public exponent E. */
++ hi_u8 *d; /* Private exponent D. */
++ hi_u8 *p; /* 1st prime factor P. */
++ hi_u8 *q; /* 2nd prime factor Q. */
++ hi_u8 *dp; /* descript:d % (p - 1) is DP. */
++ hi_u8 *dq; /* descript:d % (q - 1) is DQ. */
++ hi_u8 *qp; /* descript:1 / (q % p) is QP. */
+ hi_u16 n_len; /* Length of public modulus */
+ hi_u16 e_len; /* Length of public exponent */
+ hi_u16 d_len; /* Length of private exponent */
-+ hi_u16 p_len; /* Length of 1st prime factor,should be half of u16NLen */
-+ hi_u16 q_len; /* Length of 2nd prime factor,should be half of u16NLen */
-+ hi_u16 dp_len; /* Length of D % (P - 1),should be half of u16NLen */
-+ hi_u16 dq_len; /* Length of D % (Q - 1),should be half of u16NLen */
-+ hi_u16 qp_len; /* Length of 1 / (Q % P),should be half of u16NLen */
-+}hi_cipher_rsa_pri_key;
++ hi_u16 p_len; /* Length of 1st prime factor,should be half of n_len */
++ hi_u16 q_len; /* Length of 2nd prime factor,should be half of n_len */
++ hi_u16 dp_len; /* Length of D % (P - 1),should be half of n_len */
++ hi_u16 dq_len; /* Length of D % (Q - 1),should be half of n_len */
++ hi_u16 qp_len; /* Length of 1 / (Q % P),should be half of n_len */
++} hi_cipher_rsa_private_key;
+
+/* RSA public key encryption struct input */
+typedef struct {
-+ hi_cipher_rsa_enc_scheme scheme; /* RSA encryption scheme */
-+ hi_cipher_rsa_pub_key pub_key; /* RSA private key struct */
-+ hi_cipher_ca_type ca_type; /* CA type*/
-+}hi_cipher_rsa_pub_enc;
++ hi_cipher_rsa_encrypt_scheme scheme; /* RSA encryption scheme */
++ hi_cipher_rsa_pub_key pub_key; /* RSA public key struct */
++ hi_cipher_ca_type ca_type; /* CA type. */
++} hi_cipher_rsa_pub_encrypt;
+
+/* RSA private key decryption struct input */
+typedef struct {
-+ hi_cipher_rsa_enc_scheme scheme; /* RSA encryption scheme */
-+ hi_cipher_rsa_pri_key pri_key; /* RSA private key struct */
-+ hi_cipher_ca_type ca_type; /* CA type*/
-+}hi_cipher_rsa_pri_enc;
++ hi_cipher_rsa_encrypt_scheme scheme; /* RSA encryption scheme */
++ hi_cipher_rsa_private_key private_key; /* RSA private key struct */
++ hi_cipher_ca_type ca_type; /* CA type. */
++} hi_cipher_rsa_private_encrypt;
+
+/* RSA signature struct input */
+typedef struct {
-+ hi_cipher_rsa_sign_scheme scheme; /* RSA signature scheme*/
-+ hi_cipher_rsa_pri_key pri_key; /* RSA private key struct */
-+ hi_cipher_ca_type ca_type; /* CA type*/
-+ }hi_cipher_rsa_sign;
++ hi_cipher_rsa_sign_scheme scheme; /* RSA signature scheme. */
++ hi_cipher_rsa_private_key private_key; /* RSA private key struct */
++ hi_cipher_ca_type ca_type; /* CA type. */
++} hi_cipher_rsa_sign;
+
+/* RSA signature verify struct input */
+typedef struct {
-+ hi_cipher_rsa_sign_scheme scheme; /* RSA signature scheme*/
++ hi_cipher_rsa_sign_scheme scheme; /* RSA signature scheme. */
+ hi_cipher_rsa_pub_key pub_key; /* RSA public key struct */
-+}hi_cipher_rsa_verify;
++} hi_cipher_rsa_verify;
++
++typedef struct {
++ const hi_u8 *in; /* Input data to be cryption. */
++ hi_u32 in_len; /* Length of input data. */
++ hi_u8 *out; /* Output data. */
++ hi_u32 out_buf_len; /* Length of output buffer. */
++ hi_u32 *out_len; /* Length of output valid data. */
++} hi_cipher_rsa_crypt;
++
++typedef struct {
++ const hi_u8 *in; /* Input data to be cryption. */
++ hi_u32 in_len; /* Length of input data. */
++ const hi_u8 *hash_data; /* Hash data. */
++ hi_u32 hash_data_len; /* Length of hash data. */
++ hi_u8 *sign; /* Sign output data. */
++ hi_u32 sign_buf_len; /* Length of sign output buffer. */
++ hi_u32 *sign_len; /* Length of sign output valid data. */
++} hi_cipher_sign_data;
++
++typedef struct {
++ const hi_u8 *in; /* Input data to be cryption. */
++ hi_u32 in_len; /* Length of input data. */
++ const hi_u8 *hash_data; /* Hash data. */
++ hi_u32 hash_data_len; /* Length of hash data. */
++ hi_u8 *sign; /* Input sign data. */
++ hi_u32 sign_len; /* Length of input sign data. */
++} hi_cipher_verify_data;
+
+#ifdef __cplusplus
+#if __cplusplus
@@ -198060,98 +267195,76 @@ index 0000000..bc83176
+#endif /* __HI_CIPHER_COMPAT_H__ */
diff --git a/drivers/crypto/hisi-cipher/include/hi_common_cipher.h b/drivers/crypto/hisi-cipher/include/hi_common_cipher.h
new file mode 100644
-index 0000000..4f56550
+index 0000000..e3337bf
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/include/hi_common_cipher.h
-@@ -0,0 +1,66 @@
-+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
-+ */
-+
-+#ifndef __HI_COMMON_CIPHER__
-+#define __HI_COMMON_CIPHER__
-+
-+#ifdef __cplusplus
-+#if __cplusplus
-+extern "C" {
-+#endif
-+#endif /* __cplusplus */
-+
-+#define HI_ERR_CIPHER_NOT_INIT (HI_S32)(0x804D0001)
-+#define HI_ERR_CIPHER_INVALID_HANDLE (HI_S32)(0x804D0002)
-+#define HI_ERR_CIPHER_INVALID_POINT (HI_S32)(0x804D0003)
-+#define HI_ERR_CIPHER_INVALID_PARA (HI_S32)(0x804D0004)
-+#define HI_ERR_CIPHER_FAILED_INIT (HI_S32)(0x804D0005)
-+#define HI_ERR_CIPHER_FAILED_GETHANDLE (HI_S32)(0x804D0006)
-+#define HI_ERR_CIPHER_FAILED_RELEASEHANDLE (HI_S32)(0x804D0007)
-+#define HI_ERR_CIPHER_FAILED_CONFIGAES (HI_S32)(0x804D0008)
-+#define HI_ERR_CIPHER_FAILED_CONFIGDES (HI_S32)(0x804D0009)
-+#define HI_ERR_CIPHER_FAILED_ENCRYPT (HI_S32)(0x804D000A)
-+#define HI_ERR_CIPHER_FAILED_DECRYPT (HI_S32)(0x804D000B)
-+#define HI_ERR_CIPHER_BUSY (HI_S32)(0x804D000C)
-+#define HI_ERR_CIPHER_NO_AVAILABLE_RNG (HI_S32)(0x804D000D)
-+#define HI_ERR_CIPHER_FAILED_MEM (HI_S32)(0x804D000E)
-+#define HI_ERR_CIPHER_UNAVAILABLE (HI_S32)(0x804D000F)
-+#define HI_ERR_CIPHER_OVERFLOW (HI_S32)(0x804D0010)
-+#define HI_ERR_CIPHER_HARD_STATUS (HI_S32)(0x804D0011)
-+#define HI_ERR_CIPHER_TIMEOUT (HI_S32)(0x804D0012)
-+#define HI_ERR_CIPHER_UNSUPPORTED (HI_S32)(0x804D0013)
-+#define HI_ERR_CIPHER_REGISTER_IRQ (HI_S32)(0x804D0014)
-+#define HI_ERR_CIPHER_ILLEGAL_UUID (HI_S32)(0x804D0015)
-+#define HI_ERR_CIPHER_ILLEGAL_KEY (HI_S32)(0x804D0016)
-+#define HI_ERR_CIPHER_INVALID_ADDR (HI_S32)(0x804D0017)
-+#define HI_ERR_CIPHER_INVALID_LENGTH (HI_S32)(0x804D0018)
-+#define HI_ERR_CIPHER_ILLEGAL_DATA (HI_S32)(0x804D0019)
-+#define HI_ERR_CIPHER_RSA_SIGN (HI_S32)(0x804D001A)
-+#define HI_ERR_CIPHER_RSA_VERIFY (HI_S32)(0x804D001B)
-+#define HI_ERR_CIPHER_MEMSET_S_FAILED (HI_S32)(0x804D001C)
-+#define HI_ERR_CIPHER_MEMCPY_S_FAILED (HI_S32)(0x804D001D)
-+#define HI_ERR_CIPHER_RSA_CRYPT_FAILED (HI_S32)(0x804D001E)
-+
-+#ifdef __cplusplus
-+#if __cplusplus
-+}
-+#endif
-+#endif /* __cplusplus */
-+
-+#endif /* __CRYP_CIPHER_H__ */
-+
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C), Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cipher common.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
++ */
++
++#ifndef __HI_COMMON_CIPHER__
++#define __HI_COMMON_CIPHER__
++
++#ifdef __cplusplus
++#if __cplusplus
++extern "C" {
++#endif
++#endif /* __cplusplus */
++
++#define HI_ERR_CIPHER_NOT_INIT 0x804D0001
++#define HI_ERR_CIPHER_INVALID_HANDLE 0x804D0002
++#define HI_ERR_CIPHER_INVALID_POINT 0x804D0003
++#define HI_ERR_CIPHER_INVALID_PARA 0x804D0004
++#define HI_ERR_CIPHER_FAILED_INIT 0x804D0005
++#define HI_ERR_CIPHER_FAILED_GETHANDLE 0x804D0006
++#define HI_ERR_CIPHER_FAILED_RELEASEHANDLE 0x804D0007
++#define HI_ERR_CIPHER_FAILED_CONFIGAES 0x804D0008
++#define HI_ERR_CIPHER_FAILED_CONFIGDES 0x804D0009
++#define HI_ERR_CIPHER_FAILED_ENCRYPT 0x804D000A
++#define HI_ERR_CIPHER_FAILED_DECRYPT 0x804D000B
++#define HI_ERR_CIPHER_BUSY 0x804D000C
++#define HI_ERR_CIPHER_NO_AVAILABLE_RNG 0x804D000D
++#define HI_ERR_CIPHER_FAILED_MEM 0x804D000E
++#define HI_ERR_CIPHER_UNAVAILABLE 0x804D000F
++#define HI_ERR_CIPHER_OVERFLOW 0x804D0010
++#define HI_ERR_CIPHER_HARD_STATUS 0x804D0011
++#define HI_ERR_CIPHER_TIMEOUT 0x804D0012
++#define HI_ERR_CIPHER_UNSUPPORTED 0x804D0013
++#define HI_ERR_CIPHER_REGISTER_IRQ 0x804D0014
++#define HI_ERR_CIPHER_ILLEGAL_UUID 0x804D0015
++#define HI_ERR_CIPHER_ILLEGAL_KEY 0x804D0016
++#define HI_ERR_CIPHER_INVALID_ADDR 0x804D0017
++#define HI_ERR_CIPHER_INVALID_LENGTH 0x804D0018
++#define HI_ERR_CIPHER_ILLEGAL_DATA 0x804D0019
++#define HI_ERR_CIPHER_RSA_SIGN 0x804D001A
++#define HI_ERR_CIPHER_RSA_VERIFY 0x804D001B
++#define HI_ERR_CIPHER_MEMSET_S_FAILED 0x804D001C
++#define HI_ERR_CIPHER_MEMCPY_S_FAILED 0x804D001D
++#define HI_ERR_CIPHER_RSA_CRYPT_FAILED 0x804D001E
++
++#ifdef __cplusplus
++#if __cplusplus
++}
++#endif
++#endif /* __cplusplus */
++
++#endif /* __CRYP_CIPHER_H__ */
++
diff --git a/drivers/crypto/hisi-cipher/include/hi_types.h b/drivers/crypto/hisi-cipher/include/hi_types.h
new file mode 100644
-index 0000000..66f00fb
+index 0000000..9296c3a
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/include/hi_types.h
-@@ -0,0 +1,146 @@
+@@ -0,0 +1,84 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (C), Hisilicon Technologies Co., Ltd. 2005-2019. All rights reserved.
++ * Description : head file for hisi types adapt to kernel.
++ * Author : Hisilicon multimedia software group
++ * Create : 2005-04-23
+ */
+
+#ifndef __HI_TYPES_H__
@@ -198165,79 +267278,28 @@ index 0000000..66f00fb
+#endif
+#endif /* __cplusplus */
+
-+/*--------------------------------------------------------------------------------------------------------------*
++/* -------------------------------------------------------------------------------------------------------------*
+ * Defintion of basic data types. The data types are applicable to both the application layer and kernel codes. *
-+ *--------------------------------------------------------------------------------------------------------------*/
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup Common_TYPE */
-+/** @{ */ /** <!-- [Common_TYPE] */
++ * -------------------------------------------------------------------------------------------------------------*
++ */
++#define HI_VOID void
+
-+typedef unsigned char HI_U8;
-+typedef unsigned char HI_UCHAR;
-+typedef unsigned short HI_U16;
-+typedef unsigned int HI_U32;
-+typedef unsigned long HI_ULONG;
-+
-+typedef signed char HI_S8;
-+typedef short HI_S16;
-+typedef int HI_S32;
-+typedef long HI_SLONG;
-+
-+#ifndef _M_IX86
-+typedef unsigned long long HI_U64;
-+typedef long long HI_S64;
-+#else
-+typedef __int64 HI_U64;
-+typedef __int64 HI_S64;
-+#endif
-+
-+typedef char HI_CHAR;
-+typedef char* HI_PCHAR;
-+
-+typedef unsigned long HI_UL;
-+typedef signed long HI_SL;
-+
-+typedef float HI_FLOAT;
-+typedef double HI_DOUBLE;
-+
-+typedef void HI_VOID;
-+
-+typedef unsigned long HI_SIZE_T;
-+typedef unsigned long HI_LENGTH_T;
-+
-+typedef HI_U32 HI_HANDLE;
-+typedef uintptr_t HI_UINTPTR_T;
-+
-+/** Constant Definition */
-+typedef enum
-+{
++/* Constant Definition */
++typedef enum {
+ HI_FALSE = 0,
+ HI_TRUE = 1,
+} HI_BOOL;
+
-+#ifndef NULL
-+#define NULL 0L
-+#endif
-+
-+#define HI_NULL 0L
-+#define HI_NULL_PTR 0L
-+
-+#define HI_SUCCESS 0
-+#define HI_FAILURE (-1)
-+#define HI_INVALID_HANDLE (0xffffffff)
-+
+typedef unsigned char hi_uchar;
+typedef unsigned char hi_u8;
+typedef unsigned short hi_u16;
+typedef unsigned int hi_u32;
-+typedef unsigned long long hi_u64;
+typedef unsigned long hi_ulong;
+
+typedef char hi_char;
+typedef signed char hi_s8;
+typedef short hi_s16;
+typedef int hi_s32;
-+typedef long long hi_s64;
+typedef long hi_slong;
+
+typedef float hi_float;
@@ -198250,29 +267312,29 @@ index 0000000..66f00fb
+
+typedef hi_u32 hi_handle;
+
++typedef uintptr_t HI_UINTPTR_T;
+typedef HI_BOOL hi_bool;
+typedef HI_UINTPTR_T hi_uintptr_t;
++typedef unsigned long int hi_phys_addr_t;
+
-+/**
++#ifndef _M_IX86
++typedef unsigned long long hi_u64;
++typedef long long hi_s64;
++#else
++typedef __int64 hi_u64;
++typedef __int64 hi_s64;
++#endif
+
-+define of HI_HANDLE :
-+bit31 bit0
-+ |<---- 16bit --------->|<--- 8bit --->|<--- 8bit --->|
-+ |--------------------------------------------------------------|
-+ | HI_MOD_ID_E | mod defined data | chnID |
-+ |--------------------------------------------------------------|
++#ifndef NULL
++#define NULL 0L
++#endif
+
-+mod defined data: private data define by each module(for example: sub-mod id), usually, set to 0.
-+*/
++#define HI_NULL 0L
++#define HI_NULL_PTR 0L
+
-+#define HI_HANDLE_MAKEHANDLE(mod, privatedata, chnid) (hi_handle)( (((mod)& 0xffff) << 16) | ((((privatedata)& 0xff) << 8) ) | (((chnid) & 0xff)) )
-+
-+#define HI_HANDLE_GET_MODID(handle) (((handle) >> 16) & 0xffff)
-+#define HI_HANDLE_GET_PriDATA(handle) (((handle) >> 8) & 0xff)
-+#define HI_HANDLE_GET_CHNID(handle) (((handle)) & 0xff)
-+
-+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
++#define HI_SUCCESS 0
++#define HI_FAILURE (-1)
++#define HI_INVALID_HANDLE 0xffffffff
+
+#ifdef __cplusplus
+#if __cplusplus
@@ -198280,37 +267342,21 @@ index 0000000..66f00fb
+#endif
+#endif /* __cplusplus */
+
-+#endif /* __HI_TYPE_H__ */
++#endif /* __HI_TYPES_H__ */
+
diff --git a/drivers/crypto/hisi-cipher/include/hi_unf_cipher.h b/drivers/crypto/hisi-cipher/include/hi_unf_cipher.h
new file mode 100644
-index 0000000..ffcdd31
+index 0000000..e5aef86
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/include/hi_unf_cipher.h
-@@ -0,0 +1,857 @@
+@@ -0,0 +1,847 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (C), Hisilicon Technologies Co., Ltd. 2016-2019. All rights reserved.
++ * Description : head file for unf cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2016-06-08
+ */
+
-+/**
-+* \file
-+* \brief Describes the API about the cipher.
-+*/
-+
+#ifndef __HI_UNF_CIPHER_H__
+#define __HI_UNF_CIPHER_H__
+
@@ -198321,229 +267367,225 @@ index 0000000..ffcdd31
+extern "C" {
+#endif
+#endif /* __cplusplus */
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup CIPHER */
-+/** @{ */ /** <!-- [CIPHER] */
++/* ************************** Structure Definition *************************** */
++/* max length of SM2, unit: word */
++#define SM2_LEN_IN_WROD 8
+
-+/** max length of SM2, unit: word */
-+#define SM2_LEN_IN_WROD (8)
-+
-+/** max length of SM2, unit: byte */
++/* max length of SM2, unit: byte */
+#define SM2_LEN_IN_BYTE (SM2_LEN_IN_WROD * 4)
+
-+/** CIPHER set IV for first package */
-+#define CIPHER_IV_CHANGE_ONE_PKG (1)
++/* CIPHER set IV for first package */
++#define CIPHER_IV_CHANGE_ONE_PKG 1
+
-+/** CIPHER set IV for first package */
-+#define CIPHER_IV_CHANGE_ALL_PKG (2)
++/* CIPHER set IV for first package */
++#define CIPHER_IV_CHANGE_ALL_PKG 2
+
-+/** Cipher work mode */
-+typedef enum hiHI_UNF_CIPHER_WORK_MODE_E
-+{
-+ HI_UNF_CIPHER_WORK_MODE_ECB, /**<Electronic codebook (ECB) mode*/
-+ HI_UNF_CIPHER_WORK_MODE_CBC, /**<Cipher block chaining (CBC) mode*/
-+ HI_UNF_CIPHER_WORK_MODE_CFB, /**<Cipher feedback (CFB) mode*/
-+ HI_UNF_CIPHER_WORK_MODE_OFB, /**<Output feedback (OFB) mode*/
-+ HI_UNF_CIPHER_WORK_MODE_CTR, /**<Counter (CTR) mode*/
-+ HI_UNF_CIPHER_WORK_MODE_CCM, /**<Counter (CCM) mode*/
-+ HI_UNF_CIPHER_WORK_MODE_GCM, /**<Counter (GCM) mode*/
-+ HI_UNF_CIPHER_WORK_MODE_CBC_CTS, /**<Cipher block chaining CipherStealing mode*/
++#define DES_IV_SIZE_IN_WORD 2
++#define IV_SIZE_IN_WORD 4
++#define DES_KEY_SIZE_IN_WORD 2
++#define TDES_KEY_SIZE_IN_WORD 6
++#define AES_KEY_SIZE_IN_WORD 8
++#define SM1_KEY_SIZE_IN_WORD 4
++#define SM4_KEY_SIZE_IN_WORD 4
++
++/* Cipher work mode */
++typedef enum hiHI_UNF_CIPHER_WORK_MODE_E {
++ HI_UNF_CIPHER_WORK_MODE_ECB, /* Electronic codebook (ECB) mode */
++ HI_UNF_CIPHER_WORK_MODE_CBC, /* Cipher block chaining (CBC) mode */
++ HI_UNF_CIPHER_WORK_MODE_CFB, /* Cipher feedback (CFB) mode */
++ HI_UNF_CIPHER_WORK_MODE_OFB, /* Output feedback (OFB) mode */
++ HI_UNF_CIPHER_WORK_MODE_CTR, /* Counter (CTR) mode */
++ HI_UNF_CIPHER_WORK_MODE_CCM, /* Counter (CCM) mode */
++ HI_UNF_CIPHER_WORK_MODE_GCM, /* Counter (GCM) mode */
++ HI_UNF_CIPHER_WORK_MODE_CBC_CTS, /* Cipher block chaining CipherStealing mode */
+ HI_UNF_CIPHER_WORK_MODE_BUTT,
+ HI_UNF_CIPHER_WORK_MODE_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_WORK_MODE_E;
++} HI_UNF_CIPHER_WORK_MODE_E;
+
-+/** Cipher algorithm */
-+typedef enum hiHI_UNF_CIPHER_ALG_E
-+{
-+ HI_UNF_CIPHER_ALG_DES = 0x0, /**< Data encryption standard (DES) algorithm */
-+ HI_UNF_CIPHER_ALG_3DES = 0x1, /**< 3DES algorithm */
-+ HI_UNF_CIPHER_ALG_AES = 0x2, /**< Advanced encryption standard (AES) algorithm */
-+ HI_UNF_CIPHER_ALG_SM1 = 0x3, /**<SM1 algorithm*/
-+ HI_UNF_CIPHER_ALG_SM4 = 0x4, /**<SM4 algorithm*/
-+ HI_UNF_CIPHER_ALG_DMA = 0x5, /**<DMA copy*/
++/* Cipher algorithm */
++typedef enum hiHI_UNF_CIPHER_ALG_E {
++ HI_UNF_CIPHER_ALG_DES = 0x0, /* Data encryption standard (DES) algorithm */
++ HI_UNF_CIPHER_ALG_3DES = 0x1, /* 3DES algorithm */
++ HI_UNF_CIPHER_ALG_AES = 0x2, /* Advanced encryption standard (AES) algorithm */
++ HI_UNF_CIPHER_ALG_SM1 = 0x3, /* SM1 algorithm */
++ HI_UNF_CIPHER_ALG_SM4 = 0x4, /* SM4 algorithm */
++ HI_UNF_CIPHER_ALG_DMA = 0x5, /* DMA copy */
+ HI_UNF_CIPHER_ALG_BUTT = 0x6,
+ HI_UNF_CIPHER_ALG_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_ALG_E;
++} HI_UNF_CIPHER_ALG_E;
+
-+/** Key length */
-+typedef enum hiHI_UNF_CIPHER_KEY_LENGTH_E
-+{
-+ HI_UNF_CIPHER_KEY_AES_128BIT = 0x0, /**< 128-bit key for the AES algorithm */
-+ HI_UNF_CIPHER_KEY_AES_192BIT = 0x1, /**< 192-bit key for the AES algorithm */
-+ HI_UNF_CIPHER_KEY_AES_256BIT = 0x2, /**< 256-bit key for the AES algorithm */
-+ HI_UNF_CIPHER_KEY_DES_3KEY = 0x2, /**< Three keys for the DES algorithm */
-+ HI_UNF_CIPHER_KEY_DES_2KEY = 0x3, /**< Two keys for the DES algorithm */
-+ HI_UNF_CIPHER_KEY_DEFAULT = 0x0, /**< default key length, DES-8, SM1-48, SM4-16 */
++/* Key length */
++typedef enum hiHI_UNF_CIPHER_KEY_LENGTH_E {
++ HI_UNF_CIPHER_KEY_AES_128BIT = 0x0, /* 128-bit key for the AES algorithm */
++ HI_UNF_CIPHER_KEY_AES_192BIT = 0x1, /* 192-bit key for the AES algorithm */
++ HI_UNF_CIPHER_KEY_AES_256BIT = 0x2, /* 256-bit key for the AES algorithm */
++ HI_UNF_CIPHER_KEY_DES_3KEY = 0x2, /* Three keys for the DES algorithm */
++ HI_UNF_CIPHER_KEY_DES_2KEY = 0x3, /* Two keys for the DES algorithm */
++ HI_UNF_CIPHER_KEY_DEFAULT = 0x0, /* default key length, DES-8, SM1-48, SM4-16 */
+ HI_UNF_CIPHER_KEY_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_KEY_LENGTH_E;
++} HI_UNF_CIPHER_KEY_LENGTH_E;
+
-+/** Cipher bit width */
-+typedef enum hiHI_UNF_CIPHER_BIT_WIDTH_E
-+{
-+ HI_UNF_CIPHER_BIT_WIDTH_64BIT = 0x0, /**< 64-bit width */
-+ HI_UNF_CIPHER_BIT_WIDTH_8BIT = 0x1, /**< 8-bit width */
-+ HI_UNF_CIPHER_BIT_WIDTH_1BIT = 0x2, /**< 1-bit width */
-+ HI_UNF_CIPHER_BIT_WIDTH_128BIT = 0x3, /**< 128-bit width */
++/* Cipher bit width */
++typedef enum hiHI_UNF_CIPHER_BIT_WIDTH_E {
++ HI_UNF_CIPHER_BIT_WIDTH_64BIT = 0x0, /* 64-bit width */
++ HI_UNF_CIPHER_BIT_WIDTH_8BIT = 0x1, /* 8-bit width */
++ HI_UNF_CIPHER_BIT_WIDTH_1BIT = 0x2, /* 1-bit width */
++ HI_UNF_CIPHER_BIT_WIDTH_128BIT = 0x3, /* 128-bit width */
+ HI_UNF_CIPHER_BIT_WIDTH_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_BIT_WIDTH_E;
++} HI_UNF_CIPHER_BIT_WIDTH_E;
+
-+/** Cipher control parameters */
-+typedef struct hiTEE_CIPHER_CTRL_CHANGE_FLAG_S
-+{
-+ HI_U32 bit1IV:2; /**< Initial Vector change flag, 0-don't set, 1-set IV for first package, 2-set IV for each package */
-+ HI_U32 bitsResv:30; /**< Reserved */
-+}HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S;
++/* Cipher control parameters */
++typedef struct hiTEE_CIPHER_CTRL_CHANGE_FLAG_S {
++ HI_U32 bit1IV:2; /* Initial Vector change flag, 0-don't set, 1-set IV for first package, 2-set IV
++ for each package. */
++ HI_U32 bitsResv:30; /* Reserved */
++} HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S;
+
-+/** Key ladder selecting parameters */
-+typedef enum hiTEE_CIPHER_CA_TYPE_E
-+{
-+ HI_UNF_CIPHER_KEY_SRC_USER = 0x0, /**< User Key*/
-+ HI_UNF_CIPHER_KEY_SRC_KLAD_1, /**< KLAD Key 1*/
-+ HI_UNF_CIPHER_KEY_SRC_KLAD_2, /**< KLAD Key 2*/
-+ HI_UNF_CIPHER_KEY_SRC_KLAD_3, /**< KLAD Key 3*/
++/* Key ladder selecting parameters */
++typedef enum hiTEE_CIPHER_CA_TYPE_E {
++ HI_UNF_CIPHER_KEY_SRC_USER = 0x0, /* User Key */
++ HI_UNF_CIPHER_KEY_SRC_KLAD_1, /* KLAD Key 1 */
++ HI_UNF_CIPHER_KEY_SRC_KLAD_2, /* KLAD Key 2 */
++ HI_UNF_CIPHER_KEY_SRC_KLAD_3, /* KLAD Key 3 */
+ HI_UNF_CIPHER_KEY_SRC_BUTT,
+ HI_UNF_CIPHER_KEY_SRC_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_CA_TYPE_E;
++} HI_UNF_CIPHER_CA_TYPE_E;
+
-+/** Encryption/Decryption type selecting */
-+typedef enum
-+{
-+ HI_UNF_CIPHER_KLAD_TARGET_AES = 0x0, /**< Klad for AES*/
-+ HI_UNF_CIPHER_KLAD_TARGET_RSA, /**< Klad for RSA*/
++/* Encryption/Decryption type selecting */
++typedef enum {
++ HI_UNF_CIPHER_KLAD_TARGET_AES = 0x0, /* Klad for AES */
++ HI_UNF_CIPHER_KLAD_TARGET_RSA, /* Klad for RSA */
+ HI_UNF_CIPHER_KLAD_TARGET_BUTT,
-+}HI_UNF_CIPHER_KLAD_TARGET_E;
++} HI_UNF_CIPHER_KLAD_TARGET_E;
+
-+/** Encryption/Decryption type selecting */
-+typedef enum
-+{
++/* Encryption/Decryption type selecting */
++typedef enum {
+ HI_UNF_CIPHER_TYPE_NORMAL = 0x0,
+ HI_UNF_CIPHER_TYPE_COPY_AVOID,
+ HI_UNF_CIPHER_TYPE_BUTT,
+ HI_UNF_CIPHER_TYPE_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_TYPE_E;
++} HI_UNF_CIPHER_TYPE_E;
+
-+/** Structure of the cipher type */
-+typedef struct
-+{
++/* Structure of the cipher type */
++typedef struct {
+ HI_UNF_CIPHER_TYPE_E enCipherType;
-+}HI_UNF_CIPHER_ATTS_S;
++} HI_UNF_CIPHER_ATTS_S;
+
-+/** sm1 round config */
-+typedef enum hiHI_UNF_CIPHER_SM1_ROUND_E
-+{
-+ HI_UNF_CIPHER_SM1_ROUND_08 = 0x00, /**< sm1 round 08 */
-+ HI_UNF_CIPHER_SM1_ROUND_10 = 0x01, /**< sm1 round 10 */
-+ HI_UNF_CIPHER_SM1_ROUND_12 = 0x02, /**< sm1 round 12 */
-+ HI_UNF_CIPHER_SM1_ROUND_14 = 0x03, /**< sm1 round 14 */
++/* sm1 round config */
++typedef enum hiHI_UNF_CIPHER_SM1_ROUND_E {
++ HI_UNF_CIPHER_SM1_ROUND_08 = 0x00, /* sm1 round 08 */
++ HI_UNF_CIPHER_SM1_ROUND_10 = 0x01, /* sm1 round 10 */
++ HI_UNF_CIPHER_SM1_ROUND_12 = 0x02, /* sm1 round 12 */
++ HI_UNF_CIPHER_SM1_ROUND_14 = 0x03, /* sm1 round 14 */
+ HI_UNF_CIPHER_SM1_ROUND_BUTT,
+ HI_UNF_CIPHER_SM1_ROUND_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_SM1_ROUND_E;
++} HI_UNF_CIPHER_SM1_ROUND_E;
+
-+/** Structure of the cipher control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_S
-+{
-+ HI_U32 u32Key[8]; /**< Key input */
-+ HI_U32 u32IV[4]; /**< Initialization vector (IV) */
-+ HI_BOOL bKeyByCA; /**< Encryption using advanced conditional access (CA) or decryption using keys */
-+ HI_UNF_CIPHER_CA_TYPE_E enCaType; /**< Select keyladder type when using advanced CA */
-+ HI_UNF_CIPHER_ALG_E enAlg; /**< Cipher algorithm */
-+ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /**< Bit width for encryption or decryption */
-+ HI_UNF_CIPHER_WORK_MODE_E enWorkMode; /**< Operating mode */
-+ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /**< Key length */
-+ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /**< control information exchange choices, we default all would be change except they have been in the choices */
++/* Structure of the cipher control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_S {
++ HI_U32 u32Key[AES_KEY_SIZE_IN_WORD]; /* Key input */
++ HI_U32 u32IV[IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ HI_BOOL bKeyByCA; /* Encryption using advanced conditional access (CA) or decryption
++ using keys */
++ HI_UNF_CIPHER_CA_TYPE_E enCaType; /* Select keyladder type when using advanced CA */
++ HI_UNF_CIPHER_ALG_E enAlg; /* Cipher algorithm */
++ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /* Bit width for encryption or decryption */
++ HI_UNF_CIPHER_WORK_MODE_E enWorkMode; /* Operating mode */
++ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /* Key length */
++ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /* control information exchange choices, we default all would be
++ change except they have been in the choices */
+} HI_UNF_CIPHER_CTRL_S;
+
-+/** Structure of the cipher AES control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_AES_S
-+{
-+ HI_U32 u32EvenKey[8]; /**< Key input, default use this key*/
-+ HI_U32 u32OddKey[8]; /**< Key input, only valid for Multi encrypt/decrypt*/
-+ HI_U32 u32IV[4]; /**< Initialization vector (IV) */
-+ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /**< Bit width for encryption or decryption */
-+ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /**< Key length */
-+ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /**< control information exchange choices, we default all woulde be change except they have been in the choices */
++/* Structure of the cipher AES control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_AES_S {
++ HI_U32 u32EvenKey[AES_KEY_SIZE_IN_WORD]; /* Key input, default use this key. */
++ HI_U32 u32OddKey[AES_KEY_SIZE_IN_WORD]; /* Key input, only valid for Multi encrypt/decrypt. */
++ HI_U32 u32IV[IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /* Bit width for encryption or decryption */
++ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /* Key length */
++ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /* control information exchange choices, we default all woulde be
++ change except they have been in the choices */
+} HI_UNF_CIPHER_CTRL_AES_S;
+
-+/** Structure of the cipher AES CCM/GCM control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_AES_CCM_GCM_S
-+{
-+ HI_U32 u32Key[8]; /**< Key input */
-+ HI_U32 u32IV[4]; /**< Initialization vector (IV) */
-+ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /**< Key length */
-+ HI_U32 u32IVLen; /**< IV lenght for CCM/GCM, which is an element of {4,6,8,10,12,14,16} for CCM, and is an element of [1-16] for GCM*/
-+ HI_U32 u32TagLen; /**< Tag lenght for CCM which is an element of {4,6,8,10,12,14,16}*/
-+ HI_U32 u32ALen; /**< Associated data for CCM and GCM*/
-+ HI_SIZE_T szAPhyAddr; /**< Physical address of Associated data for CCM and GCM*/
++/* Structure of the cipher AES CCM/GCM control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_AES_CCM_GCM_S {
++ HI_U32 u32Key[AES_KEY_SIZE_IN_WORD]; /* Key input */
++ HI_U32 u32IV[IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /* Key length */
++ HI_U32 u32IVLen; /* IV lenght for CCM/GCM, which is an element of {4, 6, 8, 10, 12,
++ 14, 16}for CCM, and is an element of [1-16] for GCM. */
++ HI_U32 u32TagLen; /* Tag lenght for CCM which is an element of {4, 6, 8, 10, 12, 14,
++ 16}. */
++ HI_U32 u32ALen; /* Associated data for CCM and GCM. */
++ HI_SIZE_T szAPhyAddr; /* Physical address of Associated data for CCM and GCM. */
+} HI_UNF_CIPHER_CTRL_AES_CCM_GCM_S;
+
-+/** Structure of the cipher DES control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_DES_S
-+{
-+ HI_U32 u32Key[2]; /**< Key input */
-+ HI_U32 u32IV[2]; /**< Initialization vector (IV) */
-+ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /**< Bit width for encryption or decryption */
-+ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /**< control information exchange choices, we default all woulde be change except they have been in the choices */
++/* Structure of the cipher DES control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_DES_S {
++ HI_U32 u32Key[DES_KEY_SIZE_IN_WORD]; /* Key input */
++ HI_U32 u32IV[DES_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /* Bit width for encryption or decryption */
++ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /* control information exchange choices, we default all woulde be
++ change except they have been in the choices */
+} HI_UNF_CIPHER_CTRL_DES_S;
+
-+/** Structure of the cipher 3DES control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_3DES_S
-+{
-+ HI_U32 u32Key[6]; /**< Key input */
-+ HI_U32 u32IV[2]; /**< Initialization vector (IV) */
-+ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /**< Bit width for encryption or decryption */
-+ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /**< Key length */
-+ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /**< control information exchange choices, we default all woulde be change except they have been in the choices */
++/* Structure of the cipher 3DES control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_3DES_S {
++ HI_U32 u32Key[TDES_KEY_SIZE_IN_WORD]; /* Key input */
++ HI_U32 u32IV[DES_IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /* Bit width for encryption or decryption */
++ HI_UNF_CIPHER_KEY_LENGTH_E enKeyLen; /* Key length */
++ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /* control information exchange choices, we default all woulde be
++ change except they have been in the choices */
+} HI_UNF_CIPHER_CTRL_3DES_S;
+
-+/** Structure of the cipher SM1 control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_SM1_S
-+{
-+ HI_U32 u32EK[4]; /**< Key of EK input */
-+ HI_U32 u32AK[4]; /**< Key of AK input */
-+ HI_U32 u32SK[4]; /**< Key of SK input */
-+ HI_U32 u32IV[4]; /**< Initialization vector (IV) */
-+ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /**< Bit width for encryption or decryption */
-+ HI_UNF_CIPHER_SM1_ROUND_E enSm1Round; /**< SM1 round number, should be 8, 10, 12 or 14*/
-+ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /**< control information exchange choices, we default all woulde be change except they have been in the choices */
++/* Structure of the cipher SM1 control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_SM1_S {
++ HI_U32 u32EK[SM1_KEY_SIZE_IN_WORD]; /* Key of EK input */
++ HI_U32 u32AK[SM1_KEY_SIZE_IN_WORD]; /* Key of AK input */
++ HI_U32 u32SK[SM1_KEY_SIZE_IN_WORD]; /* Key of SK input */
++ HI_U32 u32IV[IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ HI_UNF_CIPHER_BIT_WIDTH_E enBitWidth; /* Bit width for encryption or decryption */
++ HI_UNF_CIPHER_SM1_ROUND_E enSm1Round; /* SM1 round number, should be 8, 10, 12 or 14. */
++ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /* control information exchange choices, we default all woulde be
++ change except they have been in the choices */
+} HI_UNF_CIPHER_CTRL_SM1_S;
+
-+/** Structure of the cipher SM4 control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_SM4_S
-+{
-+ HI_U32 u32Key[4]; /**< Key input */
-+ HI_U32 u32IV[4]; /**< Initialization vector (IV) */
-+ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /**< control information exchange choices, we default all woulde be change except they have been in the choices */
++/* Structure of the cipher SM4 control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_SM4_S {
++ HI_U32 u32Key[SM4_KEY_SIZE_IN_WORD]; /* Key input */
++ HI_U32 u32IV[IV_SIZE_IN_WORD]; /* Initialization vector (IV) */
++ HI_UNF_CIPHER_CTRL_CHANGE_FLAG_S stChangeFlags; /* control information exchange choices, we default all woulde be
++ change except they have been in the choices */
+} HI_UNF_CIPHER_CTRL_SM4_S;
+
-+/** Expand Structure of the cipher control information */
-+typedef struct hiHI_UNF_CIPHER_CTRL_EX_S
-+{
-+ HI_UNF_CIPHER_ALG_E enAlg; /**< Cipher algorithm */
-+ HI_UNF_CIPHER_WORK_MODE_E enWorkMode; /**< Operating mode */
-+ HI_BOOL bKeyByCA; /**< Encryption using advanced conditional access (CA) or decryption using keys */
-+ /**< Parameter for special algorithm
-+ for AES, the pointer should point to HI_UNF_CIPHER_CTRL_AES_S;
-+ for AES_CCM or AES_GCM, the pointer should point to HI_UNF_CIPHER_CTRL_AES_CCM_GCM_S;
-+ for DES, the pointer should point to HI_UNF_CIPHER_CTRL_DES_S;
-+ for 3DES, the pointer should point to HI_UNF_CIPHER_CTRL_3DES_S;
-+ for SM1, the pointer should point to HI_UNF_CIPHER_CTRL_SM1_S;
-+ for SM4, the pointer should point to HI_UNF_CIPHER_CTRL_SM4_S;
-+ */
++/* Expand Structure of the cipher control information */
++typedef struct hiHI_UNF_CIPHER_CTRL_EX_S {
++ HI_UNF_CIPHER_ALG_E enAlg; /* Cipher algorithm */
++ HI_UNF_CIPHER_WORK_MODE_E enWorkMode; /* Operating mode */
++ HI_BOOL bKeyByCA; /* Encryption using advanced conditional access (CA) or decryption
++ using keys */
++ /* Parameter for special algorithm
++ * for AES, the pointer should point to HI_UNF_CIPHER_CTRL_AES_S;
++ * for AES_CCM or AES_GCM, the pointer should point to HI_UNF_CIPHER_CTRL_AES_CCM_GCM_S;
++ * for DES, the pointer should point to HI_UNF_CIPHER_CTRL_DES_S;
++ * for 3DES, the pointer should point to HI_UNF_CIPHER_CTRL_3DES_S;
++ * for SM1, the pointer should point to HI_UNF_CIPHER_CTRL_SM1_S;
++ * for SM4, the pointer should point to HI_UNF_CIPHER_CTRL_SM4_S;
++ */
+ HI_VOID *pParam;
+} HI_UNF_CIPHER_CTRL_EX_S;
+
-+/** Cipher data */
-+typedef struct hiHI_UNF_CIPHER_DATA_S
-+{
-+ HI_SIZE_T szSrcPhyAddr; /**< phy address of the original data */
-+ HI_SIZE_T szDestPhyAddr; /**< phy address of the purpose data */
-+ HI_U32 u32ByteLength; /**< cigher data length*/
-+ HI_BOOL bOddKey; /**< Use odd key or even key*/
++/* Cipher data */
++typedef struct hiHI_UNF_CIPHER_DATA_S {
++ HI_SIZE_T szSrcPhyAddr; /* phy address of the original data */
++ HI_SIZE_T szDestPhyAddr; /* phy address of the purpose data */
++ HI_U32 u32ByteLength; /* cigher data length. */
++ HI_BOOL bOddKey; /* Use odd key or even key. */
+} HI_UNF_CIPHER_DATA_S;
+
-+/** Hash algrithm type */
-+typedef enum hiHI_UNF_CIPHER_HASH_TYPE_E
-+{
++/* Hash algrithm type */
++typedef enum hiHI_UNF_CIPHER_HASH_TYPE_E {
+ HI_UNF_CIPHER_HASH_TYPE_SHA1,
+ HI_UNF_CIPHER_HASH_TYPE_SHA224,
+ HI_UNF_CIPHER_HASH_TYPE_SHA256,
@@ -198557,585 +267599,595 @@ index 0000000..ffcdd31
+ HI_UNF_CIPHER_HASH_TYPE_SM3,
+ HI_UNF_CIPHER_HASH_TYPE_BUTT,
+ HI_UNF_CIPHER_HASH_TYPE_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_HASH_TYPE_E;
++} HI_UNF_CIPHER_HASH_TYPE_E;
+
-+/** Hash init struct input */
-+typedef struct
-+{
++/* Hash init struct input */
++typedef struct {
+ HI_U8 *pu8HMACKey;
+ HI_U32 u32HMACKeyLen;
+ HI_UNF_CIPHER_HASH_TYPE_E eShaType;
-+}HI_UNF_CIPHER_HASH_ATTS_S;
++} HI_UNF_CIPHER_HASH_ATTS_S;
+
-+typedef enum hiHI_UNF_CIPHER_RSA_ENC_SCHEME_E
-+{
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_NO_PADDING, /**< without padding */
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0, /**< PKCS#1 block type 0 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_1, /**< PKCS#1 block type 1 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_2, /**< PKCS#1 block type 2 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA1, /**< PKCS#1 RSAES-OAEP-SHA1 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA224, /**< PKCS#1 RSAES-OAEP-SHA224 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA256, /**< PKCS#1 RSAES-OAEP-SHA256 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA384, /**< PKCS#1 RSAES-OAEP-SHA384 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA512, /**< PKCS#1 RSAES-OAEP-SHA512 padding*/
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_PKCS1_V1_5, /**< PKCS#1 RSAES-PKCS1_V1_5 padding*/
++typedef enum hiHI_UNF_CIPHER_RSA_ENC_SCHEME_E {
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_NO_PADDING, /* without padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0, /* PKCS#1 block type 0 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_1, /* PKCS#1 block type 1 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_2, /* PKCS#1 block type 2 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA1, /* PKCS#1 RSAES-OAEP-SHA1 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA224, /* PKCS#1 RSAES-OAEP-SHA224 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA256, /* PKCS#1 RSAES-OAEP-SHA256 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA384, /* PKCS#1 RSAES-OAEP-SHA384 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA512, /* PKCS#1 RSAES-OAEP-SHA512 padding */
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_RSAES_PKCS1_V1_5, /* PKCS#1 RSAES-PKCS1_V1_5 padding */
+ HI_UNF_CIPHER_RSA_ENC_SCHEME_BUTT,
+ HI_UNF_CIPHER_RSA_ENC_SCHEME_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_RSA_ENC_SCHEME_E;
++} HI_UNF_CIPHER_RSA_ENC_SCHEME_E;
+
-+typedef enum hiHI_UNF_CIPHER_RSA_SIGN_SCHEME_E
-+{
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA1 = 0x100, /**< PKCS#1 RSASSA_PKCS1_V15_SHA1 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA224, /**< PKCS#1 RSASSA_PKCS1_V15_SHA224 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA256, /**< PKCS#1 RSASSA_PKCS1_V15_SHA256 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA384, /**< PKCS#1 RSASSA_PKCS1_V15_SHA384 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA512, /**< PKCS#1 RSASSA_PKCS1_V15_SHA512 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA1, /**< PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA224, /**< PKCS#1 RSASSA_PKCS1_PSS_SHA224 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA256, /**< PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA384, /**< PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature*/
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA512, /**< PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature*/
++typedef enum hiHI_UNF_CIPHER_RSA_SIGN_SCHEME_E {
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA1 = 0x100, /* PKCS#1 RSASSA_PKCS1_V15_SHA1 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA224, /* PKCS#1 RSASSA_PKCS1_V15_SHA224 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA256, /* PKCS#1 RSASSA_PKCS1_V15_SHA256 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA384, /* PKCS#1 RSASSA_PKCS1_V15_SHA384 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA512, /* PKCS#1 RSASSA_PKCS1_V15_SHA512 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA1, /* PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA224, /* PKCS#1 RSASSA_PKCS1_PSS_SHA224 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA256, /* PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA384, /* PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature */
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA512, /* PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature */
+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_BUTT,
+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_INVALID = 0xffffffff,
-+}HI_UNF_CIPHER_RSA_SIGN_SCHEME_E;
++} HI_UNF_CIPHER_RSA_SIGN_SCHEME_E;
+
-+typedef struct
-+{
-+ HI_U8 *pu8N; /**< point to public modulus */
-+ HI_U8 *pu8E; /**< point to public exponent */
-+ HI_U16 u16NLen; /**< length of public modulus, max value is 512Byte*/
-+ HI_U16 u16ELen; /**< length of public exponent, max value is 512Byte*/
-+}HI_UNF_CIPHER_RSA_PUB_KEY_S;
++typedef struct {
++ HI_U8 *pu8N; /* point to public modulus */
++ HI_U8 *pu8E; /* point to public exponent */
++ HI_U16 u16NLen; /* length of public modulus, max value is 512Byte. */
++ HI_U16 u16ELen; /* length of public exponent, max value is 512Byte. */
++} HI_UNF_CIPHER_RSA_PUB_KEY_S;
+
-+/** RSA private key struct */
-+typedef struct
-+{
-+ HI_U8 *pu8N; /*!< public modulus */
-+ HI_U8 *pu8E; /*!< public exponent */
-+ HI_U8 *pu8D; /*!< private exponent */
-+ HI_U8 *pu8P; /*!< 1st prime factor */
-+ HI_U8 *pu8Q; /*!< 2nd prime factor */
-+ HI_U8 *pu8DP; /*!< D % (P - 1) */
-+ HI_U8 *pu8DQ; /*!< D % (Q - 1) */
-+ HI_U8 *pu8QP; /*!< 1 / (Q % P) */
-+ HI_U16 u16NLen; /**< length of public modulus */
-+ HI_U16 u16ELen; /**< length of public exponent */
-+ HI_U16 u16DLen; /**< length of private exponent */
-+ HI_U16 u16PLen; /**< length of 1st prime factor */
-+ HI_U16 u16QLen; /**< length of 2nd prime factor */
-+ HI_U16 u16DPLen; /**< length of D % (P - 1) */
-+ HI_U16 u16DQLen; /**< length of D % (Q - 1) */
-+ HI_U16 u16QPLen; /**< length of 1 / (Q % P) */
-+}HI_UNF_CIPHER_RSA_PRI_KEY_S;
++/* RSA private key struct */
++typedef struct {
++ HI_U8 *pu8N; /* public modulus */
++ HI_U8 *pu8E; /* public exponent */
++ HI_U8 *pu8D; /* private exponent */
++ HI_U8 *pu8P; /* 1st prime factor */
++ HI_U8 *pu8Q; /* 2nd prime factor */
++ HI_U8 *pu8DP; /* D % (P - 1) */
++ HI_U8 *pu8DQ; /* D % (Q - 1) */
++ HI_U8 *pu8QP; /* 1 / (Q % P) */
++ HI_U16 u16NLen; /* length of public modulus */
++ HI_U16 u16ELen; /* length of public exponent */
++ HI_U16 u16DLen; /* length of private exponent */
++ HI_U16 u16PLen; /* length of 1st prime factor */
++ HI_U16 u16QLen; /* length of 2nd prime factor */
++ HI_U16 u16DPLen; /* length of D % (P - 1) */
++ HI_U16 u16DQLen; /* length of D % (Q - 1) */
++ HI_U16 u16QPLen; /* length of 1 / (Q % P) */
++} HI_UNF_CIPHER_RSA_PRI_KEY_S;
+
-+/** RSA public key encryption struct input */
-+typedef struct
-+{
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_E enScheme; /** RSA encryption scheme*/
-+ HI_UNF_CIPHER_RSA_PUB_KEY_S stPubKey; /** RSA private key struct */
++/* RSA public key encryption struct input */
++typedef struct {
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_E enScheme; /* RSA encryption scheme */
++ HI_UNF_CIPHER_RSA_PUB_KEY_S stPubKey; /* RSA private key struct */
+ HI_UNF_CIPHER_CA_TYPE_E enCaType;
-+}HI_UNF_CIPHER_RSA_PUB_ENC_S;
++} HI_UNF_CIPHER_RSA_PUB_ENC_S;
+
-+/** RSA private key decryption struct input */
-+typedef struct
-+{
-+ HI_UNF_CIPHER_RSA_ENC_SCHEME_E enScheme; /** RSA encryption scheme */
-+ HI_UNF_CIPHER_RSA_PRI_KEY_S stPriKey; /** RSA public key struct */
++/* RSA private key decryption struct input */
++typedef struct {
++ HI_UNF_CIPHER_RSA_ENC_SCHEME_E enScheme; /* RSA encryption scheme */
++ HI_UNF_CIPHER_RSA_PRI_KEY_S stPriKey; /* RSA public key struct */
+ HI_UNF_CIPHER_CA_TYPE_E enCaType;
-+}HI_UNF_CIPHER_RSA_PRI_ENC_S;
++} HI_UNF_CIPHER_RSA_PRI_ENC_S;
+
-+/** RSA signature struct input */
-+typedef struct
-+{
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_E enScheme; /** RSA signature scheme*/
-+ HI_UNF_CIPHER_RSA_PRI_KEY_S stPriKey; /** RSA private key struct */
++/* RSA signature struct input */
++typedef struct {
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_E enScheme; /* RSA signature scheme */
++ HI_UNF_CIPHER_RSA_PRI_KEY_S stPriKey; /* RSA private key struct */
+ HI_UNF_CIPHER_CA_TYPE_E enCaType;
-+ }HI_UNF_CIPHER_RSA_SIGN_S;
-+
-+/** RSA signature verify struct input */
-+typedef struct
-+{
-+ HI_UNF_CIPHER_RSA_SIGN_SCHEME_E enScheme; /** RSA signature scheme*/
-+ HI_UNF_CIPHER_RSA_PUB_KEY_S stPubKey; /** RSA public key struct */
-+ }HI_UNF_CIPHER_RSA_VERIFY_S;
-+
-+/** @} */ /** <!-- ==== Structure Definition End ==== */
++} HI_UNF_CIPHER_RSA_SIGN_S;
+
++/* RSA signature verify struct input */
++typedef struct {
++ HI_UNF_CIPHER_RSA_SIGN_SCHEME_E enScheme; /* RSA signature scheme */
++ HI_UNF_CIPHER_RSA_PUB_KEY_S stPubKey; /* RSA public key struct */
++} HI_UNF_CIPHER_RSA_VERIFY_S;
+
+#define HI_UNF_CIPHER_Open(HI_VOID) HI_UNF_CIPHER_Init(HI_VOID);
+#define HI_UNF_CIPHER_Close(HI_VOID) HI_UNF_CIPHER_DeInit(HI_VOID);
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup CIPHER */
-+/** @{ */ /** <!-- [CIPHER] */
-+/* ---CIPHER---*/
-+/**
-+\attention \n
-+This API is used to start the cipher device.
-+\param N/A
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_FAILED_INIT The cipher device fails to be initialized.
-+\see \n
-+N/A
-+*/
++/* ****************************** API Declaration **************************** */
++/*
++ * brief Init the cipher device.
++ *
++ * attention \n
++ * This API is used to start the cipher device.
++ *
++ * param N/A
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_FAILED_INIT The cipher device fails to be initialized.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_Init(HI_VOID);
+
-+/**
-+\brief Deinit the cipher device.
-+\attention \n
-+This API is used to stop the cipher device. If this API is called repeatedly, HI_SUCCESS is returned, but only the first operation takes effect.
-+
-+\param N/A
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Deinit the cipher device.
++ *
++ * attention \n
++ * This API is used to stop the cipher device. If this API is called repeatedly, HI_SUCCESS is returned, but only the
++ * first operation takes effect.
++ *
++ * param N/A
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_DeInit(HI_VOID);
+
-+/**
-+\brief Obtain a cipher handle for encryption and decryption.
++/*
++ * brief Obtain a cipher handle for encryption and decryption.
++ *
++ * param[out] phCipher Cipher handle
++ * param[in] cipher attributes
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
++ * retval ::HI_ERR_CIPHER_FAILED_GETHANDLE The cipher handle fails to be obtained, because there are no available
++ * cipher.
++ * handles.
++ * see \n
++ * N/A
++ */
++HI_S32 HI_UNF_CIPHER_CreateHandle(HI_HANDLE *phCipher, const HI_UNF_CIPHER_ATTS_S *pstCipherAttr);
+
-+\param[out] phCipher Cipher handle
-+\param[in] cipher attributes
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
-+\retval ::HI_ERR_CIPHER_FAILED_GETHANDLE The cipher handle fails to be obtained, because there are no available cipher handles.
-+\see \n
-+N/A
-+*/
-+HI_S32 HI_UNF_CIPHER_CreateHandle(HI_HANDLE* phCipher, const HI_UNF_CIPHER_ATTS_S *pstCipherAttr);
-+
-+/**
-+\attention \n
-+This API is used to destroy existing cipher handles.
-+
-+\param[in] hCipher Cipher handle
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Destroy the cipher handle.
++ * attention \n
++ * This API is used to destroy existing cipher handles.
++ * param[in] hCipher Cipher handle
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_DestroyHandle(HI_HANDLE hCipher);
+
-+/**
-+\brief Configures the cipher control information.
-+\attention \n
-+Before encryption or decryption, you must call this API to configure the cipher control information.
-+The first 64-bit data and the last 64-bit data should not be the same when using TDES algorithm.
++/*
++ * brief Configures the cipher control information.
++ *
++ * attention \n
++ * Before encryption or decryption, you must call this API to configure the cipher control information.
++ * The first 64-bit data and the last 64-bit data should not be the same when using TDES algorithm.
++ *
++ * param[in] hCipher Cipher handle.
++ * param[in] pstCtrl Cipher control information.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
++HI_S32 HI_UNF_CIPHER_ConfigHandle(HI_HANDLE hCipher, const HI_UNF_CIPHER_CTRL_S *pstCtrl);
+
-+\param[in] hCipher Cipher handle.
-+\param[in] pstCtrl Cipher control information.
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
-+HI_S32 HI_UNF_CIPHER_ConfigHandle(HI_HANDLE hCipher, const HI_UNF_CIPHER_CTRL_S* pstCtrl);
++/*
++ * brief Configures the cipher control information.
++ *
++ * attention \n
++ * Before encryption or decryption, you must call this API to configure the cipher control information.
++ * The first 64-bit data and the last 64-bit data should not be the same when using TDES algorithm.
++ *
++ * param[in] hCipher Cipher handle.
++ * param[in] pstExCtrl Cipher control information.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
++HI_S32 HI_UNF_CIPHER_ConfigHandleEx(HI_HANDLE hCipher, const HI_UNF_CIPHER_CTRL_EX_S *pstExCtrl);
+
-+/**
-+\brief Configures the cipher control information.
-+\attention \n
-+Before encryption or decryption, you must call this API to configure the cipher control information.
-+The first 64-bit data and the last 64-bit data should not be the same when using TDES algorithm.
-+
-+\param[in] hCipher Cipher handle.
-+\param[in] pstExCtrl Cipher control information.
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
-+HI_S32 HI_UNF_CIPHER_ConfigHandleEx(HI_HANDLE hCipher, const HI_UNF_CIPHER_CTRL_EX_S* pstExCtrl);
-+
-+/**
-+\brief Performs encryption.
-+
-+\attention \n
-+This API is used to perform encryption by using the cipher module.
-+The length of the encrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector, you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
-+\param[in] hCipher Cipher handle
-+\param[in] u32SrcPhyAddr Physical address of the source data
-+\param[in] u32DestPhyAddr Physical address of the target data
-+\param[in] u32ByteLength Length of the encrypted data
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Performs encryption.
++ *
++ * attention \n
++ * This API is used to perform encryption by using the cipher module.
++ * The length of the encrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can
++ * not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector,
++ * you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
++ *
++ * param[in] hCipher Cipher handle
++ * param[in] u32SrcPhyAddr Physical address of the source data
++ * param[in] u32DestPhyAddr Physical address of the target data
++ * param[in] u32ByteLength Length of the encrypted data
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_Encrypt(HI_HANDLE hCipher, HI_SIZE_T szSrcPhyAddr, HI_SIZE_T szDestPhyAddr, HI_U32 u32ByteLength);
+
-+/**
-+\brief Performs decryption.
-+
-+\attention \n
-+This API is used to perform decryption by using the cipher module.
-+The length of the decrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector, you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
-+\param[in] hCipher Cipher handle.
-+\param[in] u32SrcPhyAddr Physical address of the source data.
-+\param[in] u32DestPhyAddr Physical address of the target data.
-+\param[in] u32ByteLength Length of the decrypted data
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Performs decryption.
++ *
++ * attention \n
++ * This API is used to perform decryption by using the cipher module.
++ * The length of the decrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can
++ * not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector,
++ * you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
++ *
++ * param[in] hCipher Cipher handle.
++ * param[in] u32SrcPhyAddr Physical address of the source data.
++ * param[in] u32DestPhyAddr Physical address of the target data.
++ * param[in] u32ByteLength Length of the decrypted data
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_Decrypt(HI_HANDLE hCipher, HI_SIZE_T szSrcPhyAddr, HI_SIZE_T szDestPhyAddr, HI_U32 u32ByteLength);
+
-+/**
-+\brief Performs encryption.
-+
-+\attention \n
-+This API is used to perform encryption by using the cipher module.
-+The length of the encrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector, you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
-+\param[in] hCipher Cipher handle
-+\param[in] pu8SrcData: buffer of the source data.
-+\param[out] pu8DestData: buffer of the target data
-+\param[in] u32ByteLength Length of the encrypted data
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Performs encryption.
++ *
++ * attention \n
++ * This API is used to perform encryption by using the cipher module.
++ * The length of the encrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can
++ * not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector,
++ * you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
++ *
++ * param[in] hCipher Cipher handle
++ * param[in] pu8SrcData: buffer of the source data.
++ * param[out] pu8DestData: buffer of the target data
++ * param[in] u32ByteLength Length of the encrypted data
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_EncryptVir(HI_HANDLE hCipher, const HI_U8 *pu8SrcData, HI_U8 *pu8DestData, HI_U32 u32ByteLength);
+
-+/**
-+\brief Performs decryption.
-+
-+\attention \n
-+This API is used to perform decryption by using the cipher module.
-+The length of the decrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector, you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
-+\param[in] hCipher Cipher handle.
-+\param[in] pu8SrcData: buffer of the source data.
-+\param[out] pu8DestData: buffer of the target data
-+\param[in] u32ByteLength Length of the decrypted data
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Performs decryption.
++ *
++ * attention \n
++ * This API is used to perform decryption by using the cipher module.
++ * The length of the decrypted data should be a multiple of 8 in TDES mode and 16 in AES mode. Besides, the length can
++ * not be bigger than 0xFFFFF.After this operation, the result will affect next operation.If you want to remove vector,
++ * you need to config IV(config pstCtrl->stChangeFlags.bit1IV with 1) by transfering HI_UNF_CIPHER_ConfigHandle.
++ *
++ * param[in] hCipher Cipher handle.
++ * param[in] pu8SrcData: buffer of the source data.
++ * param[out] pu8DestData: buffer of the target data
++ * param[in] u32ByteLength Length of the decrypted data
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_DecryptVir(HI_HANDLE hCipher, const HI_U8 *pu8SrcData, HI_U8 *pu8DestData, HI_U32 u32ByteLength);
+
-+/**
-+\brief Encrypt multiple packaged data.
-+\attention \n
-+You can not encrypt more than 128 data package one time. When HI_ERR_CIPHER_BUSY return, the data package you send will not be deal, the customer should decrease the number of data package or run cipher again.Note:When encrypting more than one packaged data, every one package will be calculated using initial vector configured by HI_UNF_CIPHER_ConfigHandle.Previous result will not affect the later result.
-+\param[in] hCipher cipher handle
-+\param[in] pstDataPkg data package ready for cipher
-+\param[in] u32DataPkgNum number of package ready for cipher
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT cipher device have not been initialized
-+\retval ::HI_ERR_CIPHER_INVALID_PARA parameter error
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE handle invalid
-+\retval ::HI_ERR_CIPHER_BUSY hardware is busy, it can not deal with all data package once time
-+\see \n
-+N/A
-+*/
++/*
++ * brief Encrypt multiple packaged data.
++ *
++ * attention \n
++ * You can not encrypt more than 128 data package one time. When HI_ERR_CIPHER_BUSY return, the data package you send
++ * will not be deal, the customer should decrease the number of data package or run cipher again.Note:When encrypting
++ * more than one packaged data, every one package will be calculated using initial vector configured by
++ * HI_UNF_CIPHER_ConfigHandle. Previous result will not affect the later result.
++ *
++ * param[in] hCipher cipher handle
++ * param[in] pstDataPkg data package ready for cipher
++ * param[in] u32DataPkgNum number of package ready for cipher
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT cipher device have not been initialized
++ * retval ::HI_ERR_CIPHER_INVALID_PARA parameter error
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE handle invalid
++ * retval ::HI_ERR_CIPHER_BUSY hardware is busy, it can not deal with all data package once time
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_EncryptMulti(HI_HANDLE hCipher, const HI_UNF_CIPHER_DATA_S *pstDataPkg, HI_U32 u32DataPkgNum);
+
-+/**
-+\brief Get the cipher control information.
++/*
++ * brief Get the cipher control information.
++ *
++ * param[in] hCipher Cipher handle.
++ * param[in] pstCtrl Cipher control information.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
++HI_S32 HI_UNF_CIPHER_GetHandleConfig(HI_HANDLE hCipher, HI_UNF_CIPHER_CTRL_S *pstCtrl);
+
-+\param[in] hCipher Cipher handle.
-+\param[in] pstCtrl Cipher control information.
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
-+HI_S32 HI_UNF_CIPHER_GetHandleConfig(HI_HANDLE hCipher, HI_UNF_CIPHER_CTRL_S* pstCtrl);
-+
-+/**
-+\brief Decrypt multiple packaged data.
-+\attention \n
-+You can not decrypt more than 128 data package one time.When HI_ERR_CIPHER_BUSY return, the data package you send will not be deal, the custmer should decrease the number of data package or run cipher again.Note:When decrypting more than one packaged data, every one package will be calculated using initial vector configured by HI_UNF_CIPHER_ConfigHandle.Previous result will not affect the later result.
-+\param[in] hCipher cipher handle
-+\param[in] pstDataPkg data package ready for cipher
-+\param[in] u32DataPkgNum number of package ready for cipher
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT cipher device have not been initialized
-+\retval ::HI_ERR_CIPHER_INVALID_PARA parameter error
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE handle invalid
-+\retval ::HI_ERR_CIPHER_BUSY hardware is busy, it can not deal with all data package once time
-+\see \n
-+N/A
-+*/
++/*
++ * brief Decrypt multiple packaged data.
++ *
++ * attention \n
++ * You can not decrypt more than 128 data package one time.When HI_ERR_CIPHER_BUSY return, the data package you send
++ * will not be deal, the custmer should decrease the number of data package or run cipher again.Note:When decrypting
++ * more than one packaged data, every one package will be calculated using initial vector configured by
++ * HI_UNF_CIPHER_ConfigHandle. Previous result will not affect the later result.
++ *
++ * param[in] hCipher cipher handle
++ * param[in] pstDataPkg data package ready for cipher
++ * param[in] u32DataPkgNum number of package ready for cipher
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT cipher device have not been initialized
++ * retval ::HI_ERR_CIPHER_INVALID_PARA parameter error
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE handle invalid
++ * retval ::HI_ERR_CIPHER_BUSY hardware is busy, it can not deal with all data package once time
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_DecryptMulti(HI_HANDLE hCipher, const HI_UNF_CIPHER_DATA_S *pstDataPkg, HI_U32 u32DataPkgNum);
+
-+/**
-+\brief Get the tag data of CCM/GCM.
-+
-+\attention \n
-+This API is used to get the tag data of CCM/GCM.
-+\param[in] hCipher cipher handle
-+\param[out] pu8Tag tag data of CCM/GCM
-+\param[in/out] pu32TagLen tag data length of CCM/GCM, the input should be 16 now.
-+\retval ::HI_SUCCESS Call this API succussful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Get the tag data of CCM/GCM.
++ *
++ * attention \n
++ * This API is used to get the tag data of CCM/GCM.
++ *
++ * param[in] hCipher cipher handle
++ * param[out] pu8Tag tag data of CCM/GCM
++ * param[in/out] pu32TagLen tag data length of CCM/GCM, the input should be 16 now.
++ * retval ::HI_SUCCESS Call this API succussful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_GetTag(HI_HANDLE hCipher, HI_U8 *pu8Tag, HI_U32 *pu32TagLen);
+
-+/**
-+\brief Encrypt the clean key data by KLAD.
-+\attention \n
-+N/A
-+\param[in] enRootKey klad root key.
-+\param[in] pu8CleanKey clean key.
-+\param[in] enTarget the module who to use this key.
-+\param[out] pu8EcnryptKey encrypt key.
-+\param[in] u32KeyLen clean key.
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
-+\retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
-+\retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
-+\retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Encrypt the clean key data by KLAD.
++ * attention \n
++ * N/A
++ * param[in] enRootKey klad root key.
++ * param[in] pu8CleanKey clean key.
++ * param[in] enTarget the module who to use this key.
++ * param[out] pu8EcnryptKey encrypt key.
++ * param[in] u32KeyLen clean key.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * retval ::HI_ERR_CIPHER_NOT_INIT The cipher device is not initialized.
++ * retval ::HI_ERR_CIPHER_INVALID_POINT The pointer is null.
++ * retval ::HI_ERR_CIPHER_INVALID_PARA The parameter is invalid.
++ * retval ::HI_ERR_CIPHER_INVALID_HANDLE The handle is invalid.
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_KladEncryptKey(HI_UNF_CIPHER_CA_TYPE_E enRootKey,
+ HI_UNF_CIPHER_KLAD_TARGET_E enTarget,
-+ const HI_U8 *pu8CleanKey, HI_U8* pu8EcnryptKey, HI_U32 u32KeyLen);
++ const HI_U8 *pu8CleanKey, HI_U8 *pu8EcnryptKey, HI_U32 u32KeyLen);
+
-+/**
-+\brief Get the random number.
-+
-+\attention \n
-+This API is used to obtain the random number from the hardware.
-+
-+\param[out] pu32RandomNumber Point to the random number.
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief Get the random number.
++ *
++ * attention \n
++ * This API is used to obtain the random number from the hardware.
++ *
++ * param[out] pu32RandomNumber Point to the random number.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_GetRandomNumber(HI_U32 *pu32RandomNumber);
+
-+/**
-+\brief Init the hash module, if other program is using the hash module, the API will return failure.
-+
-+\attention \n
-+N/A
-+
-+\param[in] pstHashAttr: The hash calculating structure input.
-+\param[out] pHashHandle: The output hash handle.
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief Init the hash module, if other program is using the hash module, the API will return failure.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] pstHashAttr: The hash calculating structure input.
++ * param[out] pHashHandle: The output hash handle.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_HashInit(const HI_UNF_CIPHER_HASH_ATTS_S *pstHashAttr, HI_HANDLE *pHashHandle);
+
-+/**
-+\brief Calculate the hash, if the size of the data to be calculated is very big and the DDR ram is not enough, this API can calculate the data one block by one block. Attention: The input block length must be 64bytes aligned except for the last block.
-+
-+\attention \n
-+N/A
-+
-+\param[in] hHashHandl: Hash handle.
-+\param[in] pu8InputData: The input data buffer.
-+\param[in] u32InputDataLen: The input data length, attention: the block length input must be 64bytes aligned except the last block!
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief Calculate the hash, if the size of the data to be calculated is very big and the DDR ram is not enough, this
++ * API can calculate the data one block by one block. Attention: The input block length must be 64bytes aligned except
++ * for the last block.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] hHashHandl: Hash handle.
++ * param[in] pu8InputData: The input data buffer.
++ * param[in] u32InputDataLen: The input data length, attention: the block length input must be 64bytes aligned except
++ * the last block!
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_HashUpdate(HI_HANDLE hHashHandle, const HI_U8 *pu8InputData, HI_U32 u32InputDataLen);
+
-+
-+
-+/**
-+\brief Get the final hash value, after calculate all of the data, call this API to get the final hash value and close the handle.If there is some reason need to interrupt the calculation, this API should also be call to close the handle.
-+
-+\attention \n
-+N/A
-+
-+\param[in] hHashHandle: Hash handle.
-+\param[out] pu8OutputHash: The final output hash value.
-+
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief Get the final hash value, after calculate all of the data, call this API to get the final hash value and close
++ * the handle.If there is some reason need to interrupt the calculation, this API should also be call to close the
++ * handle.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] hHashHandle: Hash handle.
++ * param[out] pu8OutputHash: The final output hash value.
++ *
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_HashFinal(HI_HANDLE hHashHandle, HI_U8 *pu8OutputHash);
+
-+/**
-+\brief RSA encryption a plaintext with a RSA public key.
-+
-+\attention \n
-+N/A
-+
-+\param[in] pstRsaEnc: encryption struct.
-+\param[in] pu8Input: input data to be encryption
-+\param[out] u32InLen: length of input data to be encryption
-+\param[out] pu8Output: output data to be encryption
-+\param[out] pu32OutLen: length of output data to be encryption
-+
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief RSA encryption a plaintext with a RSA public key.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] pstRsaEnc: encryption struct.
++ * param[in] pu8Input: input data to be encryption
++ * param[out] u32InLen: length of input data to be encryption
++ * param[out] pu8Output: output data to be encryption
++ * param[out] pu32OutLen: length of output data to be encryption
++ *
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_RsaPublicEncrypt(const HI_UNF_CIPHER_RSA_PUB_ENC_S *pstRsaEnc,
-+ const HI_U8 *pu8Input, HI_U32 u32InLen,
-+ HI_U8 *pu8Output, HI_U32 *pu32OutLen);
++ const HI_U8 *pu8Input, HI_U32 u32InLen, HI_U8 *pu8Output, HI_U32 *pu32OutLen);
+
-+/**
-+\brief RSA decryption a ciphertext with a RSA private key.
-+
-+\attention \n
-+N/A
-+
-+\param[in] pstRsaDec: decryption struct.
-+\param[in] pu8Input: input data to be decryption
-+\param[out] u32InLen: length of input data to be decryption
-+\param[out] pu8Output: output data to be decryption
-+\param[out] pu32OutLen: length of output data to be decryption
-+
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief RSA decryption a ciphertext with a RSA private key.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] pstRsaDec: decryption struct.
++ * param[in] pu8Input: input data to be decryption
++ * param[out] u32InLen: length of input data to be decryption
++ * param[out] pu8Output: output data to be decryption
++ * param[out] pu32OutLen: length of output data to be decryption
++ *
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_RsaPrivateDecrypt(const HI_UNF_CIPHER_RSA_PRI_ENC_S *pstRsaDec,
-+ const HI_U8 *pu8Input, HI_U32 u32InLen,
-+ HI_U8 *pu8Output, HI_U32 *pu32OutLen);
++ const HI_U8 *pu8Input, HI_U32 u32InLen, HI_U8 *pu8Output, HI_U32 *pu32OutLen);
+
-+/**
-+\brief RSA encryption a plaintext with a RSA private key.
-+
-+\attention \n
-+N/A
-+
-+\param[in] pstRsaSign: encryption struct.
-+\param[in] pu8Input: input data to be encryption
-+\param[out] u32InLen: length of input data to be encryption
-+\param[out] pu8Output: output data to be encryption
-+\param[out] pu32OutLen: length of output data to be encryption
-+
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief RSA encryption a plaintext with a RSA private key.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] pstRsaSign: encryption struct.
++ * param[in] pu8Input: input data to be encryption
++ * param[out] u32InLen: length of input data to be encryption
++ * param[out] pu8Output: output data to be encryption
++ * param[out] pu32OutLen: length of output data to be encryption
++ *
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_RsaPrivateEncrypt(const HI_UNF_CIPHER_RSA_PRI_ENC_S *pstRsaEnc,
-+ const HI_U8 *pu8Input, HI_U32 u32InLen,
-+ HI_U8 *pu8Output, HI_U32 *pu32OutLen);
++ const HI_U8 *pu8Input, HI_U32 u32InLen, HI_U8 *pu8Output, HI_U32 *pu32OutLen);
+
-+/**
-+\brief RSA decryption a ciphertext with a RSA public key.
-+
-+\attention \n
-+N/A
-+
-+\param[in] pstRsaVerify: decryption struct.
-+\param[in] pu8Input: input data to be decryption
-+\param[out] u32InLen: length of input data to be decryption
-+\param[out] pu8Output: output data to be decryption
-+\param[out] pu32OutLen: length of output data to be decryption
-+
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief RSA decryption a ciphertext with a RSA public key.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] pstRsaVerify: decryption struct.
++ * param[in] pu8Input: input data to be decryption
++ * param[out] u32InLen: length of input data to be decryption
++ * param[out] pu8Output: output data to be decryption
++ * param[out] pu32OutLen: length of output data to be decryption
++ *
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_RsaPublicDecrypt(const HI_UNF_CIPHER_RSA_PUB_ENC_S *pstRsaDec,
-+ const HI_U8 *pu8Input, HI_U32 u32InLen,
-+ HI_U8 *pu8Output, HI_U32 *pu32OutLen);
++ const HI_U8 *pu8Input, HI_U32 u32InLen, HI_U8 *pu8Output, HI_U32 *pu32OutLen);
+
-+/**
-+\brief RSA signature a context with appendix, where a signer's RSA private key is used.
++/*
++ * brief RSA signature a context with appendix, where a signer's RSA private key is used.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] pstRsaSign: signature struct.
++ * param[in] pu8Input: input context to be signature.
++ * param[in] u32InLen: length of input context to be signature
++ * param[in] pu8HashData: hash value of context,if NULL, let pu8HashData = Hash(context) automatically
++ * param[out] pu8OutSign: output message of signature
++ * param[out] pu32OutSignLen: length of message of signature
++ *
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
++HI_S32 HI_UNF_CIPHER_RsaSign(const HI_UNF_CIPHER_RSA_SIGN_S *pstRsaSign, const HI_U8 *pu8InData, HI_U32 u32InDataLen,
++ const HI_U8 *pu8HashData, HI_U8 *pu8OutSign, HI_U32 *pu32OutSignLen);
+
-+\attention \n
-+N/A
-+
-+\param[in] pstRsaSign: signature struct.
-+\param[in] pu8Input: input context to be signature.
-+\param[in] u32InLen: length of input context to be signature
-+\param[in] pu8HashData: hash value of context,if NULL, let pu8HashData = Hash(context) automatically
-+\param[out] pu8OutSign: output message of signature
-+\param[out] pu32OutSignLen: length of message of signature
-+
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
-+HI_S32 HI_UNF_CIPHER_RsaSign(const HI_UNF_CIPHER_RSA_SIGN_S *pstRsaSign,
-+ const HI_U8 *pu8InData, HI_U32 u32InDataLen,
-+ const HI_U8 *pu8HashData,
-+ HI_U8 *pu8OutSign, HI_U32 *pu32OutSignLen);
-+
-+/**
-+\brief RSA signature verification a context with appendix, where a signer's RSA public key is used.
-+
-+\attention \n
-+N/A
-+
-+\param[in] pstRsaVerify: signature verification struct.
-+\param[in] pu8Input: input context to be signature verification, maybe null
-+\param[in] u32InLen: length of input context to be signature
-+\param[in] pu8HashData: hash value of context,if NULL, let pu8HashData = Hash(context) automatically
-+\param[in] pu8InSign: message of signature
-+\param[in] pu32InSignLen: length of message of signature
-+
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+
-+\see \n
-+N/A
-+*/
++/*
++ * brief RSA signature verification a context with appendix, where a signer's RSA public key is used.
++ *
++ * attention \n
++ * N/A
++ *
++ * param[in] pstRsaVerify: signature verification struct.
++ * param[in] pu8Input: input context to be signature verification, maybe null
++ * param[in] u32InLen: length of input context to be signature
++ * param[in] pu8HashData: hash value of context,if NULL, let pu8HashData = Hash(context) automatically
++ * param[in] pu8InSign: message of signature
++ * param[in] pu32InSignLen: length of message of signature
++ *
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ *
++ * see \n
++ * N/A
++ */
+HI_S32 HI_UNF_CIPHER_RsaVerify(const HI_UNF_CIPHER_RSA_VERIFY_S *pstRsaVerify,
-+ const HI_U8 *pu8InData, HI_U32 u32InDataLen,
-+ const HI_U8 *pu8HashData,
-+ const HI_U8 *pu8InSign, HI_U32 u32InSignLen);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
++ const HI_U8 *pu8InData, HI_U32 u32InDataLen, const HI_U8 *pu8HashData, const HI_U8 *pu8InSign, HI_U32 u32InSignLen);
+
+#ifdef __cplusplus
+#if __cplusplus
@@ -199147,151 +268199,100 @@ index 0000000..ffcdd31
+
diff --git a/drivers/crypto/hisi-cipher/src/Makefile b/drivers/crypto/hisi-cipher/src/Makefile
new file mode 100644
-index 0000000..80d5818
+index 0000000..e6f595a
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/Makefile
-@@ -0,0 +1,64 @@
-+#export CIPHER_SRC_BASE=$(CURDIR)/drivers/crypto/hisi-cipher/src
-+export CIPHER_SRC_BASE=$(src)
+@@ -0,0 +1,27 @@
++export CIPHER_SRC_BASE=$(CURDIR)/drivers/crypto/hisi-cipher/src
+
+include $(CIPHER_SRC_BASE)/drv/cipher_v1.0/build.mak
+
-+ifeq ($(CONFIG_ARCH_HI3519AV100),y)
-+INTER_DRV := hi3519av100
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3556AV100),y)
-+INTER_DRV := hi3556av100
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3559AV100),y)
-+INTER_DRV := hi3559av100
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516CV500),y)
-+INTER_DRV := hi3516cv500
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516DV300),y)
-+INTER_DRV := hi3516dv300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3556V200),y)
-+INTER_DRV := hi3556v200
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3559V200),y)
-+INTER_DRV := hi3559v200
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516AV300),y)
-+INTER_DRV := hi3516av300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516EV200),y)
-+INTER_DRV := hi3516ev200
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516EV300),y)
-+INTER_DRV := hi3516ev300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3518EV300),y)
-+INTER_DRV := hi3518ev300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516DV200),y)
-+INTER_DRV := hi3516dv200
-+endif
-+
+EXTRA_CFLAGS += -I$(CIPHER_SRC_BASE)/../include
+EXTRA_CFLAGS += $(CIPHER_INS)
-+EXTRA_CFLAGS += -I$(CIPHER_SRC_BASE)/../../hisi-otp
++EXTRA_CFLAGS += $(CIPHER_CFLAGS)
+
+CIPHER_OBJS += drv/cipher_initdevice.o
+
-+EXTRA_CFLAGS += -DCHIP_TYPE_$(INTER_DRV)
-+EXTRA_CFLAGS += $(CIPHER_CFLAGS)
-+
+obj-y += hi_cipher.o
+hi_cipher-y += $(CIPHER_OBJS)
++
++ifeq ($(findstring y, $(CONFIG_ARCH_HI3516CV500) $(CONFIG_ARCH_HI3516DV300) \
++ $(CONFIG_ARCH_HI3516AV300) $(CONFIG_ARCH_HI3559V200) \
++ $(CONFIG_ARCH_HI3562V100) $(CONFIG_ARCH_HI3566V100)), y)
++INTER_DRV := hi3516cv500
++else ifeq ($(findstring y, $(CONFIG_ARCH_HI3559AV100) $(CONFIG_ARCH_HI3569V100)), y)
++INTER_DRV := hi3559av100
++else ifeq ($(findstring y, $(CONFIG_ARCH_HI3519AV100) $(CONFIG_ARCH_HI3556AV100)), y)
++INTER_DRV := hi3519av100
++else ifeq ($(findstring y, $(CONFIG_ARCH_HI3516EV200) $(CONFIG_ARCH_HI3516EV300) \
++ $(CONFIG_ARCH_HI3516DV200) $(CONFIG_ARCH_HI3518EV300)), y)
++INTER_DRV := hi3516ev200
++endif
++
++EXTRA_CFLAGS += -DCHIP_TYPE_$(INTER_DRV)
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_initdevice.c b/drivers/crypto/hisi-cipher/src/drv/cipher_initdevice.c
new file mode 100644
-index 0000000..3639e69
+index 0000000..aab1564
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_initdevice.c
-@@ -0,0 +1,124 @@
+@@ -0,0 +1,110 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
++ * Description : drivers for cipher init device.
++ * Author : Hisilicon multimedia software group
++ * Create : 2018-10-20
+ */
+
+#include "hi_types.h"
+#include "drv_osal_lib.h"
+
-+extern int cipher_drv_mod_init(void);
-+extern void cipher_drv_mod_exit(void);
-+
+#ifndef __HuaweiLite__
+#ifdef IRQ_DTS_SUPPORT
+#include <linux/of_platform.h>
+
+static int hi35xx_cipher_probe(struct platform_device *pdev)
+{
-+ hi_u32 irq_num = 0;
++ hi_u32 irq_num;
+
+#if defined(ARCH_TYPE_amp) && !defined(CRYPTO_SEC_CPU)
+ irq_num = platform_get_irq_byname(pdev, "nonsec_cipher");
+ if (irq_num <= 0) {
-+ dev_err(&pdev->dev, "cannot find cipher IRQ\n");
++ dev_err(&pdev->dev, "cannot find cipher IRQ number %d.\n", irq_num);
+ return -1;
+ }
+ module_set_irq(CRYPTO_MODULE_ID_SYMC, irq_num);
+
+ irq_num = platform_get_irq_byname(pdev, "nonsec_hash");
+ if (irq_num <= 0) {
-+ dev_err(&pdev->dev, "cannot find trng IRQ\n");
++ dev_err(&pdev->dev, "cannot find trng IRQ number %d.\n", irq_num);
+ return -1;
+ }
+ module_set_irq(CRYPTO_MODULE_ID_HASH, irq_num);
+
+ irq_num = platform_get_irq_byname(pdev, "nonsec_rsa");
+ if (irq_num <= 0) {
-+ dev_err(&pdev->dev, "cannot find rsa IRQ\n");
++ dev_err(&pdev->dev, "cannot find rsa IRQ number %d.\n", irq_num);
+ return -1;
+ }
+ module_set_irq(CRYPTO_MODULE_ID_IFEP_RSA, irq_num);
+#else
+ irq_num = platform_get_irq_byname(pdev, "cipher");
+ if (irq_num <= 0) {
-+ dev_err(&pdev->dev, "cannot find cipher IRQ\n");
++ dev_err(&pdev->dev, "cannot find cipher IRQ number %d.\n", irq_num);
+ return -1;
+ }
+ module_set_irq(CRYPTO_MODULE_ID_SYMC, irq_num);
+
+ irq_num = platform_get_irq_byname(pdev, "hash");
+ if (irq_num <= 0) {
-+ dev_err(&pdev->dev, "cannot find trng IRQ\n");
++ dev_err(&pdev->dev, "cannot find trng IRQ number %d.\n", irq_num);
+ return -1;
+ }
+ module_set_irq(CRYPTO_MODULE_ID_HASH, irq_num);
+
+ irq_num = platform_get_irq_byname(pdev, "rsa");
+ if (irq_num <= 0) {
-+ dev_err(&pdev->dev, "cannot find rsa IRQ\n");
++ dev_err(&pdev->dev, "cannot find rsa IRQ number %d.\n", irq_num);
+ return -1;
+ }
+ module_set_irq(CRYPTO_MODULE_ID_IFEP_RSA, irq_num);
@@ -199311,22 +268312,22 @@ index 0000000..3639e69
+ return 0;
+}
+
-+static const struct of_device_id hi35xx_cipher_match[] = {
++static const struct of_device_id g_hi35xx_cipher_match[] = {
+ { .compatible = "hisilicon,hisi-cipher" },
-+ {},
++ { },
+};
-+MODULE_DEVICE_TABLE(of, hi35xx_cipher_match);
++MODULE_DEVICE_TABLE(of, g_hi35xx_cipher_match);
+
-+static struct platform_driver hi35xx_cipher_driver = {
++static struct platform_driver g_hi35xx_cipher_driver = {
+ .probe = hi35xx_cipher_probe,
+ .remove = hi35xx_cipher_remove,
+ .driver = {
+ .name = "hi35xx_cipher",
-+ .of_match_table = hi35xx_cipher_match,
++ .of_match_table = g_hi35xx_cipher_match,
+ },
+};
+
-+module_platform_driver(hi35xx_cipher_driver);
++module_platform_driver(g_hi35xx_cipher_driver);
+MODULE_LICENSE("GPL");
+#else
+static int __init cipher_mod_init(void)
@@ -199368,127 +268369,127 @@ index 0000000..8485fc5
+EXTRA_CFLAGS += $(CIPHER_CFLAGS)
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/build.mak b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/build.mak
new file mode 100644
-index 0000000..e6f39d1
+index 0000000..169fc16
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/build.mak
-@@ -0,0 +1,6 @@
+@@ -0,0 +1,7 @@
+CIPHER_OBJS += drv/cipher_v1.0/compat/hi_drv_compat.o
+CIPHER_OBJS += drv/cipher_v1.0/compat/drv_klad.o
+CIPHER_OBJS += drv/cipher_v1.0/compat/hal_efuse.o
++CIPHER_OBJS += drv/cipher_v1.0/compat/hal_otp.o
+
+CIPHER_CFLAGS += -I$(CIPHER_DIR)/drv/cipher_v1.0/compat
+
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/drv_klad.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/drv_klad.c
new file mode 100644
-index 0000000..0293854
+index 0000000..3d666cd
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/drv_klad.c
-@@ -0,0 +1,270 @@
+@@ -0,0 +1,254 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for klad.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "hi_types.h"
+#include "drv_osal_lib.h"
+#include "hal_efuse.h"
-+#include "../../../../../hisi-otp/hal_otp.h"
++#include "hal_otp.h"
+#include "drv_cipher_kapi.h"
++#include "drv_klad.h"
+
-+#define KLAD_REG_BASE_ADDR cipher_klad_base
++#define KLAD_REG_BASE_ADDR g_cipher_klad_base
++#define KLAD_BASE_BUF_SIZE 0x100
+#define KLAD_REG_KLAD_CTRL (KLAD_REG_BASE_ADDR + 0x00)
+#define KLAD_REG_DAT_IN (KLAD_REG_BASE_ADDR + 0x10)
+#define KLAD_REG_ENC_OUT (KLAD_REG_BASE_ADDR + 0x20)
+
+#define CIPHER_WAIT_IDEL_TIMES 1000
+
-+static hi_u8 *cipher_klad_base = HI_NULL;
-+extern hi_u8 *efuse_otp_reg_base;
++static hi_u8 *g_cipher_klad_base = HI_NULL;
+
+hi_s32 hal_cipher_klad_config(hi_u32 chn_id, hi_u32 opt_id, hi_cipher_klad_target target, hi_bool is_decrypt)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 ctrl;
++ hi_s32 ret;
++ klad_ctrl ctrl;
+
+ /* Load efuse or OTP key to KLAD */
+ ret = hal_efuse_otp_load_cipher_key(chn_id, opt_id);
+ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(hal_efuse_otp_load_cipher_key, ret);
+ return ret;
+ }
+
-+ ctrl = chn_id << 16;
-+ ctrl |= ((hi_u32)target) << 2; /* cipher klad */
-+ ctrl |= ((hi_u32)is_decrypt) << 1; /* decrypt */
-+ ctrl |= 0x00; /* start */
-+
-+ (hi_void)HAL_CIPHER_WRITE_REG(KLAD_REG_KLAD_CTRL, ctrl);
++ ctrl.u32 = 0;
++ ctrl.bits.klad2ci_addr = chn_id;
++ ctrl.bits.type = target;
++ ctrl.bits.decrypt = is_decrypt;
++ ctrl.bits.start = KLAD_CTRL_NOT_START;
+
++ (hi_void)hal_cipher_write_reg(KLAD_REG_KLAD_CTRL, ctrl.u32);
+ return HI_SUCCESS;
+}
+
+hi_void hal_cipher_start_klad(hi_u32 block_num)
+{
-+ hi_u32 ctrl = 0;
-+ hi_u32 high = 0;
++ klad_ctrl ctrl;
+
-+ high = (block_num == 1 ? 1 : 0);
++ ctrl.u32 = 0;
++ hal_cipher_read_reg(KLAD_REG_KLAD_CTRL, &ctrl.u32);
++
++ /* High 128bits is just meaningful for loading cipher 256 bits key, and meaningless to rsa. */
++ if (block_num == KLAD_HIGN_128BIT_BLOCK) {
++ ctrl.bits.high_low_128bit_flag = KLAD_CTRL_HIGH_128BIT_FLAG;
++ } else {
++ ctrl.bits.high_low_128bit_flag = KLAD_CTRL_LOW_128BIT_FLAG;
++ }
+
+ /* start */
-+ (hi_void)HAL_CIPHER_READ_REG(KLAD_REG_KLAD_CTRL, &ctrl);
-+ ctrl &= ~(0x01 << 4);
-+ ctrl |= high << 4;
-+ ctrl |= 0x01; /* start */
-+ (hi_void)HAL_CIPHER_WRITE_REG(KLAD_REG_KLAD_CTRL, ctrl);
++ ctrl.bits.start = KLAD_CTRL_START;
++ hal_cipher_write_reg(KLAD_REG_KLAD_CTRL, ctrl.u32);
+}
+
-+hi_void hal_cipher_set_klad_data(hi_u32 *data_in)
++hi_void hal_cipher_set_klad_data(hi_u32 *data_in, hi_u32 data_len_in_word)
+{
-+ hi_u32 i = 0;
++ hi_u32 i;
+
-+ for (i = 0; i < 4; i++) {
-+ (hi_void)HAL_CIPHER_WRITE_REG(KLAD_REG_DAT_IN + i * 4, data_in[i]);
++ /* The length of klad input key is 16 bytes. */
++ for (i = 0; i < data_len_in_word; i++) {
++ (hi_void)hal_cipher_write_reg(KLAD_REG_DAT_IN + i * WORD_WIDTH, data_in[i]);
+ }
+}
+
-+hi_void hal_cipher_get_klad_data(hi_u32 *data_out)
++hi_void hal_cipher_get_klad_data(hi_u32 *data_out, hi_u32 data_len_in_word)
+{
-+ hi_u32 i = 0;
++ hi_u32 i;
+
-+ for (i = 0; i < 4; i++) {
-+ (hi_void)HAL_CIPHER_READ_REG(KLAD_REG_ENC_OUT + i * 4, &data_out[i]);
++ /* The length of klad ouput key is 16 bytes. */
++ for (i = 0; i < data_len_in_word; i++) {
++ (hi_void)hal_cipher_read_reg(KLAD_REG_ENC_OUT + i * WORD_WIDTH, &data_out[i]);
+ }
+}
+
+hi_s32 hal_cipher_wait_klad_done(hi_void)
+{
-+ hi_u32 try_count = 0;
-+ hi_u32 ctrl = 0;
++ hi_s32 i;
++ klad_ctrl ctrl;
+
-+ do {
-+ HAL_CIPHER_READ_REG(KLAD_REG_KLAD_CTRL, &ctrl);
-+ if ((ctrl & 0x01) == 0x00) {
++ for (i = 0; i < CIPHER_WAIT_IDEL_TIMES; i++) {
++ ctrl.u32 = 0;
++ hal_cipher_read_reg(KLAD_REG_KLAD_CTRL, &ctrl.u32);
++ if (ctrl.bits.start == KLAD_CTRL_NOT_START) {
+ return HI_SUCCESS;
+ }
-+ try_count++;
-+ } while (try_count < CIPHER_WAIT_IDEL_TIMES);
++ }
+
-+ HI_LOG_ERROR("Klad time out!\n");
-+
-+ return HI_FAILURE;
++ if (i >= CIPHER_WAIT_IDEL_TIMES) {
++ hi_log_error("Klad wait time out!\n");
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
+
++ return HI_SUCCESS;
+}
+
+hi_void hal_cipher_klad_init(hi_void)
@@ -199496,38 +268497,38 @@ index 0000000..0293854
+ hi_u32 crg_value = 0;
+ hi_u32 *sys_addr = HI_NULL;
+
-+ sys_addr = crypto_ioremap_nocache(KLAD_CRG_ADDR_PHY, 0x100);
++ sys_addr = crypto_ioremap_nocache(KLAD_CRG_ADDR_PHY, KLAD_BASE_BUF_SIZE);
+ if (sys_addr == HI_NULL) {
-+ HI_LOG_ERROR("ERROR: sys_addr ioremap with nocache failed!!\n");
++ hi_log_error("ERROR: sys_addr ioremap with nocache failed!!\n");
+ return ;
+ }
+
-+ HAL_CIPHER_READ_REG(sys_addr, &crg_value);
++ hal_cipher_read_reg(sys_addr, &crg_value);
+ crg_value |= KLAD_CRG_RESET_BIT; /* reset */
+ crg_value |= KLAD_CRG_CLOCK_BIT; /* set the bit 0, clock opened */
-+ HAL_CIPHER_WRITE_REG(sys_addr, crg_value);
++ hal_cipher_write_reg(sys_addr, crg_value);
+
-+ /* clock select and cancel reset 0x30100*/
++ /* clock select and cancel reset 0x30100. */
+ crg_value &= (~KLAD_CRG_RESET_BIT); /* cancel reset */
+ crg_value |= KLAD_CRG_CLOCK_BIT; /* set the bit 0, clock opened */
-+ HAL_CIPHER_WRITE_REG(sys_addr, crg_value);
++ hal_cipher_write_reg(sys_addr, crg_value);
+
-+ crypto_iounmap(sys_addr, 0x100);
++ crypto_iounmap(sys_addr, KLAD_BASE_BUF_SIZE);
+}
+
+hi_s32 drv_cipher_klad_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ cipher_klad_base = crypto_ioremap_nocache(KLAD_REG_BASE_ADDR_PHY, 0x100);
-+ if (cipher_klad_base == HI_NULL) {
-+ HI_LOG_ERROR("ERROR: osal_ioremap_nocache for KLAD failed!!\n");
-+ return HI_FAILURE;
++ g_cipher_klad_base = crypto_ioremap_nocache(KLAD_REG_BASE_ADDR_PHY, KLAD_BASE_BUF_SIZE);
++ if (g_cipher_klad_base == HI_NULL) {
++ hi_log_error("ERROR: osal_ioremap_nocache for KLAD failed!!\n");
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
+ ret = hal_efuse_otp_init();
+ if (ret != HI_SUCCESS) {
-+ crypto_iounmap(cipher_klad_base, 0x100);
++ crypto_iounmap(g_cipher_klad_base, KLAD_BASE_BUF_SIZE);
+ return ret;
+ }
+
@@ -199538,200 +268539,177 @@ index 0000000..0293854
+
+hi_void drv_cipher_klad_deinit(hi_void)
+{
-+ if (cipher_klad_base != HI_NULL) {
-+ crypto_iounmap(cipher_klad_base, 0x100);
-+ cipher_klad_base = HI_NULL;
++ hi_u8 *local_efuse_otp_reg_base = HI_NULL;
++
++ if (g_cipher_klad_base != HI_NULL) {
++ crypto_iounmap(g_cipher_klad_base, KLAD_BASE_BUF_SIZE);
++ g_cipher_klad_base = HI_NULL;
+ }
+
-+ if (efuse_otp_reg_base != HI_NULL) {
-+ crypto_iounmap(efuse_otp_reg_base, 0x100);
-+ efuse_otp_reg_base = HI_NULL;
++ local_efuse_otp_reg_base = hal_efuse_otp_get_reg_base();
++ if (local_efuse_otp_reg_base != HI_NULL) {
++ crypto_iounmap(local_efuse_otp_reg_base, KLAD_BASE_BUF_SIZE);
++ local_efuse_otp_reg_base = HI_NULL;
++ hal_efuse_otp_set_reg_base(local_efuse_otp_reg_base);
+ }
+
+ return ;
+}
+
-+hi_void drv_cipher_input_buf(hi_u8 *buf, hi_u32 length)
++static hi_void drv_cipher_inverse_data(hi_u8 *data, hi_u32 len)
+{
+ hi_u32 i;
+ hi_u8 ch;
+
-+ for (i = 0; i < length / 2; i++) {
-+ ch = buf[i];
-+ buf[i] = buf[length - i - 1];
-+ buf[length - i - 1] = ch;
++ for (i = 0; i < len / MUL_VAL_2; i++) {
++ ch = data[i];
++ data[i] = data[len - i - BOUND_VAL_1];
++ data[len - i - BOUND_VAL_1] = ch;
+ }
+}
+
-+hi_s32 drv_cipher_klad_load_key(hi_u32 chn_id,
-+ hi_cipher_ca_type root_key,
-+ hi_cipher_klad_target target,
-+ hi_u8 *data_in,
-+ hi_u32 key_len)
++/* load aes or rsa clean key to klad. */
++hi_s32 drv_cipher_klad_load_key(hi_u32 chn_id, hi_cipher_ca_type root_key, hi_cipher_klad_target target, hi_u8 *data_in,
++ hi_u32 key_len)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 i = 0;
-+ hi_u32 key[4] = {0};
-+ hi_u32 opt_id = 0;;
++ hi_s32 ret;
++ hi_u32 i, opt_id;
++ hi_u32 key[AES_BLOCK_SIZE / WORD_WIDTH] = {0};
+
-+ if ((root_key < HI_CIPHER_KEY_SRC_KLAD_1) ||
-+ (root_key > HI_CIPHER_KEY_SRC_KLAD_3)) {
-+ HI_LOG_ERROR("Error: Invalid Root Key src 0x%x!\n", root_key);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+ if (((key_len % 16 ) != 0) || (key_len == 0)) {
-+ HI_LOG_ERROR("Error: Invalid key len 0x%x!\n", key_len);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+ if (data_in == HI_NULL) {
-+ HI_LOG_ERROR("Error: point for input data is null!\n");
-+ return HI_ERR_CIPHER_INVALID_POINT;
-+ }
++ hi_log_chk_param_return((root_key < HI_CIPHER_KEY_SRC_KLAD_1) || (root_key > HI_CIPHER_KEY_SRC_KLAD_3));
++ hi_log_chk_param_return(target >= HI_CIPHER_KLAD_TARGET_BUTT);
++ hi_log_chk_param_return(data_in == HI_NULL);
++ hi_log_chk_param_return(((key_len % AES_BLOCK_SIZE) != 0) || (key_len == 0));
+
-+ opt_id = root_key - HI_CIPHER_KEY_SRC_KLAD_1 + 1;
++ opt_id = root_key - HI_CIPHER_KEY_SRC_KLAD_1 + BOUND_VAL_1;
+
+ ret = hal_cipher_klad_config(chn_id, opt_id, target, HI_TRUE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Error: cipher klad config failed!\n");
++ hi_log_error("Error: cipher klad config failed!\n");
+ return ret;
+ }
+
-+ for (i = 0; i < key_len / 16; i++) {
-+ crypto_memcpy(key, sizeof(key), data_in + i * 16, 16);
-+ hal_cipher_set_klad_data(key);
++ for (i = 0; i < key_len / AES_BLOCK_SIZE; i++) {
++ crypto_memcpy(key, sizeof(key), data_in + i * AES_BLOCK_SIZE, AES_BLOCK_SIZE);
++ hal_cipher_set_klad_data(key, sizeof(key) / WORD_WIDTH);
+ hal_cipher_start_klad(i);
+ ret = hal_cipher_wait_klad_done();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Error: cipher klad wait done failed!\n");
-+ crypto_memset(key, sizeof(key), 0, sizeof(key));
++ hi_log_error("Error: cipher klad wait done failed!\n");
++ crypto_zeroize(key, sizeof(key));
+ return ret;
+ }
+ }
+
-+ crypto_memset(key, sizeof(key), 0, sizeof(key));
++ crypto_zeroize(key, sizeof(key));
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_cipher_klad_encrypt_key(hi_cipher_ca_type root_key,
-+ hi_cipher_klad_target target,
-+ hi_u32 clean_key[4],
-+ hi_u32 encrypt_key[4])
++hi_s32 drv_cipher_klad_encrypt_key(hi_cipher_ca_type root_key, hi_cipher_klad_target target, hi_u8 *clean_key,
++ hi_u8 *encrypt_key, hi_u32 key_len)
+{
+ hi_s32 ret;
+ hi_u32 opt_id;
+
-+ if ((root_key < HI_CIPHER_KEY_SRC_KLAD_1) ||
-+ (root_key >= HI_CIPHER_KEY_SRC_BUTT)) {
-+ HI_LOG_ERROR("Error: Invalid Root Key src 0x%x!\n", root_key);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+ if ((clean_key == HI_NULL) || (encrypt_key == HI_NULL)) {
-+ HI_LOG_ERROR("Clean key or encrypt key is null.\n");
-+ return HI_ERR_CIPHER_INVALID_POINT;
-+ }
++ hi_log_chk_param_return((root_key < HI_CIPHER_KEY_SRC_KLAD_1) || (root_key >= HI_CIPHER_KEY_SRC_BUTT));
++ hi_log_chk_param_return(target >= HI_CIPHER_KLAD_TARGET_BUTT);
++ hi_log_chk_param_return((clean_key == HI_NULL) || (encrypt_key == HI_NULL));
++ hi_log_chk_param_return(key_len != AES_BLOCK_SIZE);
+
-+ opt_id = root_key - HI_CIPHER_KEY_SRC_KLAD_1 + 1;
++ opt_id = root_key - HI_CIPHER_KEY_SRC_KLAD_1 + BOUND_VAL_1;
+
+ ret = hal_cipher_klad_config(0, opt_id, HI_CIPHER_KLAD_TARGET_AES, HI_FALSE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Error: cipher klad config failed!\n");
-+ return HI_FAILURE;
++ hi_log_error("Error: cipher klad config failed!\n");
++ return ret;
+ }
+
+ if (target == HI_CIPHER_KLAD_TARGET_RSA) {
-+ drv_cipher_input_buf((hi_u8 *)clean_key, 16);
++ drv_cipher_inverse_data(clean_key, key_len);
+ }
+
-+ hal_cipher_set_klad_data(clean_key);
++ hal_cipher_set_klad_data((hi_u32 *)clean_key, key_len / WORD_WIDTH);
+ hal_cipher_start_klad(0);
+ ret = hal_cipher_wait_klad_done();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Error: cipher klad wait done failed!\n");
++ hi_log_error("Error: cipher klad wait done failed!\n");
+ return ret;
+ }
-+ hal_cipher_get_klad_data(encrypt_key);
++ hal_cipher_get_klad_data((hi_u32 *)encrypt_key, key_len / WORD_WIDTH);
+
+ return HI_SUCCESS;
+}
+
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/drv_klad.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/drv_klad.h
new file mode 100644
-index 0000000..523bf64
+index 0000000..694c3de
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/drv_klad.h
-@@ -0,0 +1,49 @@
+@@ -0,0 +1,53 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv klad.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
-+#ifndef __DRV_KLAD_H_
-+#define __DRV_KLAD_H_
++#ifndef _DRV_KLAD_H_
++#define _DRV_KLAD_H_
+
-+#include "hi_types.h"
-+#include "drv_osal_lib.h"
++#include "hi_cipher_compat.h"
+
-+hi_s32 hal_cipher_klad_config(hi_u32 chn_id,
-+ hi_u32 opt_id,
-+ hi_cipher_klad_target target,
-+ hi_bool is_decrypt);
++/* Define the union klad_ctrl */
++typedef union {
++ struct {
++ hi_u32 start : 1 ; /* [0] */
++ hi_u32 decrypt : 1 ; /* [1] */
++ hi_u32 type : 2 ; /* [3..2] */
++ hi_u32 high_low_128bit_flag : 1 ; /* [4] */
++ hi_u32 resv1 : 11 ; /* [15..5] */
++ hi_u32 klad2ci_addr : 3 ; /* [18..16] */
++ hi_u32 resv2 : 13 ; /* [31..19] */
++ } bits;
+
++ hi_u32 u32;
++} klad_ctrl;
++
++#define klad_data_in(id) (0x10 + (id) * WORD_WIDTH)
++#define klad_data_out(id) (0x20 + (id) * WORD_WIDTH)
++
++#define KLAD_CTRL_NOT_START 0
++#define KLAD_CTRL_START 1
++
++#define KLAD_HIGN_128BIT_BLOCK 1
++#define KLAD_CTRL_LOW_128BIT_FLAG 0
++#define KLAD_CTRL_HIGH_128BIT_FLAG 1
++
++hi_s32 hal_cipher_klad_config(hi_u32 chn_id, hi_u32 opt_id, hi_cipher_klad_target target, hi_bool is_decrypt);
+hi_void hal_cipher_start_klad(hi_u32 block_num);
-+hi_void hal_cipher_set_klad_data(hi_u32 *data_in);
-+hi_void hal_cipher_get_klad_data(hi_u32 *data_out);
++hi_void hal_cipher_set_klad_data(hi_u32 *data_in, hi_u32 data_len_in_word);
++hi_void hal_cipher_get_klad_data(hi_u32 *data_out, hi_u32 data_len_in_word);
+hi_s32 hal_cipher_wait_klad_done(hi_void);
+
+hi_s32 drv_cipher_klad_init(hi_void);
+hi_void drv_cipher_klad_deinit(hi_void);
+
-+hi_s32 drv_cipher_klad_load_key(hi_u32 chn_id,
-+ hi_cipher_ca_type root_key,
-+ hi_cipher_klad_target target,
-+ hi_u8 *data_in,
-+ hi_u32 key_len);
++hi_s32 drv_cipher_klad_load_key(hi_u32 chn_id, hi_cipher_ca_type root_key, hi_cipher_klad_target target,
++ hi_u8 *data_in, hi_u32 key_len);
+
-+hi_s32 drv_cipher_klad_encrypt_key(hi_cipher_ca_type root_key,
-+ hi_cipher_klad_target target,
-+ hi_u32 clean_key[4],
-+ hi_u32 encrypt_key[4]);
++hi_s32 drv_cipher_klad_encrypt_key(hi_cipher_ca_type root_key, hi_cipher_klad_target target,
++ hi_u8 *clean_key, hi_u8 *encrypt_key, hi_u32 key_len);
+
+#endif
-\ No newline at end of file
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_efuse.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_efuse.c
new file mode 100644
-index 0000000..9e0bbee
+index 0000000..cd689ac
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_efuse.c
-@@ -0,0 +1,306 @@
+@@ -0,0 +1,310 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for hal efuse.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "hi_types.h"
@@ -199739,10 +268717,9 @@ index 0000000..9e0bbee
+#include "hal_efuse.h"
+
+#ifdef EFUSE_SUPPORT
++hi_u8 *g_efuse_otp_reg_base = HI_NULL;
+
-+hi_u8 *efuse_otp_reg_base = HI_NULL;
-+
-+#define EFUSE_REG_BASE_ADDR efuse_otp_reg_base
++#define EFUSE_REG_BASE_ADDR g_efuse_otp_reg_base
+#define CIPHER_KD_WKEY0 (EFUSE_REG_BASE_ADDR + 0x00)
+#define CIPHER_KD_WKEY1 (EFUSE_REG_BASE_ADDR + 0x04)
+#define CIPHER_KD_WKEY2 (EFUSE_REG_BASE_ADDR + 0x08)
@@ -199752,13 +268729,13 @@ index 0000000..9e0bbee
+#define OTP_PGM_TIME (EFUSE_REG_BASE_ADDR + 0x18)
+#define OTP_RD_TIME (EFUSE_REG_BASE_ADDR + 0x1c)
+#define OTP_LOGIC_LEVEL (EFUSE_REG_BASE_ADDR + 0x20)
-+#define KD_CTL_MODE_CIPHER_KEY_ADDR(chn_id) (chn_id<<8)
-+#define KD_CTL_MODE_OPT_KEY_ADDR(opt_id) (opt_id<<4)
-+#define KD_CTL_MODE_HASH_KL (0x8)
-+#define KD_CTL_MODE_OPT_KD (0x4)
-+#define KD_CTL_MODE_CIPHER_KL (0x2)
-+#define KD_CTL_MODE_START (0x1)
-+#define KD_TIME_OUT (1000)
++#define kd_ctl_mode_cipher_key_addr(chn_id) (chn_id << 8)
++#define kd_ctl_mode_opt_key_addr(opt_id) (opt_id << 4)
++#define KD_CTL_MODE_HASH_KL 0x8
++#define KD_CTL_MODE_OPT_KD 0x4
++#define KD_CTL_MODE_CIPHER_KL 0x2
++#define KD_CTL_MODE_START 0x1
++#define KD_TIME_OUT 1000
+
+#define REG_SYS_EFUSE_CLK_ADDR_PHY 0x120100D8
+
@@ -199766,22 +268743,21 @@ index 0000000..9e0bbee
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int cipher_kl_finish : 1 ; /* [0] */
-+ unsigned int hash_key_read_busy : 1 ; /* [1] */
-+ unsigned int Reserved_3 : 25 ; /* [26..2] */
-+ unsigned int ctrl_rdy : 1 ; /* [27] */
-+ unsigned int ctrl_busy0 : 1 ; /* [28] */
-+ unsigned int ctrl_busy1 : 1 ; /* [29] */
-+ unsigned int key_wt_error : 1 ; /* [30] */
-+ unsigned int key_wt_finish : 1 ; /* [31] */
++ hi_u32 cipher_kl_finish : 1 ; /* [0] */
++ hi_u32 hash_key_read_busy : 1 ; /* [1] */
++ hi_u32 reserved_3 : 25 ; /* [26..2] */
++ hi_u32 ctrl_rdy : 1 ; /* [27] */
++ hi_u32 ctrl_busy0 : 1 ; /* [28] */
++ hi_u32 ctrl_busy1 : 1 ; /* [29] */
++ hi_u32 key_wt_error : 1 ; /* [30] */
++ hi_u32 key_wt_finish : 1 ; /* [31] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} cipher_kd_sta;
+
-+static hi_u32 is_efuse_busy_flag = HI_FALSE;
++static hi_u32 g_is_efuse_busy_flag = HI_FALSE;
+
+hi_s32 hal_efuse_otp_init(hi_void)
+{
@@ -199790,26 +268766,26 @@ index 0000000..9e0bbee
+
+ sys_addr = crypto_ioremap_nocache(REG_SYS_EFUSE_CLK_ADDR_PHY, 0x100);
+ if (sys_addr == HI_NULL) {
-+ HI_LOG_ERROR("Error! addr ioremap failed!\n");
-+ return HI_FAILURE;
++ hi_log_error("Error! addr ioremap failed!\n");
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ HAL_CIPHER_READ_REG(sys_addr, &crg_value);
-+ crg_value |= 0x01;/* reset */
-+ crg_value |= 0x02; /* set the bit 0, clock opened */
-+ HAL_CIPHER_WRITE_REG(sys_addr, crg_value);
++ hal_cipher_read_reg(sys_addr, &crg_value);
++ crg_value |= 0x01; /* reset */
++ crg_value |= 0x02; /* set the bit 0, clock opened */
++ hal_cipher_write_reg(sys_addr, crg_value);
+
-+ /* clock select and cancel reset 0x30100*/
-+ crg_value &= (~0x01); /* cancel reset */
-+ crg_value |= 0x02; /* set the bit 0, clock opened */
-+ HAL_CIPHER_WRITE_REG(sys_addr, crg_value);
++ /* clock select and cancel reset 0x30100. */
++ crg_value &= (~0x01); /* cancel reset. */
++ crg_value |= 0x02; /* set the bit 0, clock opened */
++ hal_cipher_write_reg(sys_addr, crg_value);
+
+ crypto_iounmap(sys_addr, 0x100);
+
-+ efuse_otp_reg_base = crypto_ioremap_nocache(ENFUSE_REG_BASE_ADDR_PHY, 0x100);
-+ if (efuse_otp_reg_base == HI_NULL) {
-+ HI_LOG_ERROR("ERROR: osal_ioremap_nocache for EFUSE failed!!\n");
-+ return HI_FAILURE;
++ g_efuse_otp_reg_base = crypto_ioremap_nocache(ENFUSE_REG_BASE_ADDR_PHY, 0x100);
++ if (g_efuse_otp_reg_base == HI_NULL) {
++ hi_log_error("ERROR: osal_ioremap_nocache for EFUSE failed!!\n");
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
+ return HI_SUCCESS;
@@ -199818,23 +268794,21 @@ index 0000000..9e0bbee
+hi_s32 hal_efuse_wait_write_key(hi_void)
+{
+ cipher_kd_sta efuse_sta;
-+ hi_u32 ul_start_time = 0;
-+ hi_u32 ul_last_time = 0;
-+ hi_u32 ul_dura_time = 0;
++ hi_u32 ul_start_time, ul_last_time, ul_dura_time;
+
+ /* wait for hash_rdy */
+ ul_start_time = osal_get_tickcount();
+ while (1) {
-+ HAL_CIPHER_READ_REG(CIPHER_KD_STA, &efuse_sta.u32);
++ hal_cipher_read_reg(CIPHER_KD_STA, &efuse_sta.u32);
+ if (efuse_sta.bits.key_wt_finish == 1) {
+ break;
+ }
+
+ ul_last_time = osal_get_tickcount();
+ ul_dura_time = ul_last_time - ul_start_time;
-+ if (ul_dura_time >= KD_TIME_OUT ) {
-+ HI_LOG_ERROR("Error! efuse write key time out!\n");
-+ return HI_FAILURE;
++ if (ul_dura_time >= KD_TIME_OUT) {
++ hi_log_error("Error! efuse write key time out!\n");
++ return HI_ERR_CIPHER_TIMEOUT;
+ }
+
+ osal_msleep(1);
@@ -199845,23 +268819,21 @@ index 0000000..9e0bbee
+hi_s32 hal_efuse_wait_cipher_load_key(hi_void)
+{
+ cipher_kd_sta efuse_sta;
-+ hi_u32 ul_start_time = 0;
-+ hi_u32 ul_last_time = 0;
-+ hi_u32 ul_dura_time = 0;
++ hi_u32 ul_start_time, ul_last_time, ul_dura_time;
+
+ ul_start_time = osal_get_tickcount();
+
+ while (1) {
-+ HAL_CIPHER_READ_REG(CIPHER_KD_STA, &efuse_sta.u32);
++ hal_cipher_read_reg(CIPHER_KD_STA, &efuse_sta.u32);
+ if (efuse_sta.bits.cipher_kl_finish == 1) {
+ break;
+ }
+
+ ul_last_time = osal_get_tickcount();
+ ul_dura_time = (ul_last_time - ul_start_time);
-+ if (ul_dura_time >= KD_TIME_OUT ) {
-+ HI_LOG_ERROR("Error! efuse load key time out!\n");
-+ return HI_FAILURE;
++ if (ul_dura_time >= KD_TIME_OUT) {
++ hi_log_error("Error! efuse load key time out!\n");
++ return HI_ERR_CIPHER_TIMEOUT;
+ }
+ osal_msleep(1);
+ }
@@ -199871,23 +268843,21 @@ index 0000000..9e0bbee
+hi_s32 hal_efuse_wait_hash_load_key(hi_void)
+{
+ cipher_kd_sta efuse_sta;
-+ hi_u32 ul_start_time = 0;
-+ hi_u32 ul_last_time = 0;
-+ hi_u32 ul_dura_time = 0;
++ hi_u32 ul_start_time, ul_last_time, ul_dura_time;
+
+ ul_start_time = osal_get_tickcount();
+
+ while (1) {
-+ HAL_CIPHER_READ_REG(CIPHER_KD_STA, &efuse_sta.u32);
++ hal_cipher_read_reg(CIPHER_KD_STA, &efuse_sta.u32);
+ if (efuse_sta.bits.hash_key_read_busy == 0) {
+ break;
+ }
+
+ ul_last_time = osal_get_tickcount();
+ ul_dura_time = (ul_last_time - ul_start_time);
-+ if (ul_dura_time >= KD_TIME_OUT ) {
-+ HI_LOG_ERROR("Error! efuse load key out!\n");
-+ return HI_FAILURE;
++ if (ul_dura_time >= KD_TIME_OUT) {
++ hi_log_error("Error! efuse load key out!\n");
++ return HI_ERR_CIPHER_TIMEOUT;
+ }
+ osal_msleep(1);
+ }
@@ -199897,23 +268867,21 @@ index 0000000..9e0bbee
+hi_s32 hal_efuse_wait_ready(hi_void)
+{
+ cipher_kd_sta efuse_sta;
-+ hi_u32 ul_start_time = 0;
-+ hi_u32 ul_last_time = 0;
-+ hi_u32 ul_dura_time = 0;
++ hi_u32 ul_start_time, ul_last_time, ul_dura_time;
+
+ ul_start_time = osal_get_tickcount();
+
+ while (1) {
-+ HAL_CIPHER_READ_REG(CIPHER_KD_STA, &efuse_sta.u32);
++ hal_cipher_read_reg(CIPHER_KD_STA, &efuse_sta.u32);
+ if (efuse_sta.bits.ctrl_rdy && (!efuse_sta.bits.ctrl_busy1) && (!efuse_sta.bits.ctrl_busy0)) {
+ break;
+ }
+
+ ul_last_time = osal_get_tickcount();
+ ul_dura_time = (ul_last_time - ul_start_time);
-+ if (ul_dura_time >= KD_TIME_OUT ) {
-+ HI_LOG_ERROR("Error! efuse load key out!\n");
-+ return HI_FAILURE;
++ if (ul_dura_time >= KD_TIME_OUT) {
++ hi_log_error("Error! efuse load key out!\n");
++ return HI_ERR_CIPHER_TIMEOUT;
+ }
+ osal_msleep(1);
+ }
@@ -199924,126 +268892,140 @@ index 0000000..9e0bbee
+{
+ cipher_kd_sta efuse_sta;
+
-+ HAL_CIPHER_READ_REG(CIPHER_KD_STA, &efuse_sta.u32);
++ hal_cipher_read_reg(CIPHER_KD_STA, &efuse_sta.u32);
+ return efuse_sta.bits.key_wt_error;
+}
+
+hi_s32 hal_efuse_write_key(hi_u32 *p_key, hi_u32 opt_id)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 kd_ctl_mode = 0;
++ hi_s32 ret;
++ hi_u32 kd_ctl_mode;
+
-+ if (is_efuse_busy_flag != HI_FALSE) {
-+ return HI_FAILURE;
++ if (g_is_efuse_busy_flag != HI_FALSE) {
++ return HI_ERR_CIPHER_BUSY;
+ }
+
-+ is_efuse_busy_flag = HI_TRUE;
-+ kd_ctl_mode = KD_CTL_MODE_OPT_KEY_ADDR(opt_id) | KD_CTL_MODE_OPT_KD | KD_CTL_MODE_START;
++ g_is_efuse_busy_flag = HI_TRUE;
++ kd_ctl_mode = kd_ctl_mode_opt_key_addr(opt_id) | KD_CTL_MODE_OPT_KD | KD_CTL_MODE_START;
+
-+ HAL_CIPHER_WRITE_REG(CIPHER_KD_WKEY0, *p_key);
-+ HAL_CIPHER_WRITE_REG(CIPHER_KD_WKEY1, *(p_key + 1));
-+ HAL_CIPHER_WRITE_REG(CIPHER_KD_WKEY2, *(p_key + 2));
-+ HAL_CIPHER_WRITE_REG(CIPHER_KD_WKEY3, *(p_key + 3));
++ hal_cipher_write_reg(CIPHER_KD_WKEY0, *p_key);
++ hal_cipher_write_reg(CIPHER_KD_WKEY1, *(p_key + WORD_IDX_1));
++ hal_cipher_write_reg(CIPHER_KD_WKEY2, *(p_key + WORD_IDX_2));
++ hal_cipher_write_reg(CIPHER_KD_WKEY3, *(p_key + WORD_IDX_3));
+
-+ hal_efuse_wait_ready();
++ ret = hal_efuse_wait_ready();
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(hal_efuse_wait_ready, ret);
++ g_is_efuse_busy_flag = HI_FALSE;
++ return ret;
++ }
+
-+ HAL_CIPHER_WRITE_REG(CIPHER_KD_CTRL, kd_ctl_mode);
++ hal_cipher_write_reg(CIPHER_KD_CTRL, kd_ctl_mode);
+
+ ret = hal_efuse_wait_write_key();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(hal_efuse_wait_write_key, ret);
-+ is_efuse_busy_flag = HI_FALSE;
++ hi_log_print_func_err(hal_efuse_wait_write_key, ret);
++ g_is_efuse_busy_flag = HI_FALSE;
+ return ret;
+ }
+
+ ret = hal_efuse_get_err_stat()
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("efuse key is already write.\n");
-+ HI_LOG_PRINT_FUNC_ERR(hal_efuse_get_err_stat, ret);
-+ is_efuse_busy_flag = HI_FALSE;
++ hi_log_error("efuse key is already write.\n");
++ hi_log_print_func_err(hal_efuse_get_err_stat, ret);
++ g_is_efuse_busy_flag = HI_FALSE;
+ return ret;
+ }
+
-+ is_efuse_busy_flag = HI_FALSE;
++ g_is_efuse_busy_flag = HI_FALSE;
+ return HI_SUCCESS;
+}
+
+hi_s32 hal_efuse_otp_load_cipher_key(hi_u32 chn_id, hi_u32 opt_id)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 kd_ctl_mode = 0;
++ hi_s32 ret;
++ hi_u32 kd_ctl_mode;
+
-+ if (is_efuse_busy_flag != HI_FALSE) {
-+ return HI_FAILURE;
++ if (g_is_efuse_busy_flag != HI_FALSE) {
++ return HI_ERR_CIPHER_BUSY;
+ }
+
-+ is_efuse_busy_flag = HI_TRUE;
++ g_is_efuse_busy_flag = HI_TRUE;
+
-+ kd_ctl_mode = (KD_CTL_MODE_CIPHER_KEY_ADDR(chn_id) \
-+ | KD_CTL_MODE_OPT_KEY_ADDR(opt_id) \
-+ | KD_CTL_MODE_CIPHER_KL | KD_CTL_MODE_START);
++ kd_ctl_mode = (kd_ctl_mode_cipher_key_addr(chn_id) | kd_ctl_mode_opt_key_addr(opt_id) | \
++ KD_CTL_MODE_CIPHER_KL | KD_CTL_MODE_START);
+
-+ hal_efuse_wait_ready();
-+ HAL_CIPHER_WRITE_REG(CIPHER_KD_CTRL, kd_ctl_mode);
-+ ret = hal_efuse_wait_cipher_load_key();
++ ret = hal_efuse_wait_ready();
+ if (ret != HI_SUCCESS) {
-+ is_efuse_busy_flag = HI_FALSE;
-+ HI_LOG_PRINT_FUNC_ERR(hal_efuse_wait_cipher_load_key, ret);
++ hi_log_print_func_err(hal_efuse_wait_ready, ret);
++ g_is_efuse_busy_flag = HI_FALSE;
+ return ret;
+ }
+
-+ is_efuse_busy_flag = HI_FALSE;
++ hal_cipher_write_reg(CIPHER_KD_CTRL, kd_ctl_mode);
++ ret = hal_efuse_wait_cipher_load_key();
++ if (ret != HI_SUCCESS) {
++ g_is_efuse_busy_flag = HI_FALSE;
++ hi_log_print_func_err(hal_efuse_wait_cipher_load_key, ret);
++ return ret;
++ }
++
++ g_is_efuse_busy_flag = HI_FALSE;
+ return HI_SUCCESS;
+}
+
+hi_s32 hal_efuse_load_hash_key(hi_u32 opt_id)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 kd_ctl_mode = 0;
++ hi_s32 ret;
++ hi_u32 kd_ctl_mode;
+
-+ if (is_efuse_busy_flag)
-+ { return HI_FAILURE; }
++ if (g_is_efuse_busy_flag == HI_TRUE) {
++ return HI_ERR_CIPHER_BUSY;
++ }
+
-+ is_efuse_busy_flag = HI_TRUE;
++ g_is_efuse_busy_flag = HI_TRUE;
+
-+ kd_ctl_mode = (KD_CTL_MODE_OPT_KEY_ADDR(opt_id) | KD_CTL_MODE_HASH_KL | KD_CTL_MODE_START);
-+ hal_efuse_wait_ready();
-+ HAL_CIPHER_WRITE_REG(CIPHER_KD_CTRL, kd_ctl_mode);
-+ ret = hal_efuse_wait_hash_load_key();
++ kd_ctl_mode = (kd_ctl_mode_opt_key_addr(opt_id) | KD_CTL_MODE_HASH_KL | KD_CTL_MODE_START);
++ ret = hal_efuse_wait_ready();
+ if (ret != HI_SUCCESS) {
-+ is_efuse_busy_flag = HI_FALSE;
-+ HI_LOG_PRINT_FUNC_ERR(hal_efuse_wait_hash_load_key, ret);
++ hi_log_print_func_err(hal_efuse_wait_ready, ret);
++ g_is_efuse_busy_flag = HI_FALSE;
+ return ret;
+ }
+
-+ is_efuse_busy_flag = HI_FALSE;
++ hal_cipher_write_reg(CIPHER_KD_CTRL, kd_ctl_mode);
++ ret = hal_efuse_wait_hash_load_key();
++ if (ret != HI_SUCCESS) {
++ g_is_efuse_busy_flag = HI_FALSE;
++ hi_log_print_func_err(hal_efuse_wait_hash_load_key, ret);
++ return ret;
++ }
++
++ g_is_efuse_busy_flag = HI_FALSE;
+ return HI_SUCCESS;
+}
++
++hi_void hal_efuse_otp_set_reg_base(hi_u8 *reg_base)
++{
++ g_efuse_otp_reg_base = reg_base;
++}
++
++hi_u8 *hal_efuse_otp_get_reg_base(hi_void)
++{
++ return g_efuse_otp_reg_base;
++}
+#endif
-+
-+
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_efuse.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_efuse.h
new file mode 100644
-index 0000000..19c5f31
+index 0000000..61ca282
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_efuse.h
-@@ -0,0 +1,36 @@
+@@ -0,0 +1,27 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for hal efuse.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef _HAL_EFUSE_H_
@@ -200051,41 +269033,287 @@ index 0000000..19c5f31
+
+#include "hi_types.h"
+
-+#define HAL_CIPHER_READ_REG(addr, result) (*(result) = *(volatile unsigned int *)(hi_uintptr_t)(addr))
-+#define HAL_CIPHER_WRITE_REG(addr,result) (*(volatile unsigned int *)(hi_uintptr_t)(addr) = (result))
++#define hal_cipher_read_reg(addr, result) (*(result) = *(volatile unsigned int *)(hi_uintptr_t)(addr))
++#define hal_cipher_write_reg(addr, result) (*(volatile unsigned int *)(hi_uintptr_t)(addr) = (result))
+
-+#define HAL_SET_BIT(src, bit) ((src) |= (1<<bit))
-+#define HAL_CLEAR_BIT(src,bit) ((src) &= ~(1<<bit))
++#define hal_set_bit(src, bit) ((src) |= (1 << (bit)))
++#define hal_clear_bit(src, bit) ((src) &= ~(1 << (bit)))
+
+hi_s32 hal_efuse_write_key(hi_u32 *p_key, hi_u32 opt_id);
+hi_s32 hal_efuse_otp_load_cipher_key(hi_u32 chn_id, hi_u32 opt_id);
+hi_s32 hal_efuse_load_hash_key(hi_u32 opt_id);
+hi_s32 hal_efuse_otp_init(hi_void);
++hi_void hal_efuse_otp_set_reg_base(hi_u8 *reg_base);
++hi_u8 *hal_efuse_otp_get_reg_base(hi_void);
+
+#endif
+
+diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_otp.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_otp.c
+new file mode 100644
+index 0000000..008abbc
+--- /dev/null
++++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_otp.c
+@@ -0,0 +1,163 @@
++/*
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for hal otp.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
++ */
++
++#include "hi_types.h"
++#include "drv_osal_lib.h"
++#include "hal_otp.h"
++
++#ifdef OTP_SUPPORT
++
++hi_u8 *g_efuse_otp_reg_base = HI_NULL;
++
++/* OTP init */
++hi_s32 hal_efuse_otp_init(hi_void)
++{
++ hi_u32 crg_value = 0;
++ hi_u32 *sys_addr = HI_NULL;
++
++ sys_addr = crypto_ioremap_nocache(REG_SYS_OTP_CLK_ADDR_PHY, 0x100);
++ if (sys_addr == HI_NULL) {
++ hi_log_error("ERROR: sys_addr ioremap with nocache failed!!\n");
++ return HI_ERR_CIPHER_FAILED_MEM;
++ }
++
++ hal_cipher_read_reg(sys_addr, &crg_value);
++#if defined(CHIP_TYPE_hi3559av100)
++ crg_value |= OTP_CRG_RESET_BIT; /* reset */
++ crg_value |= OTP_CRG_CLOCK_BIT; /* set the bit 0, clock opened */
++ hal_cipher_write_reg(sys_addr, crg_value);
++
++ /* clock select and cancel reset 0x30100. */
++ crg_value &= (~OTP_CRG_RESET_BIT); /* cancel reset */
++#endif
++ crg_value |= OTP_CRG_CLOCK_BIT; /* set the bit 0, clock opened */
++ hal_cipher_write_reg(sys_addr, crg_value);
++
++ crypto_iounmap(sys_addr, 0x100);
++
++ g_efuse_otp_reg_base = crypto_ioremap_nocache(OTP_REG_BASE_ADDR_PHY, 0x100);
++ if (g_efuse_otp_reg_base == HI_NULL) {
++ hi_log_error("ERROR: osal_ioremap_nocache for OTP failed!!\n");
++ return HI_ERR_CIPHER_FAILED_MEM;
++ }
++
++ return HI_SUCCESS;
++}
++
++hi_s32 hal_otp_wait_free(hi_void)
++{
++ hi_u32 time_out_cnt = 0;
++ hi_u32 reg_value = 0;
++
++ while (1) {
++ hal_cipher_read_reg(OTP_USER_CTRL_STA, ®_value);
++ if ((reg_value & 0x1) == 0) {
++ /* bit0:otp_op_busy 0:idle, 1:busy */
++ return HI_SUCCESS;
++ }
++
++ time_out_cnt++;
++ if (time_out_cnt >= OTP_WAIT_TIME_OUT) {
++ hi_log_error("Otp wait free time out!\n");
++ break;
++ }
++ }
++ return HI_ERR_CIPHER_TIMEOUT;
++}
++
++hi_s32 hal_otp_set_mode(otp_user_work_mode otp_mode)
++{
++ hi_u32 reg_value = otp_mode;
++
++ if (otp_mode >= OTP_UNKOOWN_MODE) {
++ hi_log_error("Mode Unknown!\n");
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ (hi_void)hal_cipher_write_reg(OTP_USER_WORK_MODE, reg_value);
++ return HI_SUCCESS;
++}
++
++hi_void hal_otp_op_start(hi_void)
++{
++ hi_u32 reg_value = OTP_OP_START_VAL;
++ (hi_void)hal_cipher_write_reg(OTP_USER_OP_START, reg_value);
++}
++
++hi_s32 hal_otp_wait_op_done(hi_void)
++{
++ hi_u32 time_out_cnt = 0;
++ hi_u32 reg_value = 0;
++
++ while (1) {
++ hal_cipher_read_reg(OTP_USER_CTRL_STA, ®_value);
++ if (reg_value & 0x2) {
++ return HI_SUCCESS;
++ }
++
++ time_out_cnt++;
++ if (time_out_cnt >= OTP_WAIT_TIME_OUT) {
++ hi_log_error("Otp wait op time out!\n");
++ break;
++ }
++ }
++ return HI_ERR_CIPHER_TIMEOUT;
++}
++
++hi_void hal_choose_otp_key(otp_user_key_index which_key)
++{
++ hi_u32 reg_value;
++
++ reg_value = which_key;
++ (hi_void)hal_cipher_write_reg(OTP_USER_KEY_INDEX, reg_value);
++}
++
++/* set otp key to klad */
++hi_s32 hal_efuse_otp_load_cipher_key(hi_u32 chn_id, hi_u32 opt_id)
++{
++ hi_s32 ret;
++
++ if (opt_id > OTP_USER_KEY3) {
++ opt_id = OTP_USER_KEY0;
++ }
++
++ ret = hal_otp_wait_free();
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(hal_otp_wait_free, ret);
++ return ret;
++ }
++
++ hal_choose_otp_key(opt_id);
++
++ ret = hal_otp_set_mode(OTP_LOCK_CIPHER_KEY_MODE);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(hal_otp_set_mode, ret);
++ return ret;
++ }
++
++ hal_otp_op_start();
++
++ ret = hal_otp_wait_op_done();
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(hal_otp_wait_op_done, ret);
++ return ret;
++ }
++
++ return HI_SUCCESS;
++}
++
++hi_void hal_efuse_otp_set_reg_base(hi_u8 *reg_base)
++{
++ g_efuse_otp_reg_base = reg_base;
++}
++
++hi_u8 *hal_efuse_otp_get_reg_base(hi_void)
++{
++ return g_efuse_otp_reg_base;
++}
++#endif
++
+diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_otp.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_otp.h
+new file mode 100644
+index 0000000..f272f67
+--- /dev/null
++++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hal_otp.h
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for hal otp.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
++ */
++
++#ifndef __HAL_OTP_H__
++#define __HAL_OTP_H__
++
++#include "hi_types.h"
++#include "hal_efuse.h"
++
++#define OTP_USER_IF_BASE g_efuse_otp_reg_base
++#define OTP_USER_WORK_MODE (OTP_USER_IF_BASE + 0x0000)
++#define OTP_USER_OP_START (OTP_USER_IF_BASE + 0x0004)
++#define OTP_USER_KEY_INDEX (OTP_USER_IF_BASE + 0x0008)
++#define OTP_USER_KEY_DATA0 (OTP_USER_IF_BASE + 0x000c)
++#define OTP_USER_KEY_DATA1 (OTP_USER_IF_BASE + 0x0010)
++#define OTP_USER_KEY_DATA2 (OTP_USER_IF_BASE + 0x0014)
++#define OTP_USER_KEY_DATA3 (OTP_USER_IF_BASE + 0x0018)
++#define OTP_USER_KEY_DATA4 (OTP_USER_IF_BASE + 0x001c)
++#define OTP_USER_KEY_DATA5 (OTP_USER_IF_BASE + 0x0020)
++#define OTP_USER_KEY_DATA6 (OTP_USER_IF_BASE + 0x0024)
++#define OTP_USER_KEY_DATA7 (OTP_USER_IF_BASE + 0x0028)
++#define OTP_USER_KEY_DATA8 (OTP_USER_IF_BASE + 0x002c)
++#define OTP_USER_FLAG_VALUE (OTP_USER_IF_BASE + 0x0030)
++#define OTP_USER_FLAG_INDEX (OTP_USER_IF_BASE + 0x0034)
++#define OTP_USER_REV_ADDR (OTP_USER_IF_BASE + 0x0038)
++#define OTP_USER_REV_WDATA (OTP_USER_IF_BASE + 0x003c)
++#define OTP_USER_REV_RDATA (OTP_USER_IF_BASE + 0x0040)
++#define OTP_USER_LOCK_STA0 (OTP_USER_IF_BASE + 0x0044)
++#define OTP_USER_LOCK_STA1 (OTP_USER_IF_BASE + 0x0048)
++#define OTP_USER_CTRL_STA (OTP_USER_IF_BASE + 0x004c)
++
++#define OTP_WAIT_TIME_OUT 10000
++#define OTP_OP_START_VAL 0x1acce551
++
++typedef enum {
++ OTP_USER_LOCK_STA0_TYPE,
++ OTP_USER_LOCK_STA1_TYPE,
++ OTP_USER_LOCK_UNKNOWN_STA,
++} otp_lock_sta_type;
++
++typedef enum {
++ OTP_READ_LOCK_STA_MODE,
++ OTP_LOCK_CIPHER_KEY_MODE,
++ OTP_WRITE_KEY_ID_OR_PASSWD_MODE,
++ OTP_KEY_ID_OR_PASSWD_CRC_MODE,
++ OTP_SET_FLAG_ENABLE_MODE,
++ OTP_WRITE_USER_ROOM_MODE,
++ OTP_Read_USER_ROOM_MODE,
++ OTP_UNKOOWN_MODE,
++} otp_user_work_mode;
++
++typedef enum {
++ OTP_USER_KEY0,
++ OTP_USER_KEY1,
++ OTP_USER_KEY2,
++ OTP_USER_KEY3,
++ OTP_USER_KEY_JTAG_PW_ID,
++ OTP_USER_KEY_JTAG_PW,
++ OTP_USER_KEY_ROOTKEY,
++ OTP_USER_KEY_UNKNOWN,
++} otp_user_key_index;
++
++typedef enum {
++ OTP_KEY_LENGTH_64BIT,
++ OTP_KEY_LENGTH_128BIT,
++ OTP_KEY_LENGTH_256BIT,
++ OTP_KEY_LENGTH_UNSUPPORT,
++} otp_user_key_length;
++
++hi_s32 hal_efuse_otp_init(hi_void);
++hi_s32 hal_efuse_otp_load_cipher_key(hi_u32 chn_id, hi_u32 opt_id);
++hi_void hal_efuse_otp_set_reg_base(hi_u8 *reg_base);
++hi_u8 *hal_efuse_otp_get_reg_base(hi_void);
++unsigned short calculate_crc16 (const unsigned char *data_array_ptr, unsigned long data_array_length);
++
++#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hi_drv_compat.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hi_drv_compat.c
new file mode 100644
-index 0000000..886527e
+index 0000000..1557157
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hi_drv_compat.c
-@@ -0,0 +1,68 @@
+@@ -0,0 +1,57 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for cipher compat.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
@@ -200094,24 +269322,24 @@ index 0000000..886527e
+
+hi_s32 klad_load_hard_key(hi_u32 handle, hi_u32 ca_type, hi_u8 *key, hi_u32 key_len)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ ret = drv_cipher_klad_load_key(handle, ca_type, HI_CIPHER_KLAD_TARGET_AES, key, key_len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_cipher_klad_load_key, ret);
++ hi_log_print_func_err(drv_cipher_klad_load_key, ret);
+ return ret;
+ }
+
+ return HI_SUCCESS;
+}
+
-+hi_s32 klad_encrypt_key(hi_u32 keysel, hi_u32 target, hi_u32 clear[4], hi_u32 encrypt[4])
++hi_s32 klad_encrypt_key(hi_u32 keysel, hi_u32 target, hi_u8 *clear, hi_u8 *encrypt, hi_u32 key_len)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ ret = drv_cipher_klad_encrypt_key(keysel, target, clear, encrypt);
++ ret = drv_cipher_klad_encrypt_key(keysel, target, clear, encrypt, key_len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_cipher_klad_encrypt_key, ret);
++ hi_log_print_func_err(drv_cipher_klad_encrypt_key, ret);
+ return ret;
+ }
+
@@ -200120,11 +269348,11 @@ index 0000000..886527e
+
+hi_s32 hi_drv_compat_init(void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ ret = drv_cipher_klad_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_cipher_klad_init, ret);
++ hi_log_print_func_err(drv_cipher_klad_init, ret);
+ return ret;
+ }
+
@@ -200140,26 +269368,15 @@ index 0000000..886527e
+
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hi_drv_compat.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hi_drv_compat.h
new file mode 100644
-index 0000000..6d381ff
+index 0000000..fe5d4a8
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/hi_drv_compat.h
-@@ -0,0 +1,28 @@
+@@ -0,0 +1,17 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file cipher drv compat.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef _HI_DRV_CPMPAT_H_
@@ -200168,7 +269385,7 @@ index 0000000..6d381ff
+hi_s32 hi_drv_compat_init(hi_void);
+hi_s32 hi_drv_compat_deinit(hi_void);
+hi_s32 klad_load_hard_key(hi_u32 handle, hi_u32 ca_type, hi_u8 *key, hi_u32 key_len);
-+hi_s32 klad_encrypt_key(hi_u32 keysel, hi_u32 target, hi_u32 clear[4], hi_u32 encrypt[4]);
++hi_s32 klad_encrypt_key(hi_u32 keysel, hi_u32 target, hi_u8 *clear, hi_u8 *encrypt, hi_u32 key_len);
+
+#endif
+
@@ -200219,26 +269436,15 @@ index 0000000..426170c
\ No newline at end of file
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v100.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v100.c
new file mode 100644
-index 0000000..ec555cd
+index 0000000..10fcf69
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v100.c
-@@ -0,0 +1,375 @@
+@@ -0,0 +1,327 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv hash v100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_hash_v100.h"
@@ -200246,129 +269452,98 @@ index 0000000..ec555cd
+
+#ifdef CHIP_HASH_VER_V100
+
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!-- [hash] */
++/* ************************** Structure Definition *************************** */
++/* hash 256 result size in word */
++#define HASH256_RESULT_SIZE_IN_WORD 8
+
-+/*! \hash 256 result size in word */
-+#define HASH256_RESULT_SIZE_IN_WORD (8)
++/* Define the rec read bit mask */
++#define HASH_READ_MASK_REC 0x08
+
-+/*! Define the rec read bit mask */
-+#define HASH_READ_MASK_REC (0x08)
++/* Define the dma read bit mask */
++#define HASH_READ_MASK_DMA 0x02
+
-+/*! Define the dma read bit mask */
-+#define HASH_READ_MASK_DMA (0x02)
++/* Define the hash read bit mask */
++#define HASH_READ_MASK_HASH 0x01
+
-+/*! Define the hash read bit mask */
-+#define HASH_READ_MASK_HASH (0x01)
-+
-+/*! hash is busy ot not */
++/* hash is busy ot not */
+#ifdef MHASH_NONSUPPORT
-+static hi_u32 hash_busy = HI_FALSE;
++static hi_u32 g_hash_busy = HI_FALSE;
+#endif
+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
-+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!--[hash]*/
-+
++/* ****************************** API Declaration **************************** */
+hi_s32 drv_hash_init(void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_disable(CRYPTO_MODULE_ID_HASH);
+ module_enable(CRYPTO_MODULE_ID_HASH);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 drv_hash_deinit(void)
+{
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_enter();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+void drv_hash_resume(void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_enable(CRYPTO_MODULE_ID_HASH);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
+void drv_hash_suspend(void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_disable(CRYPTO_MODULE_ID_HASH);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
+/* wait hash ready */
+static hi_s32 drv_hash_wait_ready(hi_u32 bitmask)
+{
-+ hi_u32 i = 0;
++ hi_u32 i;
+ hash_status ready;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* wait ready */
+ for (i = 0; i < CRYPTO_TIME_OUT; i++) {
-+ ready.u32 = HASH_READ(REG_STATUS);
++ ready.u32 = hash_read(REG_STATUS);
+ if (ready.u32 & bitmask) {
+ break;
+ }
+ if (i <= MS_TO_US) {
+ crypto_udelay(1); /* short waitting for 1000 us */
+ } else {
-+ crypto_msleep(1); /* long waitting for 5000 ms*/
++ crypto_msleep(1); /* long waitting for 5000 ms. */
+ }
+ }
+ if (i >= CRYPTO_TIME_OUT) {
-+ HI_LOG_ERROR("error, hash wait done timeout\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_TIMEOUT);
++ hi_log_error("error, hash wait done timeout\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
+ return HI_ERR_CIPHER_TIMEOUT;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_hash_config(hi_u32 chn_num, hash_mode mode, hi_u32 state[HASH_RESULT_MAX_SIZE_IN_WORD])
++static hi_s32 drv_hash_cfg_hash_ctrl(hash_mode mode)
+{
+ hash_ctrl ctrl;
-+ hi_s32 ret = HI_FAILURE;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ HI_LOG_CHECK_PARAM(state == HI_NULL);
-+
-+ CRYPTO_UNUSED(chn_num);
-+
-+#ifdef MHASH_NONSUPPORT
-+ if (HI_TRUE == hash_busy) {
-+ /* the hash already starting, here just return success */
-+ HI_LOG_FUNC_EXIT();
-+ return HI_SUCCESS;
-+ }
-+ hash_busy = HI_TRUE;
-+#endif
-+
-+ /* wait ready */
-+ ret = drv_hash_wait_ready(HASH_READ_MASK_HASH);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_wait_ready, ret);
-+ return ret;
-+ }
-+
-+ ctrl.u32 = HASH_READ(REG_CTRL);
++ ctrl.u32 = hash_read(REG_CTRL);
+
+ /* only support sha1 and sha256 */
+ if (mode == HASH_MODE_SHA1) {
@@ -200376,69 +269551,118 @@ index 0000000..ec555cd
+ } else if ((mode == HASH_MODE_SHA256) || (mode == HASH_MODE_SHA224)) {
+ ctrl.bits.sha_sel = 0x01; /* SHA256 */
+ } else {
-+ HI_LOG_ERROR("error, nonsupport hash mode %d\n", mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("error, nonsupport hash mode %d\n", mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ /* control configure */
-+ ctrl.bits.read_ctrl = 0; /* 0:read by DMA, 1: read by CPU */
-+ ctrl.bits.hmac_flag = 0; /* 0: raw hash, 1: hmac */
-+ ctrl.bits.hardkey_sel = 0;/* 0: cpu key, 1: hard key*/
-+ ctrl.bits.small_end_en = 1;/* 0: big, 1: little */
-+ ctrl.bits.sha_init_update_en = 1;/* initial hash value from CPU */
++ ctrl.bits.read_ctrl = 0; /* 0:read by DMA, 1: read by CPU */
++ ctrl.bits.hmac_flag = 0; /* 0:raw hash, 1: hmac */
++ ctrl.bits.hardkey_sel = 0; /* 0:cpu key, 1: hard key. */
++ ctrl.bits.small_end_en = 1; /* 0:big, 1: little */
++ ctrl.bits.sha_init_update_en = 1; /* initial hash value from CPU */
+
-+ HASH_WRITE(REG_CTRL, ctrl.u32);
-+ HI_LOG_INFO("REG_CTRL: 0x%x\n", ctrl.u32);
++ hash_write(REG_CTRL, ctrl.u32);
++ hi_log_info("REG_CTRL: 0x%x\n", ctrl.u32);
++ return HI_SUCCESS;
++}
+
+#ifdef MHASH_NONSUPPORT
-+ {
-+ sha_start start;
++/*
++ * MHASH_NONSUPPORT is a very old version of the logic, only the old version of the chip is supported. It requires the
++ * initial length of the HASH calculation to know the total length of the HASH data. In fact, in order to support
++ * multi-segment HASH calculations, it is impossible to know the total length of the HASH data at this time.
++ * Therefore, the maximum length value of 0xFFFFFFFF is configured in the HASH initialization node, and a HASH soft
++ * reset is performed every time until all HASH data and padding data are calculated, and then take out the HASH
++ * calculation result, and reset HASH logic again.
++ */
++static hi_void drv_hash_mhash_non_support_sha_start(hi_void)
++{
++ sha_start start;
+
-+ /* logic don't support config init value of hash
-+ * here must set it to max vaule
-+ * then reset hash after compute finished
-+ */
-+ HASH_WRITE(REG_TOTALLEN_LOW, 0xFFFFFFFF);
-+ HASH_WRITE(REG_TOTALLEN_HIGH, 0x00);
++ /* logic don't support config init value of hash
++ * here must set it to max vaule
++ * then reset hash after compute finished
++ */
++ hash_write(REG_TOTALLEN_LOW, 0xFFFFFFFF);
++ hash_write(REG_TOTALLEN_HIGH, 0x00);
+
-+ /* ready to working,
-+ * the hardware still be idle until write the reg of REG_DMA_LEN
-+ * so must start the hardware before write DMA addr and length.
-+ */
-+ start.u32 = HASH_READ(REG_START);
-+ start.bits.sha_start = 0x01;
-+ HASH_WRITE(REG_START, start.u32);
-+ HI_LOG_INFO("REG_START: 0x%x\n", start.u32);
-+
-+ hash_busy = HI_TRUE;
-+ }
-+#else
-+ {
-+ hi_u32 i = 0;
-+
-+ /* write hash initial value */
-+ for (i = 0; i < HASH256_RESULT_SIZE_IN_WORD; i++) {
-+ HASH_WRITE(REG_INIT1_UPDATE + i * 4, CPU_TO_BE32(state[i]));
-+ HI_LOG_DEBUG("Set hash: 0x%x\n", state[i]);
-+ }
-+ }
++ /* ready to working,
++ * the hardware still be idle until write the reg of REG_DMA_LEN
++ * so must start the hardware before write DMA addr and length.
++ */
++ start.u32 = hash_read(REG_START);
++ start.bits.sha_start = 0x01;
++ hash_write(REG_START, start.u32);
++ hi_log_info("REG_START: 0x%x\n", start.u32);
++}
+#endif
-+ HI_LOG_FUNC_EXIT();
-+ return HI_SUCCESS;
+
++static hi_void drv_hash_cfg_initial_value(hi_u32 *state, hi_u32 state_len_in_word)
++{
++ hi_u32 i;
++
++ /* write hash initial value */
++ for (i = 0; i < state_len_in_word; i++) {
++ hash_write(REG_INIT1_UPDATE + i * WORD_WIDTH, crypto_cpu_to_be32(state[i]));
++ hi_log_debug("Set hash: 0x%x\n", state[i]);
++ }
++}
++
++hi_s32 drv_hash_cfg(hi_u32 chn_num, hash_mode mode, hi_u32 state[HASH_RESULT_MAX_SIZE_IN_WORD])
++{
++ hash_ctrl ctrl;
++ hi_s32 ret;
++
++ hi_log_func_enter();
++
++ hi_log_chk_param_return(state == HI_NULL);
++
++ crypto_unused(chn_num);
++
++#ifdef MHASH_NONSUPPORT
++ if (g_hash_busy == HI_TRUE) {
++ /* the hash already starting, here just return success */
++ hi_log_func_exit();
++ return HI_SUCCESS;
++ }
++ g_hash_busy = HI_TRUE;
++#endif
++
++ /* wait ready */
++ ret = drv_hash_wait_ready(HASH_READ_MASK_HASH);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_hash_wait_ready, ret);
++ return ret;
++ }
++
++ ret = drv_hash_cfg_hash_ctrl(mode);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_hash_cfg_hash_ctrl, ret);
++ return ret;
++ }
++
++#ifdef MHASH_NONSUPPORT
++ drv_hash_mhash_non_support_sha_start();
++ g_hash_busy = HI_TRUE;
++#else
++ drv_hash_cfg_initial_value(state, HASH_RESULT_MAX_SIZE_IN_WORD);
++#endif
++ hi_log_func_exit();
++ return HI_SUCCESS;
+}
+
+hi_s32 drv_hash_start(hi_u32 chn_num, crypto_mem *mem, hi_u32 length)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* buffer addr and size must align with word */
-+ HI_LOG_CHECK_PARAM((length & 0x03) != 0);
++ hi_log_chk_param_return((length & 0x03) != 0);
+
-+ HI_LOG_DEBUG("MMZ phy 0x%x, length 0x%x\n", ADDR_L32(mem->mmz_addr), length);
++ hi_log_debug("MMZ phy 0x%x, length 0x%x\n", addr_l32(mem->mmz_addr), length);
+
-+ CRYPTO_UNUSED(chn_num);
++ crypto_unused(chn_num);
+
+#ifndef MHASH_NONSUPPORT
+ {
@@ -200449,140 +269673,87 @@ index 0000000..ec555cd
+ * here just set the total length to buf_size each hash calculation.
+ * then we can release the hash hardware after each hash calculation.
+ */
-+ HASH_WRITE(REG_TOTALLEN_LOW, length);
++ hash_write(REG_TOTALLEN_LOW, length);
+
+ /* max length of msg is 2^32, the high 32bit of length always be zero */
-+ HASH_WRITE(REG_TOTALLEN_HIGH, 0x00);
++ hash_write(REG_TOTALLEN_HIGH, 0x00);
+
+ /* ready to working,
+ * the hardware still be idle until write the reg of REG_DMA_LEN
+ * so must start the hardware before write DMA addr and length.
+ */
-+ start.u32 = HASH_READ(REG_START);
++ start.u32 = hash_read(REG_START);
+ start.bits.sha_start = 0x01;
-+ HASH_WRITE(REG_START, start.u32);
-+ HI_LOG_INFO("REG_START: 0x%x\n", start.u32);
++ hash_write(REG_START, start.u32);
++ hi_log_info("REG_START: 0x%x\n", start.u32);
+ }
+#endif
+
+ /* DMA address and length, at once write the reg of REG_DMA_LEN,
+ * the hardware start working immediately.
+ */
-+ HASH_WRITE(REG_DMA_START_ADDR, ADDR_L32(mem->mmz_addr));
-+ HASH_WRITE(REG_DMA_LEN, length);
-+ HI_LOG_INFO("Hash PHY: 0x%x, size 0x%x\n", ADDR_L32(mem->mmz_addr), length);
++ hash_write(REG_DMA_START_ADDR, addr_l32(mem->mmz_addr));
++ hash_write(REG_DMA_LEN, length);
++ hi_log_info("Hash PHY: 0x%x, size 0x%x\n", addr_l32(mem->mmz_addr), length);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 drv_hash_wait_done(hi_u32 chn_num, hi_u32 *state)
+{
-+ hi_u32 i = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_u32 i;
++ hi_s32 ret;
+ hash_status ready;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(state == HI_NULL);
++ hi_log_chk_param_return(state == HI_NULL);
+
-+ CRYPTO_UNUSED(chn_num);
++ crypto_unused(chn_num);
+
+ /* wait ready */
+ ret = drv_hash_wait_ready(HASH_READ_MASK_REC);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_wait_ready, ret);
++ hi_log_print_func_err(drv_hash_wait_ready, ret);
+ return ret;
+ }
+
+ /* check error code */
-+ ready.u32 = HASH_READ(REG_STATUS);
++ ready.u32 = hash_read(REG_STATUS);
+ if (ready.bits.len_err) {
-+ HI_LOG_ERROR("error, hash len err, chn=%d", chn_num);
++ hi_log_error("error, hash len err, chn=%d", chn_num);
+ return HI_ERR_CIPHER_OVERFLOW;
+ }
-+ HI_LOG_INFO("Status: 0x%x\n", ready.u32);
++ hi_log_info("Status: 0x%x\n", ready.u32);
+
+ /* read hash result */
+ for (i = 0; i < HASH256_RESULT_SIZE_IN_WORD; i++) {
-+ state[i] = HASH_READ(REG_SHA_OUT1 + i * 4);
-+ HI_LOG_INFO("state[%d] 0x%x\n", i, state[i]);
++ state[i] = hash_read(REG_SHA_OUT1 + i * WORD_WIDTH);
++ hi_log_info("state[%d] 0x%x\n", i, state[i]);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+void drv_hash_reset(hi_u32 chn_num)
+{
-+ CRYPTO_UNUSED(chn_num);
++ crypto_unused(chn_num);
+#ifdef MHASH_NONSUPPORT
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_disable(CRYPTO_MODULE_ID_HASH);
+ module_enable(CRYPTO_MODULE_ID_HASH);
-+ hash_busy = HI_FALSE;
++ g_hash_busy = HI_FALSE;
+
-+ HI_LOG_INFO("Hash reset ...\n");
++ hi_log_info("Hash reset ...\n");
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+#endif
+}
+
-+hi_s32 drv_hmac256_block(hi_u32 *din, hi_u32 *hamc)
-+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 i = 0;
-+ hash_ctrl ctrl;
-+
-+ HI_LOG_FUNC_ENTER();
-+
-+ /*1.set hmac padded message ByteLength*/
-+ HASH_WRITE(REG_TOTALLEN_LOW, 0x40);
-+ HASH_WRITE(REG_TOTALLEN_HIGH, 0x00);
-+
-+ /*2.set hash ctrl register*/
-+ ctrl.u32 = HASH_READ(REG_CTRL);
-+ ctrl.bits.read_ctrl = 1;
-+ ctrl.bits.sha_sel = 0x1;
-+ ctrl.bits.hmac_flag = 1;
-+ ctrl.bits.hardkey_sel = 0;
-+ ctrl.bits.small_end_en = 1;
-+ ctrl.bits.sha_init_update_en = 0;
-+ HASH_WRITE (REG_CTRL, ctrl.u32);
-+
-+ /*3.set start*/
-+ HASH_WRITE (REG_START, 0x01);
-+
-+ /*ready input data*/
-+ ret = drv_hash_wait_ready(HASH_READ_MASK_DMA);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_wait_ready, ret);
-+ return ret;
-+ }
-+
-+ /*4.set data_in*/
-+ for (i = 0; i < HASH_BLOCK_SIZE; i++) {
-+ HASH_WRITE(REG_DATA_IN, din[i]);
-+ }
-+
-+ ret = drv_hash_wait_ready(HASH_READ_MASK_HASH);
-+ if (ret != HI_SUCCESS) {
-+ return ret;
-+ }
-+
-+ /*5.hash ready*/
-+ ret = drv_hash_wait_done(HASH_HARD_CHANNEL, hamc);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_wait_done, ret);
-+ return ret;
-+ }
-+
-+ HI_LOG_FUNC_EXIT();
-+ return HI_SUCCESS;
-+}
-+
+void drv_hash_get_capacity(hash_capacity *capacity)
+{
+ crypto_memset(capacity, sizeof(hash_capacity), 0, sizeof(hash_capacity));
@@ -200595,74 +269766,57 @@ index 0000000..ec555cd
+#endif
+}
+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
-+#endif //End of CHIP_HASH_VER_V100
++#endif /* End of CHIP_HASH_VER_V100 */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v100.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v100.h
new file mode 100644
-index 0000000..bdee104
+index 0000000..c5b3ef9
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v100.h
-@@ -0,0 +1,107 @@
+@@ -0,0 +1,87 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv hash v100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
-+#ifndef _DRV_HASH_V1_H_
-+#define _DRV_HASH_V1_H_
++#ifndef _DRV_HASH_V100_H_
++#define _DRV_HASH_V100_H_
+
+#include "drv_osal_lib.h"
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup hash drivers*/
-+/** @{*/ /** <!-- [hash]*/
++/* Define the offset of reg */
++#define REG_TOTALLEN_LOW 0x00
++#define REG_TOTALLEN_HIGH 0x04
++#define REG_STATUS 0x08
++#define REG_CTRL 0x0C
++#define REG_START 0x10
++#define REG_DMA_START_ADDR 0x14
++#define REG_DMA_LEN 0x18
++#define REG_DATA_IN 0x1C
++#define REG_REC_LEN1 0x20
++#define REG_REC_LEN2 0x24
++#define REG_SHA_OUT1 0x30
++#define REG_SHA_OUT2 0x34
++#define REG_SHA_OUT3 0x38
++#define REG_SHA_OUT4 0x3C
++#define REG_SHA_OUT5 0x40
++#define REG_SHA_OUT6 0x44
++#define REG_SHA_OUT7 0x48
++#define REG_SHA_OUT8 0x4C
++#define REG_MCU_KEY0 0x70
++#define REG_MCU_KEY1 0x74
++#define REG_MCU_KEY2 0x78
++#define REG_MCU_KEY3 0x7C
++#define REG_KL_KEY0 0x80
++#define REG_KL_KEY1 0x84
++#define REG_KL_KEY2 0x88
++#define REG_KL_KEY3 0x8C
++#define REG_INIT1_UPDATE 0x90
+
-+/*! \Define the offset of reg */
-+#define REG_TOTALLEN_LOW (0x00)
-+#define REG_TOTALLEN_HIGH (0x04)
-+#define REG_STATUS (0x08)
-+#define REG_CTRL (0x0C)
-+#define REG_START (0x10)
-+#define REG_DMA_START_ADDR (0x14)
-+#define REG_DMA_LEN (0x18)
-+#define REG_DATA_IN (0x1C)
-+#define REG_REC_LEN1 (0x20)
-+#define REG_REC_LEN2 (0x24)
-+#define REG_SHA_OUT1 (0x30)
-+#define REG_SHA_OUT2 (0x34)
-+#define REG_SHA_OUT3 (0x38)
-+#define REG_SHA_OUT4 (0x3C)
-+#define REG_SHA_OUT5 (0x40)
-+#define REG_SHA_OUT6 (0x44)
-+#define REG_SHA_OUT7 (0x48)
-+#define REG_SHA_OUT8 (0x4C)
-+#define REG_MCU_KEY0 (0x70)
-+#define REG_MCU_KEY1 (0x74)
-+#define REG_MCU_KEY2 (0x78)
-+#define REG_MCU_KEY3 (0x7C)
-+#define REG_KL_KEY0 (0x80)
-+#define REG_KL_KEY1 (0x84)
-+#define REG_KL_KEY2 (0x88)
-+#define REG_KL_KEY3 (0x8C)
-+#define REG_INIT1_UPDATE (0x90)
-+
-+/*! \Define the union hash_status */
++/* Define the union hash_status */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 hash_rdy : 1 ; /* [0] */
+ hi_u32 dma_rdy : 1 ; /* [1] */
@@ -200673,14 +269827,13 @@ index 0000000..bdee104
+ hi_u32 reserved_1 : 2 ; /* [31..7] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} hash_status;
+
-+/*! \Define the union hash_ctrl */
++/* Define the union hash_ctrl */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 read_ctrl : 1 ; /* [0] */
+ hi_u32 sha_sel : 2 ; /* [2..1] */
@@ -200691,48 +269844,33 @@ index 0000000..bdee104
+ hi_u32 reserved_1 : 25 ; /* [31..7] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} hash_ctrl;
+
-+/*! \Define the union sha_start */
++/* Define the union sha_start */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 sha_start : 1 ; /* [0] */
+ hi_u32 reserved_1 : 30 ; /* [31..1] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} sha_start;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+#endif
++#endif /* End of _DRV_HASH_V100_H_ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v200.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v200.c
new file mode 100644
-index 0000000..b508b65
+index 0000000..d53c560
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v200.c
-@@ -0,0 +1,778 @@
+@@ -0,0 +1,783 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv hash v200.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_hash_v200.h"
@@ -200740,123 +269878,161 @@ index 0000000..b508b65
+
+#ifdef CHIP_HASH_VER_V200
+
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!-- [hash] */
++/* ************************** Structure Definition *************************** */
++/* hash in entry list size */
++#define HASH_NODE_SIZE 4096
+
-+/*! hash in entry list size */
-+#define HASH_NODE_SIZE (4096)
-+
-+/*! hash in entry list size */
++/* hash in entry list size */
+#define HASH_NODE_LIST_SIZE (HASH_NODE_SIZE * HASH_HARD_CHANNEL_CNT)
+
-+/*! hash node dpth */
-+#define HASH_MAX_DEPTH (127)
++/* hash node dpth */
++#define HASH_MAX_DEPTH 127
+
-+#define KLAD_KEY_USE_ERR 0x01
-+#define ALG_LEN_ERR 0x02
-+#define SMMU_PAGE_UNVLID 0x04
-+#define OUT_SMMU_PAGE_NOT_VALID 0x08
-+#define KLAD_KEY_WRITE_ERR 0x10
++#define KLAD_KEY_USE_ERR 0x01
++#define ALG_LEN_ERR 0x02
++#define SMMU_PAGE_UNVLID 0x04
++#define OUT_SMMU_PAGE_NOT_VALID 0x08
++#define KLAD_KEY_WRITE_ERR 0x10
+
-+/*! Define the flag of node */
++/* Define the flag of node */
+typedef enum {
-+ HASH_CTRL_NONE = 0x00, /*!< middle node */
-+ HASH_CTRL_HASH_IN_FIRST = 0x01, /*!< first node */
-+ HASH_CTRL_HASH_IN_LAST = 0x02, /*!< last node */
++ HASH_CTRL_NONE = 0x00, /* middle node */
++ HASH_CTRL_HASH_IN_FIRST = 0x01, /* first node */
++ HASH_CTRL_HASH_IN_LAST = 0x02, /* last node */
+ HASH_CTRL_COUNT,
+} HASH_CTRL_EN;
+
-+/*! spacc digest in entry struct which is defined by hardware, you can't change it */
++/* spacc digest in entry struct which is defined by hardware, you can't change it */
+struct hash_entry_in {
-+ hi_u32 spacc_cmd: 2; /*!< reserve */
-+ hi_u32 rev1: 6; /*!< reserve */
-+ hi_u32 hash_ctrl: 6; /*!< hash control flag*/
-+ hi_u32 rev2: 18; /*!< reserve */
-+ hi_u32 hash_start_addr; /*!< hash message address */
-+ hi_u32 hash_alg_length; /*!< hash message length */
-+ hi_u32 word1; /*!< reserve */
++ hi_u32 spacc_cmd: 2; /* reserve */
++ hi_u32 rev1: 6; /* reserve */
++ hi_u32 hash_ctrl: 6; /* hash control flag. */
++ hi_u32 rev2: 18; /* reserve */
++ hi_u32 hash_start_addr; /* hash message address */
++ hi_u32 hash_alg_length; /* hash message length */
++ hi_u32 word1; /* reserve */
+};
+
-+/*! Define the context of hash */
++/* Define the context of hash */
+typedef struct {
-+ hash_mode hash_alg; /*!< hash mode */
-+ struct hash_entry_in *entry_in; /*! spacc digest in entry struct */
-+ hi_u32 id_in; /*!< current hash nodes to be used */
-+ hi_u32 done; /*!< calculation finish flag*/
-+ crypto_queue_head queue; /*!< quene list */
++ hash_mode hash_alg; /* hash mode */
++ struct hash_entry_in *entry_in; /* spacc digest in entry struct */
++ hi_u32 id_in; /*!< current hash nodes to be used */
++ hi_u32 done; /* calculation finish flag. */
++ crypto_queue_head queue; /* quene list */
+} hash_hard_context;
+
-+/*! hash already initialize or not */
-+static hi_u32 hash_initialize = HI_FALSE;
++/* hash already initialize or not */
++static hi_u32 g_hash_initialize = HI_FALSE;
+
-+/*! dma memory of hash node list*/
-+static crypto_mem hash_dma;
++/* dma memory of hash node list. */
++static crypto_mem g_hash_dma;
+
-+/*! Channel of hash */
-+static channel_context hash_hard_channel[CRYPTO_HARD_CHANNEL_MAX];
++/* Channel of hash */
++static channel_context g_hash_hard_channel[CRYPTO_HARD_CHANNEL_MAX];
+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
++/* ****************************** API Declaration **************************** */
++static hi_void hash_print_last_node(hi_u32 chn_num)
++{
++ struct hash_entry_in *in = HI_NULL;
++ hash_hard_context *ctx = HI_NULL;
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!--[hash]*/
++ ctx = (hash_hard_context *)g_hash_hard_channel[chn_num].ctx;
+
-+#ifdef HI_CIPHER_DEBUG
-+extern int dump_mem(void);
-+#endif
++ /* get last in node info. */
++ in = &ctx->entry_in[ctx->id_in];
++
++ hi_log_error("chn %d, src addr 0x%x, size 0x%x\n", chn_num, in->hash_start_addr, in->hash_alg_length);
++ crypto_unused(in);
++}
++
++static hi_s32 drv_hash_get_err_code(hi_u32 chn_num)
++{
++ hi_u32 code;
++
++ /* check error code
++ * bit0: klad_key_use_err
++ * bit1: alg_len_err
++ * bit2: smmu_page_unvlid
++ * bit3: out_smmu_page_not_valid
++ * bit4: klad_key_write_err
++ */
++ code = hash_read(CALC_ERR);
++ if (code & KLAD_KEY_USE_ERR) {
++ hi_log_error("hash error: klad_key_use_err, chn %d !!!\n", chn_num);
++ }
++ if (code & ALG_LEN_ERR) {
++ hi_log_error("hash error: alg_len_err, chn %d !!!\n", chn_num);
++ }
++ if (code & SMMU_PAGE_UNVLID) {
++ hi_log_error("hash error: smmu_page_unvlid, chn %d !!!\n", chn_num);
++ }
++ if (code & OUT_SMMU_PAGE_NOT_VALID) {
++ hi_log_error("symc error: out_smmu_page_not_valid, chn %d !!!\n", chn_num);
++ }
++ if (code & KLAD_KEY_WRITE_ERR) {
++ hi_log_error("symc error: klad_key_write_err, chn %d !!!\n", chn_num);
++ }
++
++ /* print the inout buffer address. */
++ if (code) {
++ hash_print_last_node(chn_num);
++ return HI_ERR_CIPHER_FAILED_MEM;
++ }
++
++ return HI_SUCCESS;
++}
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+static hi_u32 hash_done_notify(void)
++static hi_u32 hash_done_notify(hi_void)
+{
+ hash_int_raw int_raw;
+ hash_int_status int_st;
-+ hi_u32 chn_mask = 0;
++ hi_u32 chn_mask;
+
-+ int_st.u32 = HASH_READ(HASH_INT_STATUS);
++ int_st.u32 = hash_read(HASH_INT_STATUS);
+ int_raw.u32 = 0;
+
-+ /*just process the valid channel*/
++ /* just process the valid channel. */
+ int_st.bits.hash_chn_oram_int &= HASH_HARD_CHANNEL_MASK;
+ chn_mask = int_st.bits.hash_chn_oram_int;
+ int_raw.bits.hash_chn_oram_raw = int_st.bits.hash_chn_oram_int;
+
-+ HI_LOG_DEBUG("int_st 0x%x, mask 0x%x\n", int_st.u32, chn_mask);
++ hi_log_debug("int_st 0x%x, mask 0x%x\n", int_st.u32, chn_mask);
+
-+ /*Clean raw int*/
-+ HASH_WRITE(HASH_INT_RAW, int_raw.u32);
++ /* Clean raw int. */
++ hash_write(HASH_INT_RAW, int_raw.u32);
+
+ return chn_mask;
+}
+
-+static hi_u32 symc_done_test(void)
++static hi_u32 symc_done_test(hi_void)
+{
+ cipher_int_status status;
+
-+ status.u32 = SYMC_READ(CIPHER_INT_STATUS);
++ status.u32 = symc_read(CIPHER_INT_STATUS);
+
-+ /*just process the valid channel*/
++ /* just process the valid channel. */
+ status.bits.cipher_chn_obuf_int &= CIPHER_HARD_CHANNEL_MASK;
+
+ return status.bits.cipher_chn_obuf_int; /* mask */
+}
+
-+/*! hash interrupt process function */
-+static irqreturn_t hash_interrupt_isr(hi_s32 irq, void *devId)
++/* hash interrupt process function */
++static irqreturn_t hash_interrupt_isr(hi_s32 irq, hi_void *devId)
+{
-+ hi_u32 mask = 0, i = 0;
++ hi_u32 mask, i;
+ hash_hard_context *ctx = HI_NULL;
-+ irqreturn_t ret = IRQ_HANDLED;
+
-+ CRYPTO_UNUSED(irq);
++ crypto_unused(irq);
+
+ mask = hash_done_notify();
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
+ if ((mask >> i) & 0x01) {
-+ ctx = (hash_hard_context *)hash_hard_channel[i].ctx;
++ ctx = (hash_hard_context *)g_hash_hard_channel[i].ctx;
+ ctx->done = HI_TRUE;
-+ HI_LOG_DEBUG("chn %d wake up\n", i);
++ hi_log_debug("chn %d wake up\n", i);
+ crypto_queue_wait_up(&ctx->queue);
+ }
+ }
@@ -200865,22 +270041,23 @@ index 0000000..b508b65
+ * so if symc has occur interrupt, we should return IRQ_NONE
+ * to tell system continue to process the symc interrupt.
+ */
-+ if (0 != symc_done_test()) {
-+ ret = IRQ_NONE;
++ if (symc_done_test() != 0) {
++ return IRQ_NONE;
+ }
+
-+ return ret;
++ return IRQ_HANDLED;
+}
+
-+/*! hash register interrupt process function */
-+static hi_s32 drv_hash_register_interrupt(void)
++/* hash register interrupt process function */
++static hi_s32 drv_hash_register_interrupt(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_s32 ret;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ hi_u32 i;
-+ const char *name;
++ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_HASH, &int_valid, &int_num, &name);
+
@@ -200891,27 +270068,28 @@ index 0000000..b508b65
+ /* request irq */
+ ret = crypto_request_irq(int_num, hash_interrupt_isr, name);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Irq request failure, irq = %d", int_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_REGISTER_IRQ);
++ hi_log_error("Irq request failure, irq = %d", int_num);
++ hi_log_print_err_code(HI_ERR_CIPHER_REGISTER_IRQ);
+ return HI_ERR_CIPHER_REGISTER_IRQ;
+ }
+
-+ /* initialize queue list*/
++ /* initialize queue list. */
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ crypto_queue_init(&((hash_hard_context *)hash_hard_channel[i].ctx)->queue);
++ crypto_queue_init(&((hash_hard_context *)g_hash_hard_channel[i].ctx)->queue);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/*! hash unregister interrupt process function */
-+static void drv_hash_unregister_interrupt(void)
++/* hash unregister interrupt process function */
++static hi_void drv_hash_unregister_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
-+ const char *name;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
++ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_HASH, &int_valid, &int_num, &name);
+
@@ -200920,44 +270098,43 @@ index 0000000..b508b65
+ }
+
+ /* free irq */
-+ HI_LOG_DEBUG("hash free irq, num %d, name %s\n", int_num, name);
++ hi_log_debug("hash free irq, num %d, name %s\n", int_num, name);
+ crypto_free_irq(int_num, name);
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+
-+/*! set interrupt */
-+static void hash_set_interrupt(void)
++/* set interrupt */
++static hi_void hash_set_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
-+ const char *name;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
++ const char *name = HI_NULL;
+ hash_int_en hash_int_en;
+ hash_int_raw hash_int_raw;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_HASH, &int_valid, &int_num, &name);
+
+ if (int_valid == HI_FALSE) {
-+ hash_int_en.u32 = HASH_READ(HASH_INT_EN);
++ hash_int_en.u32 = hash_read(HASH_INT_EN);
+
-+ /*The top interrupt switch only can be enable/disable by secure CPU*/
++ /* The top interrupt switch only can be enable/disable by secure CPU. */
+ hash_int_en.bits.hash_int_en = 0;
+ hash_int_en.bits.hash_sec_int_en = 0;
+ hash_int_en.bits.hash_chn_oram_en &= ~HASH_HARD_CHANNEL_MASK;
-+ HASH_WRITE(HASH_INT_EN, hash_int_en.u32);
-+ HI_LOG_INFO("HASH_INT_EN: 0x%x\n", hash_int_en.u32);
++ hash_write(HASH_INT_EN, hash_int_en.u32);
++ hi_log_info("HASH_INT_EN: 0x%x\n", hash_int_en.u32);
+ } else {
-+ hash_int_en.u32 = HASH_READ(HASH_INT_EN);
++ hash_int_en.u32 = hash_read(HASH_INT_EN);
+
-+ /*The top interrupt switch only can be enable/disable by secure CPU*/
++ /* The top interrupt switch only can be enable/disable by secure CPU. */
+ hash_int_en.bits.hash_int_en = 1;
+ hash_int_en.bits.hash_sec_int_en = 1;
+ hash_int_en.bits.hash_chn_oram_en |= HASH_HARD_CHANNEL_MASK;
-+ HASH_WRITE(HASH_INT_EN, hash_int_en.u32);
-+ HI_LOG_INFO("HASH_INT_EN: 0x%x\n", hash_int_en.u32);
++ hash_write(HASH_INT_EN, hash_int_en.u32);
++ hi_log_info("HASH_INT_EN: 0x%x\n", hash_int_en.u32);
+ }
+
+ /* clear interception
@@ -200965,68 +270142,94 @@ index 0000000..b508b65
+ * call the irq function before initialization
+ * when register interrupt, this will cause a system abort.
+ */
-+ hash_int_raw.u32 = SYMC_READ(HASH_INT_RAW);
++ hash_int_raw.u32 = symc_read(HASH_INT_RAW);
+ hash_int_raw.bits.hash_chn_oram_raw &= HASH_HARD_CHANNEL_MASK; /* clear valid channel */
-+ SYMC_WRITE(HASH_INT_RAW, hash_int_raw.u32);
++ symc_write(HASH_INT_RAW, hash_int_raw.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
++
++static hi_s32 drv_hash_wait_irq(hi_u32 chnnel_id)
++{
++ hi_s32 ret;
++ hi_u32 err_code;
++ hash_hard_context *ctx = HI_NULL;
++
++ ctx = (hash_hard_context *)g_hash_hard_channel[chnnel_id].ctx;
++ if (ctx == HI_NULL) {
++ hi_log_error("hash hard ctx is null.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
++
++ ret = crypto_queue_wait_timeout(ctx->queue, &ctx->done, CRYPTO_TIME_OUT);
++ if ((ret <= 0) && (ret != -ERESTARTSYS)) {
++ hi_log_print_func_err(crypto_queue_wait_timeout, ret);
++ err_code = drv_hash_get_err_code(chnnel_id);
++ if (err_code != HI_SUCCESS) {
++ hi_log_print_func_err(drv_hash_get_err_code, err_code);
++ }
++ hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
++
++ return HI_SUCCESS;
++}
++
+#endif
+
+static hi_u32 hash_done_try(hi_u32 chn_num)
+{
-+ hash_int_raw int_raw;
-+ hi_u32 chn_mask = 0;
++ hash_int_raw int_raw;
++ hi_u32 chn_mask;
+
-+ int_raw.u32 = HASH_READ(HASH_INT_RAW);
++ int_raw.u32 = hash_read(HASH_INT_RAW);
+ int_raw.bits.hash_chn_oram_raw &= 0x01 << chn_num;
+ chn_mask = int_raw.bits.hash_chn_oram_raw;
+
-+ /*Clean raw int*/
-+ HASH_WRITE(HASH_INT_RAW, int_raw.u32);
++ /* Clean raw int. */
++ hash_write(HASH_INT_RAW, int_raw.u32);
+
+ return chn_mask;
+}
+
-+/*! set hash entry */
-+static void hash_set_entry(hi_u32 chn, compat_addr dma_addr, void *cpu_addr)
++/* set hash entry */
++static hi_void hash_set_entry(hi_u32 chn, compat_addr dma_addr, hi_void *cpu_addr)
+{
-+ hash_hard_context *ctx = (hash_hard_context *)hash_hard_channel[chn].ctx;
++ hash_hard_context *ctx = (hash_hard_context *)g_hash_hard_channel[chn].ctx;
+ chann_hash_int_node_cfg hash_in_cfg;
+
-+ /*set total num and start addr for hash in node*/
-+ hash_in_cfg.u32 = HASH_READ(CHANn_HASH_IN_NODE_CFG(chn));
++ /* set total num and start addr for hash in node. */
++ hash_in_cfg.u32 = hash_read(chann_hash_in_node_cfg(chn));
+ hash_in_cfg.bits.hash_in_node_total_num = HASH_MAX_DEPTH;
-+ HASH_WRITE(CHANn_HASH_IN_NODE_CFG(chn), hash_in_cfg.u32);
-+ HASH_WRITE(CHANn_HASH_IN_NODE_START_ADDR(chn), ADDR_L32(dma_addr));
-+ HASH_WRITE(CHANN_HASH_IN_NODE_START_HIGH(chn), ADDR_H32(dma_addr));
-+ HI_LOG_INFO("CHANn_HASH_IN_NODE_CFG[0x%x]: \t0x%x, PHY: 0x%x, VIA %p\n",
-+ CHANn_HASH_IN_NODE_CFG(chn), hash_in_cfg.u32, ADDR_L32(dma_addr), cpu_addr);
++ hash_write(chann_hash_in_node_cfg(chn), hash_in_cfg.u32);
++ hash_write(chann_hash_in_node_start_addr(chn), addr_l32(dma_addr));
++ hash_write(chann_hash_in_node_start_high(chn), addr_h32(dma_addr));
++ hi_log_info("chann_hash_in_node_cfg[0x%x]: \t0x%x, PHY: 0x%x, VIA %p\n",
++ chann_hash_in_node_cfg(chn), hash_in_cfg.u32, addr_l32(dma_addr), cpu_addr);
+
+ ctx->entry_in = (struct hash_entry_in *)cpu_addr;
+ ctx->id_in = hash_in_cfg.bits.hash_in_node_wptr;
-+
-+ return;
+}
+
-+/*! set smmu */
-+static void hash_smmu_bypass(void)
++/* set smmu */
++static hi_void hash_smmu_bypass(hi_void)
+{
+#ifdef CRYPTO_SMMU_SUPPORT
+ hash_in_smmu_en hash_in_smmu_en;
+
-+ hash_in_smmu_en.u32 = HASH_READ(HASH_IN_SMMU_EN);
++ hash_in_smmu_en.u32 = hash_read(HASH_IN_SMMU_EN);
+ hash_in_smmu_en.bits.hash_in_chan_rd_dat_smmu_en |= HASH_HARD_CHANNEL_MASK >> 1;
+ hash_in_smmu_en.bits.hash_in_chan_rd_node_smmu_en &= ~(HASH_HARD_CHANNEL_MASK >> 1);
-+ HASH_WRITE(HASH_IN_SMMU_EN, hash_in_smmu_en.u32);
-+ HI_LOG_INFO("HASH_IN_SMMU_EN[0x%x] : 0x%x\n", HASH_IN_SMMU_EN, hash_in_smmu_en.u32);
++ hash_write(HASH_IN_SMMU_EN, hash_in_smmu_en.u32);
++ hi_log_info("HASH_IN_SMMU_EN[0x%x] : 0x%x\n", HASH_IN_SMMU_EN, hash_in_smmu_en.u32);
+#endif
+}
+
-+/*! smmu set base address */
-+static hi_s32 drv_hash_smmu_base_addr(void)
++/* smmu set base address */
++static hi_void drv_hash_smmu_base_addr(hi_void)
+{
+#ifdef CRYPTO_SMMU_SUPPORT
+ hi_u64 err_raddr = 0;
@@ -201037,194 +270240,138 @@ index 0000000..b508b65
+ smmu_get_table_addr(&err_raddr, &err_waddr, &table_addr);
+
+ if (crypto_is_sec_cpu()) {
-+ /*smmu page secure table addr*/
-+ HASH_WRITE(NORM_SMMU_START_ADDR, (hi_u32)table_addr);
-+ HI_LOG_INFO("NORM_SMMU_START_ADDR[0x%x] : 0x%x\n", NORM_SMMU_START_ADDR, (hi_u32)table_addr);
++ /* smmu page secure table addr. */
++ hash_write(NORM_SMMU_START_ADDR, (hi_u32)table_addr);
++ hi_log_info("NORM_SMMU_START_ADDR[0x%x] : 0x%x\n", NORM_SMMU_START_ADDR, (hi_u32)table_addr);
+ } else {
-+ /*smmu page nonsecure table addr*/
-+ HASH_WRITE(SEC_SMMU_START_ADDR, (hi_u32)table_addr);
-+ HI_LOG_INFO("SEC_SMMU_START_ADDR[0x%x] : 0x%x\n", SEC_SMMU_START_ADDR, (hi_u32)table_addr);
++ /* smmu page nonsecure table addr. */
++ hash_write(SEC_SMMU_START_ADDR, (hi_u32)table_addr);
++ hi_log_info("SEC_SMMU_START_ADDR[0x%x] : 0x%x\n", SEC_SMMU_START_ADDR, (hi_u32)table_addr);
+ }
+#endif
-+
-+ return HI_SUCCESS;
+}
+
-+/*! set secure channel,
-+ * non-secure CPU can't change the value of SEC_CHN_CFG,
-+ * so non-secure CPU call this function will do nothing.
++/* set secure channel,
++ * non-secure CPU can't change the value of SEC_CHN_CFG,
++ * so non-secure CPU call this function will do nothing.
+ */
-+static void drv_hash_enable_secure(void)
++static hi_void drv_hash_enable_secure(hi_void)
+{
+ sec_chn_cfg sec_chn_cfg;
+
-+ sec_chn_cfg.u32 = HASH_READ(SEC_CHN_CFG);
++ sec_chn_cfg.u32 = hash_read(SEC_CHN_CFG);
+ sec_chn_cfg.bits.hash_sec_chn_cfg |= HASH_HARD_CHANNEL_MASK;
-+ HASH_WRITE(SEC_CHN_CFG, sec_chn_cfg.u32);
-+ HI_LOG_INFO("SEC_CHN_CFG[0x%x]: 0x%x\n", SEC_CHN_CFG, sec_chn_cfg.u32);
++ hash_write(SEC_CHN_CFG, sec_chn_cfg.u32);
++ hi_log_info("SEC_CHN_CFG[0x%x]: 0x%x\n", SEC_CHN_CFG, sec_chn_cfg.u32);
+}
+
-+static void hash_print_last_node(hi_u32 chn_num)
-+{
-+ struct hash_entry_in *in = HI_NULL;
-+ hash_hard_context *ctx = HI_NULL;
-+
-+ ctx = (hash_hard_context *)hash_hard_channel[chn_num].ctx;
-+
-+ /* get last in node info*/
-+ in = &ctx->entry_in[ctx->id_in];
-+
-+ HI_LOG_ERROR("chn %d, src addr 0x%x, size 0x%x\n",
-+ chn_num, in->hash_start_addr , in->hash_alg_length);
-+ CRYPTO_UNUSED(in);
-+}
-+
-+static hi_s32 drv_hash_get_err_code(hi_u32 chn_num)
-+{
-+ hi_u32 code = 0;
-+
-+ /* check error code
-+ * bit0: klad_key_use_err
-+ * bit1: alg_len_err
-+ * bit2: smmu_page_unvlid
-+ * bit3: out_smmu_page_not_valid
-+ * bit4: klad_key_write_err
-+ */
-+
-+ /*read error code*/
-+ code = HASH_READ(CALC_ERR);
-+
-+ if (code & KLAD_KEY_USE_ERR) {
-+ HI_LOG_ERROR("hash error: klad_key_use_err, chn %d !!!\n", chn_num);
-+ }
-+ if (code & ALG_LEN_ERR) {
-+ HI_LOG_ERROR("hash error: alg_len_err, chn %d !!!\n", chn_num);
-+ }
-+ if (code & SMMU_PAGE_UNVLID) {
-+ HI_LOG_ERROR("hash error: smmu_page_unvlid, chn %d !!!\n", chn_num);
-+ }
-+ if (code & OUT_SMMU_PAGE_NOT_VALID) {
-+ HI_LOG_ERROR("symc error: out_smmu_page_not_valid, chn %d !!!\n", chn_num);
-+ }
-+ if (code & KLAD_KEY_WRITE_ERR) {
-+ HI_LOG_ERROR("symc error: klad_key_write_err, chn %d !!!\n", chn_num);
-+ }
-+
-+ /*print the inout buffer address*/
-+ if (code) {
-+ hash_print_last_node(chn_num);
-+#ifdef HI_CIPHER_DEBUG
-+ tee_hal_backtraces();
-+ dump_mem();
-+#endif
-+ return HI_ERR_CIPHER_FAILED_MEM;
-+ }
-+
-+ return HI_SUCCESS;
-+}
-+
-+void hash_enrty_init(crypto_mem mem)
++hi_void hash_enrty_init(crypto_mem mem)
+{
+ hi_u32 i;
+ compat_addr mmz_addr;
-+ void *cpu_addr = HI_NULL;
++ hi_void *cpu_addr = HI_NULL;
+
-+ HI_LOG_INFO("symc entry list configure\n");
-+ ADDR_U64(mmz_addr) = ADDR_U64(mem.mmz_addr);
++ hi_log_info("symc entry list configure\n");
++ addr_u64(mmz_addr) = addr_u64(mem.mmz_addr);
+ cpu_addr = mem.dma_virt;
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ if ((HASH_HARD_CHANNEL_MASK >> i) & 0x01) { /*valid channel*/
++ if ((HASH_HARD_CHANNEL_MASK >> i) & 0x01) { /* valid channel. */
+ hash_set_entry(i, mmz_addr, cpu_addr);
-+ ADDR_U64(mmz_addr) += HASH_NODE_SIZE; /* move to next channel */
++ addr_u64(mmz_addr) += HASH_NODE_SIZE; /* move to next channel */
+ cpu_addr = (hi_u8 *)cpu_addr + HASH_NODE_SIZE; /* move to next channel */
+ }
+ }
+ return;
+}
+
-+hi_s32 drv_hash_init(void)
++static hi_s32 drv_hash_cfg_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_s32 ret_error = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ if (HI_TRUE == hash_initialize) {
-+ HI_LOG_FUNC_EXIT();
-+ return HI_SUCCESS;
-+ }
-+
-+ ret = crypto_channel_init(hash_hard_channel, CRYPTO_HARD_CHANNEL_MAX, sizeof(hash_hard_context));
++ hi_log_info("alloc memory for nodes list\n");
++ ret = hash_mem_create(&g_hash_dma, SEC_MMZ, "hash_node_list", HASH_NODE_LIST_SIZE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, hash channel list init failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_init, ret);
++ hi_log_print_func_err(hash_mem_create, ret);
+ return ret;
+ }
++ hi_log_info("HASH DMA buffer, MMU 0x%x, MMZ 0x%x, VIA %p, size 0x%x\n", addr_l32(g_hash_dma.dma_addr),
++ addr_l32(g_hash_dma.mmz_addr), g_hash_dma.dma_virt, g_hash_dma.dma_size);
+
-+ HI_LOG_INFO("enable hash\n");
-+ module_enable(CRYPTO_MODULE_ID_HASH);
++ hi_log_info("hash entry list configure\n");
++ hash_enrty_init(g_hash_dma);
+
-+ HI_LOG_INFO("alloc memory for nodes list\n");
-+ ret = hash_mem_create(&hash_dma, SEC_MMZ, "hash_node_list", HASH_NODE_LIST_SIZE);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, malloc ddr for hash nodes list failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(hash_mem_create, ret);
-+ goto __error1;
-+ }
-+ HI_LOG_INFO("HASH DMA buffer, MMU 0x%x, MMZ 0x%x, VIA %p, size 0x%x\n",
-+ ADDR_L32(hash_dma.dma_addr), ADDR_L32(hash_dma.mmz_addr),
-+ hash_dma.dma_virt, hash_dma.dma_size);
-+
-+ HI_LOG_INFO("hash entry list configure\n");
-+ hash_enrty_init(hash_dma);
-+
-+ HI_LOG_INFO("hash SMMU configure\n");
++ hi_log_info("hash SMMU configure\n");
+ hash_smmu_bypass();
+ drv_hash_smmu_base_addr();
+
-+ HI_LOG_INFO("hash secure channel configure\n");
++ hi_log_info("hash secure channel configure\n");
+ drv_hash_enable_secure();
-+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ HI_LOG_INFO("hash interrupt configure\n");
++ hi_log_info("hash interrupt configure\n");
+ hash_set_interrupt();
+
-+ HI_LOG_INFO("hash register interrupt function\n");
++ hi_log_info("hash register interrupt function\n");
+ ret = drv_hash_register_interrupt();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, register interrupt failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_register_interrupt, ret);
-+ ret_error = hash_mem_destory(&hash_dma);
++ hi_s32 ret_error;
++
++ hi_log_print_func_err(drv_hash_register_interrupt, ret);
++ ret_error = hash_mem_destory(&g_hash_dma);
+ if (ret_error != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, hash dma crypto mem destory failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(hash_mem_destory, ret_error);
++ hi_log_print_func_err(hash_mem_destory, ret_error);
+ }
-+ goto __error1;
++ return ret;
+ }
+#endif
+
-+ hash_initialize = HI_TRUE;
-+ HI_LOG_FUNC_EXIT();
+ return HI_SUCCESS;
-+
-+__error1:
-+ module_disable(CRYPTO_MODULE_ID_HASH);
-+ ret_error = crypto_channel_deinit(hash_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
-+ if (ret_error != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, crypto channel deinit failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_deinit, ret_error);
-+ }
-+
-+ return ret;
+}
+
-+hi_s32 drv_hash_deinit(void)
++hi_s32 drv_hash_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ HI_LOG_FUNC_ENTER();
++ hi_s32 ret;
+
-+ if (HI_FALSE == hash_initialize) {
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_enter();
++
++ if (g_hash_initialize == HI_TRUE) {
++ hi_log_func_exit();
++ return HI_SUCCESS;
++ }
++
++ ret = crypto_channel_init(g_hash_hard_channel, CRYPTO_HARD_CHANNEL_MAX, sizeof(hash_hard_context));
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_channel_init, ret);
++ return ret;
++ }
++
++ hi_log_info("enable hash\n");
++ module_enable(CRYPTO_MODULE_ID_HASH);
++
++ ret = drv_hash_cfg_init();
++ if (ret != HI_SUCCESS) {
++ hi_s32 ret_error;
++
++ hi_log_print_func_err(crypto_channel_init, ret);
++ module_disable(CRYPTO_MODULE_ID_HASH);
++ ret_error = crypto_channel_deinit(g_hash_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
++ if (ret_error != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_channel_deinit, ret_error);
++ }
++ return ret;
++ }
++
++ g_hash_initialize = HI_TRUE;
++ hi_log_func_exit();
++ return HI_SUCCESS;
++}
++
++hi_s32 drv_hash_deinit(hi_void)
++{
++ hi_s32 ret;
++ hi_log_func_enter();
++
++ if (g_hash_initialize == HI_FALSE) {
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
@@ -201232,128 +270379,140 @@ index 0000000..b508b65
+ drv_hash_unregister_interrupt();
+#endif
+
-+ ret = hash_mem_destory(&hash_dma);
++ ret = hash_mem_destory(&g_hash_dma);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(hash_mem_destory, ret);
++ hi_log_print_func_err(hash_mem_destory, ret);
+ return ret;
+ }
+ module_disable(CRYPTO_MODULE_ID_HASH);
-+ ret = crypto_channel_deinit(hash_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
++ ret = crypto_channel_deinit(g_hash_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_deinit, ret);
++ hi_log_print_func_err(crypto_channel_deinit, ret);
+ return ret;
+ }
+
-+ hash_initialize = HI_FALSE;
++ g_hash_initialize = HI_FALSE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void drv_hash_resume(void)
++hi_void drv_hash_resume(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("enable hash\n");
++ hi_log_info("enable hash\n");
+ module_enable(CRYPTO_MODULE_ID_HASH);
+
-+ HI_LOG_INFO("hash entry list configure\n");
-+ hash_enrty_init(hash_dma);
++ hi_log_info("hash entry list configure\n");
++ hash_enrty_init(g_hash_dma);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ HI_LOG_INFO("hash interrupt configure\n");
++ hi_log_info("hash interrupt configure\n");
+ hash_set_interrupt();
+#endif
+
-+ HI_LOG_INFO("hash SMMU configure\n");
++ hi_log_info("hash SMMU configure\n");
+ hash_smmu_bypass();
+ drv_hash_smmu_base_addr();
+
-+ HI_LOG_INFO("hash secure channel configure\n");
++ hi_log_info("hash secure channel configure\n");
+ drv_hash_enable_secure();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+void drv_hash_suspend(void)
++hi_void drv_hash_suspend(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_enter();
++ hi_log_func_exit();
+
+ return;
+}
+
++static hi_s32 drv_hash_query_raw_interrupt(hi_u32 chnnel_id)
++{
++ hi_s32 i;
++
++ /* interrupt unsupport, query the raw interrupt flag. */
++ for (i = 0; i < CRYPTO_TIME_OUT; i++) {
++ if (hash_done_try(chnnel_id)) {
++ break;
++ }
++
++ if (i <= MS_TO_US) {
++ crypto_udelay(1); /* short waitting for 1000 us. */
++ } else {
++ crypto_msleep(1); /* long waitting for 5000 ms. */
++ }
++ }
++
++ if (i >= CRYPTO_TIME_OUT) {
++ hi_u32 err_code;
++
++ hi_log_error("hash wait done timeout, chn=%d\n", chnnel_id);
++
++ err_code = drv_hash_get_err_code(chnnel_id);
++ if (err_code != HI_SUCCESS) {
++ hi_log_print_func_err(drv_hash_get_err_code, err_code);
++ }
++
++ hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
++
++ return HI_SUCCESS;
++}
++
+/* wait hash ready */
+static hi_s32 drv_hash_wait_ready(hi_u32 chn_num)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
-+ hi_u32 errcode = 0;
-+ hi_u32 i;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
+ module_get_attr(CRYPTO_MODULE_ID_HASH, &int_valid, &int_num, HI_NULL);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ /* interrupt support, wait irq*/
++ /* interrupt support, wait irq. */
+ if (int_valid) {
-+ hash_hard_context *ctx = HI_NULL;
-+
-+ ctx = (hash_hard_context *)hash_hard_channel[chn_num].ctx;
-+
-+ ret = crypto_queue_wait_timeout(ctx->queue, &ctx->done, CRYPTO_TIME_OUT);
-+ if ((0x00 < ret) || (-ERESTARTSYS == ret)) {
-+ ret = HI_SUCCESS;
-+ } else {
-+ HI_LOG_ERROR("wait done timeout, chn=%d, ret %d\n", chn_num, ret);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_TIMEOUT);
-+ ret = HI_ERR_CIPHER_TIMEOUT;
++ ret = drv_hash_wait_irq(chn_num);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_hash_wait_irq, ret);
++ return ret;
+ }
-+ } else /* interrupt unsupport, query the raw interrupt flag*/
-+#endif
-+ {
-+ for (i = 0; i < CRYPTO_TIME_OUT; i++) {
-+ if (hash_done_try(chn_num)) {
-+ break;
-+ }
-+
-+ if (MS_TO_US >= i) {
-+ crypto_udelay(1); /* short waitting for 1000 us */
-+ } else {
-+ crypto_msleep(1); /* long waitting for 5000 ms*/
-+ }
-+ }
-+ if (CRYPTO_TIME_OUT <= i) {
-+ HI_LOG_ERROR("hash wait done timeout, chn=%d\n", chn_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_TIMEOUT);
-+ ret = HI_ERR_CIPHER_TIMEOUT;
-+ } else {
-+ ret = HI_SUCCESS;
++ } else {
++ ret = drv_hash_query_raw_interrupt(chn_num);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_hash_query_raw_interrupt, ret);
++ return ret;
+ }
+ }
-+
++#else
++ ret = drv_hash_query_raw_interrupt(chn_num);
+ if (ret != HI_SUCCESS) {
-+ errcode = drv_hash_get_err_code(chn_num);
-+ HI_LOG_ERROR("hard error code: 0x%x\n", errcode);
-+ CRYPTO_UNUSED(errcode);
++ hi_log_print_func_err(drv_hash_query_raw_interrupt, ret);
++ return ret;
+ }
++#endif
+
-+ HI_LOG_FUNC_EXIT();
-+ return ret;
++ hi_log_func_exit();
++ return HI_SUCCESS;
+}
+
-+static void hash_addbuf(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size)
++static hi_void hash_addbuf(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size)
+{
+ hash_hard_context *ctx = HI_NULL;
-+ hi_u32 id = 0, size = 0;
-+ void *addr = HI_NULL;
++ hi_u32 id, size;
++ hi_void *addr = HI_NULL;
+
-+ ctx = (hash_hard_context *)hash_hard_channel[chn_num].ctx;
++ ctx = (hash_hard_context *)g_hash_hard_channel[chn_num].ctx;
+
+ /* clean in entry */
+ id = ctx->id_in++;
@@ -201364,42 +270523,39 @@ index 0000000..b508b65
+
+ /* set addr and length */
+ ctx->entry_in[id].spacc_cmd = 0x00;
-+ ctx->entry_in[id].hash_start_addr = ADDR_L32(buf_phy);
-+ ctx->entry_in[id].word1 = ADDR_H32(buf_phy);
++ ctx->entry_in[id].hash_start_addr = addr_l32(buf_phy);
++ ctx->entry_in[id].word1 = addr_h32(buf_phy);
+ ctx->entry_in[id].hash_alg_length = buf_size;
+ ctx->entry_in[id].hash_ctrl = HASH_CTRL_HASH_IN_FIRST | HASH_CTRL_HASH_IN_LAST;
+ ctx->id_in %= HASH_MAX_DEPTH;
-+ HI_LOG_INFO("add digest in buf: id %d, addr 0x%x, len 0x%x\n",
-+ id, ADDR_L32(buf_phy), buf_size);
-+
-+ return;
++ hi_log_info("add digest in buf: id %d, addr 0x%x, len 0x%x\n", id, addr_l32(buf_phy), buf_size);
+}
+
-+hi_s32 drv_hash_config(hi_u32 chn_num, hash_mode mode, hi_u32 state[HASH_RESULT_MAX_SIZE_IN_WORD])
++hi_s32 drv_hash_cfg(hi_u32 chn_num, hash_mode mode, hi_u32 state[HASH_RESULT_MAX_SIZE_IN_WORD])
+{
+ hash_hard_context *ctx = HI_NULL;
+ chann_hash_ctrl hash_ctrl;
+ hi_u32 i = 0;
+
-+ HI_LOG_CHECK_PARAM(hash_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(((HASH_HARD_CHANNEL_MASK >> chn_num) & 0x01) == 0);
++ hi_log_chk_param_return(g_hash_initialize != HI_TRUE);
++ hi_log_chk_param_return(((HASH_HARD_CHANNEL_MASK >> chn_num) & 0x01) == 0);
+
-+ ctx = (hash_hard_context *)hash_hard_channel[chn_num].ctx;
++ ctx = (hash_hard_context *)g_hash_hard_channel[chn_num].ctx;
+ ctx->hash_alg = mode;
+
+ /* Control */
-+ hash_ctrl.u32 = HASH_READ(CHANn_HASH_CTRL(chn_num));
++ hash_ctrl.u32 = hash_read(chann_hash_ctrl(chn_num));
+ hash_ctrl.bits.hash_chn_mode = 0;
+ hash_ctrl.bits.hash_chn_agl_sel = mode;
-+ HASH_WRITE(CHANn_HASH_CTRL(chn_num), hash_ctrl.u32);
-+ HI_LOG_INFO("CTRL: 0x%X\n", hash_ctrl.u32);
++ hash_write(chann_hash_ctrl(chn_num), hash_ctrl.u32);
++ hi_log_info("CTRL: 0x%X\n", hash_ctrl.u32);
+
-+ /*Write last state*/
++ /* Write last state. */
+ for (i = 0; i < HASH_RESULT_MAX_SIZE_IN_WORD; i++) {
-+ HASH_WRITE(CHANn_HASH_STATE_VAL_ADDR(chn_num), i);
-+ HASH_WRITE(CHANn_HASH_STATE_VAL(chn_num), state[i]);
++ hash_write(chann_hash_state_val_addr(chn_num), i);
++ hash_write(chann_hash_state_val(chn_num), state[i]);
+ }
-+ HI_LOG_INFO("state[0]: 0x%x\n", state[0]);
++ hi_log_info("state[0]: 0x%x\n", state[0]);
+
+ return HI_SUCCESS;
+}
@@ -201408,17 +270564,17 @@ index 0000000..b508b65
+{
+ chann_hash_int_node_cfg in_node_cfg;
+ hash_hard_context *ctx = HI_NULL;
-+ hi_u32 ptr = 0;
++ hi_u32 ptr;
+ crypto_mem *hash_dma_ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(hash_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(((HASH_HARD_CHANNEL_MASK >> chn_num) & 0x01) == 0);
++ hi_log_chk_param_return(g_hash_initialize != HI_TRUE);
++ hi_log_chk_param_return(((HASH_HARD_CHANNEL_MASK >> chn_num) & 0x01) == 0);
+
-+ ctx = (hash_hard_context *)hash_hard_channel[chn_num].ctx;
++ ctx = (hash_hard_context *)g_hash_hard_channel[chn_num].ctx;
+
-+ if (0 == length) {
++ if (length == 0) {
+ return HI_SUCCESS;
+ }
+
@@ -201428,57 +270584,58 @@ index 0000000..b508b65
+ hash_addbuf(chn_num, mem->dma_addr, length);
+
+ /* configure in-node, only compute one nodes */
-+ in_node_cfg.u32 = HASH_READ(CHANn_HASH_IN_NODE_CFG(chn_num));
++ in_node_cfg.u32 = hash_read(chann_hash_in_node_cfg(chn_num));
+ ptr = in_node_cfg.bits.hash_in_node_wptr + 1;
+ in_node_cfg.bits.hash_in_node_wptr = ptr % HASH_MAX_DEPTH;
+ in_node_cfg.bits.hash_in_node_mpackage_int_level = 1;
+
+ /* hash flush cache of hash mem and hash list buffer. */
+ crypto_cpuc_flush_dcache_area(mem->dma_virt, length);
-+ hash_dma_ctx = &hash_dma;
++ hash_dma_ctx = &g_hash_dma;
+ crypto_cpuc_flush_dcache_area(hash_dma_ctx->dma_virt, HASH_NODE_LIST_SIZE);
+
+ /* Start */
-+ HASH_WRITE(CHANn_HASH_IN_NODE_CFG(chn_num), in_node_cfg.u32);
-+ HI_LOG_INFO("CHANn_HASH_IN_NODE_CFG: 0x%x\n", in_node_cfg.u32);
++ hash_write(chann_hash_in_node_cfg(chn_num), in_node_cfg.u32);
++ hi_log_info("chann_hash_in_node_cfg: 0x%x\n", in_node_cfg.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 drv_hash_wait_done(hi_u32 chn_num, hi_u32 *state)
+{
+ hi_u32 i = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(hash_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(((HASH_HARD_CHANNEL_MASK >> chn_num) & 0x01) == 0);
++ hi_log_chk_param_return(state == HI_NULL);
++ hi_log_chk_param_return(g_hash_initialize != HI_TRUE);
++ hi_log_chk_param_return(((HASH_HARD_CHANNEL_MASK >> chn_num) & 0x01) == 0);
+
+ ret = drv_hash_wait_ready(chn_num);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_wait_ready, ret);
++ hi_log_print_func_err(drv_hash_wait_ready, ret);
+ return ret;
+ }
+
+ /* read hash result */
+ for (i = 0; i < HASH_RESULT_MAX_SIZE_IN_WORD; i++) {
-+ HASH_WRITE(CHANn_HASH_STATE_VAL_ADDR(chn_num), i);
-+ state[i] = HASH_READ(CHANn_HASH_STATE_VAL(chn_num));
++ hash_write(chann_hash_state_val_addr(chn_num), i);
++ state[i] = hash_read(chann_hash_state_val(chn_num));
+ }
-+ HI_LOG_DEBUG("digest[0]: 0x%x\n", state[0]);
++ hi_log_debug("digest[0]: 0x%x\n", state[0]);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void drv_hash_reset(hi_u32 chn_num)
++hi_void drv_hash_reset(hi_u32 chn_num)
+{
-+ CRYPTO_UNUSED(chn_num);
++ crypto_unused(chn_num);
+}
+
-+void drv_hash_get_capacity(hash_capacity *capacity)
++hi_void drv_hash_get_capacity(hash_capacity *capacity)
+{
+ crypto_memset(capacity, sizeof(hash_capacity), 0, sizeof(hash_capacity));
+
@@ -201491,144 +270648,122 @@ index 0000000..b508b65
+
+ return;
+}
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
-+#endif //End of CHIP_HASH_VER_V200
++#endif /* End of CHIP_HASH_VER_V200 */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v200.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v200.h
new file mode 100644
-index 0000000..e3e1cb8
+index 0000000..07f4205
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_hash_v200.h
-@@ -0,0 +1,198 @@
+@@ -0,0 +1,174 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv hash v200.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
-+#ifndef _DRV_HASH_V1_H_
-+#define _DRV_HASH_V1_H_
++#ifndef _DRV_HASH_V100_H_
++#define _DRV_HASH_V100_H_
+
+#include "drv_osal_lib.h"
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup hash drivers*/
-+/** @{*/ /** <!-- [hash]*/
-+
-+/*! \Define the offset of reg */
-+#define SEC_CHN_CFG (0x0304)
-+#define CALC_ERR (0x0320)
-+#define CIPHER_INT_STATUS (0x0404)
-+#define NORM_SMMU_START_ADDR (0x0440)
-+#define SEC_SMMU_START_ADDR (0x0444)
-+#define HASH_INT_STATUS (0x0804)
-+#define HASH_INT_EN (0x0808)
-+#define HASH_INT_RAW (0x080C)
-+#define HASH_IN_SMMU_EN (0x0810)
-+#define CHAN0_HASH_DAT_IN (0x0818)
-+#define CHAN0_HASH_TOTAL_DAT_LEN (0x081C)
-+#define CHANn_HASH_CTRL(id) (0x0800 + (id)*0x80)
-+#define CHANn_HASH_IN_NODE_CFG(id) (0x0804 + (id)*0x80)
-+#define CHANn_HASH_IN_NODE_START_ADDR(id)(0x0808 + (id)*0x80)
-+#define CHANn_HASH_IN_BUF_RPTR(id) (0x080C + (id)*0x80)
-+#define CHANn_HASH_STATE_VAL(id) (0x0340 + (id)*0x08)
-+#define CHANn_HASH_STATE_VAL_ADDR(id) (0x0344 + (id)*0x08)
-+#define CHANN_HASH_IN_NODE_START_HIGH(id)(0x0820 + (id)*0x80)
++/* ************************** Internal Structure Definition *************************** */
++/* Define the offset of reg */
++#define SEC_CHN_CFG 0x0304
++#define CALC_ERR 0x0320
++#define CIPHER_INT_STATUS 0x0404
++#define NORM_SMMU_START_ADDR 0x0440
++#define SEC_SMMU_START_ADDR 0x0444
++#define HASH_INT_STATUS 0x0804
++#define HASH_INT_EN 0x0808
++#define HASH_INT_RAW 0x080C
++#define HASH_IN_SMMU_EN 0x0810
++#define CHAN0_HASH_DAT_IN 0x0818
++#define CHAN0_HASH_TOTAL_DAT_LEN 0x081C
++#define chann_hash_ctrl(id) (0x0800 + (id) * 0x80)
++#define chann_hash_in_node_cfg(id) (0x0804 + (id) * 0x80)
++#define chann_hash_in_node_start_addr(id)(0x0808 + (id) * 0x80)
++#define chann_hash_in_buf_rptr(id) (0x080C + (id) * 0x80)
++#define chann_hash_state_val(id) (0x0340 + (id) * 0x08)
++#define chann_hash_state_val_addr(id) (0x0344 + (id) * 0x08)
++#define chann_hash_in_node_start_high(id)(0x0820 + (id) * 0x80)
+
+/* Define the union sec_chn_cfg */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int cipher_sec_chn_cfg : 8 ; /* [7..0] */
-+ unsigned int cipher_sec_chn_cfg_lock : 1 ; /* [8] */
-+ unsigned int reserved_0 : 7 ; /* [15..9] */
-+ unsigned int hash_sec_chn_cfg : 8 ; /* [23..16] */
-+ unsigned int hash_sec_chn_cfg_lock : 1 ; /* [24] */
-+ unsigned int reserved_1 : 7 ; /* [31..25] */
++ hi_u32 cipher_sec_chn_cfg : 8 ; /* [7..0] */
++ hi_u32 cipher_sec_chn_cfg_lock : 1 ; /* [8] */
++ hi_u32 reserved_0 : 7 ; /* [15..9] */
++ hi_u32 hash_sec_chn_cfg : 8 ; /* [23..16] */
++ hi_u32 hash_sec_chn_cfg_lock : 1 ; /* [24] */
++ hi_u32 reserved_1 : 7 ; /* [31..25] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} sec_chn_cfg;
+
+/* Define the union chan0_hash_ctrl */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int hash_ch0_start : 1 ; /* [0] */
-+ unsigned int hash_ch0_agl_sel : 3 ; /* [3..1] */
-+ unsigned int hash_ch0_hmac_calc_step : 1 ; /* [4] */
-+ unsigned int hash_ch0_mode : 1 ; /* [5] */
-+ unsigned int hash_ch0_key_sel : 1 ; /* [6] */
-+ unsigned int reserved_0 : 2 ; /* [8..7] */
-+ unsigned int hash_ch0_auto_padding_en : 1 ; /* [9] */
-+ unsigned int hash_ch0_hmac_key_addr : 3 ; /* [12..10] */
-+ unsigned int hash_ch0_used : 1 ; /* [13] */
-+ unsigned int hash_ch0_sec_alarm : 1 ; /* [13] */
-+ unsigned int reserved_1 : 17 ; /* [31..15] */
++ hi_u32 hash_ch0_start : 1 ; /* [0] */
++ hi_u32 hash_ch0_agl_sel : 3 ; /* [3..1] */
++ hi_u32 hash_ch0_hmac_calc_step : 1 ; /* [4] */
++ hi_u32 hash_ch0_mode : 1 ; /* [5] */
++ hi_u32 hash_ch0_key_sel : 1 ; /* [6] */
++ hi_u32 reserved_0 : 2 ; /* [8..7] */
++ hi_u32 hash_ch0_auto_padding_en : 1 ; /* [9] */
++ hi_u32 hash_ch0_hmac_key_addr : 3 ; /* [12..10] */
++ hi_u32 hash_ch0_used : 1 ; /* [13] */
++ hi_u32 hash_ch0_sec_alarm : 1 ; /* [13] */
++ hi_u32 reserved_1 : 17 ; /* [31..15] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} chan0_hash_ctrl;
+
+/* Define the union hash_int_status */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int reserved_0 : 18 ; /* [17..0] */
-+ unsigned int hash_chn_oram_int : 8 ; /* [25..18] */
-+ unsigned int reserved_1 : 6 ; /* [31..26] */
++ hi_u32 reserved_0 : 18 ; /* [17..0] */
++ hi_u32 hash_chn_oram_int : 8 ; /* [25..18] */
++ hi_u32 reserved_1 : 6 ; /* [31..26] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} hash_int_status;
+
+/* Define the union hash_int_en */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int reserved_0 : 18 ; /* [17..0] */
-+ unsigned int hash_chn_oram_en : 8 ; /* [25..18] */
-+ unsigned int reserved_1 : 4 ; /* [29..26] */
-+ unsigned int hash_sec_int_en : 1 ; /* [30] */
-+ unsigned int hash_int_en : 1 ; /* [31] */
++ hi_u32 reserved_0 : 18 ; /* [17..0] */
++ hi_u32 hash_chn_oram_en : 8 ; /* [25..18] */
++ hi_u32 reserved_1 : 4 ; /* [29..26] */
++ hi_u32 hash_sec_int_en : 1 ; /* [30] */
++ hi_u32 hash_int_en : 1 ; /* [31] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} hash_int_en;
+
+/* Define the union hash_int_raw */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int reserved_0 : 18 ; /* [17..0] */
-+ unsigned int hash_chn_oram_raw : 8 ; /* [25..18] */
-+ unsigned int reserved_1 : 6 ; /* [31..26] */
++ hi_u32 reserved_0 : 18 ; /* [17..0] */
++ hi_u32 hash_chn_oram_raw : 8 ; /* [25..18] */
++ hi_u32 reserved_1 : 6 ; /* [31..26] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} hash_int_raw;
+
+/* Define the union cipher_int_status */
@@ -201643,84 +270778,68 @@ index 0000000..e3e1cb8
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} cipher_int_status;
+
+/* Define the union hash_in_smmu_en */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int hash_in_chan_rd_dat_smmu_en : 7 ; /* [6..0] */
-+ unsigned int reserved_0 : 9 ; /* [15..7] */
-+ unsigned int hash_in_chan_rd_node_smmu_en : 7 ; /* [22..16] */
-+ unsigned int reserved_1 : 9 ; /* [31..23] */
++ hi_u32 hash_in_chan_rd_dat_smmu_en : 7 ; /* [6..0] */
++ hi_u32 reserved_0 : 9 ; /* [15..7] */
++ hi_u32 hash_in_chan_rd_node_smmu_en : 7 ; /* [22..16] */
++ hi_u32 reserved_1 : 9 ; /* [31..23] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} hash_in_smmu_en;
+
+/* Define the union chann_hash_ctrl */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int reserved_0 : 1 ; /* [0] */
-+ unsigned int hash_chn_agl_sel : 3 ; /* [3..1] */
-+ unsigned int reserved_1 : 1 ; /* [4] */
-+ unsigned int hash_chn_mode : 1 ; /* [5] */
-+ unsigned int hash_chn_key_sel : 1 ; /* [6] */
-+ unsigned int hash_chn_dat_in_byte_swap_en : 1 ; /* [7] */
-+ unsigned int hash_chn_dat_in_bit_swap_en : 1 ; /* [8] */
-+ unsigned int hash_chn_auto_padding_en : 1 ; /* [9] */
-+ unsigned int hash_chn_hmac_key_addr : 3 ; /* [12..10] */
-+ unsigned int reserved_2 : 19 ; /* [31..13] */
++ hi_u32 reserved_0 : 1 ; /* [0] */
++ hi_u32 hash_chn_agl_sel : 3 ; /* [3..1] */
++ hi_u32 reserved_1 : 1 ; /* [4] */
++ hi_u32 hash_chn_mode : 1 ; /* [5] */
++ hi_u32 hash_chn_key_sel : 1 ; /* [6] */
++ hi_u32 hash_chn_dat_in_byte_swap_en : 1 ; /* [7] */
++ hi_u32 hash_chn_dat_in_bit_swap_en : 1 ; /* [8] */
++ hi_u32 hash_chn_auto_padding_en : 1 ; /* [9] */
++ hi_u32 hash_chn_hmac_key_addr : 3 ; /* [12..10] */
++ hi_u32 reserved_2 : 19 ; /* [31..13] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} chann_hash_ctrl;
+
+/* Define the union chann_hash_int_node_cfg */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int hash_in_node_mpackage_int_level : 8 ; /* [7..0] */
-+ unsigned int hash_in_node_rptr : 8 ; /* [15..8] */
-+ unsigned int hash_in_node_wptr : 8 ; /* [23..16] */
-+ unsigned int hash_in_node_total_num : 8 ; /* [31..24] */
++ hi_u32 hash_in_node_mpackage_int_level : 8 ; /* [7..0] */
++ hi_u32 hash_in_node_rptr : 8 ; /* [15..8] */
++ hi_u32 hash_in_node_wptr : 8 ; /* [23..16] */
++ hi_u32 hash_in_node_total_num : 8 ; /* [31..24] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} chann_hash_int_node_cfg;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+#endif
++#endif /* End of _DRV_HASH_V100_H_ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_ifep_rsa_v100.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_ifep_rsa_v100.c
new file mode 100644
-index 0000000..00ac25e
+index 0000000..8a94792
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_ifep_rsa_v100.c
-@@ -0,0 +1,649 @@
+@@ -0,0 +1,637 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv ifep rsa v100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_ifep_rsa_v100.h"
@@ -201730,17 +270849,12 @@ index 0000000..00ac25e
+
+#ifdef CHIP_IFEP_RSA_VER_V100
+
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup rsa */
-+/** @{ */ /** <!-- [rsa] */
-+
-+
-+/*! Define the time out */
-+#define RSA_TIME_OUT 5000
++/* Define the time out */
++#define RSA_TIME_OUT 5000
+
+/* rsa support rand mask or not */
-+#define RSA_SUB_VER_RAND_MASK (0x20160907)
-+#define RSA_SUB_VER_NORMAL (0x00)
++#define RSA_SUB_VER_RAND_MASK 0x20160907
++#define RSA_SUB_VER_NORMAL 0x00
+
+/* crc 16 */
+#define CRC16_TABLE_SIZE 256
@@ -201753,37 +270867,31 @@ index 0000000..00ac25e
+#define RSA_MODE_EXP 0x00
+#define RSA_MODE_CLEAR_RAM 0x02
+
-+/*! rsa already initialize or not */
-+static hi_u32 rsa_initialize = HI_FALSE;
++/* rsa already initialize or not */
++static hi_u32 g_rsa_initialize = HI_FALSE;
+
-+/*! Define the context of rsa */
++/* Define the context of rsa */
+typedef struct {
+ hi_u32 rsa_sub_ver;
-+ hi_u32 done; /*!< calculation finish flag*/
-+ crypto_queue_head queue; /*!< quene list */
++ hi_u32 done; /* calculation finish flag. */
++ crypto_queue_head queue; /* quene list */
+} rsa_hard_context;
+
-+static rsa_hard_context rsainfo;
-+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
-+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup rsa */
-+/** @{ */ /** <!--[rsa]*/
-+
++static rsa_hard_context g_rsa_info;
++/* ****************************** API Declaration **************************** */
+#ifdef RSA_RAND_MASK
+
-+static u16 crc_table[CRC16_TABLE_SIZE];
++static hi_u16 g_crc_table[CRC16_TABLE_SIZE];
+
-+static void drv_rsa_crc16_init(void)
++static hi_void drv_rsa_crc16_init(hi_void)
+{
-+ u16 remainder;
-+ u16 n, m;
-+ u16 *local_crc_table = crc_table;
++ hi_u16 remainder;
++ hi_u16 n, m;
++ hi_u16 *local_crc_table = g_crc_table;
+
-+ for (n = 0; n < CRC16_TABLE_SIZE; n ++) {
-+ remainder = (HI_U16)n << BITS_IN_BYTE;
-+ for (m = BITS_IN_BYTE; m > 0; m --) {
++ for (n = 0; n < CRC16_TABLE_SIZE; n++) {
++ remainder = (hi_u16)n << BITS_IN_BYTE;
++ for (m = BITS_IN_BYTE; m > 0; m--) {
+ if (remainder & U16_MSB) {
+ remainder = (remainder << 1) ^ CRC16_POLYNOMIAL;
+ } else {
@@ -201794,24 +270902,24 @@ index 0000000..00ac25e
+ }
+}
+
-+static u16 drv_rsa_crc16_block(u16 crc, hi_u8 block[BLOCK_BYTES], hi_u8 rand_number[BLOCK_BYTES])
++static hi_u16 drv_rsa_crc16_block(hi_u16 crc, hi_u8 block[BLOCK_BYTES], hi_u8 rand_num[BLOCK_BYTES])
+{
+ hi_u8 i, j;
+ hi_u8 val;
+
+ for (i = 0; i < BLOCK_BYTES / WORD_WIDTH; i++) {
+ for (j = 0; j < WORD_WIDTH; j++) {
-+ val = block[i * 4 + 3 - j] ^ rand_number[i * 4 + 3 - j];
-+ crc = (crc << BITS_IN_BYTE) ^ crc_table[((crc >> BITS_IN_BYTE) ^ val) & BYTE_MASK];
++ val = block[i * WORD_WIDTH + WORD_IDX_3 - j] ^ rand_num[i * WORD_WIDTH + WORD_IDX_3 - j];
++ crc = (crc << BITS_IN_BYTE) ^ g_crc_table[((crc >> BITS_IN_BYTE) ^ val) & BYTE_MASK];
+ }
+ }
+ return crc;
+}
+
-+static u16 drv_rsa_key_crc(hi_u8 *n, hi_u8 *k, hi_u32 klen, hi_u32 randnum[2])
++static hi_u16 drv_rsa_key_crc(hi_u8 *n, hi_u8 *k, hi_u32 klen, hi_u32 randnum[MUL_VAL_2])
+{
+ hi_u32 i;
-+ u16 crc = 0;
++ hi_u16 crc = 0;
+
+ for (i = 0; i < klen; i += BLOCK_BYTES) {
+ crc = drv_rsa_crc16_block(crc, n + i, (hi_u8 *)randnum);
@@ -201825,101 +270933,106 @@ index 0000000..00ac25e
+
+#ifdef CRYPTO_OS_INT_SUPPORT
+
-+/*! set interrupt */
-+static void rsa_set_interrupt(void)
++/* set interrupt */
++static hi_void rsa_set_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ sec_rsa_int_en int_en;
+
+ module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, HI_NULL);
+ if (int_valid == HI_FALSE) {
+ return;
+ }
-+ if (rsainfo.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
++ if (g_rsa_info.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
+ return;
+ }
+
-+ int_en.u32 = IFEP_RSA_READ(REG_SEC_RSA_INT_EN);
++ int_en.u32 = ifep_rsa_read(REG_SEC_RSA_INT_EN);
+
-+ /*The top interrupt switch only can be enable/disable by secure CPU*/
++ /* The top interrupt switch only can be enable/disable by secure CPU. */
+ int_en.bits.rsa_int_en = 1;
+ int_en.bits.int_en = 1;
-+ IFEP_RSA_WRITE(REG_SEC_RSA_INT_EN, int_en.u32);
-+ HI_LOG_INFO("RSA_INT_EN: 0x%x\n", int_en.u32);
++ ifep_rsa_write(REG_SEC_RSA_INT_EN, int_en.u32);
++ hi_log_info("RSA_INT_EN: 0x%x\n", int_en.u32);
+
+ return;
+}
+
-+static hi_u32 drv_rsa_done_notify(void)
++static hi_void drv_rsa_done_notify(hi_void)
+{
+ sec_rsa_int_status int_st;
+ sec_rsa_int_raw int_raw;
+
-+ int_st.u32 = IFEP_RSA_READ(REG_SEC_RSA_INT_STATUS);
++ int_st.u32 = ifep_rsa_read(REG_SEC_RSA_INT_STATUS);
+ int_raw.u32 = 0x00;
+
-+ HI_LOG_DEBUG("REG_SEC_RSA_INT_STATUS: 0x%x\n", int_st.u32);
++ hi_log_debug("REG_SEC_RSA_INT_STATUS: 0x%x\n", int_st.u32);
++ crypto_unused(int_st.u32);
+
-+ /*Clean raw int*/
-+ int_raw.bits.rsa_int_raw = 1;
-+ IFEP_RSA_WRITE(REG_SEC_RSA_INT_RAW, int_raw.u32);
++ /* Clean raw interrupt. */
++ int_raw.bits.rsa_int_raw = RSA_INT_RAW_CLR;
++ ifep_rsa_write(REG_SEC_RSA_INT_RAW, int_raw.u32);
+
-+ return int_st.bits.rsa_int_status;
++ /* Clean error interrupt. */
++ ifep_rsa_write(REG_SEC_RSA_INT_ERR_CLR, RSA_INT_ERR_CLR);
+}
+
-+/*! rsa interrupt process function */
-+static irqreturn_t drv_rsa_interrupt_isr(hi_s32 irq, void *devId)
++/* rsa interrupt process function */
++static irqreturn_t drv_rsa_interrupt_isr(hi_s32 irq, hi_void *devId)
+{
-+ CRYPTO_UNUSED(irq);
++ crypto_unused(irq);
+
+ drv_rsa_done_notify();
+
-+ rsainfo.done = HI_TRUE;
-+ HI_LOG_DEBUG("rsa wake up\n");
-+ crypto_queue_wait_up(&rsainfo.queue);
++ g_rsa_info.done = HI_TRUE;
++ hi_log_debug("rsa wake up\n");
++ crypto_queue_wait_up(&g_rsa_info.queue);
+
+ return IRQ_HANDLED;
+}
+
-+/*! rsa register interrupt process function */
-+static hi_s32 drv_rsa_register_interrupt(void)
++/* rsa register interrupt process function */
++static hi_s32 drv_rsa_register_interrupt(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 int_valid = 0, int_num = 0;
-+ const char *name;
++ hi_s32 ret;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
++ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, &name);
+ if (int_valid == HI_FALSE) {
+ return HI_SUCCESS;
+ }
-+ if (rsainfo.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
++ if (g_rsa_info.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
+ return HI_SUCCESS;
+ }
+
+ /* request irq */
+ ret = crypto_request_irq(int_num, drv_rsa_interrupt_isr, name);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Irq request failure, irq = %d", int_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_REGISTER_IRQ);
++ hi_log_error("Irq request failure, irq = %d", int_num);
++ hi_log_print_err_code(HI_ERR_CIPHER_REGISTER_IRQ);
+ return ret;
+ }
+
-+ /* initialize queue list*/
-+ crypto_queue_init(&rsainfo.queue);
++ /* initialize queue list. */
++ crypto_queue_init(&g_rsa_info.queue);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/*! rsa unregister interrupt process function */
-+static void drv_rsa_unregister_interrupt(void)
++/* rsa unregister interrupt process function */
++static hi_void drv_rsa_unregister_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, &name);
+
@@ -201927,27 +271040,25 @@ index 0000000..00ac25e
+ return;
+ }
+
-+ if (rsainfo.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
++ if (g_rsa_info.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
+ return;
+ }
+
+ /* free irq */
-+ HI_LOG_INFO("rsa free irq, num %d, name %s\n", int_num, name);
++ hi_log_info("rsa free irq, num %d, name %s\n", int_num, name);
+ crypto_free_irq(int_num, name);
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+#endif
+
-+hi_s32 drv_rsa_init(void)
++hi_s32 drv_rsa_init(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("enable rsa\n");
++ hi_log_info("enable rsa\n");
+
-+ if (rsa_initialize == HI_TRUE) {
++ if (g_rsa_initialize == HI_TRUE) {
+ return HI_SUCCESS;
+ }
+
@@ -201960,35 +271071,35 @@ index 0000000..00ac25e
+ /* RSA request the TRNG must valid */
+ module_enable(CRYPTO_MODULE_ID_TRNG);
+
-+ rsainfo.rsa_sub_ver = IFEP_RSA_READ(REG_SEC_RSA_VERSION_ID);
-+ HI_LOG_INFO("rsa version 0x%x\n", rsainfo.rsa_sub_ver);
++ g_rsa_info.rsa_sub_ver = ifep_rsa_read(REG_SEC_RSA_VERSION_ID);
++ hi_log_info("rsa version 0x%x\n", g_rsa_info.rsa_sub_ver);
+ module_disable(CRYPTO_MODULE_ID_IFEP_RSA);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
+ {
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_INFO("rsa register interrupt function\n");
++ hi_log_info("rsa register interrupt function\n");
+ ret = drv_rsa_register_interrupt();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, register interrupt failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(drv_rsa_register_interrupt, ret);
++ hi_log_error("error, register interrupt failed\n");
++ hi_log_print_func_err(drv_rsa_register_interrupt, ret);
+ return ret;
+ }
+ }
+#endif
+
-+ rsa_initialize = HI_TRUE;
++ g_rsa_initialize = HI_TRUE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_rsa_deinit(void)
++hi_s32 drv_rsa_deinit(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if (rsa_initialize == HI_FALSE) {
++ if (g_rsa_initialize == HI_FALSE) {
+ return HI_SUCCESS;
+ }
+
@@ -201996,68 +271107,68 @@ index 0000000..00ac25e
+ drv_rsa_unregister_interrupt();
+#endif
+
-+ rsa_initialize = HI_FALSE;
++ g_rsa_initialize = HI_FALSE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static void drv_rsa_resume(void)
++static hi_void drv_rsa_resume(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_enable(CRYPTO_MODULE_ID_IFEP_RSA);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ HI_LOG_INFO("RSA interrupt configure\n");
++ hi_log_info("RSA interrupt configure\n");
+ rsa_set_interrupt();
+#endif
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static void drv_rsa_suspend(void)
++static hi_void drv_rsa_suspend(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_disable(CRYPTO_MODULE_ID_IFEP_RSA);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static void drv_rsa_set_width(rsa_key_width width)
++static hi_void drv_rsa_set_width(rsa_key_width width)
+{
+ sec_rsa_mod_reg ctrl;
+
+ ctrl.u32 = 0x00;
+ ctrl.bits.sec_rsa_mod_sel = RSA_MODE_EXP;
+ ctrl.bits.sec_rsa_key_width = width;
-+ IFEP_RSA_WRITE(REG_SEC_RSA_MOD_REG, ctrl.u32);
-+ HI_LOG_INFO("REG_SEC_RSA_MOD_REG 0x%x\n", ctrl.u32);
++ ifep_rsa_write(REG_SEC_RSA_MOD_REG, ctrl.u32);
++ hi_log_info("REG_SEC_RSA_MOD_REG 0x%x\n", ctrl.u32);
+ return;
+}
+
-+static hi_s32 drv_rsa_set_key(hi_u32 ca_type, hi_u8 *n, hi_u8 *d, hi_u32 klen, hi_u32 random[2])
++static hi_s32 drv_rsa_set_key(hi_u32 ca_type, hi_u8 *n, hi_u8 *d, hi_u32 klen, hi_u32 random[MUL_VAL_2])
+{
-+ hi_u32 i = 0, id = 0;
++ hi_u32 i;
++ hi_u32 id = 0;
+ hi_u32 val = 0x00;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ /**
++ /*
+ * The even word shell XOR with even random[0]
+ * The odd word shell XOR with odd random[1]
+ * The random may be zero.
+ * Must set N before set E.
+ * The E must padding with zero.
+ */
-+
-+ /* Set N */
+ for (i = 0; i < klen; i += WORD_WIDTH) {
++ /* Set N */
+ crypto_memcpy(&val, sizeof(hi_u32), n + i, WORD_WIDTH);
+ val ^= random[id];
-+ IFEP_RSA_WRITE(REG_SEC_RSA_WSEC_REG, val);
++ ifep_rsa_write(REG_SEC_RSA_WSEC_REG, val);
+
+ /* switch between even and odd */
+ id ^= 0x01;
@@ -202066,15 +271177,15 @@ index 0000000..00ac25e
+ /* Set D */
+ if (ca_type != HI_CIPHER_KEY_SRC_USER) {
+ ret = drv_cipher_klad_load_key(0, ca_type, HI_CIPHER_KLAD_TARGET_RSA, d, klen);
-+ if ( ret != HI_SUCCESS ) {
-+ HI_LOG_ERROR("drv_cipher_klad_load_key, error!\n");
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_cipher_klad_load_key, ret);
+ return ret;
+ }
+ } else {
+ for (i = 0; i < klen; i += WORD_WIDTH) {
+ crypto_memcpy(&val, sizeof(hi_u32), d + i, WORD_WIDTH);
+ val ^= random[id];
-+ IFEP_RSA_WRITE(REG_SEC_RSA_WSEC_REG, val);
++ ifep_rsa_write(REG_SEC_RSA_WSEC_REG, val);
+
+ /* switch between even and odd */
+ id ^= 0x01;
@@ -202083,28 +271194,27 @@ index 0000000..00ac25e
+ return HI_SUCCESS;
+}
+
-+static void drv_rsa_set_input(hi_u8 *in, hi_u32 klen)
++static hi_void drv_rsa_set_input(hi_u8 *in, hi_u32 klen)
+{
+ hi_u32 i = 0;
+ hi_u32 val = 0x00;
+
+ for (i = 0; i < klen; i += WORD_WIDTH) {
+ crypto_memcpy(&val, sizeof(hi_u32), in + i, WORD_WIDTH);
-+ IFEP_RSA_WRITE(REG_SEC_RSA_WDAT_REG, val);
++ ifep_rsa_write(REG_SEC_RSA_WDAT_REG, val);
+ }
+ return;
+}
+
-+static void drv_rsa_get_output(hi_u8 *out, hi_u32 klen)
++static hi_void drv_rsa_get_output(hi_u8 *out, hi_u32 klen)
+{
-+ hi_u32 i = 0;
-+ hi_u32 val = 0x00;
++ hi_u32 i;
++ hi_u32 val;
+
-+ for (i = 0; i < klen; i += 4) {
-+ val = IFEP_RSA_READ(REG_SEC_RSA_RRSLT_REG);
-+ crypto_memcpy(out + i, sizeof(hi_u32), &val, 4);
++ for (i = 0; i < klen; i += WORD_WIDTH) {
++ val = ifep_rsa_read(REG_SEC_RSA_RRSLT_REG);
++ crypto_memcpy(out + i, sizeof(hi_u32), &val, sizeof(hi_u32));
+ }
-+ return;
+}
+
+static hi_u32 drv_rsa_get_klen(rsa_key_width width)
@@ -202112,7 +271222,6 @@ index 0000000..00ac25e
+ hi_u32 klen = 0x00;
+
+ /* nonsupport rsa 3072, can compute it as 4096 */
-+
+ switch (width) {
+ case RSA_KEY_WIDTH_1024: {
+ klen = RSA_KEY_LEN_1024;
@@ -202127,7 +271236,7 @@ index 0000000..00ac25e
+ break;
+ }
+ default: {
-+ HI_LOG_ERROR("error, nonsupport RSA width %d\n", width);
++ hi_log_error("error, nonsupport RSA width %d\n", width);
+ klen = 0;
+ break;
+ }
@@ -202136,59 +271245,58 @@ index 0000000..00ac25e
+ return klen;
+}
+
-+static void drv_rsa_start(void)
++static hi_void drv_rsa_start(hi_void)
+{
+ sec_rsa_start_reg start;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ rsainfo.done = HI_FALSE;
++ g_rsa_info.done = HI_FALSE;
+
+ start.u32 = 0x00;
+
-+ if (rsainfo.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
++ if (g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
+ start.bits.sec_rsa_start_reg = 0x05;
+ } else {
+ start.bits.sec_rsa_start_reg = 0x01;
+ }
+
-+ IFEP_RSA_WRITE(REG_SEC_RSA_START_REG, start.u32);
-+ HI_LOG_INFO("REG_SEC_RSA_START_REG 0x%x\n", start.u32);
++ ifep_rsa_write(REG_SEC_RSA_START_REG, start.u32);
++ hi_log_info("REG_SEC_RSA_START_REG 0x%x\n", start.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+static hi_s32 drv_rsa_wait_done(void)
++static hi_s32 drv_rsa_wait_done(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ hi_u32 i;
+ sec_rsa_busy_reg ready;
+ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, &name);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ /* interrupt support, wait irq*/
-+ if ((rsainfo.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) && (int_valid == HI_TRUE)) {
-+ hi_s32 ret = HI_FAILURE;
++ /* interrupt support, wait irq. */
++ if ((g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) && (int_valid == HI_TRUE)) {
++ hi_s32 ret;
+
+ /* wait interrupt */
-+ ret = crypto_queue_wait_timeout(rsainfo.queue, &rsainfo.done, RSA_TIME_OUT);
++ ret = crypto_queue_wait_timeout(g_rsa_info.queue, &g_rsa_info.done, RSA_TIME_OUT);
+ if ((ret <= 0x00) && (ret != -ERESTARTSYS)) {
-+ HI_LOG_ERROR("wait done timeout\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_queue_wait_timeout, ret);
++ hi_log_error("wait done timeout\n");
++ hi_log_print_func_err(crypto_queue_wait_timeout, ret);
+ return HI_ERR_CIPHER_TIMEOUT;
+ }
-+ } else
-+#endif
-+ {
++ } else {
+ /* wait ready */
+ for (i = 0; i < RSA_TIME_OUT; i++) {
-+ ready.u32 = IFEP_RSA_READ(REG_SEC_RSA_BUSY_REG);
++ ready.u32 = ifep_rsa_read(REG_SEC_RSA_BUSY_REG);
+ if (!ready.bits.sec_rsa_busy_reg) {
+ break;
+ }
@@ -202196,55 +271304,69 @@ index 0000000..00ac25e
+ }
+
+ if (i >= RSA_TIME_OUT) {
-+ HI_LOG_ERROR("error, rsa wait free timeout\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_TIMEOUT);
++ hi_log_error("error, rsa wait free timeout\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
+ return HI_ERR_CIPHER_TIMEOUT;
+ }
+ }
++#else
++ /* wait ready */
++ for (i = 0; i < RSA_TIME_OUT; i++) {
++ ready.u32 = ifep_rsa_read(REG_SEC_RSA_BUSY_REG);
++ if (!ready.bits.sec_rsa_busy_reg) {
++ break;
++ }
++ crypto_msleep(1);
++ }
+
-+ HI_LOG_FUNC_EXIT();
++ if (i >= RSA_TIME_OUT) {
++ hi_log_error("error, rsa wait free timeout\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
++#endif
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static void drv_rsa_randnum(hi_u8 *n, hi_u8 *k, hi_u32 klen, hi_u32 random[2])
++static hi_void drv_rsa_randnum(hi_u8 *n, hi_u8 *k, hi_u32 klen, hi_u32 random[MUL_VAL_2])
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+#ifdef RSA_RAND_MASK
-+ if (rsainfo.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
-+ u16 crc16 = 0;
++ if (g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
++ hi_u16 crc16 = 0;
+
+ random[0] = get_rand();
+ random[1] = get_rand();
+
+ crc16 = drv_rsa_key_crc(n, k, klen, random);
-+ HI_LOG_INFO("random 0x%x 0x%x, CRC16: 0x%x\n", random[0], random[1], crc16);
-+ IFEP_RSA_WRITE(REG_SEC_RSA_KEY_RANDOM_1, random[0]);
-+ IFEP_RSA_WRITE(REG_SEC_RSA_KEY_RANDOM_2, random[1]);
-+ IFEP_RSA_WRITE(REG_SEC_RSA_CRC16_REG, crc16);
-+ } else
-+#endif
-+ {
-+ random[0] = 0x00;
-+ random[1] = 0x00;
++ hi_log_info("random 0x%x 0x%x, CRC16: 0x%x\n", random[WORD_IDX_0], random[WORD_IDX_1], crc16);
++ ifep_rsa_write(REG_SEC_RSA_KEY_RANDOM_1, random[WORD_IDX_0]);
++ ifep_rsa_write(REG_SEC_RSA_KEY_RANDOM_2, random[WORD_IDX_1]);
++ ifep_rsa_write(REG_SEC_RSA_CRC16_REG, crc16);
++ } else {
++ random[WORD_IDX_0] = 0x00;
++ random[WORD_IDX_1] = 0x00;
+ }
-+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++#else
++ random[WORD_IDX_0] = 0x00;
++ random[WORD_IDX_1] = 0x00;
++#endif
++ hi_log_func_exit();
+}
+
-+static hi_s32 drv_rsa_clean_ram(void)
++static hi_s32 drv_rsa_clean_ram(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ sec_rsa_mod_reg ctrl;
+
-+ ctrl.u32 = IFEP_RSA_READ(REG_SEC_RSA_MOD_REG);
++ ctrl.u32 = ifep_rsa_read(REG_SEC_RSA_MOD_REG);
+ ctrl.bits.sec_rsa_mod_sel = RSA_MODE_CLEAR_RAM;
-+ ctrl.bits.sec_rsa_data0_clr = 1;
-+ ctrl.bits.sec_rsa_data1_clr = 1;
-+ ctrl.bits.sec_rsa_data2_clr = 1;
-+ IFEP_RSA_WRITE(REG_SEC_RSA_MOD_REG, ctrl.u32);
++ ctrl.bits.sec_rsa_data0_clr = RSA_CLR_RAM_STORED_KEY;
++ ctrl.bits.sec_rsa_data1_clr = RSA_CLR_RAM_STORED_MSG;
++ ctrl.bits.sec_rsa_data2_clr = RSA_CLR_RAM_STORED_RESULT;
++ ifep_rsa_write(REG_SEC_RSA_MOD_REG, ctrl.u32);
+
+ /* start */
+ drv_rsa_start();
@@ -202252,50 +271374,45 @@ index 0000000..00ac25e
+ /* wait done */
+ ret = drv_rsa_wait_done();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_rsa_wait_done, ret);
++ hi_log_print_func_err(drv_rsa_wait_done, ret);
+ return ret;
+ }
+
+ return HI_SUCCESS;
+}
+
-+static hi_s32 drv_rsa_error_code(void)
++static hi_s32 drv_rsa_error_code(hi_void)
+{
-+ hi_u32 code = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_log_func_enter();
+
-+ HI_LOG_FUNC_ENTER();
++ if (g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
++ hi_u32 code;
+
-+ if (rsainfo.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
-+ code = IFEP_RSA_READ(REG_SEC_RSA_ERROR_REG);
++ code = ifep_rsa_read(REG_SEC_RSA_ERROR_REG);
++ if (code != 0) {
++ hi_log_error("rsa error code: 0x%x.\n", code);
++ hi_log_print_err_code(HI_ERR_CIPHER_HARD_STATUS);
++ return HI_ERR_CIPHER_HARD_STATUS;
++ }
+ }
+
-+ if (code == 0x00) {
-+ ret = HI_SUCCESS;
-+ } else {
-+ HI_LOG_ERROR("rsa error code: 0x%x\n", code);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_HARD_STATUS);
-+ return HI_ERR_CIPHER_HARD_STATUS;
-+ }
-+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return ret;
++ hi_log_func_exit();
++ return HI_SUCCESS;
+}
+
+hi_s32 drv_ifep_rsa_exp_mod(hi_u32 ca_type, hi_u8 *n, hi_u8 *k, hi_u8 *in, hi_u8 *out, rsa_key_width width)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 klen = 0;
-+ hi_u32 random[2] = {0, 0};
++ hi_s32 ret, ret_exit;
++ hi_u32 klen;
++ hi_u32 random[MUL_VAL_2] = {0, 0};
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(rsa_initialize);
++ hi_log_chk_init_err_return(g_rsa_initialize);
+
+ klen = drv_rsa_get_klen(width);
+ if (klen == 0) {
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ drv_rsa_resume();
@@ -202309,7 +271426,7 @@ index 0000000..00ac25e
+ /* set rsa key */
+ ret = drv_rsa_set_key(ca_type, n, k, klen, random);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_rsa_set_key, ret);
++ hi_log_print_func_err(drv_rsa_set_key, ret);
+ ret = HI_ERR_CIPHER_ILLEGAL_KEY;
+ goto exit;
+ }
@@ -202323,7 +271440,7 @@ index 0000000..00ac25e
+ /* wait done */
+ ret = drv_rsa_wait_done();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_rsa_wait_done, ret);
++ hi_log_print_func_err(drv_rsa_wait_done, ret);
+ ret = HI_ERR_CIPHER_TIMEOUT;
+ goto exit;
+ }
@@ -202334,15 +271451,19 @@ index 0000000..00ac25e
+ ret = drv_rsa_error_code();
+exit:
+ /* clean key and data */
-+ (void)drv_rsa_clean_ram();
++ ret_exit = drv_rsa_clean_ram();
++ if (ret_exit != HI_SUCCESS) {
++ hi_log_print_func_err(drv_rsa_clean_ram, ret_exit);
++ }
++
+ drv_rsa_suspend();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ret;
+}
+
-+void drv_ifep_rsa_get_capacity(rsa_capacity *capacity)
++hi_void drv_ifep_rsa_get_capacity(rsa_capacity *capacity)
+{
+ crypto_memset(capacity, sizeof(rsa_capacity), 0, sizeof(rsa_capacity));
+
@@ -202350,32 +271471,18 @@ index 0000000..00ac25e
+
+ return;
+}
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
-+#endif //End of CHIP_RSA_VER_V100
++#endif /* End of CHIP_RSA_VER_V100 */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_ifep_rsa_v100.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_ifep_rsa_v100.h
new file mode 100644
-index 0000000..86c6fbf
+index 0000000..12d2da7
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_ifep_rsa_v100.h
-@@ -0,0 +1,131 @@
+@@ -0,0 +1,121 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv ifep rsa v100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef _DRV_RSA_V1_H_
@@ -202383,212 +271490,199 @@ index 0000000..86c6fbf
+
+#include "drv_osal_lib.h"
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup rsa drivers*/
-+/** @{*/ /** <!-- [rsa]*/
++/* ************************** Internal Structure Definition *************************** */
++/* Define the offset of reg */
++#define REG_SEC_RSA_BUSY_REG 0x50
++#define REG_SEC_RSA_MOD_REG 0x54
++#define REG_SEC_RSA_WSEC_REG 0x58
++#define REG_SEC_RSA_WDAT_REG 0x5c
++#define REG_SEC_RSA_RPKT_REG 0x60
++#define REG_SEC_RSA_RRSLT_REG 0x64
++#define REG_SEC_RSA_START_REG 0x68
++#define REG_SEC_RSA_ADDR_REG 0x6C
++#define REG_SEC_RSA_ERROR_REG 0x70
++#define REG_SEC_RSA_CRC16_REG 0x74
++#define REG_SEC_RSA_KEY_RANDOM_1 0x7c
++#define REG_SEC_RSA_INT_EN 0x80
++#define REG_SEC_RSA_INT_STATUS 0x84
++#define REG_SEC_RSA_INT_RAW 0x88
++#define REG_SEC_RSA_INT_ERR_CLR 0x8c
++#define REG_SEC_RSA_VERSION_ID 0x90
++#define REG_SEC_RSA_KEY_RANDOM_2 0x94
+
-+/*! \Define the offset of reg */
-+#define REG_SEC_RSA_BUSY_REG (0x50)
-+#define REG_SEC_RSA_MOD_REG (0x54)
-+#define REG_SEC_RSA_WSEC_REG (0x58)
-+#define REG_SEC_RSA_WDAT_REG (0x5c)
-+#define REG_SEC_RSA_RPKT_REG (0x60)
-+#define REG_SEC_RSA_RRSLT_REG (0x64)
-+#define REG_SEC_RSA_START_REG (0x68)
-+#define REG_SEC_RSA_ADDR_REG (0x6C)
-+#define REG_SEC_RSA_ERROR_REG (0x70)
-+#define REG_SEC_RSA_CRC16_REG (0x74)
-+#define REG_SEC_RSA_KEY_RANDOM_1 (0x7c)
-+#define REG_SEC_RSA_INT_EN (0x80)
-+#define REG_SEC_RSA_INT_STATUS (0x84)
-+#define REG_SEC_RSA_INT_RAW (0x88)
-+#define REG_SEC_RSA_INT_ERR_CLR (0x8c)
-+#define REG_SEC_RSA_VERSION_ID (0x90)
-+#define REG_SEC_RSA_KEY_RANDOM_2 (0x94)
++#define RSA_INT_RAW_CLR 1
++#define RSA_INT_ERR_CLR 1
+
-+/*! \Define the union sec_rsa_busy_reg */
++/* Clear the RAM data of the stored result. */
++#define RSA_CLR_RAM_STORED_RESULT 1
++
++/* Clear the RAM data of the stored message. */
++#define RSA_CLR_RAM_STORED_MSG 1
++
++/* Clear the RAM data of the storage key. */
++#define RSA_CLR_RAM_STORED_KEY 1
++
++/* Define the union sec_rsa_busy_reg */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
-+ hi_u32 sec_rsa_busy_reg : 1 ; /* [0] */
-+ hi_u32 reserved_1 : 31 ; /* [31..1] */
++ hi_u32 sec_rsa_busy_reg : 1 ; /* [0] */
++ hi_u32 reserved_1 : 31 ; /* [31..1] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} sec_rsa_busy_reg;
+
-+/*! \Define the union sec_rsa_mod_reg */
++/* Define the union sec_rsa_mod_reg */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
-+ hi_u32 sec_rsa_mod_sel : 2 ; /* [1..0] */
-+ hi_u32 sec_rsa_key_width : 2 ; /* [3..2] */
++ hi_u32 sec_rsa_mod_sel : 2 ; /* [1..0] */
++ hi_u32 sec_rsa_key_width : 2 ; /* [3..2] */
+ hi_u32 sec_rsa_data0_clr : 1 ; /* [4] */
+ hi_u32 sec_rsa_data1_clr : 1 ; /* [5] */
+ hi_u32 sec_rsa_data2_clr : 1 ; /* [6] */
-+ hi_u32 reserved_1 : 25 ; /* [31..7] */
++ hi_u32 reserved_1 : 25 ; /* [31..7] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} sec_rsa_mod_reg;
+
-+/*! \Define the union sec_rsa_start_reg */
++/* Define the union sec_rsa_start_reg */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
-+ hi_u32 sec_rsa_start_reg : 4 ; /* [3..0] */
-+ hi_u32 reserved_1 : 28 ; /* [31..4] */
++ hi_u32 sec_rsa_start_reg : 4 ; /* [3..0] */
++ hi_u32 reserved_1 : 28 ; /* [31..4] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} sec_rsa_start_reg;
+
+/* Define the union sec_rsa_int_en */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int rsa_int_en : 1 ; /* [0] */
-+ unsigned int reserved_0 : 30 ; /* [30..1] */
-+ unsigned int int_en : 1 ; /* [31] */
++ hi_u32 rsa_int_en : 1 ; /* [0] */
++ hi_u32 reserved_0 : 30 ; /* [30..1] */
++ hi_u32 int_en : 1 ; /* [31] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} sec_rsa_int_en;
+
+/* Define the union sec_rsa_int_status */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int rsa_int_status : 1 ; /* [0] */
-+ unsigned int reserved_0 : 31 ; /* [31..1] */
++ hi_u32 rsa_int_status : 1 ; /* [0] */
++ hi_u32 reserved_0 : 31 ; /* [31..1] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} sec_rsa_int_status;
+
+/* Define the union sec_rsa_int_raw */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int rsa_int_raw : 1 ; /* [0] */
-+ unsigned int reserved_0 : 31 ; /* [31..1] */
++ hi_u32 rsa_int_raw : 1 ; /* [0] */
++ hi_u32 reserved_0 : 31 ; /* [31..1] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
-+
++ hi_u32 u32;
+} sec_rsa_int_raw;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_lib.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_lib.c
new file mode 100644
-index 0000000..4c57e2c
+index 0000000..26a26aa
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_lib.c
-@@ -0,0 +1,679 @@
+@@ -0,0 +1,684 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv lib.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
+#include "cryp_trng.h"
+
-+/*********************** Internal Structure Definition ***********************/
-+/** \addtogroup base type*/
-+/** @{*/ /** <!-- [base]*/
++/* ********************** Internal Structure Definition ********************** */
++/* crg register addr size. */
++#define CRG_REG_ADDR_SIZE 0x100
+
-+/*crg register addr size*/
-+#define CRG_REG_ADDR_SIZE (0x100)
++/* set a bit within a word. */
++#undef set_bit
++#define set_bit(src, bit) ((src) |= (1 << (bit)))
+
-+/*set a bit within a word*/
-+#undef SET_BIT
-+#define SET_BIT(src, bit) ((src) |= (1 << (bit)))
++/* clear a bit within a word. */
++#undef clear_bit
++#define clear_bit(src, bit) ((src) &= ~(1 << (bit)))
+
-+/*clear a bit within a word*/
-+#undef CLEAR_BIT
-+#define CLEAR_BIT(src,bit) ((src) &= ~(1 << (bit)))
++/* module already initialize or not. */
++static hi_u32 g_module_initialize = HI_FALSE;
+
-+/*! module already initialize or not */
-+static hi_u32 module_initialize = HI_FALSE;
-+
-+/*! \struct resource_channel
++/* struct resource_channel
+ * the tbale of base info of module, such as addr/reset/clk/ver.
-+*/
++ */
+struct sys_arch_hardware_info {
-+ /*the name of module, used for debug print and request interrupt*/
-+ const char *name;
++ /* the name of module, used for debug print and request interrupt. */
++ const hi_char *name;
+
-+ /*smoe field may be needn't to used*/
-+ hi_u32 reset_valid: 1; /*bis[0], reset availability, 0-valid, 1-invalid*/
-+ hi_u32 clk_valid: 1; /*bis[1], clock availability, 0-valid, 1-invalid*/
-+ hi_u32 phy_valid: 1; /*bis[2], system address availability, 0-valid, 1-invalid*/
-+ hi_u32 crg_valid: 1; /*bis[3], CRG availability, 0-valid, 1-invalid*/
-+ hi_u32 ver_valid: 1; /*bis[4], version reg availability, 0-valid, 1-invalid*/
-+ hi_u32 int_valid: 1; /*bis[5], interrupt availability, 0-valid, 1-invalid*/
-+ hi_u32 res_valid: 25; /*bis[6..31]*/
++ /* smoe field may be needn't to used. */
++ hi_u32 reset_valid: 1; /* bis[0], reset availability, 0-valid, 1-invalid. */
++ hi_u32 clk_valid: 1; /* bis[1], clock availability, 0-valid, 1-invalid. */
++ hi_u32 phy_valid: 1; /* bis[2], system address availability, 0-valid, 1-invalid. */
++ hi_u32 crg_valid: 1; /* bis[3], CRG availability, 0-valid, 1-invalid. */
++ hi_u32 ver_valid: 1; /* bis[4], version reg availability, 0-valid, 1-invalid. */
++ hi_u32 int_valid: 1; /* bis[5], interrupt availability, 0-valid, 1-invalid. */
++ hi_u32 res_valid: 25; /* bis[6..31]. */
+
-+ /*module base addr*/
++ /* module base addr. */
+ hi_u32 reg_addr_phy;
+
-+ /*base logic addr size*/
++ /* base logic addr size. */
+ hi_u32 reg_addr_size;
+
-+ /*crg register addr, which provide the switch of reset and clock*/
++ /* crg register addr, which provide the switch of reset and clock. */
+ hi_u32 crg_addr_phy;
+
-+ /*the clk switch bit index within the crg register,
-+ *if the switch bis is provided by second crg register, you need to add 32*/
++ /* the clk switch bit index within the crg register,
++ * if the switch bis is provided by second crg register, you need to add 32. */
+ hi_u32 clk_bit: 8;
+
-+ /*the reset switch bit index within the crg register,
-+ * if the switch bis is provided by second crg register, you need to add 32*/
++ /* the reset switch bit index within the crg register,
++ * if the switch bis is provided by second crg register, you need to add 32. */
+ hi_u32 reset_bit: 8;
+
-+ /*the interrupt number*/
++ /* the interrupt number. */
+ hi_u32 int_num: 8;
+
-+ /*the reserve bits*/
++ /* the reserve bits. */
+ hi_u32 res: 8;
+
-+ /*the offset of version register*/
++ /* the offset of version register. */
+ hi_u32 version_reg;
+
-+ /*the value of version register, you can used it to check the active module*/
++ /* the value of version register, you can used it to check the active module. */
+ hi_u32 version_val;
+
-+ /*cpu address of module register*/
-+ void *reg_addr_via;
++ /* cpu address of module register. */
++ hi_void *reg_addr_via;
+
-+ /*cpu address of crg register*/
-+ void *crg_addr_via;
++ /* cpu address of crg register. */
++ hi_void *crg_addr_via;
+};
+
-+static struct sys_arch_hardware_info hard_info_table[CRYPTO_MODULE_ID_CNT] = {
++static struct sys_arch_hardware_info g_hard_info_table[CRYPTO_MODULE_ID_CNT] = {
+ HARD_INFO_CIPHER,
+ HARD_INFO_CIPHER_KEY,
+ HARD_INFO_HASH,
@@ -202601,7 +271695,7 @@ index 0000000..4c57e2c
+};
+
+#ifdef CRYPTO_SWITCH_CPU
-+static struct sys_arch_hardware_info nsec_hard_info_table[CRYPTO_MODULE_ID_CNT] = {
++static struct sys_arch_hardware_info g_nsec_hard_info_table[CRYPTO_MODULE_ID_CNT] = {
+ NSEC_HARD_INFO_CIPHER,
+ NSEC_HARD_INFO_CIPHER_KEY,
+ NSEC_HARD_INFO_HASH,
@@ -202613,399 +271707,387 @@ index 0000000..4c57e2c
+ NSEC_HARD_INFO_SMMU,
+};
+
-+static hi_u32 s_secure_cpu = HI_FALSE;
++static hi_u32 g_is_secure_cpu = HI_FALSE;
+#endif
+
-+compat_addr compat_addr_zero = {.phy = 0};
-+
-+extern hi_u32 drv_symc_is_secure(void);
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup base*/
-+/** @{*/ /** <!--[base]*/
-+
-+static hi_s32 module_addr_map_reg(void)
++/* ****************************** API Code **************************** */
++static hi_s32 module_addr_map_reg(hi_void)
+{
+ hi_u32 i;
-+ hi_s32 ret = HI_SUCCESS;
+ struct sys_arch_hardware_info *table = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if (module_initialize == HI_TRUE) {
++ if (g_module_initialize == HI_TRUE) {
+ return HI_SUCCESS;
+ }
+
+ for (i = 0; i < CRYPTO_MODULE_ID_CNT; i++) {
-+ table = &hard_info_table[i];
++ table = &g_hard_info_table[i];
+
-+ HI_LOG_INFO("[%d] %s\n", i, table->name);
++ hi_log_info("[%d] %s\n", i, table->name);
+
-+ /*io remap crg register*/
++ /* io remap crg register. */
+ if (table->crg_valid) {
+ table->crg_addr_via = crypto_ioremap_nocache(table->crg_addr_phy, CRG_REG_ADDR_SIZE);
+ if (table->crg_addr_via == HI_NULL) {
-+ HI_LOG_ERROR("iomap reg of module failed\n");
++ hi_log_error("iomap reg of module failed\n");
+ module_addr_unmap();
-+ ret = HI_FAILURE;
-+ break;
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
-+ HI_LOG_INFO("crg phy 0x%x, via 0x%p\n", table->crg_addr_phy, table->crg_addr_via);
++ hi_log_info("crg phy 0x%x, via 0x%p\n", table->crg_addr_phy, table->crg_addr_via);
+ }
+
-+ /*io remap module register*/
++ /* io remap module register. */
+ if (table->phy_valid) {
+ table->reg_addr_via = crypto_ioremap_nocache(table->reg_addr_phy,
+ table->reg_addr_size);
+ if (table->reg_addr_via == HI_NULL) {
-+ HI_LOG_ERROR("iomap reg of module failed\n");
++ hi_log_error("iomap reg of module failed\n");
+ module_addr_unmap();
-+ ret = HI_FAILURE;
-+ break;
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
-+ HI_LOG_INFO("reg phy 0x%x, via 0x%p, size 0x%x\n", table->reg_addr_phy,
++ hi_log_info("reg phy 0x%x, via 0x%p, size 0x%x\n", table->reg_addr_phy,
+ table->reg_addr_via, table->reg_addr_size);
+ }
+ }
+
-+ module_initialize = HI_TRUE;
-+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return ret;
++ g_module_initialize = HI_TRUE;
++ hi_log_func_exit();
++ return HI_SUCCESS;
+}
+
-+/**
-+\brief unmap the physics addr to cpu within the base table, contains the base addr and crg addr.
-+*/
-+hi_s32 module_addr_unmap(void)
++/*
++ * brief unmap the physics addr to cpu within the base table, contains the base addr and crg addr.
++ */
++hi_s32 module_addr_unmap(hi_void)
+{
+ hi_u32 i;
+ struct sys_arch_hardware_info *table = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if (module_initialize == HI_FALSE) {
++ if (g_module_initialize == HI_FALSE) {
+ return HI_SUCCESS;
+ }
+
+ for (i = 0; i < CRYPTO_MODULE_ID_CNT; i++) {
-+ table = &hard_info_table[i];
++ table = &g_hard_info_table[i];
+
-+ HI_LOG_INFO("[%d] %s\n", i, table->name);
++ hi_log_info("[%d] %s\n", i, table->name);
+
-+ /*io unmap crg register*/
++ /* io unmap crg register. */
+ if (table->crg_valid && table->crg_addr_via) {
-+ HI_LOG_INFO("crg via addr 0x%p\n", table->crg_addr_via);
++ hi_log_info("crg via addr 0x%p\n", table->crg_addr_via);
+ crypto_iounmap(table->crg_addr_via, CRG_REG_ADDR_SIZE);
+ table->crg_addr_via = HI_NULL;
+ }
+
-+ /*io unmap module register*/
++ /* io unmap module register. */
+ if (table->phy_valid && table->reg_addr_via) {
-+ HI_LOG_INFO("reg via addr 0x%p\n", table->reg_addr_via);
++ hi_log_info("reg via addr 0x%p\n", table->reg_addr_via);
+ crypto_iounmap(table->reg_addr_via, table->reg_addr_size);
+ table->reg_addr_via = HI_NULL;
+ }
+ }
+
-+ module_initialize = HI_FALSE;
++ g_module_initialize = HI_FALSE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/**
-+\brief map the physics addr to cpu within the base table, contains the base addr and crg addr.
-+*/
-+hi_s32 module_addr_map(void)
++/*
++ * brief map the physics addr to cpu within the base table, contains the base addr and crg addr.
++ */
++hi_s32 module_addr_map(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ret = module_addr_map_reg();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(module_addr_map_reg, ret);
++ hi_log_print_func_err(module_addr_map_reg, ret);
+ return ret;
+ }
+
+#ifdef CRYPTO_SWITCH_CPU
-+ s_secure_cpu = drv_symc_is_secure();
-+ if (s_secure_cpu == HI_TRUE) {
++ g_is_secure_cpu = drv_symc_is_secure();
++ if (g_is_secure_cpu == HI_TRUE) {
+ /* default secure cpu, do nothing */
+ return HI_SUCCESS;
+ }
+
-+ HI_LOG_INFO("non-secure CPU need to remap reg addr\n");
++ hi_log_info("non-secure CPU need to remap reg addr\n");
+
+ /* use non-secure info */
-+ crypto_memcpy(&hard_info_table, sizeof(hard_info_table),
-+ &nsec_hard_info_table, sizeof(nsec_hard_info_table));
++ crypto_memcpy(&g_hard_info_table, sizeof(g_hard_info_table),
++ &g_nsec_hard_info_table, sizeof(g_nsec_hard_info_table));
+
+ /* remap module addr */
+ ret = module_addr_unmap();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(module_addr_unmap, ret);
++ hi_log_print_func_err(module_addr_unmap, ret);
+ return ret;
+ }
+ ret = module_addr_map_reg();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(module_addr_map, ret);
++ hi_log_print_func_err(module_addr_map, ret);
+ return ret;
+ }
+#endif
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/**
-+\brief get secure cpu type.
-+*/
-+hi_u32 module_get_secure(void)
++/*
++ * brief get secure cpu type.
++ */
++hi_u32 module_get_secure(hi_void)
+{
+#ifdef CRYPTO_SEC_CPU
+ return HI_TRUE;
+#elif defined(CRYPTO_SWITCH_CPU)
-+ return s_secure_cpu;
++ return g_is_secure_cpu;
+#else
+ return HI_FALSE;
+#endif
+}
+
-+/**
-+\brief open clock.
-+*/
-+static void module_clock(module_id id, hi_u32 open)
++/*
++ * brief open clock.
++ */
++static hi_void module_clock(module_id id, hi_u32 open)
+{
+ hi_u32 val = 0;
+ hi_u32 *addr = HI_NULL;
+ struct sys_arch_hardware_info *table = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ table = &hard_info_table[id];
++ table = &g_hard_info_table[id];
+
+ if (table->clk_valid) {
+ if (table->crg_addr_via == HI_NULL) {
-+ HI_LOG_ERROR("\033[0;1;31m""%s clock failed, crg addr is null\n""\033[0m", table->name);
++ hi_log_error("\033[0;1;31m""%s clock failed, crg addr is null\n""\033[0m", table->name);
+ return;
+ }
+
-+ /*open clk, the addr may be need to add 1*/
++ /* open clk, the addr may be need to add 1. */
+ addr = table->crg_addr_via;
+ addr += table->clk_bit / WORD_BIT_WIDTH;
+
+ val = crypto_read(addr);
+
+ if (open) {
-+ SET_BIT(val, table->clk_bit % WORD_BIT_WIDTH);
++ set_bit(val, table->clk_bit % WORD_BIT_WIDTH);
+ } else {
-+ CLEAR_BIT(val, table->clk_bit % WORD_BIT_WIDTH);
++ clear_bit(val, table->clk_bit % WORD_BIT_WIDTH);
+ }
+
+ crypto_write(addr, val);
+
-+ /*wait hardware clock active*/
++ /* wait hardware clock active. */
+ crypto_msleep(1);
+
-+ HI_LOG_INFO("%s clock, open %d, bit %d, phy 0x%x, via 0x%p\n",
++ hi_log_info("%s clock, open %u, bit %u, phy 0x%x, via 0x%p\n",
+ table->name, open, table->clk_bit,
+ table->crg_addr_phy, table->crg_addr_via);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+static void module_reset(module_id id, hi_u32 enable)
++static hi_void module_reset(module_id id, hi_u32 enable)
+{
+ hi_u32 val = 0;
+ hi_u32 *addr = HI_NULL;
+ hi_u32 expect = 0;
+ struct sys_arch_hardware_info *table = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ table = &hard_info_table[id];
++ table = &g_hard_info_table[id];
+
+ if (table->reset_valid) {
+ if (table->crg_addr_via == HI_NULL) {
-+ HI_LOG_ERROR("\033[0;1;31m""%s reset failed, crg addr is null\n""\033[0m", table->name);
++ hi_log_error("\033[0;1;31m""%s reset failed, crg addr is null\n""\033[0m", table->name);
+ return;
+ }
+
-+ /*the addr may be need to add 1*/
++ /* the addr may be need to add 1. */
+ addr = table->crg_addr_via;
+ addr += table->reset_bit / WORD_BIT_WIDTH;
+
+ val = crypto_read(addr);
+
+ if (enable) {
-+ SET_BIT(val, table->reset_bit % WORD_BIT_WIDTH);
++ set_bit(val, table->reset_bit % WORD_BIT_WIDTH);
+ expect = 0;
+ } else {
-+ CLEAR_BIT(val, table->reset_bit % WORD_BIT_WIDTH);
++ clear_bit(val, table->reset_bit % WORD_BIT_WIDTH);
+ expect = table->version_val;
+ }
+
+ crypto_write(addr, val);
+
-+ /*wait hardware reset finish*/
++ /* wait hardware reset finish. */
+ crypto_msleep(1);
+
-+ HI_LOG_INFO("%s reset, enable %d, bit %d, phy 0x%x, via 0x%p\n",
++ hi_log_info("%s reset, enable %u, bit %u, phy 0x%x, via 0x%p\n",
+ table->name, enable, table->reset_bit,
+ table->crg_addr_phy, table->crg_addr_via);
+
-+ /*check the value of version reg to make sure reset success*/
++ /* check the value of version reg to make sure reset success. */
+ if (table->ver_valid && table->reg_addr_via) {
+ val = crypto_read((hi_u8 *)table->reg_addr_via + table->version_reg);
+ if (val != expect) {
-+ HI_LOG_ERROR("\033[0;1;31m""%s reset failed, version reg should be 0x%x but 0x%x\n""\033[0m",
++ hi_log_error("\033[0;1;31m""%s reset failed, version reg should be 0x%x but 0x%x\n""\033[0m",
+ table->name, expect, val);
+ return;
+ }
+
-+ HI_LOG_INFO("%s version reg, offset 0x%x, expect val 0x%x, real val 0x%x\n",
++ hi_log_info("%s version reg, offset 0x%x, expect val 0x%x, real val 0x%x\n",
+ table->name, table->version_reg, expect, val);
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+/**
-+\brief enable a module, open clock and remove reset signal.
-+*/
-+void module_enable(module_id id)
++/*
++ * brief enable a module, open clock and remove reset signal.
++ */
++hi_void module_enable(module_id id)
+{
+ module_clock(id, HI_TRUE);
+ module_reset(id, HI_FALSE);
+ return;
+}
+
-+/**
-+\brief disable a module, close clock and set reset signal.
-+*/
-+void module_disable(module_id id)
++/*
++ * brief disable a module, close clock and set reset signal.
++ */
++hi_void module_disable(module_id id)
+{
+ module_reset(id, HI_TRUE);
+ module_clock(id, HI_FALSE);
+ return;
+}
+
-+/**
-+\brief get attribute of module.
-+*/
-+void module_get_attr(module_id id, hi_u32 *int_valid, hi_u32 *int_num, const char **name)
++/*
++ * brief get attribute of module.
++ */
++hi_void module_get_attr(module_id id, hi_u32 *int_valid, hi_u32 *int_num, const hi_char **name)
+{
-+ *int_valid = hard_info_table[id].int_valid;
-+ *int_num = hard_info_table[id].int_num;
-+ if (name) {
-+ *name = hard_info_table[id].name;
++ *int_valid = g_hard_info_table[id].int_valid;
++ *int_num = g_hard_info_table[id].int_num;
++ if (name != HI_NULL) {
++ *name = g_hard_info_table[id].name;
+ }
+
+ return;
+}
+
-+/**
-+\brief get base address of module.
-+*/
-+void module_set_irq(module_id id, hi_u32 irq)
++/*
++ * brief get base address of module.
++ */
++hi_void module_set_irq(module_id id, hi_u32 irq)
+{
-+ hard_info_table[id].int_num = irq;
-+ HI_LOG_INFO("%s set irq number 0x%x\n", hard_info_table[id].name, irq);
++ g_hard_info_table[id].int_num = irq;
++ hi_log_info("%s set irq number 0x%x\n", g_hard_info_table[id].name, irq);
+}
+
-+/**
-+\brief read a register.
-+*/
++/*
++ * brief read a register.
++ */
+hi_u32 module_reg_read(module_id id, hi_u32 offset)
+{
-+ hi_u32 val = 0;
-+ void *addr = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
++ hi_u32 val;
++ hi_void *addr = HI_NULL;
++ hi_s32 ret;
+
-+ HI_LOG_CHECK_PARAM(id >= CRYPTO_MODULE_ID_CNT);
-+ HI_LOG_CHECK_PARAM(offset >= hard_info_table[id].reg_addr_size);
++ hi_log_chk_param_return(id >= CRYPTO_MODULE_ID_CNT);
++ hi_log_chk_param_return(offset >= g_hard_info_table[id].reg_addr_size);
+
-+ /* tee may be read trng before cipher module init */
-+ if (hard_info_table[id].reg_addr_via == HI_NULL) {
++ /* tee may be read trng before cipher module init. */
++ if (g_hard_info_table[id].reg_addr_via == HI_NULL) {
+ ret = module_addr_map();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(module_addr_map, ret);
++ hi_log_print_func_err(module_addr_map, ret);
+ return 0;
+ }
+ }
+
-+ /*get the absolute address of reg*/
-+ addr = (hi_u8 *)(hard_info_table[id].reg_addr_via) + offset;
++ /* get the absolute address of reg. */
++ addr = (hi_u8 *)(g_hard_info_table[id].reg_addr_via) + offset;
+ val = crypto_read(addr);
+
+ return val;
+}
+
-+/**
-+\brief write a register.
-+*/
-+void module_reg_write(module_id id, hi_u32 offset, hi_u32 val)
++/*
++ * brief write a register.
++ */
++hi_void module_reg_write(module_id id, hi_u32 offset, hi_u32 val)
+{
-+ void *addr = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
++ hi_void *addr = HI_NULL;
++ hi_s32 ret;
+
-+ /*check if module is valid*/
++ /* check if module is valid. */
+ if (id >= CRYPTO_MODULE_ID_CNT) {
-+ HI_LOG_ERROR("error, invalid module id %d\n", id);
++ hi_log_error("error, invalid module id %d\n", id);
+ return;
+ }
+
-+ /*check if offset is valid*/
-+ if (offset >= hard_info_table[id].reg_addr_size) {
-+ HI_LOG_ERROR("error, reg offset overflow 0x%x\n", offset);
++ /* check if offset is valid. */
++ if (offset >= g_hard_info_table[id].reg_addr_size) {
++ hi_log_error("error, reg offset overflow 0x%x\n", offset);
+ return;
+ }
+
-+ /* tee may be read trng before cipher module init */
-+ if (hard_info_table[id].reg_addr_via == HI_NULL) {
++ /* tee may be read trng before cipher module init. */
++ if (g_hard_info_table[id].reg_addr_via == HI_NULL) {
+ ret = module_addr_map();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(module_addr_map, ret);
++ hi_log_print_func_err(module_addr_map, ret);
+ return;
+ }
+ }
+
-+ /*get the absolute address of reg*/
-+ addr = (hi_u8 *)hard_info_table[id].reg_addr_via + offset;
++ /* get the absolute address of reg. */
++ addr = (hi_u8 *)g_hard_info_table[id].reg_addr_via + offset;
+ crypto_write(addr, val);
+
+ return;
+}
+
-+/**
-+\brief Initialize the channel list.
-+*/
++/*
++ * brief Initialize the channel list.
++ */
+hi_s32 crypto_channel_init(channel_context *ctx, hi_u32 num, hi_u32 ctx_size)
+{
-+ hi_u32 size = 0;
-+ hi_u32 i = 0;
++ hi_u32 size;
++ hi_u32 i;
+ hi_u8 *buf = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
+
-+ /* clear context */
++ /* clear context. */
+ size = sizeof(channel_context) * num;
+ crypto_memset(ctx, size, 0, size);
+
-+ /* set context buffer */
++ /* set context buffer. */
+ if (ctx_size > 0) {
+ buf = (hi_u8 *)crypto_malloc(ctx_size * num);
+ if (buf == HI_NULL) {
@@ -203013,61 +272095,61 @@ index 0000000..4c57e2c
+ }
+ crypto_memset(buf, ctx_size * num, 0, ctx_size * num);
+
-+ /* the buffer addresss is stored at ctx[0].ctx*/
++ /* the buffer addresss is stored at ctx[0].ctx. */
+ for (i = 0; i < num; i++) {
+ ctx[i].ctx = buf;
+ buf += ctx_size;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/**
-+\brief denit the channel list.
-+*/
++/*
++ * brief denit the channel list.
++ */
+hi_s32 crypto_channel_deinit(channel_context *ctx, hi_u32 num)
+{
-+ hi_u32 size = 0;
++ hi_u32 size;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
+
-+ /* the buffer addresss is stored at ctx[0].ctx*/
++ /* the buffer addresss is stored at ctx[0].ctx. */
+ if (ctx[0].ctx != HI_NULL) {
+ crypto_free(ctx[0].ctx);
+ ctx[0].ctx = HI_NULL;
+ }
+
-+ /* clear context */
++ /* clear context. */
+ size = sizeof(channel_context) * num;
+ crypto_memset(ctx, size, 0, size);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/**
-+\brief allocate a channel.
-+*/
++/*
++ * brief allocate a channel.
++ */
+hi_s32 crypto_channel_alloc(channel_context *ctx, hi_u32 num, hi_u32 mask, hi_u32 *id)
+{
+ hi_s32 ret = HI_ERR_CIPHER_BUSY;
+ hi_u32 i = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
-+ HI_LOG_CHECK_PARAM(id == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
++ hi_log_chk_param_return(id == HI_NULL);
+
+ for (i = 0; i < num; i++) {
-+ /* check the valid channel */
++ /* check the valid channel. */
+ if (mask & (0x01 << i)) {
-+ if (!ctx[i].open) { /* found a free channel */
++ if (!ctx[i].open) { /* found a free channel. */
+ ret = HI_SUCCESS;
-+ ctx[i].open = HI_TRUE; /* alloc channel */
++ ctx[i].open = HI_TRUE; /* alloc channel. */
+ *id = i;
+ break;
+ }
@@ -203075,74 +272157,76 @@ index 0000000..4c57e2c
+ }
+
+ if (i == num) {
-+ HI_LOG_ERROR("error, all channels are busy.\n");
++ hi_log_error("error, all channels are busy.\n");
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ret;
+}
+
-+/**
-+\brief free a channel.
-+*/
-+void crypto_channel_free(channel_context *ctx, hi_u32 num, hi_u32 id)
++/*
++ * brief free a channel.
++ */
++hi_void crypto_channel_free(channel_context *ctx, hi_u32 num, hi_u32 id)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /*free channel*/
++ /* free channel. */
+ ctx[id].open = HI_FALSE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+/**
-+\brief get the private data of channel.
-+*/
-+void *crypto_channel_get_context(channel_context *ctx, hi_u32 num, hi_u32 id)
++/*
++ * brief get the private data of channel.
++ */
++hi_void *crypto_channel_get_context(channel_context *ctx, hi_u32 num, hi_u32 id)
+{
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto_channel_get_context() ctx is HI_NULL\n");
-+ HI_LOG_PRINT_ERR_CODE(0);
++ hi_log_error("crypto_channel_get_context() ctx is HI_NULL\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_POINT);
+ return HI_NULL;
+ }
+
+ if ((id >= num) || (!ctx[id].open)) {
-+ HI_LOG_ERROR("crypto_channel_get_context()- error, id %d, open %d, num %d\n",
-+ id, ctx[id].open, num);
-+ HI_LOG_PRINT_ERR_CODE(0);
++ hi_log_error("crypto_channel_get_context()- error, id %u, open %u, num %u\n", id, ctx[id].open, num);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_POINT);
+ return HI_NULL;
+ }
+
+ return ctx[id].ctx;
+}
+
-+void hex2str(char buf[2], hi_u8 val)
++hi_void hex2str(hi_char buf[MUL_VAL_2], hi_u32 buf_len, hi_u8 val)
+{
+ hi_u8 high, low;
+
-+ high = (val >> 4) & 0x0F;
-+ low = val & 0x0F;
-+
-+ if (high <= 9) {
-+ buf[0] = high + '0';
-+ } else {
-+ buf[0] = (high - 0x0A) + 'A';
++ if (buf_len != MUL_VAL_2) {
++ return;
+ }
+
-+ if (low <= 9) {
-+ buf[1] = low + '0';
++ high = (val >> SHIFT_4BITS) & MAX_LOW_4BITS;
++ low = val & MAX_LOW_4BITS;
++
++ if (high <= 9) { /* 0 ~ 9. */
++ buf[WORD_IDX_0] = high + '0';
+ } else {
-+ buf[1] = (low - 0x0A) + 'A';
++ buf[WORD_IDX_0] = (high - 0x0A) + 'A'; /* A ~ F. */
+ }
+
++ if (low <= 9) { /* 0 ~ 9. */
++ buf[WORD_IDX_1] = low + '0';
++ } else { /* A ~ F. */
++ buf[WORD_IDX_1] = (low - 0x0A) + 'A';
++ }
+}
+
-+/* Implementation that should never be optimized out by the compiler */
-+void crypto_zeroize( void *buf, hi_u32 len )
++/* Implementation that should never be optimized out by the compiler. */
++hi_void crypto_zeroize(hi_void *buf, hi_u32 len)
+{
-+ volatile unsigned char *p = (unsigned char *)buf;
++ volatile hi_u8 *p = (hi_u8 *)buf;
+
+ if (buf == HI_NULL) {
+ return;
@@ -203153,20 +272237,18 @@ index 0000000..4c57e2c
+ }
+}
+
-+void *crypto_calloc(size_t n, size_t size)
++hi_void *crypto_calloc(size_t n, size_t size)
+{
-+ void *ptr = HI_NULL;
++ hi_void *ptr = HI_NULL;
+
+ ptr = crypto_malloc(n * size);
-+
+ if (ptr != HI_NULL) {
+ crypto_memset(ptr, n * size, 0, n * size);
+ }
-+
+ return ptr;
+}
+
-+hi_u32 get_rand(void)
++hi_u32 get_rand(hi_void)
+{
+ hi_u32 randnum = 0;
+
@@ -203175,29 +272257,49 @@ index 0000000..4c57e2c
+ return randnum;
+}
+
-+/** @}*/ /** <!-- ==== API Code end ====*/
++#ifdef CIPHER_DEBUG_TEST_SUPPORT
++void crypto_print_hex(const hi_char *name, hi_u8 *str, hi_u32 len)
++{
++ hi_u32 i;
++ hi_u8 *tmp_str = (hi_u8 *)(str);
++
++ if (name == HI_NULL) {
++ hi_log_error("name is null.\n");
++ return;
++ }
++
++ if (str == HI_NULL) {
++ hi_log_error("str is null.\n");
++ return;
++ }
++
++ if (len == 0) {
++ hi_log_error("len is 0.\n");
++ return;
++ }
++
++ HI_PRINT("[%s]:\n", (name));
++ for (i = 0 ; i < (len); i++) {
++ if ((i % PRINT_HEX_BLOCK_LEN == 0) && (i != 0)) {
++ HI_PRINT("\n");
++ }
++
++ HI_PRINT("\\x%02x", *((tmp_str) + i));
++ }
++ HI_PRINT("\n");
++}
++#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v100.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v100.c
new file mode 100644
-index 0000000..43453fe
+index 0000000..4588f5f
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v100.c
-@@ -0,0 +1,1729 @@
+@@ -0,0 +1,1733 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv symc v100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_symc_v100.h"
@@ -203207,84 +272309,75 @@ index 0000000..43453fe
+
+#define MAX_NODE_SIZE (0x100000 - 16)
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+/*! Define the struct of node */
++/* ************************** Internal Structure Definition *************************** */
++/* Define the struct of node */
+typedef struct {
-+ hi_u32 phy_addr; /*!< physics address of buffer */
-+ hi_u32 flags; /*!< flag */
-+ hi_u32 length; /*!< length of buffer */
-+ hi_u32 iv_addr; /*!< physics address of iv */
++ hi_u32 phy_addr; /* physics address of buffer */
++ hi_u32 flags; /* flag */
++ hi_u32 length; /* length of buffer */
++ hi_u32 iv_addr; /* physics address of iv */
+} symc_entry;
+
-+/*! Define the struct of iv in node */
++/* Define the struct of iv in node */
+typedef struct {
-+ hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD]; /*!< iv data */
++ hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD]; /* iv data */
+} symc_entry_iv;
+
-+/*! Define the context of cipher */
++/* Define the context of cipher */
+typedef struct {
-+ symc_entry *entry_in; /*!< in node list */
-+ symc_entry *entry_out; /*!< out node list */
-+ symc_entry_iv *entry_iv; /*!< buffer to store the IV */
-+ hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD];/*!< iv data from user*/
++ symc_entry *entry_in; /* in node list */
++ symc_entry *entry_out; /* out node list */
++ symc_entry_iv *entry_iv; /* buffer to store the IV */
++ hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD]; /* iv data from user. */
+
-+ /* iv usage flag, should be CIPHER_IV_CHANGE_ONE_PKG
-+ * or CIPHER_IV_CHANGE_ALL_PKG.
++ /* iv usage flag, should be HI_CIPHER_IV_CHG_ONE_PACK
++ * or HI_CIPHER_IV_CHG_ALL_PACK.
+ */
+ hi_u32 iv_flag;
-+ hi_u32 id_in; /*!< current in nodes index */
-+ hi_u32 id_out; /*!< current out nodes index */
-+ hi_u32 cnt; /*!< total count nodes to be computed */
-+ hi_u32 done; /*!< calculation finish flag*/
-+ crypto_queue_head queue; /*!< quene list */
-+ callback_symc_isr callback; /*!< isr callback functon */
-+ callback_symc_destory destory; /*!< destory callback functon */
-+ void *ctx; /*!< params for isr callback functon */
++ hi_u32 id_in; /* current in nodes index */
++ hi_u32 id_out; /* current out nodes index */
++ hi_u32 cnt; /* total count nodes to be computed */
++ hi_u32 done; /* calculation finish flag. */
++ crypto_queue_head queue; /* quene list */
++ callback_symc_isr callback; /* isr callback functon */
++ callback_symc_destory destory; /* destory callback functon */
++ hi_void *ctx; /* params for isr callback functon */
+} symc_hard_context;
+
-+/*! Channel of cipher */
-+static channel_context symc_hard_channel[CRYPTO_HARD_CHANNEL_MAX];
++/* Channel of cipher */
++static channel_context g_symc_hard_channel[CRYPTO_HARD_CHANNEL_MAX];
+
-+/*! dma memory of cipher node list*/
-+static crypto_mem symc_dma;
-+
-+/*! symc already initialize or not */
-+static hi_u32 symc_initialize = HI_FALSE;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
++/* dma memory of cipher node list. */
++static crypto_mem g_symc_dma;
+
++/* symc already initialize or not */
++static hi_u32 g_symc_initialize = HI_FALSE;
+
++/* ****************************** API Code **************************** */
+static hi_u32 drv_symc_done_try(hi_u32 chn_num)
+{
+ int_raw status;
+ symc_hard_context *ctx = HI_NULL;
+ hi_u32 process = 0;
+
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ status.u32 = SYMC_READ(REG_INT_RAW);
++ status.u32 = symc_read(REG_INT_RAW);
+ status.bits.chn_obuf_raw &= 0x01 << chn_num; /* check interception */
+
-+ /*clear interception*/
-+ SYMC_WRITE(REG_INT_RAW, status.u32);
++ /* clear interception. */
++ symc_write(REG_INT_RAW, status.u32);
+
+ if (status.bits.chn_obuf_raw) {
-+ ctx = crypto_channel_get_context(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
++ ctx = crypto_channel_get_context(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto channel get context failed,ctx is null!\n");
++ hi_log_error("crypto channel get context failed, ctx is null!\n");
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
-+ process = SYMC_READ(REG_CHANn_OFULL_CNT(chn_num));
-+ SYMC_WRITE(REG_CHANn_IEMPTY_CNT(chn_num), process);
-+ SYMC_WRITE(REG_CHANn_OFULL_CNT(chn_num), process);
++ process = symc_read(reg_chann_ofull_cnt(chn_num));
++ symc_write(reg_chann_iempty_cnt(chn_num), process);
++ symc_write(reg_chann_ofull_cnt(chn_num), process);
+ ctx->cnt -= process;
+ }
+
@@ -203292,19 +272385,19 @@ index 0000000..43453fe
+}
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+static hi_u32 drv_symc_done_notify(void)
++static hi_u32 drv_symc_done_notify(hi_void)
+{
+ symc_hard_context *ctx = HI_NULL;
+ int_raw status;
+ hi_u32 process = 0;
+ hi_u32 i;
+
-+ status.u32 = SYMC_READ(REG_INT_RAW);
++ status.u32 = symc_read(REG_INT_RAW);
+
-+ /*must clear interception before any operation */
-+ SYMC_WRITE(REG_INT_RAW, status.u32);
++ /* must clear interception before any operation */
++ symc_write(REG_INT_RAW, status.u32);
+
-+ /*just process the valid channel*/
++ /* just process the valid channel. */
+ status.bits.chn_obuf_raw &= CIPHER_HARD_CHANNEL_MASK;
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
@@ -203312,54 +272405,53 @@ index 0000000..43453fe
+ /* received interception, tell hardware that
+ * we already process the output node
+ */
-+ ctx = crypto_channel_get_context(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, i);
++ ctx = crypto_channel_get_context(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, i);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto channel get context failed,ctx is null!\n");
++ hi_log_error("crypto channel get context failed, ctx is null!\n");
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
-+ process = SYMC_READ(REG_CHANn_OFULL_CNT(i));
-+ SYMC_WRITE(REG_CHANn_IEMPTY_CNT(i), process);
-+ SYMC_WRITE(REG_CHANn_OFULL_CNT(i), process);
++ process = symc_read(reg_chann_ofull_cnt(i));
++ symc_write(reg_chann_iempty_cnt(i), process);
++ symc_write(reg_chann_ofull_cnt(i), process);
+ ctx->cnt -= process;
+ }
+ }
+
+ return status.bits.chn_obuf_raw; /* mask */
-+
+}
+
-+/*! symc interrupt process function */
-+static irqreturn_t drv_symc_interrupt_isr(hi_s32 irq, void *devId)
++/* symc interrupt process function */
++static irqreturn_t drv_symc_interrupt_isr(hi_s32 irq, hi_void *dev_id)
+{
+ hi_u32 mask, i;
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_DEBUG("symc irq: %d\n", irq);
++ hi_log_debug("symc irq: %d\n", irq);
+
-+ /* get channel context*/
++ /* get channel context. */
+ mask = drv_symc_done_notify();
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
+ if ((mask >> i) & 0x01) {
-+ ctx = crypto_channel_get_context(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, i);
++ ctx = crypto_channel_get_context(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, i);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("Ctx get context failed.\n");
++ hi_log_error("Ctx get context failed.\n");
+ return IRQ_NONE;
+ }
+
-+ /*make sure all the loaded nodes are finished before start next compute*/
-+ if (0x00 != ctx->cnt) {
++ /* make sure all the loaded nodes are finished before start next compute. */
++ if (ctx->cnt != 0) {
+ continue;
+ }
+
+ /* continue to load other nodes */
+ if ((ctx->callback) && (ctx->callback(ctx->ctx) == HI_FALSE)) {
-+ HI_LOG_DEBUG("contiue to compute chn %d\n", i);
++ hi_log_debug("contiue to compute chn %d\n", i);
+ drv_symc_start(i);
+ } else { /* finished, no more nodes need to be load */
+ ctx->done = HI_TRUE;
-+ HI_LOG_DEBUG("chn %d wake up\n", i);
++ hi_log_debug("chn %d wake up\n", i);
+ crypto_queue_wait_up(&ctx->queue);
+ }
+ }
@@ -203368,15 +272460,16 @@ index 0000000..43453fe
+ return IRQ_HANDLED;
+}
+
-+/*! symc register interrupt process function */
-+static hi_s32 drv_symc_register_interrupt(void)
++/* symc register interrupt process function */
++static hi_s32 drv_symc_register_interrupt(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_s32 ret;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ hi_u32 i;
-+ const char *name;
++ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, &name);
+
@@ -203385,30 +272478,31 @@ index 0000000..43453fe
+ }
+
+ /* request irq */
-+ HI_LOG_DEBUG("symc request irq, num %d, name %s\n", int_num, name);
++ hi_log_debug("symc request irq, num %d, name %s\n", int_num, name);
+ ret = crypto_request_irq(int_num, drv_symc_interrupt_isr, name);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Irq request failure, ret=%d, irq = %d", ret, int_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_REGISTER_IRQ);
++ hi_log_error("Irq request failure, ret=%d, irq = %d", ret, int_num);
++ hi_log_print_err_code(HI_ERR_CIPHER_REGISTER_IRQ);
+ return ret;
+ }
+
-+ /* initialize queue list*/
++ /* initialize queue list. */
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ crypto_queue_init(&((symc_hard_context *)symc_hard_channel[i].ctx)->queue);
++ crypto_queue_init(&((symc_hard_context *)g_symc_hard_channel[i].ctx)->queue);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/*! symc unregister interrupt process function */
-+static void drv_symc_unregister_interrupt(void)
++/* symc unregister interrupt process function */
++static hi_void drv_symc_unregister_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, &name);
+
@@ -203417,43 +272511,42 @@ index 0000000..43453fe
+ }
+
+ /* free irq */
-+ HI_LOG_DEBUG("symc free irq, num %d, name %s\n", int_num, name);
++ hi_log_debug("symc free irq, num %d, name %s\n", int_num, name);
+ crypto_free_irq(int_num, name);
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+
-+/*! set interrupt */
-+static void drv_symc_set_interrupt(void)
++/* set interrupt */
++static hi_void drv_symc_set_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ int_en int_en;
+ int_raw int_raw;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, HI_NULL);
+
+ if (int_valid == HI_FALSE) {
-+ int_en.u32 = SYMC_READ(REG_INT_EN);
++ int_en.u32 = symc_read(REG_INT_EN);
+
-+ /*The top interrupt switch only can be enable/disable by secure CPU*/
++ /* The top interrupt switch only can be enable/disable by secure CPU. */
+ int_en.bits.sec_int_en = 0;
+ int_en.bits.int_en = 0;
+ int_en.bits.chn_obuf_en &= ~CIPHER_HARD_CHANNEL_MASK;
-+ SYMC_WRITE(REG_INT_EN, int_en.u32);
-+ HI_LOG_INFO("REG_INT_EN 0x%x\n", int_en.u32);
++ symc_write(REG_INT_EN, int_en.u32);
++ hi_log_info("REG_INT_EN 0x%x\n", int_en.u32);
+ } else {
-+ int_en.u32 = SYMC_READ(REG_INT_EN);
++ int_en.u32 = symc_read(REG_INT_EN);
+
-+ /*The top interrupt switch only can be enable/disable by secure CPU*/
++ /* The top interrupt switch only can be enable/disable by secure CPU. */
+ int_en.bits.sec_int_en = 1;
+ int_en.bits.int_en = 1;
+ int_en.bits.chn_obuf_en = CIPHER_HARD_CHANNEL_MASK;
-+ SYMC_WRITE(REG_INT_EN, int_en.u32);
-+ HI_LOG_INFO("REG_INT_EN 0x%x\n", int_en.u32);
++ symc_write(REG_INT_EN, int_en.u32);
++ hi_log_info("REG_INT_EN 0x%x\n", int_en.u32);
+ }
+
+ /* clear interception
@@ -203461,314 +272554,331 @@ index 0000000..43453fe
+ * call the irq function before initialization
+ * when register interrupt, this will cause a system abort.
+ */
-+ int_raw.u32 = SYMC_READ(REG_INT_RAW);
-+ int_raw.bits.chn_obuf_raw &= CIPHER_HARD_CHANNEL_MASK; /* clear valid channel */
-+ SYMC_WRITE(REG_INT_RAW, int_raw.u32);
++ int_raw.u32 = symc_read(REG_INT_RAW);
++ int_raw.bits.chn_obuf_raw &= CIPHER_HARD_CHANNEL_MASK; /* clear valid channel. */
++ symc_write(REG_INT_RAW, int_raw.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
++}
+
-+ return;
++static hi_s32 drv_symc_wait_irq(hi_u32 chn_num, hi_u32 timeout)
++{
++ hi_s32 ret;
++ symc_hard_context *ctx = HI_NULL;
++
++ ctx = crypto_channel_get_context(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
++ if (ctx == HI_NULL) {
++ hi_log_error("crypto channel get context failed, ctx is null, chn=%d\n", chn_num);
++ hi_log_print_func_err(crypto_channel_get_context, HI_ERR_CIPHER_INVALID_POINT);
++ return HI_ERR_CIPHER_INVALID_POINT;
++ }
++
++ /* wait interrupt */
++ ret = crypto_queue_wait_timeout(ctx->queue, &ctx->done, timeout);
++ if ((ret <= 0) && (ret != -ERESTARTSYS)) {
++ hi_log_error("wait done timeout, chn=%d\n", chn_num);
++ hi_log_print_func_err(crypto_queue_wait_timeout, HI_ERR_CIPHER_TIMEOUT);
++ drv_symc_get_err_code(chn_num);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
++
++ return HI_SUCCESS;
+}
+
+#endif
+
-+/*! set symc entry */
-+static void drv_symc_set_entry(hi_u32 chn, hi_u32 dma_addr, hi_u32 mmz_addr, void *cpu_addr)
++/* set symc entry */
++static hi_void drv_symc_set_entry(hi_u32 chn, hi_u32 dma_addr, hi_u32 mmz_addr, hi_void *cpu_addr)
+{
+ hi_u32 i;
-+ symc_hard_context *ctx = (symc_hard_context *)symc_hard_channel[chn].ctx;
++ symc_hard_context *ctx = (symc_hard_context *)g_symc_hard_channel[chn].ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /*set first in node addr*/
-+ HI_LOG_INFO("chn %d, entry in dma addr 0x%x, mmz addr 0x%x, cpu addr 0x%p\n",
++ /* set first in node addr. */
++ hi_log_info("chn %d, entry in dma addr 0x%x, mmz addr 0x%x, cpu addr 0x%p\n",
+ chn, dma_addr, mmz_addr, cpu_addr);
-+ SYMC_WRITE(REG_CHANn_SRC_LST_SADDR(chn), mmz_addr); /*node list must be mmz*/
++ symc_write(reg_chann_src_lst_saddr(chn), mmz_addr); /* node list must be mmz. */
+ ctx->entry_in = cpu_addr;
+ dma_addr += ENTRY_NODE_SIZE * SYMC_MAX_LIST_NUM;
+ mmz_addr += ENTRY_NODE_SIZE * SYMC_MAX_LIST_NUM;
+ cpu_addr = (hi_u8 *)cpu_addr + ENTRY_NODE_SIZE * SYMC_MAX_LIST_NUM;
+
-+ /*set first out node addr*/
-+ HI_LOG_INFO("chn %d, entry out dma addr 0x%x, mmz addr 0x%x, cpu addr 0x%p\n",
++ /* set first out node addr. */
++ hi_log_info("chn %d, entry out dma addr 0x%x, mmz addr 0x%x, cpu addr 0x%p\n",
+ chn, dma_addr, mmz_addr, cpu_addr);
-+ SYMC_WRITE(REG_CHANn_DEST_LST_SADDR(chn), mmz_addr); /*node list must be mmz*/
++ symc_write(reg_chann_dest_lst_saddr(chn), mmz_addr); /* node list must be mmz. */
+ ctx->entry_out = cpu_addr;
+ dma_addr += ENTRY_NODE_SIZE * SYMC_MAX_LIST_NUM;
+ mmz_addr += ENTRY_NODE_SIZE * SYMC_MAX_LIST_NUM;
+ cpu_addr = (hi_u8 *)cpu_addr + ENTRY_NODE_SIZE * SYMC_MAX_LIST_NUM;
+
-+ /*set iv addr of in node*/
-+ HI_LOG_INFO("chn %d, IV dma addr 0x%x, cpu addr 0x%p\n", chn, dma_addr, cpu_addr);
++ /* set iv addr of in node. */
++ hi_log_info("chn %d, IV dma addr 0x%x, cpu addr 0x%p\n", chn, dma_addr, cpu_addr);
+ for (i = 0; i < SYMC_MAX_LIST_NUM; i++) {
-+ /*set iv dma addr to each in node, IV dma addr may be mmz or mmu*/
++ /* set iv dma addr to each in node, IV dma addr may be mmz or mmu. */
+ ctx->entry_in[i].iv_addr = dma_addr;
+ dma_addr += SYMC_IV_MAX_SIZE;
+ }
+ ctx->entry_iv = cpu_addr;
+ cpu_addr = (hi_u8 *)cpu_addr + SYMC_IV_MAX_SIZE * SYMC_MAX_LIST_NUM;
+
-+ /*the symc module may be running at setup period,
-+ *Here, we must continue running immediately after the last node*/
-+ ctx->id_in = SYMC_READ(REG_CHANn_SRC_LST_RADDR(chn));
-+ ctx->id_out = SYMC_READ(REG_CHANn_DEST_LST_RADDR(chn));
++ /* the symc module may be running at setup period,
++ * Here, we must continue running immediately after the last node.
++ */
++ ctx->id_in = symc_read(reg_chann_src_lst_raddr(chn));
++ ctx->id_out = symc_read(reg_chann_dest_lst_raddr(chn));
+ ctx->cnt = 0x00;
-+ HI_LOG_INFO("chn %d, id in %d, out %d\n\n", chn, ctx->id_in, ctx->id_out);
++ hi_log_info("chn %d, id in %d, out %d\n\n", chn, ctx->id_in, ctx->id_out);
+
-+ /*set total node list Num */
-+ HI_LOG_DEBUG("set total node list Num\n");
-+ SYMC_WRITE(REG_CHANn_IBUF_NUM(chn), SYMC_MAX_LIST_NUM);
-+ SYMC_WRITE(REG_CHANn_OBUF_NUM(chn), SYMC_MAX_LIST_NUM);
++ /* set total node list Num */
++ hi_log_debug("set total node list Num\n");
++ symc_write(reg_chann_ibuf_num(chn), SYMC_MAX_LIST_NUM);
++ symc_write(reg_chann_obuf_num(chn), SYMC_MAX_LIST_NUM);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
+#ifdef CRYPTO_SMMU_SUPPORT
+
-+/*! set smmu */
-+static void drv_symc_smmu_bypass(void)
++/* set smmu */
++static hi_void drv_symc_smmu_bypass(hi_void)
+{
+ chann_rd_dat_addr_smmu_bypass rd_mmu;
+ chann_wr_dat_addr_smmu_bypass wr_mmu;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ rd_mmu.u32 = SYMC_READ(CHANn_RD_DAT_ADDR_SMMU_BYPASS);
-+ wr_mmu.u32 = SYMC_READ(CHANn_WR_DAT_ADDR_SMMU_BYPASS);
++ rd_mmu.u32 = symc_read(CHANn_RD_DAT_ADDR_SMMU_BYPASS);
++ wr_mmu.u32 = symc_read(CHANn_WR_DAT_ADDR_SMMU_BYPASS);
+
-+ /*bypass: 1-use mmz, 0-use mmu*/
++ /* bypass: 1-use mmz, 0-use mmu. */
+ rd_mmu.bits.chann_rd_dat_addr_smmu_bypass &= ~(CIPHER_HARD_CHANNEL_MASK >> 1);
+ wr_mmu.bits.chann_wr_dat_addr_smmu_bypass &= ~(CIPHER_HARD_CHANNEL_MASK >> 1);
+
-+ SYMC_WRITE(CHANn_RD_DAT_ADDR_SMMU_BYPASS, rd_mmu.u32);
-+ SYMC_WRITE(CHANn_WR_DAT_ADDR_SMMU_BYPASS, wr_mmu.u32);
++ symc_write(CHANn_RD_DAT_ADDR_SMMU_BYPASS, rd_mmu.u32);
++ symc_write(CHANn_WR_DAT_ADDR_SMMU_BYPASS, wr_mmu.u32);
+
-+ HI_LOG_INFO("CHANn_RD_DAT_ADDR_SMMU_BYPASS 0x%x\n", rd_mmu.u32);
-+ HI_LOG_INFO("CHANn_WR_DAT_ADDR_SMMU_BYPASS 0x%x\n", wr_mmu.u32);
++ hi_log_info("CHANn_RD_DAT_ADDR_SMMU_BYPASS 0x%x\n", rd_mmu.u32);
++ hi_log_info("CHANn_WR_DAT_ADDR_SMMU_BYPASS 0x%x\n", wr_mmu.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+/*! smmu int enable */
-+static void drv_symc_smmint_enable(void)
++/* smmu int enable */
++static hi_void drv_symc_smmint_enable(hi_void)
+{
+ smmu_scr scr;
+ smmu_int int_en;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /* enable smmu interception and disable bypass*/
-+ scr.u32 = SMMU_READ(REG_MMU_GLOBAL_CTR_ADDR);
++ /* enable smmu interception and disable bypass. */
++ scr.u32 = smmu_read(REG_MMU_GLOBAL_CTR_ADDR);
+ scr.bits.glb_bypass = 0;
+ scr.bits.int_en = 1;
-+ SMMU_WRITE(REG_MMU_GLOBAL_CTR_ADDR, scr.u32);
-+ HI_LOG_INFO("REG_MMU_GLOBAL_CTR_ADDR 0x%x\n", scr.u32);
++ smmu_write(REG_MMU_GLOBAL_CTR_ADDR, scr.u32);
++ hi_log_info("REG_MMU_GLOBAL_CTR_ADDR 0x%x\n", scr.u32);
+
-+ /*enable interception*/
++ /* enable interception. */
+ if (crypto_is_sec_cpu()) {
-+ int_en.u32 = SMMU_READ(REG_MMU_INTMAS_S);
++ int_en.u32 = smmu_read(REG_MMU_INTMAS_S);
+ int_en.bits.ints_tlbmiss = 0;
+ int_en.bits.ints_ptw_trans = 0;
+ int_en.bits.ints_tlbinvalid = 0;
-+ SMMU_WRITE(REG_MMU_INTMAS_S, int_en.u32);
-+ HI_LOG_INFO("REG_MMU_INTMAS_S 0x%x\n", int_en.u32);
++ smmu_write(REG_MMU_INTMAS_S, int_en.u32);
++ hi_log_info("REG_MMU_INTMAS_S 0x%x\n", int_en.u32);
+ } else {
-+ int_en.u32 = SMMU_READ(REG_MMU_INTMASK_NS);
++ int_en.u32 = smmu_read(REG_MMU_INTMASK_NS);
+ int_en.bits.ints_tlbmiss = 0;
+ int_en.bits.ints_ptw_trans = 0;
+ int_en.bits.ints_tlbinvalid = 0;
-+ SMMU_WRITE(REG_MMU_INTMASK_NS, int_en.u32);
-+ HI_LOG_INFO("REG_MMU_INTMASK_NS 0x%x\n", int_en.u32);
++ smmu_write(REG_MMU_INTMASK_NS, int_en.u32);
++ hi_log_info("REG_MMU_INTMASK_NS 0x%x\n", int_en.u32);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+#endif
+
-+/*! smmu int disable */
-+static void drv_symc_smmu_int_disable(void)
++/* smmu int disable */
++static hi_void drv_symc_smmu_int_disable(hi_void)
+{
+ smmu_scr scr;
+ smmu_int int_en;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /* enable smmu interception and disable bypass*/
-+ scr.u32 = SMMU_READ(REG_MMU_GLOBAL_CTR_ADDR);
++ /* enable smmu interception and disable bypass. */
++ scr.u32 = smmu_read(REG_MMU_GLOBAL_CTR_ADDR);
+ scr.bits.glb_bypass = 0;
+ scr.bits.int_en = 0;
-+ SMMU_WRITE(REG_MMU_GLOBAL_CTR_ADDR, scr.u32);
-+ HI_LOG_INFO("REG_MMU_GLOBAL_CTR_ADDR 0x%x\n", scr.u32);
++ smmu_write(REG_MMU_GLOBAL_CTR_ADDR, scr.u32);
++ hi_log_info("REG_MMU_GLOBAL_CTR_ADDR 0x%x\n", scr.u32);
+
+ /* disable secure interception */
-+ int_en.u32 = SMMU_READ(REG_MMU_INTMAS_S);
++ int_en.u32 = smmu_read(REG_MMU_INTMAS_S);
+ int_en.bits.ints_tlbmiss = 1;
+ int_en.bits.ints_ptw_trans = 1;
+ int_en.bits.ints_tlbinvalid = 1;
-+ SMMU_WRITE(REG_MMU_INTMAS_S, int_en.u32);
-+ HI_LOG_INFO("REG_MMU_INTMAS_S 0x%x\n", int_en.u32);
++ smmu_write(REG_MMU_INTMAS_S, int_en.u32);
++ hi_log_info("REG_MMU_INTMAS_S 0x%x\n", int_en.u32);
+
+ /* disable non-secure interception */
-+ int_en.u32 = SMMU_READ(REG_MMU_INTMASK_NS);
++ int_en.u32 = smmu_read(REG_MMU_INTMASK_NS);
+ int_en.bits.ints_tlbmiss = 1;
+ int_en.bits.ints_ptw_trans = 1;
+ int_en.bits.ints_tlbinvalid = 1;
-+ SMMU_WRITE(REG_MMU_INTMASK_NS, int_en.u32);
-+ HI_LOG_INFO("REG_MMU_INTMASK_NS 0x%x\n", int_en.u32);
++ smmu_write(REG_MMU_INTMASK_NS, int_en.u32);
++ hi_log_info("REG_MMU_INTMASK_NS 0x%x\n", int_en.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+/*! smmu set base address */
-+static hi_s32 drv_symc_smmu_base_addr(void)
++/* smmu set base address */
++static hi_void drv_symc_smmu_base_addr(hi_void)
+{
+ hi_u64 err_raddr = 0;
+ hi_u64 err_waddr = 0;
+ hi_u64 table_addr = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* get table base addr from system api */
+ smmu_get_table_addr(&err_raddr, &err_waddr, &table_addr);
+
+ if (crypto_is_sec_cpu()) {
+#ifdef CHIP_SMMU_VER_V200
-+ SMMU_WRITE(REG_MMU_ERR_RDADDR_H_S, 0x00); /*default error read high addr*/
-+ SMMU_WRITE(REG_MMU_ERR_WRADDR_H_S, 0x00); /*default error write high addr*/
-+ SMMU_WRITE(REG_MMU_SCB_TTBR_H, 0x00); /*smmu page table high addr*/
++ smmu_write(REG_MMU_ERR_RDADDR_H_S, 0x00); /* default error read high addr. */
++ smmu_write(REG_MMU_ERR_WRADDR_H_S, 0x00); /* default error write high addr. */
++ smmu_write(REG_MMU_SCB_TTBR_H, 0x00); /* smmu page table high addr. */
+#endif
-+ SMMU_WRITE(REG_MMU_ERR_RDADDR_S, (hi_u32)err_raddr); /*default error read addr*/
-+ SMMU_WRITE(REG_MMU_ERR_WRADDR_S, (hi_u32)err_waddr); /*default error write addr*/
-+ SMMU_WRITE(REG_MMU_SCB_TTBR, (hi_u32)table_addr); /*smmu page table addr*/
-+
++ smmu_write(REG_MMU_ERR_RDADDR_S, (hi_u32)err_raddr); /* default error read addr. */
++ smmu_write(REG_MMU_ERR_WRADDR_S, (hi_u32)err_waddr); /* default error write addr. */
++ smmu_write(REG_MMU_SCB_TTBR, (hi_u32)table_addr); /* smmu page table addr. */
+ } else {
+#ifdef CHIP_SMMU_VER_V200
-+ SMMU_WRITE(REG_MMU_ERR_RDADDR_H_NS, 0x00); /*default error read high addr*/
-+ SMMU_WRITE(REG_MMU_ERR_WRADDR_H_NS, 0x00); /*default error write high addr*/
-+ SMMU_WRITE(REG_MMU_CB_TTBR_H, 0x00); /*smmu page table high addr*/
++ smmu_write(REG_MMU_ERR_RDADDR_H_NS, 0x00); /* default error read high addr. */
++ smmu_write(REG_MMU_ERR_WRADDR_H_NS, 0x00); /* default error write high addr. */
++ smmu_write(REG_MMU_CB_TTBR_H, 0x00); /* smmu page table high addr. */
+#endif
-+ SMMU_WRITE(REG_MMU_ERR_RDADDR_NS, (hi_u32)err_raddr);/*default error read addr*/
-+ SMMU_WRITE(REG_MMU_ERR_WRADDR_NS, (hi_u32)err_waddr);/*default error write addr*/
-+ SMMU_WRITE(REG_MMU_CB_TTBR, (hi_u32)table_addr); /*smmu page table addr*/
++ smmu_write(REG_MMU_ERR_RDADDR_NS, (hi_u32)err_raddr); /* default error read addr. */
++ smmu_write(REG_MMU_ERR_WRADDR_NS, (hi_u32)err_waddr); /* default error write addr. */
++ smmu_write(REG_MMU_CB_TTBR, (hi_u32)table_addr); /* smmu page table addr. */
+ }
+
-+ HI_LOG_FUNC_EXIT();
-+ return HI_SUCCESS;
++ hi_log_func_exit();
+}
+#endif
+
-+/*! set secure channel,
-+ * non-secure CPU can't change the value of SEC_CHN_CFG,
-+ * so non-secure CPU call this function will do nothing.
++/* set secure channel,
++ * non-secure CPU can't change the value of SEC_CHN_CFG,
++ * so non-secure CPU call this function will do nothing.
+ */
-+static void drv_symc_enable_secure(void)
++static hi_void drv_symc_enable_secure(hi_void)
+{
+ sec_chn_cfg sec;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /*The REG_SEC_CHN_CFG only can be set by secure CPU*/
-+ sec.u32 = SYMC_READ(REG_SEC_CHN_CFG);
++ /* The REG_SEC_CHN_CFG only can be set by secure CPU. */
++ sec.u32 = symc_read(REG_SEC_CHN_CFG);
+ sec.bits.sec_chn_cfg = CIPHER_HARD_CHANNEL_MASK;
-+ SYMC_WRITE(REG_SEC_CHN_CFG, sec.u32);
-+ HI_LOG_INFO("REG_SEC_CHN_CFG 0x%x\n", sec.u32);
++ symc_write(REG_SEC_CHN_CFG, sec.u32);
++ hi_log_info("REG_SEC_CHN_CFG 0x%x\n", sec.u32);
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+
-+static void drv_symc_print_last_node(hi_u32 chn_num)
++static hi_void drv_symc_print_last_node(hi_u32 chn_num)
+{
-+ symc_entry *in = HI_NULL, *out = HI_NULL;
++ symc_entry *in = HI_NULL;
++ symc_entry *out = HI_NULL;
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ctx = (symc_hard_context *)symc_hard_channel[chn_num].ctx;
++ ctx = (symc_hard_context *)g_symc_hard_channel[chn_num].ctx;
+
-+ /* get last in node info*/
++ /* get last in node info. */
+ if (ctx->id_in == 0x00) {
+ in = &ctx->entry_in[SYMC_NODE_LIST_SIZE];
+ } else {
+ in = &ctx->entry_in[ctx->id_in - 1];
+ }
+
-+ /* get last out node info*/
++ /* get last out node info. */
+ if (ctx->id_out == 0x00) {
+ out = &ctx->entry_out[SYMC_NODE_LIST_SIZE];
+ } else {
+ out = &ctx->entry_out[ctx->id_out - 1];
+ }
+
-+ HI_LOG_ERROR("chn %d, src addr 0x%x, size 0x%x, dest addr 0x%x, size 0x%x\n",
++ hi_log_error("chn %d, src addr 0x%x, size 0x%x, dest addr 0x%x, size 0x%x\n",
+ chn_num, in->phy_addr, in->length, out->phy_addr, out->length);
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+
-+static void drv_symc_print_status(hi_u32 chn_num)
++static hi_void drv_symc_print_status(hi_u32 chn_num)
+{
+ int_raw raw;
+ int_status status;
+ int_en enable;
+ sec_chn_cfg cfg;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_ERROR("REG_CHANn_SRC_LST_SADDR : 0x%x\n", SYMC_READ(REG_CHANn_SRC_LST_SADDR(chn_num)));
-+ HI_LOG_ERROR("REG_CHANn_SRC_LST_RADDR : 0x%x\n", SYMC_READ(REG_CHANn_SRC_LST_RADDR(chn_num)));
-+ HI_LOG_ERROR("REG_CHANn_IBUF_NUM : 0x%x\n", SYMC_READ(REG_CHANn_IBUF_NUM(chn_num)));
-+ HI_LOG_ERROR("CHANn_SRC_ADDR : 0x%x\n", SYMC_READ(CHANn_SRC_ADDR(chn_num)));
-+ HI_LOG_ERROR("REG_CHANn_DEST_LST_SADDR : 0x%x\n", SYMC_READ(REG_CHANn_DEST_LST_SADDR(chn_num)));
-+ HI_LOG_ERROR("REG_CHANn_DEST_LST_RADDR : 0x%x\n", SYMC_READ(REG_CHANn_DEST_LST_RADDR(chn_num)));
-+ HI_LOG_ERROR("REG_CHANn_OBUF_NUM : 0x%x\n", SYMC_READ(REG_CHANn_OBUF_NUM(chn_num)));
-+ HI_LOG_ERROR("REG_CHANn_DEST_ADDR : 0x%x\n", SYMC_READ(REG_CHANn_DEST_ADDR(chn_num)));
-+ HI_LOG_ERROR("CHANn_CIPHER_CTRL : 0x%x\n", SYMC_READ(REG_CHANn_CIPHER_CTRL(chn_num)));
++ hi_log_error("reg_chann_src_lst_saddr : 0x%x\n", symc_read(reg_chann_src_lst_saddr(chn_num)));
++ hi_log_error("reg_chann_src_lst_raddr : 0x%x\n", symc_read(reg_chann_src_lst_raddr(chn_num)));
++ hi_log_error("reg_chann_ibuf_num : 0x%x\n", symc_read(reg_chann_ibuf_num(chn_num)));
++ hi_log_error("chnn_src_addr : 0x%x\n", symc_read(chnn_src_addr(chn_num)));
++ hi_log_error("reg_chann_dest_lst_saddr : 0x%x\n", symc_read(reg_chann_dest_lst_saddr(chn_num)));
++ hi_log_error("reg_chann_dest_lst_raddr : 0x%x\n", symc_read(reg_chann_dest_lst_raddr(chn_num)));
++ hi_log_error("reg_chann_obuf_num : 0x%x\n", symc_read(reg_chann_obuf_num(chn_num)));
++ hi_log_error("reg_chann_dest_addr : 0x%x\n", symc_read(reg_chann_dest_addr(chn_num)));
++ hi_log_error("chann_cipher_ctrl : 0x%x\n", symc_read(reg_chann_cipher_ctrl(chn_num)));
+
-+ raw.u32 = SYMC_READ(REG_INT_RAW);
-+ status.u32 = SYMC_READ(REG_INT_STATUS);
-+ enable.u32 = SYMC_READ(REG_INT_EN);
-+ cfg.u32 = SYMC_READ(REG_SEC_CHN_CFG);
++ raw.u32 = symc_read(REG_INT_RAW);
++ status.u32 = symc_read(REG_INT_STATUS);
++ enable.u32 = symc_read(REG_INT_EN);
++ cfg.u32 = symc_read(REG_SEC_CHN_CFG);
+
-+ HI_LOG_ERROR("\nsec_chn_cfg 0x%x, chn %d, nsec_int_en 0x%x, sec_int_en 0x%x, chn_obuf_en 0x%x, status 0x%x, raw 0x%x\n",
++ hi_log_error("\nsec_chn_cfg 0x%x, chn %u, nsec_int_en 0x%x, sec_int_en 0x%x, chn_obuf_en 0x%x, status 0x%x, "
++ "raw 0x%x\n",
+ (cfg.bits.sec_chn_cfg >> chn_num) & 0x01,
+ chn_num, enable.bits.int_en, enable.bits.sec_int_en,
+ (enable.bits.chn_obuf_en >> chn_num) & 0x01,
+ (status.bits.chn_obuf_int >> chn_num) & 0x01,
+ (raw.bits.chn_obuf_raw >> chn_num) & 0x01);
+
-+ HI_LOG_ERROR("\nThe cause of time out may be:\n"
++ hi_log_error("\nThe cause of time out may be:\n"
+ "\t1. SMMU address invalid\n"
+ "\t2. interrupt number or name incorrect\n"
+ "\t3. CPU type mismatching, request CPU and channel: %s\n",
+ crypto_is_sec_cpu() ? "secure" : "non-secure");
+
-+ /* avoid compile error when HI_LOG_ERROR be defined to empty */
-+ CRYPTO_UNUSED(raw);
-+ CRYPTO_UNUSED(status);
-+ CRYPTO_UNUSED(enable);
-+ CRYPTO_UNUSED(cfg);
++ /* a hi_void compile error when hi_log_error be defined to empty */
++ crypto_unused(raw);
++ crypto_unused(status);
++ crypto_unused(enable);
++ crypto_unused(cfg);
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+
-+static void drv_symc_get_err_code(hi_u32 chn_num)
++hi_void drv_symc_get_err_code(hi_u32 chn_num)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+#ifdef CRYPTO_SMMU_SUPPORT
+ {
@@ -203780,83 +272890,79 @@ index 0000000..43453fe
+ */
+ hi_u32 code = 0;
+
-+ /*read error code*/
++ /* read error code. */
+ if (crypto_is_sec_cpu()) {
-+ code = SMMU_READ(REG_MMU_INTRAW_S);
-+ SMMU_WRITE(REG_MMU_INTRAW_S, code);
++ code = smmu_read(REG_MMU_INTRAW_S);
++ smmu_write(REG_MMU_INTRAW_S, code);
+ } else {
-+ code = SMMU_READ(REG_MMU_INTRAW_NS);
-+ SMMU_WRITE(REG_MMU_INTRAW_NS, code);
++ code = smmu_read(REG_MMU_INTRAW_NS);
++ smmu_write(REG_MMU_INTRAW_NS, code);
+ }
-+ HI_LOG_INFO("symc done, hardware error code 0x%x\n", code);
++ hi_log_info("symc done, hardware error code 0x%x\n", code);
+
-+ if ((code >> 3) & 0x01) {
-+ HI_LOG_ERROR("MMU Error, there is a TLB Write invalid generated during the translation process.\n");
++ if ((code >> SHIFT_3BITS) & 0x01) {
++ hi_log_error("MMU Error, there is a TLB Write invalid generated during the translation process.\n");
+ }
-+ if ((code >> 2) & 0x01) {
-+ HI_LOG_ERROR("MMU Error, there is a TLB read invalid generated during the translation process.\n");
++ if ((code >> SHIFT_2BITS) & 0x01) {
++ hi_log_error("MMU Error, there is a TLB read invalid generated during the translation process.\n");
+ }
-+ if ((code >> 1) & 0x01) {
-+ HI_LOG_ERROR("MMU Error, the PTW transaciont receive an error response.\n");
++ if ((code >> SHIFT_1BITS) & 0x01) {
++ hi_log_error("MMU Error, the PTW transaciont receive an error response.\n");
+ }
+ if ((code) & 0x01) {
-+ HI_LOG_ERROR("MMU Error, there is a TLB miss generated during the translation process.\n");
++ hi_log_error("MMU Error, there is a TLB miss generated during the translation process.\n");
+ }
+ }
+#endif
+
-+ /*print the inout buffer address*/
++ /* print the inout buffer address. */
+ drv_symc_print_last_node(chn_num);
+ drv_symc_print_status(chn_num);
+
-+ HI_LOG_FUNC_EXIT();
-+ return;
++ hi_log_func_exit();
+}
+
-+void drv_symc_enrty_init(crypto_mem mem)
++hi_void drv_symc_enrty_init(crypto_mem mem)
+{
+ hi_u32 i;
-+ hi_u32 dma_addr = 0;
-+ hi_u32 mmz_addr = 0;
-+ void *cpu_addr = HI_NULL;
++ hi_u32 dma_addr;
++ hi_u32 mmz_addr;
++ hi_void *cpu_addr = HI_NULL;
+
-+ HI_LOG_INFO("symc entry list configure\n");
-+ dma_addr = ADDR_L32(mem.dma_addr);
-+ mmz_addr = ADDR_L32(mem.mmz_addr);
++ hi_log_info("symc entry list configure\n");
++ dma_addr = addr_l32(mem.dma_addr);
++ mmz_addr = addr_l32(mem.mmz_addr);
+ cpu_addr = mem.dma_virt;
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ if ((CIPHER_HARD_CHANNEL_MASK >> i) & 0x01) { /*valid channel*/
++ if ((CIPHER_HARD_CHANNEL_MASK >> i) & 0x01) { /* valid channel. */
+ drv_symc_set_entry(i, dma_addr, mmz_addr, cpu_addr);
-+ dma_addr += CHN_LIST_SIZE; /* move to next channel */
-+ mmz_addr += CHN_LIST_SIZE; /* move to next channel */
-+ cpu_addr = (hi_u8 *)cpu_addr + CHN_LIST_SIZE; /* move to next channel */
++ dma_addr += CHN_LIST_SIZE; /* move to next channel. */
++ mmz_addr += CHN_LIST_SIZE; /* move to next channel. */
++ cpu_addr = (hi_u8 *)cpu_addr + CHN_LIST_SIZE; /* move to next channel. */
+ }
+ }
-+ return;
+}
+
-+/* encrypt data using special chn*/
++/* encrypt data using special chn. */
+hi_s32 drv_cipher_aes_test(hi_void)
+{
-+ hi_s32 ret = HI_SUCCESS;
++ hi_s32 ret;
+ crypto_mem mem;
-+ hi_u32 chn = 0;
-+ hi_u32 last = 0, first = 0;
++ cryp_symc_context ctx;
++ hi_u32 chn, last, first, i;
+ hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD] = {0};
+ const char *gold_enc = "\x66\xE9\x4B\xD4\xEF\x8A\x2C\x3B\x88\x4C\xFA\x59\xCA\x34\x2B\x2E";
-+ hi_s32 i;
+
+ ret = crypto_mem_create(&mem, SEC_MMZ, "symc_data", AES_BLOCK_SIZE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, malloc ddr for symc test data failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_create, ret);
++ hi_log_print_func_err(crypto_mem_create, ret);
+ return ret;
+ }
+
-+ /* read last used channel */
-+ last = SYMC_READ(REG_HL_APP_LEN) & 0xFF;
++ /* read last used channel. */
++ last = symc_read(REG_HL_APP_LEN) & 0xFF;
+
-+ /* read the max valid channel */
++ /* read the max valid channel. */
+ for (i = CRYPTO_HARD_CHANNEL_MAX - 1; i > 0; i--) {
+ if (CIPHER_HARD_CHANNEL_MASK & (0x1 << i)) {
+ first = i;
@@ -203864,80 +272970,69 @@ index 0000000..43453fe
+ }
+ }
+
-+ /* select a channel dfferent with last used channel*/
-+ if ( last == first) {
++ /* select a channel dfferent with last used channel. */
++ if (last == first) {
+ chn = first - 1;
+ } else {
+ chn = first;
+ }
-+ HI_LOG_INFO("drv cipher aes test, first %d, last chn %d, use chn %d\n", first, last, chn);
++ hi_log_info("drv cipher aes test, first %u, last chn %u, use chn %u\n", first, last, chn);
+
-+ symc_hard_channel[chn].open = HI_TRUE;
-+ drv_symc_set_key(chn, key, HI_FALSE);
++ g_symc_hard_channel[chn].open = HI_TRUE;
++ drv_symc_set_key(chn, key, sizeof(key), HI_FALSE);
++
++ crypto_memset(&ctx, sizeof(ctx), 0, sizeof(ctx));
++ ctx.hard_chn = chn;
++ ctx.alg = SYMC_ALG_AES;
++ ctx.mode = SYMC_MODE_ECB;
++ ctx.width = SYMC_DAT_WIDTH_128;
++ ctx.sm1_round = 0;
++ ctx.hard_key = HI_FALSE;
++ crypto_chk_err_exit(drv_symc_cfg(&ctx, HI_FALSE, SYMC_KEY_DEFAULT));
+
-+ ret = drv_symc_config(chn, SYMC_ALG_AES, SYMC_MODE_ECB, SYMC_DAT_WIDTH_128,
-+ HI_FALSE, 0, SYMC_KEY_DEFAULT, HI_FALSE);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_config, ret);
-+ goto exit;
-+ }
+ crypto_memset(mem.dma_virt, AES_BLOCK_SIZE, 0, AES_BLOCK_SIZE);
+
-+ ret = drv_symc_add_inbuf(chn, mem.dma_addr, AES_BLOCK_SIZE, SYMC_NODE_USAGE_NORMAL);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
-+ goto exit;
-+ }
-+
-+ ret = drv_symc_add_outbuf(chn, mem.dma_addr, AES_BLOCK_SIZE, SYMC_NODE_USAGE_NORMAL);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_outbuf, ret);
-+ goto exit;
-+ }
++ crypto_chk_err_exit(drv_symc_add_inbuf(chn, mem.dma_addr, AES_BLOCK_SIZE, SYMC_NODE_USAGE_NORMAL));
++ crypto_chk_err_exit(drv_symc_add_outbuf(chn, mem.dma_addr, AES_BLOCK_SIZE, SYMC_NODE_USAGE_NORMAL));
+
+ /* start running */
-+ drv_symc_start(chn);
++ crypto_chk_err_exit(drv_symc_start(chn));
+
+ /* wait done */
-+ ret = drv_symc_wait_done(chn, CRYPTO_TIME_OUT);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_wait_done, ret);
-+ goto exit;
-+ }
++ crypto_chk_err_exit(drv_symc_wait_done(chn, CRYPTO_TIME_OUT));
+
-+ if (0 != memcmp(mem.dma_virt, gold_enc, AES_BLOCK_SIZE)) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_INIT);
++ if (memcmp(mem.dma_virt, gold_enc, AES_BLOCK_SIZE) != 0) {
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_INIT);
+ ret = HI_ERR_CIPHER_FAILED_INIT;
-+ goto exit;
++ goto exit__;
+ }
+
-+exit:
++exit__:
+ crypto_mem_destory(&mem);
-+ symc_hard_channel[chn].open = HI_FALSE;
-+
++ g_symc_hard_channel[chn].open = HI_FALSE;
+ return ret;
+}
+
+#ifdef CRYPTO_SWITCH_CPU
-+hi_u32 drv_symc_is_secure(void)
++hi_u32 drv_symc_is_secure(hi_void)
+{
+ sec_chn_cfg sec;
+ sec_chn_cfg tmp;
+ hi_u32 secure = HI_FALSE;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("Change the secure type of the chn0 to get cpu type\n");
++ hi_log_info("Change the secure type of the chn0 to get cpu type\n");
+ module_enable(CRYPTO_MODULE_ID_SYMC);
+
-+ sec.u32 = SYMC_READ(REG_SEC_CHN_CFG);
++ sec.u32 = symc_read(REG_SEC_CHN_CFG);
+
+ /* change the secure type of chn0 */
+ sec.bits.sec_chn_cfg ^= 0x01;
-+ SYMC_WRITE(REG_SEC_CHN_CFG, sec.u32);
++ symc_write(REG_SEC_CHN_CFG, sec.u32);
+
+ /* read the secure type of chn0 */
-+ tmp.u32 = SYMC_READ(REG_SEC_CHN_CFG);
++ tmp.u32 = symc_read(REG_SEC_CHN_CFG);
+
+ if (tmp.bits.sec_chn_cfg == sec.bits.sec_chn_cfg) {
+ /* The REG_SEC_CHN_CFG only can be set by secure CPU
@@ -203947,60 +273042,47 @@ index 0000000..43453fe
+
+ /* recovery the secure type of chn0 */
+ sec.bits.sec_chn_cfg ^= 0x01;
-+ SYMC_WRITE(REG_SEC_CHN_CFG, sec.u32);
++ symc_write(REG_SEC_CHN_CFG, sec.u32);
+ }
+
-+ HI_LOG_INFO("secure type: 0x%x\n", secure);
++ hi_log_info("secure type: 0x%x\n", secure);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return secure;
+}
+#endif
+
-+hi_s32 drv_symc_init(void)
++static hi_s32 drv_symc_cfg_init_value(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ crypto_memset(&g_symc_dma, sizeof(g_symc_dma), 0, sizeof(g_symc_dma));
++ hi_log_info("disable symc\n");
++ module_disable(CRYPTO_MODULE_ID_SYMC);
+
-+ if (symc_initialize == HI_TRUE) {
-+ return HI_SUCCESS;
-+ }
++ hi_log_info("enable symc\n");
++ module_enable(CRYPTO_MODULE_ID_SYMC);
+
-+ crypto_memset(&symc_dma, sizeof(symc_dma), 0, sizeof(symc_dma));
++ hi_log_info("enable smmu\n");
++ module_enable(CRYPTO_MODULE_ID_SMMU);
+
-+ ret = crypto_channel_init(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, sizeof(symc_hard_context));
++ hi_log_info("alloc memory for nodes list\n");
++ ret = crypto_mem_create(&g_symc_dma, SEC_MMZ, "symc_node_list", SYMC_NODE_LIST_SIZE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, symc channel list init failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_init, ret);
++ hi_log_print_func_err(crypto_mem_create, ret);
++ module_disable(CRYPTO_MODULE_ID_SMMU);
++ module_disable(CRYPTO_MODULE_ID_SYMC);
+ return ret;
+ }
+
-+ HI_LOG_INFO("disable symc\n");
-+ module_disable(CRYPTO_MODULE_ID_SYMC);
-+
-+ HI_LOG_INFO("enable symc\n");
-+ module_enable(CRYPTO_MODULE_ID_SYMC);
-+
-+ HI_LOG_INFO("enable smmu\n");
-+ module_enable(CRYPTO_MODULE_ID_SMMU);
-+
-+ HI_LOG_INFO("alloc memory for nodes list\n");
-+ ret = crypto_mem_create(&symc_dma, SEC_MMZ, "symc_node_list", SYMC_NODE_LIST_SIZE);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, malloc ddr for symc nodes list failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_create, ret);
-+ goto __error1;
-+ }
-+
-+ HI_LOG_INFO("symc secure channel configure\n");
++ hi_log_info("symc secure channel configure\n");
+ drv_symc_enable_secure();
+
-+ HI_LOG_INFO("symc entry list configure\n");
-+ drv_symc_enrty_init(symc_dma);
++ hi_log_info("symc entry list configure\n");
++ drv_symc_enrty_init(g_symc_dma);
+
+#ifdef CRYPTO_SMMU_SUPPORT
-+ HI_LOG_INFO("symc SMMU configure\n");
++ hi_log_info("symc SMMU configure\n");
+ drv_symc_smmu_int_disable();
+ drv_symc_smmu_bypass();
+ drv_symc_smmu_base_addr();
@@ -204012,20 +273094,46 @@ index 0000000..43453fe
+ drv_symc_smmint_enable();
+#endif
+
-+ HI_LOG_INFO("symc interrupt configure\n");
++ hi_log_info("symc interrupt configure\n");
+ drv_symc_set_interrupt();
+
-+ HI_LOG_INFO("symc register interrupt function\n");
++ hi_log_info("symc register interrupt function\n");
+ ret = drv_symc_register_interrupt();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, register interrupt failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_register_interrupt, ret);
-+ crypto_mem_destory(&symc_dma);
-+ goto __error1;
++ hi_log_error("error, register interrupt failed\n");
++ hi_log_print_func_err(drv_symc_register_interrupt, ret);
++ crypto_mem_destory(&g_symc_dma);
++ module_disable(CRYPTO_MODULE_ID_SMMU);
++ module_disable(CRYPTO_MODULE_ID_SYMC);
++ return ret;
+ }
+#endif
+
-+ symc_initialize = HI_TRUE;
++ return HI_SUCCESS;
++}
++
++hi_s32 drv_symc_init(hi_void)
++{
++ hi_s32 ret;
++
++ hi_log_func_enter();
++
++ if (g_symc_initialize == HI_TRUE) {
++ return HI_SUCCESS;
++ }
++
++ ret = crypto_channel_init(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, sizeof(symc_hard_context));
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_channel_init, ret);
++ return ret;
++ }
++
++ ret = drv_symc_cfg_init_value();
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_cfg_init_value, ret);
++ (hi_void)crypto_channel_deinit(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
++ return ret;
++ }
+
+ /* because can't reset hardware under tee environment
+ * the low channel(1 or 2) may be used by boot or loader,
@@ -204036,59 +273144,49 @@ index 0000000..43453fe
+ */
+ ret = drv_cipher_aes_test();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_cipher_aes_test, ret);
++ hi_log_print_func_err(drv_cipher_aes_test, ret);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ g_symc_initialize = HI_TRUE;
++ hi_log_func_exit();
+ return HI_SUCCESS;
-+
-+__error1:
-+ module_disable(CRYPTO_MODULE_ID_SMMU);
-+ module_disable(CRYPTO_MODULE_ID_SYMC);
-+ crypto_channel_deinit(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
-+
-+ symc_initialize = HI_FALSE;
-+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return ret;
+}
+
-+hi_s32 drv_symc_deinit(void)
++hi_s32 drv_symc_deinit(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
++ hi_log_chk_init_err_return(g_symc_initialize);
+
-+ crypto_mem_destory(&symc_dma);
++ crypto_mem_destory(&g_symc_dma);
+
+ module_disable(CRYPTO_MODULE_ID_SYMC);
+ module_disable(CRYPTO_MODULE_ID_SMMU);
+
-+ crypto_channel_deinit(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
++ crypto_channel_deinit(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
+ drv_symc_unregister_interrupt();
+#endif
+
-+ symc_initialize = HI_FALSE;
++ g_symc_initialize = HI_FALSE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_symc_resume(void)
++hi_s32 drv_symc_resume(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("enable symc\n");
++ hi_log_info("enable symc\n");
+ module_enable(CRYPTO_MODULE_ID_SYMC);
+ module_enable(CRYPTO_MODULE_ID_SMMU);
+ module_disable(CRYPTO_MODULE_ID_SM4);
+
+ /* must be called before set register of
-+ - interrupt
-+ - channel
++ * - interrupt
++ * - channel
+ */
+ drv_symc_enable_secure();
+
@@ -204105,39 +273203,38 @@ index 0000000..43453fe
+ drv_symc_set_interrupt();
+#endif
+
-+ drv_symc_enrty_init(symc_dma);
++ drv_symc_enrty_init(g_symc_dma);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
-+
+}
+
-+void drv_symc_suspend(void)
++hi_void drv_symc_suspend(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_disable(CRYPTO_MODULE_ID_SYMC);
+ module_disable(CRYPTO_MODULE_ID_SMMU);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return ;
+}
+
+hi_s32 drv_symc_alloc_chn(hi_u32 *chn_num)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 list = 0;
++ hi_s32 ret;
++ hi_u32 list;
+ hi_u32 chn = 0;
+ hi_u32 resume = HI_FALSE;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
++ hi_log_chk_init_err_return(g_symc_initialize);
+
-+ ret = crypto_channel_alloc(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX,
++ ret = crypto_channel_alloc(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX,
+ CIPHER_HARD_CHANNEL_MASK, &chn);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_alloc, ret);
++ hi_log_print_func_err(crypto_channel_alloc, ret);
+ return ret;
+ }
+
@@ -204146,16 +273243,16 @@ index 0000000..43453fe
+ * in this case, the hardware configuration will be reset,
+ * here try to re-config the hardware.
+ */
-+ list = SYMC_READ(REG_CHANn_SRC_LST_SADDR(chn));
++ list = symc_read(reg_chann_src_lst_saddr(chn));
+
+#ifdef CRYPTO_SMMU_SUPPORT
+ {
+ hi_u32 base = 0;
+
+ if (crypto_is_sec_cpu()) {
-+ base = SMMU_READ(REG_MMU_SCB_TTBR);
++ base = smmu_read(REG_MMU_SCB_TTBR);
+ } else {
-+ base = SMMU_READ(REG_MMU_CB_TTBR);
++ base = smmu_read(REG_MMU_CB_TTBR);
+ }
+ if ((list == 0) || (base == 0)) {
+ resume = HI_TRUE;
@@ -204171,37 +273268,33 @@ index 0000000..43453fe
+ /* smmu base address or node list address is zero
+ * means hardware be unexpected reset
+ */
-+ HI_LOG_WARN("cipher module is not ready, try to resume it now...\n");
++ hi_log_warn("cipher module is not ready, try to resume it now...\n");
+ ret = drv_symc_resume();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_resume, ret);
++ hi_log_print_func_err(drv_symc_resume, ret);
+ return ret;
+ }
+ }
+
+ *chn_num = chn;
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void drv_symc_free_chn(hi_u32 chn_num)
++hi_void drv_symc_free_chn(hi_u32 chn_num)
+{
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ ctx = crypto_channel_get_context(symc_hard_channel,
-+ CRYPTO_HARD_CHANNEL_MAX, chn_num);
++ hi_log_func_enter();
+
++ ctx = crypto_channel_get_context(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
+ if (ctx->destory != HI_NULL) {
+ ctx->destory();
+ ctx->destory = HI_NULL;
+ }
+
-+ crypto_channel_free(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
-+
-+ HI_LOG_FUNC_EXIT();
-+ return;
++ crypto_channel_free(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
++ hi_log_func_exit();
+}
+
+hi_s32 drv_symc_set_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD], hi_u32 ivlen, hi_u32 flag)
@@ -204209,49 +273302,52 @@ index 0000000..43453fe
+ hi_u32 i;
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ CRYPTO_UNUSED(ivlen);
++ crypto_unused(ivlen);
+
-+ ctx = crypto_channel_get_context(symc_hard_channel,
++ ctx = crypto_channel_get_context(g_symc_hard_channel,
+ CRYPTO_HARD_CHANNEL_MAX, chn_num);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto channel get context failed,ctx is null!\n");
++ hi_log_error("crypto channel get context failed, ctx is null!\n");
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
-+ /*copy iv data into channel context*/
++ /* copy iv data into channel context. */
+ for (i = 0; i < SYMC_IV_MAX_SIZE_IN_WORD; i++) {
+ ctx->iv[i] = iv[i];
-+ HI_LOG_INFO("IV[%d] 0x%x\n", i, iv[i]);
++ hi_log_info("IV[%d] 0x%x\n", i, iv[i]);
+ }
+ ctx->iv_flag = flag;
+
-+ HI_LOG_INFO("iv_flag 0x%x\n", flag);
++ hi_log_info("iv_flag 0x%x\n", flag);
+
-+ HI_LOG_FUNC_EXIT();
-+ return;
++ hi_log_func_exit();
++ return HI_SUCCESS;
+}
+
-+void drv_symc_get_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD])
++hi_void drv_symc_get_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD])
+{
+ hi_u32 i;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ for (i = 0; i < SYMC_IV_MAX_SIZE_IN_WORD; i++) {
-+ iv[i] = SYMC_READ(REG_CHAN_CIPHER_IVOUT(chn_num) + i * 4);
++ iv[i] = symc_read(reg_chan_cipher_ivout(chn_num) + i * WORD_WIDTH);
+ }
+
-+ HI_LOG_FUNC_EXIT();
-+ return;
++ hi_log_func_exit();
+}
+
-+void drv_symc_set_key(hi_u32 chn_num, hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD], hi_u32 odd)
++hi_void drv_symc_set_key(hi_u32 chn_num, hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD], hi_u32 key_len, hi_u32 odd)
+{
+ hi_u32 i;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
++
++ if (key_len < SYMC_KEY_MAX_SIZE_IN_WORD * WORD_WIDTH) {
++ return;
++ }
+
+ /* unsupport odd key */
+ if (odd) {
@@ -204259,18 +273355,47 @@ index 0000000..43453fe
+ }
+
+ for (i = 0; i < SYMC_KEY_MAX_SIZE_IN_WORD; i++) {
-+ SYMC_WRITE(REG_CIPHER_KEY(chn_num) + i * 4, key[i]);
++ symc_write(reg_cipher_key(chn_num) + i * WORD_WIDTH, key[i]);
+ }
+
-+ HI_LOG_FUNC_EXIT();
-+ return;
++ hi_log_func_exit();
+}
+
-+void drv_symc_set_sm1_sk(hi_u32 chn_num, hi_u32 key[SYMC_SM1_SK_SIZE_IN_WORD])
++hi_void drv_symc_set_sm1_sk(hi_u32 chn_num, hi_u32 key[SYMC_SM1_SK_SIZE_IN_WORD], hi_u32 key_len)
+{
-+ CRYPTO_UNUSED(chn_num);
-+ CRYPTO_UNUSED(key);
-+ return;
++ crypto_unused(chn_num);
++ crypto_unused(key);
++ crypto_unused(key_len);
++}
++
++static hi_void drv_symc_add_iv_to_node(symc_hard_context *ctx, hi_u32 *iv_flg, hi_u8 *iv, hi_u32 iv_len, hi_u32 *flgs)
++{
++ hi_u32 *node_iv = (hi_u32 *)iv;
++
++ crypto_unused(iv_len);
++
++ /* first node must set iv except ecb mode. */
++ if (ctx->iv_flag == HI_CIPHER_IV_CHG_ONE_PACK) {
++ *iv_flg = HI_TRUE;
++
++ /* don't set iv any more. */
++ ctx->iv_flag = 0;
++ } else if (ctx->iv_flag == HI_CIPHER_IV_CHG_ALL_PACK) {
++ *iv_flg = HI_TRUE;
++ }
++
++ /* set iv to node */
++ if (node_iv != HI_NULL) {
++ *flgs |= SYMC_BUF_LIST_FLAG_IVSET;
++ node_iv[WORD_IDX_0] = ctx->iv[WORD_IDX_0];
++ node_iv[WORD_IDX_1] = ctx->iv[WORD_IDX_1];
++ node_iv[WORD_IDX_2] = ctx->iv[WORD_IDX_2];
++ node_iv[WORD_IDX_3] = ctx->iv[WORD_IDX_3];
++ hi_log_debug("iv[0] 0x%x\n", node_iv[WORD_IDX_0]);
++ hi_log_debug("iv[1] 0x%x\n", node_iv[WORD_IDX_1]);
++ hi_log_debug("iv[2] 0x%x\n", node_iv[WORD_IDX_2]);
++ hi_log_debug("iv[3] 0x%x\n", node_iv[WORD_IDX_3]);
++ }
+}
+
+hi_s32 drv_symc_add_inbuf(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size, symc_node_usage usage)
@@ -204279,26 +273404,25 @@ index 0000000..43453fe
+ hi_u32 *node_iv = HI_NULL;
+ symc_hard_context *ctx = HI_NULL;
+ hi_u32 iv_flag = HI_FALSE;
-+ hi_u32 length = 0;
++ hi_u32 length;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ HI_LOG_CHECK_PARAM(0 == buf_size);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ hi_log_chk_param_return(buf_size == 0);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ ctx = crypto_channel_get_context(symc_hard_channel,
-+ CRYPTO_HARD_CHANNEL_MAX, chn_num);
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->cnt >= SYMC_MAX_LIST_NUM);
-+ HI_LOG_CHECK_PARAM(ctx->id_in >= SYMC_MAX_LIST_NUM);
-+ HI_LOG_CHECK_PARAM(ctx->id_out >= SYMC_MAX_LIST_NUM);
++ ctx = crypto_channel_get_context(g_symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
++ hi_log_chk_param_return(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx->cnt >= SYMC_MAX_LIST_NUM);
++ hi_log_chk_param_return(ctx->id_in >= SYMC_MAX_LIST_NUM);
++ hi_log_chk_param_return(ctx->id_out >= SYMC_MAX_LIST_NUM);
+
-+ /* split the buf to mutlit node, as the max length of one node is 1M-16*/
++ /* split the buf to mutlit node, as the max length of one node is 1M-16. */
+ while (buf_size > 0) {
+ if (ctx->cnt > SYMC_MAX_LIST_NUM) {
-+ HI_LOG_ERROR("node count %d overflow, max %d\n", ctx->cnt, SYMC_MAX_LIST_NUM);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_OVERFLOW);
++ hi_log_error("node count %d overflow, max %d\n", ctx->cnt, SYMC_MAX_LIST_NUM);
++ hi_log_print_err_code(HI_ERR_CIPHER_OVERFLOW);
+ return HI_ERR_CIPHER_OVERFLOW;
+ }
+
@@ -204311,52 +273435,31 @@ index 0000000..43453fe
+ node_iv = ctx->entry_iv[ctx->id_in].iv;
+ iv_flag = HI_FALSE;
+
-+ /*set dma addr and size, only support 32bit ddr*/
-+ entry->phy_addr = ADDR_L32(buf_phy);
++ /* set dma addr and size, only support 32bit ddr. */
++ entry->phy_addr = addr_l32(buf_phy);
+ entry->length = length;
+
-+ /*set flag*/
++ /* set flag. */
+ entry->flags = SYMC_BUF_LIST_FLAG_DUMM | SYMC_BUF_LIST_FLAG_EOL;
+
-+ HI_LOG_INFO("add inbuf, chn %d, id %d, addr 0x%x, length 0x%x, iv_flag %d\n",
++ hi_log_info("add inbuf, chn %d, id %d, addr 0x%x, length 0x%x, iv_flag %d\n",
+ chn_num, ctx->id_in, entry->phy_addr, entry->length, ctx->iv_flag);
+
-+ /*first node must set iv except ecb mode*/
-+ if (ctx->iv_flag == CIPHER_IV_CHANGE_ONE_PKG) {
-+ iv_flag = HI_TRUE;
++ drv_symc_add_iv_to_node(ctx, &iv_flag, (hi_u8 *)node_iv, sizeof(ctx->iv), &entry->flags);
+
-+ /* don't set iv any more*/
-+ ctx->iv_flag = 0;
-+ } else if (ctx->iv_flag == CIPHER_IV_CHANGE_ALL_PKG) {
-+ iv_flag = HI_TRUE;
-+ }
-+
-+ /* set iv to node */
-+ if (iv_flag) {
-+ entry->flags |= SYMC_BUF_LIST_FLAG_IVSET;
-+ node_iv[0] = ctx->iv[0];
-+ node_iv[1] = ctx->iv[1];
-+ node_iv[2] = ctx->iv[2];
-+ node_iv[3] = ctx->iv[3];
-+ HI_LOG_DEBUG("iv[0] 0x%x\n", node_iv[0]);
-+ HI_LOG_DEBUG("iv[1] 0x%x\n", node_iv[1]);
-+ HI_LOG_DEBUG("iv[2] 0x%x\n", node_iv[2]);
-+ HI_LOG_DEBUG("iv[3] 0x%x\n", node_iv[3]);
-+ }
-+
-+ /* move to next node, reset to zero if overflow*/
++ /* move to next node, reset to zero if overflow. */
+ ctx->id_in++;
+ if (ctx->id_in == SYMC_MAX_LIST_NUM) {
+ ctx->id_in = 0;
+ }
+
-+ /* total count of computed nodes add 1*/
++ /* total count of computed nodes add 1. */
+ ctx->cnt++;
+
-+ ADDR_L32(buf_phy) += length;
++ addr_l32(buf_phy) += length;
+ buf_size -= length;
+ }
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -204364,230 +273467,226 @@ index 0000000..43453fe
+{
+ symc_entry *entry = HI_NULL;
+ symc_hard_context *ctx = HI_NULL;
-+ hi_u32 length = 0;
++ hi_u32 length;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
-+ HI_LOG_CHECK_PARAM(buf_size == 0);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(buf_size == 0);
+
-+ CRYPTO_UNUSED(usage);
++ crypto_unused(usage);
+
-+ ctx = crypto_channel_get_context(symc_hard_channel,
++ ctx = crypto_channel_get_context(g_symc_hard_channel,
+ CRYPTO_HARD_CHANNEL_MAX, chn_num);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto channel get context failed,ctx is null!\n");
++ hi_log_error("crypto channel get context failed, ctx is null!\n");
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
-+ /* split the buf to mutlit node, as the max length of one node is 1M-16*/
++ /* split the buf to mutlit node, as the max length of one node is 1M-16. */
+ while (buf_size > 0) {
-+ if ( buf_size > MAX_NODE_SIZE) {
++ if (buf_size > MAX_NODE_SIZE) {
+ length = MAX_NODE_SIZE;
+ } else {
+ length = buf_size;
+ }
+ entry = &ctx->entry_out[ctx->id_out];
+
-+ /*set dma addr and size, only support 32bit ddr*/
-+ entry->phy_addr = ADDR_L32(buf_phy);
++ /* set dma addr and size, only support 32bit ddr. */
++ entry->phy_addr = addr_l32(buf_phy);
+ entry->length = length;
+
-+ HI_LOG_INFO("add outbuf, chn %d, id %d, addr 0x%x, length 0x%x\n",
++ hi_log_info("add outbuf, chn %d, id %d, addr 0x%x, length 0x%x\n",
+ chn_num, ctx->id_out, entry->phy_addr, entry->length);
+
-+ /*set flag*/
++ /* set flag. */
+ entry->flags = SYMC_BUF_LIST_FLAG_DUMM | SYMC_BUF_LIST_FLAG_EOL;
+
-+ /*move to next node, reset to zero if overflow*/
++ /* move to next node, reset to zero if overflow. */
+ ctx->id_out++;
+ if (ctx->id_out == SYMC_MAX_LIST_NUM) {
+ ctx->id_out = 0;
+ }
+
-+ ADDR_L32(buf_phy) += length;
++ addr_l32(buf_phy) += length;
+ buf_size -= length;
+ }
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_aead_ccm_add_n(hi_u32 chn_num, hi_u8 *n)
++hi_s32 drv_aead_ccm_add_n(hi_u32 chn_num, hi_u8 *nonce, hi_u32 nonce_len)
+{
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ CRYPTO_UNUSED(chn_num);
-+ CRYPTO_UNUSED(n);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ crypto_unused(chn_num);
++ crypto_unused(nonce);
++ crypto_unused(nonce_len);
+
+ return HI_ERR_CIPHER_UNSUPPORTED;
+}
+
+hi_s32 drv_aead_ccm_add_a(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size)
+{
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ CRYPTO_UNUSED(chn_num);
-+ CRYPTO_UNUSED(buf_phy);
-+ CRYPTO_UNUSED(buf_size);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ crypto_unused(chn_num);
++ crypto_unused(buf_phy);
++ crypto_unused(buf_size);
+
+ return HI_ERR_CIPHER_UNSUPPORTED;
+}
+
+hi_s32 drv_aead_gcm_add_a(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ CRYPTO_UNUSED(chn_num);
-+ CRYPTO_UNUSED(buf_phy);
-+ CRYPTO_UNUSED(buf_size);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ crypto_unused(chn_num);
++ crypto_unused(buf_phy);
++ crypto_unused(buf_size);
+
+ return HI_ERR_CIPHER_UNSUPPORTED;
+}
+
-+hi_s32 drv_aead_get_tag(hi_u32 chn_num, hi_u32 *tag)
++hi_s32 drv_aead_get_tag(hi_u32 chn_num, hi_u32 *tag, hi_u32 tag_buf_len)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ CRYPTO_UNUSED(chn_num);
-+ CRYPTO_UNUSED(tag);
-+
-+ return HI_FAILURE;
-+}
-+
-+hi_s32 drv_aead_gcm_add_clen(hi_u32 chn_num, hi_u8 *clen)
-+{
-+ HI_LOG_FUNC_ENTER();
-+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ CRYPTO_UNUSED(chn_num);
-+ CRYPTO_UNUSED(clen);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ crypto_unused(chn_num);
++ crypto_unused(tag);
++ crypto_unused(tag_buf_len);
+
+ return HI_ERR_CIPHER_UNSUPPORTED;
+}
+
-+void drv_symc_add_buf_usage(hi_u32 chn_num, hi_u32 in, symc_node_usage usage)
++hi_s32 drv_aead_gcm_add_clen(hi_u32 chn_num, hi_u8 *clen, hi_u32 clen_len)
+{
-+ CRYPTO_UNUSED(chn_num);
-+ CRYPTO_UNUSED(in);
-+ CRYPTO_UNUSED(usage);
++ hi_log_func_enter();
++
++ hi_log_chk_init_err_return(g_symc_initialize);
++ crypto_unused(chn_num);
++ crypto_unused(clen);
++ crypto_unused(clen_len);
++
++ return HI_ERR_CIPHER_UNSUPPORTED;
+}
+
-+hi_s32 drv_symc_node_check(symc_alg alg, symc_mode mode,
-+ hi_u32 klen, hi_u32 block_size,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num)
++hi_void drv_symc_add_buf_usage(hi_u32 chn_num, hi_u32 in, symc_node_usage usage)
+{
-+ hi_u32 i;
-+ hi_u32 tail = 0;
++ crypto_unused(chn_num);
++ crypto_unused(in);
++ crypto_unused(usage);
++}
+
-+ HI_LOG_FUNC_ENTER();
++hi_s32 drv_symc_node_check(symc_alg alg, symc_mode mode, hi_u32 klen, hi_u32 block_size, symc_multi_pack *pack)
++{
++ hi_u32 i, tail;
+
-+ HI_LOG_CHECK_PARAM(block_size == 0);
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ CRYPTO_UNUSED(alg);
-+ CRYPTO_UNUSED(mode);
-+ CRYPTO_UNUSED(klen);
-+ CRYPTO_UNUSED(input);
-+ CRYPTO_UNUSED(output);
-+ CRYPTO_UNUSED(usage_list);
++ hi_log_chk_param_return(block_size == 0);
++ hi_log_chk_param_return(pack == 0);
+
-+ for (i = 0; i < pkg_num; i++) {
-+ HI_LOG_DEBUG("node %d, length 0x%x\n", i, length[i]);
-+ if (0 != (length[i] % block_size)) {
++ hi_log_chk_init_err_return(g_symc_initialize);
++ crypto_unused(alg);
++ crypto_unused(mode);
++ crypto_unused(klen);
++ crypto_unused(pack->in);
++ crypto_unused(pack->out);
++ crypto_unused(pack->usage);
++
++ for (i = 0; i < pack->num; i++) {
++ hi_log_debug("node %d, length 0x%x\n", i, pack->len[i]);
++ if ((pack->len[i] % block_size) != 0) {
+ /* The last block of CTR mode don't need align with block size,
+ * but the hardware require the data size must align with block size,
+ * as the MMZ/MMU size is align with page size(4K) by system,
+ * here we can increase the last block size to align with block size.
+ */
-+ if ((mode == SYMC_MODE_CTR) && (i == pkg_num - 1)) {
-+ tail = length[i] % block_size;
-+ if ( 0x00 != tail) {
-+ length[i] += block_size - tail;
-+ }
-+ } else {
-+ HI_LOG_ERROR("error, node length must be multiple of block size %d.\n", block_size);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_LENGTH);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
++ if ((mode != SYMC_MODE_CTR) || (i != pack->num - 1)) {
++ hi_log_error("error, node length must be multiple of block size %d.\n", block_size);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_LEN);
++ return HI_ERR_CIPHER_INVALID_LEN;
++ }
++
++ tail = pack->len[i] % block_size;
++ if (tail != 0) {
++ pack->len[i] += block_size - tail;
+ }
+ }
+
-+ /* each node length can't be zero*/
-+ if (length[i] == 0) {
-+ HI_LOG_ERROR("PKG len must large than 0.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_LENGTH);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
++ /* each node length can't be zero. */
++ if (pack->len[i] == 0) {
++ hi_log_error("PKG len must large than 0.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_LEN);
++ return HI_ERR_CIPHER_INVALID_LEN;
+ }
+
+ /* check overflow */
-+ if (length[i] > ADDR_L32(input[i]) + length[i]) {
-+ HI_LOG_ERROR("PKG len overflow.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_LENGTH);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
++ if (pack->len[i] > addr_l32(pack->in[i]) + pack->len[i]) {
++ hi_log_error("PKG len overflow.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_LEN);
++ return HI_ERR_CIPHER_INVALID_LEN;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_symc_config(hi_u32 chn_num, symc_alg alg, symc_mode mode, symc_width width,
-+ hi_u32 decrypt, hi_u32 sm1_round_num, symc_klen klen, hi_u32 hard_key)
++hi_s32 drv_symc_cfg(cryp_symc_context *ctx, hi_u32 decrypt, symc_klen klen)
+{
+ chann_chipher_ctrl ctrl;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
-+ HI_LOG_CHECK_PARAM(alg > SYMC_ALG_AES);
-+ HI_LOG_CHECK_PARAM(mode > SYMC_MODE_CTR);
-+ HI_LOG_CHECK_PARAM(klen >= SYMC_KEY_LEN_COUNT);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ hi_log_chk_param_return(ctx->hard_chn >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(ctx->alg > SYMC_ALG_AES);
++ hi_log_chk_param_return(ctx->mode > SYMC_MODE_CTR);
++ hi_log_chk_param_return(klen >= SYMC_KEY_LEN_COUNT);
+
-+ CRYPTO_UNUSED(sm1_round_num);
++ crypto_unused(ctx->sm1_round);
+
-+ ctrl.u32 = SYMC_READ(REG_CHANn_CIPHER_CTRL(chn_num));
++ ctrl.u32 = symc_read(reg_chann_cipher_ctrl(ctx->hard_chn));
+
+ ctrl.bits.decrypt = decrypt;
-+ ctrl.bits.mode = mode;
-+ ctrl.bits.alg_sel = alg;
-+ ctrl.bits.width = width;
++ ctrl.bits.mode = ctx->mode;
++ ctrl.bits.alg_sel = ctx->alg;
++ ctrl.bits.width = ctx->width;
+ ctrl.bits.key_length = klen;
-+ ctrl.bits.key_sel = hard_key;
-+ ctrl.bits.key_adder = chn_num;
++ ctrl.bits.key_sel = ctx->hard_key;
++ ctrl.bits.key_adder = ctx->hard_chn;
+ ctrl.bits.weight = 1;
+
-+ SYMC_WRITE(REG_CHANn_CIPHER_CTRL(chn_num), ctrl.u32);
-+ HI_LOG_INFO("REG_CHANn_CIPHER_CTRL[%d] 0x%x\n", chn_num, ctrl.u32);
++ symc_write(reg_chann_cipher_ctrl(ctx->hard_chn), ctrl.u32);
++ hi_log_info("reg_chann_cipher_ctrl[%d] 0x%x\n", ctx->hard_chn, ctrl.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_symc_set_isr_callback(hi_u32 chn_num, callback_symc_isr callback, void *ctx)
++hi_s32 drv_symc_set_isr_callback(hi_u32 chn_num, callback_symc_isr callback, hi_void *ctx)
+{
+ symc_hard_context *hisi_ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ hisi_ctx = crypto_channel_get_context(symc_hard_channel,
++ hisi_ctx = crypto_channel_get_context(g_symc_hard_channel,
+ CRYPTO_HARD_CHANNEL_MAX, chn_num);
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto channel get context failed,hisi_ctx is null!\n");
++ hi_log_error("crypto channel get context failed, hisi_ctx is null!\n");
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
+ hisi_ctx->callback = callback;
+ hisi_ctx->ctx = ctx;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -204595,88 +273694,93 @@ index 0000000..43453fe
+{
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
-+ ctx = crypto_channel_get_context(symc_hard_channel,
++ hi_log_chk_init_err_return(g_symc_initialize);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ ctx = crypto_channel_get_context(g_symc_hard_channel,
+ CRYPTO_HARD_CHANNEL_MAX, chn_num);
-+ HI_LOG_CHECK_PARAM(ctx->cnt < 0x01);
++ hi_log_chk_param_return(ctx->cnt < 0x01);
+
-+ HI_LOG_INFO("symc start, chn %d, cnt %d\n", chn_num, ctx->cnt);
++ hi_log_info("symc start, chn %d, cnt %d\n", chn_num, ctx->cnt);
+
+ ctx->done = HI_FALSE;
+
-+ /* read last used channel */
-+ SYMC_WRITE(REG_HL_APP_LEN, chn_num);
++ /* read last used channel. */
++ symc_write(REG_HL_APP_LEN, chn_num);
+
-+ /*start work, the count of nodes to be computed is ctx->cnt*/
-+ SYMC_WRITE(REG_CHANn_INT_OCNTCFG(chn_num), ctx->cnt);
-+ SYMC_WRITE(REG_CHANn_OBUF_CNT(chn_num), ctx->cnt);
-+ SYMC_WRITE(REG_CHANn_IBUF_CNT(chn_num), ctx->cnt);
++ /* start work, the count of nodes to be computed is ctx->cnt. */
++ symc_write(reg_chann_int_ocntcfg(chn_num), ctx->cnt);
++ symc_write(reg_chann_obuf_cnt(chn_num), ctx->cnt);
++ symc_write(reg_chann_ibuf_cnt(chn_num), ctx->cnt);
++
++ hi_log_func_exit();
++ return HI_SUCCESS;
++}
++
++static hi_s32 drv_symc_query_raw_interrupt(hi_u32 chn_num, hi_u32 timeout)
++{
++ /* interrupt unsupport, query the raw interrupt flag. */
++ for (i = 0; i < timeout; i++) {
++ if (drv_symc_done_try(chn_num)) {
++ break;
++ }
++ if (i <= MS_TO_US) {
++ crypto_udelay(1); /* short waitting for 1000 us. */
++ } else {
++ crypto_msleep(1); /* long waitting for 5000 ms. */
++ }
++ }
++ if (timeout <= i) {
++ hi_log_error("symc wait done timeout, chn=%d\n", chn_num);
++ hi_log_print_func_err(crypto_queue_wait_timeout, HI_ERR_CIPHER_TIMEOUT);
++ drv_symc_get_err_code(chn_num);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
+
-+ HI_LOG_FUNC_EXIT();
+ return HI_SUCCESS;
+}
+
+hi_s32 drv_symc_wait_done(hi_u32 chn_num, hi_u32 timeout)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
-+ hi_u32 i;
++ hi_s32 ret;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_INITED(symc_initialize);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_init_err_return(g_symc_initialize);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, HI_NULL);
+
-+ HI_LOG_INFO("symc wait done, chn %d\n", chn_num);
++ hi_log_info("symc wait done, chn %d\n", chn_num);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ /* interrupt support, wait irq*/
+ if (int_valid) {
-+ hi_s32 ret = HI_FAILURE;
-+ symc_hard_context *ctx = HI_NULL;
-+
-+ ctx = crypto_channel_get_context(symc_hard_channel, CRYPTO_HARD_CHANNEL_MAX, chn_num);
-+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto channel get context failed, ctx is null, chn=%d\n", chn_num);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_get_context, HI_ERR_CIPHER_INVALID_POINT);
-+ return HI_ERR_CIPHER_INVALID_POINT;
++ /* interrupt support, wait irq. */
++ ret = drv_symc_wait_irq(chn_num, timeout);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_wait_irq, ret);
++ return ret;
+ }
-+
-+ /* wait interrupt */
-+ ret = crypto_queue_wait_timeout(ctx->queue, &ctx->done, timeout);
-+ if ((ret <= 0) && (ret != -ERESTARTSYS)) {
-+ HI_LOG_ERROR("wait done timeout, chn=%d\n", chn_num);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_queue_wait_timeout, HI_ERR_CIPHER_TIMEOUT);
-+ drv_symc_get_err_code(chn_num);
-+ return HI_ERR_CIPHER_TIMEOUT;
-+ }
-+ } else /* interrupt unsupport, query the raw interrupt flag*/
-+#endif
-+ {
-+ for (i = 0; i < timeout; i++) {
-+ if (drv_symc_done_try(chn_num)) {
-+ break;
-+ }
-+ if (i <= MS_TO_US) {
-+ crypto_udelay(1); /* short waitting for 1000 us */
-+ } else {
-+ crypto_msleep(1); /* long waitting for 5000 ms*/
-+ }
-+ }
-+ if (timeout <= i) {
-+ HI_LOG_ERROR("symc wait done timeout, chn=%d\n", chn_num);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_queue_wait_timeout, HI_ERR_CIPHER_TIMEOUT);
-+ drv_symc_get_err_code(chn_num);
-+ return HI_ERR_CIPHER_TIMEOUT;
++ } else {
++ /* interrupt unsupport, query the raw interrupt flag. */
++ ret = drv_symc_query_raw_interrupt(chn_num, timeout);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_query_raw_interrupt, ret);
++ return ret;
+ }
+ }
-+
-+ HI_LOG_FUNC_EXIT();
-+
++#else
++ /* interrupt unsupport, query the raw interrupt flag. */
++ ret = drv_symc_query_raw_interrupt(chn_num, timeout);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_query_raw_interrupt, ret);
++ return ret;
++ }
++#endif
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -204684,26 +273788,28 @@ index 0000000..43453fe
+{
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ctx = crypto_channel_get_context(symc_hard_channel,
++ ctx = crypto_channel_get_context(g_symc_hard_channel,
+ CRYPTO_HARD_CHANNEL_MAX, chn_num);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("crypto channel get context failed,ctx is null!\n");
++ hi_log_error("crypto channel get context failed, ctx is null!\n");
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
+ ctx->destory = destory;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/******* proc function begin ********/
++/* ****** proc function begin ******* */
+#if (1 == HI_PROC_SUPPORT)
-+void drv_symc_proc_ctrl(symc_chn_status *status, chann_chipher_ctrl ctrl)
++static hi_void drv_symc_proc_alg(symc_chn_status *status, hi_u32 ctrl_info)
+{
-+ status->decrypt = ctrl.bits.decrypt;
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
+ switch (ctrl.bits.alg_sel) {
+ case HI_CIPHER_ALG_DES: {
+ status->alg = "DES ";
@@ -204722,42 +273828,46 @@ index 0000000..43453fe
+ break;
+ }
+ }
++}
+
++static hi_void drv_symc_proc_mode(symc_chn_status *status, hi_u32 ctrl_info)
++{
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
+ switch (ctrl.bits.mode) {
-+ case HI_CIPHER_WORK_MODE_ECB: {
++ case HI_CIPHER_WORK_MODE_ECB:
+ status->mode = "ECB ";
+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CBC: {
++ case HI_CIPHER_WORK_MODE_CBC:
+ status->mode = "CBC ";
+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CFB: {
++ case HI_CIPHER_WORK_MODE_CFB:
+ status->mode = "CFB ";
+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_OFB: {
++ case HI_CIPHER_WORK_MODE_OFB:
+ status->mode = "OFB ";
+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CTR: {
++ case HI_CIPHER_WORK_MODE_CTR:
+ status->mode = "CTR ";
+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CCM: {
++ case HI_CIPHER_WORK_MODE_CCM:
+ status->mode = "CCM ";
+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_GCM: {
++ case HI_CIPHER_WORK_MODE_GCM:
+ status->mode = "GCM ";
+ break;
-+ }
-+ default: {
++ default:
+ status->mode = "BUTT";
+ break;
-+ }
+ }
++}
+
++static hi_void drv_symc_proc_klen(symc_chn_status *status, hi_u32 ctrl_info)
++{
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
+ if (ctrl.bits.alg_sel == HI_CIPHER_ALG_AES) {
+ switch (ctrl.bits.key_length) {
+ case HI_CIPHER_KEY_AES_128BIT: {
@@ -204797,89 +273907,100 @@ index 0000000..43453fe
+ } else {
+ status->klen = 0;
+ }
++}
+
++static hi_void drv_symc_proc_key_src(symc_chn_status *status, hi_u32 ctrl_info)
++{
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
+ if (ctrl.bits.key_sel) {
+ status->ksrc = "HW";
+ } else {
+ status->ksrc = "SW";
+ }
++}
+
++hi_void drv_symc_proc_ctrl(symc_chn_status *status, chann_chipher_ctrl ctrl)
++{
++ status->decrypt = ctrl.bits.decrypt;
++ drv_symc_proc_alg(status, ctrl.u32);
++ drv_symc_proc_mode(status, ctrl.u32);
++ drv_symc_proc_klen(status, ctrl.u32);
++ drv_symc_proc_key_src(status, ctrl.u32);
+ return;
+}
+
+hi_s32 drv_symc_proc_status(symc_chn_status *status)
+{
-+ hi_u32 addr = 0;
++ hi_u32 addr, val, i, j;
+ chann_chipher_ctrl ctrl;
+ int_raw stIntRaw;
+ int_en stIntEn;
-+ hi_u32 val;
-+ hi_u32 i, j;
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ if (symc_hard_channel[i].open == HI_TRUE) {
++ if (g_symc_hard_channel[i].open == HI_TRUE) {
+ status[i].open = "open ";
+ } else {
+ status[i].open = "close";
+ }
+
-+ /* get cipher ctrl */
++ /* get cipher ctrl. */
+ if (i != 0) {
-+ addr = REG_CHANn_CIPHER_CTRL(i);
++ addr = reg_chann_cipher_ctrl(i);
+ } else {
+ addr = REG_CHAN0_CIPHER_CTRL;
+ }
-+ ctrl.u32 = SYMC_READ(addr);
++ ctrl.u32 = symc_read(addr);
+ drv_symc_proc_ctrl(&status[i], ctrl);
+
+ /* get data in */
+ if (i != 0) {
-+ addr = REG_CHANn_SRC_LST_SADDR(i);
-+ status[i].inaddr = SYMC_READ(addr);
++ addr = reg_chann_src_lst_saddr(i);
++ status[i].inaddr = symc_read(addr);
+ } else {
+ status[i].inaddr = REG_CHAN0_CIPHER_DIN;
+ }
+
+ /* get data out */
+ if (i != 0) {
-+ addr = REG_CHANn_DEST_LST_SADDR(i);
-+ status[i].outaddr = SYMC_READ(addr);
++ addr = reg_chann_dest_lst_saddr(i);
++ status[i].outaddr = symc_read(addr);
+ } else {
+ status[0].outaddr = REG_CHAN0_CIPHER_DOUT;
+ }
+
-+ for (j = 0; j < 4; j++) {
-+ val = SYMC_READ(REG_CHAN_CIPHER_IVOUT(i) + j * 4);
-+ hex2str(status[i].iv + j * 8, (hi_u8)(val & 0xFF));
-+ hex2str(status[i].iv + j * 8 + 2, (hi_u8)((val >> 8) & 0xFF));
-+ hex2str(status[i].iv + j * 8 + 4, (hi_u8)((val >> 16) & 0xFF));
-+ hex2str(status[i].iv + j * 8 + 6, (hi_u8)((val >> 24) & 0xFF));
++ for (j = 0; j < WORD_WIDTH; j++) {
++ val = symc_read(reg_chan_cipher_ivout(i) + j * WORD_WIDTH);
++ hex2str(status[i].iv + j * BYTE_BITS, 2, (hi_u8)(val & MAX_LOW_8BITS)); /* 2bytes */
++ hex2str(status[i].iv + j * BYTE_BITS + 2, 2, (hi_u8)((val >> SHIFT_8BITS) & MAX_LOW_8BITS)); /* 2, 2byte */
++ hex2str(status[i].iv + j * BYTE_BITS + 4, 2, (hi_u8)((val >> SHIFT_16BITS) & MAX_LOW_8BITS)); /* 4, 2byte */
++ hex2str(status[i].iv + j * BYTE_BITS + 6, 2, (hi_u8)((val >> SHIFT_24BITS) & MAX_LOW_8BITS)); /* 6, 2byte */
+ }
+
+ /* get INT RAW status */
-+ stIntRaw.u32 = SYMC_READ(REG_INT_RAW);
++ stIntRaw.u32 = symc_read(REG_INT_RAW);
+ status[i].inraw = (stIntRaw.bits.chn_ibuf_raw >> i) & 0x1;
+ status[i].outraw = (stIntRaw.bits.chn_obuf_raw >> i) & 0x1;
+
+ /* get INT EN status */
-+ stIntEn.u32 = SYMC_READ(REG_INT_EN);
++ stIntEn.u32 = symc_read(REG_INT_EN);
+ status[i].intswitch = stIntEn.bits.sec_int_en;
+ status[i].inten = (stIntEn.bits.chn_ibuf_en >> i) & 0x1;
+ status[i].outen = (stIntEn.bits.chn_obuf_en >> i) & 0x1;
+
+ /* get INT_OINTCFG */
-+ addr = REG_CHANn_INT_OCNTCFG(i);
-+ status[i].outintcnt = SYMC_READ(addr);
++ addr = reg_chann_int_ocntcfg(i);
++ status[i].outintcnt = symc_read(addr);
+ }
+
+ return HI_SUCCESS;
+}
-+#endif
-+/******* proc function end ********/
++#endif /* ****** proc function end ******* */
+
-+void drv_symc_get_capacity(symc_capacity *capacity)
++hi_void drv_symc_get_capacity(symc_capacity *capacity)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ crypto_memset(capacity, sizeof(symc_capacity), 0, sizeof(symc_capacity));
+
@@ -204903,36 +274024,21 @@ index 0000000..43453fe
+ capacity->des_ofb = CRYPTO_CAPACITY_SUPPORT;
+ capacity->des_cfb = CRYPTO_CAPACITY_SUPPORT;
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+
-+/** @}*/ /** <!-- ==== API Code end ====*/
-+
-+#endif //End of CHIP_SYMC_VER_V100
++#endif /* End of CHIP_SYMC_VER_V100 */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v100.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v100.h
new file mode 100644
-index 0000000..1e7eacc
+index 0000000..7203bd9
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v100.h
-@@ -0,0 +1,244 @@
+@@ -0,0 +1,226 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
++ * Description : head file of drv osal lib.
++ * Author : Hisilicon multimedia software group
++ * Create : 2018-10-23
+ */
+
+#ifndef _DRV_SYMC_V100_H_
@@ -204940,97 +274046,92 @@ index 0000000..1e7eacc
+
+#include "drv_osal_lib.h"
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
++/* Size of entry node */
++#define ENTRY_NODE_SIZE 16
+
-+/*! \Size of entry node */
-+#define ENTRY_NODE_SIZE (16)
++/* symmetric cipher max iv size */
++#define SYMC_IV_MAX_SIZE (SYMC_IV_MAX_SIZE_IN_WORD * 4)
+
-+/*! \symmetric cipher max iv size*/
-+#define SYMC_IV_MAX_SIZE (SYMC_IV_MAX_SIZE_IN_WORD * 4)
++/* Size of nodes list. */
++#define CHN_LIST_SIZE ((ENTRY_NODE_SIZE * 2 + SYMC_IV_MAX_SIZE) * SYMC_MAX_LIST_NUM)
+
-+/*! \Size of nodes list */
-+#define CHN_LIST_SIZE \
-+ ((ENTRY_NODE_SIZE *2 + SYMC_IV_MAX_SIZE) * SYMC_MAX_LIST_NUM)
++/* Size of symc nodes list. */
++#define SYMC_NODE_LIST_SIZE (CHN_LIST_SIZE * CIPHER_HARD_CHANNEL_CNT)
+
-+/*! \Size of symc nodes list */
-+#define SYMC_NODE_LIST_SIZE (CHN_LIST_SIZE * CIPHER_HARD_CHANNEL_CNT)
++/* Dump flag of node buffer, if set to 1, the SMMU will dump the page cache. */
++#define SYMC_BUF_LIST_FLAG_DUMM (0x01 << 20)
+
-+/*! \Dump flag of node buffer, if set to 1, the SMMU will dump the page cache*/
-+#define SYMC_BUF_LIST_FLAG_DUMM (0x01 << 20)
++/* IV set flag of node buffer, if set to 1, the IV will update to hardware. */
++#define SYMC_BUF_LIST_FLAG_IVSET (0x01 << 21)
+
-+/*! \IV set flag of node buffer, if set to 1, the IV will update to hardware*/
-+#define SYMC_BUF_LIST_FLAG_IVSET (0x01 << 21)
++/* EOL flag of node buffer, set to 1 at the last node. */
++#define SYMC_BUF_LIST_FLAG_EOL (0x01 << 22)
+
-+/*! \EOL flag of node buffer, set to 1 at the last node*/
-+#define SYMC_BUF_LIST_FLAG_EOL (0x01 << 22)
++/* Define the offset of reg. */
++#define REG_CHAN0_CIPHER_DOUT 0x0000
++#define reg_chan_cipher_ivout(id) (0x0010 + (id) * 16)
++#define reg_cipher_key(id) (0x0090 + (id) * 32)
++#define REG_SEC_CHN_CFG 0x0824
++#define REG_HL_APP_LEN 0x082C
++#define REG_CHAN0_CIPHER_CTRL 0x1000
++#define REG_CHAN0_CIPHER_DIN 0x1014
++#define reg_chann_ibuf_num(id) (0x1000 + (id) * 128)
++#define reg_chann_ibuf_cnt(id) (0x1000 + (id) * 128 + 0x4)
++#define reg_chann_iempty_cnt(id) (0x1000 + (id) * 128 + 0x8)
++#define reg_chann_cipher_ctrl(id) (0x1000 + (id) * 128 + 0x10)
++#define reg_chann_src_lst_saddr(id) (0x1000 + (id) * 128 + 0x14)
++#define reg_chann_iage_cnt(id) (0x1000 + (id) * 128 + 0x1C)
++#define reg_chann_src_lst_raddr(id) (0x1000 + (id) * 128 + 0x20)
++#define chnn_src_addr(id) (0x1000 + (id) * 128 + 0x24)
++#define reg_chann_obuf_num(id) (0x1000 + (id) * 128 + 0x3C)
++#define reg_chann_obuf_cnt(id) (0x1000 + (id) * 128 + 0x40)
++#define reg_chann_ofull_cnt(id) (0x1000 + (id) * 128 + 0x44)
++#define reg_chann_int_ocntcfg(id) (0x1000 + (id) * 128 + 0x48)
++#define reg_chann_dest_lst_saddr(id) (0x1000 + (id) * 128 + 0x4C)
++#define reg_chann_oage_cnt(id) (0x1000 + (id) * 128 + 0x54)
++#define reg_chann_dest_lst_raddr(id) (0x1000 + (id) * 128 + 0x58)
++#define reg_chann_dest_addr(id) (0x1000 + (id) * 128 + 0x5C)
++#define REG_INT_STATUS 0x1400
++#define REG_INT_EN 0x1404
++#define REG_INT_RAW 0x1408
++#define CHANn_RD_DAT_ADDR_SMMU_BYPASS 0x1418
++#define CHANn_WR_DAT_ADDR_SMMU_BYPASS 0x141C
+
-+/*! \Define the offset of reg */
-+#define REG_CHAN0_CIPHER_DOUT (0x0000)
-+#define REG_CHAN_CIPHER_IVOUT(id) (0x0010 + (id)*16)
-+#define REG_CIPHER_KEY(id) (0x0090 + (id)*32)
-+#define REG_SEC_CHN_CFG (0x0824)
-+#define REG_HL_APP_LEN (0x082C)
-+#define REG_CHAN0_CIPHER_CTRL (0x1000)
-+#define REG_CHAN0_CIPHER_DIN (0x1014)
-+#define REG_CHANn_IBUF_NUM(id) (0x1000 + (id)*128)
-+#define REG_CHANn_IBUF_CNT(id) (0x1000 + (id)*128 + 0x4)
-+#define REG_CHANn_IEMPTY_CNT(id) (0x1000 + (id)*128 + 0x8)
-+#define REG_CHANn_CIPHER_CTRL(id) (0x1000 + (id)*128 + 0x10)
-+#define REG_CHANn_SRC_LST_SADDR(id) (0x1000 + (id)*128 + 0x14)
-+#define REG_CHANn_IAGE_CNT(id) (0x1000 + (id)*128 + 0x1C)
-+#define REG_CHANn_SRC_LST_RADDR(id) (0x1000 + (id)*128 + 0x20)
-+#define CHANn_SRC_ADDR(id) (0x1000 + (id)*128 + 0x24)
-+#define REG_CHANn_OBUF_NUM(id) (0x1000 + (id)*128 + 0x3C)
-+#define REG_CHANn_OBUF_CNT(id) (0x1000 + (id)*128 + 0x40)
-+#define REG_CHANn_OFULL_CNT(id) (0x1000 + (id)*128 + 0x44)
-+#define REG_CHANn_INT_OCNTCFG(id) (0x1000 + (id)*128 + 0x48)
-+#define REG_CHANn_DEST_LST_SADDR(id) (0x1000 + (id)*128 + 0x4C)
-+#define REG_CHANn_OAGE_CNT(id) (0x1000 + (id)*128 + 0x54)
-+#define REG_CHANn_DEST_LST_RADDR(id) (0x1000 + (id)*128 + 0x58)
-+#define REG_CHANn_DEST_ADDR(id) (0x1000 + (id)*128 + 0x5C)
-+#define REG_INT_STATUS (0x1400)
-+#define REG_INT_EN (0x1404)
-+#define REG_INT_RAW (0x1408)
-+#define CHANn_RD_DAT_ADDR_SMMU_BYPASS (0x1418)
-+#define CHANn_WR_DAT_ADDR_SMMU_BYPASS (0x141C)
-+
-+#define REG_MMU_GLOBAL_CTR_ADDR (0x00)
-+#define REG_MMU_INTMAS_S (0x10)
-+#define REG_MMU_INTRAW_S (0x14)
-+#define REG_MMU_INTSTAT_S (0x18)
-+#define REG_MMU_INTCLR_S (0x1c)
-+#define REG_MMU_INTMASK_NS (0x20)
-+#define REG_MMU_INTRAW_NS (0x24)
-+#define REG_MMU_INTSTAT_NS (0x28)
-+#define REG_MMU_INTCLR_NS (0x2C)
++#define REG_MMU_GLOBAL_CTR_ADDR 0x00
++#define REG_MMU_INTMAS_S 0x10
++#define REG_MMU_INTRAW_S 0x14
++#define REG_MMU_INTSTAT_S 0x18
++#define REG_MMU_INTCLR_S 0x1c
++#define REG_MMU_INTMASK_NS 0x20
++#define REG_MMU_INTRAW_NS 0x24
++#define REG_MMU_INTSTAT_NS 0x28
++#define REG_MMU_INTCLR_NS 0x2C
+
+#ifdef CHIP_SMMU_VER_V200
-+#define REG_MMU_SCB_TTBR_H (0x2e0)
-+#define REG_MMU_SCB_TTBR (0x2e4)
-+#define REG_MMU_CB_TTBR_H (0x2e8)
-+#define REG_MMU_CB_TTBR (0x2ec)
-+#define REG_MMU_ERR_RDADDR_H_S (0x2f0)
-+#define REG_MMU_ERR_RDADDR_S (0x2f4)
-+#define REG_MMU_ERR_WRADDR_H_S (0x2f8)
-+#define REG_MMU_ERR_WRADDR_S (0x2fc)
-+#define REG_MMU_ERR_RDADDR_H_NS (0x300)
-+#define REG_MMU_ERR_RDADDR_NS (0x304)
-+#define REG_MMU_ERR_WRADDR_H_NS (0x308)
-+#define REG_MMU_ERR_WRADDR_NS (0x30c)
++#define REG_MMU_SCB_TTBR_H 0x2e0
++#define REG_MMU_SCB_TTBR 0x2e4
++#define REG_MMU_CB_TTBR_H 0x2e8
++#define REG_MMU_CB_TTBR 0x2ec
++#define REG_MMU_ERR_RDADDR_H_S 0x2f0
++#define REG_MMU_ERR_RDADDR_S 0x2f4
++#define REG_MMU_ERR_WRADDR_H_S 0x2f8
++#define REG_MMU_ERR_WRADDR_S 0x2fc
++#define REG_MMU_ERR_RDADDR_H_NS 0x300
++#define REG_MMU_ERR_RDADDR_NS 0x304
++#define REG_MMU_ERR_WRADDR_H_NS 0x308
++#define REG_MMU_ERR_WRADDR_NS 0x30c
+#else
-+#define REG_MMU_SCB_TTBR (0x208)
-+#define REG_MMU_CB_TTBR (0x20C)
-+#define REG_MMU_ERR_RDADDR_S (0x2f0)
-+#define REG_MMU_ERR_WRADDR_S (0x2f4)
-+#define REG_MMU_ERR_RDADDR_NS (0x304)
-+#define REG_MMU_ERR_WRADDR_NS (0x308)
++#define REG_MMU_SCB_TTBR 0x208
++#define REG_MMU_CB_TTBR 0x20C
++#define REG_MMU_ERR_RDADDR_S 0x2f0
++#define REG_MMU_ERR_WRADDR_S 0x2f4
++#define REG_MMU_ERR_RDADDR_NS 0x304
++#define REG_MMU_ERR_WRADDR_NS 0x308
+#endif
+
-+/*! \Define the union chann_chipher_ctrl */
++/* Define the union chann_chipher_ctrl */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 decrypt : 1 ; /* [0] */
+ hi_u32 mode : 3 ; /* [3..1] */
@@ -205045,49 +274146,49 @@ index 0000000..1e7eacc
+ hi_u32 weight : 10 ; /* [31..22] */
+ } bits;
+
-+ hi_u32 u32; /*! \Define an unsigned member */
++ hi_u32 u32; /* Define an unsigned member */
+} chann_chipher_ctrl;
+
-+/*! \Define the union sec_chn_cfg */
++/* Define the union sec_chn_cfg */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 sec_chn_cfg : 8 ; /* [7..0] */
+ hi_u32 sec_chn_cfg_lock : 1 ; /* [8] */
+ hi_u32 reserved_1 : 23 ; /* [31..9] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} sec_chn_cfg;
+
-+/*! \Define the union chann_rd_dat_addr_smmu_bypass */
++/* Define the union chann_rd_dat_addr_smmu_bypass */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 chann_rd_dat_addr_smmu_bypass : 7 ; /* [6..0] */
+ hi_u32 reserved_1 : 25 ; /* [31..7] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} chann_rd_dat_addr_smmu_bypass;
+
-+/*! \Define the union chann_wr_dat_addr_smmu_bypass */
++/* Define the union chann_wr_dat_addr_smmu_bypass */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 chann_wr_dat_addr_smmu_bypass : 7 ; /* [6..0] */
+ hi_u32 reserved_1 : 25 ; /* [31..7] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} chann_wr_dat_addr_smmu_bypass;
+
-+/*! \Define the union int_status */
++/* Define the union int_status */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 chn_ibuf_int : 8 ; /* [7..0] */
+ hi_u32 chn_obuf_int : 8 ; /* [15..8] */
@@ -205095,13 +274196,13 @@ index 0000000..1e7eacc
+ hi_u32 reserved_1 : 15; /* [31..17] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} int_status;
+
-+/*! \Define the union int_en */
++/* Define the union int_en */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 chn_ibuf_en : 8 ; /* [7..0] */
+ hi_u32 chn_obuf_en : 8 ; /* [15..8] */
@@ -205111,13 +274212,13 @@ index 0000000..1e7eacc
+ hi_u32 int_en : 1 ; /* [31] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} int_en;
+
-+/*! \Define the union int_raw */
++/* Define the union int_raw */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 chn_ibuf_raw : 8 ; /* [7..0] */
+ hi_u32 chn_obuf_raw : 8 ; /* [15..8] */
@@ -205125,64 +274226,51 @@ index 0000000..1e7eacc
+ hi_u32 reserved_1 : 15; /* [31..17] */
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} int_raw;
+
-+/*! \Define the union smmu_scr */
++/* Define the union smmu_scr */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 glb_bypass : 1 ; /* [0] */
+ hi_u32 reserved_1 : 2; /* [2..1] */
+ hi_u32 int_en : 1 ; /* [3] */
+ hi_u32 reserved_2 : 28; /* [31..4] */
-+
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} smmu_scr;
+
-+/*! \Define the union smmu_int */
++/* Define the union smmu_int */
+typedef union {
-+ /*! \Define the struct bits */
++ /* Define the struct bits */
+ struct {
+ hi_u32 ints_tlbmiss : 1 ; /* [0] */
+ hi_u32 ints_ptw_trans : 1; /* [1] */
+ hi_u32 ints_tlbinvalid : 1 ; /* [2] */
+ hi_u32 reserved_2 : 29; /* [31..3] */
-+
+ } bits;
+
-+ /*! \Define an unsigned member */
++ /* Define an unsigned member */
+ hi_u32 u32;
+} smmu_int;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++/* Structure Definition end */
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v200.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v200.c
new file mode 100644
-index 0000000..d3bd694
+index 0000000..fa3d99e
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v200.c
-@@ -0,0 +1,2010 @@
+@@ -0,0 +1,1952 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv symc v200.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_symc_v200.h"
@@ -205190,181 +274278,168 @@ index 0000000..d3bd694
+
+#ifdef CHIP_SYMC_VER_V200
+
-+#define KLAD_KEY_USE_ERR 0x01
-+#define ALG_LEN_ERR 0x02
-+#define SMMU_PAGE_UNVLID 0x04
-+#define OUT_SMMU_PAGE_NOT_VALID 0x08
-+#define KLAD_KEY_WRITE_ERR 0x10
++#define KLAD_KEY_USE_ERR 0x01
++#define ALG_LEN_ERR 0x02
++#define SMMU_PAGE_UNVLID 0x04
++#define OUT_SMMU_PAGE_NOT_VALID 0x08
++#define KLAD_KEY_WRITE_ERR 0x10
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
++/* Length of pading buffer */
++#define SYMC_PAD_BUFFER_LEN 128
+
-+/*! \Length of pading buffer */
-+#define SYMC_PAD_BUFFER_LEN (128)
++/* Length of aes ccm/gcm key */
++#define AES_CCM_GCM_KEY_LEN 16
+
-+/*! \Length of aes ccm/gcm key */
-+#define AES_CCM_GCM_KEY_LEN (16)
-+
-+/*! \Total Length of pading buffer */
++/* Total Length of pading buffer */
+#define SYMC_PAD_BUFFER_TOTAL_LEN (SYMC_PAD_BUFFER_LEN * CIPHER_HARD_CHANNEL_CNT)
+
-+/*! spacc symc int entry struct which is defined by hardware, you can't change it */
++/* spacc symc int entry struct which is defined by hardware, you can't change it */
+typedef struct {
-+ hi_u32 spacc_cmd: 2; /*!< reserve */
-+ hi_u32 rev1: 6; /*!< reserve */
-+ hi_u32 sym_ctrl: 7; /*!< symc control flag*/
-+ hi_u32 rev2: 1; /*!< reserve */
-+ hi_u32 gcm_iv_len: 4; /*!< gcm iv length */
-+ hi_u32 rev3: 12; /*!< reserve */
-+ hi_u32 sym_start_high; /*!< syma start high addr */
-+ hi_u32 sym_start_addr; /*!< syma start low addr */
-+ hi_u32 sym_alg_length; /*!< syma data length */
-+ hi_u32 iv[4]; /*!< symc IV */
++ hi_u32 spacc_cmd: 2; /* reserve */
++ hi_u32 rev1: 6; /* reserve */
++ hi_u32 sym_ctrl: 7; /* symc control flag. */
++ hi_u32 rev2: 1; /* reserve */
++ hi_u32 gcm_iv_len: 4; /* gcm iv length */
++ hi_u32 rev3: 12; /* reserve */
++ hi_u32 sym_start_high; /* syma start high addr */
++ hi_u32 sym_start_addr; /* syma start low addr */
++ hi_u32 sym_alg_length; /* syma data length */
++ hi_u32 iv[AES_IV_SIZE / WORD_WIDTH]; /* symc IV */
+} symc_entry_in;
+
-+/*! spacc symc out entry struct which is defined by hardware, you can't change it */
++/* spacc symc out entry struct which is defined by hardware, you can't change it */
+typedef struct {
-+ hi_u32 rev1: 8; /*!< reserve */
-+ hi_u32 aes_ctrl: 4; /*!< aes contrl */
-+ hi_u32 rev2: 20; /*!< reserve */
-+ hi_u32 sym_start_addr; /*!< syma start high addr */
-+ hi_u32 sym_alg_length; /*!< syma data length */
-+ hi_u32 hash_rslt_start_addr; /*!< syma data length */
-+ hi_u32 tag[AEAD_TAG_SIZE_IN_WORD]; /*!< CCM/GCM tag */
++ hi_u32 rev1: 8; /* reserve */
++ hi_u32 aes_ctrl: 4; /* aes contrl */
++ hi_u32 rev2: 20; /* reserve */
++ hi_u32 sym_start_addr; /* syma start high addr */
++ hi_u32 sym_alg_length; /* syma data length */
++ hi_u32 hash_rslt_start_addr; /* syma data length */
++ hi_u32 tag[AEAD_TAG_SIZE_IN_WORD]; /* CCM/GCM tag */
+} symc_entry_out;
+
-+/*! Define the context of cipher */
++/* Define the context of cipher */
+typedef struct {
-+ hi_u32 open; /*!< open or close */
-+ symc_entry_in *entry_in; /*!< in node list */
-+ symc_entry_out *entry_out; /*!< out node list */
-+ compat_addr dma_entry; /*!< dma addr of node */
-+ compat_addr dma_pad; /*!< dma addr of padding buffer, for CCM/GCM */
-+ hi_u8 *via_pad; /*!< via addr of padding buffer, for CCM/GCM */
-+ hi_u32 offset_pad; /*!< offset of padding buffer, for CCM/GCM */
-+ hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD];/*!< iv data from user*/
++ hi_u32 open; /* open or close */
++ symc_entry_in *entry_in; /* in node list */
++ symc_entry_out *entry_out; /* out node list */
++ compat_addr dma_entry; /* dma addr of node */
++ compat_addr dma_pad; /* dma addr of padding buffer, for CCM/GCM */
++ hi_u8 *via_pad; /* via addr of padding buffer, for CCM/GCM */
++ hi_u32 offset_pad; /* offset of padding buffer, for CCM/GCM */
++ hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD]; /* iv data from user. */
+
-+ /* iv usage flag, should be CIPHER_IV_CHANGE_ONE_PKG
-+ * or CIPHER_IV_CHANGE_ALL_PKG.
++ /* iv usage flag, should be HI_CIPHER_IV_CHG_ONE_PACK
++ * or HI_CIPHER_IV_CHG_ALL_PACK.
+ */
-+ hi_u32 iv_flag; /*!< iv flag */
-+ hi_u32 iv_len; /*!< iv length */
-+ symc_alg alg; /*!< The alg of Symmetric cipher */
-+ symc_mode mode; /*!< mode */
-+ hi_u32 id_in; /*!< current in nodes index */
-+ hi_u32 id_out; /*!< current out nodes index */
-+ hi_u32 cnt_in; /*!< total count in nodes to be computed */
-+ hi_u32 cnt_out; /*!< total count out nodes to be computed */
-+ hi_u32 done; /*!< calculation finish flag*/
-+ crypto_queue_head queue; /*!< quene list */
-+ callback_symc_isr callback; /*!< isr callback functon */
-+ callback_symc_destory destory; /*!< destory callback functon */
-+ void *ctx; /*!< params for isr callback functon */
++ hi_u32 iv_flag; /* iv flag */
++ hi_u32 iv_len; /* iv length */
++ symc_alg alg; /* The alg of Symmetric cipher */
++ symc_mode mode; /* mode */
++ hi_u32 id_in; /* current in nodes index */
++ hi_u32 id_out; /* current out nodes index */
++ hi_u32 cnt_in; /* total count in nodes to be computed */
++ hi_u32 cnt_out; /* total count out nodes to be computed */
++ hi_u32 done; /* calculation finish flag. */
++ crypto_queue_head queue; /* quene list */
++ callback_symc_isr callback; /* isr callback functon */
++ callback_symc_destory destory; /* destory callback functon */
++ hi_void *ctx; /* params for isr callback functon */
+} symc_hard_context;
+
-+/*! spacc symc_chn_who_used struct which is defined by hardware, you can't change it */
++/* spacc symc_chn_who_used struct which is defined by hardware, you can't change it */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ unsigned int non_sec_chn_who_used : 16 ; /* [15..0] */
-+ unsigned int sec_chn1_who_used : 2 ; /* [17..16] */
-+ unsigned int reserved : 22 ; /* [31..18] */
++ hi_u32 non_sec_chn_who_used : 16 ; /* [15..0] */
++ hi_u32 sec_chn1_who_used : 2 ; /* [17..16] */
++ hi_u32 reserved : 22 ; /* [31..18] */
+ } bits;
+
+ /* Define an unsigned member */
-+ unsigned int u32;
++ hi_u32 u32;
+} symc_chn_who_used;
+
-+/*! Channel of cipher */
-+static symc_hard_context hard_context[CRYPTO_HARD_CHANNEL_MAX];
++/* Channel of cipher */
++static symc_hard_context g_hard_context[CRYPTO_HARD_CHANNEL_MAX];
+
-+/*! dma memory of cipher node list*/
-+static crypto_mem symc_dma;
++/* dma memory of cipher node list. */
++static crypto_mem g_symc_dma;
+
-+/*! symc already initialize or not */
-+static hi_u32 symc_initialize = HI_FALSE;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+#ifndef HI_ADVCA_FUNCTION_RELEASE
-+extern int dump_mem(void);
-+#endif
++/* symc already initialize or not */
++static hi_u32 g_symc_initialize = HI_FALSE;
+
++/* ****************************** API Code **************************** */
+static hi_u32 drv_symc_done_try(hi_u32 chn_num)
+{
+ cipher_int_raw status;
+
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ status.u32 = SYMC_READ(CIPHER_INT_RAW);
++ status.u32 = symc_read(CIPHER_INT_RAW);
+ status.bits.cipher_chn_obuf_raw &= 0x01 << chn_num; /* check interception */
+
-+ /*clear interception*/
-+ SYMC_WRITE(CIPHER_INT_RAW, status.u32);
++ /* clear interception. */
++ symc_write(CIPHER_INT_RAW, status.u32);
+
+ return (hi_u32)(status.bits.cipher_chn_obuf_raw ? HI_TRUE : HI_FALSE);
+}
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+static hi_u32 drv_symc_done_notify(void)
++static hi_u32 drv_symc_done_notify(hi_void)
+{
+ cipher_int_status status;
+ cipher_int_raw raw;
+
-+ status.u32 = SYMC_READ(CIPHER_INT_STATUS);
++ status.u32 = symc_read(CIPHER_INT_STATUS);
+ raw.u32 = 0;
+
-+ /*just process the valid channel*/
++ /* just process the valid channel. */
+ status.bits.cipher_chn_obuf_int &= CIPHER_HARD_CHANNEL_MASK;
+ raw.bits.cipher_chn_obuf_raw = status.bits.cipher_chn_obuf_int;
+
-+ /*clear interception*/
-+ SYMC_WRITE(CIPHER_INT_RAW, raw.u32);
++ /* clear interception. */
++ symc_write(CIPHER_INT_RAW, raw.u32);
+
+ return status.bits.cipher_chn_obuf_int; /* mask */
+}
+
-+static hi_u32 drv_hash_done_test(void)
++static hi_u32 drv_hash_done_test(hi_void)
+{
+ hash_int_status int_st;
-+ hi_u32 chn_mask = 0;
++ hi_u32 chn_mask;
+
-+ int_st.u32 = SYMC_READ(HASH_INT_STATUS);
++ int_st.u32 = symc_read(HASH_INT_STATUS);
+
-+ /*just process the valid channel*/
++ /* just process the valid channel. */
+ int_st.bits.hash_chn_oram_int &= HASH_HARD_CHANNEL_MASK;
+ chn_mask = int_st.bits.hash_chn_oram_int;
+
+ return chn_mask;
+}
+
-+/*! symc interrupt process function */
-+static irqreturn_t drv_symc_interrupt_isr(hi_s32 irq, void *devId)
++/* symc interrupt process function */
++static irqreturn_t drv_symc_interrupt_isr(hi_s32 irq, hi_void *dev_id)
+{
+ hi_u32 mask, i;
+ symc_hard_context *ctx = HI_NULL;
+ irqreturn_t ret = IRQ_HANDLED;
+
-+ /* get channel context*/
++ /* get channel context. */
+ mask = drv_symc_done_notify();
-+ HI_LOG_DEBUG("symc irq: %d, mask 0x%x\n", irq, mask);
++ hi_log_debug("symc irq: %d, mask 0x%x\n", irq, mask);
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
+ if ((mask >> i) & 0x01) {
-+ ctx = &hard_context[i];
++ ctx = &g_hard_context[i];
+ if ((ctx->callback) && (ctx->callback(ctx->ctx) == HI_FALSE)) {
+ /* contiue to compute */
-+ HI_LOG_DEBUG("contiue to compute chn %d\n", i);
++ hi_log_debug("contiue to compute chn %d\n", i);
+ drv_symc_start(i);
+ } else {
+ /* finish */
+ ctx->done = HI_TRUE;
-+ HI_LOG_DEBUG("chn %d wake up\n", i);
++ hi_log_debug("chn %d wake up\n", i);
+ crypto_queue_wait_up(&ctx->queue);
+ }
+ }
@@ -205381,15 +274456,16 @@ index 0000000..d3bd694
+ return ret;
+}
+
-+/*! symc register interrupt process function */
-+static hi_s32 drv_symc_register_interrupt(void)
++/* symc register interrupt process function */
++static hi_s32 drv_symc_register_interrupt(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_s32 ret;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ hi_u32 i;
-+ const char *name;
++ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, &name);
+
@@ -205398,30 +274474,31 @@ index 0000000..d3bd694
+ }
+
+ /* request irq */
-+ HI_LOG_DEBUG("symc request irq, num %d, name %s\n", int_num, name);
++ hi_log_debug("symc request irq, num %u, name %s\n", int_num, name);
+ ret = crypto_request_irq(int_num, drv_symc_interrupt_isr, name);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Irq request failure, irq = %d\n", int_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_REGISTER_IRQ);
++ hi_log_error("Irq request failure, irq = %u\n", int_num);
++ hi_log_print_err_code(HI_ERR_CIPHER_REGISTER_IRQ);
+ return ret;
+ }
+
-+ /* initialize queue list*/
++ /* initialize queue list. */
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ crypto_queue_init(&hard_context[i].queue);
++ crypto_queue_init(&g_hard_context[i].queue);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/*! symc unregister interrupt process function */
-+static void drv_symc_unregister_interrupt(void)
++/* symc unregister interrupt process function */
++static hi_void drv_symc_unregister_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
-+ const char *name;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
++ const char *name = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, &name);
+
@@ -205430,28 +274507,27 @@ index 0000000..d3bd694
+ }
+
+ /* free irq */
-+ HI_LOG_DEBUG("symc free irq, num %d, name %s\n", int_num, name);
++ hi_log_debug("symc free irq, num %d, name %s\n", int_num, name);
+ crypto_free_irq(int_num, name);
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return;
++ hi_log_func_exit();
+}
+
-+/*! set interrupt */
-+static void drv_symc_set_interrupt(void)
++/* set interrupt */
++static hi_void drv_symc_set_interrupt(hi_void)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ cipher_int_en cipher_int_en;
-+ cipher_int_raw raw;
++ cipher_int_raw raw;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, HI_NULL);
+
+ if (int_valid) {
+ /* Enable interrupt */
-+ cipher_int_en.u32 = SYMC_READ(CIPHER_INT_EN);
++ cipher_int_en.u32 = symc_read(CIPHER_INT_EN);
+
+ if (crypto_is_sec_cpu()) {
+ cipher_int_en.bits.cipher_sec_int_en = 1;
@@ -205460,19 +274536,19 @@ index 0000000..d3bd694
+ }
+ cipher_int_en.bits.cipher_chn_obuf_en |= CIPHER_HARD_CHANNEL_MASK;
+
-+ SYMC_WRITE(CIPHER_INT_EN, cipher_int_en.u32);
-+ HI_LOG_INFO("CIPHER_INT_EN: 0x%x\n", cipher_int_en.u32);
++ symc_write(CIPHER_INT_EN, cipher_int_en.u32);
++ hi_log_info("CIPHER_INT_EN: 0x%x\n", cipher_int_en.u32);
+ } else {
+ /* Disable interrupt */
-+ cipher_int_en.u32 = SYMC_READ(CIPHER_INT_EN);
++ cipher_int_en.u32 = symc_read(CIPHER_INT_EN);
+
+ if (crypto_is_sec_cpu()) {
+ cipher_int_en.bits.cipher_sec_int_en = 0;
+ } else {
+ cipher_int_en.bits.cipher_nsec_int_en = 0;
+ }
-+ SYMC_WRITE(CIPHER_INT_EN, cipher_int_en.u32);
-+ HI_LOG_INFO("CIPHER_INT_EN: 0x%x\n", cipher_int_en.u32);
++ symc_write(CIPHER_INT_EN, cipher_int_en.u32);
++ hi_log_info("CIPHER_INT_EN: 0x%x\n", cipher_int_en.u32);
+ }
+
+ /* clear interception
@@ -205480,136 +274556,157 @@ index 0000000..d3bd694
+ * call the irq function before initialization
+ * when register interrupt, this will cause a system abort.
+ */
-+ raw.u32 = SYMC_READ(CIPHER_INT_RAW);
++ raw.u32 = symc_read(CIPHER_INT_RAW);
+ raw.bits.cipher_chn_obuf_raw &= CIPHER_HARD_CHANNEL_MASK; /* clear valid channel */
-+ SYMC_WRITE(CIPHER_INT_RAW, raw.u32);
++ symc_write(CIPHER_INT_RAW, raw.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
++static hi_s32 drv_symc_wait_irq(hi_u32 chn_num, symc_hard_context *ctx, hi_u32 timeout)
++{
++ hi_s32 ret;
++
++ /* wait interrupt */
++ ret = crypto_queue_wait_timeout(ctx->queue, &ctx->done, timeout);
++
++ /* Disable SM4 independent from spacc */
++ if (ctx->alg == SYMC_ALG_SM4) {
++ module_disable(CRYPTO_MODULE_ID_SM4);
++ }
++
++ if ((ret <= 0x00) && (ret != -ERESTARTSYS)) {
++ hi_log_error("wait done timeout, chn=%d\n", chn_num);
++ hi_log_print_func_err(crypto_queue_wait_timeout, ret);
++ drv_symc_get_err_code(chn_num);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
++
++ return HI_SUCCESS;
++}
++
+#endif
+
-+/*! set reduceing power disspation */
-+static void drv_symc_core_auto_cken_bypass(void)
++/* set reduceing power disspation */
++static hi_void drv_symc_core_auto_cken_bypass(hi_void)
+{
+#ifdef CRYPTO_CORE_AUTO_CKEN_SUPPORT
+ cal_crg_cfg core_auto_cken_bypass;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ core_auto_cken_bypass.u32 = SYMC_READ(SPACC_CALC_CRG_CFG);
++ core_auto_cken_bypass.u32 = symc_read(SPACC_CALC_CRG_CFG);
+
+ core_auto_cken_bypass.bits.spacc_core_auto_cken_bypass = 0x0;
+ core_auto_cken_bypass.bits.spacc_rft_mem_wr_clk_gt_en = 0x1;
+ core_auto_cken_bypass.bits.spacc_rft_mem_rd_clk_gt_en = 0x1;
+ core_auto_cken_bypass.bits.spacc_rfs_mem_clk_gt_en = 0x1;
+
-+ SYMC_WRITE(SPACC_CALC_CRG_CFG, core_auto_cken_bypass.u32);
++ symc_write(SPACC_CALC_CRG_CFG, core_auto_cken_bypass.u32);
+
-+ HI_LOG_INFO("SPACC_CALC_CRG_CFG[0x%x]: 0x%x\n", SPACC_CALC_CRG_CFG, core_auto_cken_bypass.u32);
++ hi_log_info("SPACC_CALC_CRG_CFG[0x%x]: 0x%x\n", SPACC_CALC_CRG_CFG, core_auto_cken_bypass.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+#endif
+}
+
-+/*! set symc entry */
++/* set symc entry */
+static hi_s32 drv_symc_recover_entry(hi_u32 chn)
+{
+ chann_cipher_in_node_cfg cipher_in_cfg;
+ chann_cipher_out_node_cfg cipher_out_cfg;
-+ symc_hard_context *ctx = &hard_context[chn];
++ symc_hard_context *ctx = &g_hard_context[chn];
+ compat_addr out_addr;
-+ hi_u32 entry = 0;
++ hi_u32 entry;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* set total num and start addr for cipher in node
+ * On ree, the chn may be seized by tee,
+ * so we must check it, that is check we can write the reg of chn or not.
+ */
-+ SYMC_WRITE(CHANn_CIPHER_IN_NODE_START_ADDR(chn), ADDR_L32(ctx->dma_entry));
-+ SYMC_WRITE(CHANN_CIPHER_IN_NODE_START_HIGH(chn), ADDR_H32(ctx->dma_entry));
-+ entry = SYMC_READ(CHANn_CIPHER_IN_NODE_START_ADDR(chn));
-+ if (entry != ADDR_L32(ctx->dma_entry)) {
-+ HI_LOG_INFO("the ree chn be seized by tee\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_UNAVAILABLE);
++ symc_write(chann_cipher_in_node_start_addr(chn), addr_l32(ctx->dma_entry));
++ symc_write(chann_cipher_in_node_start_high(chn), addr_h32(ctx->dma_entry));
++ entry = symc_read(chann_cipher_in_node_start_addr(chn));
++ if (entry != addr_l32(ctx->dma_entry)) {
++ hi_log_info("the ree chn be seized by tee\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_UNAVAILABLE);
+ return HI_ERR_CIPHER_UNAVAILABLE;
+ }
-+ cipher_in_cfg.u32 = SYMC_READ(CHANn_CIPHER_IN_NODE_CFG(chn));
++ cipher_in_cfg.u32 = symc_read(chann_cipher_in_node_cfg(chn));
+ ctx->id_in = cipher_in_cfg.bits.cipher_in_node_wptr;
-+ HI_LOG_INFO("symc chn %d recover, id in 0x%x, IN_NODE_START_ADDR 0x%x, VIA %p\n",
-+ chn, ctx->id_in, ADDR_L32(ctx->dma_entry), ctx->entry_in);
++ hi_log_info("symc chn %d recover, id in 0x%x, IN_NODE_START_ADDR 0x%x, VIA %p\n",
++ chn, ctx->id_in, addr_l32(ctx->dma_entry), ctx->entry_in);
+
-+ /*set total num and start addr for cipher out node*/
-+ cipher_out_cfg.u32 = SYMC_READ(CHANn_CIPHER_OUT_NODE_CFG(chn));
-+ ADDR_U64(out_addr) = ADDR_U64(ctx->dma_entry) + SYMC_NODE_SIZE;
-+ SYMC_WRITE(CHANn_CIPHER_OUT_NODE_START_ADDR(chn), ADDR_L32(out_addr));
-+ SYMC_WRITE(CHANN_CIPHER_OUT_NODE_START_HIGH(chn), ADDR_H32(out_addr));
++ /* set total num and start addr for cipher out node. */
++ cipher_out_cfg.u32 = symc_read(chann_cipher_out_node_cfg(chn));
++ addr_u64(out_addr) = addr_u64(ctx->dma_entry) + SYMC_NODE_SIZE;
++ symc_write(chann_cipher_out_node_start_addr(chn), addr_l32(out_addr));
++ symc_write(chann_cipher_out_node_start_high(chn), addr_h32(out_addr));
+ ctx->id_out = cipher_out_cfg.bits.cipher_out_node_wptr;
-+ HI_LOG_INFO("symc chn %d recover, id out 0x%x, OUT_NODE_START_ADDR 0x%x, VIA %p\n",
-+ chn, ctx->id_out, ADDR_L32(ctx->dma_entry) + SYMC_NODE_SIZE,
-+ ctx->entry_out);
++ hi_log_info("symc chn %d recover, id out 0x%x, OUT_NODE_START_ADDR 0x%x, VIA %p\n",
++ chn, ctx->id_out, addr_l32(ctx->dma_entry) + SYMC_NODE_SIZE, ctx->entry_out);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/*! set symc entry */
-+static void drv_symc_set_entry(hi_u32 chn, compat_addr dma_addr, void *cpu_addr)
++/* set symc entry */
++static hi_void drv_symc_set_entry(hi_u32 chn, compat_addr dma_addr, hi_void *cpu_addr)
+{
+ chann_cipher_in_node_cfg cipher_in_cfg;
+ chann_cipher_out_node_cfg cipher_out_cfg;
-+ symc_hard_context *ctx = &hard_context[chn];
++ symc_hard_context *ctx = &g_hard_context[chn];
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /*set total num and start addr for cipher in node*/
-+ cipher_in_cfg.u32 = SYMC_READ(CHANn_CIPHER_IN_NODE_CFG(chn));
++ /* set total num and start addr for cipher in node. */
++ cipher_in_cfg.u32 = symc_read(chann_cipher_in_node_cfg(chn));
+ cipher_in_cfg.bits.cipher_in_node_total_num = SYMC_MAX_LIST_NUM;
-+ SYMC_WRITE(CHANn_CIPHER_IN_NODE_CFG(chn), cipher_in_cfg.u32);
-+ HI_LOG_INFO("CHANn_CIPHER_IN_NODE_CFG[0x%x]: \t0x%x, PHY: 0x%x, VIA %p\n",
-+ CHANn_CIPHER_IN_NODE_CFG(chn), cipher_in_cfg.u32, ADDR_L32(dma_addr), cpu_addr);
++ symc_write(chann_cipher_in_node_cfg(chn), cipher_in_cfg.u32);
++ hi_log_info("chann_cipher_in_node_cfg[0x%x]: \t0x%x, PHY: 0x%x, VIA %p\n",
++ chann_cipher_in_node_cfg(chn), cipher_in_cfg.u32, addr_l32(dma_addr), cpu_addr);
+ ctx->entry_in = (symc_entry_in *)cpu_addr;
+ ctx->cnt_in = 0;
-+ ADDR_U64(dma_addr) += SYMC_NODE_SIZE;
++ addr_u64(dma_addr) += SYMC_NODE_SIZE;
+ cpu_addr = (hi_u8 *)cpu_addr + SYMC_NODE_SIZE;
+
-+ /*set total num and start addr for cipher out node*/
-+ cipher_out_cfg.u32 = SYMC_READ(CHANn_CIPHER_OUT_NODE_CFG(chn));
++ /* set total num and start addr for cipher out node. */
++ cipher_out_cfg.u32 = symc_read(chann_cipher_out_node_cfg(chn));
+ cipher_out_cfg.bits.cipher_out_node_total_num = SYMC_MAX_LIST_NUM;
-+ SYMC_WRITE(CHANn_CIPHER_OUT_NODE_CFG(chn), cipher_out_cfg.u32);
-+ HI_LOG_INFO("CHANn_CIPHER_OUT_NODE_CFG[0x%x]: \t0x%x, PHY: 0x%x, VIA %p\n",
-+ CHANn_CIPHER_OUT_NODE_CFG(chn), cipher_out_cfg.u32, ADDR_L32(dma_addr), cpu_addr);
++ symc_write(chann_cipher_out_node_cfg(chn), cipher_out_cfg.u32);
++ hi_log_info("chann_cipher_out_node_cfg[0x%x]: \t0x%x, PHY: 0x%x, VIA %p\n",
++ chann_cipher_out_node_cfg(chn), cipher_out_cfg.u32, addr_l32(dma_addr), cpu_addr);
+ ctx->entry_out = (symc_entry_out *)cpu_addr;
+ ctx->cnt_out = 0;
-+ ADDR_U64(dma_addr) += SYMC_NODE_SIZE;
++ addr_u64(dma_addr) += SYMC_NODE_SIZE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+}
+
-+/*! set symc pad buffer */
-+static void drv_symc_set_pad_buffer(hi_u32 chn, compat_addr dma_addr, void *cpu_addr)
++/* set symc pad buffer */
++static hi_void drv_symc_set_pad_buffer(hi_u32 chn, compat_addr dma_addr, hi_void *cpu_addr)
+{
-+ symc_hard_context *ctx = &hard_context[chn];
++ symc_hard_context *ctx = &g_hard_context[chn];
+
+ ctx->dma_pad = dma_addr;
+ ctx->via_pad = cpu_addr;
+ ctx->offset_pad = 0x00;
+}
+
-+/*! set smmu */
-+static void drv_symc_smmu_bypass(void)
++/* set smmu */
++static hi_void drv_symc_smmu_bypass(hi_void)
+{
+#ifdef CRYPTO_SMMU_SUPPORT
+ cipher_in_smmu_en cipher_in_smmu_en;
+ out_smmu_en out_smmu_en;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ cipher_in_smmu_en.u32 = SYMC_READ(CIPHER_IN_SMMU_EN);
-+ out_smmu_en.u32 = SYMC_READ(OUT_SMMU_EN);
++ cipher_in_smmu_en.u32 = symc_read(CIPHER_IN_SMMU_EN);
++ out_smmu_en.u32 = symc_read(OUT_SMMU_EN);
+
+ cipher_in_smmu_en.bits.cipher_in_chan_rd_dat_smmu_en |= CIPHER_HARD_CHANNEL_MASK >> 1;
+ cipher_in_smmu_en.bits.cipher_in_chan_rd_node_smmu_en &= ~(CIPHER_HARD_CHANNEL_MASK >> 1);
@@ -205617,102 +274714,102 @@ index 0000000..d3bd694
+ out_smmu_en.bits.out_chan_wr_dat_smmu_en |= CIPHER_HARD_CHANNEL_MASK >> 1;
+ out_smmu_en.bits.out_chan_rd_node_smmu_en &= ~(CIPHER_HARD_CHANNEL_MASK >> 1);
+
-+ SYMC_WRITE(CIPHER_IN_SMMU_EN, cipher_in_smmu_en.u32);
-+ SYMC_WRITE(OUT_SMMU_EN, out_smmu_en.u32);
++ symc_write(CIPHER_IN_SMMU_EN, cipher_in_smmu_en.u32);
++ symc_write(OUT_SMMU_EN, out_smmu_en.u32);
+
-+ HI_LOG_INFO("CIPHER_IN_SMMU_EN[0x%x]: 0x%x\n", CIPHER_IN_SMMU_EN, cipher_in_smmu_en.u32);
-+ HI_LOG_INFO("OUT_SMMU_EN[0x%x] : 0x%x\n", OUT_SMMU_EN, out_smmu_en.u32);
++ hi_log_info("CIPHER_IN_SMMU_EN[0x%x]: 0x%x\n", CIPHER_IN_SMMU_EN, cipher_in_smmu_en.u32);
++ hi_log_info("OUT_SMMU_EN[0x%x] : 0x%x\n", OUT_SMMU_EN, out_smmu_en.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+#endif
+}
+
-+/*! smmu set base address */
-+static void drv_symc_smmu_base_addr(void)
++/* smmu set base address */
++static hi_void drv_symc_smmu_base_addr(hi_void)
+{
+#ifdef CRYPTO_SMMU_SUPPORT
+ hi_u64 err_raddr = 0;
+ hi_u64 err_waddr = 0;
+ hi_u64 table_addr = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* get table base addr from system api */
+ smmu_get_table_addr(&err_raddr, &err_waddr, &table_addr);
+
+ if (crypto_is_sec_cpu()) {
-+ SYMC_WRITE(SEC_SMMU_START_ADDR, (hi_u32)table_addr);
-+ HI_LOG_INFO("SEC_SMMU_START_ADDR[0x%x] : 0x%x\n", SEC_SMMU_START_ADDR, (hi_u32)table_addr);
++ symc_write(SEC_SMMU_START_ADDR, (hi_u32)table_addr);
++ hi_log_info("SEC_SMMU_START_ADDR[0x%x] : 0x%x\n", SEC_SMMU_START_ADDR, (hi_u32)table_addr);
+ } else {
-+ SYMC_WRITE(NORM_SMMU_START_ADDR, (hi_u32)table_addr);
-+ HI_LOG_INFO("NORM_SMMU_START_ADDR[0x%x] : 0x%x\n", NORM_SMMU_START_ADDR, (hi_u32)table_addr);
++ symc_write(NORM_SMMU_START_ADDR, (hi_u32)table_addr);
++ hi_log_info("NORM_SMMU_START_ADDR[0x%x] : 0x%x\n", NORM_SMMU_START_ADDR, (hi_u32)table_addr);
+ }
+#endif
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+/*! set secure channel,
-+ * non-secure CPU can't change the value of SEC_CHN_CFG,
-+ * so non-secure CPU call this function will do nothing.
++/* set secure channel,
++ * non-secure CPU can't change the value of SEC_CHN_CFG,
++ * so non-secure CPU call this function will do nothing.
+ */
-+static void drv_symc_enable_secure(hi_u32 chn, hi_u32 enable)
++static hi_void drv_symc_enable_secure(hi_u32 chn, hi_u32 enable)
+{
+ sec_chn_cfg sec_chn_cfg;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /*The SEC_CHN_CFG only can be set by secure CPU*/
-+ sec_chn_cfg.u32 = SYMC_READ(SEC_CHN_CFG);
++ /* The SEC_CHN_CFG only can be set by secure CPU. */
++ sec_chn_cfg.u32 = symc_read(SEC_CHN_CFG);
+ if (enable == HI_TRUE) {
+ sec_chn_cfg.bits.cipher_sec_chn_cfg |= 0x01 << chn;
+ } else {
+ sec_chn_cfg.bits.cipher_sec_chn_cfg &= ~(0x01 << chn);
+ }
-+ SYMC_WRITE(SEC_CHN_CFG, sec_chn_cfg.u32);
-+ HI_LOG_INFO("SEC_CHN_CFG[0x%x]: 0x%x\n", SEC_CHN_CFG, sec_chn_cfg.u32);
++ symc_write(SEC_CHN_CFG, sec_chn_cfg.u32);
++ hi_log_info("SEC_CHN_CFG[0x%x]: 0x%x\n", SEC_CHN_CFG, sec_chn_cfg.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+static void drv_symc_print_last_node(hi_u32 chn_num)
++static hi_void drv_symc_print_last_node(hi_u32 chn_num)
+{
+ symc_entry_in *in = HI_NULL;
+ symc_entry_out *out = HI_NULL;
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
-+ /* get last in node info*/
++ /* get last in node info. */
+ if (ctx->id_in == 0x00) {
+ in = &ctx->entry_in[SYMC_NODE_LIST_SIZE];
+ } else {
+ in = &ctx->entry_in[ctx->id_in - 1];
+ }
+
-+ /* get last out node info*/
++ /* get last out node info. */
+ if (ctx->id_out == 0x00) {
+ out = &ctx->entry_out[SYMC_NODE_LIST_SIZE];
+ } else {
+ out = &ctx->entry_out[ctx->id_out - 1];
+ }
+
-+ HI_LOG_ERROR("chn %d, src addr 0x%x, size 0x%x, dest addr 0x%x, size 0x%x\n",
++ hi_log_error("chn %d, src addr 0x%x, size 0x%x, dest addr 0x%x, size 0x%x\n",
+ chn_num, in->sym_start_addr, in->sym_alg_length,
+ out->sym_start_addr, out->sym_alg_length);
-+ CRYPTO_UNUSED(in);
-+ CRYPTO_UNUSED(out);
++ crypto_unused(in);
++ crypto_unused(out);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static void drv_symc_print_status(hi_u32 chn_num)
++static hi_void drv_symc_print_status(hi_u32 chn_num)
+{
+ cipher_int_raw raw;
+ cipher_int_status status;
@@ -205721,53 +274818,54 @@ index 0000000..d3bd694
+ chann_cipher_in_node_cfg in_node_cfg;
+ chann_cipher_out_node_cfg out_node_cfg;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ in_node_cfg.u32 = SYMC_READ(CHANn_CIPHER_IN_NODE_CFG(chn_num));
-+ out_node_cfg.u32 = SYMC_READ(CHANn_CIPHER_OUT_NODE_CFG(chn_num));
-+ HI_LOG_ERROR("CHANn_CIPHER_IN_NODE_CFG : 0x%x\n", in_node_cfg.u32);
-+ HI_LOG_ERROR("CHANn_CIPHER_IN_NODE_START_ADDR : 0x%x\n", SYMC_READ(CHANn_CIPHER_IN_NODE_START_ADDR(chn_num)));
-+ HI_LOG_ERROR("CHANn_CIPHER_IN_BUF_RPTR : 0x%x\n", SYMC_READ(CHANn_CIPHER_IN_BUF_RPTR(chn_num)));
-+ HI_LOG_ERROR("CHANn_CIPHER_OUT_NODE_CFG : 0x%x\n", out_node_cfg.u32);
-+ HI_LOG_ERROR("CHANn_CIPHER_OUT_NODE_START_ADDR: 0x%x\n", SYMC_READ(CHANn_CIPHER_OUT_NODE_START_ADDR(chn_num)));
-+ HI_LOG_ERROR("CHANn_CIPHER_OUT_BUF_RPTR : 0x%x\n", SYMC_READ(CHANn_CIPHER_OUT_BUF_RPTR(chn_num)));
-+ HI_LOG_ERROR("CHANn_CIPHER_CTRL : 0x%x\n", SYMC_READ(CHANn_CIPHER_CTRL(chn_num)));
++ in_node_cfg.u32 = symc_read(chann_cipher_in_node_cfg(chn_num));
++ out_node_cfg.u32 = symc_read(chann_cipher_out_node_cfg(chn_num));
++ hi_log_error("chann_cipher_in_node_cfg : 0x%x\n", in_node_cfg.u32);
++ hi_log_error("chann_cipher_in_node_start_addr : 0x%x\n", symc_read(chann_cipher_in_node_start_addr(chn_num)));
++ hi_log_error("chann_cipher_in_buf_rptr : 0x%x\n", symc_read(chann_cipher_in_buf_rptr(chn_num)));
++ hi_log_error("chann_cipher_out_node_cfg : 0x%x\n", out_node_cfg.u32);
++ hi_log_error("chann_cipher_out_node_start_addr: 0x%x\n", symc_read(chann_cipher_out_node_start_addr(chn_num)));
++ hi_log_error("chann_cipher_out_buf_rptr : 0x%x\n", symc_read(chann_cipher_out_buf_rptr(chn_num)));
++ hi_log_error("chann_cipher_ctrl : 0x%x\n", symc_read(chann_cipher_ctrl(chn_num)));
+
-+ raw.u32 = SYMC_READ(CIPHER_INT_RAW);
-+ status.u32 = SYMC_READ(CIPHER_INT_STATUS);
-+ enable.u32 = SYMC_READ(CIPHER_INT_EN);
-+ cfg.u32 = SYMC_READ(SEC_CHN_CFG);
-+ HI_LOG_ERROR("\nsec_chn_cfg 0x%x, chn %d, nsec_int_en 0x%x, sec_int_en 0x%x, chn_obuf_en 0x%x, status 0x%x, raw 0x%x\n",
++ raw.u32 = symc_read(CIPHER_INT_RAW);
++ status.u32 = symc_read(CIPHER_INT_STATUS);
++ enable.u32 = symc_read(CIPHER_INT_EN);
++ cfg.u32 = symc_read(SEC_CHN_CFG);
++ hi_log_error("\nsec_chn_cfg 0x%x, chn %d, nsec_int_en 0x%x, sec_int_en 0x%x, chn_obuf_en 0x%x, status 0x%x, "
++ "raw 0x%x\n",
+ (cfg.bits.cipher_sec_chn_cfg >> chn_num) & 0x01,
+ chn_num, enable.bits.cipher_nsec_int_en, enable.bits.cipher_sec_int_en,
+ (enable.bits.cipher_chn_obuf_en >> chn_num) & 0x01,
+ (status.bits.cipher_chn_obuf_int >> chn_num) & 0x01,
+ (raw.bits.cipher_chn_obuf_raw >> chn_num) & 0x01);
+
-+ HI_LOG_ERROR("\nThe cause of time out may be:\n"
++ hi_log_error("\nThe cause of time out may be:\n"
+ "\t1. SMMU address invalid\n"
+ "\t2. interrupt number or name incorrect\n"
+ "\t3. CPU type mismatching, request CPU and channel: %s\n",
+ crypto_is_sec_cpu() ? "secure" : "non-secure");
+
-+ /* avoid compile error when HI_LOG_ERROR be defined to empty */
-+ CRYPTO_UNUSED(raw);
-+ CRYPTO_UNUSED(status);
-+ CRYPTO_UNUSED(enable);
-+ CRYPTO_UNUSED(cfg);
-+ CRYPTO_UNUSED(in_node_cfg);
-+ CRYPTO_UNUSED(out_node_cfg);
++ /* ahi_void compile error when hi_log_error be defined to empty */
++ crypto_unused(raw);
++ crypto_unused(status);
++ crypto_unused(enable);
++ crypto_unused(cfg);
++ crypto_unused(in_node_cfg);
++ crypto_unused(out_node_cfg);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+static hi_s32 drv_symc_get_err_code(hi_u32 chn_num)
++hi_void drv_symc_get_err_code(hi_u32 chn_num)
+{
-+ hi_u32 code = 0;
++ hi_u32 code;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* check error code
+ * bit0: klad_key_use_err
@@ -205776,101 +274874,98 @@ index 0000000..d3bd694
+ * bit3: out_smmu_page_not_valid
+ * bit4: klad_key_write_err
+ */
-+
-+ /*read error code*/
-+ code = SYMC_READ(CALC_ERR);
-+
++ code = symc_read(CALC_ERR);
+ if (code & KLAD_KEY_USE_ERR) {
-+ HI_LOG_ERROR("symc error: klad_key_use_err, chn %d !!!\n", chn_num);
++ hi_log_error("symc error: klad_key_use_err, chn %d !!!\n", chn_num);
+ }
+ if (code & ALG_LEN_ERR) {
-+ HI_LOG_ERROR("symc error: alg_len_err, chn %d !!!\n", chn_num);
++ hi_log_error("symc error: alg_len_err, chn %d !!!\n", chn_num);
+ }
+ if (code & SMMU_PAGE_UNVLID) {
-+ HI_LOG_ERROR("symc error: smmu_page_unvlid, chn %d !!!\n", chn_num);
++ hi_log_error("symc error: smmu_page_unvlid, chn %d !!!\n", chn_num);
+ }
+ if (code & OUT_SMMU_PAGE_NOT_VALID) {
-+ HI_LOG_ERROR("symc error: out_smmu_page_not_valid, chn %d !!!\n", chn_num);
++ hi_log_error("symc error: out_smmu_page_not_valid, chn %d !!!\n", chn_num);
+ }
+ if (code & KLAD_KEY_WRITE_ERR) {
-+ HI_LOG_ERROR("symc error: klad_key_write_err, chn %d !!!\n", chn_num);
++ hi_log_error("symc error: klad_key_write_err, chn %d !!!\n", chn_num);
+ }
+
-+ /*print the inout buffer address*/
++ /* print the inout buffer address. */
+ drv_symc_print_last_node(chn_num);
+ drv_symc_print_status(chn_num);
+
-+ HI_LOG_FUNC_EXIT();
-+ return HI_SUCCESS;
++ hi_log_func_exit();
+}
+
-+static void drv_symc_entry_init(crypto_mem mem)
++static hi_void drv_symc_entry_init(crypto_mem mem)
+{
+ hi_u32 i = 0;
-+ void *cpu_addr = HI_NULL;
++ hi_void *cpu_addr = HI_NULL;
+ compat_addr dma_pad;
+ hi_u8 *via_pad = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* set in node and out node dma buffer */
-+ HI_LOG_INFO("symc entry list configure\n");
++ hi_log_info("symc entry list configure\n");
+ cpu_addr = mem.dma_virt;
+
+ /* skip the in node and out node dma buffer */
-+ ADDR_U64(dma_pad) = ADDR_U64(mem.dma_addr) + SYMC_NODE_LIST_SIZE;
++ addr_u64(dma_pad) = addr_u64(mem.dma_addr) + SYMC_NODE_LIST_SIZE;
+ via_pad = (hi_u8 *)mem.dma_virt + SYMC_NODE_LIST_SIZE;
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ if ((CIPHER_HARD_CHANNEL_MASK >> i) & 0x01) { /*valid channel*/
++ if ((CIPHER_HARD_CHANNEL_MASK >> i) & 0x01) { /* valid channel. */
+ /* in node and out node */
+ drv_symc_set_entry(i, mem.mmz_addr, cpu_addr);
-+ ADDR_U64(hard_context[i].dma_entry) = ADDR_U64(mem.mmz_addr);
-+ ADDR_U64(mem.mmz_addr) += SYMC_NODE_SIZE * 2; /* move to next channel */
-+ cpu_addr = (hi_u8 *)cpu_addr + SYMC_NODE_SIZE * 2; /* move to next channel */
++ addr_u64(g_hard_context[i].dma_entry) = addr_u64(mem.mmz_addr);
++ addr_u64(mem.mmz_addr) += SYMC_NODE_SIZE * MUL_VAL_2; /* move to next channel */
++ cpu_addr = (hi_u8 *)cpu_addr + SYMC_NODE_SIZE * MUL_VAL_2; /* move to next channel */
+
+ /* padding */
+ drv_symc_set_pad_buffer(i, dma_pad, via_pad);
-+ ADDR_U64(dma_pad) += SYMC_PAD_BUFFER_LEN;
++ addr_u64(dma_pad) += SYMC_PAD_BUFFER_LEN;
+ via_pad += SYMC_PAD_BUFFER_LEN;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static hi_s32 drv_symc_mem_init(void)
++static hi_s32 drv_symc_mem_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /** dma buffer struct
-+ * ((in_node || out_node) * chn_num) || (pad_buffer * chn_num)
-+ */
-+ HI_LOG_INFO("alloc memory for nodes list\n");
-+ ret = crypto_mem_create(&symc_dma, SEC_MMZ, "symc_node_list",
++ /*
++ * dma buffer struct
++ * ((in_node || out_node) * chn_num) || (pad_buffer * chn_num)
++ */
++ hi_log_info("alloc memory for nodes list\n");
++ ret = crypto_mem_create(&g_symc_dma, SEC_MMZ, "symc_node_list",
+ SYMC_NODE_LIST_SIZE + SYMC_PAD_BUFFER_TOTAL_LEN);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, malloc ddr for symc nodes list failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_create, ret);
++ hi_log_error("error, malloc ddr for symc nodes list failed\n");
++ hi_log_print_func_err(crypto_mem_create, ret);
+ return ret;
+ }
+
-+ drv_symc_entry_init(symc_dma);
++ drv_symc_entry_init(g_symc_dma);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 drv_symc_mem_deinit(void)
++static hi_s32 drv_symc_mem_deinit(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ ret = crypto_mem_destory(&symc_dma);
++ ret = crypto_mem_destory(&g_symc_dma);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_destory, ret);
++ hi_log_print_func_err(crypto_mem_destory, ret);
+ return ret;
+ }
+
@@ -205879,117 +274974,62 @@ index 0000000..d3bd694
+
+static hi_s32 drv_symc_chn_resume(hi_u32 chn_num)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 base = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (crypto_is_sec_cpu()) {
-+ base = SYMC_READ(SEC_SMMU_START_ADDR);
++ base = symc_read(SEC_SMMU_START_ADDR);
+ } else {
-+ base = SYMC_READ(NORM_SMMU_START_ADDR);
++ base = symc_read(NORM_SMMU_START_ADDR);
+ }
+
+ if (base == 0) {
+ /* smmu base address is zero means hardware be unexpected reset */
-+ HI_LOG_WARN("cipher module is not ready, try to resume it now...\n");
++ hi_log_warn("cipher module is not ready, try to resume it now...\n");
+ ret = drv_symc_resume();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_resume, ret);
++ hi_log_print_func_err(drv_symc_resume, ret);
+ return ret;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 drv_symc_alloc_chn(hi_u32 *chn_num)
+{
-+ hi_s32 ret = HI_ERR_CIPHER_BUSY;
-+ symc_chn_who_used tee, ree;
-+ hi_u32 i = 0;
-+ hi_u32 ree_use = 0, tee_use = 0;
++ hi_s32 ret;
++ hi_u32 i;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
+ /* check the valid channel */
-+ if ((CIPHER_HARD_CHANNEL_MASK & (0x1 << i)) && (hard_context[i].open == HI_FALSE)) {
-+ /*get every chanel status occupied with REE/TEE */
-+ tee.u32 = SYMC_READ(CHN_WHO_USED_TEE);
-+ ree.u32 = SYMC_READ(CHN_WHO_USED_REE);
-+ tee_use = tee.bits.non_sec_chn_who_used & SYMC_CHN_MASK(i);
-+ ree_use = ree.bits.non_sec_chn_who_used & SYMC_CHN_MASK(i);
-+
-+ /* 0x00 is not used */
-+ if (tee_use == 0x00 && ree_use == 0x00) {
-+ if (crypto_is_sec_cpu() == HI_TRUE) {
-+ tee.bits.non_sec_chn_who_used |= SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_TEE, tee.u32);
-+
-+ /* check if the channal aleardy be useded by other cpu
-+ * if other cpu break-in when write the CIPHER_NON_SEC_CHN_WHO_USED
-+ * the value of CIPHER_NON_SEC_CHN_WHO_USED will be channged
-+ */
-+ ree.u32 = SYMC_READ(CHN_WHO_USED_REE);
-+ ree_use = ree.bits.non_sec_chn_who_used & SYMC_CHN_MASK(i);
-+ if (ree_use) {
-+ /* chn aleardy be used by ree */
-+ tee.bits.non_sec_chn_who_used &= ~ SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_TEE, tee.u32);
-+ continue;
-+ }
-+
-+ drv_symc_enable_secure(i, HI_TRUE);
-+ ret = drv_symc_recover_entry(i);
-+ if (ret != HI_SUCCESS) {
-+ /* chn aleardy be used by ree */
-+ tee.bits.non_sec_chn_who_used &= ~ SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_TEE, tee.u32);
-+ continue;
-+ }
-+ } else {
-+ ree.bits.non_sec_chn_who_used |= SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_REE, ree.u32);
-+
-+ /* check if the channal aleardy be useded by other cpu
-+ * if other cpu break-in when write the CIPHER_NON_SEC_CHN_WHO_USED
-+ * the value of CIPHER_NON_SEC_CHN_WHO_USED will be channged
-+ */
-+ tee.u32 = SYMC_READ(CHN_WHO_USED_TEE);
-+ tee_use = tee.bits.non_sec_chn_who_used & SYMC_CHN_MASK(i);
-+ if (tee_use) {
-+ /* chn aleardy be used by tee */
-+ ree.bits.non_sec_chn_who_used &= ~ SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_REE, ree.u32);
-+ continue;
-+ }
-+
-+ drv_symc_enable_secure(i, HI_TRUE);
-+ ret = drv_symc_recover_entry(i);
-+ if (ret != HI_SUCCESS) {
-+ /* chn aleardy be used by tee */
-+ ree.bits.non_sec_chn_who_used &= ~ SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_REE, ree.u32);
-+ continue;
-+ }
-+ }
-+
-+ /* alloc channel */
-+ hard_context[i].open = HI_TRUE;
-+ *chn_num = i;
-+ HI_LOG_INFO("alloc symc chn %d.\n", i);
-+ break;
-+ }
++ if (((CIPHER_HARD_CHANNEL_MASK & (0x1 << i)) == 0x00) || (g_hard_context[i].open == HI_TRUE)) {
++ continue;
+ }
++
++ drv_symc_enable_secure(i, HI_TRUE);
++ ret = drv_symc_recover_entry(i);
++ if (ret != HI_SUCCESS) {
++ continue;
++ }
++
++ /* alloc channel */
++ g_hard_context[i].open = HI_TRUE;
++ *chn_num = i;
++ hi_log_info("alloc symc chn %d.\n", i);
++ break;
+ }
+
+ if (i >= CRYPTO_HARD_CHANNEL_MAX) {
-+ HI_LOG_ERROR("symc alloc channel failed\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_BUSY);
++ hi_log_error("symc alloc channel failed\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_BUSY);
+ return HI_ERR_CIPHER_BUSY;
+ }
+
@@ -206000,71 +275040,71 @@ index 0000000..d3bd694
+ */
+ ret = drv_symc_chn_resume(*chn_num);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_chn_resume, ret);
++ hi_log_print_func_err(drv_symc_chn_resume, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void drv_symc_free_chn(hi_u32 chn_num)
++hi_void drv_symc_free_chn(hi_u32 chn_num)
+{
+ symc_chn_who_used used;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if (hard_context[chn_num].open == HI_FALSE) {
-+ HI_LOG_FUNC_EXIT();
++ if (g_hard_context[chn_num].open == HI_FALSE) {
++ hi_log_func_exit();
+ return;
+ }
+
+ /* clean tee and ree mask */
+ if (crypto_is_sec_cpu() == HI_TRUE) {
-+ used.u32 = SYMC_READ(CHN_WHO_USED_TEE);
-+ used.bits.non_sec_chn_who_used &= ~ SYMC_CHN_MASK(chn_num);
-+ SYMC_WRITE(CHN_WHO_USED_TEE, used.u32);
++ used.u32 = symc_read(CHN_WHO_USED_TEE);
++ used.bits.non_sec_chn_who_used &= (~symc_chn_mask(chn_num));
++ symc_write(CHN_WHO_USED_TEE, used.u32);
+ } else {
-+ used.u32 = SYMC_READ(CHN_WHO_USED_REE);
-+ used.bits.non_sec_chn_who_used &= ~ SYMC_CHN_MASK(chn_num);
-+ SYMC_WRITE(CHN_WHO_USED_REE, used.u32);
++ used.u32 = symc_read(CHN_WHO_USED_REE);
++ used.bits.non_sec_chn_who_used &= (~symc_chn_mask(chn_num));
++ symc_write(CHN_WHO_USED_REE, used.u32);
+ }
+
+ drv_symc_enable_secure(chn_num, HI_FALSE);
-+ if (hard_context[chn_num].destory != HI_NULL) {
-+ hard_context[chn_num].destory();
-+ hard_context[chn_num].destory = HI_NULL;
++ if (g_hard_context[chn_num].destory != HI_NULL) {
++ g_hard_context[chn_num].destory();
++ g_hard_context[chn_num].destory = HI_NULL;
+ }
+
-+ /*free channel*/
-+ hard_context[chn_num].open = HI_FALSE;
++ /* free channel. */
++ g_hard_context[chn_num].open = HI_FALSE;
+
-+ HI_LOG_INFO("free symc chn %d.\n", chn_num);
++ hi_log_info("free symc chn %d.\n", chn_num);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
+#ifdef CRYPTO_SWITCH_CPU
-+hi_u32 drv_symc_is_secure(void)
++hi_u32 drv_symc_is_secure(hi_void)
+{
+ sec_chn_cfg sec;
+ sec_chn_cfg tmp;
+ hi_u32 secure = HI_FALSE;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("Change the secure type of the chn0 to get cpu type\n");
++ hi_log_info("Change the secure type of the chn0 to get cpu type\n");
+ module_enable(CRYPTO_MODULE_ID_SYMC);
+
-+ sec.u32 = SYMC_READ(SEC_CHN_CFG);
++ sec.u32 = symc_read(SEC_CHN_CFG);
+
+ /* change the secure type of chn0 */
+ sec.bits.cipher_sec_chn_cfg ^= 0x01;
-+ SYMC_WRITE(SEC_CHN_CFG, sec.u32);
++ symc_write(SEC_CHN_CFG, sec.u32);
+
+ /* read the secure type of chn0 */
-+ tmp.u32 = SYMC_READ(SEC_CHN_CFG);
++ tmp.u32 = symc_read(SEC_CHN_CFG);
+
+ if (tmp.bits.cipher_sec_chn_cfg == sec.bits.cipher_sec_chn_cfg) {
+ /* The REG_SEC_CHN_CFG only can be set by secure CPU
@@ -206074,32 +275114,32 @@ index 0000000..d3bd694
+
+ /* recovery the secure type of chn0 */
+ sec.bits.cipher_sec_chn_cfg ^= 0x01;
-+ SYMC_WRITE(SEC_CHN_CFG, sec.u32);
++ symc_write(SEC_CHN_CFG, sec.u32);
+ }
+
-+ HI_LOG_INFO("secure type: 0x%x\n", secure);
++ hi_log_info("secure type: 0x%x\n", secure);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return secure;
+}
+#endif
+
-+hi_s32 drv_symc_init(void)
++hi_s32 drv_symc_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 i = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if (symc_initialize == HI_TRUE) {
-+ HI_LOG_FUNC_EXIT();
++ if (g_symc_initialize == HI_TRUE) {
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
-+ crypto_memset(&symc_dma, sizeof(symc_dma), 0, sizeof(symc_dma));
-+ crypto_memset(hard_context, sizeof(hard_context), 0, sizeof(hard_context));
++ crypto_memset(&g_symc_dma, sizeof(g_symc_dma), 0, sizeof(g_symc_dma));
++ crypto_memset(g_hard_context, sizeof(g_hard_context), 0, sizeof(g_hard_context));
+
-+ HI_LOG_INFO("enable symc\n");
++ hi_log_info("enable symc\n");
+ module_enable(CRYPTO_MODULE_ID_SYMC);
+
+ module_disable(CRYPTO_MODULE_ID_SM4);
@@ -206108,25 +275148,25 @@ index 0000000..d3bd694
+ if (ret != HI_SUCCESS) {
+ goto __error;
+ }
-+ HI_LOG_INFO("SYMC DMA buffer, MMU 0x%x, MMZ 0x%x, VIA %p, size 0x%x\n",
-+ ADDR_L32(symc_dma.dma_addr), ADDR_L32(symc_dma.mmz_addr),
-+ symc_dma.dma_virt, symc_dma.dma_size);
++ hi_log_info("SYMC DMA buffer, MMU 0x%x, MMZ 0x%x, VIA %p, size 0x%x\n",
++ addr_l32(g_symc_dma.dma_addr), addr_l32(g_symc_dma.mmz_addr),
++ g_symc_dma.dma_virt, g_symc_dma.dma_size);
+
-+ HI_LOG_INFO("symc SMMU configure\n");
++ hi_log_info("symc SMMU configure\n");
+ drv_symc_smmu_bypass();
+ drv_symc_smmu_base_addr();
+
-+ HI_LOG_INFO("symc core_auto_cken_bypass configure\n");
++ hi_log_info("symc core_auto_cken_bypass configure\n");
+ drv_symc_core_auto_cken_bypass();
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ HI_LOG_INFO("symc interrupt configure\n");
++ hi_log_info("symc interrupt configure\n");
+ drv_symc_set_interrupt();
+
-+ HI_LOG_INFO("symc register interrupt function\n");
++ hi_log_info("symc register interrupt function\n");
+ ret = drv_symc_register_interrupt();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_register_interrupt, ret);
++ hi_log_print_func_err(drv_symc_register_interrupt, ret);
+ drv_symc_mem_deinit();
+ goto __error;
+ }
@@ -206142,9 +275182,9 @@ index 0000000..d3bd694
+ }
+ }
+
-+ symc_initialize = HI_TRUE;
++ g_symc_initialize = HI_TRUE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+
+__error:
@@ -206153,34 +275193,34 @@ index 0000000..d3bd694
+ return ret;
+}
+
-+hi_s32 drv_symc_resume(void)
++hi_s32 drv_symc_resume(hi_void)
+{
+ hi_u32 i;
+ symc_chn_who_used used;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("enable symc\n");
++ hi_log_info("enable symc\n");
+ module_enable(CRYPTO_MODULE_ID_SYMC);
+ module_disable(CRYPTO_MODULE_ID_SM4);
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ if (hard_context[i].open) {
++ if (g_hard_context[i].open) {
+ if (crypto_is_sec_cpu() == HI_TRUE) {
-+ used.u32 = SYMC_READ(CHN_WHO_USED_TEE);
-+ used.bits.non_sec_chn_who_used |= SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_TEE, used.u32);
++ used.u32 = symc_read(CHN_WHO_USED_TEE);
++ used.bits.non_sec_chn_who_used |= symc_chn_mask(i);
++ symc_write(CHN_WHO_USED_TEE, used.u32);
+ } else {
-+ used.u32 = SYMC_READ(CHN_WHO_USED_REE);
-+ used.bits.non_sec_chn_who_used |= SYMC_CHN_MASK(i);
-+ SYMC_WRITE(CHN_WHO_USED_REE, used.u32);
++ used.u32 = symc_read(CHN_WHO_USED_REE);
++ used.bits.non_sec_chn_who_used |= symc_chn_mask(i);
++ symc_write(CHN_WHO_USED_REE, used.u32);
+ }
+
+ drv_symc_enable_secure(i, HI_TRUE);
+ ret = drv_symc_recover_entry(i);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_recover_entry, ret);
++ hi_log_print_func_err(drv_symc_recover_entry, ret);
+ return ret;
+ }
+ }
@@ -206190,31 +275230,31 @@ index 0000000..d3bd694
+ drv_symc_set_interrupt();
+#endif
+
-+ drv_symc_entry_init(symc_dma);
++ drv_symc_entry_init(g_symc_dma);
+ drv_symc_smmu_bypass();
+ drv_symc_smmu_base_addr();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void drv_symc_suspend(void)
++hi_void drv_symc_suspend(hi_void)
+{
+ return;
+}
+
-+hi_s32 drv_symc_deinit(void)
++hi_s32 drv_symc_deinit(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 i;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
+
+ ret = drv_symc_mem_deinit();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_mem_deinit, ret);
++ hi_log_print_func_err(drv_symc_mem_deinit, ret);
+ return ret;
+ }
+ module_disable(CRYPTO_MODULE_ID_SYMC);
@@ -206230,31 +275270,31 @@ index 0000000..d3bd694
+ }
+ }
+
-+ symc_initialize = HI_FALSE;
++ g_symc_initialize = HI_FALSE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void drv_symc_add_buf_usage(hi_u32 chn_num, hi_u32 in, symc_node_usage usage)
++hi_void drv_symc_add_buf_usage(hi_u32 chn_num, hi_u32 in, symc_node_usage usage)
+{
+ symc_hard_context *ctx = HI_NULL;
+ hi_u32 id = 0;
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
+ if (in == HI_TRUE) {
+ /* get last node */
+ id = (ctx->id_in == 0) ? SYMC_MAX_LIST_NUM - 1 : ctx->id_in - 1;
+
+ ctx->entry_in[id].sym_ctrl = ctx->entry_in[id].sym_ctrl | (hi_u32)usage;
-+ HI_LOG_INFO("chn %d, add symc in ctrl: id %d, ctrl 0x%x\n", chn_num, id, ctx->entry_in[id].sym_ctrl);
++ hi_log_info("chn %d, add symc in ctrl: id %d, ctrl 0x%x\n", chn_num, id, ctx->entry_in[id].sym_ctrl);
+ } else {
+ /* get last node */
+ id = (ctx->id_out == 0) ? SYMC_MAX_LIST_NUM - 1 : ctx->id_out - 1;
+
+ ctx->entry_out[id].aes_ctrl = ctx->entry_out[id].aes_ctrl | (hi_u32)usage;
-+ HI_LOG_INFO("chn %d, add symc out ctrl: id %d, ctrl 0x%x\n", chn_num, id, ctx->entry_out[id].aes_ctrl);
++ hi_log_info("chn %d, add symc out ctrl: id %d, ctrl 0x%x\n", chn_num, id, ctx->entry_out[id].aes_ctrl);
+ }
+
+ return;
@@ -206265,58 +275305,65 @@ index 0000000..d3bd694
+ hi_u32 i;
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
-+ /*copy iv data into channel context*/
++ /* copy iv data into channel context. */
+ for (i = 0; i < SYMC_IV_MAX_SIZE_IN_WORD; i++) {
+ ctx->iv[i] = iv[i];
+ }
+ ctx->iv_flag = flag;
+ ctx->iv_len = ivlen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void drv_symc_get_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD])
++hi_void drv_symc_get_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD])
+{
+ hi_u32 i;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ for (i = 0; i < SYMC_IV_MAX_SIZE_IN_WORD; i++) {
-+ iv[i] = SYMC_READ(CHANn_CIPHER_IVOUT(chn_num) + i * 4);
-+ HI_LOG_INFO("IV[%d]: 0x%x\n", i, iv[i]);
++ iv[i] = symc_read(chann_cipher_ivout(chn_num) + i * WORD_WIDTH);
++ hi_log_info("IV[%d]: 0x%x\n", i, iv[i]);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+void drv_symc_set_key(hi_u32 chn_num, hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD], hi_u32 odd)
++hi_void drv_symc_set_key(hi_u32 chn_num, hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD], hi_u32 key_len, hi_u32 odd)
+{
-+ hi_u32 i = 0;
++ hi_u32 i;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
++ if (key_len < SYMC_KEY_MAX_SIZE_IN_WORD * WORD_WIDTH) {
++ return;
++ }
+
-+ /*Set key, odd key only valid for aes ecb/cbc/ofb/cfb/ctr*/
-+ SYMC_WRITE(ODD_EVEN_KEY_SEL, odd);
++ /* Set key, odd key only valid for aes ecb/cbc/ofb/cfb/ctr. */
++ symc_write(ODD_EVEN_KEY_SEL, odd);
+ for (i = 0; i < SYMC_KEY_MAX_SIZE_IN_WORD; i++) {
-+ SYMC_WRITE(CIPHER_KEY(chn_num) + i * 4, key[i]);
++ symc_write(cipher_key(chn_num) + i * WORD_WIDTH, key[i]);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+void drv_symc_set_sm1_sk(hi_u32 chn_num, hi_u32 key[SYMC_SM1_SK_SIZE_IN_WORD])
++hi_void drv_symc_set_sm1_sk(hi_u32 chn_num, hi_u32 key[SYMC_SM1_SK_SIZE_IN_WORD], hi_u32 key_len)
+{
-+ hi_u32 i = 0;
++ hi_u32 i;
++
++ if (key_len < SYMC_SM1_SK_SIZE_IN_WORD * WORD_WIDTH) {
++ return;
++ }
+
+ for (i = 0; i < SYMC_SM1_SK_SIZE_IN_WORD; i++) {
-+ SYMC_WRITE(SM1_SK(chn_num) + i * 4, key[i]);
++ symc_write(sm1_sk(chn_num) + i * WORD_WIDTH, key[i]);
+ }
+ return;
+}
@@ -206324,24 +275371,24 @@ index 0000000..d3bd694
+hi_s32 drv_symc_add_inbuf(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size, symc_node_usage usage)
+{
+ symc_hard_context *ctx = HI_NULL;
-+ hi_u32 id = 0, size = 0;
-+ hi_u32 i = 0;
-+ void *addr = HI_NULL;
++ hi_u32 id, size;
++ hi_u32 i;
++ hi_void *addr = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
+ id = ctx->id_in;
+ addr = &ctx->entry_in[id];
+ size = sizeof(symc_entry_in);
+ crypto_memset(addr, size, 0, size);
+ ctx->entry_in[id].spacc_cmd = 0x00;
-+ ctx->entry_in[id].sym_start_addr = ADDR_L32(buf_phy);
-+ ctx->entry_in[id].sym_start_high = ADDR_H32(buf_phy);
++ ctx->entry_in[id].sym_start_addr = addr_l32(buf_phy);
++ ctx->entry_in[id].sym_start_high = addr_h32(buf_phy);
+ ctx->entry_in[id].sym_alg_length = buf_size;
+ ctx->entry_in[id].sym_ctrl = usage;
+
@@ -206354,16 +275401,16 @@ index 0000000..d3bd694
+ */
+ for (i = 0; i < SYMC_IV_MAX_SIZE_IN_WORD; i++) {
+ ctx->entry_in[id].iv[i] = ctx->iv[i];
-+ HI_LOG_DEBUG("IV[%d]: 0x%x\n", i, ctx->iv[i]);
++ hi_log_debug("IV[%d]: 0x%x\n", i, ctx->iv[i]);
+ }
+
-+ if (ctx->iv_flag == CIPHER_IV_CHANGE_ONE_PKG) {
++ if (ctx->iv_flag == HI_CIPHER_IV_CHG_ONE_PACK) {
+ /* update iv for first node */
+ ctx->iv_flag = 0x00;
+
+ /* don't update iv any more */
+ ctx->entry_in[id].sym_ctrl |= SYMC_NODE_USAGE_FIRST;
-+ } else if (ctx->iv_flag == CIPHER_IV_CHANGE_ALL_PKG) {
++ } else if (ctx->iv_flag == HI_CIPHER_IV_CHG_ALL_PACK) {
+ /* update iv for all node */
+ ctx->entry_in[id].sym_ctrl |= SYMC_NODE_USAGE_FIRST | SYMC_NODE_USAGE_LAST;
+ }
@@ -206371,81 +275418,81 @@ index 0000000..d3bd694
+ /* move to next node */
+ ctx->id_in++;
+ ctx->id_in %= SYMC_MAX_LIST_NUM;
-+ HI_LOG_INFO("chn %d, add symc in buf[%p]: id %d, addr 0x%x, len 0x%x, ctrl 0x%x\n",
-+ chn_num, &ctx->entry_in[id], id, ADDR_L32(buf_phy), buf_size, ctx->entry_in[id].sym_ctrl);
++ hi_log_info("chn %d, add symc in buf[%p]: id %d, addr 0x%x, len 0x%x, ctrl 0x%x\n",
++ chn_num, &ctx->entry_in[id], id, addr_l32(buf_phy), buf_size, ctx->entry_in[id].sym_ctrl);
+
-+ /* total count of computed nodes add 1*/
++ /* total count of computed nodes add 1. */
+ ctx->cnt_in++;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 drv_symc_add_outbuf(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size, symc_node_usage usage)
+{
+ symc_hard_context *ctx = HI_NULL;
-+ hi_u32 id = 0, size = 0;
-+ void *addr = HI_NULL;
++ hi_u32 id, size;
++ hi_void *addr = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
+ id = ctx->id_out;
+ addr = &ctx->entry_out[id];
+ size = sizeof(symc_entry_out);
+ crypto_memset(addr, size, 0, size);
-+ ctx->entry_out[id].sym_start_addr = ADDR_L32(buf_phy);
-+ ctx->entry_out[id].tag[0] = ADDR_H32(buf_phy);
++ ctx->entry_out[id].sym_start_addr = addr_l32(buf_phy);
++ ctx->entry_out[id].tag[0] = addr_h32(buf_phy);
+ ctx->entry_out[id].sym_alg_length = buf_size;
+ ctx->entry_out[id].aes_ctrl = usage;
+
+ /* move to next node */
+ ctx->id_out++;
+ ctx->id_out %= SYMC_MAX_LIST_NUM;
-+ HI_LOG_INFO("chn %d, add symc out buf[%p]: id %d, addr 0x%x, len 0x%x, ctrl 0x%x\n",
-+ chn_num, &ctx->entry_out[id], id, ADDR_L32(buf_phy), buf_size, usage);
++ hi_log_info("chn %d, add symc out buf[%p]: id %d, addr 0x%x, len 0x%x, ctrl 0x%x\n",
++ chn_num, &ctx->entry_out[id], id, addr_l32(buf_phy), buf_size, usage);
+
-+ /* total count of computed nodes add 1*/
++ /* total count of computed nodes add 1. */
+ ctx->cnt_out++;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_aead_ccm_add_n(hi_u32 chn_num, hi_u8 *n)
++hi_s32 drv_aead_ccm_add_n(hi_u32 chn_num, hi_u8 *nonce, hi_u32 nonce_len)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ symc_hard_context *ctx = HI_NULL;
-+ symc_node_usage usage = 0x00;
++ symc_node_usage usage;
+ compat_addr dma_pad;
+ hi_u8 *via_pad = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
-+ HI_LOG_DEBUG("PAD buffer, PHY: 0x%x, VIA %p\n", ADDR_L32(ctx->dma_pad), ctx->via_pad);
++ hi_log_debug("PAD buffer, PHY: 0x%x, VIA %p\n", addr_l32(ctx->dma_pad), ctx->via_pad);
+
-+ ADDR_U64(dma_pad) = ADDR_U64(ctx->dma_pad) + ctx->offset_pad;
++ addr_u64(dma_pad) = addr_u64(ctx->dma_pad) + ctx->offset_pad;
+ via_pad = ctx->via_pad + ctx->offset_pad;
+
+ usage = SYMC_NODE_USAGE_IN_CCM_N | SYMC_NODE_USAGE_LAST;
-+ crypto_memcpy(via_pad, SYMC_CCM_N_LEN, n, SYMC_CCM_N_LEN);
++ crypto_memcpy(via_pad, SYMC_CCM_N_LEN, nonce, nonce_len);
+ ctx->offset_pad += SYMC_CCM_N_LEN;
+ ret = drv_symc_add_inbuf(chn_num, dma_pad, SYMC_CCM_N_LEN, usage);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -206453,8 +275500,10 @@ index 0000000..d3bd694
+{
+ hi_u32 idx = 0;
+
-+ /* Formatting of the Associated Data in B1, the length of A denotes as a*/
-+ /* The value a is encoded according to the following three cases:
++ /*
++ * Formatting of the Associated Data in B1, the length of A denotes as a.
++ *
++ * The value a is encoded according to the following three cases:
+ * If 0 < a < 2^16 - 2^8, then a is encoded as a[0..15], i.e., two octets.
+ * If 2^16 - 2^8 <= a < 2^32, then a is encoded as 0xff || 0xfe || a[0..31], i.e., six octets.
+ * If 2^32 <= a < 2^64, then a is encoded as 0xff || 0xff || a[0..63], i.e., ten octets.
@@ -206462,14 +275511,14 @@ index 0000000..d3bd694
+ * 11111111 11111110 00000000 00000001 00000000 00000000.
+ */
+ if (alen < SYMC_CCM_A_SMALL_LEN) {
-+ buf[idx++] = (hi_u8)(alen >> 8);
++ buf[idx++] = (hi_u8)(alen >> SHIFT_8BITS);
+ buf[idx++] = (hi_u8)(alen);
+ } else {
-+ buf[idx++] = 0xFF;
-+ buf[idx++] = 0xFE;
-+ buf[idx++] = (hi_u8)(alen >> 24);
-+ buf[idx++] = (hi_u8)(alen >> 16);
-+ buf[idx++] = (hi_u8)(alen >> 8);
++ buf[idx++] = SYMC_AAD_PAD_VAL_FF;
++ buf[idx++] = SYMC_AAD_PAD_VAL_FE;
++ buf[idx++] = (hi_u8)(alen >> SHIFT_24BITS);
++ buf[idx++] = (hi_u8)(alen >> SHIFT_16BITS);
++ buf[idx++] = (hi_u8)(alen >> SHIFT_8BITS);
+ buf[idx++] = (hi_u8)alen;
+ }
+
@@ -206481,53 +275530,53 @@ index 0000000..d3bd694
+ symc_hard_context *ctx = HI_NULL;
+ compat_addr dma_pad;
+ hi_u8 *via_pad = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 count = 0;
++ hi_s32 ret;
++ hi_u32 count;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
-+ ctx = &hard_context[chn_num];
-+ HI_LOG_CHECK_PARAM((ctx->offset_pad + SYMC_CCM_A_HEAD_LEN) >= SYMC_PAD_BUFFER_LEN);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ ctx = &g_hard_context[chn_num];
++ hi_log_chk_param_return((ctx->offset_pad + SYMC_CCM_A_HEAD_LEN) >= SYMC_PAD_BUFFER_LEN);
+
-+ /* return success when alen is zero*/
++ /* return success when alen is zero. */
+ if (buf_size == 0x00) {
+ return HI_SUCCESS;
+ }
+
-+ ADDR_U64(dma_pad) = ADDR_U64(ctx->dma_pad) + ctx->offset_pad;
++ addr_u64(dma_pad) = addr_u64(ctx->dma_pad) + ctx->offset_pad;
+ via_pad = ctx->via_pad + ctx->offset_pad;
-+ crypto_memset(via_pad, AES_BLOCK_SIZE * 2, 0, AES_BLOCK_SIZE * 2);
++ crypto_memset(via_pad, AES_BLOCK_SIZE * MUL_VAL_2, 0, AES_BLOCK_SIZE * MUL_VAL_2);
+
+ /* add ccm a head */
+ count = drv_aead_ccm_a_head(via_pad, buf_size);
+ ret = drv_symc_add_inbuf(chn_num, dma_pad, count, SYMC_NODE_USAGE_IN_CCM_A);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+
+ /* move buffer addr */
+ ctx->offset_pad += count;
-+ ADDR_U64(dma_pad) += count;
++ addr_u64(dma_pad) += count;
+ via_pad += count;
+
-+ /* add the phy of A into node list*/
++ /* add the phy of A into node list. */
+ ret = drv_symc_add_inbuf(chn_num, buf_phy, buf_size, SYMC_NODE_USAGE_IN_CCM_A);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+
-+ /*if idx + Alen do not aligned with 16, padding 0 to the tail*/
++ /* if idx + Alen do not aligned with 16, padding 0 to the tail. */
+ count = (buf_size + count) % AES_BLOCK_SIZE;
+ if (count > 0) {
-+ /* add the padding phy of A into node list*/
++ /* add the padding phy of A into node list. */
+ ret = drv_symc_add_inbuf(chn_num, dma_pad, AES_BLOCK_SIZE - count,
+ SYMC_NODE_USAGE_IN_CCM_A);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+ ctx->offset_pad += AES_BLOCK_SIZE - count;
@@ -206536,7 +275585,7 @@ index 0000000..d3bd694
+ /* add ccm a last flag */
+ drv_symc_add_buf_usage(chn_num, HI_TRUE, SYMC_NODE_USAGE_LAST);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -206545,41 +275594,41 @@ index 0000000..d3bd694
+ symc_hard_context *ctx = HI_NULL;
+ compat_addr dma_pad;
+ hi_u8 *via_pad = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 count = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
-+ ctx = &hard_context[chn_num];
-+ HI_LOG_CHECK_PARAM((ctx->offset_pad + AES_BLOCK_SIZE) >= SYMC_PAD_BUFFER_LEN);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ ctx = &g_hard_context[chn_num];
++ hi_log_chk_param_return((ctx->offset_pad + AES_BLOCK_SIZE) >= SYMC_PAD_BUFFER_LEN);
+
-+ /* return success when alen is zero*/
++ /* return success when alen is zero. */
+ if (buf_size == 0x00) {
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
-+ ADDR_U64(dma_pad) = ADDR_U64(ctx->dma_pad) + ctx->offset_pad;
++ addr_u64(dma_pad) = addr_u64(ctx->dma_pad) + ctx->offset_pad;
+ via_pad = ctx->via_pad + ctx->offset_pad;
+ crypto_memset(via_pad, AES_BLOCK_SIZE, 0, AES_BLOCK_SIZE);
+
-+ /*Add phy of A into node list*/
++ /* Add phy of A into node list. */
+ ret = drv_symc_add_inbuf(chn_num, buf_phy, buf_size, SYMC_NODE_USAGE_IN_GCM_A);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+
-+ /*if Alen do not aligned with 16, padding 0 to the tail*/
++ /* if Alen do not aligned with 16, padding 0 to the tail. */
+ count = (buf_size + count) % AES_BLOCK_SIZE;
+ if (count > 0) {
-+ /* add the padding phy of A into node list*/
++ /* add the padding phy of A into node list. */
+ ret = drv_symc_add_inbuf(chn_num, dma_pad, AES_BLOCK_SIZE - count,
+ SYMC_NODE_USAGE_IN_GCM_A);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+ ctx->offset_pad += AES_BLOCK_SIZE - count;
@@ -206588,207 +275637,175 @@ index 0000000..d3bd694
+ /* add gcm a last flag */
+ drv_symc_add_buf_usage(chn_num, HI_TRUE, SYMC_NODE_USAGE_LAST);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_aead_gcm_add_clen(hi_u32 chn_num, hi_u8 *clen)
++hi_s32 drv_aead_gcm_add_clen(hi_u32 chn_num, hi_u8 *clen, hi_u32 clen_len)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ symc_hard_context *ctx = HI_NULL;
-+ symc_node_usage usage = 0x00;
++ symc_node_usage usage;
+ compat_addr dma_pad;
+ hi_u8 *via_pad = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
-+ ctx = &hard_context[chn_num];
-+ HI_LOG_CHECK_PARAM((ctx->offset_pad + SYMC_CCM_N_LEN) >= SYMC_PAD_BUFFER_LEN);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ ctx = &g_hard_context[chn_num];
++ hi_log_chk_param_return((ctx->offset_pad + SYMC_CCM_N_LEN) >= SYMC_PAD_BUFFER_LEN);
+
+ /* add Clen */
-+ ADDR_U64(dma_pad) = ADDR_U64(ctx->dma_pad) + ctx->offset_pad;
++ addr_u64(dma_pad) = addr_u64(ctx->dma_pad) + ctx->offset_pad;
+ via_pad = ctx->via_pad + ctx->offset_pad;
+
+ usage = SYMC_NODE_USAGE_IN_GCM_LEN | SYMC_NODE_USAGE_LAST;
+
-+ crypto_memcpy(via_pad, SYMC_GCM_CLEN_LEN, clen, SYMC_GCM_CLEN_LEN);
++ crypto_memcpy(via_pad, SYMC_GCM_CLEN_LEN, clen, clen_len);
+ ctx->offset_pad += SYMC_GCM_CLEN_LEN;
+
+ ret = drv_symc_add_inbuf(chn_num, dma_pad, SYMC_GCM_CLEN_LEN, usage);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_aead_get_tag(hi_u32 chn_num, hi_u32 *tag)
++hi_s32 drv_aead_get_tag(hi_u32 chn_num, hi_u32 *tag, hi_u32 tag_buf_len)
+{
+ symc_hard_context *ctx = HI_NULL;
+ chann_cipher_out_node_cfg out_node_cfg;
+ hi_u32 last;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
-+ out_node_cfg.u32 = SYMC_READ(CHANn_CIPHER_OUT_NODE_CFG(chn_num));
++ out_node_cfg.u32 = symc_read(chann_cipher_out_node_cfg(chn_num));
+ last = out_node_cfg.bits.cipher_out_node_wptr;
+ last = (last == 0) ? (SYMC_MAX_LIST_NUM - 1) : (last - 1);
+
-+ crypto_memcpy(tag, AEAD_TAG_SIZE_IN_WORD * 4, ctx->entry_out[last].tag,
-+ AEAD_TAG_SIZE_IN_WORD * 4);
++ crypto_memcpy(tag, tag_buf_len, ctx->entry_out[last].tag, sizeof(ctx->entry_out[last].tag));
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_symc_node_check(symc_alg alg, symc_mode mode,
-+ hi_u32 klen, hi_u32 block_size,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num)
++hi_s32 drv_symc_node_check(symc_alg alg, symc_mode mode, hi_u32 klen, hi_u32 block_size, symc_multi_pack *pack)
+{
-+ hi_u32 i = 0;
++ hi_u32 i;
+ hi_u32 total = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(block_size == 0);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(block_size == 0);
++ hi_log_chk_param_return(pack == HI_NULL);
+
-+ CRYPTO_UNUSED(input);
-+ CRYPTO_UNUSED(output);
++ crypto_unused(pack->in);
++ crypto_unused(pack->out);
+
-+ for (i = 0; i < pkg_num; i++) {
-+ /* Used the odd key must accord with conditions as follows:*/
-+ if ((hi_u32)usage_list[i] & SYMC_NODE_USAGE_ODD_KEY) {
++ for (i = 0; i < pack->num; i++) {
++ /* Used the odd key must accord with conditions as follows: */
++ if ((hi_u32)pack->usage[i] & SYMC_NODE_USAGE_ODD_KEY) {
+ /* 1. Only support aes ecb/cbc/cfb/ofb/ctr */
-+ if ((alg != SYMC_ALG_AES)
-+ || ((mode != SYMC_MODE_ECB)
-+ && (mode != SYMC_MODE_CBC)
-+ && (mode != SYMC_MODE_CFB)
-+ && (mode != SYMC_MODE_OFB)
-+ && (mode != SYMC_MODE_CTR))) {
-+ HI_LOG_ERROR("Odd key only support aes ecb/cbc/cfb/ofb/ctr.");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((alg != SYMC_ALG_AES) ||
++ ((mode != SYMC_MODE_ECB) && (mode != SYMC_MODE_CBC) && (mode != SYMC_MODE_CFB) &&
++ (mode != SYMC_MODE_OFB) && (mode != SYMC_MODE_CTR))) {
++ hi_log_error("Odd key only support aes ecb/cbc/cfb/ofb/ctr.");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ /* 2. Only support aes128 */
-+ if (klen != AES_CCM_GCM_KEY_LEN) {
-+ HI_LOG_ERROR("Odd key only support aes128, klen %d\n", klen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
++ hi_log_chk_param_return(klen != AES_CCM_GCM_KEY_LEN);
+
-+ /* 3. each node length must be a multiple of 64*/
-+ if ((length[i] % (AES_BLOCK_SIZE * 4)) != 0) {
-+ HI_LOG_ERROR("Odd key only supported when each node length is a multiple of 64.");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_LENGTH);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
-+ }
++ /* 3. each node length must be a multiple of 64 */
++ hi_log_chk_param_return((pack->len[i] % (AES_BLOCK_SIZE * WORD_WIDTH)) != 0);
+ }
+
-+ /* each node length can't be zero*/
-+ if (length[i] == 0) {
-+ HI_LOG_ERROR("PKG len must large than 0.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_LENGTH);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
-+ }
-+
-+ /* check overflow */
-+ if (length[i] > ADDR_L32(input[i]) + length[i]) {
-+ HI_LOG_ERROR("PKG len overflow.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_LENGTH);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
-+ }
-+ total += length[i];
++ /* each node length can't be zero, and check overflow. */
++ hi_log_chk_param_return((pack->len[i] == 0) || (pack->len[i] > addr_l32(pack->in[i]) + pack->len[i]));
++ total += pack->len[i];
+ }
+
-+ if ((SYMC_ALG_NULL_CIPHER != alg) &&
-+ ((SYMC_MODE_ECB == mode)
-+ || (mode == SYMC_MODE_CBC)
-+ || (mode == SYMC_MODE_CFB)
-+ || (mode == SYMC_MODE_OFB))) {
++ if ((alg != SYMC_ALG_NULL_CIPHER) &&
++ ((mode == SYMC_MODE_ECB) || (mode == SYMC_MODE_CBC) || (mode == SYMC_MODE_CFB) || (mode == SYMC_MODE_OFB))) {
+ /* The length of data depend on alg and mode, which limit to hardware
+ * for ecb/cbc/ofb/cfb, the total data length must aligned with block size.
+ * for ctr/ccm/gcm, support any data length.
+ */
+ if (total % block_size != 0) {
-+ HI_LOG_ERROR("PKG len must align with 0x%x.\n", block_size);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_LENGTH);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
++ hi_log_error("PKG len must align with 0x%x.\n", block_size);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_LEN);
++ return HI_ERR_CIPHER_INVALID_LEN;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_symc_config(hi_u32 chn_num, symc_alg alg, symc_mode mode, symc_width width, hi_u32 decrypt,
-+ hi_u32 sm1_round_num, symc_klen klen, hi_u32 hard_key)
++hi_s32 drv_symc_cfg(cryp_symc_context *ctx_cfg, hi_u32 decrypt, symc_klen klen)
+{
+ symc_hard_context *ctx = HI_NULL;
+ chann_chipher_ctrl cipher_ctrl;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
++ hi_log_chk_param_return(ctx_cfg == HI_NULL);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(ctx_cfg->hard_chn >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(ctx_cfg->alg >= SYMC_ALG_COUNT);
++ hi_log_chk_param_return(ctx_cfg->mode > SYMC_MODE_GCM);
++ hi_log_chk_param_return(klen >= SYMC_KEY_LEN_COUNT);
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
-+ HI_LOG_CHECK_PARAM(alg >= SYMC_ALG_COUNT);
-+ HI_LOG_CHECK_PARAM(mode > SYMC_MODE_GCM);
-+ HI_LOG_CHECK_PARAM(klen >= SYMC_KEY_LEN_COUNT);
-+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[ctx_cfg->hard_chn];
+
+ /* record alg */
-+ ctx->alg = alg;
-+ CRYPTO_UNUSED(sm1_round_num);
++ ctx->alg = ctx_cfg->alg;
++ crypto_unused(ctx_cfg->sm1_round);
+
-+ HI_LOG_INFO("symc configure, chn %d, alg %d, mode %d, dec %d, hard %d\n",
-+ chn_num, alg, mode, decrypt, hard_key);
++ hi_log_info("symc configure, chn %d, alg %d, mode %d, dec %d, hard %d\n",
++ ctx_cfg->hard_chn, ctx_cfg->alg, ctx_cfg->mode, decrypt, ctx_cfg->hard_key);
+
-+ cipher_ctrl.u32 = SYMC_READ(CHANn_CIPHER_CTRL(chn_num));
-+ cipher_ctrl.bits.sym_chn_sm1_round_num = sm1_round_num;
-+ cipher_ctrl.bits.sym_chn_key_sel = hard_key;
++ cipher_ctrl.u32 = symc_read(chann_cipher_ctrl(ctx_cfg->hard_chn));
++ cipher_ctrl.bits.sym_chn_sm1_round_num = ctx_cfg->sm1_round;
++ cipher_ctrl.bits.sym_chn_key_sel = ctx_cfg->hard_key;
+ cipher_ctrl.bits.sym_chn_key_length = klen;
-+ cipher_ctrl.bits.sym_chn_dat_width = width;
++ cipher_ctrl.bits.sym_chn_dat_width = ctx_cfg->width;
+ cipher_ctrl.bits.sym_chn_decrypt = decrypt;
-+ cipher_ctrl.bits.sym_chn_alg_sel = alg;
-+ cipher_ctrl.bits.sym_chn_alg_mode = mode;
-+ ctx->mode = mode;
-+ SYMC_WRITE(CHANn_CIPHER_CTRL(chn_num), cipher_ctrl.u32);
-+ HI_LOG_INFO("CHANn_CIPHER_CTRL(%d): 0x%x\n", chn_num, cipher_ctrl.u32);
++ cipher_ctrl.bits.sym_chn_alg_sel = ctx_cfg->alg;
++ cipher_ctrl.bits.sym_chn_alg_mode = ctx_cfg->mode;
++ ctx->mode = ctx_cfg->mode;
++ symc_write(chann_cipher_ctrl(ctx_cfg->hard_chn), cipher_ctrl.u32);
++ hi_log_info("chann_cipher_ctrl(%d): 0x%x\n", ctx_cfg->hard_chn, cipher_ctrl.u32);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 drv_symc_set_isr_callback(hi_u32 chn_num, callback_symc_isr callback, void *ctx)
++hi_s32 drv_symc_set_isr_callback(hi_u32 chn_num, callback_symc_isr callback, hi_void *ctx)
+{
+ symc_hard_context *hisi_ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ hisi_ctx = &hard_context[chn_num];
++ hisi_ctx = &g_hard_context[chn_num];
+
+ hisi_ctx->callback = callback;
+ hisi_ctx->ctx = ctx;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -206797,37 +275814,37 @@ index 0000000..d3bd694
+ symc_hard_context *ctx = HI_NULL;
+ chann_cipher_in_node_cfg in_node_cfg;
+ chann_cipher_out_node_cfg out_node_cfg;
-+ hi_u32 ptr = 0;
++ hi_u32 ptr;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+
-+ HI_LOG_INFO("symc start, chn %d\n", chn_num);
++ hi_log_info("symc start, chn %d\n", chn_num);
+
+ ctx->done = HI_FALSE;
+
-+ /*configure out nodes*/
-+ out_node_cfg.u32 = SYMC_READ(CHANn_CIPHER_OUT_NODE_CFG(chn_num));
++ /* configure out nodes. */
++ out_node_cfg.u32 = symc_read(chann_cipher_out_node_cfg(chn_num));
+ if (out_node_cfg.bits.cipher_out_node_wptr != out_node_cfg.bits.cipher_out_node_rptr) {
-+ HI_LOG_ERROR("Error, chn %d is busy.\n", chn_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_BUSY);
++ hi_log_error("Error, chn %d is busy.\n", chn_num);
++ hi_log_print_err_code(HI_ERR_CIPHER_BUSY);
+ return HI_ERR_CIPHER_BUSY;
+ }
+ ptr = out_node_cfg.bits.cipher_out_node_wptr + ctx->cnt_out;
+ out_node_cfg.bits.cipher_out_node_wptr = ptr % SYMC_MAX_LIST_NUM;
+ out_node_cfg.bits.cipher_out_node_mpackage_int_level = ctx->cnt_out;
-+ SYMC_WRITE(CHANn_CIPHER_OUT_NODE_CFG(chn_num), out_node_cfg.u32);
-+ HI_LOG_INFO("CHANn_CIPHER_OUT_NODE_CFG: 0x%x\n", out_node_cfg.u32);
++ symc_write(chann_cipher_out_node_cfg(chn_num), out_node_cfg.u32);
++ hi_log_info("chann_cipher_out_node_cfg: 0x%x\n", out_node_cfg.u32);
+
-+ /*configure in nodes*/
-+ in_node_cfg.u32 = SYMC_READ(CHANn_CIPHER_IN_NODE_CFG(chn_num));
++ /* configure in nodes. */
++ in_node_cfg.u32 = symc_read(chann_cipher_in_node_cfg(chn_num));
+ if (in_node_cfg.bits.cipher_in_node_wptr != in_node_cfg.bits.cipher_in_node_rptr) {
-+ HI_LOG_ERROR("Error, chn %d is busy.\n", chn_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_BUSY);
++ hi_log_error("Error, chn %d is busy.\n", chn_num);
++ hi_log_print_err_code(HI_ERR_CIPHER_BUSY);
+ return HI_ERR_CIPHER_BUSY;
+ }
+ ptr = in_node_cfg.bits.cipher_in_node_wptr + ctx->cnt_in;
@@ -206840,79 +275857,90 @@ index 0000000..d3bd694
+ }
+
+ /* start */
-+ SYMC_WRITE(CHANn_CIPHER_IN_NODE_CFG(chn_num), in_node_cfg.u32);
-+ HI_LOG_INFO("CHANn_CIPHER_IN_NODE_CFG: 0x%x\n", in_node_cfg.u32);
++ symc_write(chann_cipher_in_node_cfg(chn_num), in_node_cfg.u32);
++ hi_log_info("chann_cipher_in_node_cfg: 0x%x\n", in_node_cfg.u32);
+
-+ /*all the nodes are processed, retset the cnount to zero */
++ /* all the nodes are processed, retset the cnount to zero */
+ ctx->cnt_in = 0;
+ ctx->cnt_out = 0;
+ ctx->offset_pad = 0;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
++ return HI_SUCCESS;
++}
++
++static hi_s32 drv_symc_query_ram_interrupt(hi_u32 chn_num, symc_hard_context *ctx, hi_u32 timeout)
++{
++ hi_s32 i;
++
++ /* interrupt unsupport, query the raw interrupt flag. */
++ for (i = 0; i < timeout; i++) {
++ if (drv_symc_done_try(chn_num)) {
++ break;
++ }
++ if (i <= MS_TO_US) {
++ crypto_udelay(1); /* short waitting for 1000 us. */
++ } else {
++ crypto_msleep(1); /* long waitting for 5000 ms. */
++ }
++ }
++
++ /* Disable SM4 independent from spacc */
++ if (ctx->alg == SYMC_ALG_SM4) {
++ module_disable(CRYPTO_MODULE_ID_SM4);
++ }
++
++ if (timeout <= i) {
++ hi_log_error("symc wait done timeout, chn=%d\n", chn_num);
++ hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
++ drv_symc_get_err_code(chn_num);
++ return HI_ERR_CIPHER_TIMEOUT;
++ }
++
+ return HI_SUCCESS;
+}
+
+hi_s32 drv_symc_wait_done(hi_u32 chn_num, hi_u32 timeout)
+{
-+ hi_u32 int_valid = 0, int_num = 0;
-+ hi_u32 i;
++ hi_s32 ret;
++ hi_u32 int_valid = 0;
++ hi_u32 int_num = 0;
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc_initialize != HI_TRUE);
-+ HI_LOG_CHECK_PARAM(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_chk_param_return(g_symc_initialize != HI_TRUE);
++ hi_log_chk_param_return(chn_num >= CRYPTO_HARD_CHANNEL_MAX);
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+ module_get_attr(CRYPTO_MODULE_ID_SYMC, &int_valid, &int_num, HI_NULL);
+
+#ifdef CRYPTO_OS_INT_SUPPORT
-+ /* interrupt support, wait irq*/
++ /* interrupt support, wait irq. */
+ if (int_valid) {
-+ hi_s32 ret = HI_FAILURE;
-+
-+ /* wait interrupt */
-+ ret = crypto_queue_wait_timeout(ctx->queue, &ctx->done, timeout);
-+
-+ /* Disable SM4 independent from spacc */
-+ if (ctx->alg == SYMC_ALG_SM4) {
-+ module_disable(CRYPTO_MODULE_ID_SM4);
++ ret = drv_symc_wait_irq(chn_num, ctx, timeout);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_wait_irq, ret);
++ return ret;
+ }
-+
-+ if ((ret <= 0x00) && (ret != -ERESTARTSYS)) {
-+ HI_LOG_ERROR("wait done timeout, chn=%d\n", chn_num);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_queue_wait_timeout, ret);
-+ drv_symc_get_err_code(chn_num);
-+ return HI_ERR_CIPHER_TIMEOUT;
-+ }
-+ } else /* interrupt unsupport, query the raw interrupt flag*/
-+#endif
-+ {
-+ for (i = 0; i < timeout; i++) {
-+ if (drv_symc_done_try(chn_num)) {
-+ break;
-+ }
-+ if (MS_TO_US >= i) {
-+ crypto_udelay(1); /* short waitting for 1000 us */
-+ } else {
-+ crypto_msleep(1); /* long waitting for 5000 ms*/
-+ }
-+ }
-+
-+ /* Disable SM4 independent from spacc */
-+ if (ctx->alg == SYMC_ALG_SM4) {
-+ module_disable(CRYPTO_MODULE_ID_SM4);
-+ }
-+
-+ if (timeout <= i) {
-+ HI_LOG_ERROR("symc wait done timeout, chn=%d\n", chn_num);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_TIMEOUT);
-+ drv_symc_get_err_code(chn_num);
-+ return HI_ERR_CIPHER_TIMEOUT;
++ } else {
++ /* interrupt unsupport, query the raw interrupt flag. */
++ ret = drv_symc_query_ram_interrupt(chn_num, ctx, timeout);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_query_ram_interrupt, ret);
++ return ret;
+ }
+ }
++#else
++ /* interrupt unsupport, query the raw interrupt flag. */
++ ret = drv_symc_query_ram_interrupt(chn_num, ctx, timeout);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_query_ram_interrupt, ret);
++ return ret;
++ }
++#endif
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -206920,17 +275948,165 @@ index 0000000..d3bd694
+{
+ symc_hard_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ctx = &hard_context[chn_num];
++ ctx = &g_hard_context[chn_num];
+ ctx->destory = destory;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/******* proc function begin ********/
++/* ****** proc function begin ******* */
+#if (1 == HI_PROC_SUPPORT)
++static hi_void drv_symc_proc_status_set_open(symc_chn_status *status, hi_u32 chnnel_id)
++{
++ if (g_hard_context[chnnel_id].open == HI_TRUE) {
++ status[chnnel_id].open = "open ";
++ } else {
++ status[chnnel_id].open = "close";
++ }
++}
++
++static hi_void drv_symc_proc_status_set_alg(symc_chn_status *status, hi_u32 chnnel_id, hi_u32 ctrl_info)
++{
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
++ switch (ctrl.bits.sym_chn_alg_sel) {
++ case HI_CIPHER_ALG_DES:
++ status[chnnel_id].alg = "DES ";
++ break;
++ case HI_CIPHER_ALG_3DES:
++ status[chnnel_id].alg = "3DES";
++ break;
++ case HI_CIPHER_ALG_AES:
++ status[chnnel_id].alg = "AES ";
++ break;
++ case HI_CIPHER_ALG_SM1:
++ status[chnnel_id].alg = "SM1 ";
++ break;
++ case HI_CIPHER_ALG_SM4:
++ status[chnnel_id].alg = "SM4 ";
++ break;
++ case HI_CIPHER_ALG_DMA:
++ status[chnnel_id].alg = "DMA ";
++ break;
++ default:
++ status[chnnel_id].alg = "BUTT";
++ break;
++ }
++}
++
++static hi_void drv_symc_proc_status_set_mode(symc_chn_status *status, hi_u32 chnnel_id, hi_u32 ctrl_info)
++{
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
++ switch (ctrl.bits.sym_chn_alg_mode) {
++ case HI_CIPHER_WORK_MODE_ECB:
++ status[chnnel_id].mode = "ECB ";
++ break;
++ case HI_CIPHER_WORK_MODE_CBC:
++ status[chnnel_id].mode = "CBC ";
++ break;
++ case HI_CIPHER_WORK_MODE_CFB:
++ status[chnnel_id].mode = "CFB ";
++ break;
++ case HI_CIPHER_WORK_MODE_OFB:
++ status[chnnel_id].mode = "OFB ";
++ break;
++ case HI_CIPHER_WORK_MODE_CTR:
++ status[chnnel_id].mode = "CTR ";
++ break;
++ case HI_CIPHER_WORK_MODE_CCM:
++ status[chnnel_id].mode = "CCM ";
++ break;
++ case HI_CIPHER_WORK_MODE_GCM:
++ status[chnnel_id].mode = "GCM ";
++ break;
++ default:
++ status[chnnel_id].mode = "BUTT";
++ break;
++ }
++}
++
++static hi_void drv_symc_proc_status_set_key_len(symc_chn_status *status, hi_u32 chnnel_id, hi_u32 ctrl_info)
++{
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
++ if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_AES) {
++ switch (ctrl.bits.sym_chn_key_length) {
++ case HI_CIPHER_KEY_AES_128BIT:
++ status[chnnel_id].klen = AES_KEY_128BIT;
++ break;
++ case HI_CIPHER_KEY_AES_192BIT:
++ status[chnnel_id].klen = AES_KEY_192BIT;
++ break;
++ case HI_CIPHER_KEY_AES_256BIT:
++ status[chnnel_id].klen = AES_KEY_256BIT;
++ break;
++ default:
++ status[chnnel_id].klen = 0;
++ break;
++ }
++ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_DES) {
++ status[chnnel_id].klen = DES_KEY_SIZE;
++ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_3DES) {
++ switch (ctrl.bits.sym_chn_key_length) {
++ case HI_CIPHER_KEY_DES_3KEY:
++ status[chnnel_id].klen = TDES_KEY_192BIT;
++ break;
++ case HI_CIPHER_KEY_DES_2KEY:
++ status[chnnel_id].klen = TDES_KEY_128BIT;
++ break;
++ default:
++ status[chnnel_id].klen = 0;
++ break;
++ }
++ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_SM1) {
++ status[chnnel_id].klen = SM1_AK_EK_SIZE + SM1_SK_SIZE;
++ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_SM4) {
++ status[chnnel_id].klen = SM4_KEY_SIZE;
++ } else {
++ status[chnnel_id].klen = 0;
++ }
++}
++
++static hi_void drv_symc_proc_status_set_key_sel(symc_chn_status *status, hi_u32 chnnel_id, hi_u32 ctrl_info)
++{
++ chann_chipher_ctrl ctrl;
++
++ ctrl.u32 = ctrl_info;
++ if (ctrl.bits.sym_chn_key_sel) {
++ status[chnnel_id].ksrc = "HW";
++ } else {
++ status[chnnel_id].ksrc = "SW";
++ }
++}
++
++static hi_void drv_symc_proc_status_set_addr(symc_chn_status *status, hi_u32 chnnel_id)
++{
++ hi_u32 addr;
++
++ /* get data in */
++ if (chnnel_id != 0) {
++ addr = chann_cipher_in_buf_rptr(chnnel_id);
++ status[chnnel_id].inaddr = symc_read(addr);
++ } else {
++ status[0].inaddr = CHAN0_CIPHER_DIN;
++ }
++
++ /* get data out */
++ if (chnnel_id != 0) {
++ addr = chann_cipher_out_buf_rptr(chnnel_id);
++ status[chnnel_id].outaddr = symc_read(addr);
++ } else {
++ status[0].outaddr = CHAN0_CIPHER_DOUT;
++ }
++}
++
+hi_s32 drv_symc_proc_status(symc_chn_status *status)
+{
+ hi_u32 addr = 0;
@@ -206942,186 +276118,55 @@ index 0000000..d3bd694
+ hi_u32 i, j;
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ if (hard_context[i].open == HI_TRUE) {
-+ status[i].open = "open ";
-+ } else {
-+ status[i].open = "close";
-+ }
++ drv_symc_proc_status_set_open(status, i);
++
+ /* get cipher ctrl */
-+ if (0 != i) {
-+ addr = CHANn_CIPHER_CTRL(i);
++ if (i != 0) {
++ addr = chann_cipher_ctrl(i);
+ } else {
+ addr = CHAN0_CIPHER_CTRL;
+ }
+
-+ ctrl.u32 = SYMC_READ(addr);
++ ctrl.u32 = symc_read(addr);
+ status[i].decrypt = ctrl.bits.sym_chn_decrypt;
-+ switch (ctrl.bits.sym_chn_alg_sel) {
-+ case HI_CIPHER_ALG_DES: {
-+ status[i].alg = "DES ";
-+ break;
-+ }
-+ case HI_CIPHER_ALG_3DES: {
-+ status[i].alg = "3DES";
-+ break;
-+ }
-+ case HI_CIPHER_ALG_AES: {
-+ status[i].alg = "AES ";
-+ break;
-+ }
-+ case HI_CIPHER_ALG_SM1: {
-+ status[i].alg = "SM1 ";
-+ break;
-+ }
-+ case HI_CIPHER_ALG_SM4: {
-+ status[i].alg = "SM4 ";
-+ break;
-+ }
-+ case HI_CIPHER_ALG_DMA: {
-+ status[i].alg = "DMA ";
-+ break;
-+ }
-+ default: {
-+ status[i].alg = "BUTT";
-+ break;
-+ }
-+ }
++ drv_symc_proc_status_set_alg(status, i, ctrl.u32);
++ drv_symc_proc_status_set_mode(status, i, ctrl.u32);
++ drv_symc_proc_status_set_key_len(status, i, ctrl.u32);
++ drv_symc_proc_status_set_key_sel(status, i, ctrl.u32);
++ drv_symc_proc_status_set_addr(status, i);
+
-+ switch (ctrl.bits.sym_chn_alg_mode) {
-+ case HI_CIPHER_WORK_MODE_ECB: {
-+ status[i].mode = "ECB ";
-+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CBC: {
-+ status[i].mode = "CBC ";
-+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CFB: {
-+ status[i].mode = "CFB ";
-+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_OFB: {
-+ status[i].mode = "OFB ";
-+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CTR: {
-+ status[i].mode = "CTR ";
-+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_CCM: {
-+ status[i].mode = "CCM ";
-+ break;
-+ }
-+ case HI_CIPHER_WORK_MODE_GCM: {
-+ status[i].mode = "GCM ";
-+ break;
-+ }
-+ default: {
-+ status[i].mode = "BUTT";
-+ break;
-+ }
-+ }
-+
-+ if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_AES) {
-+ switch (ctrl.bits.sym_chn_key_length) {
-+ case HI_CIPHER_KEY_AES_128BIT: {
-+ status[i].klen = AES_KEY_128BIT;
-+ break;
-+ }
-+ case HI_CIPHER_KEY_AES_192BIT: {
-+ status[i].klen = AES_KEY_192BIT;
-+ break;
-+ }
-+ case HI_CIPHER_KEY_AES_256BIT: {
-+ status[i].klen = AES_KEY_256BIT;
-+ break;
-+ }
-+ default: {
-+ status[i].klen = 0;
-+ break;
-+ }
-+ }
-+ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_DES) {
-+ status[i].klen = DES_KEY_SIZE;
-+ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_3DES) {
-+ switch (ctrl.bits.sym_chn_key_length) {
-+ case HI_CIPHER_KEY_DES_3KEY: {
-+ status[i].klen = TDES_KEY_192BIT;
-+ break;
-+ }
-+ case HI_CIPHER_KEY_DES_2KEY: {
-+ status[i].klen = TDES_KEY_128BIT;
-+ break;
-+ }
-+ default: {
-+ status[i].klen = 0;
-+ break;
-+ }
-+ }
-+ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_SM1) {
-+ status[i].klen = SM1_AK_EK_SIZE + SM1_SK_SIZE;
-+ } else if (ctrl.bits.sym_chn_alg_sel == HI_CIPHER_ALG_SM4) {
-+ status[i].klen = SM4_KEY_SIZE;
-+ } else {
-+ status[i].klen = 0;
-+ }
-+
-+ if (ctrl.bits.sym_chn_key_sel) {
-+ status[i].ksrc = "HW";
-+ } else {
-+ status[i].ksrc = "SW";
-+ }
-+
-+ /* get data in */
-+ if (0 != i) {
-+ addr = CHANn_CIPHER_IN_BUF_RPTR(i);
-+ status[i].inaddr = SYMC_READ(addr);
-+ } else {
-+ status[0].inaddr = CHAN0_CIPHER_DIN;
-+ }
-+
-+ /* get data out */
-+ if (0 != i) {
-+ addr = CHANn_CIPHER_OUT_BUF_RPTR(i);
-+ status[i].outaddr = SYMC_READ(addr);
-+ } else {
-+ status[0].outaddr = CHAN0_CIPHER_DOUT;
-+ }
-+
-+ for (j = 0; j < 4; j++) {
-+ val = SYMC_READ(CHANn_CIPHER_IVOUT(i) + j * 4);
-+ hex2str(status[i].iv + j * 8, (hi_u8)(val & 0xFF));
-+ hex2str(status[i].iv + j * 8 + 2, (hi_u8)((val >> 8) & 0xFF));
-+ hex2str(status[i].iv + j * 8 + 4, (hi_u8)((val >> 16) & 0xFF));
-+ hex2str(status[i].iv + j * 8 + 6, (hi_u8)((val >> 24) & 0xFF));
++ for (j = 0; j < WORD_WIDTH; j++) {
++ val = symc_read(chann_cipher_ivout(i) + j * WORD_WIDTH);
++ hex2str(status[i].iv + j * BYTE_BITS, 2, (hi_u8)(val & MAX_LOW_8BITS)); /* 2byte */
++ hex2str(status[i].iv + j * BYTE_BITS + 2, 2, (hi_u8)((val >> SHIFT_8BITS) & MAX_LOW_8BITS)); /* 2, 2byte */
++ hex2str(status[i].iv + j * BYTE_BITS + 4, 2, (hi_u8)((val >> SHIFT_16BITS) & MAX_LOW_8BITS)); /* 4, 2byte */
++ hex2str(status[i].iv + j * BYTE_BITS + 6, 2, (hi_u8)((val >> SHIFT_24BITS) & MAX_LOW_8BITS)); /* 6, 2byte */
+ }
+
+ /* get INT RAW status */
-+ stIntRaw.u32 = SYMC_READ(CIPHER_INT_RAW);
++ stIntRaw.u32 = symc_read(CIPHER_INT_RAW);
+ status[i].inraw = (stIntRaw.bits.cipher_chn_ibuf_raw >> i) & 0x1;
+ status[i].outraw = (stIntRaw.bits.cipher_chn_obuf_raw >> i) & 0x1;
+
+ /* get INT EN status */
-+ stIntEn.u32 = SYMC_READ(CIPHER_INT_EN);
++ stIntEn.u32 = symc_read(CIPHER_INT_EN);
+ status[i].intswitch = stIntEn.bits.cipher_nsec_int_en;
+ status[i].inten = (stIntEn.bits.cipher_chn_ibuf_en >> i) & 0x1;
+ status[i].outen = (stIntEn.bits.cipher_chn_obuf_en >> i) & 0x1;
+
+ /* get INT_OINTCFG */
-+ addr = CHANn_CIPHER_IN_NODE_CFG(i);
-+ stInNode.u32 = SYMC_READ(addr);
++ addr = chann_cipher_in_node_cfg(i);
++ stInNode.u32 = symc_read(addr);
+ status[i].outintcnt = stInNode.bits.cipher_in_node_mpackage_int_level;
-+
+ }
+
+ return HI_SUCCESS;
+}
-+#endif
-+/******* proc function end ********/
++#endif /* ****** proc function end ******* */
+
-+void drv_symc_get_capacity(symc_capacity *capacity)
++hi_void drv_symc_get_capacity(symc_capacity *capacity)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* the mode depend on alg, which limit to hardware
+ * des/3des support ecb/cbc/cfb/ofb
@@ -207129,7 +276174,6 @@ index 0000000..d3bd694
+ * sm1 support ecb/cbc/cfb/ofb
+ * sm4 support ecb/cbc/ctr
+ */
-+
+ crypto_memset(capacity, sizeof(symc_capacity), 0, sizeof(symc_capacity));
+
+ /* AES */
@@ -207170,35 +276214,21 @@ index 0000000..d3bd694
+
+ /* DMA */
+ capacity->dma = CRYPTO_CAPACITY_SUPPORT;
-+
+ return;
+}
+
-+/** @}*/ /** <!-- ==== API Code end ====*/
-+
-+#endif //End of CHIP_SYMC_VER_V200
++#endif /* End of CHIP_SYMC_VER_V200 */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v200.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v200.h
new file mode 100644
-index 0000000..43d2a67
+index 0000000..69961cd
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_symc_v200.h
-@@ -0,0 +1,257 @@
+@@ -0,0 +1,229 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv symc v200.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef _DRV_SYMC_V200_H_
@@ -207206,50 +276236,46 @@ index 0000000..43d2a67
+
+#include "drv_osal_lib.h"
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+/*! hash in entry list size */
++/* hash in entry list size */
+#define SYMC_NODE_SIZE (SYMC_MAX_LIST_NUM * 32)
+
-+/*! hash in entry list size */
++/* hash in entry list size */
+#define SYMC_NODE_LIST_SIZE (SYMC_NODE_SIZE * 2 * CIPHER_HARD_CHANNEL_CNT)
+
-+/*! \Define the offset of reg */
-+#define CHANn_CIPHER_IVOUT(id) (0x0000 + (id)*0x10)
-+#define CHAN0_CIPHER_DOUT (0x0080)
-+#define CIPHER_KEY(id) (0x0100 + (id)*0x20)
-+#define SM1_SK(id) (0x0200 + (id)*0x10)
-+#define ODD_EVEN_KEY_SEL (0x0290)
-+#define HDCP_MODE_CTRL (0x0300)
-+#define SEC_CHN_CFG (0x0304)
-+#define CALC_ERR (0x0320)
-+#define CHAN0_CIPHER_CTRL (0x0400)
-+#define CIPHER_INT_STATUS (0x0404)
-+#define CIPHER_INT_EN (0x0408)
-+#define CIPHER_INT_RAW (0x040c)
-+#define CIPHER_IN_SMMU_EN (0x0410)
-+#define OUT_SMMU_EN (0x0414)
-+#define CHAN0_CIPHER_DIN (0x0420)
-+#define NORM_SMMU_START_ADDR (0x0440)
-+#define SEC_SMMU_START_ADDR (0x0444)
-+#define CHANn_CIPHER_CTRL(id) (0x0400 + (id)*0x80)
-+#define CHANn_CIPHER_IN_NODE_CFG(id) (0x0404 + (id)*0x80)
-+#define CHANn_CIPHER_IN_NODE_START_ADDR(id) (0x0408 + (id)*0x80)
-+#define CHANn_CIPHER_IN_BUF_RPTR(id) (0x040C + (id)*0x80)
-+#define CHANn_CIPHER_OUT_NODE_CFG(id) (0x0430 + (id)*0x80)
-+#define CHANn_CIPHER_OUT_NODE_START_ADDR(id) (0x0434 + (id)*0x80)
-+#define CHANn_CIPHER_OUT_BUF_RPTR(id) (0x0438 + (id)*0x80)
-+#define CHANN_CIPHER_IN_NODE_START_HIGH(id) (0x0460 + (id)*0x80)
-+#define CHANN_CIPHER_OUT_NODE_START_HIGH(id) (0x0470 + (id)*0x80)
-+#define HASH_INT_STATUS (0x0804)
-+#define CHN_WHO_USED_REE (0x0390)
-+#define CHN_WHO_USED_TEE (0x0394)
-+#define SYMC_CHN_MASK(id) (0x01 << (id))
++/* Define the offset of reg */
++#define chann_cipher_ivout(id) (0x0000 + (id) * 0x10)
++#define CHAN0_CIPHER_DOUT 0x0080
++#define cipher_key(id) (0x0100 + (id) * 0x20)
++#define sm1_sk(id) (0x0200 + (id) * 0x10)
++#define ODD_EVEN_KEY_SEL 0x0290
++#define HDCP_MODE_CTRL 0x0300
++#define SEC_CHN_CFG 0x0304
++#define CALC_ERR 0x0320
++#define CHAN0_CIPHER_CTRL 0x0400
++#define CIPHER_INT_STATUS 0x0404
++#define CIPHER_INT_EN 0x0408
++#define CIPHER_INT_RAW 0x040c
++#define CIPHER_IN_SMMU_EN 0x0410
++#define OUT_SMMU_EN 0x0414
++#define CHAN0_CIPHER_DIN 0x0420
++#define NORM_SMMU_START_ADDR 0x0440
++#define SEC_SMMU_START_ADDR 0x0444
++#define chann_cipher_ctrl(id) (0x0400 + (id) * 0x80)
++#define chann_cipher_in_node_cfg(id) (0x0404 + (id) * 0x80)
++#define chann_cipher_in_node_start_addr(id) (0x0408 + (id) * 0x80)
++#define chann_cipher_in_buf_rptr(id) (0x040C + (id) * 0x80)
++#define chann_cipher_out_node_cfg(id) (0x0430 + (id) * 0x80)
++#define chann_cipher_out_node_start_addr(id) (0x0434 + (id) * 0x80)
++#define chann_cipher_out_buf_rptr(id) (0x0438 + (id) * 0x80)
++#define chann_cipher_in_node_start_high(id) (0x0460 + (id) * 0x80)
++#define chann_cipher_out_node_start_high(id) (0x0470 + (id) * 0x80)
++#define HASH_INT_STATUS 0x0804
++#define CHN_WHO_USED_REE 0x0390
++#define CHN_WHO_USED_TEE 0x0394
++#define symc_chn_mask(id) (0x01 << (id))
+
+/* reducing power dissipation */
-+#define SPACC_CALC_CRG_CFG (0x039C)
++#define SPACC_CALC_CRG_CFG 0x039C
+
+/* Define the union cal_crg_cfg */
+typedef union {
@@ -207264,7 +276290,6 @@ index 0000000..43d2a67
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} cal_crg_cfg;
+
+/* Define the union sec_chn_cfg */
@@ -207272,7 +276297,7 @@ index 0000000..43d2a67
+ /* Define the struct bits */
+ struct {
+ hi_u32 cipher_sec_chn_cfg : 8 ; /* [7..0] */
-+ hi_u32 cipher_sec_chn_cfg_lock : 1 ; /* [8] */
++ hi_u32 cipher_sec_chn_cfg_lock : 1 ; /* [8] */
+ hi_u32 reserved_0 : 7 ; /* [15..9] */
+ hi_u32 hash_sec_chn_cfg : 8 ; /* [23..16] */
+ hi_u32 hash_sec_chn_cfg_lock : 1 ; /* [24] */
@@ -207281,7 +276306,6 @@ index 0000000..43d2a67
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} sec_chn_cfg;
+
+/* Define the union cipher_int_status */
@@ -207296,7 +276320,6 @@ index 0000000..43d2a67
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} cipher_int_status;
+
+/* Define the union cipher_int_en */
@@ -207313,7 +276336,6 @@ index 0000000..43d2a67
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} cipher_int_en;
+
+/* Define the union cipher_int_raw */
@@ -207328,7 +276350,6 @@ index 0000000..43d2a67
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} cipher_int_raw;
+
+/* Define the union hash_int_status */
@@ -207342,62 +276363,58 @@ index 0000000..43d2a67
+
+ /* Define an unsigned member */
+ unsigned int u32;
-+
+} hash_int_status;
+
+/* Define the union cipher_in_smmu_en */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ hi_u32 cipher_in_chan_rd_dat_smmu_en : 7 ; /* [6..0] */
-+ hi_u32 reserved_0 : 9 ; /* [15..7] */
-+ hi_u32 cipher_in_chan_rd_node_smmu_en : 7 ; /* [22..16] */
-+ hi_u32 reserved_1 : 9 ; /* [31..23] */
++ hi_u32 cipher_in_chan_rd_dat_smmu_en : 7 ; /* [6..0] */
++ hi_u32 reserved_0 : 9 ; /* [15..7] */
++ hi_u32 cipher_in_chan_rd_node_smmu_en : 7 ; /* [22..16] */
++ hi_u32 reserved_1 : 9 ; /* [31..23] */
+ } bits;
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} cipher_in_smmu_en;
+
+/* Define the union out_smmu_en */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ hi_u32 out_chan_wr_dat_smmu_en : 7 ; /* [6..0] */
-+ hi_u32 reserved_0 : 9 ; /* [15..7] */
-+ hi_u32 out_chan_rd_node_smmu_en : 7 ; /* [22..16] */
-+ hi_u32 reserved_1 : 9 ; /* [31..23] */
++ hi_u32 out_chan_wr_dat_smmu_en : 7 ; /* [6..0] */
++ hi_u32 reserved_0 : 9 ; /* [15..7] */
++ hi_u32 out_chan_rd_node_smmu_en : 7 ; /* [22..16] */
++ hi_u32 reserved_1 : 9 ; /* [31..23] */
+ } bits;
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} out_smmu_en;
+
+/* Define the union chann_chipher_ctrl */
+typedef union {
+ /* Define the struct bits */
+ struct {
-+ hi_u32 reserved_0 : 1 ; /* [0] */
-+ hi_u32 sym_chn_alg_mode : 3 ; /* [3..1] */
-+ hi_u32 sym_chn_alg_sel : 3 ; /* [6..4] */
-+ hi_u32 sym_chn_decrypt : 1 ; /* [7] */
-+ hi_u32 sym_chn_dat_width : 2 ; /* [9..8] */
-+ hi_u32 sym_chn_key_length : 2 ; /* [11..10] */
-+ hi_u32 reserved_1 : 2 ; /* [13..12] */
-+ hi_u32 sym_chn_key_sel : 1 ; /* [14] */
-+ hi_u32 reserved_2 : 1 ; /* [15] */
++ hi_u32 reserved_0 : 1 ; /* [0] */
++ hi_u32 sym_chn_alg_mode : 3 ; /* [3..1] */
++ hi_u32 sym_chn_alg_sel : 3 ; /* [6..4] */
++ hi_u32 sym_chn_decrypt : 1 ; /* [7] */
++ hi_u32 sym_chn_dat_width : 2 ; /* [9..8] */
++ hi_u32 sym_chn_key_length : 2 ; /* [11..10] */
++ hi_u32 reserved_1 : 2 ; /* [13..12] */
++ hi_u32 sym_chn_key_sel : 1 ; /* [14] */
++ hi_u32 reserved_2 : 1 ; /* [15] */
+ hi_u32 sym_chn_dout_byte_swap_en : 1 ; /* [16] */
-+ hi_u32 sym_chn_din_byte_swap_en : 1 ; /* [17] */
-+ hi_u32 sym_chn_sm1_round_num : 2 ; /* [19..18] */
-+ hi_u32 reserved_3 : 2 ; /* [21..20] */
-+ hi_u32 weight : 10 ; /* [31..22] */
++ hi_u32 sym_chn_din_byte_swap_en : 1 ; /* [17] */
++ hi_u32 sym_chn_sm1_round_num : 2 ; /* [19..18] */
++ hi_u32 reserved_3 : 2 ; /* [21..20] */
++ hi_u32 weight : 10 ; /* [31..22] */
+ } bits;
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} chann_chipher_ctrl;
+
+/* Define the union chann_cipher_in_node_cfg */
@@ -207405,18 +276422,17 @@ index 0000000..43d2a67
+ /* Define the struct bits */
+ struct {
+ hi_u32 cipher_in_node_mpackage_int_level : 7 ; /* [6..0] */
-+ hi_u32 reserved_0 : 1 ; /* [7] */
-+ hi_u32 cipher_in_node_rptr : 7 ; /* [14..8] */
-+ hi_u32 reserved_1 : 1 ; /* [15] */
-+ hi_u32 cipher_in_node_wptr : 7 ; /* [22..16] */
-+ hi_u32 reserved_2 : 1 ; /* [23] */
-+ hi_u32 cipher_in_node_total_num : 7 ; /* [30..24] */
-+ hi_u32 reserved_3 : 1 ; /* [31] */
++ hi_u32 reserved_0 : 1 ; /* [7] */
++ hi_u32 cipher_in_node_rptr : 7 ; /* [14..8] */
++ hi_u32 reserved_1 : 1 ; /* [15] */
++ hi_u32 cipher_in_node_wptr : 7 ; /* [22..16] */
++ hi_u32 reserved_2 : 1 ; /* [23] */
++ hi_u32 cipher_in_node_total_num : 7 ; /* [30..24] */
++ hi_u32 reserved_3 : 1 ; /* [31] */
+ } bits;
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} chann_cipher_in_node_cfg;
+
+/* Define the union chann_cipher_out_node_cfg */
@@ -207424,44 +276440,30 @@ index 0000000..43d2a67
+ /* Define the struct bits */
+ struct {
+ hi_u32 cipher_out_node_mpackage_int_level : 7 ; /* [6..0] */
-+ hi_u32 reserved_0 : 1 ; /* [7] */
-+ hi_u32 cipher_out_node_rptr : 7 ; /* [14..8] */
-+ hi_u32 reserved_1 : 1 ; /* [15] */
-+ hi_u32 cipher_out_node_wptr : 7 ; /* [22..16] */
-+ hi_u32 reserved_2 : 1 ; /* [23] */
-+ hi_u32 cipher_out_node_total_num : 7 ; /* [30..24] */
-+ hi_u32 reserved_3 : 1 ; /* [31] */
++ hi_u32 reserved_0 : 1 ; /* [7] */
++ hi_u32 cipher_out_node_rptr : 7 ; /* [14..8] */
++ hi_u32 reserved_1 : 1 ; /* [15] */
++ hi_u32 cipher_out_node_wptr : 7 ; /* [22..16] */
++ hi_u32 reserved_2 : 1 ; /* [23] */
++ hi_u32 cipher_out_node_total_num : 7 ; /* [30..24] */
++ hi_u32 reserved_3 : 1 ; /* [31] */
+ } bits;
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} chann_cipher_out_node_cfg;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v100.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v100.c
new file mode 100644
-index 0000000..cbec5a5
+index 0000000..b972ecc
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v100.c
-@@ -0,0 +1,108 @@
+@@ -0,0 +1,98 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv trng v100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_trng_v100.h"
@@ -207469,22 +276471,14 @@ index 0000000..cbec5a5
+
+#ifdef CHIP_TRNG_VER_V100
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+/*! Define the post process depth */
++/* ************************** Internal Structure Definition *************************** */
++/* Define the post process depth */
+#define TRNG_POST_PROCESS_DEPTH 0x10
+
-+/*! Define the osc sel */
++/* Define the osc sel */
+#define TRNG_OSC_SEL 0x02
+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
-+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup hdcp */
-+/** @{ */ /** <!--[hdcp]*/
-+
++/* ****************************** API Declaration **************************** */
+hi_s32 drv_trng_randnum(hi_u32 *randnum, hi_u32 timeout)
+{
+ rng_stat stat;
@@ -207492,36 +276486,35 @@ index 0000000..cbec5a5
+ hi_u32 times = 0;
+ static hi_u32 last = 0x1082;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(randnum == HI_NULL);
++ hi_log_chk_param_return(randnum == HI_NULL);
+
+ if (ctrl.u32 != last) {
+ module_enable(CRYPTO_MODULE_ID_TRNG);
+
-+ ctrl.u32 = TRNG_READ(RNG_CTRL);
++ ctrl.u32 = trng_read(RNG_CTRL);
+ ctrl.bits.filter_enable = 0x00;
+ ctrl.bits.mix_en = 0x00;
+ ctrl.bits.drop_enable = 0x00;
+ ctrl.bits.post_process_enable = 0x01;
+ ctrl.bits.post_process_depth = TRNG_POST_PROCESS_DEPTH;
+ ctrl.bits.osc_sel = TRNG_OSC_SEL;
-+ TRNG_WRITE(RNG_CTRL, ctrl.u32);
++ trng_write(RNG_CTRL, ctrl.u32);
+ }
+
+#if defined(HI_PLATFORM_TYPE_LINUX)
+ if (timeout == 0) { /* unblock */
+ /* trng number is valid ? */
-+ stat.u32 = TRNG_READ(RNG_STAT);
++ stat.u32 = trng_read(RNG_STAT);
+ if (stat.bits.rng_data_count == 0x00) {
+ return HI_ERR_CIPHER_NO_AVAILABLE_RNG;
+ }
-+ } else /* block */
-+#endif
-+ {
++ } else {
++ /* block */
+ while (times++ < TRNG_TIMEOUT) {
+ /* trng number is valid ? */
-+ stat.u32 = TRNG_READ(RNG_STAT);
++ stat.u32 = trng_read(RNG_STAT);
+ if (stat.bits.rng_data_count > 0x00) {
+ break;
+ }
@@ -207532,13 +276525,26 @@ index 0000000..cbec5a5
+ return HI_ERR_CIPHER_NO_AVAILABLE_RNG;
+ }
+ }
++#else
++ while (times++ < TRNG_TIMEOUT) {
++ /* trng number is valid ? */
++ stat.u32 = trng_read(RNG_STAT);
++ if (stat.bits.rng_data_count > 0x00) {
++ break;
++ }
++ }
+
++ /* time out */
++ if (times >= TRNG_TIMEOUT) {
++ return HI_ERR_CIPHER_NO_AVAILABLE_RNG;
++ }
++#endif
+ /* read valid randnum */
-+ *randnum = TRNG_READ(RNG_FIFO_DATA);
++ *randnum = trng_read(RNG_FIFO_DATA);
+
-+ HI_LOG_INFO("randnum: 0x%x\n", *randnum);
++ hi_log_info("randnum: 0x%x\n", *randnum);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -207550,32 +276556,18 @@ index 0000000..cbec5a5
+
+ return;
+}
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
-+#endif //End of CHIP_TRNG_VER_V100
++#endif /* End of CHIP_TRNG_VER_V100 */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v100.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v100.h
new file mode 100644
-index 0000000..3d26b76
+index 0000000..d21de21
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v100.h
-@@ -0,0 +1,73 @@
+@@ -0,0 +1,54 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv trng v100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef _DRV_HDCP_V100_H_
@@ -207583,16 +276575,12 @@ index 0000000..3d26b76
+
+#include "drv_osal_lib.h"
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
++/* Define the offset of reg */
++#define RNG_CTRL 0x0000
++#define RNG_FIFO_DATA 0x0004
++#define RNG_STAT 0x0008
+
-+/*! \Define the offset of reg */
-+#define RNG_CTRL (0x0000)
-+#define RNG_FIFO_DATA (0x0004)
-+#define RNG_STAT (0x0008)
-+
-+#define TRNG_TIMEOUT (0x10000000)
++#define TRNG_TIMEOUT 0x10000000
+
+/* Define the union rng_ctrl */
+typedef union {
@@ -207614,7 +276602,6 @@ index 0000000..3d26b76
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} rng_ctrl;
+
+/* Define the union rng_stat */
@@ -207628,33 +276615,19 @@ index 0000000..3d26b76
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} rng_stat;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v200.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v200.c
new file mode 100644
-index 0000000..4f3b6bf
+index 0000000..ce57d01
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v200.c
-@@ -0,0 +1,103 @@
+@@ -0,0 +1,80 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv trng v200.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_trng_v200.h"
@@ -207662,19 +276635,10 @@ index 0000000..4f3b6bf
+
+#ifdef CHIP_TRNG_VER_V200
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+/*! Define the osc sel */
++/* ************************** Internal Structure Definition *************************** */
++/* Define the osc sel */
+#define TRNG_OSC_SEL 0x02
-+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
-+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup trng */
-+/** @{ */ /** <!--[trng]*/
-+
++/* ****************************** API Declaration **************************** */
+hi_s32 drv_trng_randnum(hi_u32 *randnum, hi_u32 timeout)
+{
+ hisec_com_trng_data_st stat;
@@ -207682,11 +276646,11 @@ index 0000000..4f3b6bf
+ static hi_u32 last = 0x0A;
+ hi_u32 times = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(randnum == HI_NULL);
++ hi_log_chk_param_return(randnum == HI_NULL);
+
-+ ctrl.u32 = TRNG_READ(HISEC_COM_TRNG_CTRL);
++ ctrl.u32 = trng_read(HISEC_COM_TRNG_CTRL);
+ if (ctrl.u32 != last) {
+ module_enable(CRYPTO_MODULE_ID_TRNG);
+
@@ -207697,21 +276661,21 @@ index 0000000..4f3b6bf
+ ctrl.bits.post_process_depth = 0x00;
+ ctrl.bits.drbg_enable = 0x01;
+ ctrl.bits.osc_sel = TRNG_OSC_SEL;
-+ TRNG_WRITE(HISEC_COM_TRNG_CTRL, ctrl.u32);
++ trng_write(HISEC_COM_TRNG_CTRL, ctrl.u32);
+ last = ctrl.u32;
+ }
+
+ if (timeout == 0) { /* unblock */
+ /* trng number is valid ? */
-+ stat.u32 = TRNG_READ(HISEC_COM_TRNG_DATA_ST);
-+ if (0x00 == stat.bits.trng_fifo_data_cnt) {
++ stat.u32 = trng_read(HISEC_COM_TRNG_DATA_ST);
++ if (stat.bits.trng_fifo_data_cnt == 0) {
+ return HI_ERR_CIPHER_NO_AVAILABLE_RNG;
+ }
+ } else { /* block */
+ while (times++ < timeout) {
+ /* trng number is valid ? */
-+ stat.u32 = TRNG_READ(HISEC_COM_TRNG_DATA_ST);
-+ if (0x00 < stat.bits.trng_fifo_data_cnt) {
++ stat.u32 = trng_read(HISEC_COM_TRNG_DATA_ST);
++ if (stat.bits.trng_fifo_data_cnt > 0) {
+ break;
+ }
+ }
@@ -207723,10 +276687,10 @@ index 0000000..4f3b6bf
+ }
+
+ /* read valid randnum */
-+ *randnum = TRNG_READ(HISEC_COM_TRNG_FIFO_DATA);
-+ HI_LOG_INFO("randnum: 0x%x\n", *randnum);
++ *randnum = trng_read(HISEC_COM_TRNG_FIFO_DATA);
++ hi_log_info("randnum: 0x%x\n", *randnum);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -207738,32 +276702,18 @@ index 0000000..4f3b6bf
+
+ return;
+}
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
-+#endif //End of CHIP_TRNG_VER_V200
++#endif /* End of CHIP_TRNG_VER_V200 */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v200.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v200.h
new file mode 100644
-index 0000000..464688b
+index 0000000..e7dfe50
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/drv_trng_v200.h
-@@ -0,0 +1,79 @@
+@@ -0,0 +1,57 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv trng v200.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef _DRV_TRNG_V200_H_
@@ -207771,14 +276721,11 @@ index 0000000..464688b
+
+#include "drv_osal_lib.h"
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup trng drivers*/
-+/** @{*/ /** <!-- [trng]*/
-+
-+/*! \Define the offset of reg */
-+#define HISEC_COM_TRNG_CTRL (0x00)
-+#define HISEC_COM_TRNG_FIFO_DATA (0x04)
-+#define HISEC_COM_TRNG_DATA_ST (0x08)
++/* ************************** Internal Structure Definition *************************** */
++/* Define the offset of reg */
++#define HISEC_COM_TRNG_CTRL 0x00
++#define HISEC_COM_TRNG_FIFO_DATA 0x04
++#define HISEC_COM_TRNG_DATA_ST 0x08
+
+/* Define the union hisec_com_trng_ctrl */
+typedef union {
@@ -207792,16 +276739,14 @@ index 0000000..464688b
+ hi_u32 mix_enable : 1; /* [6] */
+ hi_u32 post_process_enable: 1; /* [7] */
+ hi_u32 post_process_depth : 8; /* [15..8] */
-+ hi_u32 reserved0 : 1; /* [16] */
-+ hi_u32 trng_sel : 2; /* [18..17] */
-+ hi_u32 pos_self_test_en : 1; /* [19] */
-+ hi_u32 pre_self_test_en : 1; /* [20] */
-+ hi_u32 reserved1 : 11; /* [31..21] */
++ hi_u32 trng_sel : 1; /* [16] */
++ hi_u32 reserved0 : 2; /* [18..17] */
++ hi_u32 alarm_clr : 1; /* [19] */
++ hi_u32 reserved1 : 12; /* [31..20] */
+ } bits;
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} hisec_com_trng_ctrl;
+
+/* Define the union hisec_com_trng_data_st */
@@ -207812,182 +276757,136 @@ index 0000000..464688b
+ hi_u32 low_osc_st1 : 1; /* [1] */
+ hi_u32 low_ro_st0 : 1; /* [2] */
+ hi_u32 low_ro_st1 : 1; /* [3] */
-+ hi_u32 otp_trng_sel : 1; /* [4] */
-+ hi_u32 reserved0 : 3; /* [7..5] */
-+ hi_u32 trng_fifo_data_cnt : 8; /* [15..8] */
-+ hi_u32 sic_trng_alarm : 6; /* [21..16] */
-+ hi_u32 sic_trng_bist_alarm: 1; /* [22] */
-+ hi_u32 reserved1 : 9; /* [31..23] */
++ hi_u32 reserved0 : 4; /* [7..4] */
++ hi_u32 trng_fifo_data_cnt : 6; /* [13..8] */
++ hi_u32 reserved1 : 18; /* [31..14] */
+ } bits;
+
+ /* Define an unsigned member */
+ hi_u32 u32;
-+
+} hisec_com_trng_data_st;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+#endif
++#endif /* End of _DRV_TRNG_V200_H_ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_hash.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_hash.h
new file mode 100644
-index 0000000..3482b26
+index 0000000..5c49c54
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_hash.h
-@@ -0,0 +1,133 @@
+@@ -0,0 +1,104 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file drv hash.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_HASH_H__
+#define __DRV_HASH_H__
+
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!-- [hash] */
++#include "drv_osal_lib.h"
+
-+/*! \hash block size */
-+#define HASH_BLOCK_SIZE_64 (64) /* SHA1, SHA224, SHA256 */
-+#define HASH_BLOCK_SIZE_128 (128) /* SHA384, SHA512 */
++/* SHA1, SHA224, SHA256 hash block size */
++#define HASH_BLOCK_SIZE_64 64
++/* SHA384, SHA512 hash block size. */
++#define HASH_BLOCK_SIZE_128 128
+
-+/*! \hash capacity, 0-nonsupport, 1-support */
++/* hash capacity, 0-nonsupport, 1-support */
+typedef struct {
-+ hi_u32 sha1 : 1 ; /*!< Support SHA1 */
-+ hi_u32 sha224 : 1 ; /*!< Support SHA224 */
-+ hi_u32 sha256 : 1 ; /*!< Support SHA256 */
-+ hi_u32 sha384 : 1 ; /*!< Support SHA384 */
-+ hi_u32 sha512 : 1 ; /*!< Support SHA512 */
-+ hi_u32 sm3 : 1 ; /*!< Support SM3 */
++ hi_u32 sha1 : 1 ; /* Support SHA1 */
++ hi_u32 sha224 : 1 ; /* Support SHA224 */
++ hi_u32 sha256 : 1 ; /* Support SHA256 */
++ hi_u32 sha384 : 1 ; /* Support SHA384 */
++ hi_u32 sha512 : 1 ; /* Support SHA512 */
++ hi_u32 sm3 : 1 ; /* Support SM3 */
+} hash_capacity;
+
-+/*! \hash mode */
++/* hash mode */
+typedef enum {
-+ HASH_MODE_SHA1, /*!< SHA1 */
-+ HASH_MODE_SHA224, /*!< SHA2 224 */
-+ HASH_MODE_SHA256, /*!< SHA2 256 */
-+ HASH_MODE_SHA384, /*!< SHA2 384 */
-+ HASH_MODE_SHA512, /*!< SHA2 512 */
-+ HASH_MODE_SM3, /*!< SM3 */
++ HASH_MODE_SHA1, /* SHA1 */
++ HASH_MODE_SHA224, /* SHA2 224 */
++ HASH_MODE_SHA256, /* SHA2 256 */
++ HASH_MODE_SHA384, /* SHA2 384 */
++ HASH_MODE_SHA512, /* SHA2 512 */
++ HASH_MODE_SM3, /* SM3 */
+ HASH_MODE_COUNT,
+} hash_mode;
+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
-+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!--[hash]*/
-+
-+
-+/**
-+\brief Initialize the hash module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/* ****************************** API Declaration **************************** */
++/*
++ * \brief Initialize the hash module.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_hash_init(void);
+
-+/**
-+\brief Deinitialize the hash module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief Deinitialize the hash module.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_hash_deinit(void);
+
-+/**
-+\brief suspend the hash module.
-+\retval NA.
-+*/
++/*
++ * \brief suspend the hash module.
++ * \retval NA.
++ */
+void drv_hash_suspend(void);
+
-+/**
-+\brief resume the hash module.
-+\retval NA.
-+*/
++/*
++ * \brief resume the hash module.
++ * \retval NA.
++ */
+void drv_hash_resume(void);
+
-+/**
-+\brief set work params.
-+\param[in] chn_num The channel number.
-+\param[in] mode The hash mode.
-+\param[in] state The hash initial result.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_hash_config(hi_u32 chn_num, hash_mode mode, hi_u32 state[HASH_RESULT_MAX_SIZE_IN_WORD]);
++/*
++ * \brief set work params.
++ * \param[in] chn_num The channel number.
++ * \param[in] mode The hash mode.
++ * \param[in] state The hash initial result, length is HASH_RESULT_MAX_SIZE_IN_WORD.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_hash_cfg(hi_u32 chn_num, hash_mode mode, hi_u32 *state);
+
-+/**
-+\brief start hash calculation.
-+\param[in] chn_num The channel number.
-+\param[in] buf_phy The MMZ/SMMU address of in buffer.
-+\param[in] buf_size The MMZ/SMMU siae of in buffer.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief start hash calculation.
++ * \param[in] chn_num The channel number.
++ * \param[in] buf_phy The MMZ/SMMU address of in buffer.
++ * \param[in] buf_size The MMZ/SMMU siae of in buffer.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_hash_start(hi_u32 chn_num, crypto_mem *mem, hi_u32 buf_size);
+
-+/**
-+\brief wait running finished.
-+\param[in] chn_num The channel number.
-+\param[out] state The hash result.
-+\param[in] hashLen The length of hash result.
-+\retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
++/*
++ * \brief wait running finished.
++ * \param[in] chn_num The channel number.
++ * \param[out] state The hash result.
++ * \param[in] hashLen The length of hash result.
++ * \retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
++ */
+hi_s32 drv_hash_wait_done(hi_u32 chn_num, hi_u32 *state);
+
-+/**
-+\brief reset hash after hash finished.
-+\param[in] chn_num The channel number.
-+\retval NA.
-+*/
++/*
++ * \brief reset hash after hash finished.
++ * \param[in] chn_num The channel number.
++ * \retval NA.
++ */
+void drv_hash_reset(hi_u32 chn_num);
+
-+/**
-+\brief compute a block hmac.
-+\param[in] din block data.
-+\param[out] hamc The output.
-+\retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
-+hi_s32 drv_hmac256_block(hi_u32 *din, hi_u32 *hamc);
-+
-+/**
-+\brief get the hash capacity.
-+\param[out] capacity The hash capacity.
-+\retval NA.
-+*/
++/*
++ * \brief get the hash capacity.
++ * \param[out] capacity The hash capacity.
++ * \retval NA.
++ */
+void drv_hash_get_capacity(hash_capacity *capacity);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_osal_chip.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_osal_chip.h
new file mode 100644
-index 0000000..bf53736
+index 0000000..1454ed4
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_osal_chip.h
-@@ -0,0 +1,65 @@
+@@ -0,0 +1,54 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv osal cipher chip configuration.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_CHIP_H__
@@ -207999,13 +276898,13 @@ index 0000000..bf53736
+#elif defined(CHIP_TYPE_hi3559av100)
+#include "drv_osal_hi3559.h"
+
-+#elif (defined(CHIP_TYPE_hi3519av100) || defined(CHIP_TYPE_hi3556av100))
++#elif defined(CHIP_TYPE_hi3519av100)
+#include "drv_osal_hi3519av100.h"
+
-+#elif (defined(CHIP_TYPE_hi3516cv500) || defined(CHIP_TYPE_hi3516dv300) || defined(CHIP_TYPE_hi3556v200) || defined(CHIP_TYPE_hi3559v200) || defined(CHIP_TYPE_hi3516av300))
++#elif defined(CHIP_TYPE_hi3516cv500)
+#include "drv_osal_hi3516cv500.h"
+
-+#elif (defined(CHIP_TYPE_hi3516ev200) || (CHIP_TYPE_hi3516ev300) || (CHIP_TYPE_hi3518ev300) || (CHIP_TYPE_hi3516dv200))
++#elif defined(CHIP_TYPE_hi3516ev200)
+#include "drv_osal_hi3516ev200.h"
+
+#else
@@ -208039,194 +276938,163 @@ index 0000000..bf53736
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_srsa.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_srsa.h
new file mode 100644
-index 0000000..066d740
+index 0000000..df9b66e
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_srsa.h
-@@ -0,0 +1,97 @@
+@@ -0,0 +1,73 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv sec rsa.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_RSA_H__
+#define __DRV_RSA_H__
+
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup rsa */
-+/** @{ */ /** <!-- [rsa] */
-+
-+/*! Define RSA 1024 key length */
++/* ************************** Structure Definition *************************** */
++/* Define RSA 1024 key length */
+#define RSA_KEY_LEN_1024 128
+
-+/*! Define RSA 2048 key length */
++/* Define RSA 2048 key length */
+#define RSA_KEY_LEN_2048 256
+
-+/*! Define RSA 3072 key length */
++/* Define RSA 3072 key length */
+#define RSA_KEY_LEN_3072 384
+
-+/*! Define RSA 4096 key length */
++/* Define RSA 4096 key length */
+#define RSA_KEY_LEN_4096 512
+
-+/*! \rsa capacity, 0-nonsupport, 1-support */
++/* rsa capacity, 0-nonsupport, 1-support */
+typedef struct {
-+ hi_u32 rsa : 1 ; /*!< Support RSA */
++ hi_u32 rsa : 1 ; /* Support RSA */
+} rsa_capacity;
+
-+/*! \rsa key width */
++/* rsa key width */
+typedef enum {
-+ RSA_KEY_WIDTH_1024 = 0x00, /*!< RSA 1024 */
-+ RSA_KEY_WIDTH_2048, /*!< RSA 2048 */
-+ RSA_KEY_WIDTH_4096, /*!< RSA 4096 */
-+ RSA_KEY_WIDTH_3072, /*!< RSA 3072 */
++ RSA_KEY_WIDTH_1024 = 0x00, /* RSA 1024 */
++ RSA_KEY_WIDTH_2048, /* RSA 2048 */
++ RSA_KEY_WIDTH_4096, /* RSA 4096 */
++ RSA_KEY_WIDTH_3072, /* RSA 3072 */
+ RSA_KEY_WIDTH_COUNT,
+} rsa_key_width;
+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
-+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup rsa */
-+/** @{ */ /** <!--[rsa]*/
-+
-+
-+/**
-+\brief Initialize the rsa module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Initialize the rsa module.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_rsa_init(void);
+
-+/**
-+\brief Deinitialize the rsa module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Deinitialize the rsa module.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_rsa_deinit(void);
+
-+/**
-+\brief RSA encrypt/decrypt use rsa exponent-modular arithmetic.
-+\param[in] n The N of rsa key.
-+\param[in] k The d/e of rsa key.
-+\param[in] in The input data.
-+\param[out] out The input data.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief RSA encrypt/decrypt use rsa exponent-modular arithmetic.
++ * param[in] n The N of rsa key.
++ * param[in] k The d/e of rsa key.
++ * param[in] in The input data.
++ * param[out] out The input data.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_ifep_rsa_exp_mod(hi_u32 ca_type, hi_u8 *n, hi_u8 *k, hi_u8 *in, hi_u8 *out, rsa_key_width width);
+
-+/**
-+\brief get the hash capacity.
-+\param[out] capacity The hash capacity.
-+\retval NA.
-+*/
++/*
++ * brief get the hash capacity.
++ * param[out] capacity The hash capacity.
++ * retval NA.
++ */
+void drv_ifep_rsa_get_capacity(rsa_capacity *capacity);
+
-+/**
-+\brief get the hash capacity.
-+\param[out] capacity The hash capacity.
-+\retval NA.
-+*/
++/*
++ * brief get the hash capacity.
++ * param[out] capacity The hash capacity.
++ * retval NA.
++ */
+void drv_sic_rsa_get_capacity(rsa_capacity *capacity);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
-+#endif
++#endif /* End of __DRV_RSA_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_symc.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_symc.h
new file mode 100644
-index 0000000..999d703
+index 0000000..508b20a
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_symc.h
-@@ -0,0 +1,448 @@
+@@ -0,0 +1,483 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cipher drv symc.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
-+#ifndef __DRV_CIPHER_H__
-+#define __DRV_CIPHER_H__
++#ifndef __DRV_SYMC_H__
++#define __DRV_SYMC_H__
+
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup symmetric cipher */
-+/** @{ */ /** <!-- [symc] */
++#include "hi_types.h"
++#include "drv_cipher_kapi.h"
++#include "drv_osal_lib.h"
+
-+/*! \symmetric cipher max key size in words */
-+#define SYMC_KEY_MAX_SIZE_IN_WORD (8)
++/* symmetric cipher max key size in words */
++#define SYMC_KEY_MAX_SIZE_IN_WORD 8
+
-+/*! \symmetric cipher max iv size in word */
-+#define SYMC_IV_MAX_SIZE_IN_WORD (4)
++/* symmetric cipher max iv size in word */
++#define SYMC_IV_MAX_SIZE_IN_WORD 4
+
-+/*! \symmetric sm1 sk size in words */
-+#define SYMC_SM1_SK_SIZE_IN_WORD (4)
++/* symmetric sm1 sk size in words */
++#define SYMC_SM1_SK_SIZE_IN_WORD 4
+
-+/*! \DES BLOCK size */
-+#define DES_BLOCK_SIZE (8)
++/* DES BLOCK size */
++#define DES_BLOCK_SIZE 8
+
-+/*! \Numbers of nodes list */
-+#define SYMC_MAX_LIST_NUM (16)
++/* Numbers of nodes list */
++#define SYMC_MAX_LIST_NUM 16
+
-+/*! \Length of CCM N */
-+#define SYMC_CCM_N_LEN (16)
++/* Length of CCM N */
++#define SYMC_CCM_N_LEN 16
+
-+/*! \Length of CCM A head */
-+#define SYMC_CCM_A_HEAD_LEN (16)
++/* Length of CCM A head */
++#define SYMC_CCM_A_HEAD_LEN 16
+
-+/*! \Length of GCM CLEN */
-+#define SYMC_GCM_CLEN_LEN (16)
++/* Length of GCM CLEN */
++#define SYMC_GCM_CLEN_LEN 16
+
-+/*! \Small length of CCM A */
++/* Small length of CCM A */
+#define SYMC_CCM_A_SMALL_LEN (0x10000 - 0x100)
+
-+/*! \AES KEY size 128bit*/
-+#define AES_KEY_128BIT (16)
++/* If 2^16 - 2^8 <= a < 2^32, then a is encoded as 0xff || 0xfe || a[0..31], i.e., six octets. */
++#define SYMC_AAD_PAD_VAL_FF 0xFF
++#define SYMC_AAD_PAD_VAL_FE 0xFE
+
-+/*! \AES KEY size 192bit*/
-+#define AES_KEY_192BIT (24)
++/* AES KEY size 128bit */
++#define AES_KEY_128BIT 16
+
-+/*! \AES KEY size 256bit*/
-+#define AES_KEY_256BIT (32)
++/* AES KEY size 192bit */
++#define AES_KEY_192BIT 24
+
-+/*! \DES KEY size 128bit*/
-+#define DES_KEY_SIZE (8)
++/* AES KEY size 256bit */
++#define AES_KEY_256BIT 32
+
-+/*! \TDES KEY size 128bit*/
-+#define TDES_KEY_128BIT (16)
++/* DES KEY size 128bit */
++#define DES_KEY_SIZE 8
+
-+/*! \TDES KEY size 192bit*/
-+#define TDES_KEY_192BIT (24)
++/* TDES KEY size 128bit */
++#define TDES_KEY_128BIT 16
+
-+/*! \DES block size*/
-+#define DES_BLOCK_SIZE (8)
++/* TDES KEY size 192bit */
++#define TDES_KEY_192BIT 24
+
-+/*! \SM1 KEY size */
-+#define SM1_AK_EK_SIZE (32)
-+#define SM1_SK_SIZE (16)
++/* DES block size */
++#define DES_BLOCK_SIZE 8
+
-+/*! \SM4 KEY size */
-+#define SM4_KEY_SIZE (16)
++/* SM1 KEY size */
++#define SM1_AK_EK_SIZE 32
++#define SM1_SK_SIZE 16
+
-+/*! \symmetric cipher width */
++/* SM4 KEY size */
++#define SM4_KEY_SIZE 16
++
++/* symmetric cipher width */
+typedef enum {
+ SYMC_DAT_WIDTH_128 = 0,
+ SYMC_DAT_WIDTH_8,
@@ -208235,69 +277103,69 @@ index 0000000..999d703
+ SYMC_DAT_WIDTH_COUNT,
+} symc_width;
+
-+/*! \symmetric cipher algorithm */
++/* symmetric cipher algorithm */
+typedef enum {
-+ SYMC_ALG_DES, /*!< Data Encryption Standard */
-+ SYMC_ALG_TDES, /*!< Triple Data Encryption Standard */
-+ SYMC_ALG_AES, /*!< Advanced Encryption Standard */
-+ SYMC_ALG_SM4, /*!< SM4 Algorithm */
-+ SYMC_ALG_SM1, /*!< SM1 Algorithm */
-+ SYMC_ALG_NULL_CIPHER, /*!< null cipher, dma copy */
++ SYMC_ALG_DES, /* Data Encryption Standard */
++ SYMC_ALG_TDES, /* Triple Data Encryption Standard */
++ SYMC_ALG_AES, /* Advanced Encryption Standard */
++ SYMC_ALG_SM4, /* SM4 Algorithm */
++ SYMC_ALG_SM1, /* SM1 Algorithm */
++ SYMC_ALG_NULL_CIPHER, /* null cipher, dma copy */
+ SYMC_ALG_COUNT,
+} symc_alg;
+
-+/*! \symmetric cipher key length */
++/* symmetric cipher key length */
+typedef enum {
-+ SYMC_KEY_DEFAULT = 0, /*!< Default, aes-128, 3des-192, sm1-256, sm4-128 */
-+ SYMC_KEY_AES_192BIT, /*!< AES 192 bit key */
-+ SYMC_KEY_AES_256BIT, /*!< AES 256 bit key */
-+ SYMC_KEY_TDES_2KEY, /*!< 3DES 128 bit key */
++ SYMC_KEY_DEFAULT = 0, /* Default, aes-128, 3des-192, sm1-256, sm4-128 */
++ SYMC_KEY_AES_192BIT, /* AES 192 bit key */
++ SYMC_KEY_AES_256BIT, /* AES 256 bit key */
++ SYMC_KEY_TDES_2KEY, /* 3DES 128 bit key */
+ SYMC_KEY_LEN_COUNT,
+} symc_klen;
+
-+/*! \symmetric cipher mode */
++/* symmetric cipher mode */
+typedef enum {
-+ SYMC_MODE_ECB = 0, /*!< Electronic Codebook Mode */
-+ SYMC_MODE_CBC, /*!< Cipher Block Chaining */
-+ SYMC_MODE_CFB, /*!< Cipher Feedback Mode */
-+ SYMC_MODE_OFB, /*!< Output Feedback Mode */
-+ SYMC_MODE_CTR, /*!< Counter Mode */
-+ SYMC_MODE_CCM, /*!< Counter with Cipher Block Chaining-Message Authentication Code */
-+ SYMC_MODE_GCM, /*!< Galois/Counter Mode */
-+ SYMC_MODE_CTS, /*!< CTS Mode */
++ SYMC_MODE_ECB = 0, /* Electronic Codebook Mode */
++ SYMC_MODE_CBC, /* Cipher Block Chaining */
++ SYMC_MODE_CFB, /* Cipher Feedback Mode */
++ SYMC_MODE_OFB, /* Output Feedback Mode */
++ SYMC_MODE_CTR, /* Counter Mode */
++ SYMC_MODE_CCM, /* Counter with Cipher Block Chaining-Message Authentication Code */
++ SYMC_MODE_GCM, /* Galois/Counter Mode */
++ SYMC_MODE_CTS, /* CTS Mode */
+ SYMC_MODE_COUNT,
+} symc_mode;
+
-+/*! \locational of buffer under symmetric cipher */
++/* locational of buffer under symmetric cipher */
+typedef enum {
-+ SYMC_NODE_USAGE_NORMAL = 0x00, /*!< The normal buffer, don't update the iv */
-+ SYMC_NODE_USAGE_FIRST = 0x01, /*!< The first buffer, the usage of iv is expired */
-+ SYMC_NODE_USAGE_LAST = 0x02, /*!< The last buffer, must update the iv */
-+ SYMC_NODE_USAGE_ODD_KEY = 0x40, /*!< Use the odd key to encrypt/decrypt this buffer*/
-+ SYMC_NODE_USAGE_EVEN_KEY = 0x00,/*!< Use the even key to encrypt/decrypt this buffer*/
-+ SYMC_NODE_USAGE_IN_GCM_A = 0x00, /*!< The buffer of GCM A */
-+ SYMC_NODE_USAGE_IN_GCM_P = 0x08, /*!< The buffer of GCM P */
-+ SYMC_NODE_USAGE_IN_GCM_LEN = 0x10, /*!< The buffer of GCM LEN */
-+ SYMC_NODE_USAGE_IN_CCM_N = 0x00, /*!< The buffer of CCM N */
-+ SYMC_NODE_USAGE_IN_CCM_A = 0x08, /*!< The buffer of CCM A */
-+ SYMC_NODE_USAGE_IN_CCM_P = 0x10, /*!< The buffer of CCM P */
-+ SYMC_NODE_USAGE_CCM_LAST = 0x20, /*!< The buffer of CCM LAST */
++ SYMC_NODE_USAGE_NORMAL = 0x00, /* The normal buffer, don't update the iv */
++ SYMC_NODE_USAGE_FIRST = 0x01, /* The first buffer, the usage of iv is expired */
++ SYMC_NODE_USAGE_LAST = 0x02, /* The last buffer, must update the iv */
++ SYMC_NODE_USAGE_ODD_KEY = 0x40, /* Use the odd key to encrypt or decrypt this buffer */
++ SYMC_NODE_USAGE_EVEN_KEY = 0x00, /* Use the even key to encrypt or decrypt this buffer */
++ SYMC_NODE_USAGE_IN_GCM_A = 0x00, /* The buffer of GCM A */
++ SYMC_NODE_USAGE_IN_GCM_P = 0x08, /* The buffer of GCM P */
++ SYMC_NODE_USAGE_IN_GCM_LEN = 0x10, /* The buffer of GCM LEN */
++ SYMC_NODE_USAGE_IN_CCM_N = 0x00, /* The buffer of CCM N */
++ SYMC_NODE_USAGE_IN_CCM_A = 0x08, /* The buffer of CCM A */
++ SYMC_NODE_USAGE_IN_CCM_P = 0x10, /* The buffer of CCM P */
++ SYMC_NODE_USAGE_CCM_LAST = 0x20, /* The buffer of CCM LAST */
+} symc_node_usage;
+
-+/*! \symc error code */
-+enum symc_error_code {
-+ HI_SYMC_ERR_ALG_INVALID = HI_BASE_ERR_BASE_SYMC, /*!< invalid algorithm */
-+ HI_SYMC_ERR_MODE_INVALID, /*!< invalid mode */
-+ HI_SYMC_ERR_LEN_INVALID, /*!< data length invalid */
-+ HI_SYMC_ERR_IV_LEN_INVALID, /*!< IV length invalid */
-+ HI_SYMC_ERR_TAG_LEN_INVALID, /*!< TAG length invalid */
-+ HI_SYMC_ERR_KEY_LEN_INVALID, /*!< key length invalid */
-+ HI_SYMC_ERR_KEY_INVALID, /*!< key invalid */
-+ HI_SYMC_ERR_ID_INVALID, /*!< channel id invalid */
-+ HI_SYMC_ERR_SMMU_INVALID, /*!< SMMU invalid */
-+ HI_SYMC_ERR_TIME_OUT, /*!< encrypt/decrypt timeout */
-+ HI_SYMC_ERR_BUSY, /*!< busy */
-+};
++/* symc error code */
++typedef enum {
++ HI_SYMC_ERR_ALG_INVALID = HI_BASE_ERR_BASE_SYMC, /* invalid algorithm */
++ HI_SYMC_ERR_MODE_INVALID, /* invalid mode */
++ HI_SYMC_ERR_LEN_INVALID, /* data length invalid */
++ HI_SYMC_ERR_IV_LEN_INVALID, /* IV length invalid */
++ HI_SYMC_ERR_TAG_LEN_INVALID, /* TAG length invalid */
++ HI_SYMC_ERR_KEY_LEN_INVALID, /* key length invalid */
++ HI_SYMC_ERR_KEY_INVALID, /* key invalid */
++ HI_SYMC_ERR_ID_INVALID, /* channel id invalid */
++ HI_SYMC_ERR_SMMU_INVALID, /* SMMU invalid */
++ HI_SYMC_ERR_TIME_OUT, /* encrypt/decrypt timeout */
++ HI_SYMC_ERR_BUSY, /* busy */
++} symc_error_code;
+
+typedef struct {
+ hi_u32 id;
@@ -208317,366 +277185,372 @@ index 0000000..999d703
+ hi_u8 outen;
+ hi_u8 outraw;
+ hi_u32 outintcnt;
-+ char iv[AES_IV_SIZE * 2 + 1];
++ char iv[AES_IV_SIZE * MUL_VAL_2 + BOUND_VAL_1];
+} symc_chn_status;
+
-+/*! \symc capacity, 0-nonsupport, 1-support */
++/* symc capacity, 0-nonsupport, 1-support */
+typedef struct {
-+ hi_u32 aes_ecb : 1 ; /*!< Support AES ECB */
-+ hi_u32 aes_cbc : 1 ; /*!< Support AES CBC */
-+ hi_u32 aes_cfb : 1 ; /*!< Support AES CFB */
-+ hi_u32 aes_ofb : 1 ; /*!< Support AES OFB */
-+ hi_u32 aes_ctr : 1 ; /*!< Support AES CTR */
-+ hi_u32 aes_ccm : 1 ; /*!< Support AES CCM */
-+ hi_u32 aes_gcm : 1 ; /*!< Support AES GCM */
-+ hi_u32 aes_cts : 1 ; /*!< Support AES CTS */
-+ hi_u32 tdes_ecb : 1 ; /*!< Support TDES ECB */
-+ hi_u32 tdes_cbc : 1 ; /*!< Support TDES CBC */
-+ hi_u32 tdes_cfb : 1 ; /*!< Support TDES CFB */
-+ hi_u32 tdes_ofb : 1 ; /*!< Support TDES OFB */
-+ hi_u32 tdes_ctr : 1 ; /*!< Support TDES CTR */
-+ hi_u32 des_ecb : 1 ; /*!< Support DES ECB */
-+ hi_u32 des_cbc : 1 ; /*!< Support DES CBC */
-+ hi_u32 des_cfb : 1 ; /*!< Support DES CFB */
-+ hi_u32 des_ofb : 1 ; /*!< Support DES OFB */
-+ hi_u32 des_ctr : 1 ; /*!< Support DES CTR */
-+ hi_u32 sm1_ecb : 1 ; /*!< Support SM1 ECB */
-+ hi_u32 sm1_cbc : 1 ; /*!< Support SM1 CBC */
-+ hi_u32 sm1_cfb : 1 ; /*!< Support SM1 CFB */
-+ hi_u32 sm1_ofb : 1 ; /*!< Support SM1 OFB */
-+ hi_u32 sm1_ctr : 1 ; /*!< Support SM1 CTR */
-+ hi_u32 sm4_ecb : 1 ; /*!< Support SM4 ECB */
-+ hi_u32 sm4_cbc : 1 ; /*!< Support SM4 CBC */
-+ hi_u32 sm4_cfb : 1 ; /*!< Support SM4 CFB */
-+ hi_u32 sm4_ofb : 1 ; /*!< Support SM4 OFB */
-+ hi_u32 sm4_ctr : 1 ; /*!< Support SM4 CTR */
-+ hi_u32 dma : 1 ; /*!< Support DMA */
++ hi_u32 aes_ecb : 1 ; /* Support AES ECB */
++ hi_u32 aes_cbc : 1 ; /* Support AES CBC */
++ hi_u32 aes_cfb : 1 ; /* Support AES CFB */
++ hi_u32 aes_ofb : 1 ; /* Support AES OFB */
++ hi_u32 aes_ctr : 1 ; /* Support AES CTR */
++ hi_u32 aes_ccm : 1 ; /* Support AES CCM */
++ hi_u32 aes_gcm : 1 ; /* Support AES GCM */
++ hi_u32 aes_cts : 1 ; /* Support AES CTS */
++ hi_u32 tdes_ecb : 1 ; /* Support TDES ECB */
++ hi_u32 tdes_cbc : 1 ; /* Support TDES CBC */
++ hi_u32 tdes_cfb : 1 ; /* Support TDES CFB */
++ hi_u32 tdes_ofb : 1 ; /* Support TDES OFB */
++ hi_u32 tdes_ctr : 1 ; /* Support TDES CTR */
++ hi_u32 des_ecb : 1 ; /* Support DES ECB */
++ hi_u32 des_cbc : 1 ; /* Support DES CBC */
++ hi_u32 des_cfb : 1 ; /* Support DES CFB */
++ hi_u32 des_ofb : 1 ; /* Support DES OFB */
++ hi_u32 des_ctr : 1 ; /* Support DES CTR */
++ hi_u32 sm1_ecb : 1 ; /* Support SM1 ECB */
++ hi_u32 sm1_cbc : 1 ; /* Support SM1 CBC */
++ hi_u32 sm1_cfb : 1 ; /* Support SM1 CFB */
++ hi_u32 sm1_ofb : 1 ; /* Support SM1 OFB */
++ hi_u32 sm1_ctr : 1 ; /* Support SM1 CTR */
++ hi_u32 sm4_ecb : 1 ; /* Support SM4 ECB */
++ hi_u32 sm4_cbc : 1 ; /* Support SM4 CBC */
++ hi_u32 sm4_cfb : 1 ; /* Support SM4 CFB */
++ hi_u32 sm4_ofb : 1 ; /* Support SM4 OFB */
++ hi_u32 sm4_ctr : 1 ; /* Support SM4 CTR */
++ hi_u32 dma : 1 ; /* Support DMA */
+} symc_capacity;
+
-+typedef hi_s32 (*callback_symc_isr)(void *ctx);
-+typedef void (*callback_symc_destory)(void);
++typedef struct {
++ compat_addr *in;
++ compat_addr *out;
++ hi_u32 *len;
++ symc_node_usage *usage;
++ hi_u32 num;
++} symc_multi_pack;
+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
++/*
++ * \brief symc context structure
++ *
++ * \note if the aes key derived from klad, the context msut
++ * attached with a independent hard key channel,
++ * otherwise the context can attached with a fixed common channel.
++ */
++typedef struct {
++ hi_u32 even_key[SYMC_KEY_SIZE / WORD_WIDTH]; /* SYMC even round keys, default */
++ hi_u32 odd_key[SYMC_KEY_SIZE / WORD_WIDTH]; /* SYMC odd round keys, default */
++ hi_u32 sk[SYMC_SM1_SK_SIZE / WORD_WIDTH]; /* sm1 sk */
++ hi_u32 iv[AES_IV_SIZE / WORD_WIDTH]; /* symc IV */
++ hi_u32 tag[AEAD_TAG_SIZE / WORD_WIDTH]; /* aead tag */
++ hi_u32 ivlen; /* symc IV length */
++ hi_u32 iv_usage; /* symc IV usage */
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup symc */
-+/** @{ */ /** <!--[symc]*/
++ hi_u32 hard_chn; /* hard channel number */
++ hi_u32 hard_key; /* Key derived from klad or CPU */
+
++ symc_alg alg; /* Symmetric cipher algorithm */
++ symc_width width; /* Symmetric cipher width */
++ hi_u32 klen; /* Symmetric cipher key length */
+
-+/**
-+\brief Initialize the symc module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_symc_init(void);
++ compat_addr aad; /* Associated Data */
++ hi_u32 alen; /* Associated Data length */
++ hi_u32 tlen; /* Tag length */
+
-+/**
-+\brief Deinitialize the symc module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_symc_deinit(void);
++ symc_mode mode; /* Symmetric cipher mode */
+
-+/**
-+\brief suspend the symc module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+void drv_symc_suspend(void);
++ hi_u32 sm1_round; /* SM1 round number */
++ hi_u32 enclen; /* encrypt length */
+
-+/**
-+\brief resume the symc module.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_symc_resume(void);
++ hi_u32 block_size; /* Block size */
+
-+/**
-+\brief allocate a hard symc channel.
-+\param[out] chn_num The channel number.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++ hi_u32 cur_nodes; /* current nodes id */
++ hi_u32 total_nodes; /* total number of nodes */
++
++ compat_addr *input_list; /* input node list */
++ compat_addr *output_list; /* output node list */
++ hi_u32 *length_list; /* length of node list */
++ symc_node_usage *usage_list; /* usage of node list */
++ hi_bool tdes2dma; /* 3des with invalid key turns to dma */
++} cryp_symc_context;
++
++typedef hi_s32 (*callback_symc_isr)(hi_void *ctx);
++typedef hi_void (*callback_symc_destory)(hi_void);
++
++/*
++ * brief Initialize the symc module.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_symc_init(hi_void);
++
++/*
++ * brief Deinitialize the symc module.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_symc_deinit(hi_void);
++
++/*
++ * brief suspend the symc module.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_void drv_symc_suspend(hi_void);
++
++/*
++ * brief resume the symc module.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_symc_resume(hi_void);
++
++/*
++ * brief allocate a hard symc channel.
++ * param[out] chn_num The channel number.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_symc_alloc_chn(hi_u32 *chn_num);
+
-+/**
-+\brief free a hard symc channel.
-+\param[in] chn_num The channel number.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+void drv_symc_free_chn(hi_u32 chn_num);
++/*
++ * brief free a hard symc channel.
++ * param[in] chn_num The channel number.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_void drv_symc_free_chn(hi_u32 chn_num);
+
-+/**
-+\brief set the iv to the symc module.
-+\param[in] chn_num The channel number.
-+\retval NA.
-+*/
++/*
++ * brief set the iv to the symc module.
++ * param[in] chn_num The channel number.
++ * retval NA.
++ */
+hi_s32 drv_symc_reset(hi_u32 chn_num);
+
-+/**
-+\brief check the length of nodes list.
-+\param[in] alg The symmetric cipher algorithm.
-+\param[in] mode The symmetric cipher mode.
-+\param[in] block_size The block size.
-+\param[in] input The MMZ/SMMU address of in buffer.
-+\param[in] output The MMZ/SMMU address of out buffer.
-+\param[in] length The MMZ/SMMU siae of in buffer.
-+\param[in] klen The key length.
-+\param[in] usage_list The usage of node.
-+\param[in] pkg_num The numbers of node.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_symc_node_check(symc_alg alg, symc_mode mode,
-+ symc_klen klen, hi_u32 block_size,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num);
++/*
++ * brief symc get error code.
++ * param[in] chn_num The channel number.
++ * retval NA.
++ */
++hi_void drv_symc_get_err_code(hi_u32 chn_num);
+
-+/**
-+\brief set work params.
-+\param[in] chn_num The channel number.
-+\param[in] alg The symmetric cipher algorithm.
-+\param[in] mode The symmetric cipher mode.
-+\param[in] decrypt Decrypt or encrypt.
-+\param[in] sm1_round_num The round number of sm1.
-+\param[in] klen The key length.
-+\param[in] hard_key whether use the hard key or not.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_symc_config(hi_u32 chn_num, symc_alg alg, symc_mode mode, symc_width width, hi_u32 decrypt,
-+ hi_u32 sm1_round_num, symc_klen klen, hi_u32 hard_key);
++/*
++ * brief check the length of nodes list.
++ * param[in] alg The symmetric cipher algorithm.
++ * param[in] mode The symmetric cipher mode.
++ * param[in] block_size The block size.
++ * param[in] pack pack data info.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_symc_node_check(symc_alg alg, symc_mode mode, symc_klen klen, hi_u32 block_size, symc_multi_pack *pack);
+
-+/**
-+\brief set the iv to the symc module.
-+\param[in] chn_num The channel number.
-+\param[in] iv The IV data, hardware use the valid bytes according to the alg.
-+\param[in] flag The IV flag, should be CIPHER_IV_CHANGE_ONE_PKG or CIPHER_IV_CHANGE_ALL_PKG.
-+\retval NA.
-+*/
++/*
++ * brief set work params.
++ * param[in] ctx cryp symc context info.
++ * param[in] decrypt Decrypt or encrypt.
++ * param[in] klen The key length.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_symc_cfg(cryp_symc_context *ctx, hi_u32 decrypt, symc_klen klen);
++
++/*
++ * brief set the iv to the symc module.
++ * param[in] chn_num The channel number.
++ * param[in] iv The IV data, hardware use the valid bytes according to the alg.
++ * param[in] flag The IV flag, should be HI_CIPHER_IV_CHG_ONE_PACK or HI_CIPHER_IV_CHG_ALL_PACK.
++ * retval NA.
++ */
+hi_s32 drv_symc_set_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD], hi_u32 ivlen, hi_u32 flag);
+
-+/**
-+\brief get the iv to the symc module.
-+\param[in] chn_num The channel number.
-+\param[out] iv The IV data, the length is 16.
-+\retval NA.
-+*/
-+void drv_symc_get_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD]);
++/*
++ * brief get the iv to the symc module.
++ * param[in] chn_num The channel number.
++ * param[out] iv The IV data, the length is 16.
++ * retval NA.
++ */
++hi_void drv_symc_get_iv(hi_u32 chn_num, hi_u32 iv[SYMC_IV_MAX_SIZE_IN_WORD]);
+
-+/**
-+\brief set the key to the symc module.
-+\param[in] chn_num The channel number.
-+\param[in] key The key data, hardware use the valid bytes according to the alg.
-+\param[in] odd This id odd key or not .
-+\retval NA.
-+*/
-+void drv_symc_set_key(hi_u32 chn_num, hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD], hi_u32 odd);
++/*
++ * brief set the key to the symc module.
++ * param[in] chn_num The channel number.
++ * param[in] key The key data, hardware use the valid bytes according to the alg.
++ * param[in] odd This id odd key or not .
++ * retval NA.
++ */
++hi_void drv_symc_set_key(hi_u32 chn_num, hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD], hi_u32 key_len, hi_u32 odd);
+
-+/**
-+\brief set the sm1 sk to the symc module.
-+\param[in] chn_num The channel number.
-+\param[in] key The sk data, the length is 16.
-+\retval NA.
-+*/
-+void drv_symc_set_sm1_sk(hi_u32 chn_num, hi_u32 key[SYMC_SM1_SK_SIZE_IN_WORD]);
++/*
++ * brief set the sm1 sk to the symc module.
++ * param[in] chn_num The channel number.
++ * param[in] key The sk data, the length is 16.
++ * retval NA.
++ */
++hi_void drv_symc_set_sm1_sk(hi_u32 chn_num, hi_u32 key[SYMC_SM1_SK_SIZE_IN_WORD], hi_u32 key_len);
+
-+/**
-+\brief add a in buffer to the nodes list.
-+\param[in] chn_num The channel number.
-+\param[in] buf_phy The MMZ/SMMU address of in buffer.
-+\param[in] buf_size The MMZ/SMMU siae of in buffer.
-+\param[in] local The locational of in buffer under a symmetric cipher.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief add a in buffer to the nodes list.
++ * param[in] chn_num The channel number.
++ * param[in] buf_phy The MMZ/SMMU address of in buffer.
++ * param[in] buf_size The MMZ/SMMU siae of in buffer.
++ * param[in] local The locational of in buffer under a symmetric cipher.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_symc_add_inbuf(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size, symc_node_usage usage);
+
-+/**
-+\brief add a out buffer to the nodes list.
-+\param[in] chn_num The channel number.
-+\param[in] buf_phy The MMZ/SMMU address of out buffer.
-+\param[in] buf_size The MMZ/SMMU siae of out buffer.
-+\param[in] local The locational of in buffer under a symmetric cipher.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief add a out buffer to the nodes list.
++ * param[in] chn_num The channel number.
++ * param[in] buf_phy The MMZ/SMMU address of out buffer.
++ * param[in] buf_size The MMZ/SMMU siae of out buffer.
++ * param[in] local The locational of in buffer under a symmetric cipher.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_symc_add_outbuf(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size, symc_node_usage usage);
+
-+/**
-+\brief add a buffer usage to the nodes list.
-+\param[in] chn_num The channel number.
-+\param[in] in in or out.
-+\param[in] usage uasge.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+void drv_symc_add_buf_usage(hi_u32 chn_num, hi_u32 in, symc_node_usage usage);
++/*
++ * brief add a buffer usage to the nodes list.
++ * param[in] chn_num The channel number.
++ * param[in] in in or out.
++ * param[in] usage uasge.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_void drv_symc_add_buf_usage(hi_u32 chn_num, hi_u32 in, symc_node_usage usage);
+
-+/**
-+\brief add N of CCM to the nodes list.
-+\param[in] chn_num The channel number.
-+\param[in] n The buffer of n, the size is 16.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_aead_ccm_add_n(hi_u32 chn_num, hi_u8 *n);
++/*
++ * brief add N of CCM to the nodes list.
++ * param[in] chn_num The channel number.
++ * param[in] nonce The buffer of n, the size is 16.
++ * param[in] nonce_len The buffer of n, the size is 16.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_aead_ccm_add_n(hi_u32 chn_num, hi_u8 *nonce, hi_u32 nonce_len);
+
-+/**
-+\brief add A of CCM to the nodes list.
-+\param[in] chn_num The channel number.
-+\param[in] buf_phy The MMZ/SMMU address of A.
-+\param[in] buf_size The MMZ/SMMU size of A.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief add A of CCM to the nodes list.
++ * param[in] chn_num The channel number.
++ * param[in] buf_phy The MMZ/SMMU address of A.
++ * param[in] buf_size The MMZ/SMMU size of A.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_aead_ccm_add_a(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size);
+
-+/**
-+\brief add A of GCM to the nodes list.
-+\param[in] chn_num The channel number.
-+\param[in] buf_phy The MMZ/SMMU address of A.
-+\param[in] buf_size The MMZ/SMMU size of A.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief add A of GCM to the nodes list.
++ * param[in] chn_num The channel number.
++ * param[in] buf_phy The MMZ/SMMU address of A.
++ * param[in] buf_size The MMZ/SMMU size of A.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_aead_gcm_add_a(hi_u32 chn_num, compat_addr buf_phy, hi_u32 buf_size);
+
-+/**
-+\brief add length field of GCM to the nodes list.
-+\param[in] chn_num The channel number.
-+\param[in] buf_phy The MMZ/SMMU address of length field, the size is 16.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 drv_aead_gcm_add_clen(hi_u32 chn_num, hi_u8 *clen);
++/*
++ * brief add length field of GCM to the nodes list.
++ * param[in] chn_num The channel number.
++ * param[in] buf_phy The MMZ/SMMU address of length field, the size is 16.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 drv_aead_gcm_add_clen(hi_u32 chn_num, hi_u8 *clen, hi_u32 clen_len);
+
-+/**
-+\brief get ccm/gcm tag.
-+\param[in] chn_num The channel number.
-+\param[out] tag The tag value.
-+\retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
-+hi_s32 drv_aead_get_tag(hi_u32 chn_num, hi_u32 *tag);
++/*
++ * brief get ccm/gcm tag.
++ * param[in] chn_num The channel number.
++ * param[out] tag The tag value.
++ * param[in] tag_buf_len length in byte.
++ * retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
++ */
++hi_s32 drv_aead_get_tag(hi_u32 chn_num, hi_u32 *tag, hi_u32 tag_buf_len);
+
-+/**
-+\brief start symmetric cipher calculation.
-+\param[in] chn_num The channel number.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief start symmetric cipher calculation.
++ * param[in] chn_num The channel number.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_symc_start(hi_u32 chn_num);
+
-+/**
-+\brief wait running finished.
-+\param[in] chn_num The channel number.
-+\retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
++/*
++ * brief wait running finished.
++ * param[in] chn_num The channel number.
++ * retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
++ */
+hi_s32 drv_symc_wait_done(hi_u32 chn_num, hi_u32 timeout);
+
-+/**
-+\brief set isr callback function.
-+\param[in] chn_num The channel number.
-+\retval On finished, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
-+hi_s32 drv_symc_set_isr_callback(hi_u32 chn_num, callback_symc_isr callback, void *ctx);
++/*
++ * brief set isr callback function.
++ * param[in] chn_num The channel number.
++ * retval On finished, HI_TRUE is returned otherwise HI_FALSE is returned.
++ */
++hi_s32 drv_symc_set_isr_callback(hi_u32 chn_num, callback_symc_isr callback, hi_void *ctx);
+
-+/**
-+\brief set destory callback function.
-+\param[in] chn_num The channel number.
-+\retval On finished, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
++/*
++ * brief set destory callback function.
++ * param[in] chn_num The channel number.
++ * retval On finished, HI_TRUE is returned otherwise HI_FALSE is returned.
++ */
+hi_s32 drv_symc_set_destory_callbcak(hi_u32 chn_num, callback_symc_destory destory);
+
-+/**
-+\brief proc status.
-+\param[in] status The proc status.
-+\retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
++/*
++ * brief proc status.
++ * param[in] status The proc status.
++ * retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
++ */
+hi_s32 drv_symc_proc_status(symc_chn_status *status);
+
-+/**
-+\brief get the symc capacity.
-+\param[out] capacity The symc capacity.
-+\retval NA.
-+*/
-+void drv_symc_get_capacity(symc_capacity *capacity);
++/*
++ * brief get the symc capacity.
++ * param[out] capacity The symc capacity.
++ * retval NA.
++ */
++hi_void drv_symc_get_capacity(symc_capacity *capacity);
+
-+/** @} */ /** <!-- ==== API declaration end ==== */
++/*
++ * brief check drv symc is secure or not.
++ * retval NA.
++ */
++hi_u32 drv_symc_is_secure(hi_void);
+
-+#endif
++#endif /* End of __DRV_SYMC_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_trng.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_trng.h
new file mode 100644
-index 0000000..6d210dc
+index 0000000..d792dfb
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include/drv_trng.h
-@@ -0,0 +1,55 @@
+@@ -0,0 +1,30 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv trng.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_TRNG_H__
+#define __DRV_TRNG_H__
+
-+/*************************** Structure Definition ****************************/
-+/** \addtogroup rsa */
-+/** @{ */ /** <!-- [rsa] */
-+
-+/*! \rsa capacity, 0-nonsupport, 1-support */
++/* rsa capacity, 0-nonsupport, 1-support. */
+typedef struct {
-+ hi_u32 trng : 1 ; /*!< Support TRNG */
++ hi_u32 trng : 1; /* Support TRNG. */
+} trng_capacity;
+
-+/** @} */ /** <!-- ==== Structure Definition end ==== */
-+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup trng */
-+/** @{ */ /** <!--[trng]*/
-+
-+
-+/**
-+\brief get rand number.
-+\param[out] randnum rand number.
-+\param[in] timeout time out.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief get rand number.
++ * \param[out] randnum rand number.
++ * \param[in] timeout time out.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 drv_trng_randnum(hi_u32 *randnum, hi_u32 timeout);
+
-+/**
-+\brief get the trng capacity.
-+\param[out] capacity The hash capacity.
-+\retval NA.
-+*/
++/*
++ * \brief get the trng capacity.
++ * \param[out] capacity The hash capacity.
++ * \retval NA.
++ */
+void drv_trng_get_capacity(trng_capacity *capacity);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_hash.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_hash.c
new file mode 100644
-index 0000000..7236a7e
+index 0000000..2126ae1
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_hash.c
-@@ -0,0 +1,784 @@
+@@ -0,0 +1,810 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for cipher cryp hash.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
@@ -208684,322 +277558,372 @@ index 0000000..7236a7e
+#include "cryp_hash.h"
+#include "ext_alg.h"
+
-+/*************************** Internal Structure Definition *******************/
-+/** \addtogroup rsa */
-+/** @{*/ /** <!-- [rsa]*/
-+
-+/* size of hash physical memory */
-+#define HASH_PHY_MEM_SIZE (0x100000)/* 1M */
++/* size of hash physical memory 1M */
++#define HASH_PHY_MEM_SIZE 0x100000
+
+/* try to create memory for HASH */
-+#define HASH_PHY_MEM_CREATE_TRY_TIME (10)
++#define HASH_PHY_MEM_CREATE_TRY_TIME 10
+
+/* block size */
-+#define SHA1_BLOCK_SIZE (64) /* SHA1 */
-+#define SHA224_BLOCK_SIZE (64) /* SHA224 */
-+#define SHA256_BLOCK_SIZE (64) /* SHA256 */
-+#define SHA384_BLOCK_SIZE (128) /* SHA384 */
-+#define SHA512_BLOCK_SIZE (128) /* SHA512 */
-+#define SM3_BLOCK_SIZE (64) /* SM3 */
++#define SHA1_BLOCK_SIZE 64
++#define SHA224_BLOCK_SIZE 64
++#define SHA256_BLOCK_SIZE 64
++#define SHA384_BLOCK_SIZE 128
++#define SHA512_BLOCK_SIZE 128
++#define SM3_BLOCK_SIZE 64
+
+/* first byte of hash padding */
-+#define HASH_PADDING_B0 (0x80)
++#define HASH_PADDING_B0 0x80
+
-+/* Pading size */
-+#define HASH_BLOCK64_PAD_MIN (9) /* 0x80 || Len(64) */
-+#define HASH_BLOCK128_PAD_MIN (17) /* 0x80 || Len(128) */
++/* Hash padding 0x80 || Len(64) */
++#define HASH_BLOCK64_PAD_MIN 9
++/* Hash padding 0x80 || Len(128) */
++#define HASH_BLOCK128_PAD_MIN 17
+
+/* The max tab size of symc function */
-+#define HASH_FUNC_TAB_SIZE (16)
++#define HASH_FUNC_TAB_SIZE 16
+
-+/* SHA-1, the initial hash value, H(0)*/
-+#define SHA1_H0 0x67452301
-+#define SHA1_H1 0xefcdab89
-+#define SHA1_H2 0x98badcfe
-+#define SHA1_H3 0x10325476
-+#define SHA1_H4 0xc3d2e1f0
++/* SHA-1, the initial hash value, H(0) */
++#define SHA1_H0 0x67452301
++#define SHA1_H1 0xefcdab89
++#define SHA1_H2 0x98badcfe
++#define SHA1_H3 0x10325476
++#define SHA1_H4 0xc3d2e1f0
+
-+/* SHA-224, the initial hash value, H(0)*/
-+#define SHA224_H0 0xc1059ed8
-+#define SHA224_H1 0x367cd507
-+#define SHA224_H2 0x3070dd17
-+#define SHA224_H3 0xf70e5939
-+#define SHA224_H4 0xffc00b31
-+#define SHA224_H5 0x68581511
-+#define SHA224_H6 0x64f98fa7
-+#define SHA224_H7 0xbefa4fa4
++/* SHA-224, the initial hash value, H(0) */
++#define SHA224_H0 0xc1059ed8
++#define SHA224_H1 0x367cd507
++#define SHA224_H2 0x3070dd17
++#define SHA224_H3 0xf70e5939
++#define SHA224_H4 0xffc00b31
++#define SHA224_H5 0x68581511
++#define SHA224_H6 0x64f98fa7
++#define SHA224_H7 0xbefa4fa4
+
-+/* SHA-256, the initial hash value, H(0)*/
-+#define SHA256_H0 0x6a09e667
-+#define SHA256_H1 0xbb67ae85
-+#define SHA256_H2 0x3c6ef372
-+#define SHA256_H3 0xa54ff53a
-+#define SHA256_H4 0x510e527f
-+#define SHA256_H5 0x9b05688c
-+#define SHA256_H6 0x1f83d9ab
-+#define SHA256_H7 0x5be0cd19
++/* SHA-256, the initial hash value, H(0) */
++#define SHA256_H0 0x6a09e667
++#define SHA256_H1 0xbb67ae85
++#define SHA256_H2 0x3c6ef372
++#define SHA256_H3 0xa54ff53a
++#define SHA256_H4 0x510e527f
++#define SHA256_H5 0x9b05688c
++#define SHA256_H6 0x1f83d9ab
++#define SHA256_H7 0x5be0cd19
+
-+/* SHA-384, the initial hash value, H(0)*/
-+#define SHA384_H0 0xcbbb9d5dc1059ed8ULL
-+#define SHA384_H1 0x629a292a367cd507ULL
-+#define SHA384_H2 0x9159015a3070dd17ULL
-+#define SHA384_H3 0x152fecd8f70e5939ULL
-+#define SHA384_H4 0x67332667ffc00b31ULL
-+#define SHA384_H5 0x8eb44a8768581511ULL
-+#define SHA384_H6 0xdb0c2e0d64f98fa7ULL
-+#define SHA384_H7 0x47b5481dbefa4fa4ULL
++/* SHA-384, the initial hash value, H(0) */
++#define SHA384_H0 0xcbbb9d5dc1059ed8ULL
++#define SHA384_H1 0x629a292a367cd507ULL
++#define SHA384_H2 0x9159015a3070dd17ULL
++#define SHA384_H3 0x152fecd8f70e5939ULL
++#define SHA384_H4 0x67332667ffc00b31ULL
++#define SHA384_H5 0x8eb44a8768581511ULL
++#define SHA384_H6 0xdb0c2e0d64f98fa7ULL
++#define SHA384_H7 0x47b5481dbefa4fa4ULL
+
-+/* SHA-512, the initial hash value, H(0)*/
-+#define SHA512_H0 0x6a09e667f3bcc908ULL
-+#define SHA512_H1 0xbb67ae8584caa73bULL
-+#define SHA512_H2 0x3c6ef372fe94f82bULL
-+#define SHA512_H3 0xa54ff53a5f1d36f1ULL
-+#define SHA512_H4 0x510e527fade682d1ULL
-+#define SHA512_H5 0x9b05688c2b3e6c1fULL
-+#define SHA512_H6 0x1f83d9abfb41bd6bULL
-+#define SHA512_H7 0x5be0cd19137e2179ULL
++/* SHA-512, the initial hash value, H(0) */
++#define SHA512_H0 0x6a09e667f3bcc908ULL
++#define SHA512_H1 0xbb67ae8584caa73bULL
++#define SHA512_H2 0x3c6ef372fe94f82bULL
++#define SHA512_H3 0xa54ff53a5f1d36f1ULL
++#define SHA512_H4 0x510e527fade682d1ULL
++#define SHA512_H5 0x9b05688c2b3e6c1fULL
++#define SHA512_H6 0x1f83d9abfb41bd6bULL
++#define SHA512_H7 0x5be0cd19137e2179ULL
+
-+/* SM3, the initial hash value, H(0)*/
-+#define SM3_H0 0x7380166F
-+#define SM3_H1 0x4914B2B9
-+#define SM3_H2 0x172442D7
-+#define SM3_H3 0xDA8A0600
-+#define SM3_H4 0xA96F30BC
-+#define SM3_H5 0x163138AA
-+#define SM3_H6 0xE38DEE4D
-+#define SM3_H7 0xB0FB0E4E
++/* SM3, the initial hash value, H(0) */
++#define SM3_H0 0x7380166F
++#define SM3_H1 0x4914B2B9
++#define SM3_H2 0x172442D7
++#define SM3_H3 0xDA8A0600
++#define SM3_H4 0xA96F30BC
++#define SM3_H5 0x163138AA
++#define SM3_H6 0xE38DEE4D
++#define SM3_H7 0xB0FB0E4E
+
+/* hash function list */
-+static hash_func hash_descriptor[HASH_FUNC_TAB_SIZE];
++static hash_func g_hash_descriptor[HASH_FUNC_TAB_SIZE];
+
+#ifdef CHIP_HASH_SUPPORT
-+/**
++
++/*
+ * \brief hash context structure
+ */
+typedef struct {
-+ hash_mode mode; /*!< HASH mode */
-+ hi_u32 block_size; /*!< HASH block size */
-+ hi_u32 hash_size; /*!< HASH result size */
-+ hi_u32 hard_chn; /*!< HASH hardware channel number */
-+ hi_u8 tail[HASH_BLOCK_SIZE_128 * 2]; /*!< buffer to store the tail and padding data */
-+ hi_u32 tail_len; /*!< length of the tail message */
-+ hi_u32 total; /*!< total length of the message */
-+ hi_u32 hash[HASH_RESULT_MAX_SIZE_IN_WORD]; /*!< buffer to store the result */
-+ crypto_mem mem; /*!< DMA memory of hash message */
-+}
-+cryp_hash_context;
++ hash_mode mode; /* HASH mode */
++ hi_u32 block_size; /* HASH block size */
++ hi_u32 hash_size; /* HASH result size */
++ hi_u32 hard_chn; /* HASH hardware channel number */
++ hi_u8 tail[HASH_BLOCK_SIZE_128 * MUL_VAL_2]; /* buffer to store the tail and padding data, len is 256 bytes. */
++ hi_u32 tail_len; /* length of the tail message */
++ hi_u32 total; /* total length of the message */
++ hi_u32 hash[HASH_RESULT_MAX_SIZE_IN_WORD]; /* buffer to store the result */
++ crypto_mem mem; /* DMA memory of hash message */
++} cryp_hash_context;
+
+/* hash dma memory */
-+static crypto_mem hash_mem;
++static crypto_mem g_hash_mem;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++/* ****************************** API Code **************************** */
++static hi_void cryp_sha1_init(cryp_hash_context *hisi_ctx)
++{
++ hisi_ctx->block_size = SHA1_BLOCK_SIZE;
++ hisi_ctx->hash_size = SHA1_RESULT_SIZE;
++ hisi_ctx->hash[WORD_IDX_0] = crypto_cpu_to_be32(SHA1_H0);
++ hisi_ctx->hash[WORD_IDX_1] = crypto_cpu_to_be32(SHA1_H1);
++ hisi_ctx->hash[WORD_IDX_2] = crypto_cpu_to_be32(SHA1_H2);
++ hisi_ctx->hash[WORD_IDX_3] = crypto_cpu_to_be32(SHA1_H3);
++ hisi_ctx->hash[WORD_IDX_4] = crypto_cpu_to_be32(SHA1_H4);
++}
+
-+/******************************* API Code *****************************/
-+/** \addtogroup hash drivers*/
-+/** @{*/ /** <!-- [hash]*/
++static hi_void cryp_sha2_224_init(cryp_hash_context *hisi_ctx)
++{
++ hisi_ctx->hash_size = SHA224_RESULT_SIZE;
++ hisi_ctx->block_size = SHA224_BLOCK_SIZE;
++ hisi_ctx->hash[WORD_IDX_0] = crypto_cpu_to_be32(SHA224_H0);
++ hisi_ctx->hash[WORD_IDX_1] = crypto_cpu_to_be32(SHA224_H1);
++ hisi_ctx->hash[WORD_IDX_2] = crypto_cpu_to_be32(SHA224_H2);
++ hisi_ctx->hash[WORD_IDX_3] = crypto_cpu_to_be32(SHA224_H3);
++ hisi_ctx->hash[WORD_IDX_4] = crypto_cpu_to_be32(SHA224_H4);
++ hisi_ctx->hash[WORD_IDX_5] = crypto_cpu_to_be32(SHA224_H5);
++ hisi_ctx->hash[WORD_IDX_6] = crypto_cpu_to_be32(SHA224_H6);
++ hisi_ctx->hash[WORD_IDX_7] = crypto_cpu_to_be32(SHA224_H7);
++}
++
++static hi_void cryp_sha2_256_init(cryp_hash_context *hisi_ctx)
++{
++ hisi_ctx->hash_size = SHA256_RESULT_SIZE;
++ hisi_ctx->block_size = SHA256_BLOCK_SIZE;
++ hisi_ctx->hash[WORD_IDX_0] = crypto_cpu_to_be32(SHA256_H0);
++ hisi_ctx->hash[WORD_IDX_1] = crypto_cpu_to_be32(SHA256_H1);
++ hisi_ctx->hash[WORD_IDX_2] = crypto_cpu_to_be32(SHA256_H2);
++ hisi_ctx->hash[WORD_IDX_3] = crypto_cpu_to_be32(SHA256_H3);
++ hisi_ctx->hash[WORD_IDX_4] = crypto_cpu_to_be32(SHA256_H4);
++ hisi_ctx->hash[WORD_IDX_5] = crypto_cpu_to_be32(SHA256_H5);
++ hisi_ctx->hash[WORD_IDX_6] = crypto_cpu_to_be32(SHA256_H6);
++ hisi_ctx->hash[WORD_IDX_7] = crypto_cpu_to_be32(SHA256_H7);
++}
++
++static hi_void cryp_sha2_384_init(cryp_hash_context *hisi_ctx)
++{
++ hi_u32 idx = 0;
++ hi_u64 H0;
++
++ hisi_ctx->hash_size = SHA384_RESULT_SIZE;
++ hisi_ctx->block_size = SHA384_BLOCK_SIZE;
++ H0 = crypto_cpu_to_be64(SHA384_H0);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA384_H1);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA384_H2);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA384_H3);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA384_H4);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA384_H5);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA384_H6);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA384_H7);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++}
++
++static hi_void cryp_sha2_512_init(cryp_hash_context *hisi_ctx)
++{
++ hi_u32 idx = 0;
++ hi_u64 H0;
++
++ hisi_ctx->hash_size = SHA512_RESULT_SIZE;
++ hisi_ctx->block_size = SHA512_BLOCK_SIZE;
++ H0 = crypto_cpu_to_be64(SHA512_H0);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA512_H1);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA512_H2);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA512_H3);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA512_H4);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA512_H5);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA512_H6);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++
++ idx += WORD_IDX_2;
++ H0 = crypto_cpu_to_be64(SHA512_H7);
++ crypto_memcpy(&hisi_ctx->hash[idx], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++}
++
++static hi_void cryp_sm3_init(cryp_hash_context *hisi_ctx)
++{
++ hisi_ctx->hash_size = SM3_RESULT_SIZE;
++ hisi_ctx->block_size = SM3_BLOCK_SIZE;
++ hisi_ctx->hash[WORD_IDX_0] = crypto_cpu_to_be32(SM3_H0);
++ hisi_ctx->hash[WORD_IDX_1] = crypto_cpu_to_be32(SM3_H1);
++ hisi_ctx->hash[WORD_IDX_2] = crypto_cpu_to_be32(SM3_H2);
++ hisi_ctx->hash[WORD_IDX_3] = crypto_cpu_to_be32(SM3_H3);
++ hisi_ctx->hash[WORD_IDX_4] = crypto_cpu_to_be32(SM3_H4);
++ hisi_ctx->hash[WORD_IDX_5] = crypto_cpu_to_be32(SM3_H5);
++ hisi_ctx->hash[WORD_IDX_6] = crypto_cpu_to_be32(SM3_H6);
++ hisi_ctx->hash[WORD_IDX_7] = crypto_cpu_to_be32(SM3_H7);
++}
+
+static hi_s32 cryp_hash_initial(cryp_hash_context *hisi_ctx, hash_mode mode)
+{
-+#ifndef CHIP_TYPE_hi3516ev200
-+ hi_u64 H0;
-+#endif
-+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ switch (mode) {
+ case HASH_MODE_SHA1: {
-+ hisi_ctx->block_size = SHA1_BLOCK_SIZE;
-+ hisi_ctx->hash_size = SHA1_RESULT_SIZE;
-+ hisi_ctx->hash[0] = CPU_TO_BE32(SHA1_H0);
-+ hisi_ctx->hash[1] = CPU_TO_BE32(SHA1_H1);
-+ hisi_ctx->hash[2] = CPU_TO_BE32(SHA1_H2);
-+ hisi_ctx->hash[3] = CPU_TO_BE32(SHA1_H3);
-+ hisi_ctx->hash[4] = CPU_TO_BE32(SHA1_H4);
++ cryp_sha1_init(hisi_ctx);
+ break;
+ }
+ case HASH_MODE_SHA224: {
-+ hisi_ctx->hash_size = SHA224_RESULT_SIZE;
-+ hisi_ctx->block_size = SHA224_BLOCK_SIZE;
-+ hisi_ctx->hash[0] = CPU_TO_BE32(SHA224_H0);
-+ hisi_ctx->hash[1] = CPU_TO_BE32(SHA224_H1);
-+ hisi_ctx->hash[2] = CPU_TO_BE32(SHA224_H2);
-+ hisi_ctx->hash[3] = CPU_TO_BE32(SHA224_H3);
-+ hisi_ctx->hash[4] = CPU_TO_BE32(SHA224_H4);
-+ hisi_ctx->hash[5] = CPU_TO_BE32(SHA224_H5);
-+ hisi_ctx->hash[6] = CPU_TO_BE32(SHA224_H6);
-+ hisi_ctx->hash[7] = CPU_TO_BE32(SHA224_H7);
++ cryp_sha2_224_init(hisi_ctx);
+ break;
+ }
+ case HASH_MODE_SHA256: {
-+ hisi_ctx->hash_size = SHA256_RESULT_SIZE;
-+ hisi_ctx->block_size = SHA256_BLOCK_SIZE;
-+ hisi_ctx->hash[0] = CPU_TO_BE32(SHA256_H0);
-+ hisi_ctx->hash[1] = CPU_TO_BE32(SHA256_H1);
-+ hisi_ctx->hash[2] = CPU_TO_BE32(SHA256_H2);
-+ hisi_ctx->hash[3] = CPU_TO_BE32(SHA256_H3);
-+ hisi_ctx->hash[4] = CPU_TO_BE32(SHA256_H4);
-+ hisi_ctx->hash[5] = CPU_TO_BE32(SHA256_H5);
-+ hisi_ctx->hash[6] = CPU_TO_BE32(SHA256_H6);
-+ hisi_ctx->hash[7] = CPU_TO_BE32(SHA256_H7);
++ cryp_sha2_256_init(hisi_ctx);
+ break;
+ }
+#ifndef CHIP_TYPE_hi3516ev200
+ case HASH_MODE_SHA384: {
-+ hisi_ctx->hash_size = SHA384_RESULT_SIZE;
-+ hisi_ctx->block_size = SHA384_BLOCK_SIZE;
-+ H0 = CPU_TO_BE64(SHA384_H0);
-+ crypto_memcpy(&hisi_ctx->hash[0], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA384_H1);
-+ crypto_memcpy(&hisi_ctx->hash[2], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA384_H2);
-+ crypto_memcpy(&hisi_ctx->hash[4], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA384_H3);
-+ crypto_memcpy(&hisi_ctx->hash[6], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA384_H4);
-+ crypto_memcpy(&hisi_ctx->hash[8], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA384_H5);
-+ crypto_memcpy(&hisi_ctx->hash[10], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA384_H6);
-+ crypto_memcpy(&hisi_ctx->hash[12], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA384_H7);
-+ crypto_memcpy(&hisi_ctx->hash[14], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++ cryp_sha2_384_init(hisi_ctx);
+ break;
+ }
+ case HASH_MODE_SHA512: {
-+ hisi_ctx->hash_size = SHA512_RESULT_SIZE;
-+ hisi_ctx->block_size = SHA512_BLOCK_SIZE;
-+ H0 = CPU_TO_BE64(SHA512_H0);
-+ crypto_memcpy(&hisi_ctx->hash[0], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA512_H1);
-+ crypto_memcpy(&hisi_ctx->hash[2], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA512_H2);
-+ crypto_memcpy(&hisi_ctx->hash[4], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA512_H3);
-+ crypto_memcpy(&hisi_ctx->hash[6], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA512_H4);
-+ crypto_memcpy(&hisi_ctx->hash[8], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA512_H5);
-+ crypto_memcpy(&hisi_ctx->hash[10], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA512_H6);
-+ crypto_memcpy(&hisi_ctx->hash[12], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
-+ H0 = CPU_TO_BE64(SHA512_H7);
-+ crypto_memcpy(&hisi_ctx->hash[14], DOUBLE_WORD_WIDTH, &H0, sizeof(H0));
++ cryp_sha2_512_init(hisi_ctx);
+ break;
+ }
+#endif
+ case HASH_MODE_SM3: {
-+ hisi_ctx->hash_size = SM3_RESULT_SIZE;
-+ hisi_ctx->block_size = SM3_BLOCK_SIZE;
-+ hisi_ctx->hash[0] = CPU_TO_BE32(SM3_H0);
-+ hisi_ctx->hash[1] = CPU_TO_BE32(SM3_H1);
-+ hisi_ctx->hash[2] = CPU_TO_BE32(SM3_H2);
-+ hisi_ctx->hash[3] = CPU_TO_BE32(SM3_H3);
-+ hisi_ctx->hash[4] = CPU_TO_BE32(SM3_H4);
-+ hisi_ctx->hash[5] = CPU_TO_BE32(SM3_H5);
-+ hisi_ctx->hash[6] = CPU_TO_BE32(SM3_H6);
-+ hisi_ctx->hash[7] = CPU_TO_BE32(SM3_H7);
++ cryp_sm3_init(hisi_ctx);
+ break;
+ }
+ default: {
-+ HI_LOG_ERROR("Invalid hash mode, mode = 0x%x.\n", mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid hash mode, mode = 0x%x.\n", mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/**
-+* \brief Create DMA memory of HASH message
-+*/
++/*
++ * \brief Create DMA memory of HASH message
++ */
+static hi_s32 cryp_hash_create_mem(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 i = 0;
++ hi_s32 ret;
++ hi_u32 i;
+ hi_u32 length = HASH_PHY_MEM_SIZE;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ crypto_memset(&hash_mem, sizeof(hash_mem), 0x00, sizeof(hash_mem));
++ crypto_memset(&g_hash_mem, sizeof(g_hash_mem), 0x00, sizeof(g_hash_mem));
+
+ /* Try to alloc memory, halve the length if failed */
+ for (i = 0; i < HASH_PHY_MEM_CREATE_TRY_TIME; i++) {
-+ ret = hash_mem_create(&hash_mem, SEC_MMZ, "hash_msg_dma", length);
++ ret = hash_mem_create(&g_hash_mem, SEC_MMZ, "hash_msg_dma", length);
+ if (ret == HI_SUCCESS) {
+ return HI_SUCCESS;
+ } else {
-+ /* halve the length */
-+ length /= 0x02;
++ /* half the length */
++ length /= MUL_VAL_2;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_ERR_CIPHER_FAILED_MEM;
+}
+
+static hi_s32 cryp_hash_destory_mem(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ ret = hash_mem_destory(&hash_mem);
++ ret = hash_mem_destory(&g_hash_mem);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_destory, ret);
++ hi_log_print_func_err(crypto_mem_destory, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static hi_s32 cryp_hash_chunk_copy(const hi_void *chunk, hi_void *dma, hi_u32 len, hash_chunk_src src)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* Don't process the empty message */
+ if (len == 0x00) {
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
-+ HI_LOG_CHECK_PARAM(chunk == HI_NULL);
-+ HI_LOG_CHECK_PARAM(dma == HI_NULL);
++ hi_log_chk_param_return(chunk == HI_NULL);
++ hi_log_chk_param_return(dma == HI_NULL);
+
+ if (src == HASH_CHUNCK_SRC_LOCAL) {
+ crypto_memcpy(dma, len, chunk, len);
+ } else {
+ ret = crypto_copy_from_user(dma, chunk, len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_copy_from_user, ret);
++ hi_log_print_func_err(crypto_copy_from_user, ret);
+ return ret;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+/* hash hardware computation */
-+static hi_s32 cryp_hash_process(cryp_hash_context *hisi_ctx,
-+ hi_u8 *msg, hi_u32 length,
-+ hash_chunk_src src)
++static hi_s32 cryp_hash_process(cryp_hash_context *hisi_ctx, hi_u8 *msg, hi_u32 length, hash_chunk_src src)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_void *buf = HI_NULL;
-+ hi_u32 left = 0, size = 0, max = 0;
++ hi_u32 left, size, max;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* Don't process the empty message */
+ if (length == 0x00) {
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
-+ HI_LOG_DEBUG("length 0x%x, dma_size 0x%x\n", length, hisi_ctx->mem.dma_size);
++ hi_log_debug("length 0x%x, dma_size 0x%x\n", length, hisi_ctx->mem.dma_size);
+
+ /* get dma buffer */
+ buf = crypto_mem_virt(&hisi_ctx->mem);
@@ -209022,33 +277946,33 @@ index 0000000..7236a7e
+ size = max;
+ }
+
-+ HI_LOG_DEBUG("msg 0x%p, size 0x%x, left 0x%x, max 0x%x\n", msg, size, left, max);
++ hi_log_debug("msg 0x%p, size 0x%x, left 0x%x, max 0x%x\n", msg, size, left, max);
+
+ /* copy message to dma buffer */
+ ret = cryp_hash_chunk_copy(msg, buf, size, src);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_chunk_copy, ret);
++ hi_log_print_func_err(cryp_hash_chunk_copy, ret);
+ goto exit;
+ }
+
+ /* configure mode */
-+ ret = drv_hash_config(hisi_ctx->hard_chn, hisi_ctx->mode, hisi_ctx->hash);
++ ret = drv_hash_cfg(hisi_ctx->hard_chn, hisi_ctx->mode, hisi_ctx->hash);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_config, ret);
++ hi_log_print_func_err(drv_hash_cfg, ret);
+ goto exit;
+ }
+
+ /* start */
+ ret = drv_hash_start(hisi_ctx->hard_chn, &hisi_ctx->mem, size);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_start, ret);
++ hi_log_print_func_err(drv_hash_start, ret);
+ goto exit;
+ }
+
+ /* wait done */
+ ret = drv_hash_wait_done(hisi_ctx->hard_chn, hisi_ctx->hash);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_wait_done, ret);
++ hi_log_print_func_err(drv_hash_wait_done, ret);
+ break;
+ }
+
@@ -209057,7 +277981,7 @@ index 0000000..7236a7e
+ msg += size;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+
+exit:
@@ -209067,9 +277991,9 @@ index 0000000..7236a7e
+/* hash message paading to align at block size */
+static hi_u32 cryp_hash_pading(hi_u32 block_size, hi_u8 *msg, hi_u32 tail_size, hi_u32 total)
+{
-+ hi_u32 pad_len = 0, min = 0;
++ hi_u32 pad_len, min;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* get min padding size */
+ if (block_size == HASH_BLOCK_SIZE_64) {
@@ -209086,36 +278010,36 @@ index 0000000..7236a7e
+ }
+
+ /* Format(binary): {data|| 0x80 || 00 00 ... || Len(64)} */
-+ crypto_memset(&msg[tail_size], HASH_BLOCK_SIZE_128 * 2 - tail_size, 0, pad_len);
++ crypto_memset(&msg[tail_size], HASH_BLOCK_SIZE_128 * MUL_VAL_2 - tail_size, 0, pad_len);
+ msg[tail_size] = HASH_PADDING_B0;
-+ tail_size += pad_len - 8;
++ tail_size += pad_len - WORD_WIDTH * MUL_VAL_2; /* Two word length left. */
+
+ /* write 8 bytes fix data length * 8 */
+ msg[tail_size++] = 0x00;
+ msg[tail_size++] = 0x00;
+ msg[tail_size++] = 0x00;
-+ msg[tail_size++] = (hi_u8)((total >> 29) & 0x07);
-+ msg[tail_size++] = (hi_u8)((total >> 21) & 0xff);
-+ msg[tail_size++] = (hi_u8)((total >> 13) & 0xff);
-+ msg[tail_size++] = (hi_u8)((total >> 5) & 0xff);
-+ msg[tail_size++] = (hi_u8)((total << 3) & 0xff);
++ msg[tail_size++] = (hi_u8)((total >> SHIFT_29BITS) & MAX_LOW_3BITS);
++ msg[tail_size++] = (hi_u8)((total >> SHIFT_21BITS) & MAX_LOW_8BITS);
++ msg[tail_size++] = (hi_u8)((total >> SHIFT_13BITS) & MAX_LOW_8BITS);
++ msg[tail_size++] = (hi_u8)((total >> SHIFT_5BITS) & MAX_LOW_8BITS);
++ msg[tail_size++] = (hi_u8)((total << SHIFT_3BITS) & MAX_LOW_8BITS);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return tail_size;
+}
+
+static hi_void *cryp_hash_create(hash_mode mode)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ cryp_hash_context *hisi_ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ hisi_ctx = crypto_calloc(1, sizeof(cryp_hash_context));
++ hisi_ctx = crypto_calloc(MUL_VAL_1, sizeof(cryp_hash_context));
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_ERROR("malloc hash context buffer failed!");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_error("malloc hash context buffer failed!");
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
+ return HI_NULL;
+ }
+
@@ -209124,13 +278048,13 @@ index 0000000..7236a7e
+
+ ret = cryp_hash_initial(hisi_ctx, mode);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_initial, ret);
++ hi_log_print_func_err(cryp_hash_initial, ret);
+ goto error1;
+ }
+
-+ crypto_memcpy(&hisi_ctx->mem, sizeof(crypto_mem), &hash_mem, sizeof(crypto_mem));
++ crypto_memcpy(&hisi_ctx->mem, sizeof(crypto_mem), &g_hash_mem, sizeof(crypto_mem));
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return hisi_ctx;
+
@@ -209145,9 +278069,9 @@ index 0000000..7236a7e
+{
+ cryp_hash_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
@@ -209155,20 +278079,20 @@ index 0000000..7236a7e
+ crypto_free(ctx);
+ ctx = HI_NULL;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static hi_s32 cryp_hash_update(hi_void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ cryp_hash_context *hisi_ctx = ctx;
-+ hi_u32 inverse_len = 0;
++ hi_u32 inverse_len;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
-+ HI_LOG_DEBUG("last: total 0x%x, block size %d, tail_len %d, chunkLen 0x%x, src %d\n", hisi_ctx->total,
++ hi_log_debug("last: total 0x%x, block size %d, tail_len %d, chunkLen 0x%x, src %d\n", hisi_ctx->total,
+ hisi_ctx->block_size, hisi_ctx->tail_len, chunkLen, src);
+
+ /* total len */
@@ -209183,29 +278107,22 @@ index 0000000..7236a7e
+ }
+
+ /* try to make up the tail data to be a block */
-+ ret = cryp_hash_chunk_copy(chunk,
-+ hisi_ctx->tail + hisi_ctx->tail_len,
-+ inverse_len,
-+ src);
++ ret = cryp_hash_chunk_copy(chunk, hisi_ctx->tail + hisi_ctx->tail_len, inverse_len, src);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_chunk_copy, ret);
++ hi_log_print_func_err(cryp_hash_chunk_copy, ret);
+ return ret;
+ }
+ hisi_ctx->tail_len += inverse_len;
+ chunk += inverse_len;
+ chunkLen -= inverse_len; /* the chunkLen may be zero */
+
-+ HI_LOG_DEBUG("new: total 0x%x, tail_len %d, chunkLen 0x%x\n", hisi_ctx->total,
-+ hisi_ctx->tail_len, chunkLen);
++ hi_log_debug("new: total 0x%x, tail_len %d, chunkLen 0x%x\n", hisi_ctx->total, hisi_ctx->tail_len, chunkLen);
+
+ /* process tail block */
+ if (hisi_ctx->tail_len == hisi_ctx->block_size) {
-+ ret = cryp_hash_process(hisi_ctx,
-+ hisi_ctx->tail,
-+ hisi_ctx->tail_len,
-+ HASH_CHUNCK_SRC_LOCAL);
++ ret = cryp_hash_process(hisi_ctx, hisi_ctx->tail, hisi_ctx->tail_len, HASH_CHUNCK_SRC_LOCAL);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_process, ret);
++ hi_log_print_func_err(cryp_hash_process, ret);
+ return ret;
+ }
+ /* new tail len */
@@ -209215,58 +278132,47 @@ index 0000000..7236a7e
+ chunkLen -= hisi_ctx->tail_len;
+
+ /* save new tail */
-+ ret = cryp_hash_chunk_copy(chunk + chunkLen,
-+ hisi_ctx->tail,
-+ hisi_ctx->tail_len,
-+ src);
++ ret = cryp_hash_chunk_copy(chunk + chunkLen, hisi_ctx->tail, hisi_ctx->tail_len, src);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_chunk_copy, ret);
++ hi_log_print_func_err(cryp_hash_chunk_copy, ret);
+ return ret;
+ }
+ }
+
-+ HI_LOG_DEBUG("new: total 0x%x, tail_len %d, chunkLen 0x%x\n", hisi_ctx->total,
-+ hisi_ctx->tail_len, chunkLen);
++ hi_log_debug("new: total 0x%x, tail_len %d, chunkLen 0x%x\n", hisi_ctx->total, hisi_ctx->tail_len, chunkLen);
+
+ /* process left block, just resurn HI_SUCCESS if the chunkLen is zero */
+ ret = cryp_hash_process(hisi_ctx, chunk, chunkLen, src);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_process, ret);
++ hi_log_print_func_err(cryp_hash_process, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_hash_finish(hi_void *ctx, hi_void *hash, hi_u32 *hashlen)
++static hi_s32 cryp_hash_finish(hi_void *ctx, hi_void *hash, hi_u32 hash_buf_len, hi_u32 *hashlen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ cryp_hash_context *hisi_ctx = ctx;
-+ hi_u32 left = 0;
++ hi_u32 left;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
+ /* padding message */
-+ left = cryp_hash_pading(hisi_ctx->block_size,
-+ hisi_ctx->tail,
-+ hisi_ctx->tail_len,
-+ hisi_ctx->total);
-+
++ left = cryp_hash_pading(hisi_ctx->block_size, hisi_ctx->tail, hisi_ctx->tail_len, hisi_ctx->total);
+ ret = cryp_hash_process(hisi_ctx, hisi_ctx->tail, left, HASH_CHUNCK_SRC_LOCAL);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_process, ret);
++ hi_log_print_func_err(cryp_hash_process, ret);
+ return ret;
+ }
+
-+ crypto_memcpy(hash,
-+ HASH_RESULT_MAX_SIZE,
-+ hisi_ctx->hash,
-+ hisi_ctx->hash_size);
++ crypto_memcpy(hash, hash_buf_len, hisi_ctx->hash, hisi_ctx->hash_size);
+ *hashlen = hisi_ctx->hash_size;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+#endif
@@ -209275,39 +278181,37 @@ index 0000000..7236a7e
+{
+ hi_u32 i = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* check availability */
-+ if ((func->create == HI_NULL)
-+ || (func->destroy == HI_NULL)
-+ || (func->update == HI_NULL)
-+ || (func->finish == HI_NULL)) {
-+ HI_LOG_ERROR("hash function is null.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((func->create == HI_NULL) || (func->destroy == HI_NULL) || (func->update == HI_NULL) ||
++ (func->finish == HI_NULL)) {
++ hi_log_error("hash function is null.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ HI_LOG_DEBUG("register hash mode %d\n", func->mode);
++ hi_log_debug("register hash mode %d\n", func->mode);
+
+ /* is it already registered? */
+ for (i = 0; i < HASH_FUNC_TAB_SIZE; i++) {
-+ if (hash_descriptor[i].valid && hash_descriptor[i].mode == func->mode) {
-+ HI_LOG_FUNC_EXIT();
++ if (g_hash_descriptor[i].valid && g_hash_descriptor[i].mode == func->mode) {
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+ }
+
+ /* find a blank spot */
+ for (i = 0; i < HASH_FUNC_TAB_SIZE; i++) {
-+ if (!hash_descriptor[i].valid) {
-+ hash_descriptor[i] = *func;
-+ hash_descriptor[i].valid = HI_TRUE;
-+ HI_LOG_FUNC_EXIT();
++ if (!g_hash_descriptor[i].valid) {
++ g_hash_descriptor[i] = *func;
++ g_hash_descriptor[i].valid = HI_TRUE;
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+ }
+
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ return HI_ERR_CIPHER_INVALID_PARAM;
+}
+
+/* hash function register */
@@ -209315,7 +278219,7 @@ index 0000000..7236a7e
+{
+ hash_func func;
+
-+ crypto_memset(&func, sizeof(func), 0 , sizeof(func));
++ crypto_memset(&func, sizeof(func), 0, sizeof(func));
+
+ /* register the hash function if supported */
+ if (capacity) {
@@ -209384,41 +278288,41 @@ index 0000000..7236a7e
+ hi_u32 i = 0;
+ hash_func *template = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* find the valid function */
+ for (i = 0; i < HASH_FUNC_TAB_SIZE; i++) {
-+ if (hash_descriptor[i].valid) {
-+ if (hash_descriptor[i].mode == mode) {
-+ template = &hash_descriptor[i];
++ if (g_hash_descriptor[i].valid) {
++ if (g_hash_descriptor[i].mode == mode) {
++ template = &g_hash_descriptor[i];
+ break;
+ }
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return template;
+}
+
+hi_s32 cryp_hash_init(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ crypto_memset(hash_descriptor, sizeof(hash_descriptor), 0, sizeof(hash_descriptor));
++ crypto_memset(g_hash_descriptor, sizeof(g_hash_descriptor), 0, sizeof(g_hash_descriptor));
+
+#ifdef CHIP_HASH_SUPPORT
+ {
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ ret = drv_hash_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_hash_init, ret);
++ hi_log_print_func_err(drv_hash_init, ret);
+ return ret;
+ }
+
+ ret = cryp_hash_create_mem();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_create_mem, ret);
++ hi_log_print_func_err(cryp_hash_create_mem, ret);
+ drv_hash_deinit();
+ return ret;
+ }
@@ -209428,98 +278332,87 @@ index 0000000..7236a7e
+ /* hash function register */
+ cryp_register_all_hash();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_void cryp_hash_deinit(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_s32 ret;
++ hi_log_func_enter();
+
+#ifdef CHIP_HASH_SUPPORT
-+ drv_hash_deinit();
-+ cryp_hash_destory_mem();
++ ret = drv_hash_deinit();
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_hash_deinit, ret);
++ }
++
++ ret = cryp_hash_destory_mem();
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_hash_destory_mem, ret);
++ return;
++ }
+#endif
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+}
-+
-+/** @}*/ /** <!-- ==== API Code end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_rsa.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_rsa.c
new file mode 100644
-index 0000000..0fa81b4
+index 0000000..373f60b
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_rsa.c
-@@ -0,0 +1,1043 @@
+@@ -0,0 +1,1048 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : driver for cryp rsa.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
++#include "cryp_rsa.h"
+#include "drv_osal_lib.h"
+#include "drv_srsa.h"
-+#include "cryp_rsa.h"
+#include "cryp_trng.h"
+#include "mbedtls/rsa.h"
++#include "mbedtls/bignum.h"
+
-+/********************** Internal Structure Definition ************************/
-+/** \addtogroup rsa */
-+/** @{*/ /** <!-- [rsa]*/
++/* Internal Structure Definition */
++#define RSA_PKCS1_TYPE_MIN_PAD_LEN 11
+
-+#define RSA_PKCS1_TYPE_MIN_PAD_LEN (11)
++/* rsa padding value 0xff. */
++#define RSA_PADDING_VAL_FF 0xFF
++
++/* rsa key len in bits */
+#define RSA_BITS_1024 1024
+#define RSA_BITS_2048 2048
+#define RSA_BITS_3072 3072
+#define RSA_BITS_4096 4096
+
-+/*! rsa mutex */
-+static crypto_mutex rsa_mutex;
-+static hi_u32 rsa_key_ca_type = HI_UNF_CIPHER_KEY_SRC_USER;
++/* rsa mutex */
++static crypto_mutex g_rsa_mutex;
++static hi_u32 g_rsa_key_ca_type = HI_CIPHER_KEY_SRC_USER;
+
-+#define KAPI_RSA_LOCK() \
-+ ret = crypto_mutex_lock(&rsa_mutex); \
-+ if (ret != HI_SUCCESS) \
-+ {\
-+ HI_LOG_ERROR("error, rsa lock failed\n");\
-+ HI_LOG_FUNC_EXIT();\
-+ return ret;\
-+ }
++#define kapi_rsa_lock_err_return() \
++ do { \
++ ret = crypto_mutex_lock(&g_rsa_mutex); \
++ if (ret != HI_SUCCESS) { \
++ hi_log_error("error, rsa lock failed\n"); \
++ return ret; \
++ } \
++ } while (0)
+
-+#define KAPI_RSA_UNLOCK() crypto_mutex_unlock(&rsa_mutex)
++#define kapi_rsa_unlock() crypto_mutex_unlock(&g_rsa_mutex)
+
-+/*! \rsa rsa soft function */
-+extern int mbedtls_mpi_exp_mod_sw(mbedtls_mpi *X, const mbedtls_mpi *A,
-+ const mbedtls_mpi *E, const mbedtls_mpi *N,
-+ mbedtls_mpi *_RR);
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup rsa drivers*/
-+/** @{*/ /** <!-- [rsa]*/
-+
-+void mbedtls_mpi_print(const mbedtls_mpi *X, const char *name)
++/* API Code for cryp rsa */
++hi_void mbedtls_mpi_print(const mbedtls_mpi *x, const char *name)
+{
+#ifdef CIPHER_DEBUG_SUPPORT
+ int ret;
+ size_t n;
-+ hi_u8 buf[512] = {0};
++ hi_u8 buf[RSA_KEY_WIDTH_4096] = {0};
+
-+ n = mbedtls_mpi_size(X);
-+ MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(X, buf, n));
++ n = mbedtls_mpi_size(x);
++ MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(x, buf, n));
+ HI_PRINT_HEX(name, (hi_u8 *)buf, n);
+
+cleanup:
@@ -209531,208 +278424,209 @@ index 0000000..0fa81b4
+static hi_s32 rsa_get_klen(unsigned long module_len, hi_u32 *keylen, rsa_key_width *width)
+{
+ if (module_len <= RSA_KEY_LEN_1024) {
-+ *keylen = 128;
++ *keylen = RSA_KEY_LEN_1024;
+ *width = RSA_KEY_WIDTH_1024;
+ } else if (module_len <= RSA_KEY_LEN_2048) {
-+ *keylen = 256;
++ *keylen = RSA_KEY_LEN_2048;
+ *width = RSA_KEY_WIDTH_2048;
+ } else if (module_len <= RSA_KEY_LEN_4096) {
-+ *keylen = 512;
++ *keylen = RSA_KEY_LEN_4096;
+ *width = RSA_KEY_WIDTH_4096;
+ } else {
-+ HI_LOG_ERROR("error, invalid key len %ld\n", module_len);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("error, invalid key len %ld\n", module_len);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_check_data(hi_u8 *N, hi_u8 *E, hi_u8 *MC, hi_u32 len)
++static hi_s32 cryp_check_data(hi_u8 *n, hi_u8 *e, hi_u8 *mc, hi_u32 len)
+{
+ hi_u32 i;
+
-+ /*MC > 0*/
++ /* MC > 0 */
+ for (i = 0; i < len; i++) {
-+ if (0 < MC[i]) {
++ if (mc[i] > 0) {
+ break;
+ }
+ }
+ if (i >= len) {
-+ HI_LOG_ERROR("RSA M/C is zero, error!\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("RSA M/C is zero, error!\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ /*MC < N*/
++ /* MC < N */
+ for (i = 0; i < len; i++) {
-+ if (MC[i] < N[i]) {
++ if (mc[i] < n[i]) {
+ break;
+ }
+ }
+ if (i >= len) {
-+ HI_LOG_ERROR("RSA M/C is larger than N, error!\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("RSA M/C is larger than N, error!\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ /*E >= 1*/
++ /* E >= 1 */
+ for (i = 0; i < len; i++) {
-+ if (E[i] > 0) {
++ if (e[i] > 0) {
+ break;
+ }
+ }
+ if (i >= len) {
-+ HI_LOG_ERROR("RSA D/E is zero, error!\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("RSA D/E is zero, error!\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ return HI_SUCCESS;
+}
+
-+static int cryp_ifep_rsa_exp_mod(hi_u32 ca_type, mbedtls_mpi *X, const mbedtls_mpi *A,
-+ const mbedtls_mpi *E, const mbedtls_mpi *N,
-+ mbedtls_mpi *_RR)
++static int cryp_ifep_rsa_exp_mod(hi_u32 ca_type, mbedtls_mpi *x, const mbedtls_mpi *a,
++ const mbedtls_mpi *e, const mbedtls_mpi *n, mbedtls_mpi *rr)
+{
-+ hi_u32 module_len = 0;
++ hi_u32 module_len;
+ hi_u8 *buf = HI_NULL;
-+ hi_u8 *n = HI_NULL, *k = HI_NULL;
-+ hi_u8 *in = HI_NULL, *out = HI_NULL;
++ hi_u8 *tmp_n = HI_NULL;
++ hi_u8 *k = HI_NULL;
++ hi_u8 *in = HI_NULL;
++ hi_u8 *out = HI_NULL;
+ hi_u32 keylen = 0;
+ rsa_key_width width = 0;
-+ mbedtls_mpi _A;
-+ hi_s32 ret = HI_FAILURE;
++ mbedtls_mpi tmp_a;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* computes valid bits of N */
-+ module_len = MAX(mbedtls_mpi_size(N), mbedtls_mpi_size(E));
++ module_len = crypto_max(mbedtls_mpi_size(n), mbedtls_mpi_size(e));
+
+ ret = rsa_get_klen(module_len, &keylen, &width);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(rsa_get_klen, ret);
++ hi_log_print_func_err(rsa_get_klen, ret);
+ return ret;
+ }
+
+ /* mallc buf to store n || k(e or d) || in || out */
-+ buf = crypto_malloc(keylen * 4);
++ buf = crypto_calloc(MUL_VAL_4, keylen);
+ if (buf == HI_NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_malloc, HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_print_func_err(crypto_calloc, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ /* zero */
-+ crypto_memset(buf, keylen * 4, 0, keylen * 4);
-+
-+ n = buf;
-+ k = n + keylen;
++ tmp_n = buf;
++ k = tmp_n + keylen;
+ in = k + keylen;
+ out = in + keylen;
+
-+ mbedtls_mpi_init(&_A);
-+ CHECK_EXIT(mbedtls_mpi_mod_mpi(&_A, A, N));
++ mbedtls_mpi_init(&tmp_a);
++ crypto_chk_err_exit(mbedtls_mpi_mod_mpi(&tmp_a, a, n));
+
+ /* read A, E, N */
-+ CHECK_EXIT(mbedtls_mpi_write_binary(&_A, in, keylen));
-+ CHECK_EXIT(mbedtls_mpi_write_binary(E, k, keylen));
-+ CHECK_EXIT(mbedtls_mpi_write_binary(N, n, keylen));
++ crypto_chk_err_exit(mbedtls_mpi_write_binary(&tmp_a, in, keylen));
++ crypto_chk_err_exit(mbedtls_mpi_write_binary(e, k, keylen));
++ crypto_chk_err_exit(mbedtls_mpi_write_binary(n, tmp_n, keylen));
+
-+ /* key and data valid ?*/
-+ CHECK_EXIT(cryp_check_data(n, k, in, keylen));
++ /* key and data valid ? */
++ crypto_chk_err_exit(cryp_check_data(tmp_n, k, in, keylen));
+
+ /* out = in ^ k mod n */
-+ ret = drv_ifep_rsa_exp_mod(ca_type, n, k, in, out, width);
++ ret = drv_ifep_rsa_exp_mod(ca_type, tmp_n, k, in, out, width);
+ if (ret == HI_SUCCESS) {
+ /* write d */
-+ mbedtls_mpi_read_binary(X, out, keylen);
++ mbedtls_mpi_read_binary(x, out, keylen);
+ }
+
+exit__:
+
-+ mbedtls_mpi_free(&_A);
++ mbedtls_mpi_free(&tmp_a);
+ crypto_free(buf);
+ buf = HI_NULL;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ret;
+}
+#endif
+
-+int mbedtls_mpi_exp_mod(mbedtls_mpi *X, const mbedtls_mpi *A,
-+ const mbedtls_mpi *E,
-+ const mbedtls_mpi *N,
-+ mbedtls_mpi *_RR)
++int mbedtls_mpi_exp_mod(mbedtls_mpi *x, const mbedtls_mpi *a, const mbedtls_mpi *e, const mbedtls_mpi *n,
++ mbedtls_mpi *rr)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+#if defined(CHIP_IFEP_RSA_VER_V100)
-+ hi_u32 elen = 0;
++ hi_u32 elen;
+#endif
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(X == HI_NULL);
-+ HI_LOG_CHECK_PARAM(A == HI_NULL);
-+ HI_LOG_CHECK_PARAM(E == HI_NULL);
-+ HI_LOG_CHECK_PARAM(N == HI_NULL);
++ hi_log_chk_param_return(x == HI_NULL);
++ hi_log_chk_param_return(a == HI_NULL);
++ hi_log_chk_param_return(e == HI_NULL);
++ hi_log_chk_param_return(n == HI_NULL);
+
-+ mbedtls_mpi_print(A, "M");
-+ mbedtls_mpi_print(E, "E");
-+ mbedtls_mpi_print(N, "N");
++ mbedtls_mpi_print(a, "M");
++ mbedtls_mpi_print(e, "E");
++ mbedtls_mpi_print(n, "N");
+
+#if defined(CHIP_IFEP_RSA_VER_V100)
-+ elen = mbedtls_mpi_size(E);
++ elen = mbedtls_mpi_size(e);
+ if (elen <= RSA_KEY_LEN_4096) {
+ /* The private key may be not from user when generate rsa key pare
+ * in this case use klad key will failed.
+ */
-+ ret = cryp_ifep_rsa_exp_mod(rsa_key_ca_type, X, A, E, N, _RR);
-+ } else
-+#endif
-+ {
-+ if (rsa_key_ca_type != HI_UNF_CIPHER_KEY_SRC_USER) {
-+ HI_LOG_ERROR("sofrware rsa nonsupport klad key\n");
++ ret = cryp_ifep_rsa_exp_mod(g_rsa_key_ca_type, x, a, e, n, rr);
++ } else {
++ if (g_rsa_key_ca_type != HI_CIPHER_KEY_SRC_USER) {
++ hi_log_error("sofrware rsa nonsupport klad key\n");
+ return HI_ERR_CIPHER_ILLEGAL_KEY;
+ }
+
-+ ret = mbedtls_mpi_exp_mod_sw(X, A, E, N, _RR);
++ ret = mbedtls_mpi_exp_mod_sw(x, a, e, n, rr);
++ }
++#else
++ if (g_rsa_key_ca_type != HI_CIPHER_KEY_SRC_USER) {
++ hi_log_error("sofrware rsa nonsupport klad key\n");
++ return HI_ERR_CIPHER_ILLEGAL_KEY;
+ }
+
-+ mbedtls_mpi_print(X, "X");
++ ret = mbedtls_mpi_exp_mod_sw(x, a, e, n, rr);
++#endif
++ mbedtls_mpi_print(x, "X");
+
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa mpi_exp_mod failed, ret = 0x%x\n", ret);
++ hi_log_error("rsa mpi_exp_mod failed, ret = 0x%x\n", ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+int cryp_rsa_init(void)
++int cryp_rsa_init(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ crypto_mutex_init(&rsa_mutex);
++ crypto_mutex_init(&g_rsa_mutex);
+
+#if defined(CHIP_IFEP_RSA_VER_V100)
+ {
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ ret = drv_rsa_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_rsa_init, ret);
++ hi_log_print_func_err(drv_rsa_init, ret);
+ return ret;
+ }
+ }
+#endif
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void cryp_rsa_deinit(void)
++hi_void cryp_rsa_deinit(hi_void)
+{
+#if defined(CHIP_IFEP_RSA_VER_V100)
+ rsa_capacity capacity;
@@ -209745,20 +278639,35 @@ index 0000000..0fa81b4
+ }
+#endif
+
-+ crypto_mutex_destroy(&rsa_mutex);
++ crypto_mutex_destroy(&g_rsa_mutex);
+}
+
-+int mbedtls_get_random(void *param, hi_u8 *rand, size_t size)
++int mbedtls_get_random(hi_void *param, hi_u8 *rand, size_t size)
+{
+ hi_u32 i;
-+ hi_u32 randnum = 0;
++ hi_u32 randnum, left_size;
+
-+ for (i = 0; i < size; i += 4) {
-+ cryp_trng_get_random(&randnum, -1);
-+ rand[i + 3] = (hi_u8)(randnum >> 24) & 0xFF;
-+ rand[i + 2] = (hi_u8)(randnum >> 16) & 0xFF;
-+ rand[i + 1] = (hi_u8)(randnum >> 8) & 0xFF;
-+ rand[i + 0] = (hi_u8)(randnum) & 0xFF;
++ for (i = 0; i < size; i += WORD_WIDTH) {
++ cryp_trng_get_random(&randnum, CRYP_TRNG_TIMEOUT);
++
++ left_size = (size - i) > WORD_WIDTH ? WORD_WIDTH : (size - i);
++ switch (left_size) {
++ case WORD_IDX_4:
++ rand[i + WORD_IDX_3] = (hi_u8)(randnum >> SHIFT_24BITS) & MAX_LOW_8BITS;
++ /* fall through */
++ case WORD_IDX_3:
++ rand[i + WORD_IDX_2] = (hi_u8)(randnum >> SHIFT_16BITS) & MAX_LOW_8BITS;
++ /* fall through */
++ case WORD_IDX_2:
++ rand[i + WORD_IDX_1] = (hi_u8)(randnum >> SHIFT_8BITS) & MAX_LOW_8BITS;
++ /* fall through */
++ case WORD_IDX_1:
++ rand[i + WORD_IDX_0] = (hi_u8)(randnum) & MAX_LOW_8BITS;
++ break;
++ default:
++ hi_log_error("left size %u is error\n", left_size);
++ return HI_ERR_CIPHER_INVALID_LEN;
++ }
+ }
+
+ return HI_SUCCESS;
@@ -209766,9 +278675,9 @@ index 0000000..0fa81b4
+
+static hi_s32 cryp_rsa_init_key(cryp_rsa_key *key, hi_u32 *mode, mbedtls_rsa_context *rsa)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ mbedtls_mpi_init(&rsa->N);
+ mbedtls_mpi_init(&rsa->E);
@@ -209777,39 +278686,39 @@ index 0000000..0fa81b4
+ mbedtls_mpi_init(&rsa->Q);
+ mbedtls_mpi_init(&rsa->DP);
+ mbedtls_mpi_init(&rsa->DQ);
-+ mbedtls_mpi_init(&rsa->Q);
++ mbedtls_mpi_init(&rsa->QP);
+
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->N, key->n, key->klen));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->N, key->n, key->klen));
+ rsa->len = key->klen;
+ if ((rsa->len < RSA_MIN_KEY_LEN) || (rsa->len > RSA_MAX_KEY_LEN)) {
-+ HI_LOG_ERROR("RSA invalid keylen: 0x%x!\n", (hi_u32)rsa->len);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ ret = HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("RSA invalid keylen: 0x%x!\n", (hi_u32)rsa->len);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ ret = HI_ERR_CIPHER_INVALID_PARAM;
+ goto exit__;
+ }
+
+ if (key->public) {
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->E, (hi_u8 *)&key->e, WORD_WIDTH));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->E, (hi_u8 *)&key->e, WORD_WIDTH));
+ *mode = MBEDTLS_RSA_PUBLIC;
+ } else {
+ if (key->d != HI_NULL) { /* Non CRT */
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->D, key->d, key->klen));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->D, key->d, key->klen));
+ *mode = MBEDTLS_RSA_PRIVATE;
+ } else { /* CRT */
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->P, key->p, key->klen / 2));
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->Q, key->q, key->klen / 2));
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->DP, key->dp, key->klen / 2));
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->DQ, key->dq, key->klen / 2));
-+ CHECK_EXIT(mbedtls_mpi_read_binary(&rsa->QP, key->qp, key->klen / 2));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->P, key->p, key->klen / MUL_VAL_2));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->Q, key->q, key->klen / MUL_VAL_2));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->DP, key->dp, key->klen / MUL_VAL_2));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->DQ, key->dq, key->klen / MUL_VAL_2));
++ crypto_chk_err_exit(mbedtls_mpi_read_binary(&rsa->QP, key->qp, key->klen / MUL_VAL_2));
+ *mode = MBEDTLS_RSA_PRIVATE;
+ }
+ }
+
-+ rsa_key_ca_type = key->ca_type;
++ g_rsa_key_ca_type = key->ca_type;
+
-+ HI_LOG_DEBUG("mode %d, e 0x%x\n", *mode, key->e);
++ hi_log_debug("mode %d, e 0x%x\n", *mode, key->e);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+
+exit__:
@@ -209821,14 +278730,14 @@ index 0000000..0fa81b4
+ mbedtls_mpi_free(&rsa->Q);
+ mbedtls_mpi_free(&rsa->DP);
+ mbedtls_mpi_free(&rsa->DQ);
-+ mbedtls_mpi_free(&rsa->Q);
++ mbedtls_mpi_free(&rsa->QP);
+
+ return ret;
+}
+
-+static void cryp_rsa_deinit_key(mbedtls_rsa_context *rsa)
++static hi_void cryp_rsa_deinit_key(mbedtls_rsa_context *rsa)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ mbedtls_mpi_free(&rsa->N);
+ mbedtls_mpi_free(&rsa->E);
@@ -209837,168 +278746,190 @@ index 0000000..0fa81b4
+ mbedtls_mpi_free(&rsa->Q);
+ mbedtls_mpi_free(&rsa->DP);
+ mbedtls_mpi_free(&rsa->DQ);
-+ mbedtls_mpi_free(&rsa->Q);
++ mbedtls_mpi_free(&rsa->QP);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+}
+
+static hi_s32 cryp_rsa_get_alg(hi_u32 scheme, int *padding, int *hash_id, int *hashlen)
+{
+ switch (scheme) {
-+ case HI_CIPHER_RSA_ENC_SCHEME_NO_PADDING:
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0:
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_1:
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_2: {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_NO_PADDING:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_0:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_1:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_2:
+ *padding = 0x00;
+ *hash_id = 0;
+ *hashlen = 0;
+ break;
-+ }
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_PKCS1_V1_5: {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_PKCS1_V1_5:
+ *padding = MBEDTLS_RSA_PKCS_V15;
+ *hash_id = 0;
+ *hashlen = 0;
+ break;
-+ }
-+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA1: {
++ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA1:
+ *padding = MBEDTLS_RSA_PKCS_V15;
+ *hash_id = MBEDTLS_MD_SHA1;
+ *hashlen = SHA1_RESULT_SIZE;
+ break;
-+ }
-+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA224: {
++ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA224:
+ *padding = MBEDTLS_RSA_PKCS_V15;
+ *hash_id = MBEDTLS_MD_SHA224;
+ *hashlen = SHA224_RESULT_SIZE;
+ break;
-+ }
-+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA256: {
++ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA256:
+ *padding = MBEDTLS_RSA_PKCS_V15;
+ *hash_id = MBEDTLS_MD_SHA256;
+ *hashlen = SHA256_RESULT_SIZE;
+ break;
-+ }
-+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA384: {
++ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA384:
+ *padding = MBEDTLS_RSA_PKCS_V15;
+ *hash_id = MBEDTLS_MD_SHA384;
+ *hashlen = SHA384_RESULT_SIZE;
+ break;
-+ }
-+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA512: {
++ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA512:
+ *padding = MBEDTLS_RSA_PKCS_V15;
+ *hash_id = MBEDTLS_MD_SHA512;
+ *hashlen = SHA512_RESULT_SIZE;
+ break;
-+ }
+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA1:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA1: {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA1:
+ *padding = MBEDTLS_RSA_PKCS_V21;
+ *hash_id = MBEDTLS_MD_SHA1;
+ *hashlen = SHA1_RESULT_SIZE;
+ break;
-+ }
+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA224:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA224: {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA224:
+ *padding = MBEDTLS_RSA_PKCS_V21;
+ *hash_id = MBEDTLS_MD_SHA224;
+ *hashlen = SHA224_RESULT_SIZE;
+ break;
-+ }
+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA256:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA256: {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA256:
+ *padding = MBEDTLS_RSA_PKCS_V21;
+ *hash_id = MBEDTLS_MD_SHA256;
+ *hashlen = SHA256_RESULT_SIZE;
+ break;
-+ }
+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA384:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA384: {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA384:
+ *padding = MBEDTLS_RSA_PKCS_V21;
+ *hash_id = MBEDTLS_MD_SHA384;
+ *hashlen = SHA384_RESULT_SIZE;
+ break;
-+ }
+ case HI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA512:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA512: {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA512:
+ *padding = MBEDTLS_RSA_PKCS_V21;
+ *hash_id = MBEDTLS_MD_SHA512;
+ *hashlen = SHA512_RESULT_SIZE;
+ break;
-+ }
-+ default: {
-+ HI_LOG_ERROR("RSA padding mode error, mode = 0x%x.\n", scheme);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
++ default:
++ hi_log_error("RSA padding mode error, mode = 0x%x.\n", scheme);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ HI_LOG_DEBUG("padding %d, hash_id %d, hashlen %d\n", *padding, *hash_id, *hashlen);
++ hi_log_debug("padding %d, hash_id %d, hashlen %d\n", *padding, *hash_id, *hashlen);
++ return HI_SUCCESS;
++}
++
++/*
++ * PKCS #1: block type 0, 1, 2 message padding.
++ * description: EB = 00 || BT || PS || 00 || D
++ * description: PS_LEN >= 8, mlen < key_len - 11
++ */
++static hi_s32 ext_rsa_calc(mbedtls_rsa_context *rsa, hi_u32 mode, const hi_u8 *in, hi_u8 *out, hi_u32 len)
++{
++ hi_s32 ret;
++
++ crypto_unused(len);
++
++ if (mode == MBEDTLS_RSA_PUBLIC) {
++ ret = mbedtls_rsa_public(rsa, in, out);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_rsa_public, ret);
++ return HI_ERR_CIPHER_RSA_CRYPT_FAILED;
++ }
++ } else {
++ ret = mbedtls_rsa_private(rsa, HI_NULL, 0, in, out);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_rsa_private, ret);
++ return HI_ERR_CIPHER_RSA_CRYPT_FAILED;
++ }
++ }
+
+ return HI_SUCCESS;
+}
+
-+/*PKCS #1: block type 0,1,2 message padding*/
-+/*************************************************
-+EB = 00 || BT || PS || 00 || D
-+
-+PS_LEN >= 8, mlen < key_len - 11
-+*************************************************/
-+static hi_s32 rsa_padding_add_pkcs1_type(mbedtls_rsa_context *rsa, hi_u32 mode, hi_u32 klen,
-+ hi_u8 bt, hi_u8 *in, hi_u8 inlen, hi_u8 *out)
++static hi_s32 rsa_pkcs1_block_padding(hi_u8 bt, hi_u8 *buf, hi_u32 buf_len)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 plen = 0;
-+ hi_u8 *peb = HI_NULL;
-+ hi_u32 i = 0;
-+
-+ HI_LOG_FUNC_ENTER();
-+
-+ if (inlen > klen - RSA_PKCS1_TYPE_MIN_PAD_LEN) {
-+ HI_LOG_ERROR("klen is invalid.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ peb = out;
-+
-+ /* first byte is 0x00 */
-+ *(peb++) = 0;
-+
-+ /* Private Key BT (Block Type) */
-+ *(peb++) = bt;
-+
-+ /* The padding string PS shall consist of k-3-||D|| octets */
-+ plen = klen - 3 - inlen;
+ switch (bt) {
-+ case 0x00: {
-+ /* For block type 00, the octets shall have value 00 */
-+ crypto_memset(peb, plen, 0x00, plen);
++ case RSA_BLOCK_YTPE_0:
++ /* For block type 00, the octets shall have value 0x00 */
++ crypto_memset(buf, buf_len, 0x00, buf_len);
+ break;
-+ }
-+ case 0x01: {
-+ /* for block type 01, they shall have value FF */
-+ crypto_memset(peb, plen, 0xFF, plen);
++ case RSA_BLOCK_YTPE_1:
++ /* for block type 01, they shall have value 0xFF */
++ crypto_memset(buf, buf_len, RSA_PADDING_VAL_FF, buf_len);
+ break;
-+ }
-+ case 0x02: {
++ case RSA_BLOCK_YTPE_2: {
++ hi_s32 i;
++
+ /* for block type 02, they shall be pseudorandomly generated and nonzero. */
-+ (hi_void)mbedtls_get_random(HI_NULL, peb, plen);
++ (hi_void)mbedtls_get_random(HI_NULL, buf, buf_len);
+
+ /* make sure nonzero */
-+ for (i = 0; i < plen; i++) {
-+ if (0x00 == peb[i]) {
-+ peb[i] = 0x01;
++ for (i = 0; i < buf_len; i++) {
++ if (buf[i] == 0) {
++ buf[i] = CRYPTO_NUM_1;
+ }
+ }
+ break;
+ }
+ default: {
-+ HI_LOG_ERROR("BT(0x%x) is invalid.\n", plen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("BT(0x%x) is invalid.\n", buf_len);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
+
++ return HI_SUCCESS;
++}
++
++static hi_s32 rsa_padding_add_pkcs1_type(mbedtls_rsa_context *rsa, rsa_padding_pack *pad)
++{
++ hi_s32 ret;
++ hi_u32 plen;
++ hi_u8 *peb = HI_NULL;
++
++ hi_log_func_enter();
++
++ crypto_unused(pad->out_len);
++
++ if (pad->in_len > pad->klen - RSA_PKCS1_TYPE_MIN_PAD_LEN) {
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ peb = pad->out;
++
++ /* first byte is 0x00 */
++ *(peb++) = 0;
++
++ /* Private Key BT (Block Type) */
++ *(peb++) = pad->bt;
++
++ /*
++ * The padding string PS shall consist of k-3-||D|| octets, 3 bytes is used by 0x00||BT||...||0x00, the last 0
++ * follow PS.
++ */
++ plen = pad->klen - CRYPTO_NUM_3 - pad->in_len;
++
++ ret = rsa_pkcs1_block_padding(pad->bt, peb, plen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_pkcs1_block_padding, ret);
++ return ret;
++ }
++
+ /* skip the padding string */
+ peb += plen;
+
@@ -210006,712 +278937,635 @@ index 0000000..0fa81b4
+ *(peb++) = 0x00;
+
+ /* input data */
-+ crypto_memcpy(peb, inlen, in, inlen);
++ crypto_memcpy(peb, pad->in_len, pad->in, pad->in_len);
+
-+ if (mode == MBEDTLS_RSA_PUBLIC) {
-+ ret = mbedtls_rsa_public(rsa, out, out);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa public failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_public, ret);
-+ return HI_ERR_CIPHER_RSA_CRYPT_FAILED;
-+ }
-+ } else {
-+ ret = mbedtls_rsa_private(rsa, HI_NULL, 0, out, out);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa private failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_private, ret);
-+ return HI_ERR_CIPHER_RSA_CRYPT_FAILED;
-+ }
++ ret = ext_rsa_calc(rsa, pad->mode, pad->out, pad->out, *pad->out_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ext_rsa_calc, ret);
++ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/*PKCS #1: block type 0,1,2 message padding*/
-+/*************************************************
-+EB = 00 || BT || PS || 00 || D
-+
-+PS_LEN >= 8, mlen < key_len - 11
-+*************************************************/
-+static hi_s32 rsa_padding_check_pkcs1_type(mbedtls_rsa_context *rsa, hi_u32 klen, hi_u32 mode,
-+ hi_u8 bt, hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen)
++/*
++ * PKCS #1: block type 0, 1, 2 message padding.
++ * description: EB = 00 || BT || PS || 00 || D.
++ * description: PS_LEN >= 8, mlen < key_len - 11.
++ */
++static hi_s32 rsa_pkcs1_chk_block_padding(hi_u8 *peb, hi_u32 *idx, rsa_padding_pack *pad)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u8 *peb = HI_NULL;
++ hi_u32 offset = *idx;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ if (mode == MBEDTLS_RSA_PUBLIC) {
-+ ret = mbedtls_rsa_public(rsa, in, in);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa public failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_public, ret);
-+ return HI_ERR_CIPHER_RSA_CRYPT_FAILED;
-+ }
-+ } else {
-+ ret = mbedtls_rsa_private(rsa, HI_NULL, 0, in, in);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa private failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_private, ret);
-+ return HI_ERR_CIPHER_RSA_CRYPT_FAILED;
-+ }
-+ }
-+
-+ *outlen = 0x00;
-+ peb = in;
-+
-+ /* first byte must be 0x00 */
-+ if (*peb != 0x00) {
-+ HI_LOG_ERROR("EB[0] != 0x00.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+ peb++;
-+
-+ /* Private Key BT (Block Type) */
-+ if (*peb != bt) {
-+ HI_LOG_ERROR("EB[1] != BT(0x%x).\n", bt);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+ peb++;
-+
-+ switch (bt) {
-+ case 0x00:
++ switch (pad->bt) {
++ case RSA_BLOCK_YTPE_0:
+ /* For block type 00, the octets shall have value 00 */
-+ for (; peb < in + inlen - 1; peb++) {
-+ if ((*peb == 0x00) && (*(peb + 1) != 0)) {
++ for (; offset < pad->in_len - 1; offset++) {
++ if ((peb[offset] == 0x00) && (peb[offset + 1] != 0)) {
+ break;
+ }
+ }
+ break;
-+ case 0x01:
++ case RSA_BLOCK_YTPE_1:
+ /* For block type 0x01 the octets shall have value 0xFF */
-+ for (; peb < in + inlen - 1; peb++) {
-+ if (*peb == 0xFF) {
++ for (; offset < pad->in_len - 1; offset++) {
++ if (peb[offset] == 0xFF) {
+ continue;
-+ } else if (*peb == 0x00) {
++ } else if (peb[offset] == 0x00) {
+ break;
+ } else {
-+ peb = in + inlen - 1;
++ offset = pad->in_len - 1;
+ break;
+ }
+ }
+ break;
-+ case 0x02:
++ case RSA_BLOCK_YTPE_2:
+ /* for block type 02, they shall be pseudorandomly generated and nonzero. */
-+ for (; peb < in + inlen - 1; peb++) {
-+ if (0x00 == *peb) {
++ for (; offset < pad->in_len - 1; offset++) {
++ if (peb[offset] == 0) {
+ break;
+ }
+ }
+ break;
+ default:
-+ HI_LOG_ERROR("BT(0x%x) is invalid.\n", bt);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("BT(0x%x) is invalid.\n", pad->bt);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ if (peb >= (in + inlen - 1)) {
-+ HI_LOG_ERROR("PS Error.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if (offset >= pad->in_len - 1) {
++ hi_log_error("PS Error.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ /* skip 0x00 after PS */
-+ peb++;
-+
-+ /* get payload data */
-+ *outlen = in + klen - peb;
-+ crypto_memcpy(out, klen, peb, *outlen);
-+
-+ HI_LOG_FUNC_EXIT();
++ *idx = offset;
+ return HI_SUCCESS;
+}
+
-+static hi_s32 rsa_no_padding(mbedtls_rsa_context *rsa, hi_u32 klen, hi_u32 mode,
-+ hi_u8 *in, hi_u32 inlen, hi_u8 *out)
++static hi_s32 rsa_padding_check_pkcs1_type(mbedtls_rsa_context *rsa, rsa_padding_pack *pad)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
++ hi_u8 *peb = HI_NULL;
++ hi_u32 idx;
++
++ hi_log_func_enter();
++
++ ret = ext_rsa_calc(rsa, pad->mode, pad->in, pad->in, pad->in_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ext_rsa_calc, ret);
++ return ret;
++ }
++
++ *(pad->out_len) = 0x00;
++ peb = pad->in;
++ idx = 0;
++
++ /* first byte must be 0x00 */
++ if (peb[idx] != 0x00) {
++ hi_log_error("EB[0] != 0x00.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++ idx++;
++
++ /* Private Key BT (Block Type) */
++ if (peb[idx] != pad->bt) {
++ hi_log_error("EB[1] != BT(0x%x).\n", pad->bt);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++ idx++;
++
++ /* Block Type padding. */
++ ret = rsa_pkcs1_chk_block_padding(peb, &idx, pad);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_pkcs1_chk_block_padding, ret);
++ return ret;
++ }
++
++ /* skip 0x00 after PS */
++ idx++;
++
++ /* get payload data */
++ *(pad->out_len) = pad->klen - idx;
++ crypto_memcpy(pad->out, pad->klen, &peb[idx], *(pad->out_len));
++
++ hi_log_func_exit();
++ return HI_SUCCESS;
++}
++
++static hi_s32 rsa_no_padding(mbedtls_rsa_context *rsa, rsa_padding_pack *no_pad)
++{
++ hi_s32 ret;
+ hi_u8 *data = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if (inlen > klen) {
-+ HI_LOG_ERROR("input length %d invalid.\n", inlen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if (no_pad->in_len > no_pad->klen) {
++ hi_log_error("input length %d invalid.\n", no_pad->in_len);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ /* mallc data buf */
+ data = crypto_malloc(RSA_MAX_KEY_LEN);
+ if (data == HI_NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_malloc, HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_print_func_err(crypto_malloc, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
+ crypto_memset(data, RSA_MAX_KEY_LEN, 0, RSA_MAX_KEY_LEN);
-+ crypto_memcpy(data + klen - inlen, RSA_MAX_KEY_LEN, in, inlen);
++ crypto_memcpy(data + no_pad->klen - no_pad->in_len, RSA_MAX_KEY_LEN, no_pad->in, no_pad->in_len);
+
-+ if (mode == MBEDTLS_RSA_PUBLIC) {
-+ ret = mbedtls_rsa_public(rsa, data, out);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa public failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_public, ret);
-+ crypto_free(data);
-+ data = HI_NULL;
-+ return HI_ERR_CIPHER_RSA_CRYPT_FAILED;
-+ }
-+ } else {
-+ ret = mbedtls_rsa_private(rsa, HI_NULL, 0, data, out);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa private failed, ret = %d.\n", ret);
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_private, ret);
-+ crypto_free(data);
-+ data = HI_NULL;
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
++ ret = ext_rsa_calc(rsa, no_pad->mode, data, no_pad->out, no_pad->in_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ext_rsa_calc, ret);
++ crypto_free(data);
++ data = HI_NULL;
++ return ret;
+ }
+
+ crypto_free(data);
+ data = HI_NULL;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 cryp_rsa_encrypt(cryp_rsa_key *key, hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen, hi_u8 *out, hi_u32 *outlen)
++static hi_s32 ext_rsa_encrypt(hi_cipher_rsa_encrypt_scheme scheme, mbedtls_rsa_context *rsa, rsa_padding_pack *pad)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 mode = 0;
++ hi_s32 ret;
++
++ switch (scheme) {
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_NO_PADDING:
++ ret = rsa_no_padding(rsa, pad);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_no_padding, ret);
++ return ret;
++ }
++ break;
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_0:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_1:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_2:
++ pad->bt = scheme - HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_0;
++ ret = rsa_padding_add_pkcs1_type(rsa, pad);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_padding_add_pkcs1_type, ret);
++ return ret;
++ }
++ break;
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA1:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA224:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA256:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA384:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA512:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_PKCS1_V1_5:
++ ret = mbedtls_rsa_pkcs1_encrypt(rsa, mbedtls_get_random, HI_NULL, pad->mode, pad->in_len, pad->in,
++ pad->out);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_rsa_pkcs1_encrypt, ret);
++ return ret;
++ }
++ break;
++ default:
++ hi_log_error("RSA padding mode error, mode = 0x%x.\n", scheme);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ return HI_SUCCESS;
++}
++
++hi_s32 cryp_rsa_encrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa_crypt)
++{
++ hi_s32 ret;
+ int padding = 0;
+ int hash_id = 0;
+ int hashlen = 0;
-+ hi_u32 bt = 0;
+ mbedtls_rsa_context rsa;
++ rsa_padding_pack pad;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(key == HI_NULL);
-+ HI_LOG_CHECK_PARAM(in == HI_NULL);
-+ HI_LOG_CHECK_PARAM(out == HI_NULL);
-+ HI_LOG_CHECK_PARAM(outlen == HI_NULL);
-+ HI_LOG_CHECK_PARAM(key->klen > RSA_KEY_LEN_4096);
-+ HI_LOG_CHECK_PARAM(inlen > key->klen);
-+ HI_LOG_CHECK_PARAM(key->ca_type >= HI_CIPHER_KEY_SRC_BUTT);
++ hi_log_chk_param_return(key == HI_NULL);
++ hi_log_chk_param_return(rsa_crypt == HI_NULL);
++ hi_log_chk_param_return(rsa_crypt->in == HI_NULL);
++ hi_log_chk_param_return(rsa_crypt->out == HI_NULL);
++ hi_log_chk_param_return(key->klen > RSA_KEY_LEN_4096);
++ hi_log_chk_param_return(rsa_crypt->in_len > key->klen);
++ hi_log_chk_param_return(key->ca_type >= HI_CIPHER_KEY_SRC_BUTT);
+
-+ ret = cryp_rsa_get_alg(scheme, &padding, &hash_id, &hashlen);
++ ret = cryp_rsa_get_alg(rsa_crypt->scheme, &padding, &hash_id, &hashlen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_get_alg failed");
-+ HI_LOG_PRINT_ERR_CODE(ret);
++ hi_log_print_func_err(cryp_rsa_get_alg, ret);
+ return ret;
+ }
+
-+ KAPI_RSA_LOCK();
++ kapi_rsa_lock_err_return();
+
+ mbedtls_rsa_init(&rsa, padding, hash_id);
++ crypto_memset(&pad, sizeof(pad), 0, sizeof(pad));
+
-+ ret = cryp_rsa_init_key(key, &mode, &rsa);
++ ret = cryp_rsa_init_key(key, &pad.mode, &rsa);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_init_key failed");
-+ HI_LOG_PRINT_ERR_CODE(ret);
-+ KAPI_RSA_UNLOCK();
++ hi_log_print_func_err(cryp_rsa_init_key, ret);
++ kapi_rsa_unlock();
+ return ret;
+ }
+
-+ switch (scheme) {
-+ case HI_CIPHER_RSA_ENC_SCHEME_NO_PADDING: {
-+ ret = rsa_no_padding(&rsa, key->klen, mode, in, inlen, out);
-+ break;
-+ }
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0:
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_1:
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_2: {
-+ bt = scheme - HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0;
-+ ret = rsa_padding_add_pkcs1_type(&rsa, mode, key->klen, bt, in, inlen, out);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa add pkcs1_type failed, ret = 0x%x", ret);
-+ HI_LOG_PRINT_FUNC_ERR(rsa_padding_add_pkcs1_type, ret);
-+ ret = HI_ERR_CIPHER_FAILED_ENCRYPT;
-+ }
-+ break;
-+ }
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA1:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA224:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA256:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA384:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA512:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_PKCS1_V1_5: {
-+ ret = mbedtls_rsa_pkcs1_encrypt(&rsa, mbedtls_get_random,
-+ HI_NULL, mode, inlen, in, out);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa pkcs1 encrypt failed, ret = %d", ret);
-+ HI_LOG_PRINT_FUNC_ERR(rsa_padding_add_pkcs1_type, ret);
-+ ret = HI_ERR_CIPHER_FAILED_ENCRYPT;
-+ }
-+ break;
-+ }
-+ default: {
-+ HI_LOG_ERROR("RSA padding mode error, mode = 0x%x.\n", scheme);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ ret = HI_ERR_CIPHER_INVALID_PARA;
-+ break;
-+ }
-+ }
-+
-+ if (ret == HI_SUCCESS) {
-+ *outlen = key->klen;
++ pad.in = rsa_crypt->in;
++ pad.in_len = rsa_crypt->in_len;
++ pad.out = rsa_crypt->out;
++ pad.out_len = &rsa_crypt->out_len;
++ pad.klen = key->klen;
++ ret = ext_rsa_encrypt(rsa_crypt->scheme, &rsa, &pad);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ext_rsa_encrypt, ret);
++ cryp_rsa_deinit_key(&rsa);
++ kapi_rsa_unlock();
++ return ret;
+ }
+
++ rsa_crypt->out_len = key->klen;
+ cryp_rsa_deinit_key(&rsa);
-+
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa encrypt failed, scheme %d, ret = 0x%x\n", scheme, ret);
-+ KAPI_RSA_UNLOCK();
-+ return ret;
-+ }
-+
-+ KAPI_RSA_UNLOCK();
-+ HI_LOG_FUNC_EXIT();
-+
++ kapi_rsa_unlock();
++ hi_log_func_exit();
+ return ret;
+}
+
-+hi_s32 cryp_rsa_decrypt(cryp_rsa_key *key, hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen, hi_u8 *out, hi_u32 *outlen)
++static hi_s32 ext_rsa_decrypt(hi_cipher_rsa_encrypt_scheme scheme, mbedtls_rsa_context *rsa, rsa_padding_pack *pad)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 mode = 0;
-+ int padding = 0;
-+ int hash_id = 0;
-+ int hashlen = 0;
-+ hi_u32 bt = 0;
-+ size_t outsize = 0;
-+ mbedtls_rsa_context rsa;
-+
-+ HI_LOG_FUNC_ENTER();
-+
-+ HI_LOG_CHECK_PARAM(key == HI_NULL);
-+ HI_LOG_CHECK_PARAM(in == HI_NULL);
-+ HI_LOG_CHECK_PARAM(out == HI_NULL);
-+ HI_LOG_CHECK_PARAM(outlen == HI_NULL);
-+ HI_LOG_CHECK_PARAM(key->klen > RSA_KEY_LEN_4096);
-+ HI_LOG_CHECK_PARAM(inlen != key->klen);
-+ HI_LOG_CHECK_PARAM(key->ca_type >= HI_CIPHER_KEY_SRC_BUTT);
-+
-+ ret = cryp_rsa_get_alg(scheme, &padding, &hash_id, &hashlen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_sign_get_alg failed");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_get_alg, ret);
-+ return ret;
-+ }
-+
-+ KAPI_RSA_LOCK();
-+
-+ mbedtls_rsa_init(&rsa, padding, hash_id);
-+
-+ ret = cryp_rsa_init_key(key, &mode, &rsa);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_init_key failed");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_init_key, ret);
-+ KAPI_RSA_UNLOCK();
-+ return ret;
-+ }
++ hi_s32 ret;
++ size_t out_size = 0;
+
+ switch (scheme) {
-+ case HI_CIPHER_RSA_ENC_SCHEME_NO_PADDING: {
-+ ret = rsa_no_padding(&rsa, key->klen, mode, in, inlen, out);
-+ *outlen = key->klen;
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_NO_PADDING:
++ ret = rsa_no_padding(rsa, pad);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(rsa_no_padding, ret);
++ hi_log_print_func_err(rsa_no_padding, ret);
++ return ret;
++ }
++ *pad->out_len = pad->klen;
++ break;
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_0:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_1:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_2:
++ pad->bt = scheme - HI_CIPHER_RSA_ENCRYPT_SCHEME_BLOCK_TYPE_0;
++ ret = rsa_padding_check_pkcs1_type(rsa, pad);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_padding_check_pkcs1_type, ret);
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_DECRYPT);
++ return HI_ERR_CIPHER_FAILED_DECRYPT;
+ }
+ break;
-+ }
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0:
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_1:
-+ case HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_2: {
-+ bt = scheme - HI_CIPHER_RSA_ENC_SCHEME_BLOCK_TYPE_0;
-+ ret = rsa_padding_check_pkcs1_type(&rsa, key->klen, mode, bt, in, inlen, out, outlen);
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA1:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA224:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA256:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA384:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_OAEP_SHA512:
++ case HI_CIPHER_RSA_ENCRYPT_SCHEME_RSAES_PKCS1_V1_5:
++ ret = mbedtls_rsa_pkcs1_decrypt(rsa, mbedtls_get_random, HI_NULL, pad->mode, &out_size,
++ pad->in, pad->out, pad->klen);
++ *pad->out_len = (hi_u32)out_size;
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa check pkcs1 type failed, ret = %d", ret);
-+ HI_LOG_PRINT_FUNC_ERR(rsa_padding_check_pkcs1_type, ret);
-+ ret = HI_ERR_CIPHER_FAILED_DECRYPT;
++ hi_log_print_func_err(mbedtls_rsa_pkcs1_decrypt, ret);
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_DECRYPT);
++ return HI_ERR_CIPHER_FAILED_DECRYPT;
+ }
+ break;
-+ }
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA1:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA224:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA256:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA384:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA512:
-+ case HI_CIPHER_RSA_ENC_SCHEME_RSAES_PKCS1_V1_5: {
-+ ret = mbedtls_rsa_pkcs1_decrypt(&rsa, mbedtls_get_random,
-+ HI_NULL, mode, &outsize, in, out, key->klen);
-+ *outlen = (hi_u32)outsize;
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa pkcs1 decrypt failed, ret = %d", ret);
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_pkcs1_decrypt, ret);
-+ ret = HI_ERR_CIPHER_FAILED_DECRYPT;
-+ }
-+ break;
-+ }
-+ default: {
-+ HI_LOG_ERROR("RSA padding mode error, mode = 0x%x.\n", scheme);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ ret = HI_ERR_CIPHER_INVALID_PARA;
-+ break;
-+ }
++ default:
++ hi_log_error("RSA padding mode error, mode = 0x%x.\n", scheme);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ cryp_rsa_deinit_key(&rsa);
-+
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("rsa decrypt failed, scheme %d, ret = 0x%x\n", scheme, ret);
-+ KAPI_RSA_UNLOCK();
-+ return ret;
-+ }
-+
-+ KAPI_RSA_UNLOCK();
-+ HI_LOG_FUNC_EXIT();
-+
+ return HI_SUCCESS;
+}
+
-+hi_s32 cryp_rsa_sign_hash(cryp_rsa_key *key, hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen, hi_u8 *out, hi_u32 *outlen, hi_u32 saltlen)
++hi_s32 cryp_rsa_decrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa_crypt)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
++ int padding = 0;
++ int hash_id = 0;
++ int hashlen = 0;
++ mbedtls_rsa_context rsa;
++ rsa_padding_pack pad;
++
++ hi_log_func_enter();
++
++ hi_log_chk_param_return(key == HI_NULL);
++ hi_log_chk_param_return(rsa_crypt == HI_NULL);
++ hi_log_chk_param_return(rsa_crypt->in == HI_NULL);
++ hi_log_chk_param_return(rsa_crypt->out == HI_NULL);
++ hi_log_chk_param_return(key->klen > RSA_KEY_LEN_4096);
++ hi_log_chk_param_return(rsa_crypt->in_len != key->klen);
++ hi_log_chk_param_return(key->ca_type >= HI_CIPHER_KEY_SRC_BUTT);
++
++ ret = cryp_rsa_get_alg(rsa_crypt->scheme, &padding, &hash_id, &hashlen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_rsa_get_alg, ret);
++ return ret;
++ }
++
++ kapi_rsa_lock_err_return();
++
++ mbedtls_rsa_init(&rsa, padding, hash_id);
++ crypto_memset(&pad, sizeof(pad), 0, sizeof(pad));
++
++ ret = cryp_rsa_init_key(key, &pad.mode, &rsa);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_rsa_init_key, ret);
++ kapi_rsa_unlock();
++ return ret;
++ }
++
++ pad.in = rsa_crypt->in;
++ pad.in_len = rsa_crypt->in_len;
++ pad.out = rsa_crypt->out;
++ pad.out_len = &rsa_crypt->out_len;
++ pad.klen = key->klen;
++ ret = ext_rsa_decrypt(rsa_crypt->scheme, &rsa, &pad);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ext_rsa_decrypt, ret);
++ cryp_rsa_deinit_key(&rsa);
++ kapi_rsa_unlock();
++ return ret;
++ }
++
++ rsa_crypt->out_len = *pad.out_len;
++ cryp_rsa_deinit_key(&rsa);
++ kapi_rsa_unlock();
++ hi_log_func_exit();
++ return HI_SUCCESS;
++}
++
++hi_s32 cryp_rsa_sign_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa_sign)
++{
++ hi_s32 ret;
+ hi_u32 mode = 0;
+ int padding = 0;
+ int hash_id = 0;
+ int hashlen = 0;
+ mbedtls_rsa_context rsa;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(key == HI_NULL);
-+ HI_LOG_CHECK_PARAM(in == HI_NULL);
-+ HI_LOG_CHECK_PARAM(out == HI_NULL);
-+ HI_LOG_CHECK_PARAM(outlen == HI_NULL);
-+ HI_LOG_CHECK_PARAM(key->klen > RSA_KEY_LEN_4096);
-+ HI_LOG_CHECK_PARAM(inlen > key->klen);
++ hi_log_chk_param_return(key == HI_NULL);
++ hi_log_chk_param_return(rsa_sign == HI_NULL);
++ hi_log_chk_param_return(rsa_sign->in == HI_NULL);
++ hi_log_chk_param_return(rsa_sign->out == HI_NULL);
++ hi_log_chk_param_return(key->klen > RSA_KEY_LEN_4096);
++ hi_log_chk_param_return(rsa_sign->in_len > key->klen);
+
-+ ret = cryp_rsa_get_alg(scheme, &padding, &hash_id, &hashlen);
++ ret = cryp_rsa_get_alg(rsa_sign->scheme, &padding, &hash_id, &hashlen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_sign_get_alg failed");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_get_alg, ret);
++ hi_log_print_func_err(cryp_rsa_get_alg, ret);
+ return ret;
+ }
++ hi_log_chk_param_return(rsa_sign->in_len < hashlen);
+
-+ KAPI_RSA_LOCK();
++ kapi_rsa_lock_err_return();
+
+ mbedtls_rsa_init(&rsa, padding, hash_id);
+
+ ret = cryp_rsa_init_key(key, &mode, &rsa);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_init_key failed");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_init_key, ret);
-+ KAPI_RSA_UNLOCK();
++ hi_log_print_func_err(cryp_rsa_init_key, ret);
++ kapi_rsa_unlock();
+ return ret;
+ }
+
++ /* rsa_sign->in is input hash data, rsa_sign->out is ouput sign data. */
+ ret = mbedtls_rsa_pkcs1_sign(&rsa, mbedtls_get_random, HI_NULL,
-+ mode, hash_id, hashlen, in, out);
++ mode, hash_id, hashlen, rsa_sign->in, rsa_sign->out);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa_pkcs1 sign failed, ret = 0x%x\n", ret);
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_pkcs1_sign, ret);
-+ ret = HI_ERR_CIPHER_RSA_SIGN;
++ hi_log_print_func_err(mbedtls_rsa_pkcs1_sign, ret);
++ hi_log_print_err_code(HI_ERR_CIPHER_RSA_SIGN);
+ cryp_rsa_deinit_key(&rsa);
-+ KAPI_RSA_UNLOCK();
-+ return ret;
++ kapi_rsa_unlock();
++ return HI_ERR_CIPHER_RSA_SIGN;
+ }
+
-+ *outlen = key->klen;
-+
++ rsa_sign->out_len = key->klen;
+ cryp_rsa_deinit_key(&rsa);
+
-+ KAPI_RSA_UNLOCK();
-+ HI_LOG_FUNC_EXIT();
++ kapi_rsa_unlock();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 cryp_rsa_verify_hash(cryp_rsa_key *key, hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *hash, hi_u32 hlen, hi_u8 *sign, hi_u32 signlen, hi_u32 saltlen)
++hi_s32 cryp_rsa_verify_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa_verify)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ int padding = 0;
+ int hash_id = 0;
+ int hashlen = 0;
+ hi_u32 mode = 0;
+ mbedtls_rsa_context rsa;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(key == HI_NULL);
-+ HI_LOG_CHECK_PARAM(hash == HI_NULL);
-+ HI_LOG_CHECK_PARAM(sign == HI_NULL);
-+ HI_LOG_CHECK_PARAM(key->klen > RSA_KEY_LEN_4096);
-+ HI_LOG_CHECK_PARAM(signlen > key->klen);
-+ HI_LOG_CHECK_PARAM(key->ca_type != HI_CIPHER_KEY_SRC_USER);
++ hi_log_chk_param_return(key == HI_NULL);
++ hi_log_chk_param_return(rsa_verify == HI_NULL);
++ hi_log_chk_param_return(rsa_verify->in == HI_NULL);
++ hi_log_chk_param_return(rsa_verify->out == HI_NULL);
++ hi_log_chk_param_return(key->klen > RSA_KEY_LEN_4096);
++ hi_log_chk_param_return(rsa_verify->in_len != key->klen);
++ hi_log_chk_param_return(rsa_verify->out_len > key->klen);
++ hi_log_chk_param_return(key->ca_type != HI_CIPHER_KEY_SRC_USER);
+
-+ ret = cryp_rsa_get_alg(scheme, &padding, &hash_id, &hashlen);
++ ret = cryp_rsa_get_alg(rsa_verify->scheme, &padding, &hash_id, &hashlen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_sign_get_alg failed");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_get_alg, ret);
++ hi_log_print_func_err(cryp_rsa_get_alg, ret);
+ return ret;
+ }
++ hi_log_chk_param_return(rsa_verify->in_len < hashlen);
+
-+ KAPI_RSA_LOCK();
++ kapi_rsa_lock_err_return();
+
+ mbedtls_rsa_init(&rsa, padding, hash_id);
+
+ ret = cryp_rsa_init_key(key, &mode, &rsa);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_rsa_init_key failed, ret = %d\n", ret);
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_init_key, ret);
-+ KAPI_RSA_UNLOCK();
++ hi_log_print_func_err(cryp_rsa_init_key, ret);
++ kapi_rsa_unlock();
+ return ret;
+ }
+
++ /* rsa_verify->out is input hash data, rsa_verify->in is input sign data. */
+ ret = mbedtls_rsa_pkcs1_verify(&rsa, mbedtls_get_random, HI_NULL,
-+ mode, hash_id, hashlen, hash, sign);
++ mode, hash_id, hashlen, rsa_verify->out, rsa_verify->in);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa pkcs1 verify failed, ret = 0x%x\n", ret);
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_rsa_pkcs1_verify, ret);
-+ ret = HI_ERR_CIPHER_RSA_VERIFY;
++ hi_log_print_func_err(mbedtls_rsa_pkcs1_verify, ret);
++ hi_log_print_err_code(HI_ERR_CIPHER_RSA_VERIFY);
+ cryp_rsa_deinit_key(&rsa);
-+ KAPI_RSA_UNLOCK();
-+ return ret;
++ kapi_rsa_unlock();
++ return HI_ERR_CIPHER_RSA_VERIFY;
+ }
+
+ cryp_rsa_deinit_key(&rsa);
-+ KAPI_RSA_UNLOCK();
-+ HI_LOG_FUNC_EXIT();
++ kapi_rsa_unlock();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
-+
-+/** @}*/ /** <!-- ==== API Code end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_symc.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_symc.c
new file mode 100644
-index 0000000..d49336a
+index 0000000..6d7deb5
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_symc.c
-@@ -0,0 +1,2006 @@
+@@ -0,0 +1,1958 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for cipher cryp symc.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
++#include "cryp_symc.h"
+#include "drv_osal_lib.h"
+#include "drv_symc.h"
-+#include "cryp_symc.h"
+#include "ext_alg.h"
+
-+/*************************** Internal Structure Definition *******************/
-+/** \addtogroup aes */
-+/** @{*/ /** <!-- [aes]*/
++/* ************************** Internal Structure Definition ****************** */
++/* AES set IV for first package */
++#define SYMC_IV_USAGE_ONE_PKG 1
+
+/* AES set IV for first package */
-+#define SYMC_IV_USAGE_ONE_PKG (1)
++#define SYMC_IV_USAGE_ALL_PKG 2
+
-+/* AES set IV for first package */
-+#define SYMC_IV_USAGE_ALL_PKG (2)
-+
-+/* SYMC interrupt level */
-+#define SYMC_INT_LEVEL (SYMC_MAX_LIST_NUM - 15) /* (1UL) */
++/* SYMC interrupt level (1UL) */
++#define SYMC_INT_LEVEL (SYMC_MAX_LIST_NUM - 15)
+
+/* Length of SYMC ccm q */
-+#define SYMC_CCM_Q_LEN_2B (2)
-+#define SYMC_CCM_Q_LEN_3B (3)
-+#define SYMC_CCM_Q_LEN_4B (4)
++#define SYMC_CCM_Q_LEN_2B 2
++#define SYMC_CCM_Q_LEN_3B 3
++#define SYMC_CCM_Q_LEN_4B 4
+
+/* Length of SYMC ccm P */
-+#define SYMC_CCM_P_LEN_2B (0xFFFF)
-+#define SYMC_CCM_P_LEN_3B (0xFFFFFF)
++#define SYMC_CCM_P_LEN_2B 0xFFFF
++#define SYMC_CCM_P_LEN_3B 0xFFFFFF
+
+/* length range of aead */
-+#define AES_CCM_MIN_IV_LEN (7)
-+#define AES_CCM_MAX_IV_LEN (13)
-+#define AES_CCM_NQ_LEN (14)
-+#define AES_CCM_MIN_TAG_LEN (4)
-+#define AES_CCM_MAX_TAG_LEN (16)
-+#define AES_GCM_MIN_IV_LEN (1)
-+#define AES_GCM_MAX_IV_LEN (16)
-+#define AES_GCM_MIN_TAG_LEN (1)
-+#define AES_GCM_MAX_TAG_LEN (16)
++#define AES_CCM_MIN_IV_LEN 7
++#define AES_CCM_MAX_IV_LEN 13
++#define AES_CCM_NQ_LEN 14
++#define AES_CCM_MIN_TAG_LEN 4
++#define AES_CCM_MAX_TAG_LEN 16
++#define AES_GCM_MIN_IV_LEN 1
++#define AES_GCM_MAX_IV_LEN 16
++#define AES_GCM_MIN_TAG_LEN 1
++#define AES_GCM_MAX_TAG_LEN 16
++#define AAD_EXIST 1
++#define AAD_NOT_EXIST 0
++#define N_AND_Q_VAL 15
+
+/* Multi nodes added status, finished or finished */
-+#define SYMC_NODES_ADD_FINISHED (0x0a0a0a0a)
-+#define SYMC_NODES_ADD_NOTFINISHED (0X05050505)
-+
-+/**
-+ * \brief symc context structure
-+ *
-+ * \note if the aes key derived from klad, the context msut
-+ * attached with a independent hard key channel,
-+ * otherwise the context can attached with a fixed common channel.
-+ */
-+typedef struct {
-+ hi_u32 even_key[SYMC_KEY_SIZE / 4]; /*!< SYMC even round keys, default */
-+ hi_u32 odd_key[SYMC_KEY_SIZE / 4]; /*!< SYMC odd round keys, default */
-+ hi_u32 sk[SYMC_SM1_SK_SIZE / 4]; /*!< sm1 sk */
-+ hi_u32 iv[AES_IV_SIZE / 4]; /*!< symc IV */
-+ hi_u32 tag[AEAD_TAG_SIZE / 4]; /*!< aead tag */
-+ hi_u32 ivlen; /*!< symc IV length */
-+ hi_u32 iv_usage; /*!< symc IV usage */
-+
-+ hi_u32 hard_chn; /*!< hard channel number */
-+ hi_u32 hard_key; /*!< Key derived from klad or CPU */
-+
-+ symc_alg alg; /*!< Symmetric cipher algorithm */
-+ symc_width width; /*!< Symmetric cipher width */
-+ hi_u32 klen; /*!< Symmetric cipher key length */
-+
-+ compat_addr aad; /*!< Associated Data */
-+ hi_u32 alen; /*!< Associated Data length */
-+ hi_u32 tlen; /*!< Tag length */
-+
-+ symc_mode mode; /*!< Symmetric cipher mode */
-+
-+ hi_u32 sm1_round; /*!< SM1 round number */
-+ hi_u32 enclen; /*!< encrypt length */
-+
-+ hi_u32 block_size; /*!< Block size */
-+
-+ hi_u32 cur_nodes; /*!< current nodes id */
-+ hi_u32 total_nodes; /*!< total number of nodes */
-+
-+ compat_addr *input_list; /*!< input node list */
-+ compat_addr *output_list; /*!< output node list */
-+ hi_u32 *length_list; /*!< length of node list */
-+ symc_node_usage *usage_list; /*!< usage of node list */
-+ hi_bool tdes2dma; /*!< 3des with invalid key turns to dma */
-+}
-+cryp_symc_context;
++#define SYMC_NODES_ADD_FINISHED 0x0a0a0a0a
++#define SYMC_NODES_ADD_NOTFINISHED 0x05050505
+
+/* The max tab size of symc function */
-+#define SYMC_FUNC_TAB_SIZE (SYMC_ALG_COUNT * SYMC_MODE_COUNT)
++#define SYMC_FUNC_TAB_SIZE (SYMC_ALG_COUNT * SYMC_MODE_COUNT)
+
+/* symc function list */
-+static symc_func symc_descriptor[SYMC_FUNC_TAB_SIZE];
++static symc_func g_symc_descriptor[SYMC_FUNC_TAB_SIZE];
+
+/* symc context */
-+static cryp_symc_context symc_context[CRYPTO_HARD_CHANNEL_MAX];
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
++static cryp_symc_context g_symc_context[CRYPTO_HARD_CHANNEL_MAX];
+
+/* symc function register */
-+static void cryp_register_all_symc(void);
++static hi_void cryp_register_all_symc(hi_void);
+
+#ifdef CHIP_AES_CCM_GCM_SUPPORT
-+static hi_u32 cyp_aead_gcm_clen(hi_u8 *buf, hi_u32 alen, hi_u32 enclen);
++static hi_u32 cyp_aead_gcm_clen(hi_u8 *buf, hi_u32 buf_len, hi_u32 alen, hi_u32 enclen);
+#endif
+
-+hi_s32 cryp_symc_init(void)
++hi_s32 cryp_symc_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ crypto_memset(symc_descriptor, sizeof(symc_descriptor), 0, sizeof(symc_descriptor));
++ crypto_memset(g_symc_descriptor, sizeof(g_symc_descriptor), 0, sizeof(g_symc_descriptor));
+
+ ret = drv_symc_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_init, ret);
++ hi_log_print_func_err(drv_symc_init, ret);
+ return ret;
+ }
+
+ cryp_register_all_symc();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void cryp_symc_deinit(void)
++hi_void cryp_symc_deinit(hi_void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ drv_symc_deinit();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
+hi_s32 cryp_symc_alloc_chn(hi_u32 *hard_chn)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 key[SYMC_KEY_MAX_SIZE_IN_WORD] = {0, 1, 2, 3, 4, 5, 6, 7};
+ hi_u32 sm1_key[SYMC_SM1_SK_SIZE_IN_WORD] = {0, 1, 2, 3};
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* allocate a aes hard key channel */
+ ret = drv_symc_alloc_chn(hard_chn);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_alloc_chn, ret);
++ hi_log_print_func_err(drv_symc_alloc_chn, ret);
+ return ret;
+ }
+
+ /* Set a fake key to clear the true key. */
-+ drv_symc_set_key(*hard_chn, key, HI_FALSE);
-+ drv_symc_set_sm1_sk(*hard_chn, sm1_key);
++ drv_symc_set_key(*hard_chn, key, sizeof(key), HI_FALSE);
++ drv_symc_set_sm1_sk(*hard_chn, sm1_key, sizeof(sm1_key));
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void cryp_symc_free_chn(hi_u32 hard_chn)
++hi_void cryp_symc_free_chn(hi_u32 hard_chn)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ drv_symc_free_chn(hard_chn);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+}
+
-+static void *cryp_symc_create(hi_u32 hard_chn)
++static hi_void *cryp_symc_create(hi_u32 hard_chn)
+{
+ cryp_symc_context *hisi_ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ hisi_ctx = &symc_context[hard_chn];
++ hisi_ctx = &g_symc_context[hard_chn];
+ crypto_memset(hisi_ctx, sizeof(cryp_symc_context), 0, sizeof(cryp_symc_context));
+ hisi_ctx->hard_key = HI_FALSE;
+ hisi_ctx->hard_chn = hard_chn;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return hisi_ctx;
+}
+
-+static void cryp_symc_setkey(void *ctx, const hi_u8 *key, hi_u32 keylen, hi_u32 odd)
++static hi_void cryp_symc_setkey(hi_void *ctx, const hi_u8 *key, hi_u32 keylen, hi_u32 odd)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_ERROR("Invalid point.\n");
++ hi_log_error("Invalid point.\n");
+ return;
+ }
+
@@ -210722,24 +279576,24 @@ index 0000000..d49336a
+ }
+ hisi_ctx->klen = keylen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static void cryp_symc_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
++static hi_void cryp_symc_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_ERROR("Invalid point.\n");
++ hi_log_error("Invalid point.\n");
+ return;
+ }
+
+ if (iv == HI_NULL) {
+ if (ivlen != 0) {
-+ HI_LOG_ERROR("Invalid iv len(%u), iv is null.\n", ivlen);
++ hi_log_error("Invalid iv len(%u), iv is null.\n", ivlen);
+ }
+ return;
+ }
@@ -210748,122 +279602,122 @@ index 0000000..d49336a
+ hisi_ctx->iv_usage = usage;
+ hisi_ctx->ivlen = ivlen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static void cryp_symc_getiv(void *ctx, hi_u8 *iv, hi_u32 *ivlen)
++static hi_void cryp_symc_getiv(hi_void *ctx, hi_u8 *iv, hi_u32 *ivlen)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_ERROR("Invalid point.\n");
++ hi_log_error("Invalid point.\n");
+ return;
+ }
+ crypto_memcpy(iv, AES_IV_SIZE, hisi_ctx->iv, hisi_ctx->ivlen);
+ *ivlen = hisi_ctx->ivlen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static void cryp_symc_setmode(void *ctx, symc_alg alg, symc_mode mode, symc_width width)
++static hi_void cryp_symc_setmode(hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_ERROR("Invalid point.\n");
++ hi_log_error("Invalid point.\n");
+ return;
+ }
+ hisi_ctx->mode = mode;
+ hisi_ctx->alg = alg;
+ hisi_ctx->width = width;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static void cryp_3des2dma_setmode(void *ctx, symc_alg alg, symc_mode mode, symc_width width)
++static hi_void cryp_3des2dma_setmode(hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (hisi_ctx == HI_NULL) {
-+ HI_LOG_ERROR("Invalid point.\n");
++ hi_log_error("Invalid point.\n");
+ return;
+ }
+
-+ CRYPTO_UNUSED(alg);
-+ CRYPTO_UNUSED(mode);
-+ CRYPTO_UNUSED(width);
++ crypto_unused(alg);
++ crypto_unused(mode);
++ crypto_unused(width);
+
+ hisi_ctx->mode = SYMC_MODE_ECB;
+ hisi_ctx->alg = SYMC_ALG_TDES;
+ hisi_ctx->width = SYMC_DAT_WIDTH_64;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static hi_s32 cryp_symc_sm1_setsk(void *ctx, const hi_u8 *key)
++static hi_s32 cryp_symc_sm1_setsk(hi_void *ctx, const hi_u8 *key)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
-+ crypto_memcpy(hisi_ctx->sk, SYMC_SM1_SK_SIZE, key, SYMC_SM1_SK_SIZE);
++ crypto_memcpy(hisi_ctx->sk, sizeof(hisi_ctx->sk), key, SYMC_SM1_SK_SIZE);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_symc_sm1_setround(void *ctx, hi_u32 round)
++static hi_s32 cryp_symc_sm1_setround(hi_void *ctx, hi_u32 round)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
+ hisi_ctx->sm1_round = round;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static hi_s32 symc_add_buf(cryp_symc_context *ctx, symc_node_usage out_uasge)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 cur = ctx->cur_nodes;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /*Add P in*/
++ /* Add P in. */
+ ret = drv_symc_add_inbuf(ctx->hard_chn,
+ ctx->input_list[cur],
+ ctx->length_list[cur],
+ ctx->usage_list[cur]);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
+ return ret;
+ }
+
-+ /*Add P out, only need the last flag*/
++ /* Add P out, only need the last flag. */
+ ret = drv_symc_add_outbuf(ctx->hard_chn,
+ ctx->output_list[cur],
+ ctx->length_list[cur],
+ out_uasge);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_outbuf, ret);
++ hi_log_print_func_err(drv_symc_add_outbuf, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ret;
+}
@@ -210879,37 +279733,94 @@ index 0000000..d49336a
+ return usage;
+}
+
-+static hi_s32 symc_add_buf_list(void *ctx)
++static hi_s32 symc_add_next_node(cryp_symc_context *ctx, hi_u32 *total, symc_node_usage usage)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 i = 0;
-+ hi_u32 nodes = 0;
-+ hi_u32 cur = 0;
-+ hi_u32 total_len = 0;
++ hi_s32 ret;
++ hi_u32 cur, total_len;
++
++ total_len = *total;
++ total_len %= ctx->block_size;
++ /* Compute the tail length. */
++ if (total_len > 0) {
++ total_len = ctx->block_size - total_len;
++ }
++
++ /* if the total length don't aligned with block size, split joint the follow nodes. */
++ while ((total_len > 0) && (ctx->cur_nodes < ctx->total_nodes)) {
++ cur = ctx->cur_nodes;
++
++ /* The next node large than tail size, just split it to 2 nodes. */
++ if (ctx->length_list[cur] > total_len) {
++ /* Add P in. */
++ ret = drv_symc_add_inbuf(ctx->hard_chn, ctx->input_list[cur], total_len, ctx->usage_list[cur]);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_add_inbuf, ret);
++ return ret;
++ }
++
++ /* Add P out. */
++ usage = symc_get_out_usage(ctx->mode, cur, ctx->total_nodes);
++ ret = drv_symc_add_outbuf(ctx->hard_chn, ctx->output_list[cur], total_len, usage);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_add_outbuf, ret);
++ return ret;
++ }
++
++ /* Let next node skip the tail size. */
++ addr_u64(ctx->input_list[cur]) += total_len;
++ addr_u64(ctx->output_list[cur]) += total_len;
++ ctx->length_list[cur] -= total_len;
++ total_len = 0;
++ } else {
++ /* The next node less than tail size, add it to nodes list. */
++ usage = symc_get_out_usage(ctx->mode, cur, ctx->total_nodes);
++ ret = symc_add_buf(ctx, usage); /* Add one node. */
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(symc_add_buf, ret);
++ return ret;
++ }
++
++ /* re-compute the tail size. */
++ total_len -= ctx->length_list[cur];
++
++ /* Process next node. */
++ ctx->cur_nodes++;
++ }
++ }
++
++ *total = total_len;
++ return HI_SUCCESS;
++}
++
++static hi_s32 symc_add_buf_list(hi_void *ctx)
++{
++ hi_s32 ret;
++ hi_u32 i, nodes, cur, total_len;
+ cryp_symc_context *hisi_ctx = ctx;
-+ symc_node_usage usage = SYMC_NODE_USAGE_NORMAL;
++ symc_node_usage usage;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /* compute finished*/
++ /* compute finished. */
+ if (hisi_ctx->cur_nodes == hisi_ctx->total_nodes) {
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return SYMC_NODES_ADD_FINISHED;
+ }
+
-+ /* compute not finished*/
-+ /* select the minimum numbers of nodes to calculate*/
-+ nodes = MIN(SYMC_INT_LEVEL, hisi_ctx->total_nodes - hisi_ctx->cur_nodes);
++ /* compute not finished.
++ * select the minimum numbers of nodes to calculate.
++ */
++ nodes = crypto_min(SYMC_INT_LEVEL, hisi_ctx->total_nodes - hisi_ctx->cur_nodes);
+ total_len = 0;
+
+ for (i = 0; i < nodes; i++) {
+ cur = hisi_ctx->cur_nodes;
+ usage = symc_get_out_usage(hisi_ctx->mode, cur, hisi_ctx->total_nodes);
+
-+ /*Add one node*/
++ /* Add one node. */
+ ret = symc_add_buf(hisi_ctx, usage);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(symc_add_buf, ret);
++ hi_log_print_func_err(symc_add_buf, ret);
+ return ret;
+ }
+
@@ -210921,92 +279832,42 @@ index 0000000..d49336a
+ * must aligned with block size, otherwise can't recv interrupt,
+ * which limit to hardware devising.
+ */
-+
-+ /* Compute the tail length*/
-+ total_len %= hisi_ctx->block_size;
-+ if (total_len > 0) {
-+ total_len = hisi_ctx->block_size - total_len;
++ ret = symc_add_next_node(hisi_ctx, &total_len, usage);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(symc_add_next_node, ret);
++ return ret;
+ }
+
-+ /*if the total length don't aligned with block size, split joint the follow nodes*/
-+ while ((total_len > 0) && (hisi_ctx->cur_nodes < hisi_ctx->total_nodes)) {
-+ cur = hisi_ctx->cur_nodes;
-+
-+ /*The next node large than tail size, just split it to 2 nodes */
-+ if (hisi_ctx->length_list[cur] > total_len) {
-+ /*Add P in*/
-+ ret = drv_symc_add_inbuf(hisi_ctx->hard_chn, hisi_ctx->input_list[cur],
-+ total_len, hisi_ctx->usage_list[cur]);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_inbuf, ret);
-+ return ret;
-+ }
-+
-+ /*Add P out*/
-+ usage = symc_get_out_usage(hisi_ctx->mode, cur, hisi_ctx->total_nodes);
-+ ret = drv_symc_add_outbuf(hisi_ctx->hard_chn, hisi_ctx->output_list[cur],
-+ total_len, usage);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_outbuf, ret);
-+ return ret;
-+ }
-+
-+ /*Let next node skip the tail size*/
-+ ADDR_U64(hisi_ctx->input_list[cur]) += total_len;
-+ ADDR_U64(hisi_ctx->output_list[cur]) += total_len;
-+ hisi_ctx->length_list[cur] -= total_len;
-+ total_len = 0;
-+ } else {
-+ /*The next node less than tail size, add it to nodes list */
-+
-+ /*Add one node*/
-+ usage = symc_get_out_usage(hisi_ctx->mode, cur, hisi_ctx->total_nodes);
-+ ret = symc_add_buf(hisi_ctx, usage);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(symc_add_buf, ret);
-+ return ret;
-+ }
-+
-+ /*re-compute the tail size*/
-+ total_len -= hisi_ctx->length_list[cur];
-+
-+ /*Process next node*/
-+ hisi_ctx->cur_nodes++;
-+ }
-+ }
+#ifdef CHIP_AES_CCM_GCM_SUPPORT
+ /* gcm add nodes finished ? */
-+ if ((hisi_ctx->mode == SYMC_MODE_GCM)
-+ && (hisi_ctx->cur_nodes == hisi_ctx->total_nodes)) {
++ if ((hisi_ctx->mode == SYMC_MODE_GCM) && (hisi_ctx->cur_nodes == hisi_ctx->total_nodes)) {
+ hi_u8 clen[AES_BLOCK_SIZE];
++ compat_addr addr_null;
+
+ /* At the and of GCM, must add a empty node to nodes list,
-+ * limit to hardware devising
-+ */
-+ drv_symc_add_outbuf(hisi_ctx->hard_chn, ADDR_NULL, 0x00, SYMC_NODE_USAGE_LAST);
-+ /*Format the length fields of C and add to nodes list*/
-+ cyp_aead_gcm_clen(clen, hisi_ctx->alen, hisi_ctx->enclen);
-+ drv_aead_gcm_add_clen(hisi_ctx->hard_chn, clen);
++ * limit to hardware devising
++ */
++ crypto_memset(&addr_null, sizeof(addr_null), 0, sizeof(addr_null));
++ drv_symc_add_outbuf(hisi_ctx->hard_chn, addr_null, 0x00, SYMC_NODE_USAGE_LAST);
++ /* Format the length fields of C and add to nodes list. */
++ cyp_aead_gcm_clen(clen, sizeof(clen), hisi_ctx->alen, hisi_ctx->enclen);
++ drv_aead_gcm_add_clen(hisi_ctx->hard_chn, clen, sizeof(clen));
+ }
+#endif
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return SYMC_NODES_ADD_NOTFINISHED;
-+
+}
+
+static symc_klen cryp_symc_key_type(symc_alg alg, hi_u32 klen)
+{
+ symc_klen type;
+
-+ if ((alg == SYMC_ALG_AES)
-+ && (klen == AES_KEY_192BIT)) {
++ if ((alg == SYMC_ALG_AES) && (klen == AES_KEY_192BIT)) {
+ type = SYMC_KEY_AES_192BIT;
-+ } else if ((alg == SYMC_ALG_AES)
-+ && (klen == AES_KEY_256BIT)) {
++ } else if ((alg == SYMC_ALG_AES) && (klen == AES_KEY_256BIT)) {
+ type = SYMC_KEY_AES_256BIT;
-+ } else if ((alg == SYMC_ALG_TDES)
-+ && (klen == TDES_KEY_128BIT)) {
++ } else if ((alg == SYMC_ALG_TDES) && (klen == TDES_KEY_128BIT)) {
+ type = SYMC_KEY_TDES_2KEY;
+ } else {
+ type = SYMC_KEY_DEFAULT;
@@ -211015,15 +279876,15 @@ index 0000000..d49336a
+ return type;
+}
+
-+static hi_s32 cryp_symc_config(void *ctx, hi_u32 decrypt)
++static hi_s32 cryp_symc_config(hi_void *ctx, hi_u32 decrypt)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+ symc_klen type;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("symc configure, chn %d, alg %d, mode %d, dec %d, klen %d, hard %d, iv len %d, iv usage %d\n",
++ hi_log_info("symc configure, chn %u, alg %d, mode %d, dec %u, klen %u, hard %u, iv len %u, iv usage %u\n",
+ hisi_ctx->hard_chn, hisi_ctx->alg, hisi_ctx->mode,
+ decrypt, hisi_ctx->klen, hisi_ctx->hard_key,
+ hisi_ctx->ivlen, hisi_ctx->iv_usage);
@@ -211031,35 +279892,34 @@ index 0000000..d49336a
+ type = cryp_symc_key_type(hisi_ctx->alg, hisi_ctx->klen);
+
+ /* configure */
-+ ret = drv_symc_config(hisi_ctx->hard_chn, hisi_ctx->alg, hisi_ctx->mode, hisi_ctx->width,
-+ decrypt, hisi_ctx->sm1_round, type, hisi_ctx->hard_key);
++ ret = drv_symc_cfg(hisi_ctx, decrypt, type);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_config, ret);
++ hi_log_print_func_err(drv_symc_cfg, ret);
+ return ret;
+ }
+
+ if (hisi_ctx->hard_key != HI_TRUE) {
+ /* set odd key */
-+ drv_symc_set_key(hisi_ctx->hard_chn, hisi_ctx->odd_key, HI_TRUE);
++ drv_symc_set_key(hisi_ctx->hard_chn, hisi_ctx->odd_key, sizeof(hisi_ctx->odd_key), HI_TRUE);
+
+ /* set even key */
-+ drv_symc_set_key(hisi_ctx->hard_chn, hisi_ctx->even_key, HI_FALSE);
++ drv_symc_set_key(hisi_ctx->hard_chn, hisi_ctx->even_key, sizeof(hisi_ctx->even_key), HI_FALSE);
+ }
+
+ if (hisi_ctx->alg == SYMC_ALG_SM1) {
-+ drv_symc_set_sm1_sk(hisi_ctx->hard_chn, hisi_ctx->sk);
++ drv_symc_set_sm1_sk(hisi_ctx->hard_chn, hisi_ctx->sk, sizeof(hisi_ctx->sk));
+ }
+
+ /* set iv */
+ ret = drv_symc_set_iv(hisi_ctx->hard_chn, hisi_ctx->iv, hisi_ctx->ivlen, hisi_ctx->iv_usage);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_set_iv, ret);
++ hi_log_print_func_err(drv_symc_set_iv, ret);
+ return ret;
+ }
+
-+ /*first node must set iv except ecb mode*/
-+ if (hisi_ctx->iv_usage == CIPHER_IV_CHANGE_ONE_PKG) {
-+ /* don't set iv any more*/
++ /* first node must set iv except ecb mode. */
++ if (hisi_ctx->iv_usage == HI_CIPHER_IV_CHG_ONE_PACK) {
++ /* don't set iv any more. */
+ hisi_ctx->iv_usage = 0;
+ }
+
@@ -211071,101 +279931,96 @@ index 0000000..d49336a
+ hisi_ctx->block_size = AES_BLOCK_SIZE;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_symc_wait_done(void *ctx, hi_u32 timeout)
++static hi_s32 cryp_symc_wait_done(hi_void *ctx, hi_u32 timeout)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* wait done */
+ ret = drv_symc_wait_done(hisi_ctx->hard_chn, timeout);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_wait_done, ret);
++ hi_log_print_func_err(drv_symc_wait_done, ret);
+ return ret;
+ }
+
+ drv_symc_get_iv(hisi_ctx->hard_chn, hisi_ctx->iv);
+
-+ if ((hisi_ctx->mode == SYMC_MODE_CCM)
-+ || (hisi_ctx->mode == SYMC_MODE_GCM)) {
-+ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag);
++ if ((hisi_ctx->mode == SYMC_MODE_CCM) || (hisi_ctx->mode == SYMC_MODE_GCM)) {
++ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag, sizeof(hisi_ctx->tag));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_get_tag, ret);
++ hi_log_print_func_err(drv_aead_get_tag, ret);
+ return ret;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_symc_crypto_init(cryp_symc_context *hisi_ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, symc_node_usage usage)
++static hi_s32 cryp_symc_crypto_init(cryp_symc_context *hisi_ctx, hi_u32 operation, symc_multi_pack *pack,
++ symc_node_usage usage)
+{
+ hi_u32 i = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
++ hi_log_chk_param_return(pack == HI_NULL);
+
+ /* length of pkage can't be zero */
+ hisi_ctx->enclen = 0;
-+ if (pkg_num == 0x01) {
-+ hisi_ctx->enclen += length[i];
-+ usage_list[i] = usage_list[i] | (hi_u32)usage;
++ if (pack->num == 0x01) {
++ hisi_ctx->enclen += pack->len[i];
++ pack->usage[i] = (hi_u32)pack->usage[i] | (hi_u32)usage;
+ } else {
-+ for (i = 0; i < pkg_num; i++) {
-+ if (length[i] == 0x00) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_OVERFLOW);
-+ return HI_ERR_CIPHER_INVALID_LENGTH;
++ for (i = 0; i < pack->num; i++) {
++ if (pack->len[i] == 0x00) {
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_LEN);
++ return HI_ERR_CIPHER_INVALID_LEN;
+ }
+
-+ HI_LOG_CHECK_PARAM(hisi_ctx->enclen + length[i] < hisi_ctx->enclen);
++ hi_log_chk_param_return(hisi_ctx->enclen + pack->len[i] < hisi_ctx->enclen);
+
-+ hisi_ctx->enclen += length[i];
-+ usage_list[i] = usage_list[i] | (hi_u32)usage;
++ hisi_ctx->enclen += pack->len[i];
++ pack->usage[i] = (hi_u32)pack->usage[i] | (hi_u32)usage;
+ }
+ }
+
+ /* configuration parameter */
+ ret = cryp_symc_config(hisi_ctx, operation);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_config, ret);
++ hi_log_print_func_err(cryp_symc_config, ret);
+ return ret;
+ }
+
-+ hisi_ctx->input_list = input;
-+ hisi_ctx->output_list = output;
-+ hisi_ctx->length_list = length;
-+ hisi_ctx->usage_list = usage_list;
-+ hisi_ctx->total_nodes = pkg_num;
++ hisi_ctx->input_list = pack->in;
++ hisi_ctx->output_list = pack->out;
++ hisi_ctx->length_list = pack->len;
++ hisi_ctx->usage_list = pack->usage;
++ hisi_ctx->total_nodes = pack->num;
+ hisi_ctx->cur_nodes = 0;
+
+ /* set isr callback function */
+ ret = drv_symc_set_isr_callback(hisi_ctx->hard_chn, HI_NULL, HI_NULL);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_set_isr_callback, ret);
++ hi_log_print_func_err(drv_symc_set_isr_callback, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static hi_s32 cryp_symc_crypto_process(cryp_symc_context *hisi_ctx, hi_u32 wait)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (wait == HI_TRUE) {
+ while (symc_add_buf_list(hisi_ctx) == SYMC_NODES_ADD_NOTFINISHED) {
@@ -211175,7 +280030,7 @@ index 0000000..d49336a
+ /* wait done */
+ ret = drv_symc_wait_done(hisi_ctx->hard_chn, CRYPTO_TIME_OUT);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_wait_done, ret);
++ hi_log_print_func_err(drv_symc_wait_done, ret);
+ return ret;
+ }
+ }
@@ -211183,95 +280038,79 @@ index 0000000..d49336a
+ /* add buf list once */
+ ret = symc_add_buf_list(hisi_ctx);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(symc_add_buf_list, ret);
++ hi_log_print_func_err(symc_add_buf_list, ret);
+ return ret;
+ }
+
+ /* set isr callback function */
+ ret = drv_symc_set_isr_callback(hisi_ctx->hard_chn, symc_add_buf_list, hisi_ctx);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_set_isr_callback, ret);
++ hi_log_print_func_err(drv_symc_set_isr_callback, ret);
+ return ret;
+ }
+
+ /* start running */
+ ret = drv_symc_start(hisi_ctx->hard_chn);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_start, ret);
++ hi_log_print_func_err(drv_symc_start, ret);
+ return ret;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_symc_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num,
-+ hi_u32 wait)
++static hi_s32 cryp_symc_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 wait)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
+ if (hisi_ctx->alg == SYMC_ALG_NULL_CIPHER) {
+ /* set last flag for each node when DMA copy */
-+ hisi_ctx->iv_usage = CIPHER_IV_CHANGE_ALL_PKG;
++ hisi_ctx->iv_usage = HI_CIPHER_IV_CHG_ALL_PACK;
+ }
+
-+ ret = cryp_symc_crypto_init(hisi_ctx, operation, input, output, length,
-+ usage_list, pkg_num, SYMC_NODE_USAGE_NORMAL);
++ ret = cryp_symc_crypto_init(hisi_ctx, operation, pack, SYMC_NODE_USAGE_NORMAL);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_crypto_init, ret);
++ hi_log_print_func_err(cryp_symc_crypto_init, ret);
+ return ret;
+ }
-+ usage_list[pkg_num - 1] = (hi_u32)usage_list[pkg_num - 1] | SYMC_NODE_USAGE_LAST;
++ pack->usage[pack->num - 1] = (hi_u32)pack->usage[pack->num - 1] | SYMC_NODE_USAGE_LAST;
+
+ /* tdes used as dma */
+ if (hisi_ctx->tdes2dma == HI_TRUE) {
-+ if ((pkg_num != 0x01) && (length[0] < DES_BLOCK_SIZE)) {
-+ HI_LOG_ERROR("Invalid 3des dma for pkg num (0x%x) or data lenth (0x%x).\n", pkg_num, length[0]);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((pack->num != 0x01) && (pack->len[0] < DES_BLOCK_SIZE)) {
++ hi_log_error("Invalid 3des dma for pkg num (0x%x) or data lenth (0x%x).\n", pack->num, pack->len[0]);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ } else {
+ /* check the length of nodes list */
-+ ret = drv_symc_node_check(hisi_ctx->alg,
-+ hisi_ctx->mode,
-+ hisi_ctx->klen,
-+ hisi_ctx->block_size,
-+ input,
-+ output,
-+ length,
-+ usage_list,
-+ pkg_num);
++ ret = drv_symc_node_check(hisi_ctx->alg, hisi_ctx->mode, hisi_ctx->klen, hisi_ctx->block_size, pack);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_node_check, ret);
++ hi_log_print_func_err(drv_symc_node_check, ret);
+ return ret;
+ }
+ }
+
+ ret = cryp_symc_crypto_process(hisi_ctx, wait);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_crypto_process, ret);
++ hi_log_print_func_err(cryp_symc_crypto_process, ret);
+ return ret;
+ }
+
+ drv_symc_get_iv(hisi_ctx->hard_chn, hisi_ctx->iv);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+#ifdef CHIP_AES_CCM_GCM_SUPPORT
-+static hi_s32 cryp_aead_ccm_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
++static hi_s32 cryp_aead_ccm_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
+{
+ hi_u8 ccm_iv[AES_IV_SIZE] = {0};
+
@@ -211279,14 +280118,13 @@ index 0000000..d49336a
+ * The octet length of the binary represen tation of the
+ * octet length of the payload denoted q,
+ * n is an element of {7, 8, 9, 10, 11, 12, 13}
-+ * n + q = 15
++ * descript: n + q = 15
+ * here the string of N is pConfig->iv, and n is pConfig->ivLen.
+ */
-+ if ((ivlen < AES_CCM_MIN_IV_LEN)
-+ || (ivlen > AES_CCM_MAX_IV_LEN)) {
-+ HI_LOG_ERROR("Invalid ccm iv len, ivlen = 0x%x.\n", ivlen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((ivlen < AES_CCM_MIN_IV_LEN) || (ivlen > AES_CCM_MAX_IV_LEN)) {
++ hi_log_error("Invalid ccm iv len, ivlen = 0x%x.\n", ivlen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ /* Formatting of the Counter Blocks(IV for CTR)
@@ -211303,8 +280141,7 @@ index 0000000..d49336a
+ * others bits shall be set to 0.
+ * so the first byte of IV shall be q -1, that is 15 - pConfig->ivLen - 1
+ */
-+ crypto_memset(ccm_iv, sizeof(ccm_iv), 0, AES_IV_SIZE);
-+ ccm_iv[0] = AES_CCM_NQ_LEN - ivlen; /*IV[0] = q - 1 = 15 - n -1*/
++ ccm_iv[0] = AES_CCM_NQ_LEN - ivlen; /* descript: IV[0] = q - 1 = 15 - n -1. */
+ crypto_memcpy(&ccm_iv[1], sizeof(ccm_iv) - 1, iv, ivlen);
+ ivlen += 1;
+
@@ -211313,13 +280150,12 @@ index 0000000..d49336a
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_aead_gcm_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
++static hi_s32 cryp_aead_gcm_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
+{
-+ if ((ivlen < AES_GCM_MIN_IV_LEN)
-+ || (ivlen > AES_GCM_MAX_IV_LEN)) {
-+ HI_LOG_ERROR("Invalid gcm iv len, ivlen = 0x%x.\n", ivlen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((ivlen < AES_GCM_MIN_IV_LEN) || (ivlen > AES_GCM_MAX_IV_LEN)) {
++ hi_log_error("Invalid gcm iv len, ivlen = 0x%x.\n", ivlen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ cryp_symc_setiv(ctx, iv, ivlen, usage);
@@ -211327,13 +280163,12 @@ index 0000000..d49336a
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cyp_aead_ccm_n(hi_u8 *buf, hi_u8 *iv, hi_u32 ivlen,
-+ hi_u32 alen, hi_u32 enclen, hi_u32 tlen)
++static hi_s32 cyp_aead_ccm_n(cryp_symc_context *ctx, hi_u8 *buf, hi_u32 buf_len)
+{
+ hi_u32 idx = 0;
-+ hi_u32 q = 0;
++ hi_u32 q;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* Format B0
+ * The leading octet of the first block of the formatting, B0,
@@ -211353,16 +280188,16 @@ index 0000000..d49336a
+ * |Octet number 0 | 1 ... 15-q | 16-q ... 15 |
+ * |Contents Flags | N | Q |
+ * ---------------------------------------------
-+ */
-+ crypto_memset(buf, AES_BLOCK_SIZE, 0, AES_BLOCK_SIZE);
-+ buf[idx] = (alen > 0 ? 1 : 0) << 6; /* Adata */
-+ buf[idx] |= ((tlen - 2) / 2) << 3; /* (t -2)/2 */
-+ buf[idx] |= (15 - ivlen); /* q-1, n+q=15 */
++ */
++ crypto_memset(buf, buf_len, 0, buf_len);
++ buf[idx] = (ctx->alen > 0 ? AAD_EXIST : AAD_NOT_EXIST) << SHIFT_6BITS; /* descript: Adata exists or not. */
++ buf[idx] |= ((ctx->tlen - CRYPTO_NUM_2) / MUL_VAL_2) << SHIFT_3BITS; /* descript: (t -2) / 2 */
++ buf[idx] |= (N_AND_Q_VAL - ctx->ivlen); /* descript: q-1, n+q=15 */
+ idx++;
+
-+ /* copy N, skip Flags in byte0*/
-+ crypto_memcpy(&buf[idx], AES_BLOCK_SIZE - idx, &iv[1], ivlen - 1);
-+ idx += ivlen - 1;
++ /* copy N, skip Flags in byte0. */
++ crypto_memcpy(&buf[idx], AES_BLOCK_SIZE - idx, &ctx->iv[1], ctx->ivlen - 1);
++ idx += ctx->ivlen - 1;
+
+ q = AES_BLOCK_SIZE - idx;
+
@@ -211370,117 +280205,115 @@ index 0000000..d49336a
+ /* max payload len of 2^32, jump to the location of last word */
+ idx = AES_BLOCK_SIZE - SYMC_CCM_Q_LEN_4B;
+
-+ buf[idx++] = (hi_u8)(enclen >> 24);
-+ buf[idx++] = (hi_u8)(enclen >> 16);
-+ buf[idx++] = (hi_u8)(enclen >> 8);
-+ buf[idx++] = (hi_u8)(enclen);
-+ } else if ((q == SYMC_CCM_Q_LEN_3B) && (enclen <= SYMC_CCM_P_LEN_3B)) {
-+ /* max payload len of 2^24*/
-+ buf[idx++] = (hi_u8)(enclen >> 16);
-+ buf[idx++] = (hi_u8)(enclen >> 8);
-+ buf[idx++] = (hi_u8)(enclen);
-+ } else if ((q == SYMC_CCM_Q_LEN_2B) && (enclen <= SYMC_CCM_P_LEN_2B)) {
-+ /* max payload len of 2^16*/
-+ buf[idx++] = (hi_u8)(enclen >> 8);
-+ buf[idx++] = (hi_u8)(enclen);
++ buf[idx++] = (hi_u8)(ctx->enclen >> SHIFT_24BITS);
++ buf[idx++] = (hi_u8)(ctx->enclen >> SHIFT_16BITS);
++ buf[idx++] = (hi_u8)(ctx->enclen >> SHIFT_8BITS);
++ buf[idx++] = (hi_u8)(ctx->enclen);
++ } else if ((q == SYMC_CCM_Q_LEN_3B) && (ctx->enclen <= SYMC_CCM_P_LEN_3B)) {
++ /* max payload len of 2^24. */
++ buf[idx++] = (hi_u8)(ctx->enclen >> SHIFT_16BITS);
++ buf[idx++] = (hi_u8)(ctx->enclen >> SHIFT_8BITS);
++ buf[idx++] = (hi_u8)(ctx->enclen);
++ } else if ((q == SYMC_CCM_Q_LEN_2B) && (ctx->enclen <= SYMC_CCM_P_LEN_2B)) {
++ /* max payload len of 2^16. */
++ buf[idx++] = (hi_u8)(ctx->enclen >> SHIFT_8BITS);
++ buf[idx++] = (hi_u8)(ctx->enclen);
+ } else {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_u32 cyp_aead_gcm_clen(hi_u8 *buf, hi_u32 alen, hi_u32 enclen)
++static hi_u32 cyp_aead_gcm_clen(hi_u8 *buf, hi_u32 buf_len, hi_u32 alen, hi_u32 enclen)
+{
+ hi_u32 idx = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
++ crypto_unused(buf_len);
+
+ /* Format len(C), 16 byets, coding in bits.
+ * Byet0~7: bits number of Add
+ * Byet8~15: bits number of P
+ */
++ buf[idx++] = 0x00;
++ buf[idx++] = 0x00;
++ buf[idx++] = 0x00;
++ buf[idx++] = (hi_u8)((alen >> SHIFT_29BITS) & MAX_LOW_3BITS);
++ buf[idx++] = (hi_u8)((alen >> SHIFT_21BITS) & MAX_LOW_8BITS);
++ buf[idx++] = (hi_u8)((alen >> SHIFT_13BITS) & MAX_LOW_8BITS);
++ buf[idx++] = (hi_u8)((alen >> SHIFT_5BITS) & MAX_LOW_8BITS);
++ buf[idx++] = (hi_u8)((alen << SHIFT_3BITS) & MAX_LOW_8BITS);
+
+ buf[idx++] = 0x00;
+ buf[idx++] = 0x00;
+ buf[idx++] = 0x00;
-+ buf[idx++] = (hi_u8)((alen >> 29) & 0x07);
-+ buf[idx++] = (hi_u8)((alen >> 21) & 0xff);
-+ buf[idx++] = (hi_u8)((alen >> 13) & 0xff);
-+ buf[idx++] = (hi_u8)((alen >> 5) & 0xff);
-+ buf[idx++] = (hi_u8)((alen << 3) & 0xff);
-+
-+ buf[idx++] = 0x00;
-+ buf[idx++] = 0x00;
-+ buf[idx++] = 0x00;
-+ buf[idx++] = (hi_u8)((enclen >> 29) & 0x07);
-+ buf[idx++] = (hi_u8)((enclen >> 21) & 0xff);
-+ buf[idx++] = (hi_u8)((enclen >> 13) & 0xff);
-+ buf[idx++] = (hi_u8)((enclen >> 5) & 0xff);
-+ buf[idx++] = (hi_u8)((enclen << 3) & 0xff);
++ buf[idx++] = (hi_u8)((enclen >> SHIFT_29BITS) & MAX_LOW_3BITS);
++ buf[idx++] = (hi_u8)((enclen >> SHIFT_21BITS) & MAX_LOW_8BITS);
++ buf[idx++] = (hi_u8)((enclen >> SHIFT_13BITS) & MAX_LOW_8BITS);
++ buf[idx++] = (hi_u8)((enclen >> SHIFT_5BITS) & MAX_LOW_8BITS);
++ buf[idx++] = (hi_u8)((enclen << SHIFT_3BITS) & MAX_LOW_8BITS);
+
+ return idx;
+}
+
-+static hi_s32 cryp_aead_ccm_set_aad(void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen)
++static hi_s32 cryp_aead_ccm_set_aad(hi_void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* the parameter t denotes the octet length of T(tag)
+ * t is an element of { 4, 6, 8, 10, 12, 14, 16}
+ * here t is pConfig->u32TagLen
+ */
-+ if ((tlen & 0x01)
-+ || (tlen < AES_CCM_MIN_TAG_LEN)
-+ || (tlen > AES_CCM_MAX_TAG_LEN)) {
-+ HI_LOG_ERROR("Invalid tag len, tlen = 0x%x.\n", tlen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((tlen & 0x01) || (tlen < AES_CCM_MIN_TAG_LEN) || (tlen > AES_CCM_MAX_TAG_LEN)) {
++ hi_log_error("Invalid tag len, tlen = 0x%x.\n", tlen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ hisi_ctx->aad = aad;
+ hisi_ctx->alen = alen;
+ hisi_ctx->tlen = tlen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_aead_gcm_set_aad(void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen)
++static hi_s32 cryp_aead_gcm_set_aad(hi_void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if ((tlen < AES_GCM_MIN_TAG_LEN)
+ || (tlen > AES_GCM_MAX_TAG_LEN)) {
-+ HI_LOG_ERROR("Invalid tag len, tlen = 0x%x.\n", tlen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid tag len, tlen = 0x%x.\n", tlen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ hisi_ctx->aad = aad;
+ hisi_ctx->alen = alen;
+ hisi_ctx->tlen = tlen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static hi_s32 cryp_aead_crypto_zero(cryp_symc_context *hisi_ctx, hi_u32 wait)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* start running */
+ ret = drv_symc_start(hisi_ctx->hard_chn);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_start, ret);
++ hi_log_print_func_err(drv_symc_start, ret);
+ return ret;
+ }
+
@@ -211488,43 +280321,79 @@ index 0000000..d49336a
+ if (wait == HI_TRUE) {
+ ret = drv_symc_wait_done(hisi_ctx->hard_chn, CRYPTO_TIME_OUT);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_wait_done, ret);
++ hi_log_print_func_err(drv_symc_wait_done, ret);
+ return ret;
+ }
+
-+ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag);
++ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag, sizeof(hisi_ctx->tag));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_get_tag, ret);
++ hi_log_print_func_err(drv_aead_get_tag, ret);
+ return ret;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_aead_ccm_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 wait)
++static hi_s32 cryp_ccm_add_p(cryp_symc_context *hisi_ctx, symc_multi_pack *pack, hi_u32 wait)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
++
++ if (hisi_ctx->enclen == 0) {
++ compat_addr addr_null;
++ crypto_memset(&addr_null, sizeof(addr_null), 0, sizeof(addr_null));
++
++ /* Set CCM last flag. */
++ drv_symc_add_buf_usage(hisi_ctx->hard_chn, HI_TRUE, SYMC_NODE_USAGE_CCM_LAST);
++
++ /* If P is HI_NULL, must add a empty node into node list, limit to hardware devising */
++ ret = drv_symc_add_outbuf(hisi_ctx->hard_chn, addr_null, 0x00, SYMC_NODE_USAGE_LAST);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_symc_add_outbuf, ret);
++ return ret;
++ }
++
++ ret = cryp_aead_crypto_zero(hisi_ctx, wait);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_aead_crypto_zero, ret);
++ return ret;
++ }
++ } else {
++ /* for CCM, must set P last and ccm last flag */
++ pack->usage[pack->num - 1] = (hi_u32)pack->usage[pack->num - 1] |
++ (SYMC_NODE_USAGE_CCM_LAST | SYMC_NODE_USAGE_LAST);
++ ret = cryp_symc_crypto_process(hisi_ctx, wait);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_symc_crypto_process, ret);
++ return ret;
++ }
++
++ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag, sizeof(hisi_ctx->tag));
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(drv_aead_get_tag, ret);
++ return ret;
++ }
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 cryp_aead_ccm_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 wait)
++{
++ hi_s32 ret;
+ hi_u8 n[AES_BLOCK_SIZE] = {0};
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = cryp_symc_crypto_init(hisi_ctx, operation, input, output, length,
-+ usage_list, pkg_num, SYMC_NODE_USAGE_IN_CCM_P);
++ ret = cryp_symc_crypto_init(hisi_ctx, operation, pack, SYMC_NODE_USAGE_IN_CCM_P);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_crypto_init, ret);
++ hi_log_print_func_err(cryp_symc_crypto_init, ret);
+ return ret;
+ }
+
-+ /***
++ /*
+ * NIST Special Publication 800-38C
+ * The data that CCM protects consists of a message, i.e., a bit string,
+ * called the payload, denoted P, of bit length denoted Plen,
@@ -211533,165 +280402,124 @@ index 0000000..d49336a
+ * CCM provides assurance of the confidentiality of P and assurance of
+ * the authenticity of the origin of both A and P;
+ * confidentiality is not provided for A.
-+ ***/
-+
-+ /* Compute N */
-+ ret = cyp_aead_ccm_n(n,
-+ (hi_u8 *)hisi_ctx->iv,
-+ hisi_ctx->ivlen,
-+ hisi_ctx->alen,
-+ hisi_ctx->enclen,
-+ hisi_ctx->tlen);
++ * Compute N.
++ */
++ ret = cyp_aead_ccm_n(hisi_ctx, n, sizeof(n));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cyp_aead_ccm_n, ret);
++ hi_log_print_func_err(cyp_aead_ccm_n, ret);
+ return ret;
+ }
+
-+ ret = drv_aead_ccm_add_n(hisi_ctx->hard_chn, n);
++ ret = drv_aead_ccm_add_n(hisi_ctx->hard_chn, n, sizeof(n));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_ccm_add_n, ret);
++ hi_log_print_func_err(drv_aead_ccm_add_n, ret);
+ return ret;
+ }
+
+ /* Compute A */
+ ret = drv_aead_ccm_add_a(hisi_ctx->hard_chn, hisi_ctx->aad, hisi_ctx->alen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_ccm_add_a, ret);
++ hi_log_print_func_err(drv_aead_ccm_add_a, ret);
+ return ret;
+ }
+
-+ if (0 == hisi_ctx->enclen) {
-+ /*Set CCM last flag*/
-+ drv_symc_add_buf_usage(hisi_ctx->hard_chn,
-+ HI_TRUE,
-+ SYMC_NODE_USAGE_CCM_LAST);
-+
-+ /* If P is HI_NULL, must add a empty node into node list, limit to hardware devising*/
-+ ret = drv_symc_add_outbuf(hisi_ctx->hard_chn,
-+ ADDR_NULL,
-+ 0x00,
-+ SYMC_NODE_USAGE_LAST);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_outbuf, ret);
-+ return ret;
-+ }
-+
-+ ret = cryp_aead_crypto_zero(hisi_ctx, wait);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_aead_crypto_zero, ret);
-+ return ret;
-+ }
-+ } else {
-+ /* for CCM, must set P last and ccm last flag */
-+ usage_list[pkg_num - 1] = (hi_u32)usage_list[pkg_num - 1] | (SYMC_NODE_USAGE_CCM_LAST | SYMC_NODE_USAGE_LAST);
-+ ret = cryp_symc_crypto_process(hisi_ctx, wait);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_crypto_process, ret);
-+ return ret;
-+ }
-+
-+ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_get_tag, ret);
-+ return ret;
-+ }
++ /* Compute A */
++ ret = cryp_ccm_add_p(hisi_ctx, pack, wait);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_ccm_add_p, ret);
++ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_aead_gcm_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 wait)
++static hi_s32 cryp_aead_gcm_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 wait)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ cryp_symc_context *hisi_ctx = ctx;
+ hi_u8 clen[AES_BLOCK_SIZE] = {0};
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = cryp_symc_crypto_init(hisi_ctx, operation, input, output, length,
-+ usage_list, pkg_num, SYMC_NODE_USAGE_IN_GCM_P);
++ ret = cryp_symc_crypto_init(hisi_ctx, operation, pack, SYMC_NODE_USAGE_IN_GCM_P);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_crypto_init, ret);
++ hi_log_print_func_err(cryp_symc_crypto_init, ret);
+ return ret;
+ }
+
-+ /***
++ /*
+ * NIST Special Publication 800-38D
+ * A || P || Clen.
-+ ***/
-+
-+ /* Compute A */
++ * Compute A.
++ */
+ ret = drv_aead_gcm_add_a(hisi_ctx->hard_chn, hisi_ctx->aad, hisi_ctx->alen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_gcm_add_a, ret);
++ hi_log_print_func_err(drv_aead_gcm_add_a, ret);
+ return ret;
+ }
+
-+ if (0 == hisi_ctx->enclen) {
-+ /* At the and of GCM, must add a empty node to nodes list,
-+ * limit to hardware devising
++ if (hisi_ctx->enclen == 0) {
++ compat_addr addr_null;
++ crypto_memset(&addr_null, sizeof(addr_null), 0, sizeof(addr_null));
++ /*
++ * At the and of GCM, must add a empty node to nodes list,
++ * limit to hardware devising.
+ */
-+ ret = drv_symc_add_outbuf(hisi_ctx->hard_chn, ADDR_NULL, 0x00, SYMC_NODE_USAGE_LAST);
++ ret = drv_symc_add_outbuf(hisi_ctx->hard_chn, addr_null, 0x00, SYMC_NODE_USAGE_LAST);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_symc_add_outbuf, ret);
++ hi_log_print_func_err(drv_symc_add_outbuf, ret);
+ return ret;
+ }
+
-+ /*Format the length fields of C and add to nodes list*/
-+ cyp_aead_gcm_clen(clen, hisi_ctx->alen, 0x00);
-+ ret = drv_aead_gcm_add_clen(hisi_ctx->hard_chn, clen);
++ /* Format the length fields of C and add to nodes list. */
++ cyp_aead_gcm_clen(clen, sizeof(clen), hisi_ctx->alen, 0x00);
++ ret = drv_aead_gcm_add_clen(hisi_ctx->hard_chn, clen, sizeof(clen));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_gcm_add_clen, ret);
++ hi_log_print_func_err(drv_aead_gcm_add_clen, ret);
+ return ret;
+ }
+
+ ret = cryp_aead_crypto_zero(hisi_ctx, wait);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_aead_crypto_zero, ret);
++ hi_log_print_func_err(cryp_aead_crypto_zero, ret);
+ return ret;
+ }
+ } else {
-+ /* for GCM, must set P last and gcm last flag */
-+ usage_list[pkg_num - 1] = (hi_u32)usage_list[pkg_num - 1] | SYMC_NODE_USAGE_LAST;
++ /* for GCM, must set P last and gcm last flag. */
++ pack->usage[pack->num - BOUND_VAL_1] = (hi_u32)pack->usage[pack->num - BOUND_VAL_1] | SYMC_NODE_USAGE_LAST;
+ ret = cryp_symc_crypto_process(hisi_ctx, wait);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_crypto_process, ret);
++ hi_log_print_func_err(cryp_symc_crypto_process, ret);
+ return ret;
+ }
+
-+ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag);
++ ret = drv_aead_get_tag(hisi_ctx->hard_chn, hisi_ctx->tag, sizeof(hisi_ctx->tag));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(drv_aead_get_tag, ret);
++ hi_log_print_func_err(drv_aead_get_tag, ret);
+ return ret;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_aead_get_tag(void *ctx, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen)
++static hi_s32 cryp_aead_get_tag(hi_void *ctx, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(*taglen < hisi_ctx->tlen);
++ hi_log_chk_param_return(*taglen < hisi_ctx->tlen);
+
-+ HI_LOG_DEBUG("tag buffer len %d, tag len %d\n", *taglen, hisi_ctx->tlen);
++ hi_log_debug("tag buffer len %d, tag len %d\n", *taglen, hisi_ctx->tlen);
+
+ *taglen = hisi_ctx->tlen;
+
+ crypto_memcpy(tag, AEAD_TAG_SIZE, hisi_ctx->tag, hisi_ctx->tlen);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+#endif
@@ -211700,40 +280528,38 @@ index 0000000..d49336a
+{
+ hi_u32 i = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* check availability */
-+ if ((func->create == HI_NULL)
-+ || (func->crypto == HI_NULL)) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((func->create == HI_NULL) || (func->crypto == HI_NULL)) {
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ /* is it already registered? */
+ for (i = 0; i < SYMC_FUNC_TAB_SIZE; i++) {
-+ if (symc_descriptor[i].valid
-+ && symc_descriptor[i].alg == func->alg
-+ && symc_descriptor[i].mode == func->mode) {
-+ HI_LOG_FUNC_EXIT();
++ if ((g_symc_descriptor[i].valid) && (g_symc_descriptor[i].alg == func->alg) &&
++ (g_symc_descriptor[i].mode == func->mode)) {
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+ }
+
+ /* find a blank spot */
+ for (i = 0; i < SYMC_FUNC_TAB_SIZE; i++) {
-+ if (!symc_descriptor[i].valid) {
-+ crypto_memcpy(&symc_descriptor[i], sizeof(symc_func), func, sizeof(symc_func));
-+ symc_descriptor[i].valid = HI_TRUE;
-+ HI_LOG_DEBUG("symc_descriptor[%d], alg %d, mode %d\n", i,
-+ symc_descriptor[i].alg, symc_descriptor[i].mode);
++ if (g_symc_descriptor[i].valid == 0) {
++ crypto_memcpy(&g_symc_descriptor[i], sizeof(symc_func), func, sizeof(symc_func));
++ g_symc_descriptor[i].valid = HI_TRUE;
++ hi_log_debug("g_symc_descriptor[%d], alg %d, mode %d\n", i,
++ g_symc_descriptor[i].alg, g_symc_descriptor[i].mode);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+ }
+
+ /* Can't find a blank spot */
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_OVERFLOW);
++ hi_log_print_err_code(HI_ERR_CIPHER_OVERFLOW);
+ return HI_ERR_CIPHER_OVERFLOW;
+}
+
@@ -211742,36 +280568,36 @@ index 0000000..d49336a
+ hi_u32 i = 0;
+ symc_func *template = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* find the valid function */
+ for (i = 0; i < SYMC_FUNC_TAB_SIZE; i++) {
-+ HI_LOG_DEBUG("symc_descriptor[%d] valid %d, alg %d, mode %d \n",
-+ i, symc_descriptor[i].valid, symc_descriptor[i].alg, symc_descriptor[i].mode);
++ hi_log_debug("g_symc_descriptor[%d] valid %d, alg %d, mode %d \n",
++ i, g_symc_descriptor[i].valid, g_symc_descriptor[i].alg, g_symc_descriptor[i].mode);
+
-+ if (symc_descriptor[i].valid) {
-+ if (symc_descriptor[i].alg == alg
-+ && symc_descriptor[i].mode == mode) {
-+ template = &symc_descriptor[i];
++ if (g_symc_descriptor[i].valid) {
++ if (g_symc_descriptor[i].alg == alg
++ && g_symc_descriptor[i].mode == mode) {
++ template = &g_symc_descriptor[i];
+ break;
+ }
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return template;
+}
+
-+/***
++/*
+ * Defined the default template of Symmetric cipher function,
+ * the function can be replaced by other engine
+ */
-+static hi_s32 cryp_aes_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++static hi_s32 cryp_aes_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
-+ hi_u32 klen = 0;
++ hi_u32 klen;
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* set the key length depend on alg
+ * des/3des support 2key and 3key
@@ -211779,7 +280605,7 @@ index 0000000..d49336a
+ * sm1 support ak/ek/sk
+ * sm4 support 128
+ */
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
+ hisi_ctx->tdes2dma = HI_FALSE;
+
@@ -211797,40 +280623,72 @@ index 0000000..d49336a
+ break;
+ }
+ default: {
-+ HI_LOG_ERROR("aes with invalid keylen.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid aes key len: 0x%x\n", *hisi_klen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
-+ HI_LOG_INFO("key len %d, type %d\n", klen, hisi_klen);
++ hi_log_info("key len %d, type %d\n", klen, hisi_klen);
+
+ *hisi_klen = klen;
+
+ if (fkey == HI_NULL) {
+ hisi_ctx->hard_key = HI_TRUE;
+ hisi_ctx->klen = klen;
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
+ cryp_symc_setkey(ctx, fkey, klen, HI_FALSE);
+
-+ if (skey) {
++ if (skey != HI_NULL) {
+ cryp_symc_setkey(ctx, skey, klen, HI_TRUE);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_tdes_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++static hi_s32 cryp_tdes_chk_cpu_key(const hi_u8 *fkey, const hi_u32 *hisi_klen, hi_u32 *invalid, hi_u32 *klen)
+{
++ /* check k1 != k2. */
++ if (memcmp(&fkey[0], &fkey[DES_BLOCK_SIZE], DES_BLOCK_SIZE) == 0) {
++ *invalid = HI_TRUE;
++ }
++
++ switch (*hisi_klen) {
++ case HI_CIPHER_KEY_DES_2KEY: {
++ *klen = TDES_KEY_128BIT;
++ break;
++ }
++ case HI_CIPHER_KEY_DES_3KEY: {
++ *klen = TDES_KEY_192BIT;
++
++ /* check k2 != k3. */
++ if (memcmp(&fkey[DES_BLOCK_SIZE], &fkey[DES_BLOCK_SIZE * MUL_VAL_2], DES_BLOCK_SIZE) == 0) {
++ *invalid = HI_TRUE;
++ }
++ break;
++ }
++ default: {
++ hi_log_error("3des with invalid keylen, keylen = 0x%x.\n", *hisi_klen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARA);
++ return HI_ERR_CIPHER_INVALID_PARA;
++ }
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 cryp_tdes_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++{
++ hi_s32 ret;
+ hi_u32 klen = 0;
+ cryp_symc_context *hisi_ctx = ctx;
+ symc_capacity capacity;
+ hi_u32 invalid = HI_FALSE;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* set the key length depend on alg
+ * des/3des support 2key and 3key
@@ -211838,16 +280696,17 @@ index 0000000..d49336a
+ * sm1 support ak/ek/sk
+ * sm4 support 128
+ */
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
-+ CRYPTO_UNUSED(skey);
++ crypto_unused(skey);
+
+ hisi_ctx->tdes2dma = HI_FALSE;
+
+ if (fkey == HI_NULL) {
-+ if (HI_CIPHER_KEY_DES_2KEY != *hisi_klen) {
-+ HI_LOG_ERROR("error, tdes hard key must be 2key.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_ILLEGAL_KEY);
++ /* 3des use hard key. */
++ if (*hisi_klen != HI_CIPHER_KEY_DES_2KEY) {
++ hi_log_error("error, tdes hard key must be 2key.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_ILLEGAL_KEY);
+ return HI_ERR_CIPHER_ILLEGAL_KEY;
+ }
+
@@ -211855,73 +280714,51 @@ index 0000000..d49336a
+ hisi_ctx->klen = TDES_KEY_128BIT;
+ *hisi_klen = TDES_KEY_128BIT;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
+ /* get symc capacity */
+ drv_symc_get_capacity(&capacity);
-+
-+ /*check k1 != k2*/
-+ if (memcmp(&fkey[0], &fkey[8], DES_BLOCK_SIZE) == 0) {
-+ invalid = HI_TRUE;
-+ }
-+
-+ switch (*hisi_klen) {
-+ case HI_CIPHER_KEY_DES_2KEY: {
-+ klen = TDES_KEY_128BIT;
-+ break;
-+ }
-+ case HI_CIPHER_KEY_DES_3KEY: {
-+ klen = TDES_KEY_192BIT;
-+
-+ /*check k2 != k3*/
-+ if (memcmp(&fkey[8], &fkey[16], DES_BLOCK_SIZE) == 0) {
-+ invalid = HI_TRUE;
-+ }
-+ break;
-+ }
-+ default: {
-+ HI_LOG_ERROR("3des with invalid keylen, keylen = 0x%x.\n", *hisi_klen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
++ ret = cryp_tdes_chk_cpu_key(fkey, (const hi_u32 *)hisi_klen, &invalid, &klen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_symc_sm1_setsk, ret);
++ return ret;
+ }
+
+ if (invalid == HI_TRUE) {
+ if (capacity.dma == CRYPTO_CAPACITY_SUPPORT) {
-+ HI_LOG_ERROR("3des with invalid key.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
++ hi_log_error("3des with invalid key.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARA);
+ return HI_ERR_CIPHER_ILLEGAL_KEY;
+ }
+
-+ /* if don't support dma, the tdes with invalid key can be used as dma*/
++ /* if don't support dma, the tdes with invalid key can be used as dma. */
+ hisi_ctx->tdes2dma = HI_TRUE;
+ }
+
+ cryp_symc_setkey(ctx, fkey, klen, HI_FALSE);
+
+ *hisi_klen = klen;
-+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_des_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++static hi_s32 cryp_des_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
-+ CRYPTO_UNUSED(skey);
++ crypto_unused(skey);
+
+ hisi_ctx->tdes2dma = HI_FALSE;
+
+ if (fkey == HI_NULL) {
-+ HI_LOG_ERROR("error, des nonsupport hard key.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_ILLEGAL_KEY);
++ hi_log_error("error, des nonsupport hard key.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_ILLEGAL_KEY);
+ return HI_ERR_CIPHER_ILLEGAL_KEY;
+ }
+
@@ -211929,46 +280766,46 @@ index 0000000..d49336a
+
+ *hisi_klen = DES_KEY_SIZE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_3des2dma_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++static hi_s32 cryp_3des2dma_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
+ hi_u8 key[TDES_KEY_128BIT] = {0};
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
+
-+ CRYPTO_UNUSED(fkey);
-+ CRYPTO_UNUSED(skey);
++ crypto_unused(fkey);
++ crypto_unused(skey);
+
+ cryp_symc_setkey(ctx, key, TDES_KEY_128BIT, HI_FALSE);
+
+ *hisi_klen = TDES_KEY_128BIT;
+ hisi_ctx->tdes2dma = HI_TRUE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_sm1_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++static hi_s32 cryp_sm1_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_klen == HI_NULL);
-+ HI_LOG_CHECK_PARAM(*hisi_klen == HI_CIPHER_KEY_DEFAULT);
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
-+ CRYPTO_UNUSED(skey);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_klen == HI_NULL);
++ hi_log_chk_param_return(*hisi_klen == HI_CIPHER_KEY_DEFAULT);
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
++ crypto_unused(skey);
+
+ hisi_ctx->tdes2dma = HI_FALSE;
+
+ if (fkey == HI_NULL) {
+ hisi_ctx->hard_key = HI_TRUE;
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
@@ -211977,31 +280814,31 @@ index 0000000..d49336a
+ /* sm1 support ak/ek/sk */
+ ret = cryp_symc_sm1_setsk(ctx, skey);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_sm1_setsk, ret);
++ hi_log_print_func_err(cryp_symc_sm1_setsk, ret);
+ return ret;
+ }
+
+ *hisi_klen = SM1_AK_EK_SIZE;
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_sm4_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++static hi_s32 cryp_sm4_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
+ cryp_symc_context *hisi_ctx = ctx;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(hisi_klen == HI_NULL);
-+ HI_LOG_CHECK_PARAM(*hisi_klen != HI_CIPHER_KEY_DEFAULT);
-+ HI_LOG_CHECK_PARAM(hisi_ctx == HI_NULL);
-+ CRYPTO_UNUSED(skey);
++ hi_log_func_enter();
++ hi_log_chk_param_return(hisi_klen == HI_NULL);
++ hi_log_chk_param_return(*hisi_klen != HI_CIPHER_KEY_DEFAULT);
++ hi_log_chk_param_return(hisi_ctx == HI_NULL);
++ crypto_unused(skey);
+
+ hisi_ctx->tdes2dma = HI_FALSE;
+
+ if (fkey == HI_NULL) {
+ hisi_ctx->hard_key = HI_TRUE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+ }
+
@@ -212010,30 +280847,30 @@ index 0000000..d49336a
+
+ *hisi_klen = SM4_KEY_SIZE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cryp_symc_setiv_default(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
++static hi_s32 cryp_symc_setiv_default(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (iv == HI_NULL) {
+ return HI_SUCCESS;
+ }
+
+ if (ivlen > AES_IV_SIZE) {
-+ return HI_FAILURE;
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ cryp_symc_setiv(ctx, iv, ivlen, usage);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+/* Default As AES */
-+static void cryp_register_symc_default(symc_func *func, symc_alg alg, symc_mode mode)
++static hi_void cryp_register_symc_default(symc_func *func, symc_alg alg, symc_mode mode)
+{
+ crypto_memset(func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212049,10 +280886,10 @@ index 0000000..d49336a
+ return;
+}
+
-+static void cryp_register_symc_aes(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_symc_aes(hi_u32 capacity, symc_mode mode)
+{
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212060,12 +280897,11 @@ index 0000000..d49336a
+ cryp_register_symc_default(&func, SYMC_ALG_AES, mode);
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#ifdef SOFT_AES_SUPPORT
-+ else {
++ } else {
+ cryp_register_symc_default(&func, SYMC_ALG_AES, mode);
+ func.create = ext_mbedtls_symc_create;
+ func.destroy = ext_mbedtls_symc_destory;
@@ -212077,19 +280913,18 @@ index 0000000..d49336a
+ func.waitdone = HI_NULL;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#endif
-+
++ }
+ return;
+}
+
-+static void cryp_register_symc_dma(hi_u32 dma_capacity, hi_u32 tdes_capacity)
++static hi_void cryp_register_symc_dma(hi_u32 dma_capacity, hi_u32 tdes_capacity)
+{
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(func), 0, sizeof(func));
+
@@ -212101,7 +280936,7 @@ index 0000000..d49336a
+ func.crypto = cryp_symc_crypto;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+ } else if (tdes_capacity == CRYPTO_CAPACITY_SUPPORT) {
@@ -212113,19 +280948,19 @@ index 0000000..d49336a
+ func.crypto = cryp_symc_crypto;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+ }
+ return;
+}
+
-+static void cryp_register_symc_aes_cts(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_symc_aes_cts(hi_u32 capacity, symc_mode mode)
+{
+#ifdef SOFT_AES_CTS_SUPPORT
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_DEBUG("CTS crypto capacity %d, mode %d\n", capacity, mode);
++ hi_log_debug("CTS crypto capacity %d, mode %d\n", capacity, mode);
+
+ if (capacity != CRYPTO_CAPACITY_SUPPORT) {
+ symc_func func;
@@ -212135,10 +280970,10 @@ index 0000000..d49336a
+ cryp_register_symc_default(&func, SYMC_ALG_AES, mode);
+ func.crypto = cryp_aes_cbc_cts_crypto;
+ func.waitdone = HI_NULL;
-+ HI_LOG_DEBUG("CTS crypto 0x%p, mode %d\n", func.crypto, mode);
++ hi_log_debug("CTS crypto 0x%p, mode %d\n", func.crypto, mode);
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+ }
@@ -212146,12 +280981,12 @@ index 0000000..d49336a
+ return;
+}
+
-+static void cryp_register_aead_ccm(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_aead_ccm(hi_u32 capacity, symc_mode mode)
+{
+ if (capacity == CRYPTO_CAPACITY_SUPPORT) {
+#ifdef CHIP_AES_CCM_GCM_SUPPORT
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(func), 0, sizeof(func));
+
@@ -212162,14 +280997,14 @@ index 0000000..d49336a
+ func.setiv = cryp_aead_ccm_setiv;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+#endif
+ } else {
+#ifdef SOFT_AES_CCM_GCM_SUPPORT
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(func), 0, sizeof(func));
+
@@ -212187,7 +281022,7 @@ index 0000000..d49336a
+ func.waitdone = HI_NULL;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+#endif
@@ -212196,12 +281031,12 @@ index 0000000..d49336a
+ return;
+}
+
-+static void cryp_register_aead_gcm(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_aead_gcm(hi_u32 capacity, symc_mode mode)
+{
+ if (capacity == CRYPTO_CAPACITY_SUPPORT) {
+#ifdef CHIP_AES_CCM_GCM_SUPPORT
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212212,14 +281047,14 @@ index 0000000..d49336a
+ func.setiv = cryp_aead_gcm_setiv;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+#endif
+ } else {
+#ifdef SOFT_AES_CCM_GCM_SUPPORT
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212237,7 +281072,7 @@ index 0000000..d49336a
+ func.waitdone = HI_NULL;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+#endif
@@ -212246,10 +281081,10 @@ index 0000000..d49336a
+ return;
+}
+
-+static void cryp_register_symc_tdes(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_symc_tdes(hi_u32 capacity, symc_mode mode)
+{
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212258,12 +281093,11 @@ index 0000000..d49336a
+ func.setkey = cryp_tdes_setkey;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#ifdef SOFT_TDES_SUPPORT
-+ else {
++ } else {
+ cryp_register_symc_default(&func, SYMC_ALG_TDES, mode);
+ func.create = ext_mbedtls_symc_create;
+ func.destroy = ext_mbedtls_symc_destory;
@@ -212275,18 +281109,18 @@ index 0000000..d49336a
+ func.waitdone = HI_NULL;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#endif
++ }
+ return;
+}
+
-+static void cryp_register_symc_des(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_symc_des(hi_u32 capacity, symc_mode mode)
+{
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212295,12 +281129,11 @@ index 0000000..d49336a
+ func.setkey = cryp_des_setkey;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#ifdef SOFT_TDES_SUPPORT
-+ else {
++ } else {
+ cryp_register_symc_default(&func, SYMC_ALG_DES, mode);
+ func.create = ext_mbedtls_symc_create;
+ func.destroy = ext_mbedtls_symc_destory;
@@ -212312,18 +281145,18 @@ index 0000000..d49336a
+ func.waitdone = HI_NULL;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#endif
++ }
+ return;
+}
+
-+static void cryp_register_symc_sm1(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_symc_sm1(hi_u32 capacity, symc_mode mode)
+{
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212333,17 +281166,17 @@ index 0000000..d49336a
+ func.setkey = cryp_sm1_setkey;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
+ }
+ return;
+}
+
-+static void cryp_register_symc_sm4(hi_u32 capacity, symc_mode mode)
++static hi_void cryp_register_symc_sm4(hi_u32 capacity, symc_mode mode)
+{
+ symc_func func;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ crypto_memset(&func, sizeof(symc_func), 0, sizeof(symc_func));
+
@@ -212352,12 +281185,11 @@ index 0000000..d49336a
+ func.setkey = cryp_sm4_setkey;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#ifdef SOFT_SM4_SUPPORT
-+ else {
++ } else {
+ cryp_register_symc_default(&func, SYMC_ALG_SM4, mode);
+ func.create = ext_sm4_create;
+ func.destroy = ext_sm4_destory;
@@ -212368,29 +281200,30 @@ index 0000000..d49336a
+ func.crypto = ext_sm4_crypto;
+ ret = cryp_register_symc(&func);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_register_symc, ret);
++ hi_log_print_func_err(cryp_register_symc, ret);
+ return;
+ }
-+ }
+#endif
++ }
+ return;
+}
+
+/* symc function register */
-+static void cryp_register_all_symc(void)
++static hi_void cryp_register_all_symc(hi_void)
+{
+ symc_capacity capacity;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ crypto_memset(&capacity, sizeof(capacity), 0, sizeof(capacity));
+
+ /* get symc capacity */
+ drv_symc_get_capacity(&capacity);
+
-+ /* register the symc function if supported */
-+
-+ /* AES */
++ /*
++ * register the symc function if supported.
++ * AES.
++ */
+ cryp_register_symc_aes(capacity.aes_ecb, SYMC_MODE_ECB);
+ cryp_register_symc_aes(capacity.aes_cbc, SYMC_MODE_CBC);
+ cryp_register_symc_aes(capacity.aes_cfb, SYMC_MODE_CFB);
@@ -212431,125 +281264,140 @@ index 0000000..d49336a
+ cryp_register_symc_sm4(capacity.sm4_ofb, SYMC_MODE_OFB);
+ cryp_register_symc_sm4(capacity.sm4_ctr, SYMC_MODE_CTR);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+symc_func *cryp_get_symc_op(hi_cipher_alg alg, hi_cipher_work_mode mode)
++static hi_s32 cryp_get_symc_alg(hi_cipher_alg alg, symc_alg *cryp_alg)
+{
-+ hi_u32 cryp_mode = 0;
-+ symc_func *func = HI_NULL;
-+ symc_alg cryp_alg;
-+
-+ HI_LOG_FUNC_ENTER();
++ symc_alg local_alg;
+
+ switch (alg) {
+ case HI_CIPHER_ALG_DES:
-+ cryp_alg = SYMC_ALG_DES;
++ local_alg = SYMC_ALG_DES;
+ break;
+ case HI_CIPHER_ALG_3DES:
-+ cryp_alg = SYMC_ALG_TDES;
++ local_alg = SYMC_ALG_TDES;
+ break;
+ case HI_CIPHER_ALG_AES:
-+ cryp_alg = SYMC_ALG_AES;
++ local_alg = SYMC_ALG_AES;
+ break;
+ case HI_CIPHER_ALG_SM1:
-+ cryp_alg = SYMC_ALG_SM1;
++ local_alg = SYMC_ALG_SM1;
+ break;
+ case HI_CIPHER_ALG_SM4:
-+ cryp_alg = SYMC_ALG_SM4;
++ local_alg = SYMC_ALG_SM4;
+ break;
+ case HI_CIPHER_ALG_DMA:
-+ cryp_alg = SYMC_ALG_NULL_CIPHER;
-+ mode = HI_CIPHER_WORK_MODE_ECB;
++ local_alg = SYMC_ALG_NULL_CIPHER;
+ break;
+ default:
-+ HI_LOG_ERROR("Invalid alg, alg = 0x%x.\n", alg);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_NULL;
++ hi_log_error("Invalid alg, alg = 0x%x.\n", alg);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
++ *cryp_alg = local_alg;
++ return HI_SUCCESS;
++}
++
++static hi_s32 cryp_get_symc_mode(hi_cipher_work_mode mode, symc_mode *cryp_mode)
++{
++ symc_mode local_mode;
+ switch (mode) {
+ case HI_CIPHER_WORK_MODE_ECB:
-+ cryp_mode = SYMC_MODE_ECB;
++ local_mode = SYMC_MODE_ECB;
+ break;
+ case HI_CIPHER_WORK_MODE_CBC:
-+ cryp_mode = SYMC_MODE_CBC;
++ local_mode = SYMC_MODE_CBC;
+ break;
+ case HI_CIPHER_WORK_MODE_CFB:
-+ cryp_mode = SYMC_MODE_CFB;
++ local_mode = SYMC_MODE_CFB;
+ break;
+ case HI_CIPHER_WORK_MODE_OFB:
-+ cryp_mode = SYMC_MODE_OFB;
++ local_mode = SYMC_MODE_OFB;
+ break;
+ case HI_CIPHER_WORK_MODE_CTR:
-+ cryp_mode = SYMC_MODE_CTR;
++ local_mode = SYMC_MODE_CTR;
+ break;
+ case HI_CIPHER_WORK_MODE_CCM:
-+ cryp_mode = SYMC_MODE_CCM;
++ local_mode = SYMC_MODE_CCM;
+ break;
+ case HI_CIPHER_WORK_MODE_GCM:
-+ cryp_mode = SYMC_MODE_GCM;
++ local_mode = SYMC_MODE_GCM;
+ break;
+ default:
-+ HI_LOG_ERROR("Invalid mode, mode = 0x%x.\n", mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_NULL;
++ hi_log_error("Invalid mode, mode = 0x%x.\n", mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ *cryp_mode = local_mode;
++ return HI_SUCCESS;
++}
++
++symc_func *cryp_get_symc_op(hi_cipher_alg alg, hi_cipher_work_mode mode)
++{
++ hi_s32 ret;
++ symc_mode cryp_mode = 0;
++ symc_func *func = HI_NULL;
++ symc_alg cryp_alg = 0;
++ hi_cipher_work_mode local_mode;
++
++ hi_log_func_enter();
++
++ ret = cryp_get_symc_alg(alg, &cryp_alg);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_get_symc_alg, ret);
++ return HI_NULL;
++ }
++
++ if (alg == HI_CIPHER_ALG_DMA) {
++ local_mode = HI_CIPHER_WORK_MODE_ECB;
++ } else {
++ local_mode = mode;
++ }
++
++ ret = cryp_get_symc_mode(local_mode, &cryp_mode);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cryp_get_symc_mode, ret);
++ return HI_NULL;
+ }
+
+ func = cryp_get_symc(cryp_alg, cryp_mode);
++ if (func == HI_NULL) {
++ hi_log_print_func_err(cryp_get_symc, HI_ERR_CIPHER_INVALID_POINT);
++ return HI_NULL;
++ }
+
-+ HI_LOG_FUNC_EXIT();
-+
++ hi_log_func_exit();
+ return func;
+}
-+
-+/** @}*/ /** <!-- ==== API Code end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_trng.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_trng.c
new file mode 100644
-index 0000000..243c6a4
+index 0000000..7702a22
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/cryp_trng.c
-@@ -0,0 +1,122 @@
+@@ -0,0 +1,100 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for cipher cryp trng.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
+#include "drv_trng.h"
+#include "cryp_trng.h"
+
-+/********************** Internal Structure Definition ************************/
-+/** \addtogroup trng */
-+/** @{*/ /** <!-- [trng]*/
-+
+/* the max continuous bits of randnum is allowed */
+#define CONTINUOUS_BITS_ALLOWD 0x08
+
+/* times try to read rang */
+#define RANG_READ_TRY_TIME 0x40
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup trng drivers*/
-+/** @{*/ /** <!-- [trng]*/
-+
++/* ****************************** API Code **************************** */
+#ifdef CHIP_TRNG_SUPPORT
+static hi_s32 cryp_trng_check(hi_u32 randnum)
+{
@@ -212560,7 +281408,7 @@ index 0000000..243c6a4
+
+ /* compare with last rand number */
+ if (randnum == lastrand) {
-+ return HI_FAILURE;
++ return HI_ERR_CIPHER_NO_AVAILABLE_RNG;
+ }
+
+ /* update last randnum */
@@ -212568,10 +281416,10 @@ index 0000000..243c6a4
+ byte = (hi_u8 *)&randnum;
+
+ /* continuous 8 bits0 or bit1 is prohibited */
-+ for (i = 0; i < 4; i++) {
++ for (i = 0; i < WORD_WIDTH; i++) {
+ /* compare with 0x00 and 0xff */
+ if ((byte[i] == 0x00) || (byte[i] == 0xff)) {
-+ return HI_FAILURE;
++ return HI_ERR_CIPHER_NO_AVAILABLE_RNG;
+ }
+ }
+#else
@@ -212585,16 +281433,16 @@ index 0000000..243c6a4
+
+hi_s32 cryp_trng_get_random(hi_u32 *randnum, hi_u32 timeout)
+{
-+ hi_u32 i = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_u32 i;
++ hi_s32 ret;
+ trng_capacity capacity;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ drv_trng_get_capacity(&capacity);
+ if (!capacity.trng) {
-+ HI_LOG_ERROR("error, trng nonsupport\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_UNSUPPORTED);
++ hi_log_error("error, trng nonsupport\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_UNSUPPORTED);
+ return HI_ERR_CIPHER_UNSUPPORTED;
+ }
+
@@ -212611,11 +281459,11 @@ index 0000000..243c6a4
+ }
+
+ if (i >= RANG_READ_TRY_TIME) {
-+ HI_LOG_ERROR("error, trng randnum check failed\n");
++ hi_log_error("error, trng randnum check failed\n");
+ return HI_ERR_CIPHER_NO_AVAILABLE_RNG;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
@@ -212624,67 +281472,40 @@ index 0000000..243c6a4
+
+hi_s32 cryp_trng_get_random(hi_u32 *randnum, hi_u32 timeout)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ get_random_bytes((hi_u8 *)randnum, WORD_WIDTH);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+#endif
-+
-+/** @}*/ /** <!-- ==== API Code end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_hash.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_hash.h
new file mode 100644
-index 0000000..bc8eba5
+index 0000000..7063307
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_hash.h
-@@ -0,0 +1,104 @@
+@@ -0,0 +1,77 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cryp hash.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __CRYP_HASH_H_
+#define __CRYP_HASH_H_
+
-+#include "drv_osal_lib.h"
++#include "drv_cipher_kapi.h"
+#include "drv_hash.h"
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!--[hash]*/
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+/**
-+* \brief Initialize crypto of hash *
-+*/
++/* Initialize crypto of hash. */
+hi_s32 cryp_hash_init(hi_void);
+
-+/**
-+* \brief Deinitialize crypto of hash
-+*/
++/* Deinitialize crypto of hash. */
+hi_void cryp_hash_deinit(hi_void);
+
-+/**
++/*
+ * \brief Create hash handle
+ *
+ * \param mode Hash mode
@@ -212692,14 +281513,14 @@ index 0000000..bc8eba5
+ */
+typedef hi_void *(*func_hash_create)(hash_mode mode);
+
-+/**
++/*
+ * \brief Clear hash context
+ *
+ * \param ctx symc handle to be destory
+ */
-+typedef hi_s32 (*func_hash_destory)( hi_void *ctx);
++typedef hi_s32 (*func_hash_destory)(hi_void *ctx);
+
-+/**
++/*
+ * \brief Hash message chunk calculation
+ *
+ * Note: the message must be write to the buffer
@@ -212711,425 +281532,345 @@ index 0000000..bc8eba5
+ * \param length length of hash message
+ * \param src source of hash message
+ */
-+typedef hi_s32 (*func_hash_update)( hi_void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src);
++typedef hi_s32 (*func_hash_update)(hi_void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src);
+
-+/**
++/*
+ * \brief HASH final digest
+ *
+ * \param ctx Hash handle
+ * \param hash HASH checksum result
+ * \param hashlen Length of HASH checksum result
+ */
-+typedef hi_s32 (*func_hash_finish)( hi_void *ctx, hi_void *hash, hi_u32 *hashlen);
++typedef hi_s32 (*func_hash_finish)(hi_void *ctx, hi_void *hash, hi_u32 hash_buf_len, hi_u32 *hashlen);
+
-+/*! \struct of Hash function template */
++/* struct of Hash function template. */
+typedef struct {
-+ hi_u32 valid; /*!< vliad or not */
-+ hi_u32 mode; /*!< Mode of Hash */
-+ hi_u32 block_size; /*!< block size */
-+ hi_u32 size; /*!< hash output size */
-+ func_hash_create create; /*!< Create function */
-+ func_hash_destory destroy; /*!< destroy function */
-+ func_hash_update update; /*!< update function */
-+ func_hash_finish finish; /*!< finish function */
++ hi_u32 valid; /* vliad or not */
++ hi_u32 mode; /* Mode of Hash */
++ hi_u32 block_size; /* block size */
++ hi_u32 size; /* hash output size */
++ func_hash_create create; /* Create function */
++ func_hash_destory destroy; /* destroy function */
++ func_hash_update update; /* update function */
++ func_hash_finish finish; /* finish function */
+} hash_func;
+
-+/**
-+\brief Clone the function from template of hash engine.
-+\param[out] func The struct of function.
-+\param[in] mode The work mode.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief Clone the function from template of hash engine.
++ * \param[out] func The struct of function.
++ * \param[in] mode The work mode.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hash_func *cryp_get_hash(hash_mode mode);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_rsa.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_rsa.h
new file mode 100644
-index 0000000..30d40f0
+index 0000000..f3ef7b4
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_rsa.h
-@@ -0,0 +1,136 @@
+@@ -0,0 +1,104 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file cryp hash.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __CRYP_RSA_H_
+#define __CRYP_RSA_H_
+
++#include "drv_cipher_kapi.h"
+#include "drv_osal_lib.h"
+#include "drv_srsa.h"
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup rsa */
-+/** @{ */ /** <!--[rsa]*/
++#define CRYP_TRNG_TIMEOUT (-1)
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++typedef enum {
++ RSA_BLOCK_YTPE_0 = 0X0,
++ RSA_BLOCK_YTPE_1,
++ RSA_BLOCK_YTPE_2,
++} rsa_pkcs1_padding_type;
+
-+/******************************* API Code *****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
++typedef struct {
++ hi_u32 mode;
++ hi_u32 klen;
++ hi_u8 *in;
++ hi_u32 in_len;
++ hi_u8 *out;
++ hi_u32 *out_len;
++ hi_u8 bt;
++} rsa_padding_pack;
+
-+/**
-+* \brief Initialize crypto of rsa *
-+*/
++/*
++ * brief Initialize crypto of rsa *
++ */
+hi_s32 cryp_rsa_init(hi_void);
+
-+/**
-+* \brief Deinitialize crypto of rsa *
-+*/
++/*
++ * brief Deinitialize crypto of rsa *
++ */
+hi_void cryp_rsa_deinit(hi_void);
+
-+/**
-+\brief RSA encryption a plaintext with a RSA key.
-+\param[in] key: rsa key.
-+\param[in] scheme: rsa encrypt scheme.
-+\param[in] in: input data to be encryption
-+\param[in] in: input data to be encryption
-+\param[out] inlen: length of input data to be encryption
-+\param[out] out: output data to be encryption
-+\param[out] outlen: length of output data to be encryption
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\see \n
-+N/A
-+*/
-+hi_s32 cryp_rsa_encrypt(cryp_rsa_key *key, hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen);
++/*
++ * brief RSA encryption a plaintext with a RSA key.
++ * param[in] key: rsa key.
++ * param[in] rsa_crypt: rsa encrypt data.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * see \n
++ * N/A
++ */
++hi_s32 cryp_rsa_encrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa_crypt);
+
-+/**
-+\brief RSA decryption a plaintext with a RSA key.
-+\param[in] key: rsa key.
-+\param[in] scheme: rsa encrypt scheme.
-+\param[in] in: input data to be encryption
-+\param[in] in: input data to be encryption
-+\param[out] inlen: length of input data to be encryption
-+\param[out] out: output data to be encryption
-+\param[out] outlen: length of output data to be encryption
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\see \n
-+N/A
-+*/
-+hi_s32 cryp_rsa_decrypt(cryp_rsa_key *key, hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen);
++/*
++ * brief RSA decryption a plaintext with a RSA key.
++ * param[in] key: rsa key.
++ * param[in] rsa_crypt: rsa decrypt data.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * see \n
++ * N/A
++ */
++hi_s32 cryp_rsa_decrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa_crypt);
+
-+/**
-+\brief RSA sign a hash value with a RSA private key.
-+\param[in] key: rsa key.
-+\param[in] scheme: rsa sign scheme.
-+\param[in] in: input data to be encryption
-+\param[in] in: input data to be encryption
-+\param[out] inlen: length of input data to be encryption
-+\param[out] out: output data to be encryption
-+\param[out] outlen: length of output data to be encryption
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\see \n
-+N/A
-+*/
-+hi_s32 cryp_rsa_sign_hash(cryp_rsa_key *key, hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen, hi_u32 saltlen);
++/*
++ * brief RSA sign a hash value with a RSA private key.
++ * param[in] key: rsa key.
++ * param[in] rsa_sign: rsa sign data.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * see \n
++ * N/A
++ */
++hi_s32 cryp_rsa_sign_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa_sign);
+
-+/**
-+\brief RSA verify a hash value with a RSA public key.
-+\param[in] key: rsa key.
-+\param[in] scheme: rsa sign scheme.
-+\param[in] in: input data to be encryption
-+\param[in] in: input data to be encryption
-+\param[out] inlen: length of input data to be encryption
-+\param[out] out: output data to be encryption
-+\param[out] outlen: length of output data to be encryption
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\see \n
-+N/A
-+*/
-+hi_s32 cryp_rsa_verify_hash(cryp_rsa_key *key, hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *sign, hi_u32 signlen, hi_u32 saltlen);
++/*
++ * brief RSA verify a hash value with a RSA public key.
++ * param[in] key: rsa key.
++ * param[in] rsa_verify: rsa sign data.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * see \n
++ * N/A
++ */
++hi_s32 cryp_rsa_verify_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa_verify);
+
-+/**
-+\brief Generate a RSA private key.
-+\param[in] numbits: bit numbers of the integer public modulus.
-+\param[in] exponent: value of public exponent
-+\param[out] key: rsa key.
-+\retval ::HI_SUCCESS Call this API successful.
-+\retval ::HI_FAILURE Call this API fails.
-+\see \n
-+N/A
-+*/
++/*
++ * brief Generate a RSA private key.
++ * param[in] numbits: bit numbers of the integer public modulus.
++ * param[in] exponent: value of public exponent
++ * param[out] key: rsa key.
++ * retval ::HI_SUCCESS Call this API successful.
++ * retval ::HI_FAILURE Call this API fails.
++ * see \n
++ * N/A
++ */
+hi_s32 cryp_rsa_gen_key(hi_u32 numbits, hi_u32 exponent, cryp_rsa_key *key);
+
-+/**
-+\brief Generate random.
-+N/A
-+*/
++/*
++ * brief Generate random.
++ * N/A
++ */
+int mbedtls_get_random(hi_void *param, hi_u8 *rand, size_t size);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_symc.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_symc.h
new file mode 100644
-index 0000000..143d961
+index 0000000..3857809
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_symc.h
-@@ -0,0 +1,216 @@
+@@ -0,0 +1,181 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cryp symc.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef CRYP_SYMC_H_
+#define CRYP_SYMC_H_
+
++#include "hi_cipher_compat.h"
++#include "drv_cipher_kapi.h"
+#include "drv_osal_lib.h"
+#include "drv_symc.h"
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup aes */
-+/** @{ */ /** <!--[aes]*/
-+
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+
-+/**
-+* \brief Initialize crypto of symc *
-+*/
++/*
++ * brief Initialize crypto of symc
++ */
+hi_s32 cryp_symc_init(hi_void);
+
-+/**
-+* \brief Deinitialize crypto of symc *
-+*/
++/*
++ * brief Deinitialize crypto of symc
++ */
+hi_void cryp_symc_deinit(hi_void);
+
-+/**
-+ * \brief Create symc handle
++/*
++ * brief Create symc handle
+ *
-+ * \param handle symc handle to be initialized
-+ * \param chn symc channel
++ * param handle symc handle to be initialized
++ * param chn symc channel
+ */
-+typedef hi_void *(*func_symc_create)( hi_u32 hard_chn );
++typedef hi_void *(*func_symc_create)(hi_u32 hard_chn);
+
+/**
-+ * \brief Clear symc context
++ * brief Clear symc context
+ *
-+ * \param handle symc handle to be destory
++ * param handle symc handle to be destory
+ */
-+typedef hi_s32 (*func_symc_destroy)( hi_void *ctx);
++typedef hi_s32 (*func_symc_destroy)(hi_void *ctx);
+
+/**
-+ * \brief symc key schedule
++ * brief symc key schedule
+ *
-+ * \param handle SYMC handle
-+ * \param[in] fkey first key buffer, defualt
-+ * \param[in] skey second key buffer, expand
-+ * \param hisi_klen input key type, output key length in bytes
++ * param handle symc handle
++ * param[in] fkey first key buffer, defualt
++ * param[in] skey second key buffer, expand
++ * param hisi_klen input key type, output key length in bytes
+ *
-+ * \return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
++ * return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
+ */
-+typedef hi_s32 (*func_symc_setkey)( hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
++typedef hi_s32 (*func_symc_setkey)(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
+
+/**
-+ * \brief Symc iv schedule
++ * brief Symc iv schedule
+ *
-+ * \param handle symc handle
-+ * \param IV Symc IV
-+ * \param ivlen length of iv
++ * param handle symc handle
++ * param IV Symc IV
++ * param ivlen length of iv
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+typedef hi_s32 (*func_symc_setiv)( hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
++typedef hi_s32 (*func_symc_setiv)(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
+
+/**
-+ * \brief Symc iv schedule
++ * brief Symc iv schedule
+ *
-+ * \param handle symc handle
-+ * \param IV Symc IV
-+ * \param ivlen must be 128, 192 or 256
++ * param handle symc handle
++ * param IV Symc IV
++ * param ivlen must be 128, 192 or 256
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+typedef hi_void (*func_symc_getiv)( hi_void *ctx, hi_u8 *iv, hi_u32 *ivlen);
++typedef hi_void (*func_symc_getiv)(hi_void *ctx, hi_u8 *iv, hi_u32 *ivlen);
+
+/**
-+ * \brief SYMC alg and mode
++ * brief SYMC alg and mode
+ *
-+ * \param handle SYMC handle
-+ * \param alg Symmetric cipher alg
-+ * \param mode Symmetric cipher mode
-+ * \param keybits must be 128, 192 or 256
++ * param handle SYMC handle
++ * param alg Symmetric cipher alg
++ * param mode Symmetric cipher mode
++ * param keybits must be 128, 192 or 256
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+typedef hi_void (*func_symc_setmode)( hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width);
++typedef hi_void (*func_symc_setmode)(hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width);
+
+/**
-+ * \brief SYMC wait done
++ * brief SYMC wait done
+ *
-+ * \param ctx SYMC handle
-+ * \return 0 if successful.
++ * param ctx SYMC handle
++ * return 0 if successful.
+ */
+typedef hi_s32 (*func_symc_wait_done)(hi_void *ctx, hi_u32 timeout);
+
+/**
-+ * \brief SYMC alg and mode
++ * brief SYMC alg and mode
+ *
-+ * \param handle SYMC handle
-+ * \param round SM1 round number
++ * param handle SYMC handle
++ * param round SM1 round number
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+typedef hi_s32 (*func_symc_sm1_setround)( hi_void *ctx, hi_u32 round);
++typedef hi_s32 (*func_symc_sm1_setround)(hi_void *ctx, hi_u32 round);
+
+/**
-+ * \brief symc buffer encryption/decryption.
++ * brief symc buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param handle symc handle
-+ * \param operation decrypt or encrypt
-+ * \param mode mode
-+ * \param length length of the input data
-+ * \param input buffer holding the input data
-+ * \param output buffer holding the output data
-+ * \param usage_list usage of buffer
-+ * \param pkg_num numbers of buffer
-+ * \param last last or not
++ * param ctx symc ctx
++ * param operation decrypt or encrypt
++ * param pack package for encrypt or decrypt.
++ * param wait last or not
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+typedef hi_s32 (*func_symc_crypto)(hi_void *ctx, hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num,
-+ hi_u32 wait);
++typedef hi_s32 (*func_symc_crypto)(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 wait);
+
+/**
-+ * \brief CCM/GCM set Associated Data
++ * brief CCM/GCM set Associated Data
+ *
-+ * \param ctx SYMC handle
-+ * \param aad Associated Data
-+ * \param alen Associated Data Length
-+ * \param tlen Tag length
++ * param ctx SYMC handle
++ * param aad Associated Data
++ * param alen Associated Data Length
++ * param tlen Tag length
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+typedef hi_s32 (*func_aead_set_aad)( hi_void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen);
++typedef hi_s32 (*func_aead_set_aad)(hi_void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen);
+
+/**
-+ * \brief SYMC multiple buffer encryption/decryption.
-+ * \param[in] id The channel number.
-+ * \param[in] tag tag data of CCM/GCM
-+ * \param uuid uuid The user identification.
++ * brief SYMC multiple buffer encryption/decryption.
++ * param[in] id The channel number.
++ * param[in] tag tag data of CCM/GCM
++ * param uuid uuid The user identification.
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
+typedef hi_s32 (*func_aead_get_tag)(hi_void *ctx, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen);
+
-+/*! \struct of Symmetric cipher function template */
++/* struct of Symmetric cipher function template */
+typedef struct {
-+ hi_u32 valid; /*!< vliad or not */
-+ symc_alg alg; /*!< Alg of Symmetric cipher */
-+ symc_mode mode; /*!< Mode of Symmetric cipher */
-+ func_symc_setmode setmode; /*!< Set mode function */
-+ func_symc_sm1_setround setround; /*!< SM1 set round function */
-+ func_symc_create create; /*!< Create function */
-+ func_symc_destroy destroy; /*!< destroy function */
-+ func_symc_setkey setkey; /*!< setkey function */
-+ func_symc_setiv setiv; /*!< setiv function */
-+ func_symc_getiv getiv; /*!< getiv function */
-+ func_aead_set_aad setadd; /*!< setadd function */
-+ func_aead_get_tag gettag; /*!< get tag function */
-+ func_symc_crypto crypto; /*!< crypto function */
-+ func_symc_wait_done waitdone; /*!< wait done */
++ hi_u32 valid; /* vliad or not */
++ symc_alg alg; /* Alg of Symmetric cipher */
++ symc_mode mode; /* Mode of Symmetric cipher */
++ func_symc_setmode setmode; /* Set mode function */
++ func_symc_sm1_setround setround; /* SM1 set round function */
++ func_symc_create create; /* Create function */
++ func_symc_destroy destroy; /* destroy function */
++ func_symc_setkey setkey; /* setkey function */
++ func_symc_setiv setiv; /* setiv function */
++ func_symc_getiv getiv; /* getiv function */
++ func_aead_set_aad setadd; /* setadd function */
++ func_aead_get_tag gettag; /* get tag function */
++ func_symc_crypto crypto; /* crypto function */
++ func_symc_wait_done waitdone; /* wait done */
+} symc_func;
+
-+/**
-+\brief symc alloc channel.
-+\param[out] hard_chn symc channel.
-+\retval On success, func is returned. On error, HI_NULL is returned.
-+*/
++/*
++ * brief symc alloc channel.
++ * param[out] hard_chn symc channel.
++ * retval On success, func is returned. On error, HI_NULL is returned.
++ */
+hi_s32 cryp_symc_alloc_chn(hi_u32 *hard_chn);
+
-+/**
-+\brief symc free channel.
-+\param[in] hard_chn symc channel.
-+\retval On success, func is returned. On error, HI_NULL is returned.
-+*/
++/*
++ * brief symc free channel.
++ * param[in] hard_chn symc channel.
++ * retval On success, func is returned. On error, HI_NULL is returned.
++ */
+hi_void cryp_symc_free_chn(hi_u32 hard_chn);
+
-+/**
-+\brief Clone the function from template of aes engine.
-+\param[in] alg The alg of Symmetric cipher.
-+\param[in] mode The work mode.
-+\retval On success, func is returned. On error, HI_NULL is returned.
-+*/
++/*
++ * brief Clone the function from template of aes engine.
++ * param[in] alg The alg of Symmetric cipher.
++ * param[in] mode The work mode.
++ * retval On success, func is returned. On error, HI_NULL is returned.
++ */
+symc_func *cryp_get_symc_op(hi_cipher_alg alg, hi_cipher_work_mode mode);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
-+
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_trng.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_trng.h
new file mode 100644
-index 0000000..c6163a0
+index 0000000..6cf0501
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/crypto/include/cryp_trng.h
-@@ -0,0 +1,44 @@
+@@ -0,0 +1,21 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cipher cryp trng.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __CRYP_TRNG_H_
@@ -213138,48 +281879,25 @@ index 0000000..c6163a0
+#include "drv_osal_lib.h"
+#include "drv_trng.h"
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup trng */
-+/** @{ */ /** <!--[trng]*/
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup trng drivers*/
-+/** @{*/ /** <!-- [trng]*/
-+
-+/**
-+\brief get rand number.
-+\param[out] randnum rand number.
-+\param[in] timeout time out.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
-+hi_s32 cryp_trng_get_random( hi_u32 *randnum, hi_u32 timeout );
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
++/*
++ * brief get rand number.
++ * param[out] randnum rand number.
++ * param[in] timeout time out.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
++hi_s32 cryp_trng_get_random(hi_u32 *randnum, hi_u32 timeout);
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_aead.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_aead.c
new file mode 100644
-index 0000000..7fc62ca
+index 0000000..484b6c4
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_aead.c
-@@ -0,0 +1,348 @@
+@@ -0,0 +1,333 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
++ * Description : ext for aes ccm and gcm.
++ * Author : Hisilicon multimedia software group
++ * Create : 2018-10-23
+ */
+
+#include "drv_osal_lib.h"
@@ -213189,81 +281907,86 @@ index 0000000..7fc62ca
+
+#ifdef SOFT_AES_CCM_GCM_SUPPORT
+
-+/**
-+ * \brief aes ccm context structure
++/*
++ * aes ccm context structure
+ */
+typedef struct {
-+ hi_u32 key[SYMC_KEY_SIZE / 4]; /*!< SYMC even round keys, default */
-+ hi_u32 iv[AES_IV_SIZE / 4]; /*!< symc IV */
-+ hi_u32 tag[AEAD_TAG_SIZE / 4]; /*!< aead tag */
-+ hi_u32 ivlen; /*!< symc IV length */
-+ hi_u32 klen; /*!< symc key length */
-+ compat_addr aad; /*!< Associated Data */
-+ hi_u32 alen; /*!< Associated Data length */
-+ hi_u32 tlen; /*!< Tag length */
-+}
-+ext_aead_context;
++ hi_u32 key[SYMC_KEY_SIZE / WORD_WIDTH]; /* SYMC even round keys, default */
++ hi_u32 iv[AES_IV_SIZE / WORD_WIDTH]; /* symc IV */
++ hi_u32 tag[AEAD_TAG_SIZE / WORD_WIDTH]; /* aead tag */
++ hi_u32 ivlen; /* symc IV length */
++ hi_u32 klen; /* symc key length */
++ compat_addr aad; /* Associated Data */
++ hi_u32 alen; /* Associated Data length */
++ hi_u32 tlen; /* Tag length */
++} ext_aead_context;
+
-+void *ext_mbedtls_aead_create(hi_u32 hard_chn)
++typedef struct {
++ crypto_mem in;
++ crypto_mem out;
++ crypto_mem aad;
++} ext_ccm_gcm_mem;
++
++hi_void *ext_mbedtls_aead_create(hi_u32 hard_chn)
+{
+ ext_aead_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ctx = crypto_calloc(1, sizeof(ext_aead_context));
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("malloc failed \n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_calloc, 0);
++ hi_log_error("malloc failed \n");
++ hi_log_print_func_err(crypto_calloc, 0);
+ return HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ctx;
+}
+
-+hi_s32 ext_mbedtls_aead_destory(void *ctx)
++hi_s32 ext_mbedtls_aead_destory(hi_void *ctx)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (ctx != HI_NULL) {
+ crypto_free(ctx);
+ ctx = HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_aead_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
++hi_s32 ext_mbedtls_aead_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
+{
+ ext_aead_context *aead = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(aead == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ivlen > AES_IV_SIZE);
++ hi_log_chk_param_return(aead == HI_NULL);
++ hi_log_chk_param_return(ivlen > AES_IV_SIZE);
+
+ if (iv != HI_NULL) {
+ crypto_memcpy(aead->iv, AES_IV_SIZE, iv, ivlen);
+ aead->ivlen = ivlen;
-+ HI_LOG_DEBUG("ivlen %d\n", ivlen);
++ hi_log_debug("ivlen %d\n", ivlen);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_aead_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++hi_s32 ext_mbedtls_aead_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
-+ hi_u32 klen = 0;
++ hi_u32 klen;
+ ext_aead_context *aead = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(aead == HI_NULL);
-+ HI_LOG_CHECK_PARAM(fkey == HI_NULL);
-+ HI_LOG_CHECK_PARAM(hisi_klen == HI_NULL);
++ hi_log_chk_param_return(aead == HI_NULL);
++ hi_log_chk_param_return(fkey == HI_NULL);
++ hi_log_chk_param_return(hisi_klen == HI_NULL);
+
+ switch (*hisi_klen) {
+ case HI_CIPHER_KEY_AES_128BIT: {
@@ -213279,261 +282002,241 @@ index 0000000..7fc62ca
+ break;
+ }
+ default: {
-+ HI_LOG_ERROR("Invalid aes key len: 0x%x\n", klen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid aes key len: 0x%x\n", *hisi_klen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
-+ HI_LOG_INFO("key len %d, type %d\n", klen, hisi_klen);
++ hi_log_info("key len %d, type %d\n", klen, hisi_klen);
+
+ crypto_memcpy(aead->key, SYMC_KEY_SIZE, fkey, klen);
+ aead->klen = klen;
+ *hisi_klen = klen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_aead_set_aad(void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen)
++hi_s32 ext_mbedtls_aead_set_aad(hi_void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen)
+{
+ ext_aead_context *aead = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(aead == HI_NULL);
++ hi_log_chk_param_return(aead == HI_NULL);
+
+ aead->aad = aad;
+ aead->alen = alen;
+ aead->tlen = tlen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_aead_get_tag(void *ctx, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen)
++hi_s32 ext_mbedtls_aead_get_tag(hi_void *ctx, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen)
+{
+ ext_aead_context *aead = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(aead == HI_NULL);
-+ HI_LOG_CHECK_PARAM(*taglen < aead->tlen);
++ hi_log_chk_param_return(aead == HI_NULL);
++ hi_log_chk_param_return(*taglen < aead->tlen);
+
-+ HI_LOG_DEBUG("tag buffer len %d, tag len %d\n", *taglen, aead->tlen);
++ hi_log_debug("tag buffer len %d, tag len %d\n", *taglen, aead->tlen);
+
+ *taglen = aead->tlen;
+
+ crypto_memcpy(tag, AEAD_TAG_SIZE, aead->tag, aead->tlen);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_aead_ccm_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 last)
++static hi_s32 ext_ccm_gcm_mem_open(ext_ccm_gcm_mem *mem, symc_multi_pack *pack, compat_addr aad, hi_u32 aad_len)
+{
++ hi_s32 ret;
++
++ ret = crypto_mem_open(&mem->in, pack->in[0], pack->len[0]);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_open, ret);
++ return ret;
++ }
++
++ ret = crypto_mem_open(&mem->out, pack->out[0], pack->len[0]);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_open, ret);
++ (hi_void)crypto_mem_close(&mem->in);
++ return ret;
++ }
++
++ ret = crypto_mem_open(&mem->aad, aad, aad_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_open, ret);
++ (hi_void)crypto_mem_close(&mem->out);
++ (hi_void)crypto_mem_close(&mem->in);
++ return ret;
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 ext_ccm_gcm_mem_close(ext_ccm_gcm_mem *mem)
++{
++ hi_s32 ret;
++
++ ret = crypto_mem_close(&mem->aad);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_close, ret);
++ (hi_void)crypto_mem_close(&mem->out);
++ (hi_void)crypto_mem_close(&mem->in);
++ return ret;
++ }
++
++ ret = crypto_mem_close(&mem->out);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_close, ret);
++ (hi_void)crypto_mem_close(&mem->in);
++ return ret;
++ }
++
++ ret = crypto_mem_close(&mem->in);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_close, ret);
++ return ret;
++ }
++
++ return HI_SUCCESS;
++}
++
++hi_s32 ext_mbedtls_aead_ccm_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last)
++{
++ hi_s32 ret, ret_err;
+ ext_aead_context *aead = ctx;
+ mbedtls_ccm_context ccm;
-+ crypto_mem mem_in, mem_out, aad;
-+ hi_s32 ret = HI_FAILURE;
++ ext_ccm_gcm_mem mem;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(aead == HI_NULL);
-+ HI_LOG_CHECK_PARAM(length == HI_NULL);
-+ HI_LOG_CHECK_PARAM(pkg_num != 0x01);
++ hi_log_chk_param_return((aead == HI_NULL) || (pack == HI_NULL));
++ hi_log_chk_param_return((pack->num != 1) || (pack->len == HI_NULL));
+
-+ ret = crypto_mem_open(&mem_in, input[0], length[0]);
++ crypto_memset(&mem, sizeof(mem), 0, sizeof(mem));
++
++ ret = ext_ccm_gcm_mem_open(&mem, pack, aead->aad, aead->alen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of input failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+ return HI_ERR_CIPHER_FAILED_MEM;
-+ }
-+
-+ ret = crypto_mem_open(&mem_out, output[0], length[0]);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of output failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+ goto error1;
-+ }
-+
-+ ret = crypto_mem_open(&aad, aead->aad, aead->alen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of aad failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_FUNC_EXIT();
-+ goto error2;
++ hi_log_print_func_err(ext_ccm_gcm_mem_open, ret);
++ return ret;
+ }
+
+ mbedtls_ccm_init(&ccm);
+
-+ HI_LOG_DEBUG("aead 0x%p, klen len: %d\n", aead, aead->klen);
++ hi_log_debug("aead 0x%p, klen len: %d\n", aead, aead->klen);
+
-+ ret = mbedtls_ccm_setkey(&ccm, MBEDTLS_CIPHER_ID_AES, (hi_u8 *)aead->key,
-+ aead->klen * BITS_IN_BYTE);
++ ret = mbedtls_ccm_setkey(&ccm, MBEDTLS_CIPHER_ID_AES, (hi_u8 *)aead->key, aead->klen * BITS_IN_BYTE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_ccm_setkey, ret);
-+ goto error3;
-+ }
-+
-+ if (operation) {
-+ ret = mbedtls_ccm_auth_decrypt(&ccm, length[0],
-+ (hi_u8 *)aead->iv , aead->ivlen,
-+ crypto_mem_virt(&aad), aead->alen,
-+ crypto_mem_virt(&mem_in), crypto_mem_virt(&mem_out),
-+ (hi_u8 *)aead->tag, aead->tlen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_ccm_auth_decrypt, ret);
-+ }
-+ } else {
-+ ret = mbedtls_ccm_encrypt_and_tag(&ccm, length[0],
-+ (hi_u8 *)aead->iv , aead->ivlen,
-+ crypto_mem_virt(&aad), aead->alen,
-+ crypto_mem_virt(&mem_in), crypto_mem_virt(&mem_out),
-+ (hi_u8 *)aead->tag, aead->tlen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_ccm_encrypt_and_tag, ret);
-+ }
-+ }
-+
-+ HI_LOG_FUNC_EXIT();
-+
-+error3:
-+ mbedtls_ccm_free(&ccm);
-+ crypto_mem_close(&aad);
-+error2:
-+ crypto_mem_close(&mem_out);
-+error1:
-+ crypto_mem_close(&mem_in);
-+
-+ return ret;
-+}
-+
-+hi_s32 ext_mbedtls_aead_gcm_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 last)
-+{
-+ ext_aead_context *aead = ctx;
-+ mbedtls_gcm_context *gcm = HI_NULL;
-+ crypto_mem mem_in, mem_out, aad;
-+ hi_s32 ret = HI_FAILURE;
-+
-+ HI_LOG_FUNC_ENTER();
-+
-+ HI_LOG_CHECK_PARAM(aead == HI_NULL);
-+ HI_LOG_CHECK_PARAM(length == HI_NULL);
-+ HI_LOG_CHECK_PARAM(pkg_num != 0x01);
-+
-+ crypto_memset(&aad, sizeof(aad), 0, sizeof(aad));
-+ crypto_memset(&mem_in, sizeof(mem_in), 0, sizeof(mem_in));
-+ crypto_memset(&mem_out, sizeof(mem_out), 0, sizeof(mem_out));
-+
-+ gcm = crypto_calloc(1, sizeof(mbedtls_gcm_context));
-+ if (gcm == HI_NULL) {
-+ HI_LOG_ERROR("crypto calloc for mbedtls gcm context failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_FUNC_ERR(crypto_calloc, ret);
-+ return ret;
-+ }
-+
-+ ret = crypto_mem_open(&mem_in, input[0], length[0]);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of input failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_open, ret);
++ hi_log_print_func_err(mbedtls_ccm_setkey, ret);
+ goto error0;
+ }
+
-+ ret = crypto_mem_open(&mem_out, output[0], length[0]);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of output failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_open, ret);
-+ goto error1;
++ if (operation) {
++ ret = mbedtls_ccm_auth_decrypt(&ccm, pack->len[0], (hi_u8 *)aead->iv, aead->ivlen, crypto_mem_virt(&mem.aad),
++ aead->alen, crypto_mem_virt(&mem.in), crypto_mem_virt(&mem.out), (hi_u8 *)aead->tag, aead->tlen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_ccm_auth_decrypt, ret);
++ }
++ } else {
++ ret = mbedtls_ccm_encrypt_and_tag(&ccm, pack->len[0], (hi_u8 *)aead->iv, aead->ivlen, crypto_mem_virt(&mem.aad),
++ aead->alen, crypto_mem_virt(&mem.in), crypto_mem_virt(&mem.out), (hi_u8 *)aead->tag, aead->tlen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_ccm_encrypt_and_tag, ret);
++ }
+ }
+
-+ ret = crypto_mem_open(&aad, aead->aad, aead->alen);
++ hi_log_func_exit();
++
++error0:
++ mbedtls_ccm_free(&ccm);
++ ret_err = ext_ccm_gcm_mem_close(&mem);
++ if (ret_err != HI_SUCCESS) {
++ hi_log_print_func_err(ext_ccm_gcm_mem_close, ret_err);
++ }
++ return ret;
++}
++
++hi_s32 ext_mbedtls_aead_gcm_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last)
++{
++ hi_s32 ret, ret_err;
++ ext_aead_context *aead = ctx;
++ mbedtls_gcm_context *gcm = HI_NULL;
++ ext_ccm_gcm_mem mem;
++
++ hi_log_func_enter();
++
++ hi_log_chk_param_return((aead == HI_NULL) || (pack == HI_NULL));
++ hi_log_chk_param_return((pack->num != 1) || (pack->len == HI_NULL));
++
++ crypto_memset(&mem, sizeof(mem), 0, sizeof(mem));
++
++ gcm = crypto_calloc(1, sizeof(mbedtls_gcm_context));
++ if (gcm == HI_NULL) {
++ hi_log_print_func_err(crypto_calloc, HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
++ }
++
++ ret = ext_ccm_gcm_mem_open(&mem, pack, aead->aad, aead->alen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of aad failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_open, ret);
-+ goto error2;
++ hi_log_print_func_err(ext_ccm_gcm_mem_open, ret);
++ goto error0;
+ }
+
+ mbedtls_gcm_init(gcm);
+
-+ ret = mbedtls_gcm_setkey(gcm, MBEDTLS_CIPHER_ID_AES, (hi_u8 *)aead->key,
-+ aead->klen * BITS_IN_BYTE);
++ ret = mbedtls_gcm_setkey(gcm, MBEDTLS_CIPHER_ID_AES, (hi_u8 *)aead->key, aead->klen * BITS_IN_BYTE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_gcm_setkey, ret);
-+ goto error3;
++ hi_log_print_func_err(mbedtls_gcm_setkey, ret);
++ goto error1;
+ }
+
-+ ret = mbedtls_gcm_starts(gcm, operation ? MBEDTLS_DECRYPT : MBEDTLS_ENCRYPT,
-+ (hi_u8 *)aead->iv , aead->ivlen,
-+ crypto_mem_virt(&aad), aead->alen);
++ ret = mbedtls_gcm_starts(gcm, operation ? MBEDTLS_DECRYPT : MBEDTLS_ENCRYPT, (hi_u8 *)aead->iv, aead->ivlen,
++ crypto_mem_virt(&mem.aad), aead->alen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_gcm_starts, ret);
-+ goto error3;
++ hi_log_print_func_err(mbedtls_gcm_starts, ret);
++ goto error1;
+ }
+
-+ ret = mbedtls_gcm_update(gcm, length[0], crypto_mem_virt(&mem_in),
-+ crypto_mem_virt(&mem_out));
++ ret = mbedtls_gcm_update(gcm, pack->len[0], crypto_mem_virt(&mem.in), crypto_mem_virt(&mem.out));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_gcm_update, ret);
-+ goto error3;
++ hi_log_print_func_err(mbedtls_gcm_update, ret);
++ goto error1;
+ }
+
+ ret = mbedtls_gcm_finish(gcm, (hi_u8 *)aead->tag, aead->tlen);
+
-+error3:
-+ mbedtls_gcm_free(gcm);
-+ crypto_mem_close(&aad);
-+error2:
-+ crypto_mem_close(&mem_out);
+error1:
-+ crypto_mem_close(&mem_in);
++ mbedtls_gcm_free(gcm);
++ ret_err = ext_ccm_gcm_mem_close(&mem);
++ if (ret_err != HI_SUCCESS) {
++ hi_log_print_func_err(ext_ccm_gcm_mem_close, ret_err);
++ }
++
+error0:
+ crypto_free(gcm);
+ gcm = HI_NULL;
-+
+ return ret;
+}
+
-+#endif // End of SOFT_AES_CCM_GCM_SUPPORT
++#endif /* End of SOFT_AES_CCM_GCM_SUPPORT */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_hash.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_hash.c
new file mode 100644
-index 0000000..34c8b96
+index 0000000..7efc333
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_hash.c
-@@ -0,0 +1,157 @@
+@@ -0,0 +1,162 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for ext hash.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
@@ -213546,28 +282249,28 @@ index 0000000..34c8b96
+ || defined(SOFT_SHA256_SUPPORT) \
+ || defined(SOFT_SHA512_SUPPORT)
+
-+void *mbedtls_hash_create(hash_mode mode)
++hi_void *mbedtls_hash_create(hash_mode mode)
+{
+ mbedtls_md_type_t md_type;
+ const mbedtls_md_info_t *info;
+ mbedtls_md_context_t *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* convert to mebdtls type */
+ md_type = MBEDTLS_MD_SHA1 + (mode - HASH_MODE_SHA1);
+
+ info = mbedtls_md_info_from_type(md_type);
+ if (info == HI_NULL) {
-+ HI_LOG_ERROR("error, invalid hash mode %d\n", mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
++ hi_log_error("error, invalid hash mode %d\n", mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
+ return HI_NULL;
+ }
+
+ ctx = crypto_malloc(sizeof(mbedtls_md_context_t));
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("malloc hash context buffer failed!");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_error("malloc hash context buffer failed!");
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
+ return HI_NULL;
+ }
+ crypto_memset(ctx, sizeof(mbedtls_md_context_t), 0, sizeof(mbedtls_md_context_t));
@@ -213576,127 +282279,132 @@ index 0000000..34c8b96
+ mbedtls_md_setup(ctx, info, HI_FALSE);
+ mbedtls_md_starts(ctx);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ctx;
+}
+
-+hi_s32 mbedtls_hash_update(void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src)
++static hi_s32 ext_hash_update_from_user(mbedtls_md_context_t *md, hi_u8 *chunk, hi_u32 chunk_len)
+{
++ hi_s32 ret;
+ hi_u8 *ptr = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
-+ mbedtls_md_context_t *md = ctx;
-+ hi_u32 offset = 0, length = 0;
++ hi_u32 len;
++ hi_u32 offset = 0;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
-+
-+ if (chunkLen == 0x00) {
-+ return HI_SUCCESS;
++ ptr = crypto_calloc(HASH_MAX_BUFFER_SIZE);
++ if (ptr == HI_NULL) {
++ hi_log_print_func_err(crypto_malloc, HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ if (src == HASH_CHUNCK_SRC_USER) {
-+ ptr = crypto_malloc(HASH_MAX_BUFFER_SIZE);
-+ if (ptr == HI_NULL) {
-+ HI_LOG_ERROR("malloc hash chunk buffer failed, chunkLen 0x%x\n!", chunkLen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
++ while (offset < chunk_len) {
++ len = chunk_len - offset;
++ if (len > HASH_MAX_BUFFER_SIZE) {
++ len = HASH_MAX_BUFFER_SIZE;
++ }
++ ret = crypto_copy_from_user(ptr, chunk + offset, len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_copy_from_user, ret);
++ crypto_free(ptr);
++ ptr = HI_NULL;
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
-+ crypto_memset(ptr, HASH_MAX_BUFFER_SIZE, 0, HASH_MAX_BUFFER_SIZE);
-+
-+ while (offset < chunkLen) {
-+ length = chunkLen - offset;
-+ if (length > HASH_MAX_BUFFER_SIZE) {
-+ length = HASH_MAX_BUFFER_SIZE;
-+ }
-+ if (crypto_copy_from_user(ptr, chunk + offset, length)) {
-+ HI_LOG_ERROR("copy hash chunk from user failed!");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ goto exit;
-+ }
-+ ret = mbedtls_md_update(md, ptr, length);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_md_update, ret);
-+ break;
-+ }
-+ crypto_msleep(1);
-+ offset += length;
-+ }
-+ } else {
-+ ret = mbedtls_md_update(md, chunk, chunkLen);
++ ret = mbedtls_md_update(md, ptr, len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(mbedtls_md_update, ret);
++ hi_log_print_func_err(mbedtls_md_update, ret);
++ crypto_free(ptr);
++ ptr = HI_NULL;
++ return ret;
+ }
++ crypto_msleep(1);
++ offset += len;
+ }
+
-+exit:
+ if (ptr != HI_NULL) {
+ crypto_free(ptr);
+ ptr = HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return ret;
++ return HI_SUCCESS;
+}
+
-+hi_s32 mbedtls_hash_finish(void *ctx, void *hash, hi_u32 *hashlen)
++hi_s32 mbedtls_hash_update(hi_void *ctx, hi_u8 *chunk, hi_u32 chunk_len, hash_chunk_src src)
++{
++ hi_u8 *ptr = HI_NULL;
++ hi_s32 ret;
++ mbedtls_md_context_t *md = ctx;
++
++ hi_log_func_enter();
++
++ hi_log_chk_param_return(ctx == HI_NULL);
++
++ if (chunk_len == 0x00) {
++ return HI_SUCCESS;
++ }
++
++ if (src == HASH_CHUNCK_SRC_USER) {
++ ret = ext_hash_update_from_user(md, chunk, chunk_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_md_update, ret);
++ return ret;
++ }
++ } else {
++ ret = mbedtls_md_update(md, chunk, chunk_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_md_update, ret);
++ return ret;
++ }
++ }
++
++ hi_log_func_exit();
++ return HI_SUCCESS;
++}
++
++hi_s32 mbedtls_hash_finish(hi_void *ctx, hi_void *hash, hi_u32 hash_buf_len, hi_u32 *hashlen)
+{
+ mbedtls_md_context_t *md = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
++ hi_log_chk_param_return(hash_buf_len == 0);
+
+ mbedtls_md_finish(md, hash);
+
+ *hashlen = mbedtls_md_get_size(md->md_info);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 mbedtls_hash_destory(void *ctx)
++hi_s32 mbedtls_hash_destory(hi_void *ctx)
+{
+ mbedtls_md_context_t *md = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
+
+ mbedtls_md_free(md);
+ crypto_free(ctx);
+ ctx = HI_NULL;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+#endif // End of SOFT_AES_CCM_GCM_SUPPORT
++#endif /* End of SOFT_AES_CCM_GCM_SUPPORT */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_sm3.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_sm3.c
new file mode 100644
-index 0000000..2a643ed
+index 0000000..7f16530
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_sm3.c
-@@ -0,0 +1,412 @@
+@@ -0,0 +1,381 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for cipher adapt to sm3.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
@@ -213704,29 +282412,26 @@ index 0000000..2a643ed
+
+#ifdef SOFT_SM3_SUPPORT
+
-+/*************************** Internal Structure Definition ****************************/
-+/** \addtogroup sm3 */
-+/** @{*/ /** <!-- [sm3]*/
-+
-+hi_u32 ROTATELEFT(hi_u32 x, hi_u32 n)
++/* ************************** Internal Structure Definition For SM3 *************************** */
++hi_u32 rotate_left(hi_u32 x, hi_u32 n)
+{
-+ n %= 32;
++ n %= SHIFT_32BITS;
+
+ if (n == 0) {
+ return x;
+ }
+
-+ return x << n | x >> (32 - n);
++ return (x << n) | (x >> (SHIFT_32BITS - n));
+}
+
-+#define P0(x) ((x) ^ ROTATELEFT((x),9) ^ ROTATELEFT((x),17))
-+#define P1(x) ((x) ^ ROTATELEFT((x),15) ^ ROTATELEFT((x),23))
++#define p0(x) ((x) ^ rotate_left((x), SHIFT_9BITS) ^ rotate_left((x), SHIFT_17BITS))
++#define p1(x) ((x) ^ rotate_left((x), SHIFT_15BITS) ^ rotate_left((x), SHIFT_23BITS))
+
-+#define FF0(x,y,z) ((x) ^ (y) ^ (z))
-+#define FF1(x,y,z) (((x) & (y)) | ((x) & (z)) | ((y) & (z)))
++#define ff0(x, y, z) ((x) ^ (y) ^ (z))
++#define ff1(x, y, z) (((x) & (y)) | ((x) & (z)) | ((y) & (z)))
+
-+#define GG0(x,y,z) ((x) ^ (y) ^ (z))
-+#define GG1(x,y,z) (((x) & (y)) | ((~(x)) & (z)))
++#define gg0(x, y, z) ((x) ^ (y) ^ (z))
++#define gg1(x, y, z) (((x) & (y)) | ((~(x)) & (z)))
+
+#define SM3_BLOCK_SIZE 64
+#define SM3_W_SIZE ((SM3_BLOCK_SIZE) + (WORD_WIDTH))
@@ -213735,7 +282440,7 @@ index 0000000..2a643ed
+#define SM3_PAD_LEN_SIZE 8
+#define SM3_BYTE_MSB 0x80
+
-+/* SM3, the initial hash value, H(0)*/
++/* SM3, the initial hash value, H(0). */
+#define SM3_H0 0x7380166F
+#define SM3_H1 0x4914B2B9
+#define SM3_H2 0x172442D7
@@ -213745,48 +282450,45 @@ index 0000000..2a643ed
+#define SM3_H6 0xE38DEE4D
+#define SM3_H7 0xB0FB0E4E
+
-+#define HASH_MAX_BUFFER_SIZE 0x10000 /* 64K */
++/* 64K */
++#define HASH_MAX_BUFFER_SIZE 0x10000
+
-+/**
-+ * \brief aes ccm context structure
-+ */
++/* brief aes ccm context structure */
+typedef struct {
+ hi_u32 state[SM3_RESULT_SIZE_IN_WORD];
+ hi_u8 tail[SM3_BLOCK_SIZE];
+ hi_u32 tail_len;
+ hi_u32 total;
-+}
-+ext_sm3_context;
++} ext_sm3_context;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup sm3 */
-+/** @{*/ /** <!-- [sm3]*/
-+
-+hi_s32 sm3_compress(hi_u32 digest[SM3_RESULT_SIZE_IN_WORD], const hi_u8 block[SM3_BLOCK_SIZE])
++/* ****************************** API Code for sm3 **************************** */
++hi_s32 sm3_compress(hi_u32 digest[SM3_RESULT_SIZE_IN_WORD], const hi_u8 block[SM3_BLOCK_SIZE], hi_u32 block_len)
+{
+ hi_s32 j;
+ hi_u32 *W = HI_NULL;
+ hi_u32 *W1 = HI_NULL;
+ hi_u32 *T = HI_NULL;
+ const hi_u32 *local_block = (const hi_u32 *)block;
-+ hi_u32 A = digest[0];
-+ hi_u32 B = digest[1];
-+ hi_u32 C = digest[2];
-+ hi_u32 D = digest[3];
-+ hi_u32 E = digest[4];
-+ hi_u32 F = digest[5];
-+ hi_u32 G = digest[6];
-+ hi_u32 H = digest[7];
++ hi_u32 A = digest[WORD_IDX_0];
++ hi_u32 B = digest[WORD_IDX_1];
++ hi_u32 C = digest[WORD_IDX_2];
++ hi_u32 D = digest[WORD_IDX_3];
++ hi_u32 E = digest[WORD_IDX_4];
++ hi_u32 F = digest[WORD_IDX_5];
++ hi_u32 G = digest[WORD_IDX_6];
++ hi_u32 H = digest[WORD_IDX_7];
+ hi_u32 SS1, SS2, TT1, TT2;
+ hi_u32 *buf = HI_NULL;
-+ hi_u32 buf_size = 0;
++ hi_u32 buf_size;
++
++ if (block_len != SM3_BLOCK_SIZE) {
++ return HI_ERR_CIPHER_INVALID_LENGTH;
++ }
+
+ buf_size = sizeof(hi_u32) * (SM3_W_SIZE + SM3_BLOCK_SIZE + SM3_BLOCK_SIZE);
+ buf = (hi_u32 *)crypto_malloc(buf_size);
+ if (buf == HI_NULL) {
-+ HI_LOG_ERROR("sm3 compress crypto malloc buff failed!\n");
++ hi_log_error("sm3 compress crypto malloc buff failed!\n");
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+ crypto_memset(buf, buf_size, 0, buf_size);
@@ -213794,58 +282496,58 @@ index 0000000..2a643ed
+ W1 = buf + SM3_W_SIZE;
+ T = buf + SM3_W_SIZE + SM3_BLOCK_SIZE;
+
-+ for (j = 0; j < 16; j++) {
-+ W[j] = CPU_TO_BE32(local_block[j]);
++ for (j = 0; j < SM3_BLOCK_SIZE / WORD_WIDTH; j++) {
++ W[j] = crypto_cpu_to_be32(local_block[j]);
+ }
-+ for (j = 16; j < SM3_W_SIZE; j++) {
-+ W[j] = P1(W[j - 16] ^ W[j - 9] ^ ROTATELEFT(W[j - 3], 15)) ^ ROTATELEFT(W[j - 13], 7) ^ W[j - 6];
++ for (j = SM3_BLOCK_SIZE / WORD_WIDTH; j < SM3_W_SIZE; j++) {
++ W[j] = p1(W[j - 16] ^ W[j - 9] ^ \ /* soft sm3 alg:offset 16, 9. */
++ rotate_left(W[j - 3], 15)) ^ \ /* soft sm3 alg:offset 3, and rotate left 15. */
++ rotate_left(W[j - 13], 7) ^ W[j - 6]; /* soft sm3 alg:offset 13, 6 and rotate left 7. */
+ }
+ for (j = 0; j < SM3_BLOCK_SIZE; j++) {
-+ W1[j] = W[j] ^ W[j + 4];
++ W1[j] = W[j] ^ W[j + 4]; /* soft sm3 alg:offset 4. */
+ }
+
-+ for (j = 0; j < 16; j++) {
-+
-+ T[j] = 0x79CC4519;
-+ SS1 = ROTATELEFT((ROTATELEFT(A, 12) + E + ROTATELEFT(T[j], j)), 7);
-+ SS2 = SS1 ^ ROTATELEFT(A, 12);
-+ TT1 = FF0(A, B, C) + D + SS2 + W1[j];
-+ TT2 = GG0(E, F, G) + H + SS1 + W[j];
++ for (j = 0; j < SM3_BLOCK_SIZE / WORD_WIDTH; j++) {
++ T[j] = 0x79CC4519; /* soft sm3 alg: T init 0x79CC4519. */
++ SS1 = rotate_left((rotate_left(A, 12) + E + rotate_left(T[j], j)), 7); /* soft sm3 alg:rotate left 12, 7. */
++ SS2 = SS1 ^ rotate_left(A, 12); /* soft sm3 alg:rotate left 12. */
++ TT1 = ff0(A, B, C) + D + SS2 + W1[j];
++ TT2 = gg0(E, F, G) + H + SS1 + W[j];
+ D = C;
-+ C = ROTATELEFT(B, 9);
++ C = rotate_left(B, 9); /* soft sm3 alg:rotate left 9. */
+ B = A;
+ A = TT1;
+ H = G;
-+ G = ROTATELEFT(F, 19);
++ G = rotate_left(F, 19); /* soft sm3 alg:rotate left 19. */
+ F = E;
-+ E = P0(TT2);
++ E = p0(TT2);
+ }
+
-+ for (j = 16; j < SM3_BLOCK_SIZE; j++) {
-+
-+ T[j] = 0x7A879D8A;
-+ SS1 = ROTATELEFT((ROTATELEFT(A, 12) + E + ROTATELEFT(T[j], j)), 7);
-+ SS2 = SS1 ^ ROTATELEFT(A, 12);
-+ TT1 = FF1(A, B, C) + D + SS2 + W1[j];
-+ TT2 = GG1(E, F, G) + H + SS1 + W[j];
++ for (j = SM3_BLOCK_SIZE / WORD_WIDTH; j < SM3_BLOCK_SIZE; j++) {
++ T[j] = 0x7A879D8A; /* soft sm3 alg: T init 0x7A879D8A. */
++ SS1 = rotate_left((rotate_left(A, 12) + E + rotate_left(T[j], j)), 7); /* soft sm3 alg:rotate left 12, 7. */
++ SS2 = SS1 ^ rotate_left(A, 12); /* soft sm3 alg:rotate left 12. */
++ TT1 = ff1(A, B, C) + D + SS2 + W1[j];
++ TT2 = gg1(E, F, G) + H + SS1 + W[j];
+ D = C;
-+ C = ROTATELEFT(B, 9);
++ C = rotate_left(B, 9); /* soft sm3 alg:rotate left 9. */
+ B = A;
+ A = TT1;
+ H = G;
-+ G = ROTATELEFT(F, 19);
++ G = rotate_left(F, 19); /* soft sm3 alg:rotate left 19. */
+ F = E;
-+ E = P0(TT2);
++ E = p0(TT2);
+ }
+
-+ digest[0] ^= A;
-+ digest[1] ^= B;
-+ digest[2] ^= C;
-+ digest[3] ^= D;
-+ digest[4] ^= E;
-+ digest[5] ^= F;
-+ digest[6] ^= G;
-+ digest[7] ^= H;
++ digest[WORD_IDX_0] ^= A;
++ digest[WORD_IDX_1] ^= B;
++ digest[WORD_IDX_2] ^= C;
++ digest[WORD_IDX_3] ^= D;
++ digest[WORD_IDX_4] ^= E;
++ digest[WORD_IDX_5] ^= F;
++ digest[WORD_IDX_6] ^= G;
++ digest[WORD_IDX_7] ^= H;
+
+ if (buf != HI_NULL) {
+ crypto_free(buf);
@@ -213855,20 +282557,20 @@ index 0000000..2a643ed
+ return HI_SUCCESS;
+}
+
-+static void sm3_init(ext_sm3_context *ctx)
++static hi_void sm3_init(ext_sm3_context *ctx)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ctx->state[0] = SM3_H0;
-+ ctx->state[1] = SM3_H1;
-+ ctx->state[2] = SM3_H2;
-+ ctx->state[3] = SM3_H3;
-+ ctx->state[4] = SM3_H4;
-+ ctx->state[5] = SM3_H5;
-+ ctx->state[6] = SM3_H6;
-+ ctx->state[7] = SM3_H7;
++ ctx->state[WORD_IDX_0] = SM3_H0;
++ ctx->state[WORD_IDX_1] = SM3_H1;
++ ctx->state[WORD_IDX_2] = SM3_H2;
++ ctx->state[WORD_IDX_3] = SM3_H3;
++ ctx->state[WORD_IDX_4] = SM3_H4;
++ ctx->state[WORD_IDX_5] = SM3_H5;
++ ctx->state[WORD_IDX_6] = SM3_H6;
++ ctx->state[WORD_IDX_7] = SM3_H7;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
@@ -213876,9 +282578,9 @@ index 0000000..2a643ed
+static hi_s32 sm3_update(ext_sm3_context *ctx, const hi_u8 *data, hi_u32 data_len)
+{
+ hi_u32 left = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ctx->total += data_len;
+
@@ -213890,9 +282592,9 @@ index 0000000..2a643ed
+ return HI_SUCCESS;
+ } else {
+ crypto_memcpy(ctx->tail + ctx->tail_len, left, data, left);
-+ ret = sm3_compress(ctx->state, ctx->tail);
++ ret = sm3_compress(ctx->state, ctx->tail, sizeof(ctx->tail));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(sm3_compress, ret);
++ hi_log_print_func_err(sm3_compress, ret);
+ return ret;
+ }
+
@@ -213902,9 +282604,9 @@ index 0000000..2a643ed
+ }
+
+ while (data_len >= SM3_BLOCK_SIZE) {
-+ ret = sm3_compress(ctx->state, data);
++ ret = sm3_compress(ctx->state, data, SM3_BLOCK_SIZE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(sm3_compress, ret);
++ hi_log_print_func_err(sm3_compress, ret);
+ return ret;
+ }
+
@@ -213917,204 +282619,179 @@ index 0000000..2a643ed
+ crypto_memcpy(ctx->tail, SM3_BLOCK_SIZE, data, data_len);
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return HI_SUCCESS;
+}
+
-+static hi_s32 sm3_final(ext_sm3_context *ctx, hi_u8 *digest)
++static hi_s32 sm3_final(ext_sm3_context *ctx, hi_u8 *digest, hi_u32 digest_len)
+{
+ hi_s32 i = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
++ hi_u32 idx = 0;
+ hi_u32 hash[SM3_RESULT_SIZE_IN_WORD] = {0};
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
++ hi_log_chk_param_return(digest_len < SM3_BLOCK_SIZE);
+
+ ctx->tail[ctx->tail_len] = SM3_BYTE_MSB;
++ idx++;
+
+ /* a block is enough */
+ if (ctx->tail_len + SM3_PAD_MIN_SIZE <= SM3_BLOCK_SIZE) {
-+ crypto_memset(ctx->tail + ctx->tail_len + 1, SM3_BLOCK_SIZE - ctx->tail_len - 1, 0,
-+ SM3_BLOCK_SIZE - ctx->tail_len - 1);
++ crypto_memset(ctx->tail + ctx->tail_len + idx, SM3_BLOCK_SIZE - ctx->tail_len - idx, 0,
++ SM3_BLOCK_SIZE - ctx->tail_len - idx);
+ } else {
+ /* 2 block is request */
-+ crypto_memset(ctx->tail + ctx->tail_len + 1, SM3_BLOCK_SIZE - ctx->tail_len - 1,
-+ 0, SM3_BLOCK_SIZE - ctx->tail_len - 1);
-+ ret = sm3_compress(ctx->state, ctx->tail);
++ crypto_memset(ctx->tail + ctx->tail_len + idx, SM3_BLOCK_SIZE - ctx->tail_len - idx, 0,
++ SM3_BLOCK_SIZE - ctx->tail_len - idx);
++ ret = sm3_compress(ctx->state, ctx->tail, sizeof(ctx->tail));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(sm3_compress, ret);
++ hi_log_print_func_err(sm3_compress, ret);
+ return ret;
+ }
+ crypto_memset(ctx->tail, SM3_BLOCK_SIZE, 0, SM3_BLOCK_SIZE);
+ }
+
+ /* write 8 bytes fix data length * 8 */
-+ ctx->tail[SM3_BLOCK_SIZE - 5] = (hi_u8)((ctx->total >> 29) & 0x07);
-+ ctx->tail[SM3_BLOCK_SIZE - 4] = (hi_u8)((ctx->total >> 21) & 0xff);
-+ ctx->tail[SM3_BLOCK_SIZE - 3] = (hi_u8)((ctx->total >> 13) & 0xff);
-+ ctx->tail[SM3_BLOCK_SIZE - 2] = (hi_u8)((ctx->total >> 5) & 0xff);
-+ ctx->tail[SM3_BLOCK_SIZE - 1] = (hi_u8)((ctx->total << 3) & 0xff);
++ ctx->tail[SM3_BLOCK_SIZE - WORD_IDX_5] = (hi_u8)((ctx->total >> SHIFT_29BITS) & MAX_LOW_3BITS);
++ ctx->tail[SM3_BLOCK_SIZE - WORD_IDX_4] = (hi_u8)((ctx->total >> SHIFT_21BITS) & MAX_LOW_8BITS);
++ ctx->tail[SM3_BLOCK_SIZE - WORD_IDX_3] = (hi_u8)((ctx->total >> SHIFT_13BITS) & MAX_LOW_8BITS);
++ ctx->tail[SM3_BLOCK_SIZE - WORD_IDX_2] = (hi_u8)((ctx->total >> SHIFT_5BITS) & MAX_LOW_8BITS);
++ ctx->tail[SM3_BLOCK_SIZE - WORD_IDX_1] = (hi_u8)((ctx->total << SHIFT_3BITS) & MAX_LOW_8BITS);
+
-+ ret = sm3_compress(ctx->state, ctx->tail);
++ ret = sm3_compress(ctx->state, ctx->tail, sizeof(ctx->tail));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(sm3_compress, ret);
++ hi_log_print_func_err(sm3_compress, ret);
+ return ret;
+ }
+
+ for (i = 0; i < SM3_RESULT_SIZE_IN_WORD; i++) {
-+ hash[i] = CPU_TO_BE32(ctx->state[i]);
++ hash[i] = crypto_cpu_to_be32(ctx->state[i]);
+ }
+
-+ crypto_memcpy(digest, SM3_RESULT_SIZE, hash, SM3_RESULT_SIZE);
++ crypto_memcpy(digest, digest_len, hash, SM3_RESULT_SIZE);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return HI_SUCCESS;
+}
+
-+void *ext_sm3_create(hash_mode mode)
++hi_void *ext_sm3_create(hash_mode mode)
+{
+ ext_sm3_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ctx = crypto_malloc(sizeof(ext_sm3_context));
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("malloc hash context buffer failed!");
++ hi_log_error("malloc hash context buffer failed!");
+ return HI_NULL;
+ }
+ crypto_memset(ctx, sizeof(ext_sm3_context), 0, sizeof(ext_sm3_context));
+
+ sm3_init(ctx);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ctx;
+}
+
-+hi_s32 ext_sm3_update(void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src)
++hi_s32 ext_sm3_update(hi_void *ctx, hi_u8 *chunk, hi_u32 chunk_len, hash_chunk_src src)
+{
+ hi_u8 *ptr = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u32 offset = 0, length = 0;
++ hi_s32 ret;
++ hi_u32 offset = 0;
++ hi_u32 length;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
+
-+ if (chunkLen == 0x00) {
++ if (chunk_len == 0x00) {
+ return HI_SUCCESS;
+ }
+
+ if (src == HASH_CHUNCK_SRC_USER) {
-+ ptr = crypto_malloc(HASH_MAX_BUFFER_SIZE);
-+ if (HI_NULL == ptr) {
-+ HI_LOG_ERROR("malloc hash chunk buffer failed!");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
++ ptr = crypto_calloc(HASH_MAX_BUFFER_SIZE);
++ if (ptr == HI_NULL) {
++ hi_log_print_func_err(crypto_calloc, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ while (offset < chunkLen) {
-+ length = chunkLen - offset;
++ while (offset < chunk_len) {
++ length = chunk_len - offset;
+ if (length > HASH_MAX_BUFFER_SIZE) {
+ length = HASH_MAX_BUFFER_SIZE;
+ }
-+ ret = crypto_copy_from_user(ptr, chunk + offset, length);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("copy hash chunk from user failed!");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+ goto exit;
-+ }
-+ ret = sm3_update(ctx, ptr, length);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(sm3_update, ret);
-+ goto exit;
-+ }
+
++ crypto_chk_err_exit(crypto_copy_from_user(ptr, chunk + offset, length));
++ crypto_chk_err_exit(sm3_update(ctx, ptr, length));
+ crypto_msleep(1);
+ offset += length;
+ }
+ } else {
+ if (chunk == HI_NULL) {
-+ HI_LOG_ERROR("Invalid point,chunk is null!\n");
++ hi_log_error("Invalid point, chunk is null!\n");
+ ret = HI_ERR_CIPHER_INVALID_POINT;
-+ goto exit;
++ goto exit__;
+ }
-+ ret = sm3_update(ctx, chunk, chunkLen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(sm3_update, ret);
-+ goto exit;
-+ }
-+
++ crypto_chk_err_exit(sm3_update(ctx, chunk, chunk_len));
+ ret = HI_SUCCESS;
+ }
+
-+exit:
++exit__:
+ if (ptr != HI_NULL) {
+ crypto_free(ptr);
+ ptr = HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
-+
++ hi_log_func_exit();
+ return ret;
+}
+
-+hi_s32 ext_sm3_finish(void *ctx, void *hash, hi_u32 *hashlen)
++hi_s32 ext_sm3_finish(hi_void *ctx, hi_void *hash, hi_u32 hash_buf_len, hi_u32 *hashlen)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ HI_LOG_FUNC_ENTER();
++ hi_s32 ret;
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
+
-+ ret = sm3_final(ctx, hash);
++ ret = sm3_final(ctx, hash, hash_buf_len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(sm3_final, ret);
++ hi_log_print_func_err(sm3_final, ret);
+ return ret;
+ }
+ *hashlen = SM3_RESULT_SIZE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_sm3_destory(void *ctx)
++hi_s32 ext_sm3_destory(hi_void *ctx)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
++ hi_log_chk_param_return(ctx == HI_NULL);
+
+ crypto_free(ctx);
+ ctx = HI_NULL;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
-+
+#endif
-+/** @}*/ /** <!-- ==== API Code end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_sm4.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_sm4.c
new file mode 100644
-index 0000000..d55c255
+index 0000000..4ec73c2
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_sm4.c
-@@ -0,0 +1,562 @@
+@@ -0,0 +1,548 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for ext sm4.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
@@ -214122,15 +282799,14 @@ index 0000000..d55c255
+
+#ifdef SOFT_SM4_SUPPORT
+
-+/************************ Internal Structure Definition **********************/
-+/** \addtogroup sm3 */
-+/** @{*/ /** <!-- [sm3]*/
++/* *********************** Internal Structure Definition ********************* */
++#define SM4_BLOCK_SIZE 16
+
-+static const hi_u32 FK[4] = {
++static const hi_u32 g_fk[SM4_BLOCK_SIZE / WORD_WIDTH] = {
+ 0xa3b1bac6, 0x56aa3350, 0x677d9197, 0xb27022dc
+};
+
-+static const hi_u32 CK[] = {
++static const hi_u32 g_ck[] = {
+ 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
+ 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
+ 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
@@ -214141,7 +282817,7 @@ index 0000000..d55c255
+ 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
+};
+
-+static const hi_u32 Sbox[16][16] = {
++static const hi_u32 g_sbox[16][16] = { /* Two-dimensional array 16, 16. */
+ {0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05},
+ {0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3, 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99},
+ {0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a, 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62},
@@ -214160,99 +282836,96 @@ index 0000000..d55c255
+ {0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20, 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48}
+};
+
-+#define GETU32(pt) (((hi_u32)(pt)[0] <<24) ^ ((hi_u32)(pt)[1] << 16) ^ ((hi_u32)(pt)[2] << 8) ^ ((hi_u32)(pt)[3]))
-+#define PUTU32(ct, st) {(ct)[0] = (hi_u8)((st) >> 24); (ct)[1] = (hi_u8)((st) >> 16); (ct)[2] = (hi_u8)((st) >> 8); (ct)[3] = (hi_u8)(st);}
++#define getu32(pt) (((hi_u32)(pt)[0] << 24) ^ ((hi_u32)(pt)[1] << 16) ^ ((hi_u32)(pt)[2] << 8) ^ ((hi_u32)(pt)[3]))
++#define putu32(ct, st) {(ct)[0] = (hi_u8)((st) >> 24); (ct)[1] = (hi_u8)((st) >> 16); (ct)[2] = (hi_u8)((st) >> 8); \
++ (ct)[3] = (hi_u8)(st);}
+
-+#define SM4_BLOCK_SIZE 16
-+#define KEY_EXT 0
-+#define CIPHER 1
-+
-+typedef struct tagSM1_KEY_S {
-+ hi_u32 rd_key[36];
++#define KEY_EXT 0
++#define CIPHER 1
++#define SM4_RD_KEY_LEN 32
++#define SM4_RD_KEY_BUF_LEN 36
++typedef struct {
++ hi_u32 rd_key[SM4_RD_KEY_BUF_LEN];
+} sm4_key;
+
+typedef union {
-+ hi_u32 i; /* i = {c[3], c[2], c[1], c[0]} */
-+ hi_u8 c[4];
-+} IS4;
++ hi_u32 i; /* descript: i = {c[3], c[2], c[1], c[0]} */
++ hi_u8 c[WORD_WIDTH];
++} is4;
+
+typedef struct {
-+ hi_u8 key[SM4_KEY_SIZE]; /*!< sm4 even round keys, default */
-+ hi_u32 klen; /*!< symc key length */
++ hi_u8 key[SM4_KEY_SIZE]; /* sm4 even round keys, default */
++ hi_u32 klen; /* symc key length */
+ hi_u8 iv[AES_IV_SIZE];
+ symc_mode mode;
-+}ext_sm4_context;
++} ext_sm4_context;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup sm4 */
-+/** @{*/ /** <!-- [sm4]*/
++/* linearity replace: left shift left, right shift right, max for residual. */
++#define linearity_replace(tmp, left, right, max) (((tmp) << (left)) + (((tmp) >> (right)) & (max)))
+
+/* Sbox */
-+hi_u32 Mix_R(const hi_u32 data_in, const int type)
++hi_u32 mix_r(const hi_u32 data_in, const hi_s32 type)
+{
-+ IS4 temp;
-+ hi_u32 rep_rsl = 0;
-+ hi_u8 sbox_tmp[4] = {0};
-+ hi_u8 sbox_c = 0;
-+ hi_u8 sbox_r = 0;
-+ int j;
++ is4 temp;
++ hi_u32 rep_rsl;
++ hi_u8 sbox_tmp[WORD_WIDTH] = {0};
++ hi_u8 sbox_c, sbox_r;
++ hi_s32 j;
+
-+ for (j = 0; j < 4; j++) {
++ for (j = 0; j < WORD_WIDTH; j++) {
+ sbox_tmp[j] = 0;
-+ sbox_r = ((data_in << (j * 8)) >> 28);
-+ sbox_c = ((data_in << (j * 8 + 4)) >> 28);
-+ sbox_tmp[j] = Sbox[sbox_r][sbox_c];
++ sbox_r = ((data_in << (j * BYTE_BITS)) >> 28); /* soft sm4 alg: right shift 28 bits. */
++ sbox_c = ((data_in << (j * BYTE_BITS + BYTE_4BIT)) >> 28); /* soft sm4 alg: right shift 28 bits. */
++ sbox_tmp[j] = g_sbox[sbox_r][sbox_c];
+ }
-+ temp.c[3] = sbox_tmp[0];
-+ temp.c[2] = sbox_tmp[1];
-+ temp.c[1] = sbox_tmp[2];
-+ temp.c[0] = sbox_tmp[3];
++ temp.c[WORD_IDX_3] = sbox_tmp[WORD_IDX_0];
++ temp.c[WORD_IDX_2] = sbox_tmp[WORD_IDX_1];
++ temp.c[WORD_IDX_1] = sbox_tmp[WORD_IDX_2];
++ temp.c[WORD_IDX_0] = sbox_tmp[WORD_IDX_3];
+
+ /* linearity replace */
+ if (type == KEY_EXT) {
-+ rep_rsl = temp.i
-+ ^ ((temp.i << 13) + ((temp.i >> 19) & 0x00001fff))
-+ ^ ((temp.i << 23) + ((temp.i >> 9) & 0x007fffff));
++ rep_rsl = temp.i ^ \
++ linearity_replace(temp.i, 13, 19, 0x00001fff) ^ \ /* linearity replace: left shift 13, 19, 0x00001fff. */
++ linearity_replace(temp.i, 23, 9, 0x007fffff); /* linearity replace: left shift 23, 9, 0x007fffff. */
+ } else {
-+ rep_rsl = temp.i
-+ ^ ((temp.i << 2) + ((temp.i >> 30) & 0x00000003))
-+ ^ ((temp.i << 10) + ((temp.i >> 22) & 0x000003ff))
-+ ^ ((temp.i << 18) + ((temp.i >> 14) & 0x0003ffff))
-+ ^ ((temp.i << 24) + ((temp.i >> 8) & 0x00ffffff));
++ rep_rsl = temp.i ^ \
++ linearity_replace(temp.i, 2, 30, 0x00000003) ^ \ /* linearity replace: left shift 2, 30, 0x00000003. */
++ linearity_replace(temp.i, 10, 22, 0x000003ff) ^ \ /* linearity replace: left shift 10, 22, 0x000003ff. */
++ linearity_replace(temp.i, 18, 14, 0x0003ffff) ^ \ /* linearity replace: left shift 18, 14, 0x0003ffff. */
++ linearity_replace(temp.i, 24, 8, 0x00ffffff); /* linearity replace: left shift 24, 8, 0x00ffffff. */
+ }
+
+ return rep_rsl;
+}
+
+/* Set key */
-+int sm4_set_encrypt_key(const hi_u8 *userKey, const int bits, sm4_key *key)
++hi_s32 sm4_set_encrypt_key(const hi_u8 *user_key, const hi_s32 bits, sm4_key *key)
+{
-+ int i = 0;
-+ hi_u32 k_temp[4] = {0};
-+ hi_u32 K[36] = {0};
-+ hi_u32 temp = 0;
++ hi_s32 i;
++ hi_u32 k_temp[SM4_KEY_SIZE / WORD_WIDTH] = {0};
++ hi_u32 K[SM4_RD_KEY_BUF_LEN] = {0};
++ hi_u32 temp;
+
-+ if (!userKey || !key) {
++ if (user_key == HI_NULL || key == HI_NULL) {
+ return -1;
+ }
+
-+ k_temp[0] = GETU32(userKey);
-+ k_temp[1] = GETU32(userKey + 4);
-+ k_temp[2] = GETU32(userKey + 8);
-+ k_temp[3] = GETU32(userKey + 12);
++ k_temp[WORD_IDX_0] = getu32(user_key);
++ k_temp[WORD_IDX_1] = getu32(user_key + WORD_IDX_1 * WORD_WIDTH);
++ k_temp[WORD_IDX_2] = getu32(user_key + WORD_IDX_2 * WORD_WIDTH);
++ k_temp[WORD_IDX_3] = getu32(user_key + WORD_IDX_3 * WORD_WIDTH);
+
-+ for (i = 0; i < 4; i++) {
-+ K[i] = k_temp[i] ^ FK[i];
++ for (i = 0; i < SM4_KEY_SIZE / WORD_WIDTH; i++) {
++ K[i] = k_temp[i] ^ g_fk[i];
+ }
+ i = 0;
+ while (1) {
-+ temp = K[i + 1] ^ K[i + 2] ^ K[i + 3] ^ CK[i];
-+ K[i + 4] = K[i] ^ Mix_R(temp, KEY_EXT);
-+ key->rd_key[i] = K[i + 4];
++ temp = K[i + WORD_IDX_1] ^ K[i + WORD_IDX_2] ^ K[i + WORD_IDX_3] ^ g_ck[i];
++ K[i + WORD_IDX_4] = K[i] ^ mix_r(temp, KEY_EXT);
++ key->rd_key[i] = K[i + WORD_IDX_4];
+
-+ if (++i == 32) {
++ if (++i == SM4_RD_KEY_LEN) {
+ return 0;
+ }
+ }
@@ -214261,66 +282934,73 @@ index 0000000..d55c255
+}
+
+/* SM4 Encrypt */
-+void sm4_encrypt(const hi_u8 *in, hi_u8 *out, const sm4_key *key)
++hi_void sm4_encrypt(const hi_u8 *in, hi_u8 *out, const sm4_key *key, hi_u32 len)
+{
-+ hi_u32 s[36] = {0};
-+ hi_u32 temp = 0;
-+ int i;
++ hi_u32 s[SM4_RD_KEY_BUF_LEN] = {0};
++ hi_u32 temp;
++ hi_s32 i;
+
-+ s[0] = GETU32(in);
-+ s[1] = GETU32(in + 4);
-+ s[2] = GETU32(in + 8);
-+ s[3] = GETU32(in + 12);
++ crypto_unused(len);
+
-+ for (i = 0; i < 32; i++) {
-+ temp = s[i + 1] ^ s[i + 2] ^ s[i + 3] ^ key->rd_key[i];
-+ s[i + 4] = s[i] ^ Mix_R(temp, CIPHER);
++ s[WORD_IDX_0] = getu32(in + WORD_IDX_0 * WORD_WIDTH);
++ s[WORD_IDX_1] = getu32(in + WORD_IDX_1 * WORD_WIDTH);
++ s[WORD_IDX_2] = getu32(in + WORD_IDX_2 * WORD_WIDTH);
++ s[WORD_IDX_3] = getu32(in + WORD_IDX_3 * WORD_WIDTH);
++
++ for (i = 0; i < SM4_RD_KEY_LEN; i++) {
++ temp = s[i + WORD_IDX_1] ^ s[i + WORD_IDX_2] ^ s[i + WORD_IDX_3] ^ key->rd_key[i];
++ s[i + WORD_IDX_4] = s[i] ^ mix_r(temp, CIPHER);
+ }
-+ PUTU32(out , s[35]);
-+ PUTU32(out + 4, s[34]);
-+ PUTU32(out + 8, s[33]);
-+ PUTU32(out + 12, s[32]);
++ putu32(out + WORD_IDX_0 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_3]);
++ putu32(out + WORD_IDX_1 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_2]);
++ putu32(out + WORD_IDX_2 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_1]);
++ putu32(out + WORD_IDX_3 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_0]);
+
+ return;
+}
+
+/* SM4 Decrypt */
-+void sm4_decrypt(const hi_u8 *in, hi_u8 *out, const sm4_key *key)
++hi_void sm4_decrypt(const hi_u8 *in, hi_u8 *out, const sm4_key *key, hi_u32 len)
+{
-+ hi_u32 s[36] = {0};
-+ hi_u32 temp = 0;
-+ int i;
++ hi_u32 s[SM4_RD_KEY_BUF_LEN] = {0};
++ hi_u32 temp;
++ hi_s32 i;
+
-+ s[0] = GETU32(in);
-+ s[1] = GETU32(in + 4);
-+ s[2] = GETU32(in + 8);
-+ s[3] = GETU32(in + 12);
++ crypto_unused(len);
+
-+ for (i = 0; i < 32; i++) {
-+ temp = s[i + 1] ^ s[i + 2] ^ s[i + 3] ^ key->rd_key[31 - i];
-+ s[i + 4] = s[i] ^ Mix_R(temp, CIPHER);
++ s[WORD_IDX_0] = getu32(in + WORD_IDX_0 * WORD_WIDTH);
++ s[WORD_IDX_1] = getu32(in + WORD_IDX_1 * WORD_WIDTH);
++ s[WORD_IDX_2] = getu32(in + WORD_IDX_2 * WORD_WIDTH);
++ s[WORD_IDX_3] = getu32(in + WORD_IDX_3 * WORD_WIDTH);
++
++ for (i = 0; i < SM4_RD_KEY_LEN; i++) {
++ temp = s[i + WORD_IDX_1] ^ s[i + WORD_IDX_2] ^ s[i + WORD_IDX_3] ^ \
++ key->rd_key[SM4_RD_KEY_LEN - BOUND_VAL_1 - i];
++ s[i + WORD_IDX_4] = s[i] ^ mix_r(temp, CIPHER);
+ }
-+ PUTU32(out , s[35]);
-+ PUTU32(out + 4, s[34]);
-+ PUTU32(out + 8, s[33]);
-+ PUTU32(out + 12, s[32]);
++
++ putu32(out + WORD_IDX_0 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_3]);
++ putu32(out + WORD_IDX_1 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_2]);
++ putu32(out + WORD_IDX_2 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_1]);
++ putu32(out + WORD_IDX_3 * WORD_WIDTH, s[SM4_RD_KEY_LEN + WORD_IDX_0]);
+
+ return;
+}
+
+/* SM4 ECB Crypt */
-+void sm4_ecb_crypt(const hi_u8 *in, hi_u8 *out, const sm4_key *key, const int dec)
++hi_void sm4_ecb_crypt(const hi_u8 *in, hi_u8 *out, hi_u32 len, const sm4_key *key, const hi_s32 dec)
+{
+ if (dec == SYMC_OPERATION_ENCRYPT) {
-+ sm4_encrypt(in, out, key);
++ sm4_encrypt(in, out, key, len);
+ } else {
-+ sm4_decrypt(in, out, key);
++ sm4_decrypt(in, out, key, len);
+ }
+ return;
+}
+
+/* SM4 CBC Crypt */
-+void sm4_cbc_crypt(const hi_u8 *in, hi_u8 *out, const hi_u32 length, const sm4_key *key, hi_u8 *ivec, const int dec)
++hi_void sm4_cbc_crypt(const hi_u8 *in, hi_u8 *out, const hi_u32 length, const sm4_key *key, hi_u8 *ivec,
++ const hi_s32 dec)
+{
+ hi_u32 n = 0;
+ hi_u32 len = length;
@@ -214332,9 +283012,9 @@ index 0000000..d55c255
+ tmp[n] = in[n] ^ ivec[n];
+ }
+
-+ sm4_encrypt(tmp, out, key);
++ sm4_encrypt(tmp, out, key, SM4_BLOCK_SIZE);
+
-+ memcpy((void *)ivec, out, SM4_BLOCK_SIZE);
++ memcpy((hi_void *)ivec, out, SM4_BLOCK_SIZE);
+ len -= SM4_BLOCK_SIZE;
+ in += SM4_BLOCK_SIZE;
+ out += SM4_BLOCK_SIZE;
@@ -214342,11 +283022,11 @@ index 0000000..d55c255
+ } else {
+ while (len >= SM4_BLOCK_SIZE) {
+ memcpy(tmp, in, sizeof(tmp));
-+ sm4_decrypt(tmp, out, key);
++ sm4_decrypt(tmp, out, key, SM4_BLOCK_SIZE);
+ for (n = 0; n < SM4_BLOCK_SIZE; ++n) {
+ out[n] ^= ivec[n];
+ }
-+ memcpy((void *)ivec, tmp, SM4_BLOCK_SIZE);
++ memcpy((hi_void *)ivec, tmp, SM4_BLOCK_SIZE);
+ len -= SM4_BLOCK_SIZE;
+ in += SM4_BLOCK_SIZE;
+ out += SM4_BLOCK_SIZE;
@@ -214356,12 +283036,12 @@ index 0000000..d55c255
+ return;
+}
+
-+/* increment counter (128bit int) by 2^64 */
-+static void sm4_ctr128_inc(hi_u8 *counter)
++/* increment counter (128bit hi_s32) by 2^64 */
++static hi_void sm4_ctr128_inc(hi_u8 *counter)
+{
-+ int i;
++ hi_s32 i;
+
-+ for (i = 15; i >= 0; i--) {
++ for (i = SM4_BLOCK_SIZE - BOUND_VAL_1; i >= 0; i--) {
+ counter[i]++;
+ if (counter[i] != 0) {
+ return;
@@ -214371,16 +283051,16 @@ index 0000000..d55c255
+}
+
+/* SM4 CTR Crypt, CTR mode is big-endian. The rest of SM4 code is endian-neutral */
-+void sm4_ctr128_crypt(const hi_u8 *in, hi_u8 *out, int length, const sm4_key *key, hi_u8 counter[SM4_BLOCK_SIZE], hi_u8 ecount_buf[SM4_BLOCK_SIZE], int *num)
++hi_void sm4_ctr128_crypt(const hi_u8 *in, hi_u8 *out, hi_s32 length, const sm4_key *key, hi_u8 counter[SM4_BLOCK_SIZE],
++ hi_u8 ecount_buf[SM4_BLOCK_SIZE], hi_s32 *num)
+{
-+ int n = 0;
-+ int l = 0;
-+ l = length;
++ hi_s32 n, l;
+
++ l = length;
+ n = *num;
+ while (l--) {
+ if (n == 0) {
-+ sm4_encrypt(counter, ecount_buf, key);
++ sm4_encrypt(counter, ecount_buf, key, SM4_BLOCK_SIZE);
+ sm4_ctr128_inc(counter);
+ }
+ *(out++) = *(in++) ^ ecount_buf[n];
@@ -214392,29 +283072,28 @@ index 0000000..d55c255
+}
+
+/* SM4 ECB RM */
-+hi_u32 sm4_ecb_rm(const hi_u8 *data_in, hi_u8 *data_out, int data_len, const hi_u8 *key, int bit, hi_u32 decrypt)
++hi_u32 sm4_ecb_rm(const hi_u8 *data_in, hi_u8 *data_out, hi_s32 data_len, const hi_u8 *key, hi_s32 bit, hi_u32 decrypt)
+{
+ sm4_key ctx;
+
+ sm4_set_encrypt_key(key, bit, &ctx);
+
-+ while (data_len >= 16) {
-+ sm4_ecb_crypt(data_in, data_out, &ctx, decrypt);
-+ data_len = data_len - 16;
-+ data_in = data_in + 16;
-+ data_out = data_out + 16;
++ while (data_len >= SM4_BLOCK_SIZE) {
++ sm4_ecb_crypt(data_in, data_out, SM4_BLOCK_SIZE, &ctx, decrypt);
++ data_len = data_len - SM4_BLOCK_SIZE;
++ data_in = data_in + SM4_BLOCK_SIZE;
++ data_out = data_out + SM4_BLOCK_SIZE;
+ }
+
+ return data_len;
+}
+
+/* SM4 CBC RM */
-+hi_u32 sm4_cbc_rm(const hi_u8 *data_in, hi_u8 *data_out, int data_len,
-+ const hi_u8 *key, int bit, hi_u32 decrypt,
-+ hi_u8 *iv)
++hi_u32 sm4_cbc_rm(const hi_u8 *data_in, hi_u8 *data_out, hi_s32 data_len, const hi_u8 *key, hi_s32 bit, hi_u32 decrypt,
++ hi_u8 *iv)
+{
-+ int left_len;
-+ int valid_data_len;
++ hi_s32 left_len;
++ hi_s32 valid_data_len;
+ sm4_key ctx;
+
+ sm4_set_encrypt_key(key, bit, &ctx);
@@ -214427,14 +283106,13 @@ index 0000000..d55c255
+}
+
+/* SM4 CTR RM */
-+hi_u32 sm4_ctr_rm(const hi_u8 *data_in, hi_u8 *data_out, int data_len,
-+ const hi_u8 *key, int bit, hi_u32 decrypt,
-+ const hi_u8 *iv)
++hi_u32 sm4_ctr_rm(const hi_u8 *data_in, hi_u8 *data_out, hi_s32 data_len, const hi_u8 *key, hi_s32 bit, hi_u32 decrypt,
++ const hi_u8 *iv)
+{
-+ int num = 0;
-+ int i;
-+ hi_u32 valid_data_len = 0;
-+ hi_u8 encrypt_cnt[16] = {0};
++ hi_s32 num = 0;
++ hi_s32 i;
++ hi_u32 valid_data_len;
++ hi_u8 encrypt_cnt[SM4_BLOCK_SIZE] = {0};
+ sm4_key ctx;
+
+ /* The SM4_ctr128_crypt request:
@@ -214444,10 +283122,6 @@ index 0000000..d55c255
+ * ecount_buf must be initialized with zeros before the first
+ * called to SM4_ctr128_crypt().
+ */
-+ for (i = 0; i < 16; i++) {
-+ encrypt_cnt[i] = 0;
-+ }
-+
+ valid_data_len = data_len;
+
+ sm4_set_encrypt_key(key, bit, &ctx);
@@ -214456,50 +283130,50 @@ index 0000000..d55c255
+ return 0;
+}
+
-+void *ext_sm4_create(hi_u32 hard_chn)
++hi_void *ext_sm4_create(hi_u32 hard_chn)
+{
+ ext_sm4_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ctx = crypto_malloc(sizeof(ext_sm4_context));
+ if (ctx == HI_NULL) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
+ return HI_NULL;
+ }
+ crypto_memset(ctx, sizeof(ext_sm4_context), 0, sizeof(ext_sm4_context));
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ctx;
+}
+
-+hi_s32 ext_sm4_destory(void *ctx)
++hi_s32 ext_sm4_destory(hi_void *ctx)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (ctx != HI_NULL) {
+ crypto_free(ctx);
+ ctx = HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void ext_sm4_setmode(void *ctx, symc_alg alg, symc_mode mode, symc_width width)
++hi_void ext_sm4_setmode(hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width)
+{
+ ext_sm4_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (symc == HI_NULL) {
-+ HI_LOG_ERROR("ctx is null\n");
++ hi_log_error("ctx is null\n");
+ return;
+ }
+
+ if (width != SYMC_DAT_WIDTH_128) {
-+ HI_LOG_ERROR("Invalid width: 0x%x\n", width);
++ hi_log_error("Invalid width: 0x%x\n", width);
+ return;
+ }
+
@@ -214514,175 +283188,164 @@ index 0000000..d55c255
+ symc->mode = SYMC_MODE_CTR;
+ break;
+ default:
-+ HI_LOG_ERROR("unsupport mode %d\n", mode);
++ hi_log_error("unsupport mode %d\n", mode);
+ return;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+hi_s32 ext_sm4_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
++hi_s32 ext_sm4_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
+{
+ ext_sm4_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(iv == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ivlen != HI_NULL);
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(iv == HI_NULL);
++ hi_log_chk_param_return(ivlen != HI_NULL);
+
+ crypto_memcpy(symc->iv, AES_IV_SIZE, iv, ivlen);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+void ext_sm4_getiv(void *ctx, hi_u8 *iv, hi_u32 *ivlen)
++hi_void ext_sm4_getiv(hi_void *ctx, hi_u8 *iv, hi_u32 *ivlen)
+{
+ ext_sm4_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if ((symc == HI_NULL) || (iv == HI_NULL) || (ivlen == HI_NULL)) {
+ return;
+ }
+
-+ crypto_memcpy(iv, AES_IV_SIZE, symc->iv, AES_IV_SIZE);
++ crypto_memcpy(iv, AES_IV_SIZE, symc->iv, sizeof(symc->iv));
+ *ivlen = AES_IV_SIZE;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return;
+}
+
-+hi_s32 ext_sm4_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++hi_s32 ext_sm4_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
+ hi_u32 klen = 0;
+ ext_sm4_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(fkey == HI_NULL);
-+ HI_LOG_CHECK_PARAM(hisi_klen == HI_NULL);
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(fkey == HI_NULL);
++ hi_log_chk_param_return(hisi_klen == HI_NULL);
+
+ switch (*hisi_klen) {
+ case HI_CIPHER_KEY_AES_128BIT:
+ klen = AES_KEY_128BIT;
+ break;
+ default:
-+ HI_LOG_ERROR("Invalid aes key len: 0x%x\n", klen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid aes key len: 0x%x\n", klen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
-+ HI_LOG_INFO("key len %d, type %d\n", klen, hisi_klen);
++ hi_log_info("key len %d, type %d\n", klen, hisi_klen);
+
+ crypto_memcpy(symc->key, SYMC_KEY_SIZE, fkey, klen);
+ symc->klen = klen;
+ *hisi_klen = klen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_sm4_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 last)
++static hi_s32 ext_sm4_rm(ext_sm4_context *symc, crypto_mem *mem_in, crypto_mem *mem_out, hi_u32 len, hi_u32 operation)
+{
-+ ext_sm4_context *symc = ctx;
-+ crypto_mem mem_in, mem_out;
-+ hi_s32 ret = HI_FAILURE;
-+
-+ HI_LOG_FUNC_ENTER();
-+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(length == HI_NULL);
-+ HI_LOG_CHECK_PARAM(input == HI_NULL);
-+ HI_LOG_CHECK_PARAM(output == HI_NULL);
-+ HI_LOG_CHECK_PARAM(usage_list == HI_NULL);
-+ HI_LOG_CHECK_PARAM(pkg_num != 0x01);
-+
-+ crypto_memset(&mem_in, sizeof(mem_in), 0, sizeof(mem_in));
-+ crypto_memset(&mem_out, sizeof(mem_out), 0, sizeof(mem_out));
-+
-+ ret = crypto_mem_open(&mem_in, input[0], length[0]);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of input failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ goto error0;
-+ }
-+
-+ ret = crypto_mem_open(&mem_out, output[0], length[0]);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of output failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ goto error1;
-+ }
-+
+ switch (symc->mode) {
+ case SYMC_MODE_ECB: {
-+ sm4_ecb_rm(crypto_mem_virt(&mem_in), crypto_mem_virt(&mem_out),
-+ length[0], symc->key, symc->klen, operation);
++ sm4_ecb_rm(crypto_mem_virt(mem_in), crypto_mem_virt(mem_out),
++ len, symc->key, symc->klen, operation);
+ break;
+ }
+ case SYMC_MODE_CBC: {
-+ sm4_cbc_rm(crypto_mem_virt(&mem_in), crypto_mem_virt(&mem_out),
-+ length[0], symc->key, symc->klen, operation, symc->iv);
++ sm4_cbc_rm(crypto_mem_virt(mem_in), crypto_mem_virt(mem_out),
++ len, symc->key, symc->klen, operation, symc->iv);
+ break;
+ }
+ case SYMC_MODE_CTR: {
-+ sm4_ctr_rm(crypto_mem_virt(&mem_in), crypto_mem_virt(&mem_out),
-+ length[0], symc->key, symc->klen, operation, symc->iv);
++ sm4_ctr_rm(crypto_mem_virt(mem_in), crypto_mem_virt(mem_out),
++ len, symc->key, symc->klen, operation, symc->iv);
+ break;
+ }
+ default: {
+ HI_PRINT("Err, Invalid mode 0x%x\n", symc->mode);
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ return HI_SUCCESS;
++}
++
++hi_s32 ext_sm4_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last)
++{
++ ext_sm4_context *symc = ctx;
++ crypto_mem mem_in, mem_out;
++ hi_s32 ret;
++
++ hi_log_func_enter();
++
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(pack == HI_NULL);
++ hi_log_chk_param_return(pack->len == HI_NULL);
++ hi_log_chk_param_return(pack->in == HI_NULL);
++ hi_log_chk_param_return(pack->out == HI_NULL);
++ hi_log_chk_param_return(pack->usage == HI_NULL);
++ hi_log_chk_param_return(pack->num != 0x01);
++
++ crypto_memset(&mem_in, sizeof(mem_in), 0, sizeof(mem_in));
++ crypto_memset(&mem_out, sizeof(mem_out), 0, sizeof(mem_out));
++
++ ret = crypto_mem_open(&mem_in, pack->in[0], pack->len[0]);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_open, ret);
++ return ret;
++ }
++
++ ret = crypto_mem_open(&mem_out, pack->out[0], pack->len[0]);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_open, ret);
++ crypto_mem_close(&mem_in);
++ return ret;
++ }
++
++ ret = ext_sm4_rm(symc, &mem_in, &mem_out, pack->len[0], operation);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ext_sm4_rm, ret);
++ crypto_mem_close(&mem_out);
++ crypto_mem_close(&mem_in);
++ return ret;
++ }
+
+ crypto_mem_close(&mem_out);
-+error1:
+ crypto_mem_close(&mem_in);
-+error0:
-+
-+ return ret;
++ hi_log_func_exit();
++ return HI_SUCCESS;
+}
+
+#endif
-+/** @}*/ /** <!-- ==== API Code end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_symc.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_symc.c
new file mode 100644
-index 0000000..df63294
+index 0000000..4ab04d1
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/ext_symc.c
-@@ -0,0 +1,293 @@
+@@ -0,0 +1,287 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for ext symc.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
@@ -214691,44 +283354,43 @@ index 0000000..df63294
+
+#if defined(SOFT_AES_SUPPORT) || defined(SOFT_TDES_SUPPORT)
+
-+/**
-+ * \brief aes ccm context structure
++/*
++ * brief aes ccm context structure
+ */
+typedef struct {
-+ hi_u32 key[SYMC_KEY_SIZE / 4]; /*!< SYMC even round keys, default */
-+ hi_u32 klen; /*!< symc key length */
++ hi_u32 key[SYMC_KEY_SIZE / WORD_WIDTH]; /* symc even round keys, default */
++ hi_u32 klen; /* symc key length */
+ mbedtls_cipher_id_t cipher_id;
+ mbedtls_cipher_mode_t mode;
+ mbedtls_cipher_context_t cipher;
-+}
-+ext_symc_context;
++} ext_symc_context;
+
-+void *ext_mbedtls_symc_create(hi_u32 hard_chn)
++hi_void *ext_mbedtls_symc_create(hi_u32 hard_chn)
+{
+ ext_symc_context *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ctx = crypto_malloc(sizeof(ext_symc_context));
+ if (ctx == HI_NULL) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+ HI_LOG_ERROR("malloc failed \n");
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_error("malloc failed \n");
+ return HI_NULL;
+ }
+ crypto_memset(ctx, sizeof(ext_symc_context), 0, sizeof(ext_symc_context));
+
+ mbedtls_cipher_init(&ctx->cipher);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ctx;
+}
+
-+hi_s32 ext_mbedtls_symc_destory(void *ctx)
++hi_s32 ext_mbedtls_symc_destory(hi_void *ctx)
+{
+ ext_symc_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (ctx != HI_NULL) {
+ mbedtls_cipher_free(&symc->cipher);
@@ -214736,18 +283398,18 @@ index 0000000..df63294
+ ctx = HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_symc_setmode(void *ctx, symc_alg alg, symc_mode mode, symc_width width)
++hi_s32 ext_mbedtls_symc_setmode(hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width)
+{
+ ext_symc_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(width != SYMC_DAT_WIDTH_128);
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(width != SYMC_DAT_WIDTH_128);
+
+ switch (alg) {
+ case SYMC_ALG_AES:
@@ -214760,9 +283422,9 @@ index 0000000..df63294
+ symc->cipher_id = MBEDTLS_CIPHER_ID_DES;
+ break;
+ default:
-+ HI_LOG_ERROR("unsupport alg %d\n", alg);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("unsupport alg %d\n", alg);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ switch (mode) {
@@ -214782,65 +283444,65 @@ index 0000000..df63294
+ symc->mode = MBEDTLS_MODE_CTR;
+ break;
+ default:
-+ HI_LOG_ERROR("unsupport mode %d\n", mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("unsupport mode %d\n", mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ HI_LOG_DEBUG("cipher_id %d, mode %d\n", symc->cipher_id, symc->mode);
++ hi_log_debug("cipher_id %d, mode %d\n", symc->cipher_id, symc->mode);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_symc_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
++hi_s32 ext_mbedtls_symc_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ ext_symc_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(iv == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ivlen > AES_IV_SIZE);
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(iv == HI_NULL);
++ hi_log_chk_param_return(ivlen > AES_IV_SIZE);
+
+ ret = mbedtls_cipher_set_iv(&symc->cipher, iv, ivlen);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ret;
+}
+
-+hi_s32 ext_mbedtls_symc_getiv(void *ctx, hi_u8 *iv, hi_u32 *ivlen)
++hi_s32 ext_mbedtls_symc_getiv(hi_void *ctx, hi_u8 *iv, hi_u32 *ivlen)
+{
+ ext_symc_context *symc = ctx;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(iv == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ivlen == HI_NULL);
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(iv == HI_NULL);
++ hi_log_chk_param_return(ivlen == HI_NULL);
+
+ crypto_memcpy(iv, AES_IV_SIZE, symc->cipher.iv, symc->cipher.iv_size);
+ *ivlen = symc->cipher.iv_size;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return HI_SUCCESS;
+}
+
-+hi_s32 ext_mbedtls_symc_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
++hi_s32 ext_mbedtls_symc_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 klen = 0;
+ ext_symc_context *symc = ctx;
+ const mbedtls_cipher_info_t *info = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(fkey == HI_NULL);
-+ HI_LOG_CHECK_PARAM(hisi_klen == HI_NULL);
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(fkey == HI_NULL);
++ hi_log_chk_param_return(hisi_klen == HI_NULL);
+
+ if (symc->cipher_id == MBEDTLS_CIPHER_ID_AES) {
+ switch (*hisi_klen) {
@@ -214854,483 +283516,426 @@ index 0000000..df63294
+ klen = AES_KEY_256BIT;
+ break;
+ default:
-+ HI_LOG_ERROR("Invalid aes key len: 0x%x\n", klen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid aes key len: 0x%x\n", klen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ crypto_memcpy(symc->key, SYMC_KEY_SIZE, fkey, klen);
+ } else if (symc->cipher_id == MBEDTLS_CIPHER_ID_3DES) {
+ klen = TDES_KEY_192BIT;
+ crypto_memcpy(symc->key, SYMC_KEY_SIZE, fkey, klen);
+ if (*hisi_klen == HI_CIPHER_KEY_DES_2KEY) {
-+ /* k3 = k1*/
-+ symc->key[4] = symc->key[0];
-+ symc->key[5] = symc->key[1];
++ /* descript: k3 = k1 */
++ symc->key[WORD_IDX_4] = symc->key[WORD_IDX_0];
++ symc->key[WORD_IDX_5] = symc->key[WORD_IDX_1];
+ }
+ } else if (symc->cipher_id == MBEDTLS_CIPHER_ID_DES) {
+ klen = DES_KEY_SIZE;
+ crypto_memcpy(symc->key, SYMC_KEY_SIZE, fkey, klen);
+ }
-+ HI_LOG_INFO("key len %d, type %d\n", klen, *hisi_klen);
++ hi_log_info("key len %d, type %d\n", klen, *hisi_klen);
+
+ symc->klen = klen;
+
-+ HI_LOG_DEBUG("cipher_id %d, klen %d, mode %d\n", symc->cipher_id, klen, symc->mode);
-+ info = mbedtls_cipher_info_from_values(symc->cipher_id, klen * 8, symc->mode);
-+ HI_LOG_CHECK_PARAM(info == HI_NULL);
++ hi_log_debug("cipher_id %d, klen %d, mode %d\n", symc->cipher_id, klen, symc->mode);
++ info = mbedtls_cipher_info_from_values(symc->cipher_id, klen * BYTE_BITS, symc->mode);
++ hi_log_chk_param_return(info == HI_NULL);
+
+ ret = mbedtls_cipher_setup(&symc->cipher, info);
+
+ *hisi_klen = klen;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ret;
+}
+
-+hi_s32 ext_mbedtls_symc_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 last)
++static hi_s32 ext_symc_update(ext_symc_context *symc, crypto_mem *mem_in, crypto_mem *mem_out, hi_u32 len, hi_u32 *olen)
++{
++ hi_s32 ret;
++ if (symc->mode == MBEDTLS_MODE_ECB) {
++ hi_u32 offset = 0;
++ while (offset < len) {
++ ret = mbedtls_cipher_update(symc->cipher, crypto_mem_virt(mem_in) + offset,
++ mbedtls_cipher_get_block_size(symc->cipher), crypto_mem_virt(mem_out) + offset, olen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_cipher_update, ret);
++ return ret;
++ }
++ offset += mbedtls_cipher_get_block_size(symc->cipher);
++ }
++ } else {
++ ret = mbedtls_cipher_update(symc->cipher, crypto_mem_virt(mem_in), len, crypto_mem_virt(mem_out), olen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(mbedtls_cipher_update, ret);
++ return ret;
++ }
++ }
++
++ return HI_SUCCESS;
++}
++
++hi_s32 ext_mbedtls_symc_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last)
+{
+ ext_symc_context *symc = ctx;
+ crypto_mem mem_in, mem_out;
+ hi_u32 offset = 0;
+ size_t olen = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(symc == HI_NULL);
-+ HI_LOG_CHECK_PARAM(input == HI_NULL);
-+ HI_LOG_CHECK_PARAM(output == HI_NULL);
-+ HI_LOG_CHECK_PARAM(length == HI_NULL);
-+ HI_LOG_CHECK_PARAM(pkg_num != 0x01);
++ hi_log_chk_param_return(symc == HI_NULL);
++ hi_log_chk_param_return(pack == HI_NULL);
++ hi_log_chk_param_return(pack->in == HI_NULL);
++ hi_log_chk_param_return(pack->out == HI_NULL);
++ hi_log_chk_param_return(pack->len == HI_NULL);
++ hi_log_chk_param_return(pack->num != 0x01);
+
-+ ret = mbedtls_cipher_setkey(&symc->cipher, (hi_u8 *)symc->key, symc->klen * 8,
++ ret = mbedtls_cipher_setkey(&symc->cipher, (hi_u8 *)symc->key, symc->klen * BYTE_BITS,
+ operation ? MBEDTLS_DECRYPT : MBEDTLS_ENCRYPT);
-+ if (ret != HI_SUCCESS)
-+ { return ret; }
-+
-+ ret = crypto_mem_open(&mem_in, input[0], length[0]);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of input failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ goto error0;
++ hi_log_print_func_err(mbedtls_cipher_setkey, ret);
++ return ret;
+ }
+
-+ ret = crypto_mem_open(&mem_out, output[0], length[0]);
++ ret = crypto_mem_open(&mem_in, pack->in[0], pack->len[0]);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("open mem of output failed\n");
-+ ret = HI_ERR_CIPHER_FAILED_MEM;
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ goto error1;
++ hi_log_print_func_err(crypto_mem_open, ret);
++ return ret;
+ }
+
-+ HI_LOG_DEBUG("symc 0x%p, klen len: %d\n", symc, symc->klen);
-+
-+ if (symc->mode == MBEDTLS_MODE_ECB) {
-+ offset = 0;
-+ while (offset < length[0]) {
-+ ret = mbedtls_cipher_update(&symc->cipher, crypto_mem_virt(&mem_in) + offset,
-+ mbedtls_cipher_get_block_size(&symc->cipher),
-+ crypto_mem_virt(&mem_out) + offset, &olen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("mbedtls_cipher_update failed\n");
-+ break;
-+ }
-+ offset += mbedtls_cipher_get_block_size(&symc->cipher);
-+ }
-+ } else {
-+ ret = mbedtls_cipher_update(&symc->cipher, crypto_mem_virt(&mem_in),
-+ length[0], crypto_mem_virt(&mem_out), &olen);
++ ret = crypto_mem_open(&mem_out, pack->out[0], pack->len[0]);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_mem_open, ret);
++ crypto_mem_close(&mem_in);
++ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_debug("symc 0x%p, klen len: %d\n", symc, symc->klen);
++
++ ret = ext_symc_update(symc, mem_in, mem_out, pack->len[0], &olen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ext_symc_update, ret);
++ crypto_mem_close(&mem_out);
++ crypto_mem_close(&mem_in);
++ return ret;
++ }
+
+ crypto_mem_close(&mem_out);
-+error1:
+ crypto_mem_close(&mem_in);
-+error0:
-+
++ hi_log_func_exit();
+ return ret;
+}
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/ext_alg.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/ext_alg.h
new file mode 100644
-index 0000000..d53b63e
+index 0000000..002a6b3
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/ext_alg.h
-@@ -0,0 +1,359 @@
+@@ -0,0 +1,296 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for ext alg of cipher soft ware.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __EXT_ALG_H_
+#define __EXT_ALG_H_
+
-+#include "drv_osal_lib.h"
+#include "drv_hash.h"
+#include "drv_symc.h"
++#include "drv_cipher_kapi.h"
++#include "drv_osal_lib.h"
+
-+/******************************* API Declaration *****************************/
-+/** \addtogroup hash */
-+/** @{ */ /** <!--[hash]*/
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup cipher drivers*/
-+/** @{*/ /** <!-- [cipher]*/
-+
-+/**
-+ * \brief Create symc handle
++/*
++ * brief Create symc handle
+ *
-+ * \param handle symc handle to be initialized
-+ * \param hard_key symc use hard key ot not
++ * param handle symc handle to be initialized
++ * param hard_key symc use hard key ot not
+ */
-+void *ext_mbedtls_aead_create(hi_u32 hard_key);
++hi_void *ext_mbedtls_aead_create(hi_u32 hard_key);
+
-+/**
-+ * \brief Clear symc context
++/*
++ * brief Clear symc context
+ *
-+ * \param handle symc handle to be destory
++ * param handle symc handle to be destory
+ */
-+hi_s32 ext_mbedtls_aead_destory(void *ctx);
++hi_s32 ext_mbedtls_aead_destory(hi_void *ctx);
+
-+/**
-+ * \brief symc iv schedule
++/*
++ * brief symc iv schedule
+ *
-+ * \param handle symc handle
-+ * \param IV encryption key
-+ * \param ivlen length of iv
++ * param handle symc handle
++ * param IV encryption key
++ * param ivlen length of iv
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+hi_s32 ext_mbedtls_aead_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
++hi_s32 ext_mbedtls_aead_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
+
-+/**
-+ * \brief symc key schedule
++/*
++ * brief symc key schedule
+ *
-+ * \param ctx SYMC handle
-+ * \param key SYMC key
-+ * \param keylen SYMC key length
++ * param ctx SYMC handle
++ * param key SYMC key
++ * param keylen SYMC key length
+ *
-+ * \return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
++ * return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
+ */
-+hi_s32 ext_mbedtls_aead_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
++hi_s32 ext_mbedtls_aead_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
+
-+/**
-+ * \brief SYMC alg and mode
++/*
++ * brief SYMC alg and mode
+ *
-+ * \param ctx SYMC handle
-+ * \param aad Associated Data
-+ * \param alen Associated Data Length
-+ * \param tlen Tag length
++ * param ctx SYMC handle
++ * param aad Associated Data
++ * param alen Associated Data Length
++ * param tlen Tag length
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+hi_s32 ext_mbedtls_aead_set_aad( void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen);
++hi_s32 ext_mbedtls_aead_set_aad(hi_void *ctx, compat_addr aad, hi_u32 alen, hi_u32 tlen);
+
-+/**
-+\brief get ccm/gcm tag.
-+\param[in] chn_num The channel number.
-+\param[out] tag The tag value.
-+\param[out] taglen tag length
-+\retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
-+*/
-+hi_s32 ext_mbedtls_aead_get_tag(void *ctx, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen);
++/*
++ * brief get ccm/gcm tag.
++ * param[in] chn_num The channel number.
++ * param[out] tag The tag value.
++ * param[out] taglen tag length
++ * \retval On received interception, HI_TRUE is returned otherwise HI_FALSE is returned.
++ */
++hi_s32 ext_mbedtls_aead_get_tag(hi_void *ctx, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen);
+
-+/**
-+ * \brief aead ccm buffer encryption/decryption.
++/*
++ * brief aead ccm buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param handle symc handle
-+ * \param decrypt decrypt or encrypt
-+ * \param mode mode
-+ * \param length length of the input data
-+ * \param input buffer holding the input data
-+ * \param output buffer holding the output data
-+ * \param usage_list usage of buffer
-+ * \param pkg_num numbers of buffer
++ * param ctx symc ctx.
++ * param operation operation of encrypt or decrypt.
++ * param pack package of decrypt or encrypt.
++ * param last last or not.
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 ext_mbedtls_aead_ccm_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ hi_u32 usage_list[],
-+ hi_u32 pkg_num, hi_u32 last);
++hi_s32 ext_mbedtls_aead_ccm_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last);
+
-+/**
-+ * \brief aead gcm buffer encryption/decryption.
++/*
++ * brief aead gcm buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param handle symc handle
-+ * \param decrypt decrypt or encrypt
-+ * \param mode mode
-+ * \param length length of the input data
-+ * \param input buffer holding the input data
-+ * \param output buffer holding the output data
-+ * \param usage_list usage of buffer
-+ * \param pkg_num numbers of buffer
++ * param ctx symc ctx.
++ * param operation operation of encrypt or decrypt.
++ * param pack package of decrypt or encrypt.
++ * param last last or not.
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 ext_mbedtls_aead_gcm_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ hi_u32 usage_list[],
-+ hi_u32 pkg_num, hi_u32 last);
++hi_s32 ext_mbedtls_aead_gcm_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last);
+
-+/**
-+ * \brief Create symc handle
++/*
++ * brief Create symc handle
+ *
-+ * \param handle symc handle to be initialized
-+ * \param hard_key symc use hard key ot not
++ * param handle symc handle to be initialized
++ * param hard_key symc use hard key ot not
+ */
-+void *ext_mbedtls_symc_create(hi_u32 hard_key);
++hi_void *ext_mbedtls_symc_create(hi_u32 hard_key);
+
-+/**
-+ * \brief Clear symc context
++/*
++ * brief Clear symc context
+ *
-+ * \param handle symc handle to be destory
++ * param handle symc handle to be destory
+ */
-+hi_s32 ext_mbedtls_symc_destory(void *ctx);
++hi_s32 ext_mbedtls_symc_destory(hi_void *ctx);
+
-+/**
-+ * \brief SYMC alg and mode
++/*
++ * brief SYMC alg and mode
+ *
-+ * \param handle SYMC handle
-+ * \param alg Symmetric cipher alg
-+ * \param mode Symmetric cipher mode
++ * param handle SYMC handle
++ * param alg Symmetric cipher alg
++ * param mode Symmetric cipher mode
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+void ext_mbedtls_symc_setmode(void *ctx, symc_alg alg, symc_mode mode, symc_width width);
++hi_void ext_mbedtls_symc_setmode(hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width);
+
-+/**
-+ * \brief symc iv schedule
++/*
++ * brief symc iv schedule
+ *
-+ * \param handle symc handle
-+ * \param IV encryption key
-+ * \param ivlen length of iv
++ * param handle symc handle
++ * param IV encryption key
++ * param ivlen length of iv
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+hi_s32 ext_mbedtls_symc_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
++hi_s32 ext_mbedtls_symc_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
+
-+/**
-+ * \brief Symc iv schedule
++/*
++ * brief Symc iv schedule
+ *
-+ * \param handle symc handle
-+ * \param IV Symc IV
-+ * \param ivlen must be 128, 192 or 256
++ * param handle symc handle
++ * param IV Symc IV
++ * param ivlen must be 128, 192 or 256
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+void ext_mbedtls_symc_getiv(void *ctx, hi_u8 *iv, hi_u32 *ivlen);
++hi_void ext_mbedtls_symc_getiv(hi_void *ctx, hi_u8 *iv, hi_u32 *ivlen);
+
-+/**
-+ * \brief symc key schedule
++/*
++ * brief symc key schedule
+ *
-+ * \param ctx SYMC handle
-+ * \param key SYMC key
-+ * \param keylen SYMC key length
++ * param ctx SYMC handle
++ * param key SYMC key
++ * param keylen SYMC key length
+ *
-+ * \return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
++ * return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
+ */
-+hi_s32 ext_mbedtls_symc_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
++hi_s32 ext_mbedtls_symc_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
+
-+/**
-+ * \brief symc buffer encryption/decryption.
++/*
++ * brief symc buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param handle symc handle
-+ * \param decrypt decrypt or encrypt
-+ * \param mode mode
-+ * \param length length of the input data
-+ * \param input buffer holding the input data
-+ * \param output buffer holding the output data
-+ * \param usage_list usage of buffer
-+ * \param pkg_num numbers of buffer
-+ *
-+ * \return 0 if successful
++ * param ctx symc ctx
++ * param operation decrypt or encrypt
++ * param pack package for encrypt or decrypt.
++ * param last last or not
++ * return 0 if successful
+ */
-+hi_s32 ext_mbedtls_symc_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 last);
++hi_s32 ext_mbedtls_symc_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last);
+
-+/**
-+ * \brief Create sm4 handle
++/*
++ * brief Create sm4 handle
+ *
-+ * \param handle sm4 handle to be initialized
-+ * \param hard_key sm4 use hard key ot not
++ * param handle sm4 handle to be initialized
++ * param hard_key sm4 use hard key ot not
+ */
-+void *ext_sm4_create(hi_u32 hard_key);
++hi_void *ext_sm4_create(hi_u32 hard_key);
+
-+/**
-+ * \brief Clear sm4 context
++/*
++ * brief Clear sm4 context
+ *
-+ * \param handle sm4 handle to be destory
++ * param handle sm4 handle to be destory
+ */
-+hi_s32 ext_sm4_destory(void *ctx);
++hi_s32 ext_sm4_destory(hi_void *ctx);
+
-+/**
-+ * \brief sm4 alg and mode
++/*
++ * brief sm4 alg and mode
+ *
-+ * \param handle sm4 handle
-+ * \param alg Symmetric cipher alg
-+ * \param mode Symmetric cipher mode
++ * param handle sm4 handle
++ * param alg Symmetric cipher alg
++ * param mode Symmetric cipher mode
+ *
-+ * \return NA.
++ * return NA.
+ */
-+void ext_sm4_setmode(void *ctx, symc_alg alg, symc_mode mode, symc_width width);
++hi_void ext_sm4_setmode(hi_void *ctx, symc_alg alg, symc_mode mode, symc_width width);
+
-+/**
-+ * \brief sm4 iv schedule
++/*
++ * brief sm4 iv schedule
+ *
-+ * \param handle sm4 handle
-+ * \param IV encryption key
-+ * \param ivlen length of iv
++ * param handle sm4 handle
++ * param IV encryption key
++ * param ivlen length of iv
+ *
-+ * \return 0 if successful.
++ * return 0 if successful.
+ */
-+hi_s32 ext_sm4_setiv(void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
++hi_s32 ext_sm4_setiv(hi_void *ctx, const hi_u8 *iv, hi_u32 ivlen, hi_u32 usage);
+
-+/**
-+ * \brief Symc iv schedule
++/*
++ * brief Symc iv schedule
+ *
-+ * \param handle symc handle
-+ * \param IV Symc IV
-+ * \param ivlen must be 128, 192 or 256
++ * param handle symc handle
++ * param IV Symc IV
++ * param ivlen must be 128, 192 or 256
+ *
-+ * \return NA.
++ * return NA.
+ */
-+void ext_sm4_getiv(void *ctx, hi_u8 *iv, hi_u32 *ivlen);
++hi_void ext_sm4_getiv(hi_void *ctx, hi_u8 *iv, hi_u32 *ivlen);
+
-+/**
-+ * \brief sm4 key schedule
++/*
++ * brief sm4 key schedule
+ *
-+ * \param ctx sm4 handle
-+ * \param key sm4 key
-+ * \param keylen sm4 key length
++ * param ctx sm4 handle
++ * param key sm4 key
++ * param keylen sm4 key length
+ *
-+ * \return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
++ * return 0 if successful, or HI_SYMC_ERR_KEY_LEN_INVALID
+ */
-+hi_s32 ext_sm4_setkey(void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
++hi_s32 ext_sm4_setkey(hi_void *ctx, const hi_u8 *fkey, const hi_u8 *skey, hi_u32 *hisi_klen);
+
-+/**
-+ * \brief sm4 buffer encryption/decryption.
++/*
++ * brief sm4 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of aes you should use the same key schedule for
+ * both encryption and decryption.
+ *
-+ * \param handle sm4 handle
-+ * \param decrypt decrypt or encrypt
-+ * \param mode mode
-+ * \param length length of the input data
-+ * \param input buffer holding the input data
-+ * \param output buffer holding the output data
-+ * \param usage_list usage of buffer
-+ * \param pkg_num numbers of buffer
++ * param ctx sm4 ctx
++ * param operation decrypt or encrypt
++ * param pack package for encrypt or decrypt.
++ * param last last or not
+ *
-+ * \return 0 if successful
++ * return 0 if successful
+ */
-+hi_s32 ext_sm4_crypto(void *ctx,
-+ hi_u32 operation,
-+ compat_addr input[],
-+ compat_addr output[],
-+ hi_u32 length[],
-+ symc_node_usage usage_list[],
-+ hi_u32 pkg_num, hi_u32 last);
++hi_s32 ext_sm4_crypto(hi_void *ctx, hi_u32 operation, symc_multi_pack *pack, hi_u32 last);
+
-+/**
-+ * \brief Clear hash context
++/*
++ * brief Clear hash context
+ *
-+ * \param ctx symc handle to be destory
++ * param ctx symc handle to be destory
+ */
-+void *mbedtls_hash_create(hash_mode mode);
++hi_void *mbedtls_hash_create(hash_mode mode);
+
-+/**
-+ * \brief Hash message chunk calculation
++/*
++ * brief Hash message chunk calculation
+ *
+ * Note: the message must be write to the buffer
+ * which get from cryp_hash_get_cpu_addr, and the length of message chunk
+ * can't large than the length which get from cryp_hash_get_cpu_addr.
+ *
-+ * \param ctx hash handle to be destory
-+ * \param chunk hash message to update
-+ * \param length length of hash message
-+ * \param src source of hash message
++ * param ctx hash handle to be destory
++ * param chunk hash message to update
++ * param length length of hash message
++ * param src source of hash message
+ */
-+hi_s32 mbedtls_hash_update(void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src);
++hi_s32 mbedtls_hash_update(hi_void *ctx, hi_u8 *chunk, hi_u32 chunk_len, hash_chunk_src src);
+
-+/**
-+ * \brief HASH final digest
++/*
++ * brief HASH final digest
+ *
-+ * \param ctx Hash handle
-+ * \param hash HASH checksum result
-+ * \param hashlen Length of HASH checksum result
++ * param ctx Hash handle
++ * param hash HASH checksum result
++ * param hashlen Length of HASH checksum result
+ */
-+hi_s32 mbedtls_hash_finish(void *ctx, void *hash, hi_u32 *hashlen);
++hi_s32 mbedtls_hash_finish(hi_void *ctx, hi_void *hash, hi_u32 *hashlen);
+
-+/**
-+ * \brief Clear hash context
++/*
++ * brief Clear hash context
+ *
-+ * \param ctx symc handle to be destory
++ * param ctx symc handle to be destory
+ */
-+hi_s32 mbedtls_hash_destory(void *ctx);
++hi_s32 mbedtls_hash_destory(hi_void *ctx);
+
+/* sm3 */
-+void *ext_sm3_create(hash_mode mode);
++hi_void *ext_sm3_create(hash_mode mode);
+
-+hi_s32 ext_sm3_update(void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src);
++hi_s32 ext_sm3_update(hi_void *ctx, hi_u8 *chunk, hi_u32 chunkLen, hash_chunk_src src);
+
-+hi_s32 ext_sm3_finish(void *ctx, void *hash, hi_u32 *hashlen);
++hi_s32 ext_sm3_finish(hi_void *ctx, hi_void *hash, hi_u32 *hashlen);
+
-+hi_s32 ext_sm3_destory(void *ctx);
-+
-+/** @} */ /** <!-- ==== API declaration end ==== */
++hi_s32 ext_sm3_destory(hi_void *ctx);
+#endif
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/aes.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/aes.h
new file mode 100644
-index 0000000..0654b16
+index 0000000..a8b62da
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/aes.h
-@@ -0,0 +1,676 @@
+@@ -0,0 +1,674 @@
+/**
+ * \file aes.h
+ *
@@ -215354,21 +283959,19 @@ index 0000000..0654b16
+ */
+
+/* Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved.
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -216009,10 +284612,10 @@ index 0000000..0654b16
+#endif /* aes.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/aesni.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/aesni.h
new file mode 100644
-index 0000000..20df500
+index 0000000..0196f49
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/aesni.h
-@@ -0,0 +1,134 @@
+@@ -0,0 +1,132 @@
+/**
+ * \file aesni.h
+ *
@@ -216023,21 +284626,19 @@ index 0000000..20df500
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -216149,10 +284750,10 @@ index 0000000..20df500
+#endif /* MBEDTLS_AESNI_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/asn1.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/asn1.h
new file mode 100644
-index 0000000..00b6f2c
+index 0000000..96c1c9a
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/asn1.h
-@@ -0,0 +1,360 @@
+@@ -0,0 +1,358 @@
+/**
+ * \file asn1.h
+ *
@@ -216160,21 +284761,19 @@ index 0000000..00b6f2c
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -216515,10 +285114,10 @@ index 0000000..00b6f2c
+#endif /* asn1.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/asn1write.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/asn1write.h
new file mode 100644
-index 0000000..a681656
+index 0000000..76c1780
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/asn1write.h
-@@ -0,0 +1,324 @@
+@@ -0,0 +1,322 @@
+/**
+ * \file asn1write.h
+ *
@@ -216526,21 +285125,19 @@ index 0000000..a681656
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -216845,10 +285442,10 @@ index 0000000..a681656
+#endif /* MBEDTLS_ASN1_WRITE_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/bignum.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/bignum.h
new file mode 100644
-index 0000000..3efb5d4
+index 0000000..eeaddbf
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/bignum.h
-@@ -0,0 +1,961 @@
+@@ -0,0 +1,964 @@
+/**
+ * \file bignum.h
+ *
@@ -216856,21 +285453,19 @@ index 0000000..3efb5d4
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -217649,6 +286244,11 @@ index 0000000..3efb5d4
+ const mbedtls_mpi *E, const mbedtls_mpi *N,
+ mbedtls_mpi *_RR );
+
++/* rsa rsa soft function */
++int mbedtls_mpi_exp_mod_sw( mbedtls_mpi *X, const mbedtls_mpi *A,
++ const mbedtls_mpi *E, const mbedtls_mpi *N,
++ mbedtls_mpi *_RR );
++
+/**
+ * \brief Fill an MPI with a number of random bytes.
+ *
@@ -217812,10 +286412,10 @@ index 0000000..3efb5d4
+#endif /* bignum.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/bn_mul.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/bn_mul.h
new file mode 100644
-index 0000000..58d37a5
+index 0000000..a27a9ba
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/bn_mul.h
-@@ -0,0 +1,911 @@
+@@ -0,0 +1,909 @@
+/**
+ * \file bn_mul.h
+ *
@@ -217823,21 +286423,19 @@ index 0000000..58d37a5
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -218236,7 +286834,7 @@ index 0000000..58d37a5
+ * The Sparc(64) assembly is reported to be broken.
+ * Disable it for now, until we're able to fix it.
+ */
-+#if 0 && defined(__sparc__)
++#if __CRYPTO_TEST_SUPPORT__ && defined(__sparc__)
+#if defined(__sparc64__)
+
+#define MULADDC_INIT \
@@ -218729,10 +287327,10 @@ index 0000000..58d37a5
+#endif /* bn_mul.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/ccm.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/ccm.h
new file mode 100644
-index 0000000..b9a5112
+index 0000000..3f6b8f6
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/ccm.h
-@@ -0,0 +1,306 @@
+@@ -0,0 +1,304 @@
+/**
+ * \file ccm.h
+ *
@@ -218764,21 +287362,19 @@ index 0000000..b9a5112
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -219041,10 +287637,10 @@ index 0000000..b9a5112
+#endif /* MBEDTLS_CCM_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/check_config.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/check_config.h
new file mode 100644
-index 0000000..f5f16cd
+index 0000000..abe7ac8
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/check_config.h
-@@ -0,0 +1,700 @@
+@@ -0,0 +1,698 @@
+/**
+ * \file check_config.h
+ *
@@ -219052,21 +287648,19 @@ index 0000000..f5f16cd
+ */
+/*
+ * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -219747,10 +288341,10 @@ index 0000000..f5f16cd
+#endif /* MBEDTLS_CHECK_CONFIG_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/cipher.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/cipher.h
new file mode 100644
-index 0000000..3820a73
+index 0000000..922b6c3
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/cipher.h
-@@ -0,0 +1,874 @@
+@@ -0,0 +1,872 @@
+/**
+ * \file cipher.h
+ *
@@ -219762,21 +288356,19 @@ index 0000000..3820a73
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -220627,10 +289219,10 @@ index 0000000..3820a73
+#endif /* MBEDTLS_CIPHER_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/cipher_internal.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/cipher_internal.h
new file mode 100644
-index 0000000..9f2858a
+index 0000000..c6def0b
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/cipher_internal.h
-@@ -0,0 +1,127 @@
+@@ -0,0 +1,125 @@
+/**
+ * \file cipher_internal.h
+ *
@@ -220640,21 +289232,19 @@ index 0000000..9f2858a
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -220760,10 +289350,10 @@ index 0000000..9f2858a
+#endif /* MBEDTLS_CIPHER_WRAP_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/config.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/config.h
new file mode 100644
-index 0000000..35747ca
+index 0000000..7746371
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/config.h
-@@ -0,0 +1,3312 @@
+@@ -0,0 +1,3310 @@
+/**
+ * \file config.h
+ *
@@ -220775,21 +289365,19 @@ index 0000000..35747ca
+ */
+/*
+ * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -223868,7 +292456,7 @@ index 0000000..35747ca
+ *
+ * \param cond The expression that should evaluate to true, but doesn't.
+ */
-+//#define MBEDTLS_PARAM_FAILED( cond )
++//#define MBEDTLS_PARAM_FAILED( cond ) assert( cond )
+
+/* SSL Cache options */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */
@@ -224078,10 +292666,10 @@ index 0000000..35747ca
+#define MBEDTLS_RSA_NO_CRT
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/des.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/des.h
new file mode 100644
-index 0000000..ae7a58b
+index 0000000..25f9b15
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/des.h
-@@ -0,0 +1,358 @@
+@@ -0,0 +1,356 @@
+/**
+ * \file des.h
+ *
@@ -224093,21 +292681,19 @@ index 0000000..ae7a58b
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ *
@@ -224442,10 +293028,10 @@ index 0000000..ae7a58b
+#endif /* des.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/error.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/error.h
new file mode 100644
-index 0000000..146a1fb
+index 0000000..647a11a
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/error.h
-@@ -0,0 +1,125 @@
+@@ -0,0 +1,123 @@
+/**
+ * \file error.h
+ *
@@ -224453,21 +293039,19 @@ index 0000000..146a1fb
+ */
+/*
+ * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -224573,10 +293157,10 @@ index 0000000..146a1fb
+#endif /* error.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/gcm.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/gcm.h
new file mode 100644
-index 0000000..8313ec1
+index 0000000..0ce45db
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/gcm.h
-@@ -0,0 +1,321 @@
+@@ -0,0 +1,319 @@
+/**
+ * \file gcm.h
+ *
@@ -224592,21 +293176,19 @@ index 0000000..8313ec1
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -224900,10 +293482,10 @@ index 0000000..8313ec1
+#endif /* gcm.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/md.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/md.h
new file mode 100644
-index 0000000..cdf164a
+index 0000000..3cfa594
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/md.h
-@@ -0,0 +1,466 @@
+@@ -0,0 +1,464 @@
+ /**
+ * \file md.h
+ *
@@ -224913,21 +293495,19 @@ index 0000000..cdf164a
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -225372,10 +293952,10 @@ index 0000000..cdf164a
+#endif /* MBEDTLS_MD_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/md_internal.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/md_internal.h
new file mode 100644
-index 0000000..b917cf3
+index 0000000..04de482
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/md_internal.h
-@@ -0,0 +1,117 @@
+@@ -0,0 +1,115 @@
+/**
+ * \file md_internal.h
+ *
@@ -225387,21 +293967,19 @@ index 0000000..b917cf3
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -225495,10 +294073,10 @@ index 0000000..b917cf3
+#endif /* MBEDTLS_MD_WRAP_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/oid.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/oid.h
new file mode 100644
-index 0000000..1ea4a3f
+index 0000000..6fbd018
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/oid.h
-@@ -0,0 +1,607 @@
+@@ -0,0 +1,605 @@
+/**
+ * \file oid.h
+ *
@@ -225506,21 +294084,19 @@ index 0000000..1ea4a3f
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -226108,10 +294684,10 @@ index 0000000..1ea4a3f
+#endif /* oid.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/pk.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/pk.h
new file mode 100644
-index 0000000..898a399
+index 0000000..91950f9
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/pk.h
-@@ -0,0 +1,749 @@
+@@ -0,0 +1,747 @@
+/**
+ * \file pk.h
+ *
@@ -226119,21 +294695,19 @@ index 0000000..898a399
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -226863,10 +295437,10 @@ index 0000000..898a399
+#endif /* MBEDTLS_PK_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/pkcs5.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/pkcs5.h
new file mode 100644
-index 0000000..ffd729f
+index 0000000..d4bb36d
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/pkcs5.h
-@@ -0,0 +1,101 @@
+@@ -0,0 +1,99 @@
+/**
+ * \file pkcs5.h
+ *
@@ -226876,21 +295450,19 @@ index 0000000..ffd729f
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -226970,10 +295542,10 @@ index 0000000..ffd729f
+#endif /* pkcs5.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/platform.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/platform.h
new file mode 100644
-index 0000000..10c3fb9
+index 0000000..a92057d
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/platform.h
-@@ -0,0 +1,406 @@
+@@ -0,0 +1,404 @@
+/**
+ * \file platform.h
+ *
@@ -226990,21 +295562,19 @@ index 0000000..10c3fb9
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -227033,20 +295603,20 @@ index 0000000..10c3fb9
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
-+typedef unsigned long long uint64_t;
++//typedef unsigned long long uint64_t;
+typedef signed char int8_t;
+typedef short int16_t;
+typedef int int32_t;
-+typedef long long int64_t;
++//typedef long long int64_t;
+
+typedef int8_t int_least8_t;
+typedef int16_t int_least16_t;
+typedef int32_t int_least32_t;
-+typedef int64_t int_least64_t;
++//typedef int64_t int_least64_t;
+typedef uint8_t uint_least8_t;
+typedef uint16_t uint_least16_t;
+typedef uint32_t uint_least32_t;
-+typedef uint64_t uint_least64_t;
++//typedef uint64_t uint_least64_t;
+
+#ifndef __HuaweiLite__
+typedef int8_t int_fast8_t;
@@ -227062,8 +295632,8 @@ index 0000000..10c3fb9
+typedef unsigned long uintptr_t;
+#endif
+
-+typedef long long intmax_t;
-+typedef unsigned long long uintmax_t;
++//typedef long long intmax_t;
++//typedef unsigned long long uintmax_t;
+
+/**
+ * \name SECTION: Module settings
@@ -227382,10 +295952,10 @@ index 0000000..10c3fb9
+#endif /* platform.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/platform_util.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/platform_util.h
new file mode 100644
-index 0000000..58b4630
+index 0000000..b0e72ad
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/platform_util.h
-@@ -0,0 +1,187 @@
+@@ -0,0 +1,185 @@
+/**
+ * \file platform_util.h
+ *
@@ -227394,21 +295964,19 @@ index 0000000..58b4630
+ */
+/*
+ * Copyright (C) 2018, Arm Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -227575,10 +296143,10 @@ index 0000000..58b4630
+#endif /* MBEDTLS_PLATFORM_UTIL_H */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/rsa.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/rsa.h
new file mode 100644
-index 0000000..e3adba2
+index 0000000..862f7f1
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/rsa.h
-@@ -0,0 +1,1269 @@
+@@ -0,0 +1,1267 @@
+/**
+ * \file rsa.h
+ *
@@ -227592,21 +296160,19 @@ index 0000000..e3adba2
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -228850,10 +297416,10 @@ index 0000000..e3adba2
+#endif /* rsa.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/rsa_internal.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/rsa_internal.h
new file mode 100644
-index 0000000..8ee0bfe
+index 0000000..53abd3c
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/rsa_internal.h
-@@ -0,0 +1,228 @@
+@@ -0,0 +1,226 @@
+/**
+ * \file rsa_internal.h
+ *
@@ -228892,21 +297458,19 @@ index 0000000..8ee0bfe
+ */
+/*
+ * Copyright (C) 2006-2017, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ *
@@ -229084,10 +297648,10 @@ index 0000000..8ee0bfe
+#endif /* rsa_internal.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha1.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha1.h
new file mode 100644
-index 0000000..f0fad25
+index 0000000..d6b23f1
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha1.h
-@@ -0,0 +1,351 @@
+@@ -0,0 +1,349 @@
+/**
+ * \file sha1.h
+ *
@@ -229102,21 +297666,19 @@ index 0000000..f0fad25
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -229441,10 +298003,10 @@ index 0000000..f0fad25
+#endif /* mbedtls_sha1.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha256.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha256.h
new file mode 100644
-index 0000000..6b44685
+index 0000000..f10201d
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha256.h
-@@ -0,0 +1,296 @@
+@@ -0,0 +1,294 @@
+/**
+ * \file sha256.h
+ *
@@ -229455,21 +298017,19 @@ index 0000000..6b44685
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -229743,10 +298303,10 @@ index 0000000..6b44685
+#endif /* mbedtls_sha256.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha512.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha512.h
new file mode 100644
-index 0000000..c308e99
+index 0000000..979b9c5
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/sha512.h
-@@ -0,0 +1,298 @@
+@@ -0,0 +1,296 @@
+/**
+ * \file sha512.h
+ * \brief This file contains SHA-384 and SHA-512 definitions and functions.
@@ -229756,21 +298316,19 @@ index 0000000..c308e99
+ */
+/*
+ * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -230047,10 +298605,10 @@ index 0000000..c308e99
+#endif /* mbedtls_sha512.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/version.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/version.h
new file mode 100644
-index 0000000..d84be51
+index 0000000..56e7398
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/include/mbedtls/version.h
-@@ -0,0 +1,114 @@
+@@ -0,0 +1,112 @@
+/**
+ * \file version.h
+ *
@@ -230058,21 +298616,19 @@ index 0000000..d84be51
+ */
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -230167,29 +298723,27 @@ index 0000000..d84be51
+#endif /* version.h */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/aes.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/aes.c
new file mode 100644
-index 0000000..11407bb
+index 0000000..ec65c29
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/aes.c
-@@ -0,0 +1,2207 @@
+@@ -0,0 +1,2205 @@
+/*
+ * FIPS-197 compliant AES implementation
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -232380,29 +300934,27 @@ index 0000000..11407bb
+#endif /* MBEDTLS_AES_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/asn1parse.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/asn1parse.c
new file mode 100644
-index 0000000..52267f0
+index 0000000..4cabb40
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/asn1parse.c
-@@ -0,0 +1,401 @@
+@@ -0,0 +1,399 @@
+/*
+ * Generic ASN.1 parsing
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -232787,29 +301339,27 @@ index 0000000..52267f0
+#endif /* MBEDTLS_ASN1_PARSE_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/bignum.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/bignum.c
new file mode 100644
-index 0000000..12f5088
+index 0000000..e81c3c6
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/bignum.c
-@@ -0,0 +1,2672 @@
+@@ -0,0 +1,2670 @@
+/*
+ * Multi-precision integer library
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -235465,29 +304015,27 @@ index 0000000..12f5088
+#endif /* MBEDTLS_BIGNUM_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/ccm.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/ccm.c
new file mode 100644
-index 0000000..a763c94
+index 0000000..6c02d06
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/ccm.c
-@@ -0,0 +1,551 @@
+@@ -0,0 +1,549 @@
+/*
+ * NIST SP800-38C compliant CCM implementation
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -236022,10 +304570,10 @@ index 0000000..a763c94
+#endif /* MBEDTLS_CCM_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/cipher.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/cipher.c
new file mode 100644
-index 0000000..99c5b66
+index 0000000..757785a
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/cipher.c
-@@ -0,0 +1,1163 @@
+@@ -0,0 +1,1161 @@
+/**
+ * \file cipher.c
+ *
@@ -236034,21 +304582,19 @@ index 0000000..99c5b66
+ * \author Adriaan de Jong <dejong@fox-it.com>
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -237191,10 +305737,10 @@ index 0000000..99c5b66
+#endif /* MBEDTLS_CIPHER_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/cipher_wrap.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/cipher_wrap.c
new file mode 100644
-index 0000000..d6f6768
+index 0000000..6dd8c5d
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/cipher_wrap.c
-@@ -0,0 +1,2274 @@
+@@ -0,0 +1,2272 @@
+/**
+ * \file cipher_wrap.c
+ *
@@ -237203,21 +305749,19 @@ index 0000000..d6f6768
+ * \author Adriaan de Jong <dejong@fox-it.com>
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -239471,29 +308015,27 @@ index 0000000..d6f6768
+#endif /* MBEDTLS_CIPHER_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/des.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/des.c
new file mode 100644
-index 0000000..ccc6145
+index 0000000..a2338da
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/des.c
-@@ -0,0 +1,1057 @@
+@@ -0,0 +1,1055 @@
+/*
+ * FIPS-46-3 compliant Triple-DES implementation
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -240534,29 +309076,27 @@ index 0000000..ccc6145
+#endif /* MBEDTLS_DES_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/error.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/error.c
new file mode 100644
-index 0000000..72beb19
+index 0000000..12312a0
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/error.c
-@@ -0,0 +1,918 @@
+@@ -0,0 +1,916 @@
+/*
+ * Error message information
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -241458,29 +309998,27 @@ index 0000000..72beb19
+#endif /* MBEDTLS_ERROR_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/gcm.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/gcm.c
new file mode 100644
-index 0000000..0267dbd
+index 0000000..ae45bc1
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/gcm.c
-@@ -0,0 +1,994 @@
+@@ -0,0 +1,992 @@
+/*
+ * NIST SP800-38D compliant GCM implementation
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -242458,10 +310996,10 @@ index 0000000..0267dbd
+#endif /* MBEDTLS_GCM_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/md.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/md.c
new file mode 100644
-index 0000000..ac53aaf
+index 0000000..773343d
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/md.c
-@@ -0,0 +1,478 @@
+@@ -0,0 +1,476 @@
+/**
+ * \file mbedtls_md.c
+ *
@@ -242470,21 +311008,19 @@ index 0000000..ac53aaf
+ * \author Adriaan de Jong <dejong@fox-it.com>
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -242942,10 +311478,10 @@ index 0000000..ac53aaf
+#endif /* MBEDTLS_MD_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/md_wrap.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/md_wrap.c
new file mode 100644
-index 0000000..97067b0
+index 0000000..32f0871
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/md_wrap.c
-@@ -0,0 +1,588 @@
+@@ -0,0 +1,586 @@
+/**
+ * \file md_wrap.c
+ *
@@ -242954,21 +311490,19 @@ index 0000000..97067b0
+ * \author Adriaan de Jong <dejong@fox-it.com>
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -243536,31 +312070,29 @@ index 0000000..97067b0
+#endif /* MBEDTLS_MD_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/oid.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/oid.c
new file mode 100644
-index 0000000..f03e5b0
+index 0000000..b4c7d28
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/oid.c
-@@ -0,0 +1,752 @@
+@@ -0,0 +1,750 @@
+/**
+ * \file oid.c
+ *
+ * \brief Object Identifier (OID) database
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -244294,30 +312826,28 @@ index 0000000..f03e5b0
+#endif /* MBEDTLS_OID_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/platform_util.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/platform_util.c
new file mode 100644
-index 0000000..a93a086
+index 0000000..4b8d431
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/platform_util.c
-@@ -0,0 +1,140 @@
+@@ -0,0 +1,138 @@
+/*
+ * Common and shared functions used by multiple modules in the Mbed TLS
+ * library.
+ *
+ * Copyright (C) 2018, Arm Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of Mbed TLS (https://tls.mbed.org)
+ */
@@ -244440,29 +312970,27 @@ index 0000000..a93a086
+#endif /* MBEDTLS_HAVE_TIME_DATE && MBEDTLS_PLATFORM_GMTIME_R_ALT */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/rsa.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/rsa.c
new file mode 100644
-index 0000000..07a061c
+index 0000000..a2cb74d
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/rsa.c
-@@ -0,0 +1,2883 @@
+@@ -0,0 +1,2879 @@
+/*
+ * The RSA public-key cryptosystem
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -245677,7 +314205,7 @@ index 0000000..07a061c
+ MBEDTLS_MPI_CHK(kapi_hash_start( &hashid, hisi_type, NULL, 0 ));
+ MBEDTLS_MPI_CHK(kapi_hash_update( hashid, src, slen, HASH_CHUNCK_SRC_LOCAL ));
+ MBEDTLS_MPI_CHK(kapi_hash_update( hashid, counter, 4, HASH_CHUNCK_SRC_LOCAL ));
-+ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, mask, &hisi_hlen ));
++ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, mask, sizeof(mask), &hisi_hlen ));
+
+ for( i = 0; i < use_len; ++i )
+ *p++ ^= mask[i];
@@ -245747,7 +314275,7 @@ index 0000000..07a061c
+ /* Construct DB */
+ MBEDTLS_MPI_CHK(kapi_hash_start( &hashid, hisi_type, NULL, 0 ));
+ MBEDTLS_MPI_CHK(kapi_hash_update( hashid, (hi_u8 *)label, label_len, HASH_CHUNCK_SRC_LOCAL));
-+ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, p, &hisi_hlen));
++ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, p, hlen, &hisi_hlen));
+
+ p += hlen;
+ p += olen - 2 * hlen - 2 - ilen;
@@ -245984,7 +314512,7 @@ index 0000000..07a061c
+ /* Generate lHash */
+ MBEDTLS_MPI_CHK(kapi_hash_start( &hashid, hisi_type, NULL, 0 ));
+ MBEDTLS_MPI_CHK(kapi_hash_update( hashid, (hi_u8 *)label, label_len, HASH_CHUNCK_SRC_LOCAL ));
-+ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, lhash, &hisi_hlen ));
++ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, lhash, MBEDTLS_MD_MAX_SIZE, &hisi_hlen ));
+
+ /*
+ * Check contents, in "constant-time"
@@ -246445,7 +314973,7 @@ index 0000000..07a061c
+ MBEDTLS_MPI_CHK(kapi_hash_update( hashid, p, 8, HASH_CHUNCK_SRC_LOCAL ));
+ MBEDTLS_MPI_CHK(kapi_hash_update( hashid, (hi_u8 *)hash, hashlen, HASH_CHUNCK_SRC_LOCAL ));
+ MBEDTLS_MPI_CHK(kapi_hash_update( hashid, salt, slen, HASH_CHUNCK_SRC_LOCAL ));
-+ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, p, &hisi_hlen ));
++ MBEDTLS_MPI_CHK(kapi_hash_finish( hashid, p, hlen, &hisi_hlen ));
+ mbedtls_platform_zeroize( salt, sizeof( salt ) );
+
+ /* Compensate for boundary condition when applying mask */
@@ -246847,7 +315375,7 @@ index 0000000..07a061c
+ ret = kapi_hash_update( hashid, p, observed_salt_len, HASH_CHUNCK_SRC_LOCAL );
+ if ( ret != 0 )
+ goto exit;
-+ ret = kapi_hash_finish( hashid, result, &hisi_hlen );
++ ret = kapi_hash_finish( hashid, result, MBEDTLS_MD_MAX_SIZE, &hisi_hlen );
+ if ( ret != 0 )
+ goto exit;
+
@@ -247102,13 +315630,11 @@ index 0000000..07a061c
+ mbedtls_mpi_free( &ctx->E );
+ mbedtls_mpi_free( &ctx->N );
+
-+#if !defined(MBEDTLS_RSA_NO_CRT)
+ mbedtls_mpi_free( &ctx->RQ );
+ mbedtls_mpi_free( &ctx->RP );
+ mbedtls_mpi_free( &ctx->QP );
+ mbedtls_mpi_free( &ctx->DQ );
+ mbedtls_mpi_free( &ctx->DP );
-+#endif /* MBEDTLS_RSA_NO_CRT */
+
+#if defined(MBEDTLS_THREADING_C)
+ mbedtls_mutex_free( &ctx->mutex );
@@ -247329,29 +315855,27 @@ index 0000000..07a061c
+#endif /* MBEDTLS_RSA_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/rsa_internal.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/rsa_internal.c
new file mode 100644
-index 0000000..3304e5e
+index 0000000..0422c75
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/rsa_internal.c
-@@ -0,0 +1,496 @@
+@@ -0,0 +1,494 @@
+/*
+ * Helper functions for the RSA module
+ *
+ * Copyright (C) 2006-2017, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ *
@@ -247831,29 +316355,27 @@ index 0000000..3304e5e
+#endif /* MBEDTLS_RSA_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha1.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha1.c
new file mode 100644
-index 0000000..61269a7
+index 0000000..f15cc45
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha1.c
-@@ -0,0 +1,571 @@
+@@ -0,0 +1,569 @@
+/*
+ * FIPS-180-1 compliant SHA-1 implementation
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -248408,29 +316930,27 @@ index 0000000..61269a7
+#endif /* MBEDTLS_SHA1_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha256.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha256.c
new file mode 100644
-index 0000000..94eb238
+index 0000000..006f484
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha256.c
-@@ -0,0 +1,585 @@
+@@ -0,0 +1,583 @@
+/*
+ * FIPS-180-2 compliant SHA-256 implementation
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -248999,29 +317519,27 @@ index 0000000..94eb238
+#endif /* MBEDTLS_SHA256_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha512.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha512.c
new file mode 100644
-index 0000000..9e827e3
+index 0000000..91c380d
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/extend/mbedtls/sha512.c
-@@ -0,0 +1,636 @@
+@@ -0,0 +1,634 @@
+/*
+ * FIPS-180-2 compliant SHA-384/512 implementation
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
-+ * SPDX-License-Identifier: GPL-2.0
++ * SPDX-License-Identifier: Apache-2.0
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * Licensed under the Apache License, Version 2.0 (the "License"); you may
++ * not use this file except in compliance with the License.
++ * You may obtain a copy of the License at
+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * http://www.apache.org/licenses/LICENSE-2.0
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ * Unless required by applicable law or agreed to in writing, software
++ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
++ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++ * See the License for the specific language governing permissions and
++ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
@@ -249641,44 +318159,30 @@ index 0000000..9e827e3
+#endif /* MBEDTLS_SHA512_C */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_dispatch.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_dispatch.c
new file mode 100644
-index 0000000..5f87b35
+index 0000000..63ffa7e
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_dispatch.c
-@@ -0,0 +1,817 @@
+@@ -0,0 +1,868 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for kapi dispatch of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
-+#include "drv_osal_lib.h"
-+#include "cryp_symc.h"
-+#include "ext_alg.h"
++#include "hi_cipher_compat.h"
+#include "hi_drv_compat.h"
++#include "cryp_symc.h"
+
-+/*************************** Internal Structure Definition *******************/
++/* max pakage numher of symc mutli encrypt */
++#define SYMC_MULTI_MAX_PKG 0x1000
+
-+/* ! \max pakage numher of symc mutli encrypt */
-+#define SYMC_MULTI_MAX_PKG (0x1000)
++#define RSA_PUBLIC_BUFFER_NUM 0x03
++#define RSA_PRIVATE_BUFFER_NUM 0x07
+
-+#define RSA_PUBLIC_BUFFER_NUM (0x03)
-+#define RSA_PRIVATE_BUFFER_NUM (0x07)
++#define MAX_CENC_SUB_SAMPLE 100
+
-+#define MAX_CENC_SUB_SAMPLE (100)
-+
-+typedef hi_s32 (*hi_drv_func)(void *param);
++typedef hi_s32 (*hi_drv_func)(hi_void *param);
+
+typedef struct {
+ const char *name;
@@ -249686,243 +318190,209 @@ index 0000000..5f87b35
+ hi_u32 cmd;
+} crypto_dispatch_func;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++typedef struct {
++ hi_u8 *buf;
++ hi_u32 buf_size;
++ hi_u32 offset;
++} kapi_rsa_buf;
+
-+/******************************* API Code *****************************/
-+/** \addtogroup link*/
-+/** @{*/ /** <!-- [link]*/
-+
-+static hi_s32 dispatch_symc_create_handle(void *argp)
++/* ****************************** API Code **************************** */
++static hi_s32 dispatch_symc_create_handle(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ symc_create_t *symc_create = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* allocate a aes channel */
+ ret = kapi_symc_create(&symc_create->id);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_create, ret);
++ hi_log_print_func_err(kapi_symc_create, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_symc_destroy_handle(void *argp)
++static hi_s32 dispatch_symc_destroy_handle(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ symc_destroy_t *destroy = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ret = kapi_symc_destroy(destroy->id);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_destroy, ret);
++ hi_log_print_func_err(kapi_symc_destroy, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_symc_config(void *argp)
++static hi_s32 dispatch_symc_cfg(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ symc_config_t *config = argp;
++ hi_s32 ret;
++ symc_cfg_t *cfg = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = kapi_symc_config(config->id,
-+ config->hard_key,
-+ config->alg,
-+ config->mode,
-+ config->width,
-+ config->klen,
-+ config->sm1_round_num,
-+ (hi_u8 *)config->fkey,
-+ (hi_u8 *)config->skey,
-+ (hi_u8 *)config->iv,
-+ config->ivlen,
-+ config->iv_usage,
-+ config->aad,
-+ config->alen,
-+ config->tlen);
++ ret = kapi_symc_cfg(cfg);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_config, ret);
++ hi_log_print_func_err(kapi_symc_cfg, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_symc_encrypt(void *argp)
++static hi_s32 dispatch_symc_encrypt(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ symc_encrypt_t *encrypt = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if ((encrypt->operation == SYMC_OPERATION_ENCRYPT)
-+ || (encrypt->operation == SYMC_OPERATION_DECRYPT)) {
-+ ret = cipher_check_mmz_phy_addr(ADDR_U64(encrypt->input), encrypt->length);
++ if ((encrypt->operation == SYMC_OPERATION_ENCRYPT) || (encrypt->operation == SYMC_OPERATION_DECRYPT)) {
++ ret = cipher_check_mmz_phy_addr(addr_u64(encrypt->in), encrypt->len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Invalid input mmz phy addr for crypt.\n");
-+ HI_LOG_PRINT_FUNC_ERR(cipher_check_mmz_phy_addr, ret);
++ hi_log_print_func_err(cipher_check_mmz_phy_addr, ret);
+ return ret;
+ }
+
-+ ret = cipher_check_mmz_phy_addr(ADDR_U64(encrypt->output), encrypt->length);
++ ret = cipher_check_mmz_phy_addr(addr_u64(encrypt->out), encrypt->len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Invalid output mmz phy addr for crypt.\n");
-+ HI_LOG_PRINT_FUNC_ERR(cipher_check_mmz_phy_addr, ret);
++ hi_log_print_func_err(cipher_check_mmz_phy_addr, ret);
+ return ret;
+ }
+
-+ ret = kapi_symc_crypto(encrypt->id,
-+ encrypt->input,
-+ encrypt->output,
-+ encrypt->length,
-+ encrypt->operation,
-+ encrypt->last);
++ ret = kapi_symc_crypto(encrypt);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_crypto, ret);
++ hi_log_print_func_err(kapi_symc_crypto, ret);
+ return ret;
+ }
-+ } else if ((encrypt->operation == SYMC_OPERATION_ENCRYPT_VIA)
-+ || (encrypt->operation == SYMC_OPERATION_DECRYPT_VIA)) {
-+ ret = kapi_symc_crypto_via(encrypt->id,
-+ encrypt->input,
-+ encrypt->output,
-+ encrypt->length,
-+ encrypt->operation,
-+ encrypt->last,
-+ HI_TRUE);
++ } else if ((encrypt->operation == SYMC_OPERATION_ENCRYPT_VIA) ||
++ (encrypt->operation == SYMC_OPERATION_DECRYPT_VIA)) {
++ ret = kapi_symc_crypto_via(encrypt, HI_TRUE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_crypto_via, ret);
++ hi_log_print_func_err(kapi_symc_crypto_via, ret);
+ return ret;
+ }
+ } else {
-+ HI_LOG_ERROR("encrypt operation(0x%x) is unsupported.\n", encrypt->operation);
++ hi_log_error("encrypt operation(0x%x) is unsupported.\n", encrypt->operation);
+ return HI_ERR_CIPHER_UNSUPPORTED;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_symc_encrypt_multi(void *argp)
++static hi_s32 dispatch_symc_encrypt_multi(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ symc_encrypt_multi_t *encrypt_mutli = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_DEBUG("operation %d\n", encrypt_mutli->operation);
-+ ret = kapi_symc_crypto_multi(encrypt_mutli->id,
-+ ADDR_VIA(encrypt_mutli->pkg),
-+ encrypt_mutli->pkg_num,
-+ encrypt_mutli->operation,
-+ HI_TRUE);
++ hi_log_debug("operation %d\n", encrypt_mutli->operation);
++ ret = kapi_symc_crypto_multi(encrypt_mutli->id, addr_via(encrypt_mutli->pack), encrypt_mutli->pack_num,
++ encrypt_mutli->operation, HI_TRUE);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_crypto_multi, ret);
++ hi_log_print_func_err(kapi_symc_crypto_multi, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_symc_get_tag(void *argp)
++static hi_s32 dispatch_symc_get_tag(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ aead_tag_t *aead_tag = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = kapi_aead_get_tag(aead_tag->id,
-+ aead_tag->tag,
-+ &aead_tag->taglen);
++ ret = kapi_aead_get_tag(aead_tag->id, aead_tag->tag, &aead_tag->taglen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_aead_get_tag, ret);
++ hi_log_print_func_err(kapi_aead_get_tag, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_symc_get_config(void *argp)
++static hi_s32 dispatch_symc_get_cfg(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ symc_get_config_t *get_config = argp;
++ hi_s32 ret;
++ symc_get_cfg_t *get_cfg = argp;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ ret = kapi_symc_get_config(get_config->id, &get_config->ctrl);
++ hi_log_func_enter();
+
++ ret = kapi_symc_get_cfg(get_cfg->id, &get_cfg->ctrl);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_get_config, ret);
++ hi_log_print_func_err(kapi_symc_get_cfg, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_klad_key(void *argp)
++static hi_s32 dispatch_klad_key(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ klad_key_t *klad = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = klad_encrypt_key(klad->keysel, klad->target, klad->clear, klad->encrypt);
++ ret = klad_encrypt_key(klad->keysel, klad->target, klad->clear, klad->encrypt, sizeof(klad->clear));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(klad_encrypt_key, ret);
++ hi_log_print_func_err(klad_encrypt_key, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_hash_start(void *argp)
++static hi_s32 dispatch_hash_start(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hash_start_t *start = argp;
+ hi_u8 *key = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
-+ HI_LOG_CHECK_PARAM(start->type >= HI_CIPHER_HASH_TYPE_BUTT);
++ hi_log_func_enter();
++ hi_log_chk_param_return(start->type >= HI_CIPHER_HASH_TYPE_BUTT);
+
+ if (start->type == HI_CIPHER_HASH_TYPE_SM3) {
-+ HI_LOG_ERROR("Sm3 is unsupported.\n");
++ hi_log_error("Sm3 is unsupported.\n");
+ return HI_ERR_CIPHER_UNSUPPORTED;
+ }
+
-+ if (start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA1
-+ || start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA224
-+ || start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA256
-+ || start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA384
-+ || start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA512) {
-+
-+ HI_LOG_CHECK_PARAM(start->keylen > MAX_MALLOC_BUF_SIZE);
-+ HI_LOG_CHECK_PARAM(ADDR_VIA(start->key) == HI_NULL);
++ if (start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA1 ||
++ start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA224 ||
++ start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA256 ||
++ start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA384 ||
++ start->type == HI_CIPHER_HASH_TYPE_HMAC_SHA512) {
++ hi_log_chk_param_return(start->keylen > MAX_MALLOC_BUF_SIZE);
++ hi_log_chk_param_return(addr_via(start->key) == HI_NULL);
+
+ key = (hi_u8 *)crypto_calloc(1, start->keylen);
+ if (key == HI_NULL) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_calloc, ret);
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_print_func_err(crypto_calloc, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ CHECK_EXIT(crypto_copy_from_user(key, ADDR_VIA(start->key), start->keylen));
++ crypto_chk_err_exit(crypto_copy_from_user(key, addr_via(start->key), start->keylen));
+ }
+
-+ CHECK_EXIT(kapi_hash_start(&start->id, start->type, key, start->keylen));
++ crypto_chk_err_exit(kapi_hash_start(&start->id, start->type, key, start->keylen));
+
+ if (key != HI_NULL) {
+ crypto_zeroize(key, start->keylen);
@@ -249930,7 +318400,7 @@ index 0000000..5f87b35
+ key = HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+
+exit__:
@@ -249943,172 +318413,268 @@ index 0000000..5f87b35
+ return ret;
+}
+
-+static hi_s32 dispatch_hash_update(void *argp)
++static hi_s32 dispatch_hash_update(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hash_update_t *update = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ADDR_VIA(update->input) == HI_NULL);
++ hi_log_chk_param_return(addr_via(update->input) == HI_NULL);
+
+ update->src = HASH_CHUNCK_SRC_USER;
-+ ret = kapi_hash_update(update->id,
-+ ADDR_VIA(update->input),
-+ update->length,
-+ update->src);
++ ret = kapi_hash_update(update->id, addr_via(update->input), update->length, update->src);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_update, ret);
++ hi_log_print_func_err(kapi_hash_update, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_hash_finish(void *argp)
++static hi_s32 dispatch_hash_finish(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hash_finish_t *finish = argp;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = kapi_hash_finish(finish->id, (hi_u8 *)finish->hash, &finish->hashlen);
++ ret = kapi_hash_finish(finish->id, (hi_u8 *)finish->hash, sizeof(finish->hash), &finish->hashlen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_finish, ret);
++ hi_log_print_func_err(kapi_hash_finish, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 rsa_alloc_buffer(cryp_rsa_key *key, rsa_info_t *rsa_info,
-+ hi_u8 **in, hi_u8 **out)
++static hi_s32 rsa_buf_chk_info_param(rsa_info_t *rsa_info)
+{
-+ hi_u32 size = 0, klen = 0;
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u8 *buf = HI_NULL;
-+
-+ HI_LOG_FUNC_ENTER();
-+
++ hi_log_chk_param_return(rsa_info == HI_NULL);
+ if (rsa_info->public == HI_FALSE) {
-+ HI_LOG_CHECK_PARAM((ADDR_VIA(rsa_info->d) == HI_NULL)
-+ && ((ADDR_VIA(rsa_info->p) == HI_NULL)
-+ || (ADDR_VIA(rsa_info->q) == HI_NULL)
-+ || (ADDR_VIA(rsa_info->dp) == HI_NULL)
-+ || (ADDR_VIA(rsa_info->dq) == HI_NULL)
-+ || (ADDR_VIA(rsa_info->qp) == HI_NULL)));
++ hi_log_chk_param_return((addr_via(rsa_info->d) == HI_NULL) &&
++ ((addr_via(rsa_info->p) == HI_NULL) ||
++ (addr_via(rsa_info->q) == HI_NULL) ||
++ (addr_via(rsa_info->dp) == HI_NULL) ||
++ (addr_via(rsa_info->dq) == HI_NULL) ||
++ (addr_via(rsa_info->qp) == HI_NULL)));
+ }
+
-+ HI_LOG_CHECK_PARAM(rsa_info->inlen > rsa_info->klen);
-+ HI_LOG_CHECK_PARAM(rsa_info->outlen > rsa_info->klen);
-+ HI_LOG_CHECK_PARAM(rsa_info->klen < RSA_KEY_BITWIDTH_1024);
-+ HI_LOG_CHECK_PARAM(rsa_info->klen > RSA_KEY_BITWIDTH_4096);
++ hi_log_chk_param_return(rsa_info->inlen > rsa_info->klen);
++ hi_log_chk_param_return(rsa_info->klen < RSA_KEY_BITWIDTH_1024);
++ hi_log_chk_param_return(rsa_info->klen > RSA_KEY_BITWIDTH_4096);
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 rsa_pub_alloc(cryp_rsa_key *key, rsa_info_t *rsa_info, hi_u8 **in, hi_u8 **out)
++{
++ hi_s32 ret;
++ hi_u32 size;
++ hi_u8 *buf = HI_NULL;
++ hi_u32 klen = rsa_info->klen;
++
++ hi_log_chk_param_return(key->ca_type != HI_CIPHER_KEY_SRC_USER);
++
++ /* buffer size of key, input and output */
++ size = rsa_info->klen * RSA_PUBLIC_BUFFER_NUM;
++ buf = crypto_calloc(1, size);
++ if (buf == HI_NULL) {
++ hi_log_print_func_err(crypto_calloc, HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
++ }
++
++ key->n = buf;
++ buf += klen;
++ *in = buf;
++ buf += klen;
++ *out = buf;
++ buf += klen;
++ key->bufsize = size;
++
++ crypto_chk_err_exit(crypto_copy_from_user(key->n, addr_via(rsa_info->n), klen));
++ crypto_chk_err_exit(crypto_copy_from_user(*in, addr_via(rsa_info->in), klen));
++ key->e = rsa_info->e;
++
++ return HI_SUCCESS;
++
++exit__:
++ if (key->n != HI_NULL) {
++ crypto_zeroize(key->n, key->bufsize);
++ crypto_free(key->n);
++ key->n = HI_NULL;
++ }
++
++ hi_log_error("error, copy rsa key from user failed\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
++}
++
++static hi_void rsa_private_set_key_param(cryp_rsa_key *key, kapi_rsa_buf *rsa_buf, hi_u32 klen, hi_u32 e)
++{
++ hi_u8 *ptr = rsa_buf->buf;
++
++ key->n = ptr;
++ ptr += klen;
++ rsa_buf->offset += klen;
++
++ key->d = ptr;
++ ptr += klen;
++ rsa_buf->offset += klen;
++
++ key->p = ptr;
++ ptr += klen / MUL_VAL_2;
++ rsa_buf->offset += klen / MUL_VAL_2;
++
++ key->q = ptr;
++ ptr += klen / MUL_VAL_2;
++ rsa_buf->offset += klen / MUL_VAL_2;
++
++ key->dp = ptr;
++ ptr += klen / MUL_VAL_2;
++ rsa_buf->offset += klen / MUL_VAL_2;
++
++ key->dq = ptr;
++ ptr += klen / MUL_VAL_2;
++ rsa_buf->offset += klen / MUL_VAL_2;
++
++ key->qp = ptr;
++ ptr += klen / MUL_VAL_2;
++ rsa_buf->offset += klen / MUL_VAL_2;
++
++ key->e = e;
++ key->bufsize = rsa_buf->buf_size;
++}
++
++static hi_s32 rsa_private_get_cfg(cryp_rsa_key *key, rsa_info_t *rsa_info, hi_u8 **in, hi_u8 **out, hi_u8 *buf)
++{
++ hi_s32 ret;
++ hi_u8 *ptr = buf;
++ hi_u32 klen = rsa_info->klen;
++
++ if (addr_via(rsa_info->n) != HI_NULL) {
++ /* invalid user n, n is even number. */
++ crypto_chk_err_exit(crypto_copy_from_user(key->n, addr_via(rsa_info->n), klen));
++ if ((key->ca_type == HI_CIPHER_KEY_SRC_USER) && ((key->n[klen - BOUND_VAL_1] & CRYPTO_NUM_1) == 0)) {
++ hi_log_error("invalid n, n is even number.\n");
++ goto exit__;
++ }
++ }
++
++ if (addr_via(rsa_info->d) != HI_NULL) {
++ crypto_chk_err_exit(crypto_copy_from_user(key->d, addr_via(rsa_info->d), klen));
++ } else {
++ crypto_chk_err_exit(crypto_copy_from_user(key->p, addr_via(rsa_info->p), klen / MUL_VAL_2));
++ crypto_chk_err_exit(crypto_copy_from_user(key->q, addr_via(rsa_info->q), klen / MUL_VAL_2));
++ crypto_chk_err_exit(crypto_copy_from_user(key->dp, addr_via(rsa_info->dp), klen / MUL_VAL_2));
++ crypto_chk_err_exit(crypto_copy_from_user(key->dq, addr_via(rsa_info->dq), klen / MUL_VAL_2));
++ crypto_chk_err_exit(crypto_copy_from_user(key->qp, addr_via(rsa_info->qp), klen / MUL_VAL_2));
++ key->d = HI_NULL;
++ }
++
++ *in = ptr;
++ ptr += klen;
++ *out = ptr;
++ ptr += klen;
++
++ if (addr_via(rsa_info->in) != HI_NULL) {
++ crypto_chk_err_exit(crypto_copy_from_user(*in, addr_via(rsa_info->in), rsa_info->inlen));
++ }
++
++ return HI_SUCCESS;
++exit__:
++ return ret;
++}
++
++static hi_s32 rsa_private_alloc(cryp_rsa_key *key, rsa_info_t *rsa_info, hi_u8 **in, hi_u8 **out)
++{
++ hi_s32 ret;
++ hi_u32 size;
++ hi_u8 *ptr = HI_NULL;
++ hi_u8 *buf = HI_NULL;
++ hi_u32 klen = rsa_info->klen;
++ kapi_rsa_buf rsa_buf;
++
++ /* n + d or n + p + q + dP + dQ + qp
++ * the length of n/d is klen,
++ * the length of p/q/dP/dQ/qp is klen/2,
++ * the length of input is klen
++ * the length of output is klen
++ */
++ hi_log_chk_param_return(key->ca_type > HI_CIPHER_KEY_SRC_BUTT);
++ crypto_memset(&rsa_buf, sizeof(rsa_buf), 0, sizeof(rsa_buf));
++
++ size = klen * RSA_PRIVATE_BUFFER_NUM;
++ buf = crypto_calloc(MUL_VAL_1, size);
++ if (buf == HI_NULL) {
++ hi_log_print_func_err(crypto_calloc, HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
++ }
++ ptr = buf;
++
++ rsa_buf.buf = buf;
++ rsa_buf.buf_size = size;
++ rsa_private_set_key_param(key, &rsa_buf, klen, rsa_info->e);
++
++ ptr += rsa_buf.offset; /* set buf for in and out */
++ crypto_chk_err_exit(rsa_private_get_cfg(key, rsa_info, in, out, ptr));
++ return HI_SUCCESS;
++
++exit__:
++ if (buf != HI_NULL) {
++ crypto_zeroize(buf, size);
++ crypto_free(buf);
++ buf = HI_NULL;
++ }
++
++ hi_log_error("error, copy rsa key from user failed\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
++}
++
++static hi_s32 rsa_alloc_buffer(cryp_rsa_key *key, rsa_info_t *rsa_info, hi_u8 **in, hi_u8 **out)
++{
++ hi_s32 ret;
++ hi_u32 klen;
++
++ hi_log_func_enter();
++
++ ret = rsa_buf_chk_info_param(rsa_info);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_buf_chk_info_param, ret);
++ return ret;
++ }
+
+ crypto_memset(key, sizeof(cryp_rsa_key), 0, sizeof(cryp_rsa_key));
+
-+ key->klen = klen = rsa_info->klen;
++ klen = rsa_info->klen;
++ key->klen = klen;
+ key->public = rsa_info->public;
+ key->ca_type = rsa_info->ca_type;
+
+ if (rsa_info->public) {
-+ HI_LOG_CHECK_PARAM(key->ca_type != HI_CIPHER_KEY_SRC_USER);
-+
-+ /* buffer size of key, input and output */
-+ size = rsa_info->klen * RSA_PUBLIC_BUFFER_NUM;
-+
-+ buf = crypto_calloc(1, size);
-+ if (buf == HI_NULL) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_calloc, ret);
-+ return HI_ERR_CIPHER_FAILED_MEM;
++ ret = rsa_pub_alloc(key, rsa_info, in, out);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_pub_alloc, ret);
++ return ret;
+ }
-+
-+ key->n = buf;
-+ buf += klen;
-+ *in = buf;
-+ buf += klen;
-+ *out = buf;
-+ buf += klen;
-+ key->bufsize = size;
-+
-+ CHECK_EXIT(crypto_copy_from_user(key->n, ADDR_VIA(rsa_info->n), klen));
-+ CHECK_EXIT(crypto_copy_from_user(*in, ADDR_VIA(rsa_info->in), klen));
-+ key->e = rsa_info->e;
+ } else {
-+ /* n + d or n + p + q + dP + dQ + qp
-+ * the length of n/d is klen,
-+ * the length of p/q/dP/dQ/qp is klen/2,
-+ * the length of input is klen
-+ * the length of output is klen
-+ */
-+ size = klen * RSA_PRIVATE_BUFFER_NUM;
-+
-+ buf = crypto_calloc(1, size);
-+ HI_LOG_CHECK_PARAM(buf == HI_NULL);
-+
-+ key->n = buf;
-+ buf += klen;
-+ key->d = buf;
-+ buf += klen;
-+ key->p = buf;
-+ buf += klen / 2;
-+ key->q = buf;
-+ buf += klen / 2;
-+ key->dp = buf;
-+ buf += klen / 2;
-+ key->dq = buf;
-+ buf += klen / 2;
-+ key->qp = buf;
-+ buf += klen / 2;
-+ key->e = rsa_info->e;
-+ key->bufsize = size;
-+
-+ if (ADDR_VIA(rsa_info->n) != HI_NULL) {
-+ CHECK_EXIT(crypto_copy_from_user(key->n, ADDR_VIA(rsa_info->n), klen));
-+ }
-+
-+ if (ADDR_VIA(rsa_info->d) != HI_NULL) {
-+ CHECK_EXIT(crypto_copy_from_user(key->d, ADDR_VIA(rsa_info->d), klen));
-+ } else {
-+ CHECK_EXIT(crypto_copy_from_user(key->p, ADDR_VIA(rsa_info->p), klen / 2));
-+ CHECK_EXIT(crypto_copy_from_user(key->q, ADDR_VIA(rsa_info->q), klen / 2));
-+ CHECK_EXIT(crypto_copy_from_user(key->dp, ADDR_VIA(rsa_info->dp), klen / 2));
-+ CHECK_EXIT(crypto_copy_from_user(key->dq, ADDR_VIA(rsa_info->dq), klen / 2));
-+ CHECK_EXIT(crypto_copy_from_user(key->qp, ADDR_VIA(rsa_info->qp), klen / 2));
-+ key->d = HI_NULL;
-+ }
-+
-+ *in = buf;
-+ buf += klen;
-+ *out = buf;
-+ buf += klen;
-+
-+ if (ADDR_VIA(rsa_info->in) != HI_NULL) {
-+ CHECK_EXIT(crypto_copy_from_user(*in, ADDR_VIA(rsa_info->in), rsa_info->inlen));
++ ret = rsa_private_alloc(key, rsa_info, in, out);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(rsa_private_alloc, ret);
++ return ret;
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
-+
-+exit__:
-+ if (key->n != HI_NULL) {
-+ crypto_zeroize(key->n, key->bufsize);
-+ crypto_free(key->n);
-+ key->n = HI_NULL;
-+ }
-+
-+ HI_LOG_ERROR("error, copy rsa key from user failed\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_FAILED_MEM);
-+
-+ return HI_ERR_CIPHER_FAILED_MEM;
+}
+
-+static void rsa_free_buffer(cryp_rsa_key *key)
++static hi_void rsa_free_buffer(cryp_rsa_key *key)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ if (key->n != HI_NULL) {
+ crypto_zeroize(key->n, key->bufsize);
@@ -250116,187 +318682,194 @@ index 0000000..5f87b35
+ key->n = HI_NULL;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return;
+}
+
-+static hi_s32 dispatch_rsa_encrypt(void *argp)
++static hi_s32 dispatch_rsa_encrypt(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ rsa_info_t *rsa_info = argp;
-+ hi_u8 *in = HI_NULL;
-+ hi_u8 *out = HI_NULL;
+ cryp_rsa_key key;
++ cryp_rsa_crypt_data rsa;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
++ crypto_memset(&rsa, sizeof(rsa), 0, sizeof(rsa));
+ crypto_memset(&key, sizeof(cryp_rsa_key), 0, sizeof(cryp_rsa_key));
+
-+ ret = rsa_alloc_buffer(&key, rsa_info, &in, &out);
++ ret = rsa_alloc_buffer(&key, rsa_info, &rsa.in, &rsa.out);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa_alloc_key failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(rsa_alloc_buffer, ret);
++ hi_log_print_func_err(rsa_alloc_buffer, ret);
+ return ret;
+ }
++ rsa.in_len = rsa_info->inlen;
++ rsa.out_len = rsa_info->outlen;
++ rsa.scheme = rsa_info->scheme;
+
-+ ret = kapi_rsa_encrypt(&key, rsa_info->scheme, in, rsa_info->inlen,
-+ out, &rsa_info->outlen);
++ ret = kapi_rsa_encrypt(&key, &rsa);
+ if (ret != HI_SUCCESS) {
+ rsa_free_buffer(&key);
-+ HI_LOG_PRINT_FUNC_ERR(kapi_rsa_encrypt, ret);
++ hi_log_print_func_err(kapi_rsa_encrypt, ret);
+ return ret;
+ }
+
-+ ret = crypto_copy_to_user(ADDR_VIA(rsa_info->out), out, rsa_info->outlen);
++ ret = crypto_copy_to_user(addr_via(rsa_info->out), rsa.out, rsa.out_len);
+ if (ret != HI_SUCCESS) {
+ rsa_free_buffer(&key);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_copy_to_user, ret);
++ hi_log_print_func_err(crypto_copy_to_user, ret);
+ return ret;
+ }
+
++ rsa_info->outlen = rsa.out_len;
+ rsa_free_buffer(&key);
-+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_rsa_decrypt(void *argp)
++static hi_s32 dispatch_rsa_decrypt(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ rsa_info_t *rsa_info = argp;
-+ hi_u8 *in = HI_NULL;
-+ hi_u8 *out = HI_NULL;
+ cryp_rsa_key key;
++ cryp_rsa_crypt_data rsa;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
++ crypto_memset(&rsa, sizeof(rsa), 0, sizeof(rsa));
+ crypto_memset(&key, sizeof(cryp_rsa_key), 0, sizeof(cryp_rsa_key));
+
-+ ret = rsa_alloc_buffer(&key, rsa_info, &in, &out);
++ ret = rsa_alloc_buffer(&key, rsa_info, &rsa.in, &rsa.out);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa_alloc_key failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(rsa_alloc_buffer, ret);
++ hi_log_print_func_err(rsa_alloc_buffer, ret);
+ return ret;
+ }
++ rsa.in_len = rsa_info->inlen;
++ rsa.out_len = rsa_info->outlen;
++ rsa.scheme = rsa_info->scheme;
+
-+ ret = kapi_rsa_decrypt(&key, rsa_info->scheme,
-+ in, rsa_info->inlen, out, &rsa_info->outlen);
++ ret = kapi_rsa_decrypt(&key, &rsa);
+ if (ret != HI_SUCCESS) {
+ rsa_free_buffer(&key);
-+ HI_LOG_PRINT_FUNC_ERR(kapi_rsa_decrypt, ret);
++ hi_log_print_func_err(kapi_rsa_decrypt, ret);
+ return ret;
+ }
+
-+ ret = crypto_copy_to_user(ADDR_VIA(rsa_info->out), out, rsa_info->outlen);
++ ret = crypto_copy_to_user(addr_via(rsa_info->out), rsa.out, rsa.out_len);
+ if (ret != HI_SUCCESS) {
+ rsa_free_buffer(&key);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_copy_to_user, ret);
++ hi_log_print_func_err(crypto_copy_to_user, ret);
+ return ret;
+ }
+
++ rsa_info->outlen = rsa.out_len;
+ rsa_free_buffer(&key);
-+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_rsa_sign_hash(void *argp)
++static hi_s32 dispatch_rsa_sign_hash(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ rsa_info_t *rsa_info = argp;
-+ hi_u8 *in = HI_NULL;
-+ hi_u8 *out = HI_NULL;
+ cryp_rsa_key key;
++ cryp_rsa_sign_data rsa;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
++ crypto_memset(&rsa, sizeof(rsa), 0, sizeof(rsa));
+ crypto_memset(&key, sizeof(cryp_rsa_key), 0, sizeof(cryp_rsa_key));
+
-+ ret = rsa_alloc_buffer(&key, rsa_info, &in, &out);
++ ret = rsa_alloc_buffer(&key, rsa_info, &rsa.in, &rsa.out);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa alloc key buffer failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(rsa_alloc_buffer, ret);
++ hi_log_print_func_err(rsa_alloc_buffer, ret);
+ return ret;
+ }
++ rsa.in_len = rsa_info->inlen;
++ rsa.out_len = rsa_info->outlen;
++ rsa.scheme = rsa_info->scheme;
+
-+ ret = kapi_rsa_sign_hash(&key, rsa_info->scheme, in,
-+ rsa_info->inlen, out, &rsa_info->outlen);
++ ret = kapi_rsa_sign_hash(&key, &rsa);
+ if (ret != HI_SUCCESS) {
+ rsa_free_buffer(&key);
-+ HI_LOG_PRINT_FUNC_ERR(kapi_rsa_sign_hash, ret);
++ hi_log_print_func_err(kapi_rsa_sign_hash, ret);
+ return ret;
+ }
+
-+ ret = crypto_copy_to_user(ADDR_VIA(rsa_info->out), out, rsa_info->outlen);
++ ret = crypto_copy_to_user(addr_via(rsa_info->out), rsa.out, rsa.out_len);
+ if (ret != HI_SUCCESS) {
+ rsa_free_buffer(&key);
-+ HI_LOG_PRINT_FUNC_ERR(crypto_copy_to_user, ret);
++ hi_log_print_func_err(crypto_copy_to_user, ret);
+ return ret;
+ }
+
++ rsa_info->outlen = rsa.out_len;
+ rsa_free_buffer(&key);
-+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 dispatch_rsa_verify_hash(void *argp)
++static hi_s32 dispatch_rsa_verify_hash(hi_void *argp)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ rsa_info_t *rsa_info = argp;
-+ hi_u8 *in = HI_NULL;
-+ hi_u8 *out = HI_NULL;
+ cryp_rsa_key key;
++ cryp_rsa_sign_data rsa;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
++ crypto_memset(&rsa, sizeof(rsa), 0, sizeof(rsa));
+ crypto_memset(&key, sizeof(cryp_rsa_key), 0, sizeof(cryp_rsa_key));
+
-+ ret = rsa_alloc_buffer(&key, rsa_info, &in, &out);
++ ret = rsa_alloc_buffer(&key, rsa_info, &rsa.in, &rsa.out);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, rsa_alloc_key failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(rsa_alloc_buffer, ret);
++ hi_log_print_func_err(rsa_alloc_buffer, ret);
+ return ret;
+ }
++ rsa.in_len = rsa_info->inlen;
++ rsa.out_len = rsa_info->outlen;
++ rsa.scheme = rsa_info->scheme;
+
+ /* copy hash value from user */
-+ CHECK_EXIT(crypto_copy_from_user(out, ADDR_VIA(rsa_info->out), rsa_info->outlen));
-+ CHECK_EXIT(kapi_rsa_verify_hash(&key,
-+ rsa_info->scheme,
-+ out,
-+ rsa_info->outlen,
-+ in,
-+ rsa_info->inlen));
++ ret = crypto_copy_from_user(rsa.out, addr_via(rsa_info->out), rsa_info->outlen);
++ if (ret != HI_SUCCESS) {
++ rsa_free_buffer(&key);
++ hi_log_print_func_err(crypto_copy_from_user, ret);
++ return ret;
++ }
++
++ ret = kapi_rsa_verify_hash(&key, &rsa);
++ if (ret != HI_SUCCESS) {
++ rsa_free_buffer(&key);
++ hi_log_print_func_err(kapi_rsa_verify_hash, ret);
++ return ret;
++ }
++
+ rsa_free_buffer(&key);
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
-+
-+exit__:
-+ rsa_free_buffer(&key);
-+
-+ return ret;
+}
+
-+static hi_s32 dispatch_trng_get_random(void *argp)
++static hi_s32 dispatch_trng_get_random(hi_void *argp)
+{
+ trng_t *trng = argp;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ret = kapi_trng_get_random(&trng->randnum, trng->timeout);
+ if (ret != HI_SUCCESS) {
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static crypto_dispatch_func dispatch_func[CRYPTO_CMD_COUNT] = {
++static crypto_dispatch_func g_dispatch_func[CRYPTO_CMD_COUNT] = {
+ {"CreateHandle", dispatch_symc_create_handle, CRYPTO_CMD_SYMC_CREATEHANDLE},
+ {"DestroyHandle", dispatch_symc_destroy_handle, CRYPTO_CMD_SYMC_DESTROYHANDLE},
-+ {"ConfigChn", dispatch_symc_config, CRYPTO_CMD_SYMC_CONFIGHANDLE},
++ {"ConfigChn", dispatch_symc_cfg, CRYPTO_CMD_SYMC_CONFIGHANDLE},
+ {"Encrypt", dispatch_symc_encrypt, CRYPTO_CMD_SYMC_ENCRYPT},
+ {"EncryptMulti", dispatch_symc_encrypt_multi, CRYPTO_CMD_SYMC_ENCRYPTMULTI},
+ {"GetTag", dispatch_symc_get_tag, CRYPTO_CMD_SYMC_GETTAG},
@@ -250308,83 +318881,83 @@ index 0000000..5f87b35
+ {"RsaSign", dispatch_rsa_sign_hash, CRYPTO_CMD_RSA_SIGN},
+ {"RsaVerify", dispatch_rsa_verify_hash, CRYPTO_CMD_RSA_VERIFY},
+ {"TRNG", dispatch_trng_get_random, CRYPTO_CMD_TRNG},
-+ {"GetSymcConfig", dispatch_symc_get_config, CRYPTO_CMD_SYMC_GET_CONFIG},
++ {"GetSymcConfig", dispatch_symc_get_cfg, CRYPTO_CMD_SYMC_GET_CONFIG},
+ {"KladKey", dispatch_klad_key, CRYPTO_CMD_KLAD_KEY},
+};
+
+hi_s32 crypto_ioctl(hi_u32 cmd, hi_void *argp)
+{
-+ hi_u32 nr = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_u32 nr;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ nr = CRYPTO_IOC_NR (cmd);
-+ HI_LOG_CHECK_PARAM(argp == HI_NULL);
-+ HI_LOG_CHECK_PARAM(nr >= CRYPTO_CMD_COUNT);
-+ HI_LOG_CHECK_PARAM(cmd != dispatch_func[nr].cmd);
++ nr = crypto_ioc_nr(cmd);
++ hi_log_chk_param_return(argp == HI_NULL);
++ hi_log_chk_param_return(nr >= CRYPTO_CMD_COUNT);
++ hi_log_chk_param_return(cmd != g_dispatch_func[nr].cmd);
+
-+ HI_LOG_DEBUG("cmd 0x%x, nr %d, size %d, local cmd 0x%x\n",
-+ cmd, nr, CRYPTO_IOC_SIZE(cmd), dispatch_func[nr].cmd);
++ hi_log_debug("cmd 0x%x, nr %d, size %d, local cmd 0x%x\n",
++ cmd, nr, crypto_ioc_size(cmd), g_dispatch_func[nr].cmd);
+
-+ HI_LOG_INFO("Link Func NR %d, Name: %s\n", nr, dispatch_func[nr].name);
-+ ret = dispatch_func[nr].func(argp);
++ hi_log_info("Link Func NR %d, Name: %s\n", nr, g_dispatch_func[nr].name);
++ ret = g_dispatch_func[nr].func(argp);
+ if (ret != HI_SUCCESS) {
-+ /*TRNG may be empty in FIFO, don't report error, try to read it again */
++ /* TRNG may be empty in FIFO, don't report error, try to read it again */
+ if (cmd != CRYPTO_CMD_TRNG) {
-+ HI_LOG_ERROR("error, call dispatch_fun fun failed!\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_dispatch_func, ret);
++ hi_log_error("error, call dispatch_fun fun failed!\n");
++ hi_log_print_func_err(crypto_dispatch_func, ret);
+ }
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 crypto_entry(void)
++hi_s32 crypto_entry(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ crypto_mem_init();
+
+ ret = module_addr_map();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("module addr map failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(module_addr_map, ret);
++ hi_log_error("module addr map failed\n");
++ hi_log_print_func_err(module_addr_map, ret);
+ return ret;
+ }
+
+ ret = kapi_symc_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("kapi symc init failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_init, ret);
++ hi_log_error("kapi symc init failed\n");
++ hi_log_print_func_err(kapi_symc_init, ret);
+ goto error;
+ }
+
+ ret = kapi_hash_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("kapi hash init failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_init, ret);
++ hi_log_error("kapi hash init failed\n");
++ hi_log_print_func_err(kapi_hash_init, ret);
+ goto error1;
+ }
+
+ ret = kapi_rsa_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("kapi rsa init failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(kapi_rsa_init, ret);
++ hi_log_error("kapi rsa init failed\n");
++ hi_log_print_func_err(kapi_rsa_init, ret);
+ goto error2;
+ }
+
+ ret = hi_drv_compat_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(hi_drv_compat_init, ret);
++ hi_log_print_func_err(hi_drv_compat_init, ret);
+ goto error3;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+
+error3:
@@ -250397,348 +318970,312 @@ index 0000000..5f87b35
+ module_addr_unmap();
+
+ return ret;
-+
+}
+
-+hi_s32 crypto_exit(void)
++hi_s32 crypto_exit(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ret = kapi_symc_deinit();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_deinit, ret);
++ hi_log_print_func_err(kapi_symc_deinit, ret);
+ return ret;
+ }
+
+ ret = kapi_hash_deinit();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_deinit, ret);
++ hi_log_print_func_err(kapi_hash_deinit, ret);
+ return ret;
+ }
+
+ ret = kapi_rsa_deinit();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_rsa_deinit, ret);
++ hi_log_print_func_err(kapi_rsa_deinit, ret);
+ return ret;
+ }
+
+ ret = hi_drv_compat_deinit();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(hi_drv_compat_deinit, ret);
++ hi_log_print_func_err(hi_drv_compat_deinit, ret);
+ return ret;
+ }
+
+ ret = module_addr_unmap();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(module_addr_unmap, ret);
++ hi_log_print_func_err(module_addr_unmap, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+
-+hi_s32 crypto_release(void)
++hi_s32 crypto_release(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
+ ret = kapi_symc_release();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_release, ret);
++ hi_log_print_func_err(kapi_symc_release, ret);
+ return ret;
+ }
+
+ ret = kapi_hash_release();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_release, ret);
++ hi_log_print_func_err(kapi_hash_release, ret);
+ return ret;
+ }
+
+ return HI_SUCCESS;
+}
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_hash.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_hash.c
new file mode 100644
-index 0000000..47d7d57
+index 0000000..b12e713
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_hash.c
-@@ -0,0 +1,638 @@
+@@ -0,0 +1,624 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
++ * Description : drv for kapi hash.
++ * Author : Hisilicon multimedia software group
++ * Create : 2018-10-23
+ */
+
-+#include "drv_osal_lib.h"
+#include "cryp_hash.h"
-+#include "ext_alg.h"
++#include "drv_osal_lib.h"
+
+#ifdef MHASH_NONSUPPORT
-+#define HASH_SOFT_CHANNEL_MAX (0x01)
-+#define HASH_SOFT_CHANNEL_MASK (0x01)
++#define HASH_SOFT_CHANNEL_MAX 0x01
++#define HASH_SOFT_CHANNEL_MASK 0x01
+#else
-+#define HASH_SOFT_CHANNEL_MAX (0x08)
-+#define HASH_SOFT_CHANNEL_MASK (0xFF)
++#define HASH_SOFT_CHANNEL_MAX 0x08
++#define HASH_SOFT_CHANNEL_MASK 0xFF
+#endif
+
-+/*! /hmac ipad byte */
-+#define HMAC_IPAD_BYTE (0x36)
++/* hmac ipad byte */
++#define HMAC_IPAD_BYTE 0x36
+
-+/*! /hmac opad byte */
-+#define HMAC_OPAD_BYTE (0x5C)
++/* hmac opad byte */
++#define HMAC_OPAD_BYTE 0x5C
+
-+#define HMAC_HASH (0x01)
-+#define HMAC_AESCBC (0x02)
++#define HMAC_HASH 0x01
++#define HMAC_AESCBC 0x02
+
+typedef struct {
-+ hash_func *func; /*!< HASH function */
-+ void *cryp_ctx; /*!< Context of cryp instance */
-+ hi_u32 hmac; /*!< HMAC or not */
-+ hi_u32 mac_id; /*!< CMAC handle */
-+ hi_u8 hmac_ipad[HASH_BLOCK_SIZE_128]; /*!< hmac ipad */
-+ hi_u8 hmac_opad[HASH_BLOCK_SIZE_128]; /*!< hmac opad */
-+ crypto_owner owner; /*!< user ID */
++ hash_func *func; /* HASH function */
++ hi_void *cryp_ctx; /* Context of cryp instance */
++ hi_u32 hmac; /* HMAC or not */
++ hi_u32 mac_id; /* CMAC handle */
++ hi_u8 hmac_ipad[HASH_BLOCK_SIZE_128]; /* hmac ipad */
++ hi_u8 hmac_opad[HASH_BLOCK_SIZE_128]; /* hmac opad */
++ crypto_owner owner; /* user ID */
+} kapi_hash_ctx;
+
-+/*! Context of cipher */
-+static channel_context hash_ctx[HASH_SOFT_CHANNEL_MAX];
++/* Context of cipher */
++static channel_context g_hash_ctx[HASH_SOFT_CHANNEL_MAX];
+
-+/*! hash mutex */
-+static crypto_mutex hash_mutex;
++/* hash mutex */
++static crypto_mutex g_hash_mutex;
+
-+#define kapi_check_hash_handle(handle) \
-+ do \
-+ { \
-+ if((HI_HANDLE_GET_MODID(handle) != HI_ID_CIPHER) \
-+ || (HI_HANDLE_GET_PriDATA(handle) != 0)) \
-+ { \
-+ HI_LOG_ERROR("invalid handle 0x%x!\n", handle); \
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA); \
-+ return HI_ERR_CIPHER_INVALID_HANDLE; \
-+ } \
-+ if (HI_HANDLE_GET_CHNID(handle) >= HASH_SOFT_CHANNEL_MAX) \
-+ { \
-+ HI_LOG_ERROR("chan %d is too large, max: %d\n", HI_HANDLE_GET_CHNID(handle), HASH_SOFT_CHANNEL_MAX); \
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA); \
-+ return HI_ERR_CIPHER_INVALID_HANDLE; \
-+ } \
-+ if (hash_ctx[HI_HANDLE_GET_CHNID(handle)].open == HI_FALSE) \
-+ { \
-+ HI_LOG_ERROR("chan %d is not open\n", HI_HANDLE_GET_CHNID(handle)); \
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA); \
-+ return HI_ERR_CIPHER_INVALID_HANDLE; \
++#define kapi_hash_lock_err_return() \
++ do { \
++ ret = crypto_mutex_lock(&g_hash_mutex); \
++ if (ret != HI_SUCCESS) { \
++ hi_log_error("error, hash lock failed\n"); \
++ hi_log_print_err_code(HI_ERR_CIPHER_BUSY); \
++ return HI_ERR_CIPHER_BUSY; \
+ } \
+ } while (0)
+
-+#define KAPI_HASH_LOCK() \
-+ ret = crypto_mutex_lock(&hash_mutex); \
-+ if (ret != HI_SUCCESS) \
-+ {\
-+ HI_LOG_ERROR("error, hash lock failed\n");\
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_BUSY); \
-+ return HI_ERR_CIPHER_BUSY;\
++#define kapi_hash_unlock() crypto_mutex_unlock(&g_hash_mutex)
++
++static hi_s32 kapi_hash_chk_handle(hi_handle handle)
++{
++ if((hi_handle_get_modid(handle) != HI_ID_CIPHER) || (hi_handle_get_private_data(handle) != 0)) { \
++ hi_log_error("invalid handle 0x%x!\n", handle);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_HANDLE);
++ return HI_ERR_CIPHER_INVALID_HANDLE;
+ }
+
-+#define KAPI_HASH_UNLOCK() crypto_mutex_unlock(&hash_mutex)
++ if (hi_handle_get_chnid(handle) >= HASH_SOFT_CHANNEL_MAX) {
++ hi_log_error("chan %d is too large, max: %d\n", hi_handle_get_chnid(handle), HASH_SOFT_CHANNEL_MAX);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_HANDLE);
++ return HI_ERR_CIPHER_INVALID_HANDLE;
++ }
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++ if (g_hash_ctx[hi_handle_get_chnid(handle)].open == HI_FALSE) {
++ hi_log_error("chan %d is not open\n", hi_handle_get_chnid(handle));
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_HANDLE);
++ return HI_ERR_CIPHER_INVALID_HANDLE;
++ }
+
-+/******************************* API Code *****************************/
-+/** \addtogroup hash */
-+/** @{*/ /** <!-- [kapi]*/
++ return HI_SUCCESS;
++}
+
-+hi_s32 kapi_hash_init(void)
++/* API Code for kapi hash. */
++hi_s32 kapi_hash_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_INFO("HASH init\n");
++ hi_log_info("HASH init\n");
+
-+ crypto_mutex_init(&hash_mutex);
++ crypto_mutex_init(&g_hash_mutex);
+
+ ret = cryp_hash_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, cryp_hash_init failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_hash_init, ret);
++ hi_log_error("error, cryp_hash_init failed\n");
++ hi_log_print_func_err(cryp_hash_init, ret);
+ return ret;
+ }
+
+ /* Initialize soft channel list */
-+ ret = crypto_channel_init(hash_ctx, HASH_SOFT_CHANNEL_MAX, sizeof(kapi_hash_ctx));
++ ret = crypto_channel_init(g_hash_ctx, HASH_SOFT_CHANNEL_MAX, sizeof(kapi_hash_ctx));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, hash channel list init failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_init, ret);
++ hi_log_error("error, hash channel list init failed\n");
++ hi_log_print_func_err(crypto_channel_init, ret);
+ cryp_hash_deinit();
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_hash_deinit(void)
++hi_s32 kapi_hash_deinit(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = crypto_channel_deinit(hash_ctx, HASH_SOFT_CHANNEL_MAX);
++ ret = crypto_channel_deinit(g_hash_ctx, HASH_SOFT_CHANNEL_MAX);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, hash channel list deinit failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_deinit, ret);
++ hi_log_error("error, hash channel list deinit failed\n");
++ hi_log_print_func_err(crypto_channel_deinit, ret);
+ return ret;
+ }
+
+ cryp_hash_deinit();
+
-+ crypto_mutex_destroy(&hash_mutex);
++ crypto_mutex_destroy(&g_hash_mutex);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static kapi_hash_ctx *kapi_hash_get_ctx(hi_u32 id)
+{
-+ return crypto_channel_get_context(hash_ctx, HASH_SOFT_CHANNEL_MAX, id);
++ return crypto_channel_get_context(g_hash_ctx, HASH_SOFT_CHANNEL_MAX, id);
+}
+
+static hi_s32 kapi_hash_create(hi_u32 *id)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 chn = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* allocate a hash channel */
-+ ret = crypto_channel_alloc(hash_ctx, HASH_SOFT_CHANNEL_MAX, HASH_SOFT_CHANNEL_MASK, &chn);
++ ret = crypto_channel_alloc(g_hash_ctx, HASH_SOFT_CHANNEL_MAX, HASH_SOFT_CHANNEL_MASK, &chn);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, allocate hash channel failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_channel_alloc, ret);
++ hi_log_error("error, allocate hash channel failed\n");
++ hi_log_print_func_err(crypto_channel_alloc, ret);
+ return ret;
+ }
+
+ *id = chn;
+
-+ HI_LOG_DEBUG("kapi create soft chn %d\n", chn);
++ hi_log_debug("kapi create soft chn %d\n", chn);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static hi_s32 kapi_hash_destroy(hi_u32 id)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(HASH_SOFT_CHANNEL_MAX <= id);
++ hi_log_chk_param_return(id >= HASH_SOFT_CHANNEL_MAX);
+
+ /* Free soft channel */
-+ crypto_channel_free(hash_ctx, HASH_SOFT_CHANNEL_MAX, id);
++ crypto_channel_free(g_hash_ctx, HASH_SOFT_CHANNEL_MAX, id);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 kpai_hash_mode_transform(hi_cipher_hash_type type,
-+ hash_mode *mode, hi_u32 *hmac)
++static hi_s32 kpai_hash_mode_transform(hi_cipher_hash_type type, hash_mode *mode, hi_u32 *hmac)
+{
+ *hmac = HI_FALSE;
+
+ /* transform hash mode */
+ switch (type) {
-+ case HI_CIPHER_HASH_TYPE_HMAC_SHA1: {
++ case HI_CIPHER_HASH_TYPE_HMAC_SHA1:
+ *hmac = HMAC_HASH;
+ *mode = HASH_MODE_SHA1;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_SHA1: {
++ case HI_CIPHER_HASH_TYPE_SHA1:
+ *mode = HASH_MODE_SHA1;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_HMAC_SHA224: {
++ case HI_CIPHER_HASH_TYPE_HMAC_SHA224:
+ *hmac = HMAC_HASH;
+ *mode = HASH_MODE_SHA224;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_SHA224: {
++ case HI_CIPHER_HASH_TYPE_SHA224:
+ *mode = HASH_MODE_SHA224;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_HMAC_SHA256: {
++ case HI_CIPHER_HASH_TYPE_HMAC_SHA256:
+ *hmac = HMAC_HASH;
+ *mode = HASH_MODE_SHA256;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_SHA256: {
++ case HI_CIPHER_HASH_TYPE_SHA256:
+ *mode = HASH_MODE_SHA256;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_HMAC_SHA384: {
++ case HI_CIPHER_HASH_TYPE_HMAC_SHA384:
+ *hmac = HMAC_HASH;
+ *mode = HASH_MODE_SHA384;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_SHA384: {
++ case HI_CIPHER_HASH_TYPE_SHA384:
+ *mode = HASH_MODE_SHA384;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_HMAC_SHA512: {
++ case HI_CIPHER_HASH_TYPE_HMAC_SHA512:
+ *hmac = HMAC_HASH;
+ *mode = HASH_MODE_SHA512;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_SHA512: {
++ case HI_CIPHER_HASH_TYPE_SHA512:
+ *mode = HASH_MODE_SHA512;
+ break;
-+ }
-+ case HI_CIPHER_HASH_TYPE_SM3: {
++ case HI_CIPHER_HASH_TYPE_SM3:
+ *mode = HASH_MODE_SM3;
+ break;
-+ }
-+ default: {
-+ HI_LOG_ERROR("error, invalid hash type %d\n", type);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
++ default:
++ hi_log_error("error, invalid hash type %d\n", type);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
-+
+ return HI_SUCCESS;
+}
+
+static hi_s32 kapi_hmac_start(kapi_hash_ctx *ctx, hi_u8 *key, hi_u32 keylen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u8 sum[HASH_RESULT_MAX_SIZE] = {0};
+ hi_u32 len = 0;
+ hi_u32 i;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(key == HI_NULL);
++ hi_log_chk_param_return(key == HI_NULL);
+
+ /* clean ipad and opad */
+ crypto_memset(ctx->hmac_ipad, HASH_BLOCK_SIZE_128, 0x00, ctx->func->block_size);
+ crypto_memset(ctx->hmac_opad, HASH_BLOCK_SIZE_128, 0x00, ctx->func->block_size);
+
+ /* compute K0 */
-+
+ if (keylen <= ctx->func->block_size) {
+ /* If the length of K = B: set K0 = K.
+ *
@@ -250753,26 +319290,23 @@ index 0000000..47d7d57
+ * then append (B-L) zeros to create a B-byte
+ * string K0 (i.e., K0 = H(K) || 00...00).
+ */
-+
-+ /* H(K) */
-+ ctx->cryp_ctx = ctx->func->create(ctx->func->mode);
++ ctx->cryp_ctx = ctx->func->create(ctx->func->mode); /* H(K) */
+ if (ctx->cryp_ctx == HI_NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->create, 0);
++ hi_log_print_func_err(ctx->func->create, 0);
+ return HI_ERR_CIPHER_BUSY;
+ }
+
+ /* update key */
-+ CHECK_EXIT(ctx->func->update(ctx->cryp_ctx, key,
-+ keylen, HASH_CHUNCK_SRC_LOCAL));
++ crypto_chk_err_exit(ctx->func->update(ctx->cryp_ctx, key, keylen, HASH_CHUNCK_SRC_LOCAL));
+
+ /* sum */
-+ CHECK_EXIT(ctx->func->finish(ctx->cryp_ctx, sum, &len));
++ crypto_chk_err_exit(ctx->func->finish(ctx->cryp_ctx, sum, sizeof(sum), &len));
+ ctx->func->destroy(ctx->cryp_ctx);
+ ctx->cryp_ctx = HI_NULL;
+
-+ /* K0 = H(K) || 00...00 */
-+ crypto_memcpy(ctx->hmac_ipad, HASH_BLOCK_SIZE_128, sum, len);
-+ crypto_memcpy(ctx->hmac_opad, HASH_BLOCK_SIZE_128, sum, len);
++ /* descript: K0 = H(K) || 00...00. */
++ crypto_memcpy(ctx->hmac_ipad, sizeof(ctx->hmac_ipad), sum, len);
++ crypto_memcpy(ctx->hmac_opad, sizeof(ctx->hmac_opad), sum, len);
+ }
+
+ /* Exclusive-Or K0 with ipad/opad byte to produce K0 ^ ipad and K0 ^ opad */
@@ -250784,13 +319318,12 @@ index 0000000..47d7d57
+ /* H(K0 ^ ipad) */
+ ctx->cryp_ctx = ctx->func->create(ctx->func->mode);
+ if (ctx->cryp_ctx == HI_NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->create, 0);
++ hi_log_print_func_err(ctx->func->create, 0);
+ return HI_ERR_CIPHER_BUSY;
+ }
-+ CHECK_EXIT(ctx->func->update(ctx->cryp_ctx, ctx->hmac_ipad,
-+ ctx->func->block_size, HASH_CHUNCK_SRC_LOCAL));
++ crypto_chk_err_exit(ctx->func->update(ctx->cryp_ctx, ctx->hmac_ipad, ctx->func->block_size, HASH_CHUNCK_SRC_LOCAL));
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+
+exit__:
@@ -250798,480 +319331,461 @@ index 0000000..47d7d57
+ ctx->cryp_ctx = HI_NULL;
+ crypto_memset(ctx->hmac_ipad, sizeof(ctx->hmac_ipad), 0, sizeof(ctx->hmac_ipad));
+ crypto_memset(ctx->hmac_opad, sizeof(ctx->hmac_opad), 0, sizeof(ctx->hmac_opad));
-+
+ return ret;
+}
+
-+static hi_s32 kapi_hmac_finish(kapi_hash_ctx *ctx, hi_u8 *hash, hi_u32 *hashlen)
++static hi_s32 kapi_hmac_finish(kapi_hash_ctx *ctx, hi_u8 *hash, hi_u32 hash_buf_len, hi_u32 *hashlen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u8 sum[HASH_RESULT_MAX_SIZE] = {0};
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ /* sum = H((K0 ^ ipad) || text). */
-+ ctx->func->finish(ctx->cryp_ctx, sum, hashlen);
++ /* descript: sum = H((K0 ^ ipad) || text). */
++ ctx->func->finish(ctx->cryp_ctx, sum, sizeof(sum), hashlen);
+ ctx->func->destroy(ctx->cryp_ctx);
+ ctx->cryp_ctx = HI_NULL;
+
+ /* H((K0 ^ opad)|| sum). */
+ ctx->cryp_ctx = ctx->func->create(ctx->func->mode);
+ if (ctx->cryp_ctx == HI_NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->create, 0);
++ hi_log_print_func_err(ctx->func->create, 0);
+ return HI_ERR_CIPHER_BUSY;
+ }
+
+ /* update(K0 ^ opad) */
-+ ret = ctx->func->update(ctx->cryp_ctx, ctx->hmac_opad,
-+ ctx->func->block_size, HASH_CHUNCK_SRC_LOCAL);
++ ret = ctx->func->update(ctx->cryp_ctx, ctx->hmac_opad, ctx->func->block_size, HASH_CHUNCK_SRC_LOCAL);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->update, ret);
++ hi_log_print_func_err(ctx->func->update, ret);
+ return ret;
+ }
+
+ /* update(sum) */
-+ ret = ctx->func->update(ctx->cryp_ctx, sum,
-+ ctx->func->size, HASH_CHUNCK_SRC_LOCAL);
++ ret = ctx->func->update(ctx->cryp_ctx, sum, ctx->func->size, HASH_CHUNCK_SRC_LOCAL);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->update, ret);
++ hi_log_print_func_err(ctx->func->update, ret);
+ return ret;
+ }
+
+ /* H */
-+ ret = ctx->func->finish(ctx->cryp_ctx, hash, hashlen);
++ ret = ctx->func->finish(ctx->cryp_ctx, hash, hash_buf_len, hashlen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->finish, ret);
++ hi_log_print_func_err(ctx->func->finish, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_hash_start(hi_u32 *id, hi_cipher_hash_type type,
-+ hi_u8 *key, hi_u32 keylen)
++static hi_s32 kapi_hash_finsh_calc(kapi_hash_ctx *ctx, hi_u8 *hash, hi_u32 hash_buf_len, hi_u32 *hashlen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
++
++ if (ctx->hmac) {
++ ret = kapi_hmac_finish(ctx, hash, hash_buf_len, hashlen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hmac_finish, ret);
++ return ret;
++ }
++ } else {
++ ret = ctx->func->finish(ctx->cryp_ctx, hash, hash_buf_len, hashlen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ctx->func->finish, ret);
++ return ret;
++ }
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_hash_chk_ctx(hi_u32 id, hi_u32 *soft_hash_id)
++{
++ hi_s32 ret;
+ kapi_hash_ctx *ctx = HI_NULL;
-+ hash_mode mode = 0x00;
-+ hi_u32 hmac = 0;
-+ hi_u32 soft_hash_id = 0;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ HI_LOG_CHECK_PARAM(id == HI_NULL);
-+
-+ /* transform hash mode */
-+ ret = kpai_hash_mode_transform(type, &mode, &hmac);
++ ret = kapi_hash_chk_handle((hi_handle)id);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kpai_hash_mode_transform, ret);
++ hi_log_print_func_err(kapi_hash_chk_handle, ret);
+ return ret;
+ }
+
-+ KAPI_HASH_LOCK();
-+
-+ /* Create hash channel */
-+ ret = kapi_hash_create(&soft_hash_id);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, kapi_hash_create failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_create, ret);
-+ KAPI_HASH_UNLOCK();
-+ return ret;
-+ }
-+
-+ ctx = kapi_hash_get_ctx(soft_hash_id);
++ *soft_hash_id = hi_handle_get_chnid(id);
++ ctx = kapi_hash_get_ctx(*soft_hash_id);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("error, kapi_hash_get_ctx failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_get_ctx, 0);
-+ ret = HI_ERR_CIPHER_BUSY;
-+ goto error1;
++ hi_log_error("kapi hash get ctx is null.\n");
++ hi_log_print_func_err(kapi_hash_get_ctx, HI_ERR_CIPHER_INVALID_POINT);
++ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
++ crypto_chk_owner_err_return(&ctx->owner);
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_hash_set_ctx(kapi_hash_ctx *ctx, hash_mode mode, hi_u32 hmac)
++{
+ crypto_memset(ctx, sizeof(kapi_hash_ctx), 0, sizeof(kapi_hash_ctx));
+ /* record owner */
+ crypto_get_owner(&ctx->owner);
+ ctx->hmac = hmac;
+
-+ /* Clone the function from template of hash engine*/
++ /* Clone the function from template of hash engine */
+ ctx->cryp_ctx = HI_NULL;
+ ctx->func = cryp_get_hash(mode);
+ if (ctx->func == HI_NULL) {
-+ HI_LOG_ERROR("error, cryp_get_hash failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_get_hash, 0);
-+ ret = HI_ERR_CIPHER_INVALID_PARA;
-+ goto error1;
++ hi_log_print_func_err(cryp_get_hash, HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ if ((ctx->func->create == HI_NULL)
-+ || (ctx->func->update == HI_NULL)
-+ || (ctx->func->finish == HI_NULL)
-+ || (ctx->func->destroy == HI_NULL)) {
-+ HI_LOG_ERROR("error, cryp hash func is HI_NULL\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_UNSUPPORTED);
-+ ret = HI_ERR_CIPHER_UNSUPPORTED;
-+ goto error1;
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_hash_create_calc(kapi_hash_ctx *ctx, hash_mode mode, hi_u32 hmac, hi_u8 *key, hi_u32 keylen)
++{
++ hi_s32 ret;
++
++ ret = kapi_hash_set_ctx(ctx, mode, hmac);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_set_ctx, ret);
++ return ret;
++ }
++
++ if ((ctx->func->create == HI_NULL) || (ctx->func->update == HI_NULL) || (ctx->func->finish == HI_NULL) ||
++ (ctx->func->destroy == HI_NULL)) {
++ hi_log_error("error, cryp hash func is null.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_UNSUPPORTED);
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
+ if (ctx->hmac) {
+ ret = kapi_hmac_start(ctx, key, keylen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, kapi_hmac_start failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hmac_start, ret);
-+ goto error1;
++ hi_log_print_func_err(kapi_hmac_start, ret);
++ return ret;
+ }
+ } else {
+ ctx->cryp_ctx = ctx->func->create(mode);
+ if (ctx->cryp_ctx == HI_NULL) {
-+ HI_LOG_ERROR("error, hash context for hash engine failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->create, 0);
-+ ret = HI_ERR_CIPHER_BUSY;
-+ goto error1;
++ hi_log_print_func_err(ctx->func->create, HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+ }
++ return HI_SUCCESS;
++}
+
-+ *id = HI_HANDLE_MAKEHANDLE(HI_ID_CIPHER, 0, soft_hash_id);
++hi_s32 kapi_hash_start(hi_u32 *id, hi_cipher_hash_type type, hi_u8 *key, hi_u32 keylen)
++{
++ hi_s32 ret, ret_error;
++ kapi_hash_ctx *ctx = HI_NULL;
++ hash_mode mode = 0x00;
++ hi_u32 hmac = 0;
++ hi_u32 soft_hash_id = 0;
+
-+ KAPI_HASH_UNLOCK();
++ hi_log_func_enter();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_chk_param_return(id == HI_NULL);
++
++ /* transform hash mode */
++ ret = kpai_hash_mode_transform(type, &mode, &hmac);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kpai_hash_mode_transform, ret);
++ return ret;
++ }
++
++ kapi_hash_lock_err_return();
++
++ /* Create hash channel */
++ ret = kapi_hash_create(&soft_hash_id);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_create, ret);
++ kapi_hash_unlock();
++ return ret;
++ }
++
++ ctx = kapi_hash_get_ctx(soft_hash_id);
++ if (ctx == HI_NULL) {
++ hi_log_print_func_err(kapi_hash_get_ctx, HI_ERR_CIPHER_FAILED_MEM);
++ ret = HI_ERR_CIPHER_FAILED_MEM;
++ goto error1;
++ }
++
++ ret = kapi_hash_create_calc(ctx, mode, hmac, key, keylen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_create_calc, ret);
++ goto error1;
++ }
++
++ *id = hi_handle_makehandle(HI_ID_CIPHER, 0, soft_hash_id);
++ kapi_hash_unlock();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+
+error1:
-+ kapi_hash_destroy(soft_hash_id);
-+
-+ KAPI_HASH_UNLOCK();
-+
-+ HI_LOG_FUNC_EXIT();
++ ret_error = kapi_hash_destroy(soft_hash_id);
++ if (ret_error != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_destroy, ret_error);
++ }
+
++ kapi_hash_unlock();
++ hi_log_func_exit();
+ return ret;
-+
+}
+
-+hi_s32 kapi_hash_update(hi_u32 id, hi_u8 *input, hi_u32 length,
-+ hash_chunk_src src)
++hi_s32 kapi_hash_update(hi_u32 id, hi_u8 *input, hi_u32 length, hash_chunk_src src)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_hash_ctx *ctx = HI_NULL;
+ hi_u32 soft_hash_id = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ kapi_check_hash_handle(id);
-+ soft_hash_id = HI_HANDLE_GET_CHNID(id);
++ hi_log_chk_param_return(input > input + length); /* check overflow */
++ ret = kapi_hash_chk_ctx((hi_handle)id, &soft_hash_id);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_chk_ctx, ret);
++ return ret;
++ }
+
+ ctx = kapi_hash_get_ctx(soft_hash_id);
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
-+ HI_LOG_CHECK_PARAM(input > input + length); /* check overflow */
++ hi_log_chk_param_return(ctx->func == HI_NULL);
++ hi_log_chk_param_return(ctx->func->update == HI_NULL);
+
-+ CHECK_OWNER(&ctx->owner);
-+
-+ HI_LOG_CHECK_PARAM(ctx->func == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->func->update == HI_NULL);
-+
-+ KAPI_HASH_LOCK();
++ kapi_hash_lock_err_return();
+
+ ret = ctx->func->update(ctx->cryp_ctx, input, length, src);
-+
+ /* release resource */
+ if (ret != HI_SUCCESS) {
+ ctx->func->destroy(ctx->cryp_ctx);
+ ctx->cryp_ctx = HI_NULL;
+ kapi_hash_destroy(soft_hash_id);
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->update, ret);
-+ KAPI_HASH_UNLOCK();
++ hi_log_print_func_err(ctx->func->update, ret);
++ kapi_hash_unlock();
+ return ret;
+ }
+
-+ KAPI_HASH_UNLOCK();
++ kapi_hash_unlock();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_hash_finish(hi_u32 id, hi_u8 *hash, hi_u32 *hashlen)
++hi_s32 kapi_hash_finish(hi_u32 id, hi_u8 *hash, hi_u32 hash_buf_len, hi_u32 *hashlen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_hash_ctx *ctx = HI_NULL;
+ hi_u32 soft_hash_id = 0;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ kapi_check_hash_handle(id);
-+ soft_hash_id = HI_HANDLE_GET_CHNID(id);
++ hi_log_chk_param_return(hash == HI_NULL);
++ hi_log_chk_param_return(hash_buf_len == 0);
++ hi_log_chk_param_return(hashlen == HI_NULL);
+
-+ HI_LOG_CHECK_PARAM(hash == HI_NULL);
-+ HI_LOG_CHECK_PARAM(hashlen == HI_NULL);
-+
-+ ctx = kapi_hash_get_ctx(soft_hash_id);
-+ HI_LOG_CHECK_PARAM(ctx == HI_NULL);
-+
-+ CHECK_OWNER(&ctx->owner);
-+
-+#if defined(HASH_CMAC_SUPPORT)
-+ if (ctx->hmac == HMAC_AESCBC) {
-+ ret = kapi_hash_cbcmac_finish(ctx->mac_id, hash, hashlen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_cbcmac_finish, ret);
-+ kapi_hash_destroy(soft_hash_id);
-+ return ret;
-+ }
-+ kapi_hash_destroy(soft_hash_id);
-+ HI_LOG_FUNC_EXIT();
-+ return HI_SUCCESS;
++ ret = kapi_hash_chk_ctx((hi_handle)id, &soft_hash_id);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_chk_ctx, ret);
++ return ret;
+ }
-+#endif
++ ctx = kapi_hash_get_ctx(soft_hash_id);
+
-+ HI_LOG_CHECK_PARAM(ctx->func == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->func->destroy == HI_NULL);
++ hi_log_chk_param_return(ctx->func == HI_NULL);
++ hi_log_chk_param_return(ctx->func->destroy == HI_NULL);
+
-+ KAPI_HASH_LOCK();
++ kapi_hash_lock_err_return();
+
-+ if (ctx->hmac) {
-+ ret = kapi_hmac_finish(ctx, hash, hashlen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hmac_finish, ret);
-+ ctx->func->destroy(ctx->cryp_ctx);
-+ ctx->cryp_ctx = HI_NULL;
-+ kapi_hash_destroy(soft_hash_id);
-+ KAPI_HASH_UNLOCK();
-+ return ret;
-+ }
-+ } else {
-+ ret = ctx->func->finish(ctx->cryp_ctx, hash, hashlen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->finish, ret);
-+ ctx->func->destroy(ctx->cryp_ctx);
-+ ctx->cryp_ctx = HI_NULL;
-+ kapi_hash_destroy(soft_hash_id);
-+ KAPI_HASH_UNLOCK();
-+ return ret;
-+ }
++ ret = kapi_hash_finsh_calc(ctx, hash, hash_buf_len, hashlen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_finsh_calc, ret);
++ ctx->func->destroy(ctx->cryp_ctx);
++ ctx->cryp_ctx = HI_NULL;
++ (hi_void)kapi_hash_destroy(soft_hash_id);
++ kapi_hash_unlock();
++ return ret;
+ }
+
+ /* release resource */
+ ctx->func->destroy(ctx->cryp_ctx);
+ ctx->cryp_ctx = HI_NULL;
-+ kapi_hash_destroy(soft_hash_id);
++ ret = kapi_hash_destroy(soft_hash_id);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_destroy, ret);
++ kapi_hash_unlock();
++ return ret;
++ }
+
-+ KAPI_HASH_UNLOCK();
-+
-+ HI_LOG_FUNC_EXIT();
-+
-+ return ret;
++ kapi_hash_unlock();
++ hi_log_func_exit();
++ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_hash_release(void)
++hi_s32 kapi_hash_release(hi_void)
+{
+ hi_u32 i = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_hash_ctx *ctx = HI_NULL;
+ crypto_owner owner;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ crypto_get_owner(&owner);
+
-+ HI_LOG_INFO("hash release owner 0x%x\n", owner);
++ hi_log_info("hash release owner 0x%x\n", owner);
+
+ /* destroy the channel which are created by current user */
+ for (i = 0; i < HASH_SOFT_CHANNEL_MAX; i++) {
-+ if (hash_ctx[i].open == HI_TRUE) {
++ if (g_hash_ctx[i].open == HI_TRUE) {
+ ctx = kapi_hash_get_ctx(i);
+ if (ctx == HI_NULL) {
-+ HI_LOG_ERROR("kapi hash get ctx failed,point is null.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_POINT);
++ hi_log_error("kapi hash get ctx failed, point is null.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_POINT);
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
-+ if (memcmp(&owner, &ctx->owner, sizeof(owner)) == 0) {
-+ HI_LOG_INFO("hash release chn %d\n", i);
++ if (memcmp(&owner, &ctx->owner, sizeof(owner)) != 0) {
++ continue;
++ }
+
-+ if ((ctx->func != HI_NULL)
-+ && (ctx->func->destroy != HI_NULL)
-+ && (ctx->cryp_ctx != HI_NULL)) {
-+ ctx->func->destroy(ctx->cryp_ctx);
-+ }
-+ ctx->cryp_ctx = HI_NULL;
-+ ret = kapi_hash_destroy(i);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_hash_destroy, ret);
-+ return ret;
-+ }
++ hi_log_info("hash release chn %d\n", i);
++ if ((ctx->func != HI_NULL) && (ctx->func->destroy != HI_NULL) && (ctx->cryp_ctx != HI_NULL)) {
++ ctx->func->destroy(ctx->cryp_ctx);
++ }
++ ctx->cryp_ctx = HI_NULL;
++ ret = kapi_hash_destroy(i);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_hash_destroy, ret);
++ return ret;
+ }
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_rsa.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_rsa.c
new file mode 100644
-index 0000000..94a2e15
+index 0000000..395b246
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_rsa.c
-@@ -0,0 +1,138 @@
+@@ -0,0 +1,108 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for kapi rsa of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
+#include "cryp_rsa.h"
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup rsa */
-+/** @{*/ /** <!-- [kapi]*/
-+
-+/**
-+\brief Kapi Init.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/* ****************************** API Code **************************** */
++/*
++ * brief Kapi Init.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_rsa_init(void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ ret = cryp_rsa_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_init, ret);
++ hi_log_print_func_err(cryp_rsa_init, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+/**
-+\brief Kapi Deinitialize.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * brief Kapi Deinitialize.
++ * retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 kapi_rsa_deinit(void)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ cryp_rsa_deinit();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_rsa_encrypt(cryp_rsa_key *key,
-+ hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen)
++hi_s32 kapi_rsa_encrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = cryp_rsa_encrypt(key, scheme, in, inlen, out, outlen);
++ ret = cryp_rsa_encrypt(key, rsa);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_encrypt, ret);
++ hi_log_print_func_err(cryp_rsa_encrypt, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_rsa_decrypt(cryp_rsa_key *key,
-+ hi_cipher_rsa_enc_scheme scheme,
-+ hi_u8 *in, hi_u32 inlen,
-+ hi_u8 *out, hi_u32 *outlen)
++hi_s32 kapi_rsa_decrypt(cryp_rsa_key *key, cryp_rsa_crypt_data *rsa)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = cryp_rsa_decrypt(key, scheme, in, inlen, out, outlen);
++ ret = cryp_rsa_decrypt(key, rsa);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_decrypt, ret);
++ hi_log_print_func_err(cryp_rsa_decrypt, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_rsa_sign_hash(cryp_rsa_key *key,
-+ hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *hash, hi_u32 hlen,
-+ hi_u8 *sign, hi_u32 *signlen)
++hi_s32 kapi_rsa_sign_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = cryp_rsa_sign_hash(key, scheme, hash, hlen, sign, signlen, hlen);
++ ret = cryp_rsa_sign_hash(key, rsa);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_sign_hash, ret);
++ hi_log_print_func_err(cryp_rsa_sign_hash, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_rsa_verify_hash(cryp_rsa_key *key,
-+ hi_cipher_rsa_sign_scheme scheme,
-+ hi_u8 *hash, hi_u32 hlen,
-+ hi_u8 *sign, hi_u32 signlen)
++hi_s32 kapi_rsa_verify_hash(cryp_rsa_key *key, cryp_rsa_sign_data *rsa)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ ret = cryp_rsa_verify_hash(key, scheme, hash, hlen, sign, signlen, hlen);
++ ret = cryp_rsa_verify_hash(key, rsa);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_rsa_verify_hash, ret);
++ hi_log_print_func_err(cryp_rsa_verify_hash, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_symc.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_symc.c
new file mode 100644
-index 0000000..7d96ea8
+index 0000000..4cce653
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_symc.c
-@@ -0,0 +1,960 @@
+@@ -0,0 +1,1054 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for kapi symc of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
@@ -251279,189 +319793,200 @@ index 0000000..7d96ea8
+#include "hi_drv_compat.h"
+
+/* max number of nodes */
-+#define MAX_PKG_NUMBER (100000)
++#define MAX_PKG_NUMBER 100000
+
+/* max length of CCM/GCM AAD */
-+#define MAX_AEAD_A_LEN (0x100000)
++#define MAX_AEAD_A_LEN 0x100000
+
+typedef struct {
-+ hi_u32 open : 1; /*!< open or close */
-+ hi_u32 config : 1; /*!< aleardy config or not */
++ hi_u32 open : 1; /* open or close */
++ hi_u32 config : 1; /* aleardy config or not */
+ symc_func *func;
-+ void *cryp_ctx; /*!< Context of cryp instance */
-+ crypto_owner owner; /*!< user ID */
-+ hi_cipher_ctrl ctrl; /*!< control infomation */
++ void *cryp_ctx; /* Context of cryp instance */
++ crypto_owner owner; /* user ID */
++ hi_cipher_ctrl ctrl; /* control infomation */
+} kapi_symc_ctx;
+
++typedef struct {
++ hi_u32 soft_id;
++ symc_width width;
++ hi_u32 byca;
++ hi_u32 ca_type;
++ hi_u32 klen;
++} symc_set_cfg_param;
++
+/*! Context of cipher */
-+static kapi_symc_ctx kapi_ctx[CRYPTO_HARD_CHANNEL_MAX];
++static kapi_symc_ctx g_kapi_ctx[CRYPTO_HARD_CHANNEL_MAX];
+
+/* symc mutex */
-+static crypto_mutex symc_mutex;
++static crypto_mutex g_symc_mutex;
+
-+#define KAPI_SYMC_CHECK_HANDLE(handle) \
-+ do \
-+ { \
-+ if((HI_HANDLE_GET_MODID(handle) != HI_ID_CIPHER) \
-+ || (HI_HANDLE_GET_PriDATA(handle) != 0)) \
-+ { \
-+ HI_LOG_ERROR("Invalid handle 0x%x!\n", handle); \
-+ return HI_ERR_CIPHER_INVALID_HANDLE; \
-+ } \
-+ if (HI_HANDLE_GET_CHNID(handle) >= CRYPTO_HARD_CHANNEL_MAX) \
-+ { \
-+ HI_LOG_ERROR("chan %d is too large, max: %d\n", HI_HANDLE_GET_CHNID(handle), CRYPTO_HARD_CHANNEL_MAX); \
-+ return HI_ERR_CIPHER_INVALID_HANDLE; \
-+ } \
-+ if (kapi_ctx[HI_HANDLE_GET_CHNID(handle)].open == HI_FALSE) \
-+ { \
-+ HI_LOG_ERROR("chan %d is not open\n", HI_HANDLE_GET_CHNID(handle)); \
-+ return HI_ERR_CIPHER_INVALID_HANDLE; \
++#define kapi_symc_lock_err_return() \
++ do { \
++ ret = crypto_mutex_lock(&g_symc_mutex); \
++ if (ret != HI_SUCCESS) { \
++ hi_log_error("error, symc lock failed\n"); \
++ hi_log_print_func_err(crypto_mutex_lock, ret); \
++ return ret; \
+ } \
+ } while (0)
+
-+#define KAPI_SYMC_LOCK() \
-+ ret = crypto_mutex_lock(&symc_mutex); \
-+ if (ret != HI_SUCCESS) \
-+ {\
-+ HI_LOG_ERROR("error, symc lock failed\n");\
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mutex_lock, ret);\
-+ return ret;\
++#define kapi_symc_unlock() crypto_mutex_unlock(&g_symc_mutex)
++#define AES_CCM_MIN_TAG_LEN 4
++#define AES_CCM_MAX_TAG_LEN 16
++#define AES_GCM_MIN_TAG_LEN 1
++#define AES_GCM_MAX_TAG_LEN 16
++
++/* ****************************** API Code **************************** */
++static hi_s32 kapi_symc_chk_handle(hi_handle handle)
++{
++ if ((hi_handle_get_modid(handle) != HI_ID_CIPHER) || (hi_handle_get_private_data(handle) != 0)) {
++ hi_log_error("Invalid handle 0x%x!\n", handle);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_HANDLE);
++ return HI_ERR_CIPHER_INVALID_HANDLE;
+ }
+
-+#define KAPI_SYMC_UNLOCK() crypto_mutex_unlock(&symc_mutex)
-+#define AES_CCM_MIN_TAG_LEN (4)
-+#define AES_CCM_MAX_TAG_LEN (16)
-+#define AES_GCM_MIN_TAG_LEN (1)
-+#define AES_GCM_MAX_TAG_LEN (16)
++ if (hi_handle_get_chnid(handle) >= CRYPTO_HARD_CHANNEL_MAX) {
++ hi_log_error("chan %d is too large, max: %d\n", hi_handle_get_chnid(handle), CRYPTO_HARD_CHANNEL_MAX);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_HANDLE);
++ return HI_ERR_CIPHER_INVALID_HANDLE;
++ }
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++ if (g_kapi_ctx[hi_handle_get_chnid(handle)].open == HI_FALSE) {
++ hi_log_error("chan %d is not open\n", hi_handle_get_chnid(handle));
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_HANDLE);
++ return HI_ERR_CIPHER_INVALID_HANDLE;
++ }
+
-+/******************************* API Code *****************************/
-+/** \addtogroup symc */
-+/** @{*/ /** <!-- [kapi]*/
++ return HI_SUCCESS;
++}
+
+hi_s32 kapi_symc_init(void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_INFO("kapi_symc_init()\n");
++ hi_log_info("kapi_symc_init()\n");
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ crypto_mutex_init(&symc_mutex);
++ crypto_mutex_init(&g_symc_mutex);
+
-+ crypto_memset(kapi_ctx, sizeof(kapi_ctx), 0, sizeof(kapi_ctx));
++ crypto_memset(g_kapi_ctx, sizeof(g_kapi_ctx), 0, sizeof(g_kapi_ctx));
+
+ ret = cryp_symc_init();
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_init, ret);
++ hi_log_print_func_err(cryp_symc_init, ret);
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 kapi_symc_deinit(void)
+{
-+ HI_LOG_INFO("kapi_symc_deinit()\n");
++ hi_log_info("kapi_symc_deinit()\n");
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ cryp_symc_deinit();
+
-+ crypto_mutex_destroy(&symc_mutex);
++ crypto_mutex_destroy(&g_symc_mutex);
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 kapi_symc_release(void)
+{
-+ hi_u32 i = 0, chn = 0;
-+ hi_s32 ret = HI_FAILURE;
++ hi_u32 i, chn;
++ hi_s32 ret;
+ kapi_symc_ctx *ctx = HI_NULL;
+ crypto_owner owner;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ crypto_get_owner(&owner);
+
-+ HI_LOG_INFO("symc release owner 0x%x\n", owner);
++ hi_log_info("symc release owner 0x%x\n", owner);
+
+ /* destroy the channel which are created by current user */
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
-+ ctx = &kapi_ctx[i];
++ ctx = &g_kapi_ctx[i];
+ if (ctx->open == HI_TRUE) {
-+ if (memcmp(&owner, &ctx->owner, sizeof(owner)) == 0) {
-+ chn = HI_HANDLE_MAKEHANDLE(HI_ID_CIPHER, 0, i);
-+ HI_LOG_INFO("symc release chn %d\n", chn);
-+ ret = kapi_symc_destroy(chn);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_destroy, ret);
-+ return ret;
-+ }
++ if (memcmp(&owner, &ctx->owner, sizeof(owner)) != 0) {
++ continue;
++ }
++ chn = hi_handle_makehandle(HI_ID_CIPHER, 0, i);
++ hi_log_info("symc release chn %d\n", chn);
++ ret = kapi_symc_destroy(chn);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_destroy, ret);
++ return ret;
+ }
+ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+
+hi_s32 kapi_symc_create(hi_u32 *id)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 chn = 0;
+ kapi_symc_ctx *ctx = HI_NULL;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(id == HI_NULL);
++ hi_log_chk_param_return(id == HI_NULL);
+
-+ KAPI_SYMC_LOCK();
++ kapi_symc_lock_err_return();
+
+ /* allocate a aes soft channel for hard channel allocted */
+ ret = cryp_symc_alloc_chn(&chn);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("error, allocate symc channel failed\n");
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_alloc_chn, ret);
-+ KAPI_SYMC_UNLOCK();
++ hi_log_error("error, allocate symc channel failed\n");
++ hi_log_print_func_err(cryp_symc_alloc_chn, ret);
++ kapi_symc_unlock();
+ return ret;
+ }
-+ ctx = &kapi_ctx[chn];
++ ctx = &g_kapi_ctx[chn];
+
+ crypto_memset(ctx, sizeof(kapi_symc_ctx), 0, sizeof(kapi_symc_ctx));
+ crypto_get_owner(&ctx->owner);
+
-+ *id = HI_HANDLE_MAKEHANDLE(HI_ID_CIPHER, 0, chn);
++ *id = hi_handle_makehandle(HI_ID_CIPHER, 0, chn);
+ ctx->open = HI_TRUE;
+ ctx->config = HI_FALSE;
+
-+ HI_LOG_INFO("kapi_symc_create()- chn %d\n", chn);
++ hi_log_info("kapi_symc_create()- chn %d\n", chn);
+
-+ KAPI_SYMC_UNLOCK();
++ kapi_symc_unlock();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 kapi_symc_destroy(hi_u32 id)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_symc_ctx *ctx = HI_NULL;
-+ hi_u32 soft_id = 0;
++ hi_u32 soft_id;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ KAPI_SYMC_CHECK_HANDLE(id);
-+ soft_id = HI_HANDLE_GET_CHNID(id);
-+ ctx = &kapi_ctx[soft_id];
-+ CHECK_OWNER(&ctx->owner);
++ ret = kapi_symc_chk_handle((hi_handle)id);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_handle, ret);
++ return ret;
++ }
+
-+ KAPI_SYMC_LOCK();
++ soft_id = hi_handle_get_chnid(id);
++ ctx = &g_kapi_ctx[soft_id];
++ crypto_chk_owner_err_return(&ctx->owner);
++
++ kapi_symc_lock_err_return();
+
+ cryp_symc_free_chn(soft_id);
+
@@ -251469,8 +319994,8 @@ index 0000000..7d96ea8
+ if ((ctx->func != HI_NULL) && (ctx->func->destroy != HI_NULL)) {
+ ret = ctx->func->destroy(ctx->cryp_ctx);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->destroy, ret);
-+ KAPI_SYMC_UNLOCK();
++ hi_log_print_func_err(ctx->func->destroy, ret);
++ kapi_symc_unlock();
+ return ret;
+ }
+ ctx->cryp_ctx = HI_NULL;
@@ -251478,142 +320003,170 @@ index 0000000..7d96ea8
+
+ ctx->open = HI_FALSE;
+
-+ HI_LOG_INFO("kapi_symc_destroy()- chn 0x%x\n", id);
++ hi_log_info("kapi_symc_destroy()- chn 0x%x\n", id);
+
-+ KAPI_SYMC_UNLOCK();
++ kapi_symc_unlock();
++
++ hi_log_func_exit();
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_symc_chk_des_3des_param(hi_cipher_alg alg, hi_cipher_work_mode mode, hi_u32 width)
++{
++#ifndef CHIP_DES_SUPPORT
++ if (alg == HI_CIPHER_ALG_DES) {
++ hi_log_error("Invalid alg, unsupport des.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARA);
++ return HI_ERR_CIPHER_INVALID_PARA;
++ }
++#endif
++#ifndef CHIP_3DES_SUPPORT
++ if (alg == HI_CIPHER_ALG_3DES) {
++ hi_log_error("Invalid alg, unsupport 3des.\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARA);
++ return HI_ERR_CIPHER_INVALID_PARA;
++ }
++#endif
++ if (mode > HI_CIPHER_WORK_MODE_OFB) {
++ hi_log_error("Invalid alg %d and mode %d\n", alg, mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARA);
++ return HI_ERR_CIPHER_INVALID_PARA;
++ }
++
++ if ((mode == HI_CIPHER_WORK_MODE_CFB) || (mode == HI_CIPHER_WORK_MODE_OFB)) {
++ if ((width != SYMC_DAT_WIDTH_64) && (width != SYMC_DAT_WIDTH_8) && (width != SYMC_DAT_WIDTH_1)) {
++ hi_log_error("Invalid mode %d and bit width %d\n", mode, width);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARA);
++ return HI_ERR_CIPHER_INVALID_PARA;
++ }
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_symc_chk_aes_param(hi_cipher_alg alg, hi_cipher_work_mode mode, hi_u32 width)
++{
++ if (mode > HI_CIPHER_WORK_MODE_BUTT) {
++ hi_log_error("Invalid alg %d and mode %d\n", alg, mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ if ((mode == HI_CIPHER_WORK_MODE_CFB) && (width != SYMC_DAT_WIDTH_1) && (width != SYMC_DAT_WIDTH_8) &&
++ (width != SYMC_DAT_WIDTH_128)) {
++ hi_log_error("Invalid alg %d mode %d and width %d\n", alg, mode, width);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ if ((mode == HI_CIPHER_WORK_MODE_OFB) && (width != SYMC_DAT_WIDTH_128)) {
++ hi_log_error("Invalid alg %d mode %d and width %d\n", alg, mode, width);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_symc_chk_sm1_param(hi_cipher_alg alg, hi_cipher_work_mode mode, hi_u32 width, hi_u32 round)
++{
++ if (mode > HI_CIPHER_WORK_MODE_OFB) {
++ hi_log_error("Invalid alg %d and mode %d\n", alg, mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ if ((mode == HI_CIPHER_WORK_MODE_OFB)
++ && (width != SYMC_DAT_WIDTH_128)) {
++ hi_log_error("Invalid alg %d mode %d and width %d\n", alg, mode, width);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ if ((mode == HI_CIPHER_WORK_MODE_CFB)
++ && (width >= SYMC_DAT_WIDTH_COUNT)) {
++ hi_log_error("Invalid alg %d mode %d and width %d\n", alg, mode, width);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ if ((alg == HI_CIPHER_ALG_SM1) && (round >= HI_CIPHER_SM1_ROUND_BUTT)) {
++ hi_log_error("Invalid alg %d and Sm1Round %d\n", alg, round);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_symc_chk_sm4_param(hi_cipher_alg alg, hi_cipher_work_mode mode)
++{
++ if ((mode != HI_CIPHER_WORK_MODE_ECB) && (mode != HI_CIPHER_WORK_MODE_CBC) && (mode != HI_CIPHER_WORK_MODE_CTR)) {
++ hi_log_error("Invalid alg %d and mode %d\n", alg, mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
+
-+ HI_LOG_FUNC_EXIT();
+ return HI_SUCCESS;
+}
+
+static hi_s32 kapi_symc_width_check(hi_cipher_alg alg, hi_cipher_work_mode mode, hi_u32 width, hi_u32 round)
+{
++ hi_s32 ret;
++
+ /* the bit width depend on alg and mode, which limit to hardware
+ * des/3des with cfb/ofb support bit1, bit8, bit 64.
+ * aes with cfb/ofb only support bit128.
+ * sm1 with ofb only support bit128, cfb support bit1, bit8, bit 64.
+ */
++ hi_log_func_enter();
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_chk_param_return(alg >= HI_CIPHER_ALG_BUTT);
++ hi_log_chk_param_return((alg != HI_CIPHER_ALG_DMA) && (mode >= HI_CIPHER_WORK_MODE_BUTT));
++ hi_log_chk_param_return((alg != HI_CIPHER_ALG_DMA) && (width >= SYMC_DAT_WIDTH_COUNT));
+
+ if ((alg == HI_CIPHER_ALG_3DES) || (alg == HI_CIPHER_ALG_DES)) {
-+#ifndef CHIP_DES_SUPPORT
-+ if (alg == HI_CIPHER_ALG_DES) {
-+ HI_LOG_ERROR("Invalid alg, unsupport des.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+#endif
-+#ifndef CHIP_3DES_SUPPORT
-+ if (alg == HI_CIPHER_ALG_3DES) {
-+ HI_LOG_ERROR("Invalid alg, unsupport 3des.\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+#endif
-+ if (mode > HI_CIPHER_WORK_MODE_OFB) {
-+ HI_LOG_ERROR("Invalid alg %d and mode %d\n", alg, mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if ((mode == HI_CIPHER_WORK_MODE_CFB) || (mode == HI_CIPHER_WORK_MODE_OFB)) {
-+ if ((width != SYMC_DAT_WIDTH_64)
-+ && (width != SYMC_DAT_WIDTH_8)
-+ && (width != SYMC_DAT_WIDTH_1)) {
-+ HI_LOG_ERROR("Invalid mode %d and bit width %d\n", mode, width);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
++ ret = kapi_symc_chk_des_3des_param(alg, mode, width);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_des_3des_param, ret);
++ return ret;
+ }
+ }
+
+ if (alg == HI_CIPHER_ALG_AES) {
-+ if (mode > HI_CIPHER_WORK_MODE_BUTT) {
-+ HI_LOG_ERROR("Invalid alg %d and mode %d\n", alg, mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if ((mode == HI_CIPHER_WORK_MODE_CFB)
-+ && (width != SYMC_DAT_WIDTH_1)
-+ && (width != SYMC_DAT_WIDTH_8)
-+ && (width != SYMC_DAT_WIDTH_128)) {
-+ HI_LOG_ERROR("Invalid alg %d mode %d and width %d\n", alg, mode, width);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if ((mode == HI_CIPHER_WORK_MODE_OFB)
-+ && (width != SYMC_DAT_WIDTH_128)) {
-+ HI_LOG_ERROR("Invalid alg %d mode %d and width %d\n", alg, mode, width);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ ret = kapi_symc_chk_aes_param(alg, mode, width);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_aes_param, ret);
++ return ret;
+ }
+ }
+
+ if (alg == HI_CIPHER_ALG_SM1) {
-+ if (mode > HI_CIPHER_WORK_MODE_OFB) {
-+ HI_LOG_ERROR("Invalid alg %d and mode %d\n", alg, mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if ((mode == HI_CIPHER_WORK_MODE_OFB)
-+ && (width != SYMC_DAT_WIDTH_128)) {
-+ HI_LOG_ERROR("Invalid alg %d mode %d and width %d\n", alg, mode, width);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if ((mode == HI_CIPHER_WORK_MODE_CFB)
-+ && (width >= SYMC_DAT_WIDTH_COUNT)) {
-+ HI_LOG_ERROR("Invalid alg %d mode %d and width %d\n", alg, mode, width);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ ret = kapi_symc_chk_sm1_param(alg, mode, width, round);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_sm1_param, ret);
++ return ret;
+ }
+ }
+
-+ if ((alg == HI_CIPHER_ALG_SM4)
-+ && (mode != HI_CIPHER_WORK_MODE_ECB)
-+ && (mode != HI_CIPHER_WORK_MODE_CBC)
-+ && (mode != HI_CIPHER_WORK_MODE_CTR)) {
-+ HI_LOG_ERROR("Invalid alg %d and mode %d\n", alg, mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if (alg == HI_CIPHER_ALG_SM4) {
++ ret = kapi_symc_chk_sm4_param(alg, mode);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_sm4_param, ret);
++ return ret;
++ }
+ }
+
-+ if ((alg == HI_CIPHER_ALG_SM1) && (round >= HI_CIPHER_SM1_ROUND_BUTT)) {
-+ HI_LOG_ERROR("Invalid alg %d and Sm1Round %d\n", alg, round);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if (alg >= HI_CIPHER_ALG_BUTT) {
-+ HI_LOG_ERROR("Invalid alg %d .\n", alg);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if (width >= SYMC_DAT_WIDTH_COUNT) {
-+ HI_LOG_ERROR("Invalid mode %d\n", width);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 kapi_symc_match_width(hi_cipher_work_mode work_mode,
-+ hi_cipher_bit_width bit_width,
-+ symc_width *width)
++static hi_s32 kapi_symc_match_width(hi_cipher_work_mode work_mode, hi_cipher_bit_width bit_width, symc_width *width)
+{
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
+ /* set the bit width which depend on alg and mode */
-+ if ((HI_CIPHER_WORK_MODE_CFB == work_mode)
-+ || (HI_CIPHER_WORK_MODE_OFB == work_mode)) {
++ if ((work_mode == HI_CIPHER_WORK_MODE_CFB) || (work_mode == HI_CIPHER_WORK_MODE_OFB)) {
+ switch (bit_width) {
+ case HI_CIPHER_BIT_WIDTH_64BIT: {
+ *width = SYMC_DAT_WIDTH_64;
@@ -251632,510 +320185,568 @@ index 0000000..7d96ea8
+ break;
+ }
+ default: {
-+ HI_LOG_ERROR("Invalid width: 0x%x, mode 0x%x\n",
-+ bit_width, work_mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid width: 0x%x, mode 0x%x\n", bit_width, work_mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
+ } else {
-+ *width = SYMC_DAT_WIDTH_128;
++ if (bit_width == HI_CIPHER_BIT_WIDTH_128BIT) {
++ *width = SYMC_DAT_WIDTH_128;
++ }
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+static hi_s32 kapi_symc_check_param(hi_u32 hard_key, hi_u32 iv_usage,
-+ hi_cipher_alg alg,
-+ hi_cipher_work_mode work_mode,
-+ hi_cipher_bit_width bit_width,
-+ hi_cipher_key_length key_len,
-+ hi_cipher_sm1_round sm1_round_num,
-+ symc_width *width)
++static hi_s32 kapi_symc_chk_param(hi_u32 hard_key, symc_cfg_t *cfg, symc_width *width)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ if (alg == HI_CIPHER_ALG_DMA) {
-+ HI_LOG_INFO("Alg is DMA.\n");
-+ HI_DBG_PRINT_U32(alg);
++ if (cfg->alg == HI_CIPHER_ALG_DMA) {
++ hi_log_info("Alg is DMA.\n");
++ hi_dbg_print_u32(cfg->alg);
+ return HI_SUCCESS;
+ }
+
-+ if ((hard_key != HI_TRUE) && (hard_key != HI_FALSE)) {
-+ HI_LOG_ERROR("Invalid hard_key: 0x%x\n", hard_key);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((hard_key != HI_TRUE) && (hard_key != HI_FALSE)) {
++ hi_log_error("Invalid hard_key: 0x%x\n", hard_key);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
-+ if (key_len > HI_CIPHER_KEY_DES_2KEY) {
-+ HI_LOG_ERROR("Invalid key len: 0x%x\n", key_len);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if (cfg->klen > HI_CIPHER_KEY_DES_2KEY) {
++ hi_log_error("Invalid key len: 0x%x\n", cfg->klen);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ /* set the bit width which depend on alg and mode */
-+ ret = kapi_symc_match_width(work_mode, bit_width, width);
++ ret = kapi_symc_match_width(cfg->mode, cfg->width, width);
+ if (ret != HI_SUCCESS) {
-+ HI_ERR_PRINT_U32(work_mode);
-+ HI_ERR_PRINT_U32(bit_width);
-+ HI_ERR_PRINT_U32(*width);
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_match_width, ret);
++ hi_err_print_u32(cfg->mode);
++ hi_err_print_u32(cfg->width);
++ hi_err_print_u32(*width);
++ hi_log_print_func_err(kapi_symc_match_width, ret);
+ return ret;
+ }
+
-+ ret = kapi_symc_width_check(alg, work_mode, *width, sm1_round_num);
++ ret = kapi_symc_width_check(cfg->alg, cfg->mode, *width, cfg->sm1_round_num);
+ if (ret != HI_SUCCESS) {
-+ HI_ERR_PRINT_U32(alg);
-+ HI_ERR_PRINT_U32(work_mode);
-+ HI_ERR_PRINT_U32(*width);
-+ HI_ERR_PRINT_U32(sm1_round_num);
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_width_check, ret);
++ hi_err_print_u32(cfg->alg);
++ hi_err_print_u32(cfg->mode);
++ hi_err_print_u32(*width);
++ hi_err_print_u32(cfg->sm1_round_num);
++ hi_log_print_func_err(kapi_symc_width_check, ret);
+ return ret;
+ }
+
-+ if (iv_usage > CIPHER_IV_CHANGE_ALL_PKG) {
-+ HI_LOG_ERROR("Invalid IV Change Flags: 0x%x\n", iv_usage);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if (cfg->iv_usage > HI_CIPHER_IV_CHG_ALL_PACK) {
++ hi_log_error("Invalid IV Change Flags: 0x%x\n", cfg->iv_usage);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ if ((iv_usage == CIPHER_IV_CHANGE_ALL_PKG)
-+ && ((work_mode == HI_CIPHER_WORK_MODE_CCM)
-+ || (work_mode == HI_CIPHER_WORK_MODE_GCM))) {
-+ HI_LOG_ERROR("Invalid IV Change Flags: 0x%x\n", iv_usage);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((cfg->iv_usage == HI_CIPHER_IV_CHG_ALL_PACK) &&
++ ((cfg->mode == HI_CIPHER_WORK_MODE_CCM) || (cfg->mode == HI_CIPHER_WORK_MODE_GCM))) {
++ hi_log_error("Invalid IV Change Flags: 0x%x\n", cfg->iv_usage);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+static hi_s32 kapi_symc_check_ccm_gcm_taglen(hi_cipher_alg alg, hi_cipher_work_mode work_mode, hi_u32 tlen)
+{
-+ HI_LOG_CHECK_PARAM(alg != HI_CIPHER_ALG_AES);
++ hi_log_chk_param_return(alg != HI_CIPHER_ALG_AES);
+
+ if (work_mode == HI_CIPHER_WORK_MODE_CCM) {
+ /* the parameter t denotes the octet length of T(tag)
+ * t is an element of { 4, 6, 8, 10, 12, 14, 16}
+ * here t is pConfig->u32TagLen
+ */
-+ if ((tlen & 0x01)
-+ || (tlen < AES_CCM_MIN_TAG_LEN)
-+ || (tlen > AES_CCM_MAX_TAG_LEN)) {
-+ HI_LOG_ERROR("Invalid ccm tag len, tlen = 0x%x.\n", tlen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if ((tlen & 0x01) || (tlen < AES_CCM_MIN_TAG_LEN) || (tlen > AES_CCM_MAX_TAG_LEN)) {
++ hi_log_error("Invalid ccm tag len, tlen = 0x%x.\n", tlen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ } else if (work_mode == HI_CIPHER_WORK_MODE_GCM) {
+ if ((tlen < AES_GCM_MIN_TAG_LEN) || (tlen > AES_GCM_MAX_TAG_LEN)) {
-+ HI_LOG_ERROR("Invalid gcm tag len, tlen = 0x%x.\n", tlen);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Invalid gcm tag len, tlen = 0x%x.\n", tlen);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ } else {
-+ HI_LOG_ERROR("Aes with invalid work mode 0x%x for check tag length.\n", work_mode);
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("Aes with invalid work mode 0x%x for check tag length.\n", work_mode);
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_symc_config(hi_u32 id,
-+ hi_u32 hard_key,
-+ hi_cipher_alg alg,
-+ hi_cipher_work_mode work_mode,
-+ hi_cipher_bit_width bit_width,
-+ hi_cipher_key_length key_len,
-+ hi_cipher_sm1_round sm1_round_num,
-+ hi_u8 *fkey, hi_u8 *skey,
-+ hi_u8 *iv, hi_u32 ivlen, hi_u32 iv_usage,
-+ compat_addr aad, hi_u32 alen, hi_u32 tlen)
++static hi_s32 kapi_symc_chk_cfg(symc_cfg_t *cfg, symc_set_cfg_param *set_cfg)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_symc_ctx *ctx = HI_NULL;
-+ symc_width width = SYMC_DAT_WIDTH_COUNT;
-+ hi_u32 soft_id = 0;
-+ hi_u32 byca = HI_FALSE;
-+ hi_u32 ca_type = 0;
-+ hi_u32 klen = key_len;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_chk_param_return(cfg == HI_NULL);
++ hi_log_chk_param_return(cfg->alen > MAX_AEAD_A_LEN);
++ hi_log_chk_param_return(addr_l32(cfg->aad) + cfg->alen < cfg->alen);
+
-+ HI_LOG_CHECK_PARAM(fkey == HI_NULL);
-+ HI_LOG_CHECK_PARAM(alen > MAX_AEAD_A_LEN);
-+ HI_LOG_CHECK_PARAM(ADDR_L32(aad) + alen < alen);
-+
-+ KAPI_SYMC_CHECK_HANDLE(id);
-+ soft_id = HI_HANDLE_GET_CHNID(id);
-+ ctx = &kapi_ctx[soft_id];
-+ CHECK_OWNER(&ctx->owner);
-+
-+ /***
-+ hard_key: bit[0~7] flag of hard key or not
-+ bit[8~31] ca type
-+ */
-+ byca = hard_key & 0xFF;
-+ ca_type = hard_key >> BITS_IN_BYTE;
-+
-+ ret = kapi_symc_check_param(byca, iv_usage, alg, work_mode,
-+ bit_width, key_len, sm1_round_num, &width);
++ ret = kapi_symc_chk_handle((hi_handle)cfg->id);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("hard_key 0x%x\n", hard_key);
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_check_param, ret);
++ hi_log_print_func_err(kapi_symc_chk_handle, ret);
+ return ret;
+ }
+
-+ KAPI_SYMC_LOCK();
++ set_cfg->soft_id = hi_handle_get_chnid(cfg->id);
++ ctx = &g_kapi_ctx[set_cfg->soft_id];
++ if (ctx == HI_NULL) {
++ hi_log_error("kapi symc ctx is null.\n");
++ return HI_ERR_CIPHER_INVALID_POINT;
++ }
+
-+ /* Destroy the last attached instance of Symmetric cipher engine */
++ crypto_chk_owner_err_return(&ctx->owner);
++
++ /*
++ * hard_key: bit[0~7] flag of hard key or not
++ * bit[8~31] ca type
++ */
++ set_cfg->byca = cfg->hard_key & 0xFF;
++ set_cfg->ca_type = cfg->hard_key >> BITS_IN_BYTE;
++
++ ret = kapi_symc_chk_param(set_cfg->byca, cfg, &set_cfg->width);
++ if (ret != HI_SUCCESS) {
++ hi_log_error("hard_key 0x%x\n", cfg->hard_key);
++ hi_log_print_func_err(kapi_symc_chk_param, ret);
++ return ret;
++ }
++
++ set_cfg->klen = (hi_u32)cfg->klen;
++
++ return HI_SUCCESS;
++}
++
++static hi_void kapi_symc_set_alg_mode(kapi_symc_ctx *ctx, symc_set_cfg_param *set_cfg)
++{
++ /* set mode and alg */
++ if (ctx->func->setmode) {
++ ctx->func->setmode(ctx->cryp_ctx, ctx->func->alg, ctx->func->mode, set_cfg->width);
++ }
++}
++
++static hi_s32 kapi_symc_set_key(symc_cfg_t *cfg, kapi_symc_ctx *ctx, symc_set_cfg_param *set_cfg)
++{
++ hi_s32 ret;
++
++ if (ctx->func->setkey == HI_NULL) {
++ return HI_SUCCESS;
++ }
++
++ if (set_cfg->byca == HI_TRUE) {
++ ret = ctx->func->setkey(ctx->cryp_ctx, HI_NULL, HI_NULL, &set_cfg->klen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ctx->func->setkey, ret);
++ return ret;
++ }
++
++ if (cfg->klen == HI_CIPHER_KEY_AES_192BIT) {
++ set_cfg->klen = AES_KEY_256BIT;
++ }
++
++ ret = klad_load_hard_key(cfg->id, set_cfg->ca_type, cfg->fkey, set_cfg->klen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(klad_load_hard_key, ret);
++ return ret;
++ }
++ } else {
++ ret = ctx->func->setkey(ctx->cryp_ctx, cfg->fkey, cfg->skey, &set_cfg->klen);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ctx->func->setkey, ret);
++ return ret;
++ }
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_symc_cpy_key_iv(symc_cfg_t *cfg, kapi_symc_ctx *ctx, symc_set_cfg_param *set_cfg)
++{
++ if (cfg->iv != HI_NULL) {
++ if (cfg->ivlen > AES_IV_SIZE) {
++ hi_log_error("Invalid iv len.\n");
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ crypto_memcpy(ctx->ctrl.iv, AES_IV_SIZE, cfg->iv, cfg->ivlen);
++ }
++
++ if (cfg->fkey != HI_NULL) {
++ if (set_cfg->klen > AES_KEY_256BIT) {
++ hi_log_error("Invalid key len.\n");
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ crypto_memcpy(ctx->ctrl.key, AES_KEY_256BIT, cfg->fkey, set_cfg->klen);
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 kapi_symc_cfg_set_param(symc_cfg_t *cfg, kapi_symc_ctx *ctx, symc_set_cfg_param *set_cfg)
++{
++ hi_s32 ret;
++
++ /* null means can ignore the function */
++ if (ctx->func->create) {
++ /* Create a instance from template of engine */
++ ctx->cryp_ctx = ctx->func->create(set_cfg->soft_id);
++ if (ctx->cryp_ctx == HI_NULL) {
++ hi_log_error("attach contxet buffer to soft_id %d failed\n", set_cfg->soft_id);
++ hi_log_print_func_err(ctx->func->create, HI_ERR_CIPHER_FAILED_MEM);
++ return HI_ERR_CIPHER_FAILED_MEM;
++ }
++ }
++
++ /* set mode and alg */
++ kapi_symc_set_alg_mode(ctx, set_cfg);
++
++ /* Set even key, may be also need set odd key */
++ crypto_chk_err_exit(kapi_symc_set_key(cfg, ctx, set_cfg));
++
++ /* Set IV */
++ if (ctx->func->setiv) {
++ crypto_chk_err_exit(ctx->func->setiv(ctx->cryp_ctx, cfg->iv, cfg->ivlen, cfg->iv_usage));
++ }
++
++ /* set sm1 round num */
++ if (ctx->func->setround) {
++ crypto_chk_err_exit(ctx->func->setround(ctx->cryp_ctx, cfg->sm1_round_num));
++ }
++
++ /* Set AAD */
++ if (ctx->func->setadd) {
++ crypto_chk_err_exit(cipher_check_mmz_phy_addr(addr_u64(cfg->aad), cfg->alen));
++ hi_log_info("set add, phy 0x%x, alen %d, tlen %d\n", addr_l32(cfg->aad), cfg->alen, cfg->tlen);
++ crypto_chk_err_exit(kapi_symc_check_ccm_gcm_taglen(cfg->alg, cfg->mode, cfg->tlen));
++ crypto_chk_err_exit(ctx->func->setadd(ctx->cryp_ctx, cfg->aad, cfg->alen, cfg->tlen));
++ }
++
++ /* save crtl */
++ crypto_memset(&ctx->ctrl, sizeof(hi_cipher_ctrl), 0, sizeof(hi_cipher_ctrl));
++ ctx->ctrl.key_by_ca = set_cfg->byca;
++ ctx->ctrl.alg = cfg->alg;
++ ctx->ctrl.bit_width = cfg->width;
++ ctx->ctrl.ca_type = set_cfg->ca_type;
++ ctx->ctrl.key_len = cfg->klen;
++ ctx->ctrl.work_mode = cfg->mode;
++ ctx->ctrl.chg_flags.bits_iv = cfg->iv_usage;
++
++ crypto_chk_err_exit(kapi_symc_cpy_key_iv(cfg, ctx, set_cfg));
++ ctx->config = HI_TRUE;
++ return HI_SUCCESS;
++exit__:
++ return ret;
++}
++
++hi_s32 kapi_symc_cfg(symc_cfg_t *cfg)
++{
++ hi_s32 ret;
++ kapi_symc_ctx *ctx = HI_NULL;
++ symc_set_cfg_param set_cfg;
++
++ hi_log_func_enter();
++
++ crypto_memset(&set_cfg, sizeof(set_cfg), 0, sizeof(set_cfg));
++
++ ret = kapi_symc_chk_cfg(cfg, &set_cfg);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_cfg, ret);
++ return ret;
++ }
++ ctx = &g_kapi_ctx[set_cfg.soft_id];
++
++ kapi_symc_lock_err_return();
++
++ /* Destroy the last attached instance of Symmetric cipher engine. */
+ if ((ctx->func != HI_NULL) && (ctx->func->destroy != HI_NULL)) {
+ (void)ctx->func->destroy(ctx->cryp_ctx);
+ }
+ ctx->cryp_ctx = HI_NULL;
+
-+ /* Clone the function from template of symc engine*/
-+ ctx->func = cryp_get_symc_op(alg, work_mode);
-+
++ /* Clone the function from template of symc engine. */
++ ctx->func = cryp_get_symc_op(cfg->alg, cfg->mode);
+ if (ctx->func == HI_NULL) {
-+ HI_LOG_ERROR("error, get symc function failed, alg %d, work_mode %d\n",
-+ alg, work_mode);
-+ HI_LOG_PRINT_FUNC_ERR(cryp_get_symc_op, ret);
-+ KAPI_SYMC_UNLOCK();
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("error, get symc function failed, alg %d, work_mode %d\n", cfg->alg, cfg->mode);
++ hi_log_print_func_err(cryp_get_symc_op, ret);
++ kapi_symc_unlock();
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ /* null means can ignore the function */
-+ if (ctx->func->create) {
-+ /* Create a instance from template of engine */
-+ ctx->cryp_ctx = ctx->func->create(soft_id);
-+ if (ctx->cryp_ctx == HI_NULL) {
-+ HI_LOG_ERROR("attach contxet buffer to soft_id %d failed\n", soft_id);
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_create, ret);
-+ goto exit__;
-+ }
++ ret = kapi_symc_cfg_set_param(cfg, ctx, &set_cfg);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(klad_load_hard_key, ret);
++ kapi_symc_unlock();
++ return ret;
+ }
+
-+ /* set mode and alg */
-+ if (ctx->func->setmode) {
-+ ctx->func->setmode(ctx->cryp_ctx, ctx->func->alg, ctx->func->mode, width);
-+ }
-+
-+ /* Set even key, may be also need set odd key */
-+ if (ctx->func->setkey) {
-+ if (byca == HI_TRUE) {
-+ CHECK_EXIT(ctx->func->setkey(ctx->cryp_ctx, HI_NULL, HI_NULL, &klen));
-+
-+ if (key_len == HI_CIPHER_KEY_AES_192BIT) {
-+ klen = AES_KEY_256BIT;
-+ }
-+
-+ CHECK_EXIT(klad_load_hard_key(id, ca_type, fkey, klen));
-+ } else {
-+ CHECK_EXIT(ctx->func->setkey(ctx->cryp_ctx, fkey, skey, &klen));
-+ }
-+ }
-+
-+ /* Set IV */
-+ if (ctx->func->setiv) {
-+ CHECK_EXIT(ctx->func->setiv(ctx->cryp_ctx, iv, ivlen, iv_usage));
-+ }
-+
-+ /* set sm1 round num */
-+ if (ctx->func->setround) {
-+ CHECK_EXIT(ctx->func->setround(ctx->cryp_ctx, sm1_round_num));
-+ }
-+
-+ /* Set AAD */
-+ if (ctx->func->setadd) {
-+ ret = cipher_check_mmz_phy_addr(ADDR_U64(aad), alen);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Invalid aad mmz phy addr.\n");
-+ HI_LOG_PRINT_FUNC_ERR(cipher_check_mmz_phy_addr, ret);
-+ goto exit__;
-+ }
-+
-+ HI_LOG_INFO("set add, phy 0x%x, alen %d, tlen %d\n", ADDR_L32(aad), alen, tlen);
-+ CHECK_EXIT(kapi_symc_check_ccm_gcm_taglen(alg, work_mode, tlen));
-+ CHECK_EXIT(ctx->func->setadd(ctx->cryp_ctx, aad, alen, tlen));
-+ }
-+
-+ /* save crtl */
-+ crypto_memset(&ctx->ctrl, sizeof(hi_cipher_ctrl), 0, sizeof(hi_cipher_ctrl));
-+ ctx->ctrl.key_by_ca = byca;
-+ ctx->ctrl.alg = alg;
-+ ctx->ctrl.bit_width = bit_width;
-+ ctx->ctrl.ca_type = ca_type;
-+ ctx->ctrl.key_len = key_len;
-+ ctx->ctrl.work_mode = work_mode;
-+ ctx->ctrl.change_flags.bit1_iv = iv_usage;
-+
-+ if (iv != HI_NULL) {
-+ if (ivlen > AES_IV_SIZE) {
-+ HI_LOG_ERROR("Invalid iv len.\n");
-+ ret = HI_ERR_CIPHER_INVALID_PARA;
-+ goto exit__;
-+ }
-+
-+ crypto_memcpy(ctx->ctrl.iv, AES_IV_SIZE, iv, ivlen);
-+ }
-+ if (fkey != HI_NULL) {
-+ if (klen > AES_KEY_256BIT) {
-+ HI_LOG_ERROR("Invalid key len.\n");
-+ ret = HI_ERR_CIPHER_INVALID_PARA;
-+ goto exit__;
-+ }
-+
-+ crypto_memcpy(ctx->ctrl.key, AES_KEY_256BIT, fkey, klen);
-+ }
-+
-+ ctx->config = HI_TRUE;
-+
-+ KAPI_SYMC_UNLOCK();
-+ HI_LOG_FUNC_EXIT();
++ kapi_symc_unlock();
++ hi_log_func_exit();
+ return HI_SUCCESS;
-+
-+exit__:
-+ KAPI_SYMC_UNLOCK();
-+
-+ return ret;
+}
+
-+hi_s32 kapi_symc_get_config(hi_u32 id, hi_cipher_ctrl *ctrl)
++hi_s32 kapi_symc_get_cfg(hi_u32 id, hi_cipher_ctrl *ctrl)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_symc_ctx *ctx = HI_NULL;
-+ hi_u32 soft_id = 0;
++ hi_u32 soft_id;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctrl == HI_NULL);
++ hi_log_chk_param_return(ctrl == HI_NULL);
+
-+ KAPI_SYMC_CHECK_HANDLE(id);
-+ soft_id = HI_HANDLE_GET_CHNID(id);
-+ ctx = &kapi_ctx[soft_id];
-+ CHECK_OWNER(&ctx->owner);
-+ HI_LOG_CHECK_PARAM(ctx->config != HI_TRUE);
++ ret = kapi_symc_chk_handle((hi_handle)id);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_handle, ret);
++ return ret;
++ }
+
-+ KAPI_SYMC_LOCK();
++ soft_id = hi_handle_get_chnid(id);
++ ctx = &g_kapi_ctx[soft_id];
++ crypto_chk_owner_err_return(&ctx->owner);
++ hi_log_chk_param_return(ctx->config != HI_TRUE);
++
++ kapi_symc_lock_err_return();
+
+ crypto_memcpy(ctrl, sizeof(hi_cipher_ctrl), &ctx->ctrl, sizeof(hi_cipher_ctrl));
++ crypto_zeroize(ctrl->key, sizeof(ctrl->key));
+
-+ KAPI_SYMC_UNLOCK();
++ kapi_symc_unlock();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+
+ return ret;
+}
+
-+hi_s32 kapi_symc_crypto(hi_u32 id, compat_addr input,
-+ compat_addr output, hi_u32 length,
-+ hi_u32 operation, hi_u32 last)
++hi_s32 kapi_symc_crypto(symc_encrypt_t *crypt)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ symc_node_usage usage;
+ kapi_symc_ctx *ctx = HI_NULL;
-+ hi_u32 soft_id = 0;
++ hi_u32 soft_id;
++ symc_multi_pack pack;
+
-+ HI_LOG_FUNC_ENTER();
-+
-+ KAPI_SYMC_CHECK_HANDLE(id);
-+ soft_id = HI_HANDLE_GET_CHNID(id);
-+ ctx = &kapi_ctx[soft_id];
-+ CHECK_OWNER(&ctx->owner);
-+ HI_LOG_CHECK_PARAM(ADDR_U64(input) + length < length);
-+ HI_LOG_CHECK_PARAM(ADDR_U64(output) + length < length);
-+ HI_LOG_CHECK_PARAM(ctx->func == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->func->crypto == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->config != HI_TRUE);
-+ HI_LOG_CHECK_PARAM((operation != 0x00) && (operation != 0x01));
-+
-+ HI_LOG_INFO("src/dest phyaddr information.\n");
-+ HI_DBG_PRINT_U32(operation);
-+ HI_DBG_PRINT_H32(ADDR_L32(input));
-+ HI_DBG_PRINT_H32(ADDR_L32(output));
-+ HI_DBG_PRINT_H32(length);
-+
-+ usage = SYMC_NODE_USAGE_NORMAL;
-+
-+ KAPI_SYMC_LOCK();
-+
-+ ret = ctx->func->crypto(ctx->cryp_ctx, operation, &input,
-+ &output, &length, &usage, 1, HI_TRUE);
++ hi_log_func_enter();
++ hi_log_chk_param_return(crypt == HI_NULL);
++ ret = kapi_symc_chk_handle((hi_handle)crypt->id);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(ctx->func->crypto, ret);
-+ KAPI_SYMC_UNLOCK();
++ hi_log_print_func_err(kapi_symc_chk_handle, ret);
+ return ret;
+ }
+
-+ KAPI_SYMC_UNLOCK();
++ soft_id = hi_handle_get_chnid(crypt->id);
++ ctx = &g_kapi_ctx[soft_id];
++ crypto_chk_owner_err_return(&ctx->owner);
++ hi_log_chk_param_return(addr_u64(crypt->in) + crypt->len < crypt->len);
++ hi_log_chk_param_return(addr_u64(crypt->out) + crypt->len < crypt->len);
++ hi_log_chk_param_return(ctx->func == HI_NULL);
++ hi_log_chk_param_return(ctx->func->crypto == HI_NULL);
++ hi_log_chk_param_return(ctx->config != HI_TRUE);
++ hi_log_chk_param_return((crypt->operation != SYMC_OPERATION_ENCRYPT) &&
++ (crypt->operation != SYMC_OPERATION_DECRYPT));
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_info("src/dest phyaddr information.\n");
++ hi_dbg_print_u32(crypt->operation);
++ hi_dbg_print_h32(addr_l32(crypt->in));
++ hi_dbg_print_h32(addr_l32(crypt->out));
++ hi_dbg_print_h32(crypt->len);
++
++ usage = SYMC_NODE_USAGE_NORMAL;
++ crypto_memset(&pack, sizeof(pack), 0, sizeof(pack));
++ pack.in = &crypt->in;
++ pack.out = &crypt->out;
++ pack.len = &crypt->len;
++ pack.usage = &usage;
++ pack.num = 1; /* 1 single package encrypt or decrypt. */
++
++ kapi_symc_lock_err_return();
++
++ ret = ctx->func->crypto(ctx->cryp_ctx, crypt->operation, &pack, HI_TRUE);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(ctx->func->crypto, ret);
++ kapi_symc_unlock();
++ return ret;
++ }
++
++ kapi_symc_unlock();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
-+hi_s32 kapi_symc_crypto_via(hi_u32 id, compat_addr input,
-+ compat_addr output, hi_u32 length,
-+ hi_u32 operation, hi_u32 last, hi_u32 is_from_user)
++hi_s32 kapi_symc_crypto_via(symc_encrypt_t *crypt, hi_u32 is_from_user)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_s32 ret_exit = HI_FAILURE;
++ hi_s32 ret, ret_exit;
+ crypto_mem mem = {0};
++ symc_encrypt_t local_crypt;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ADDR_VIA(input) == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ADDR_VIA(output) == HI_NULL);
-+ HI_LOG_CHECK_PARAM(length == 0x00);
++ hi_log_chk_param_return(crypt == HI_NULL);
++ hi_log_chk_param_return(addr_via(crypt->in) == HI_NULL);
++ hi_log_chk_param_return(addr_via(crypt->out) == HI_NULL);
++ hi_log_chk_param_return(crypt->len == 0x00);
+
-+ ret = crypto_mem_create(&mem, SEC_MMZ, "AES_IN", length);
++ crypto_memset(&local_crypt, sizeof(local_crypt), 0, sizeof(local_crypt));
++
++ ret = crypto_mem_create(&mem, SEC_MMZ, "AES_IN", crypt->len);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_create, ret);
++ hi_log_print_func_err(crypto_mem_create, ret);
+ return ret;
+ }
+
+ if (is_from_user == HI_TRUE) {
-+ ret = crypto_copy_from_user(mem.dma_virt, ADDR_VIA(input), length);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_copy_from_user, ret);
-+ goto exit;
-+ }
++ crypto_chk_err_exit(crypto_copy_from_user(mem.dma_virt, addr_via(crypt->in), crypt->len));
+ } else {
-+ crypto_memcpy(mem.dma_virt, length, ADDR_VIA(input), length);
++ crypto_memcpy(mem.dma_virt, crypt->len, addr_via(crypt->in), crypt->len);
+ }
+
-+ ret = kapi_symc_crypto(id, mem.dma_addr, mem.dma_addr, length, operation & 0x01, last);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_crypto, ret);
-+ goto exit;
-+ }
++ local_crypt.id = crypt->id;
++ local_crypt.in = mem.dma_addr;
++ local_crypt.out = mem.dma_addr;
++ local_crypt.len = crypt->len;
++ local_crypt.last = crypt->last;
++ local_crypt.operation = crypt->operation & SYMC_OPERATION_DECRYPT;
++ crypto_chk_err_exit(kapi_symc_crypto(&local_crypt));
+
+ if (is_from_user == HI_TRUE) {
-+ ret = crypto_copy_to_user(ADDR_VIA(output), mem.dma_virt, length);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_copy_to_user, ret);
-+ goto exit;
-+ }
++ crypto_chk_err_exit(crypto_copy_to_user(addr_via(crypt->out), mem.dma_virt, crypt->len));
+ } else {
-+ crypto_memcpy(ADDR_VIA(output), length, mem.dma_virt, length);
++ crypto_memcpy(addr_via(crypt->out), crypt->len, mem.dma_virt, crypt->len);
+ }
+
-+exit:
++exit__:
+ ret_exit = crypto_mem_destory(&mem);
+ if (ret_exit != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mem_destory, ret_exit);
-+ HI_ERR_PRINT_S32(ret);
++ hi_log_print_func_err(crypto_mem_destory, ret_exit);
+ return ret_exit;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return ret;
+}
+
-+static hi_s32 kapi_symc_crypto_multi_start(kapi_symc_ctx *ctx, const void *pkg, hi_u32 pkg_num, hi_u32 operation, hi_u32 wait)
++static hi_s32 kapi_symc_chk_multi_pack(hi_cipher_data *tmp, hi_cipher_data *pack)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ void *buf = HI_NULL, *temp = HI_NULL;
-+ compat_addr *input = HI_NULL;
-+ compat_addr *output = HI_NULL;
-+ symc_node_usage *usage = HI_NULL;
++ hi_s32 ret;
++
++ /* copy node list from user space to kernel. */
++ ret = crypto_copy_from_user(tmp, pack, sizeof(hi_cipher_data));
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(crypto_copy_from_user, ret);
++ return ret;
++ }
++
++ if (tmp->src_phys_addr + tmp->byte_len < tmp->byte_len) {
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ if (tmp->dst_phys_addr + tmp->byte_len < tmp->byte_len) {
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ if ((tmp->odd_key != HI_TRUE) && (tmp->odd_key != HI_FALSE)) {
++ hi_log_error("invalid odd key for multicipher crypt!\n");
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARAM);
++ return HI_ERR_CIPHER_INVALID_PARAM;
++ }
++
++ ret = cipher_check_mmz_phy_addr(tmp->src_phys_addr, tmp->byte_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cipher_check_mmz_phy_addr, ret);
++ return ret;
++ }
++
++ ret = cipher_check_mmz_phy_addr(tmp->dst_phys_addr, tmp->byte_len);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(cipher_check_mmz_phy_addr, ret);
++ return ret;
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_void kapi_symc_multi_pack_set_mem(symc_multi_pack *pack, hi_u8 *buf, hi_u32 size)
++{
++ hi_u8 *tmp = buf;
++ hi_u32 pack_num = pack->num;
++
++ crypto_unused(size);
++
++ tmp = buf;
++ pack->in = (compat_addr *)tmp;
++
++ tmp = (hi_u8 *)tmp + sizeof(compat_addr) * pack_num; /* descrypt: buf + input. */
++ pack->out = (compat_addr *)tmp;
++
++ tmp = (hi_u8 *)tmp + sizeof(compat_addr) * pack_num; /* descrypt: buf + input + output. */
++ pack->usage = (symc_node_usage *)tmp;
++
++ tmp = (hi_u8 *)tmp + sizeof(symc_node_usage) * pack_num; /* descrypt: buf + input + output + usage. */
++ pack->len = (hi_u32 *)tmp;
++}
++
++static hi_s32 kapi_symc_crypto_multi_start(kapi_symc_ctx *ctx, const hi_void *pkg, hi_u32 pkg_num, hi_u32 operation,
++ hi_u32 wait)
++{
++ hi_s32 ret;
++ hi_void *buf = HI_NULL;
+ hi_cipher_data pkg_tmp;
-+ hi_u32 *length = HI_NULL;
-+ hi_u32 size = 0;
-+ hi_u32 i;
++ hi_u32 i, size;
++ symc_multi_pack pack;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(ctx->func == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->func->crypto == HI_NULL);
-+ HI_LOG_CHECK_PARAM(pkg == HI_NULL);
-+ HI_LOG_CHECK_PARAM(pkg_num > MAX_PKG_NUMBER);
-+ HI_LOG_CHECK_PARAM(pkg_num == 0x00);
++ hi_log_chk_param_return((ctx == HI_NULL) || (ctx->func == HI_NULL) || (ctx->func->crypto == HI_NULL));
++ hi_log_chk_param_return((pkg == HI_NULL) || (pkg_num > MAX_PKG_NUMBER) || (pkg_num == 0x00));
+
+ /* size of input:output:usage:length */
-+ size = (sizeof(compat_addr) + sizeof(compat_addr) + sizeof(hi_u32) + sizeof(hi_u32)) * pkg_num;
-+
-+ buf = crypto_malloc(size);
++ size = (sizeof(compat_addr) + sizeof(compat_addr) + sizeof(symc_node_usage) + sizeof(hi_u32)) * pkg_num;
++ buf = crypto_calloc(1, size);
+ if (buf == HI_NULL) {
-+ HI_LOG_ERROR("Malloc for pkg failed.\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_malloc, ret);
++ hi_log_print_func_err(crypto_calloc, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ temp = buf;
-+ input = (compat_addr *)temp;
-+ temp = (hi_u8 *)temp + sizeof(compat_addr) * pkg_num; /*buf + input*/
-+ output = (compat_addr *)temp;
-+ temp = (hi_u8 *)temp + sizeof(compat_addr) * pkg_num; /*buf + input + output*/
-+ usage = temp;
-+ temp = (hi_u8 *)temp + sizeof(hi_u32) * pkg_num; /*buf + input + output + usage*/
-+ length = temp;
++ crypto_memset(&pack, sizeof(pack), 0, sizeof(pack));
+
-+ /*Compute and check the nodes length*/
++ pack.num = pkg_num;
++ kapi_symc_multi_pack_set_mem(&pack, buf, size);
++
++ /* Compute and check the nodes length. */
+ for (i = 0; i < pkg_num; i++) {
-+ /*copy node list from user space to kernel*/
-+ ret = crypto_copy_from_user(&pkg_tmp, (hi_u8 *)pkg + sizeof(hi_cipher_data) * i,
-+ sizeof(hi_cipher_data));
++ ret = kapi_symc_chk_multi_pack(&pkg_tmp, (hi_cipher_data *)((hi_u8 *)pkg + sizeof(hi_cipher_data) * i));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("copy data from user fail!\n");
-+ HI_LOG_PRINT_FUNC_ERR(crypto_copy_from_user, ret);
++ hi_log_print_func_err(kapi_symc_chk_multi_pack, ret);
+ crypto_free(buf);
+ buf = HI_NULL;
+ return ret;
+ }
+
-+ if (pkg_tmp.src_phy_addr + pkg_tmp.byte_length < pkg_tmp.byte_length) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ crypto_free(buf);
-+ buf = HI_NULL;
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
++ addr_u64(pack.in[i]) = pkg_tmp.src_phys_addr;
++ addr_u64(pack.out[i]) = pkg_tmp.dst_phys_addr;
++ pack.len[i] = pkg_tmp.byte_len;
++ pack.usage[i] = SYMC_NODE_USAGE_EVEN_KEY;
+
-+ if (pkg_tmp.dest_phy_addr + pkg_tmp.byte_length < pkg_tmp.byte_length) {
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ crypto_free(buf);
-+ buf = HI_NULL;
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ if ((pkg_tmp.odd_key != HI_TRUE) && (pkg_tmp.odd_key != HI_FALSE)) {
-+ HI_LOG_ERROR("invalid odd key for multicipher crypt!\n");
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);
-+ crypto_free(buf);
-+ buf = HI_NULL;
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+ }
-+
-+ ret = cipher_check_mmz_phy_addr(pkg_tmp.src_phy_addr, pkg_tmp.byte_length);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Invalid output mmz phy addr for multicipher crypt.\n");
-+ HI_LOG_PRINT_FUNC_ERR(cipher_check_mmz_phy_addr, ret);
-+ crypto_free(buf);
-+ buf = HI_NULL;
-+ return ret;
-+ }
-+
-+ ret = cipher_check_mmz_phy_addr(pkg_tmp.dest_phy_addr, pkg_tmp.byte_length);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Invalid output mmz phy addr for multicipher crypt.\n");
-+ HI_LOG_PRINT_FUNC_ERR(cipher_check_mmz_phy_addr, ret);
-+ crypto_free(buf);
-+ buf = HI_NULL;
-+ return ret;
-+ }
-+
-+ ADDR_U64(input[i]) = pkg_tmp.src_phy_addr;
-+ ADDR_U64(output[i]) = pkg_tmp.dest_phy_addr;
-+ length[i] = pkg_tmp.byte_length;
-+ usage[i] = SYMC_NODE_USAGE_EVEN_KEY;
-+
-+ HI_LOG_DEBUG("pkg %d, in 0x%x, out 0x%x, length 0x%x, usage 0x%x\n", i,
-+ ADDR_L32(input[i]), ADDR_L32(output[i]), length[i], usage[i]);
++ hi_log_debug("pkg %d, in 0x%x, out 0x%x, length 0x%x, usage 0x%x\n", i, addr_l32(pack.in[i]),
++ addr_l32(pack.out[i]), pack.len[i], pack.usage[i]);
+ }
+
-+ ret = ctx->func->crypto(ctx->cryp_ctx, operation, input,
-+ output, length, usage, pkg_num, wait);
++ ret = ctx->func->crypto(ctx->cryp_ctx, operation, &pack, wait);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_symc_crypto, ret);
++ hi_log_print_func_err(ctx->func->crypto, ret);
+ crypto_free(buf);
+ buf = HI_NULL;
+ return ret;
@@ -252144,130 +320755,119 @@ index 0000000..7d96ea8
+ crypto_free(buf);
+ buf = HI_NULL;
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 kapi_symc_crypto_multi(hi_u32 id, const void *pkg, hi_u32 pkg_num, hi_u32 operation, hi_u32 last)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_symc_ctx *ctx = HI_NULL;
-+ hi_u32 soft_id = 0;
++ hi_u32 soft_id;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ KAPI_SYMC_CHECK_HANDLE(id);
-+ soft_id = HI_HANDLE_GET_CHNID(id);
-+ ctx = &kapi_ctx[soft_id];
-+ CHECK_OWNER(&ctx->owner);
-+ HI_LOG_CHECK_PARAM(ctx->func == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->config != HI_TRUE);
-+ HI_LOG_CHECK_PARAM((operation != 0x00) && (operation != 0x01));
-+
-+ KAPI_SYMC_LOCK();
-+
-+ ret = kapi_symc_crypto_multi_start(ctx, pkg, pkg_num, operation, HI_TRUE);
++ ret = kapi_symc_chk_handle((hi_handle)id);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(kapi_symc_crypto_multi_start, ret);
-+ KAPI_SYMC_UNLOCK();
++ hi_log_print_func_err(kapi_symc_chk_handle, ret);
+ return ret;
+ }
+
-+ KAPI_SYMC_UNLOCK();
++ soft_id = hi_handle_get_chnid(id);
++ ctx = &g_kapi_ctx[soft_id];
++ crypto_chk_owner_err_return(&ctx->owner);
++ hi_log_chk_param_return(ctx->func == HI_NULL);
++ hi_log_chk_param_return(ctx->config != HI_TRUE);
++ hi_log_chk_param_return((operation != 0x00) && (operation != 0x01));
+
-+ HI_LOG_FUNC_EXIT();
++ kapi_symc_lock_err_return();
++
++ ret = kapi_symc_crypto_multi_start(ctx, pkg, pkg_num, operation, HI_TRUE);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_crypto_multi_start, ret);
++ kapi_symc_unlock();
++ return ret;
++ }
++
++ kapi_symc_unlock();
++
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
+
+hi_s32 kapi_aead_get_tag(hi_u32 id, hi_u32 tag[AEAD_TAG_SIZE_IN_WORD], hi_u32 *taglen)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ kapi_symc_ctx *ctx = HI_NULL;
-+ hi_u32 soft_id = 0;
++ hi_u32 soft_id;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(tag == HI_NULL);
-+ HI_LOG_CHECK_PARAM(taglen == HI_NULL);
-+ HI_LOG_CHECK_PARAM(*taglen != AES_CCM_MAX_TAG_LEN);
++ hi_log_chk_param_return(tag == HI_NULL);
++ hi_log_chk_param_return(taglen == HI_NULL);
++ hi_log_chk_param_return(*taglen != AES_CCM_MAX_TAG_LEN);
+
-+ KAPI_SYMC_CHECK_HANDLE(id);
-+ soft_id = HI_HANDLE_GET_CHNID(id);
-+ ctx = &kapi_ctx[soft_id];
-+ CHECK_OWNER(&ctx->owner);
-+ HI_LOG_CHECK_PARAM(ctx->func == HI_NULL);
-+ HI_LOG_CHECK_PARAM(ctx->func->gettag == HI_NULL);
++ ret = kapi_symc_chk_handle((hi_handle)id);
++ if (ret != HI_SUCCESS) {
++ hi_log_print_func_err(kapi_symc_chk_handle, ret);
++ return ret;
++ }
+
-+ KAPI_SYMC_LOCK();
++ soft_id = hi_handle_get_chnid(id);
++ ctx = &g_kapi_ctx[soft_id];
++ crypto_chk_owner_err_return(&ctx->owner);
++ hi_log_chk_param_return(ctx->func == HI_NULL);
++ hi_log_chk_param_return(ctx->func->gettag == HI_NULL);
++
++ kapi_symc_lock_err_return();
+
+ if (ctx->func->gettag) {
+ ret = ctx->func->gettag(ctx->cryp_ctx, tag, taglen);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(cryp_aead_get_tag, ret);
-+ KAPI_SYMC_UNLOCK();
++ hi_log_print_func_err(cryp_aead_get_tag, ret);
++ kapi_symc_unlock();
+ return ret;
+ }
+ }
+
-+ KAPI_SYMC_UNLOCK();
++ kapi_symc_unlock();
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_trng.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_trng.c
new file mode 100644
-index 0000000..e4f1fda
+index 0000000..725dee6
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/kapi_trng.c
-@@ -0,0 +1,46 @@
+@@ -0,0 +1,27 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for kapi trng.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
+#include "cryp_trng.h"
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup trng */
-+/** @{*/ /** <!-- [kapi]*/
-+
++/* ****************************** API Code **************************** */
+hi_s32 kapi_trng_get_random(hi_u32 *randnum, hi_u32 timeout)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ HI_LOG_FUNC_ENTER();
++ hi_log_func_enter();
+
-+ HI_LOG_CHECK_PARAM(randnum == HI_NULL);
++ hi_log_chk_param_return(randnum == HI_NULL);
+
+ ret = cryp_trng_get_random(randnum, timeout);
+ if (ret != HI_SUCCESS) {
+ return ret;
+ }
+
-+ HI_LOG_FUNC_EXIT();
++ hi_log_func_exit();
+ return HI_SUCCESS;
+}
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/build.mak b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/build.mak
new file mode 100644
index 0000000..ebe2c52
@@ -252286,26 +320886,15 @@ index 0000000..ebe2c52
+
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_init_linux.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_init_linux.c
new file mode 100644
-index 0000000..53b777a
+index 0000000..2526a01
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_init_linux.c
-@@ -0,0 +1,288 @@
+@@ -0,0 +1,252 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for linux drv osal init of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include <linux/proc_fs.h>
@@ -252336,28 +320925,24 @@ index 0000000..53b777a
+#include "drv_symc.h"
+#include "drv_hash.h"
+
-+/************************ Internal Structure Definition *********************/
++#ifdef KAPI_TEST_SUPPORT
++#include "kapi_symc_test.h"
++#endif
+
+#define CIPHER_PROC_NAME "driver/hi_cipher"
+
-+extern hi_s32 crypto_ioctl(hi_u32 cmd, hi_void *argp);
-+extern hi_s32 crypto_entry(void);
-+extern hi_s32 crypto_exit(void);
-+hi_s32 crypto_release(void);
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup link*/
-+/** @{*/ /** <!-- [link]*/
-+
-+/******* proc function begin ********/
++/* ****************************** API Code **************************** */
+#if (1 == HI_PROC_SUPPORT)
+hi_s32 symc_proc_read(struct seq_file *p, hi_void *v)
+{
+ symc_chn_status *status = HI_NULL;
-+ int i = 0;
-+ hi_s32 ret = HI_SUCCESS;
++ int i;
++ hi_s32 ret;
++
++ if (p == HI_NULL || v == HI_NULL) {
++ hi_log_error("Invalid point\n");
++ return HI_ERR_CIPHER_INVALID_POINT;
++ }
+
+ seq_printf(p, "\n------------------------------------------"
+ "CIPHER STATUS-------------------------------"
@@ -252367,13 +320952,12 @@ index 0000000..53b777a
+ "Addr in/out KeyFrom INT-RAW in/out INT-EN "
+ "in/out INT_OCNTCFG IVOUT\n");
+
-+ status = (symc_chn_status *)crypto_malloc(8 * sizeof(symc_chn_status));
++ status = (symc_chn_status *)crypto_calloc(CRYPTO_HARD_CHANNEL_MAX, sizeof(symc_chn_status));
+ if (status == HI_NULL) {
-+ return HI_FAILURE;
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ crypto_memset(status, 8 * sizeof(symc_chn_status), 0, 8 * sizeof(symc_chn_status));
-+ for (i = 0; i < 8; i++) {
++ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
+ status[i].id = i;
+ }
+
@@ -252382,7 +320966,7 @@ index 0000000..53b777a
+ seq_printf(p, "CIPHER_ProcGetStatus failed!\n");
+ crypto_free(status);
+ status = NULL;
-+ return HI_FAILURE;
++ return ret;
+ }
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
@@ -252406,11 +320990,7 @@ index 0000000..53b777a
+ }
+
+#ifdef KAPI_TEST_SUPPORT
-+ {
-+ extern hi_s32 kapi_test_main(void);
-+
-+ kapi_test_main();
-+ }
++ kapi_test_main();
+#endif
+
+ crypto_free(status);
@@ -252424,21 +321004,21 @@ index 0000000..53b777a
+ return single_open(file, symc_proc_read, NULL);
+}
+
-+static const struct file_operations DRV_CIPHER_ProcFops = {
-+ .owner = THIS_MODULE,
-+ .open = symc_proc_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
++static const struct file_operations g_drv_cipher_proc_fops = {
++ .owner = THIS_MODULE,
++ .open = symc_proc_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
+};
+
+static hi_void symc_proc_init(hi_void)
+{
+ struct proc_dir_entry *proc_entry = HI_NULL;
+
-+ proc_entry = proc_create(CIPHER_PROC_NAME, 0, NULL, &DRV_CIPHER_ProcFops);
++ proc_entry = proc_create(CIPHER_PROC_NAME, 0, NULL, &g_drv_cipher_proc_fops);
+ if (proc_entry == NULL) {
-+ HI_LOG_ERROR("cipher: can't create %s.\n", CIPHER_PROC_NAME);
++ hi_log_error("cipher: can't create %s.\n", CIPHER_PROC_NAME);
+ }
+}
+
@@ -252446,15 +321026,7 @@ index 0000000..53b777a
+{
+ remove_proc_entry(CIPHER_PROC_NAME, NULL);
+}
-+#endif
-+/******* proc function end ********/
-+
-+
-+hi_s32 _crypto_ioctl(struct inode *inode, struct file *file,
-+ hi_u32 cmd, hi_void *arg)
-+{
-+ return crypto_ioctl(cmd, arg);
-+}
++#endif /* ****** proc function end ******* */
+
+static hi_s32 hi_cipher_open(struct inode *inode, struct file *file)
+{
@@ -252466,40 +321038,38 @@ index 0000000..53b777a
+
+static long hi_cipher_ioctl(struct file *ffile, unsigned int cmd, unsigned long arg)
+{
-+ long ret = HI_SUCCESS;
-+ hi_u8 unCmdParam[256] = {0};
++ long ret;
++ hi_u8 cmd_param[CRYPTO_CMD_PARAM_SIZE] = {0};
+
+ if ((ffile == HI_NULL) || (ffile->f_path.dentry == HI_NULL) || (arg == 0x00)) {
-+ HI_LOG_ERROR("Invalid cmd param size!\n");
++ hi_log_error("Invalid cmd param size!\n");
+ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
-+ if (_IOC_SIZE(cmd) > sizeof(unCmdParam)) {
-+ HI_LOG_ERROR("Invalid cmd param size %d!\n", _IOC_SIZE(cmd));
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ if (_IOC_SIZE(cmd) > sizeof(cmd_param)) {
++ hi_log_error("Invalid cmd param size %d!\n", _IOC_SIZE(cmd));
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
-+ if (((CRYPTO_IOC_DIR(cmd) == CRYPTO_IOC_W) || (CRYPTO_IOC_DIR(cmd) == CRYPTO_IOC_RW))
-+ && (_IOC_SIZE(cmd) != 0)) {
-+ ret = copy_from_user((hi_void *)unCmdParam, (void __user *)(HI_UINTPTR_T)arg, _IOC_SIZE(cmd));
++ if (((crypto_ioc_dir(cmd) == CRYPTO_IOC_W) || (crypto_ioc_dir(cmd) == CRYPTO_IOC_RW)) && (_IOC_SIZE(cmd) != 0)) {
++ ret = copy_from_user((hi_void *)cmd_param, (void __user *)(hi_uintptr_t)arg, _IOC_SIZE(cmd));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("copy data from user failed, ret:0x%lx!\n", ret);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("copy data from user failed, ret:0x%lx!\n", ret);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
+
-+ ret = _crypto_ioctl(ffile->f_path.dentry->d_inode, ffile, cmd, (hi_void *)unCmdParam);
++ ret = crypto_ioctl(cmd, (hi_void *)cmd_param);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("copy data from user failed, ret:0x%lx!\n", ret);
++ hi_log_error("copy data from user failed, ret:0x%lx!\n", ret);
+ return ret;
+ }
+
-+ if (((CRYPTO_IOC_DIR(cmd) == CRYPTO_IOC_R) || (CRYPTO_IOC_DIR(cmd) == CRYPTO_IOC_RW))
-+ && (_IOC_SIZE(cmd) != 0)) {
-+ ret = copy_to_user((void __user *)(HI_UINTPTR_T)arg, (const hi_void *)unCmdParam, _IOC_SIZE(cmd));
++ if (((crypto_ioc_dir(cmd) == CRYPTO_IOC_R) || (crypto_ioc_dir(cmd) == CRYPTO_IOC_RW)) && (_IOC_SIZE(cmd) != 0)) {
++ ret = copy_to_user((hi_void __user *)(hi_uintptr_t)arg, (const hi_void *)cmd_param, _IOC_SIZE(cmd));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("copy data to user fail, ret:0x%lx!\n", ret);
-+ return HI_ERR_CIPHER_INVALID_PARA;
++ hi_log_error("copy data to user fail, ret:0x%lx!\n", ret);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+ }
+ return HI_SUCCESS;
@@ -252510,7 +321080,7 @@ index 0000000..53b777a
+ return crypto_release();
+}
+
-+static struct file_operations dev_cipher_fops = {
++static struct file_operations g_dev_cipher_fops = {
+ .owner = THIS_MODULE,
+ .open = hi_cipher_open,
+ .unlocked_ioctl = hi_cipher_ioctl,
@@ -252520,42 +321090,41 @@ index 0000000..53b777a
+ .release = hi_cipher_release,
+};
+
-+static struct miscdevice cipher_dev = {
++static struct miscdevice g_cipher_dev = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = UMAP_DEVNAME_CIPHER,
-+ .fops = &dev_cipher_fops,
++ .fops = &g_dev_cipher_fops,
+};
+
-+void *cipher_get_device(void)
++hi_void *cipher_get_device(hi_void)
+{
-+ return (void *)cipher_dev.this_device;
++ return (hi_void *)g_cipher_dev.this_device;
+}
+
-+int cipher_drv_mod_init(void)
++hi_s32 cipher_drv_mod_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ if (misc_register(&cipher_dev)) {
-+ HI_LOG_ERROR("ERROR: could not register cipher devices\n");
-+ return -1;
++ if (misc_register(&g_cipher_dev)) {
++ hi_log_error("ERROR: could not register cipher devices\n");
++ return HI_ERR_CIPHER_ILLEGAL_DATA;
+ }
+
+ /* dma data structure shall be initialised before being used in Kernel 4.9
+ * or else call dma_set_coherent_mask/dma_alloc_coherent will return error
+ */
-+ of_dma_configure(cipher_dev.this_device, cipher_dev.this_device->of_node);
++ of_dma_configure(g_cipher_dev.this_device, g_cipher_dev.this_device->of_node);
+
+ ret = crypto_entry();
+ if (ret != HI_SUCCESS) {
-+ misc_deregister(&cipher_dev);
-+ return HI_FAILURE;
++ misc_deregister(&g_cipher_dev);
++ return ret;
+ }
+
-+ /******* proc function begin ********/
++ /* ****** proc function begin ******* */
+#if (1 == HI_PROC_SUPPORT)
+ symc_proc_init();
-+#endif
-+ /******* proc function end ********/
++#endif /* ****** proc function end ******* */
+
+#ifdef MODULE
+ HI_PRINT("Load hi_cipher.ko success.\n");
@@ -252566,68 +321135,45 @@ index 0000000..53b777a
+
+void cipher_drv_mod_exit(void)
+{
-+ /******* proc function begin ********/
++ /* ****** proc function begin ******* */
+#if (1 == HI_PROC_SUPPORT)
+ symc_proc_deinit();
-+#endif
-+ /******* proc function end ********/
-+ misc_deregister(&cipher_dev);
++#endif /* ****** proc function end ******* */
++ misc_deregister(&g_cipher_dev);
+ crypto_exit();
-+
-+ return ;
+}
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_init_liteos.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_init_liteos.c
new file mode 100644
-index 0000000..9179da0
+index 0000000..5facd17
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_init_liteos.c
-@@ -0,0 +1,186 @@
+@@ -0,0 +1,149 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for liteos drv osal init of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
+#include "drv_symc.h"
+#include "drv_hash.h"
+
-+/************************ Internal Structure Definition *********************/
++/* *********************** Internal Structure Definition ******************** */
++static osal_dev_t *g_cipher_device;
+
-+extern hi_s32 crypto_ioctl(hi_u32 cmd, hi_void *argp);
-+extern hi_s32 crypto_entry(void);
-+extern hi_s32 crypto_exit(void);
-+extern hi_s32 crypto_recover_hdcp_key(void);
-+
-+static osal_dev_t *cipher_device;
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup link*/
-+/** @{*/ /** <!-- [link]*/
-+
-+/******* proc function begin ********/
++/* ****** proc function begin ******* */
+#if (1 == HI_PROC_SUPPORT)
+hi_s32 symc_proc_read(struct osal_proc_dir_entry *p)
+{
+ symc_chn_status *status = HI_NULL;
-+ int i = 0;
-+ hi_s32 ret = HI_SUCCESS;
++ hi_s32 i;
++ hi_s32 ret;
++
++ if (p == HI_NULL) {
++ hi_log_error("Invalid point\n");
++ return HI_ERR_CIPHER_INVALID_POINT;
++ }
+
+ PROC_PRINT(p, "\n------------------------------------------"
+ "CIPHER STATUS-------------------------------"
@@ -252637,14 +321183,13 @@ index 0000000..9179da0
+ "Addr in/out KeyFrom INT-RAW in/out INT-EN "
+ "in/out INT_OCNTCFG IVOUT\n");
+
-+ status = (symc_chn_status *)crypto_malloc(sizeof(symc_chn_status) * 8);
++ status = (symc_chn_status *)crypto_calloc(CRYPTO_HARD_CHANNEL_MAX, sizeof(symc_chn_status));
+ if (status == HI_NULL) {
+ PROC_PRINT(p, "crypto malloc for status buff failed!\n");
-+ return HI_FAILURE;
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ crypto_memset(status, sizeof(symc_chn_status) * 8, 0, sizeof(symc_chn_status) * 8);
-+ for (i = 0; i < 8; i++) {
++ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
+ status[i].id = i;
+ }
+
@@ -252653,27 +321198,18 @@ index 0000000..9179da0
+ PROC_PRINT(p, "CIPHER_ProcGetStatus failed!\n");
+ crypto_free(status);
+ status = HI_NULL;
-+ return HI_FAILURE;
++ return ret;
+ }
+
+ for (i = 0; i < CRYPTO_HARD_CHANNEL_MAX; i++) {
+ PROC_PRINT(p, " %d %s %d %s %s %03d %08x/%08x "
+ " %s %d/%d %d/%d %08x %s\n",
+ i,
-+ status[i].open,
-+ status[i].decrypt,
-+ status[i].alg,
-+ status[i].mode,
-+ status[i].klen,
-+ status[i].inaddr,
-+ status[i].outaddr,
-+ status[i].ksrc,
-+ status[i].inraw,
-+ status[i].outraw,
-+ status[i].inten,
-+ status[i].outen,
-+ status[i].outintcnt,
-+ status[i].iv);
++ status[i].open, status[i].decrypt, status[i].alg,
++ status[i].mode, status[i].klen, status[i].inaddr,
++ status[i].outaddr, status[i].ksrc, status[i].inraw,
++ status[i].outraw, status[i].inten, status[i].outen,
++ status[i].outintcnt, status[i].iv);
+ }
+ crypto_free(status);
+ status = HI_NULL;
@@ -252687,7 +321223,7 @@ index 0000000..9179da0
+
+ proc_entry = osal_create_proc_entry(UMAP_DEVNAME_CIPHER, HI_NULL);
+ if (proc_entry == HI_NULL) {
-+ HI_LOG_ERROR("cipher: can't create proc.\n");
++ hi_log_error("cipher: can't create proc.\n");
+ return;
+ }
+ proc_entry->read = symc_proc_read;
@@ -252697,15 +321233,14 @@ index 0000000..9179da0
+{
+ osal_remove_proc_entry(UMAP_DEVNAME_CIPHER, NULL);
+}
-+#endif
-+/******* proc function end ********/
++#endif /* ****** proc function end ******* */
+
-+static long hi_cipher_ioctl(hi_u32 cmd, unsigned long arg, void *private_data)
++static long hi_cipher_ioctl(hi_u32 cmd, unsigned long arg, hi_void *private_data)
+{
-+ return crypto_ioctl(cmd, (void *)arg);
++ return crypto_ioctl(cmd, (hi_void *)arg);
+}
+
-+static osal_fileops_t dev_cipher_fops = {
++static osal_fileops_t g_dev_cipher_fops = {
+ .open = HI_NULL,
+ .unlocked_ioctl = hi_cipher_ioctl,
+#ifdef CONFIG_COMPAT
@@ -252714,18 +321249,17 @@ index 0000000..9179da0
+ .release = HI_NULL,
+};
+
-+int cipher_drv_mod_init(void)
++hi_s32 cipher_drv_mod_init(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ cipher_device = osal_createdev(UMAP_DEVNAME_CIPHER);
-+ cipher_device->fops = &dev_cipher_fops;
-+ cipher_device->minor = UMAP_MIN_MINOR_CIPHER;
++ g_cipher_device = osal_createdev(UMAP_DEVNAME_CIPHER);
++ g_cipher_device->fops = &g_dev_cipher_fops;
++ g_cipher_device->minor = UMAP_MIN_MINOR_CIPHER;
+
-+
-+ ret = osal_registerdevice(cipher_device);
++ ret = osal_registerdevice(g_cipher_device);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("register CIPHER failed.\n");
++ hi_log_error("register CIPHER failed.\n");
+ return ret;
+ }
+
@@ -252734,11 +321268,10 @@ index 0000000..9179da0
+ goto error;
+ }
+
-+ /******* proc function begin ********/
++ /* ****** proc function begin ******* */
+#if (1 == HI_PROC_SUPPORT)
+ symc_proc_init();
-+#endif
-+ /******* proc function end ********/
++#endif /* ****** proc function end ******* */
+
+#ifdef MODULE
+ HI_PRINT("Load hi_cipher.ko success.\n");
@@ -252747,62 +321280,40 @@ index 0000000..9179da0
+ return HI_SUCCESS;
+
+error:
-+ osal_deregisterdevice(cipher_device);
-+ osal_destroydev(cipher_device);
++ osal_deregisterdevice(g_cipher_device);
++ osal_destroydev(g_cipher_device);
+
+ return ret;
+}
+
-+void cipher_drv_mod_exit(void)
++hi_void cipher_drv_mod_exit(hi_void)
+{
-+
-+ /******* proc function begin ********/
++ /* ****** proc function begin ******* */
+#if (1 == HI_PROC_SUPPORT)
+ symc_proc_deinit();
-+#endif
-+ /******* proc function end ********/
++#endif /* ****** proc function end ******* */
+
+ (hi_void)crypto_exit();
-+ osal_deregisterdevice(cipher_device);
-+ osal_destroydev(cipher_device);
-+
-+ return ;
++ osal_deregisterdevice(g_cipher_device);
++ osal_destroydev(g_cipher_device);
+}
-+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_sys_linux.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_sys_linux.c
new file mode 100644
-index 0000000..5503967
+index 0000000..60e9014
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_sys_linux.c
-@@ -0,0 +1,520 @@
+@@ -0,0 +1,492 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for osal sys linux of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
+#include <linux/dmapool.h>
+#include <asm/cacheflush.h>
+
-+/************************* Internal Structure Definition *********************/
-+/** \addtogroup base type*/
-+/** @{*/ /** <!-- [base]*/
-+
-+
+/* under TEE, we only can malloc secure mmz at system steup,
+ * then map the mmz to Smmu, but the smmu can't map to cpu address,
+ * so we must save the cpu address in a static table when malloc and map mmz.
@@ -252815,10 +321326,10 @@ index 0000000..5503967
+typedef struct {
+ hi_u32 valid;
+ compat_addr dma;
-+ void *via;
++ hi_void *via;
+} crypto_mem_map_table;
+
-+static crypto_mem_map_table loacl_map_table[CRYPTO_MEM_MAP_TABLE_DEPTH];
++static crypto_mem_map_table g_loacl_map_table[CRYPTO_MEM_MAP_TABLE_DEPTH];
+
+#ifdef CONFIG_64BIT
+#define crypto_flush_dcache_area __flush_dcache_area
@@ -252826,77 +321337,75 @@ index 0000000..5503967
+#define crypto_flush_dcache_area __cpuc_flush_dcache_area
+#endif
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++/* in 32-bit system. */
++#define SYS_32BITS 32
+
-+/******************************* API Code *****************************/
-+/** \addtogroup base*/
-+/** @{*/ /** <!--[base]*/
++/* in 64-bit system. */
++#define SYS_64BITS 64
+
-+/*****************************************************************
-+ * mmz/mmu api *
-+ *****************************************************************/
++/* mmz/mmu api. */
+static hi_s32 cipher_dma_set_mask(struct device *dev)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+
-+ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
++ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(SYS_64BITS));
+ if (ret == HI_SUCCESS) {
+ return ret;
+ }
+
-+ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
++ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(SYS_32BITS));
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("Failed to set DMA mask %d.\n", ret);
++ hi_log_error("Failed to set DMA mask %d.\n", ret);
+ return ret;
+ }
+
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cipher_dma_alloc_coherent(crypto_mem *mem, hi_u32 type, char const *name, hi_u32 size)
++static hi_s32 cipher_dma_alloc_coherent(crypto_mem *mem, hi_u32 type, const hi_char *name, hi_u32 size)
+{
+ struct device *dev = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_s32 i;
+
+ if (mem == HI_NULL) {
-+ HI_LOG_ERROR("mem is null.\n");
-+ return HI_FAILURE;
++ hi_log_error("mem is null.\n");
++ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
+ if (size >= DMA_ALLOC_MAX_SIZE) {
-+ HI_LOG_ERROR("dma alloc coherent with invalid size(0x%x).\n", size);
-+ return HI_FAILURE;
++ hi_log_error("dma alloc coherent with invalid size(0x%x).\n", size);
++ return HI_ERR_CIPHER_INVALID_PARAM;
+ }
+
+ dev = (struct device *)cipher_get_device();
+ if (dev == HI_NULL) {
-+ HI_LOG_ERROR("cipher_get_device error.\n");
-+ return HI_FAILURE;
++ hi_log_error("cipher_get_device error.\n");
++ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
+ ret = cipher_dma_set_mask(dev);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("cipher dma set mask failed.\n");
++ hi_log_error("cipher dma set mask failed.\n");
+ return ret;
+ }
+
+ mem->dma_size = size;
-+ mem->dma_virt = dma_alloc_coherent(dev, mem->dma_size, (dma_addr_t *)(&ADDR_U64(mem->dma_addr)), GFP_ATOMIC);
++ mem->dma_virt = dma_alloc_coherent(dev, mem->dma_size, (dma_addr_t *)(&addr_u64(mem->dma_addr)), GFP_ATOMIC);
+ if (mem->dma_virt == HI_NULL) {
-+ HI_LOG_ERROR("dma_alloc_coherent error.\n");
-+ return HI_FAILURE;
++ hi_log_error("dma_alloc_coherent error.\n");
++ return HI_ERR_CIPHER_FAILED_MEM;
+ }
-+ ADDR_U64(mem->mmz_addr) = ADDR_U64(mem->dma_addr);
++ addr_u64(mem->mmz_addr) = addr_u64(mem->dma_addr);
+
-+ /* save the map info */
++ /* save the map info. */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if (loacl_map_table[i].valid == HI_FALSE) {
-+ ADDR_U64(loacl_map_table[i].dma) = ADDR_U64(mem->dma_addr);
-+ loacl_map_table[i].via = mem->dma_virt;
-+ loacl_map_table[i].valid = HI_TRUE;
-+ HI_LOG_DEBUG("map local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid == HI_FALSE) {
++ addr_u64(g_loacl_map_table[i].dma) = addr_u64(mem->dma_addr);
++ g_loacl_map_table[i].via = mem->dma_virt;
++ g_loacl_map_table[i].valid = HI_TRUE;
++ hi_log_debug("map local map %d, dam 0x%x, via 0x%p\n",
++ i, addr_u64(mem->dma_addr), mem->dma_virt);
+ break;
+ }
+ }
@@ -252907,13 +321416,13 @@ index 0000000..5503967
+static hi_s32 cipher_dma_free_coherent(crypto_mem *mem)
+{
+ struct device *dev = HI_NULL;
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_s32 i = 0;
+ crypto_mem mem_temp;
+
+ if (mem == HI_NULL) {
-+ HI_LOG_ERROR("mem is null.\n");
-+ return HI_FAILURE;
++ hi_log_error("mem is null.\n");
++ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
+ crypto_memset(&mem_temp, sizeof(mem_temp), 0, sizeof(mem_temp));
@@ -252921,27 +321430,25 @@ index 0000000..5503967
+
+ dev = (struct device *)cipher_get_device();
+ if (dev == NULL) {
-+ HI_LOG_ERROR("cipher_get_device error.\n");
-+ return HI_FAILURE;
++ hi_log_error("cipher_get_device error.\n");
++ return HI_ERR_CIPHER_INVALID_POINT;
+ }
+
+ ret = cipher_dma_set_mask(dev);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("cipher dma set mask failed.\n");
++ hi_log_error("cipher dma set mask failed.\n");
+ return ret;
+ }
+
-+ dma_free_coherent(dev, mem->dma_size, mem->dma_virt, ADDR_U64(mem->dma_addr));
++ dma_free_coherent(dev, mem->dma_size, mem->dma_virt, addr_u64(mem->dma_addr));
+
-+ /* remove the map info */
++ /* remove the map info. */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if ( loacl_map_table[i].valid &&
-+ ADDR_U64(loacl_map_table[i].dma) == ADDR_U64(mem_temp.dma_addr)) {
-+ ADDR_U64(loacl_map_table[i].dma) = 0x00;
-+ loacl_map_table[i].via = HI_NULL;
-+ loacl_map_table[i].valid = HI_FALSE;
-+ HI_LOG_DEBUG("unmap local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem_temp.dma_addr), mem_temp.dma_virt);
++ if (g_loacl_map_table[i].valid && addr_u64(g_loacl_map_table[i].dma) == addr_u64(mem_temp.dma_addr)) {
++ addr_u64(g_loacl_map_table[i].dma) = 0x00;
++ g_loacl_map_table[i].via = HI_NULL;
++ g_loacl_map_table[i].valid = HI_FALSE;
++ hi_log_debug("unmap local map %d, dam 0x%x, via 0x%p\n", i, addr_u64(mem_temp.dma_addr), mem_temp.dma_virt);
+ break;
+ }
+ }
@@ -252950,17 +321457,18 @@ index 0000000..5503967
+ return HI_SUCCESS;
+}
+
-+/*brief allocate and map a mmz or smmu memory
-+* we can't allocate smmu directly during TEE boot period.
-+* in addition, the buffer of cipher node list must be mmz.
-+* so here we have to allocate a mmz memory then map to smmu if necessary.
-+*/
-+static hi_s32 hash_mem_alloc_remap(crypto_mem *mem, hi_u32 type, char const *name, hi_u32 size)
++/*
++ * brief allocate and map a mmz or smmu memory
++ * we can't allocate smmu directly during TEE boot period.
++ * in addition, the buffer of cipher node list must be mmz.
++ * so here we have to allocate a mmz memory then map to smmu if necessary.
++ */
++static hi_s32 hash_mem_alloc_remap(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size)
+{
+ hi_u32 i;
+ crypto_memset(mem, sizeof(crypto_mem), 0, sizeof(crypto_mem));
+
-+ HI_LOG_DEBUG("mem_alloc_remap()- name %s, size 0x%x\n", name, size);
++ hi_log_debug("mem_alloc_remap()- name %s, size 0x%x\n", name, size);
+
+ mem->dma_size = size;
+ mem->dma_virt = kzalloc(size, GFP_KERNEL);
@@ -252968,8 +321476,8 @@ index 0000000..5503967
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ ADDR_U64(mem->mmz_addr) = virt_to_phys(mem->dma_virt);
-+ if (0 == ADDR_U64(mem->mmz_addr)) {
++ addr_u64(mem->mmz_addr) = virt_to_phys(mem->dma_virt);
++ if (addr_u64(mem->mmz_addr) == 0) {
+ if (mem->dma_virt != HI_NULL) {
+ kfree(mem->dma_virt);
+ mem->dma_virt = HI_NULL;
@@ -252978,21 +321486,21 @@ index 0000000..5503967
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ ADDR_U64(mem->dma_addr) = ADDR_U64(mem->mmz_addr);
++ addr_u64(mem->dma_addr) = addr_u64(mem->mmz_addr);
+
-+ HI_LOG_DEBUG("MMZ/MMU malloc, MMZ 0x%x, MMZ/MMU 0x%x, VIA 0x%p, SIZE 0x%x\n",
-+ ADDR_U64(mem->mmz_addr), ADDR_U64(mem->dma_addr), mem->dma_virt, size);
++ hi_log_debug("MMZ/MMU malloc, MMZ 0x%x, MMZ/MMU 0x%x, VIA 0x%p, SIZE 0x%x\n",
++ addr_u64(mem->mmz_addr), addr_u64(mem->dma_addr), mem->dma_virt, size);
+
+ mem->user_buf = HI_NULL;
+
-+ /* save the map info */
++ /* save the map info. */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if (loacl_map_table[i].valid == HI_FALSE) {
-+ ADDR_U64(loacl_map_table[i].dma) = ADDR_U64(mem->dma_addr);
-+ loacl_map_table[i].via = mem->dma_virt;
-+ loacl_map_table[i].valid = HI_TRUE;
-+ HI_LOG_DEBUG("map local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid == HI_FALSE) {
++ addr_u64(g_loacl_map_table[i].dma) = addr_u64(mem->dma_addr);
++ g_loacl_map_table[i].via = mem->dma_virt;
++ g_loacl_map_table[i].valid = HI_TRUE;
++ hi_log_debug("map local map %d, dam 0x%x, via 0x%p\n",
++ i, addr_u64(mem->dma_addr), mem->dma_virt);
+ break;
+ }
+ }
@@ -253000,7 +321508,7 @@ index 0000000..5503967
+ return HI_SUCCESS;
+}
+
-+/*brief release and unmap a mmz or smmu memory */
++/* brief release and unmap a mmz or smmu memory. */
+static hi_s32 hash_mem_release_unmap(crypto_mem *mem)
+{
+ hi_u32 i;
@@ -253008,15 +321516,15 @@ index 0000000..5503967
+ kfree(mem->dma_virt);
+ mem->dma_virt = HI_NULL;
+
-+ /* remove the map info */
++ /* remove the map info. */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if ( loacl_map_table[i].valid &&
-+ ADDR_U64(loacl_map_table[i].dma) == ADDR_U64(mem->dma_addr)) {
-+ ADDR_U64(loacl_map_table[i].dma) = 0x00;
-+ loacl_map_table[i].via = HI_NULL;
-+ loacl_map_table[i].valid = HI_FALSE;
-+ HI_LOG_DEBUG("unmap local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid &&
++ addr_u64(g_loacl_map_table[i].dma) == addr_u64(mem->dma_addr)) {
++ addr_u64(g_loacl_map_table[i].dma) = 0x00;
++ g_loacl_map_table[i].via = HI_NULL;
++ g_loacl_map_table[i].valid = HI_FALSE;
++ hi_log_debug("unmap local map %d, dam 0x%x, via 0x%p\n",
++ i, addr_u64(mem->dma_addr), mem->dma_virt);
+ break;
+ }
+ }
@@ -253025,66 +321533,61 @@ index 0000000..5503967
+ return HI_SUCCESS;
+}
+
-+static hi_s32 crypto_mem_alloc_remap(crypto_mem *mem, hi_u32 type, char const *name, hi_u32 size)
++static hi_s32 crypto_mem_alloc_remap(crypto_mem *mem, hi_u32 type, const hi_char *name, hi_u32 size)
+{
+ return cipher_dma_alloc_coherent(mem, type, name, size);
+}
+
-+/*brief release and unmap a mmz or smmu memory */
++/* brief release and unmap a mmz or smmu memory. */
+static hi_s32 crypto_mem_release_unmap(crypto_mem *mem)
+{
+ return cipher_dma_free_coherent(mem);
+}
+
-+/*brief map a mmz or smmu memory */
++/* brief map a mmz or smmu memory. */
+static hi_s32 crypto_mem_map(crypto_mem *mem)
+{
+ hi_u32 i;
+
-+ HI_LOG_DEBUG("crypto_mem_map()- dma 0x%x, size 0x%x\n",
-+ ADDR_U64(mem->dma_addr), mem->dma_size);
++ hi_log_debug("crypto_mem_map()- dma 0x%x, size 0x%x\n",
++ addr_u64(mem->dma_addr), mem->dma_size);
+
+ /* try to query the table to get cpu address firstly,
+ * if can't get cpu address from the table, then call system api to map it.
+ */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if ( loacl_map_table[i].valid &&
-+ ADDR_U64(loacl_map_table[i].dma) == ADDR_U64(mem->dma_addr)) {
-+ mem->dma_virt = loacl_map_table[i].via;
-+ HI_LOG_DEBUG("local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid && addr_u64(g_loacl_map_table[i].dma) == addr_u64(mem->dma_addr)) {
++ mem->dma_virt = g_loacl_map_table[i].via;
++ hi_log_debug("local map %d, dam 0x%x, via 0x%p\n", i, addr_u64(mem->dma_addr), mem->dma_virt);
+ return HI_SUCCESS;
+ }
+ }
+
-+ mem->dma_virt = (hi_u8 *)phys_to_virt(ADDR_U64(mem->dma_addr));
++ mem->dma_virt = (hi_u8 *)phys_to_virt(addr_u64(mem->dma_addr));
+ if (mem->dma_virt == HI_NULL) {
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ HI_LOG_INFO("crypto_mem_map()- via 0x%p\n", mem->dma_virt);
++ hi_log_info("crypto_mem_map()- via 0x%p\n", mem->dma_virt);
+
+ return HI_SUCCESS;
-+
+}
+
-+/*brief unmap a mmz or smmu memory */
++/* brief unmap a mmz or smmu memory. */
+static hi_s32 crypto_mem_unmap(crypto_mem *mem)
+{
+ hi_u32 i;
+
-+ HI_LOG_DEBUG("crypto_mem_unmap()- dma 0x%x, size 0x%x\n",
-+ ADDR_U64(mem->dma_addr), mem->dma_size);
++ hi_log_debug("crypto_mem_unmap()- dma 0x%x, size 0x%x\n",
++ addr_u64(mem->dma_addr), mem->dma_size);
+
+ /* try to query the table to ummap cpu address firstly,
+ * if can't get cpu address from the table, then call system api to unmap it.
+ */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if ( loacl_map_table[i].valid &&
-+ ADDR_U64(loacl_map_table[i].dma) == ADDR_U64(mem->dma_addr)) {
-+ /* this api can't unmap the dma within the map table */
-+ HI_LOG_DEBUG("local unmap %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid && addr_u64(g_loacl_map_table[i].dma) == addr_u64(mem->dma_addr)) {
++ /* this api can't unmap the dma within the map table. */
++ hi_log_debug("local unmap %d, dam 0x%x, via 0x%p\n", i, addr_u64(mem->dma_addr), mem->dma_virt);
+ return HI_SUCCESS;
+ }
+ }
@@ -253092,52 +321595,51 @@ index 0000000..5503967
+ return HI_SUCCESS;
+}
+
-+void crypto_cpuc_flush_dcache_area(void *kvir, hi_u32 length)
++hi_void crypto_cpuc_flush_dcache_area(hi_void *kvir, hi_u32 length)
+{
+ crypto_flush_dcache_area(kvir, length);
+}
+
-+void crypto_mem_init(void)
++hi_void crypto_mem_init(hi_void)
+{
-+ crypto_memset(&loacl_map_table, sizeof(loacl_map_table), 0, sizeof(loacl_map_table));
++ crypto_memset(&g_loacl_map_table, sizeof(g_loacl_map_table), 0, sizeof(g_loacl_map_table));
+}
+
-+void crypto_mem_deinit(void)
++hi_void crypto_mem_deinit(hi_void)
+{
-+
+}
+
+hi_s32 crypto_mem_create(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return crypto_mem_alloc_remap(mem, type, name, size);
+}
+
+hi_s32 crypto_mem_destory(crypto_mem *mem)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return crypto_mem_release_unmap(mem);
+}
+
+hi_s32 hash_mem_create(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return hash_mem_alloc_remap(mem, type, name, size);
+}
+
+hi_s32 hash_mem_destory(crypto_mem *mem)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return hash_mem_release_unmap(mem);
+}
+
+hi_s32 crypto_mem_open(crypto_mem *mem, compat_addr dma_addr, hi_u32 dma_size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ mem->dma_addr = dma_addr;
+ mem->dma_size = dma_size;
@@ -253147,14 +321649,14 @@ index 0000000..5503967
+
+hi_s32 crypto_mem_close(crypto_mem *mem)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
-+ return crypto_mem_unmap(mem);;
++ return crypto_mem_unmap(mem);
+}
+
-+hi_s32 crypto_mem_attach(crypto_mem *mem, void *buffer)
++hi_s32 crypto_mem_attach(crypto_mem *mem, hi_void *buffer)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ mem->user_buf = buffer;
+
@@ -253163,17 +321665,16 @@ index 0000000..5503967
+
+hi_s32 crypto_mem_flush(crypto_mem *mem, hi_u32 dma2user, hi_u32 offset, hi_u32 data_size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
-+ HI_LOG_CHECK_PARAM(mem->dma_virt == HI_NULL);
-+ HI_LOG_CHECK_PARAM(mem->user_buf == HI_NULL);
-+ HI_LOG_CHECK_PARAM(data_size + offset > mem->dma_size);
++ hi_log_chk_param_return(mem == HI_NULL);
++ hi_log_chk_param_return(mem->dma_virt == HI_NULL);
++ hi_log_chk_param_return(mem->user_buf == HI_NULL);
++ hi_log_chk_param_return(data_size + offset < data_size);
++ hi_log_chk_param_return(data_size + offset > mem->dma_size);
+
+ if (dma2user) {
-+ crypto_memcpy((hi_u8 *)mem->user_buf + offset, data_size,
-+ (hi_u8 *)mem->dma_virt + offset, data_size);
++ crypto_memcpy((hi_u8 *)mem->user_buf + offset, data_size, (hi_u8 *)mem->dma_virt + offset, data_size);
+ } else {
-+ crypto_memcpy((hi_u8 *)mem->dma_virt + offset, data_size,
-+ (hi_u8 *)mem->user_buf + offset, data_size);
++ crypto_memcpy((hi_u8 *)mem->dma_virt + offset, data_size, (hi_u8 *)mem->user_buf + offset, data_size);
+ }
+
+ return HI_SUCCESS;
@@ -253181,14 +321682,14 @@ index 0000000..5503967
+
+hi_s32 crypto_mem_phys(crypto_mem *mem, compat_addr *dma_addr)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
-+ dma_addr->phy = ADDR_U64(mem->dma_addr);
++ dma_addr->phy = addr_u64(mem->dma_addr);
+
+ return HI_SUCCESS;
+}
+
-+void *crypto_mem_virt(crypto_mem *mem)
++hi_void *crypto_mem_virt(crypto_mem *mem)
+{
+ if (mem == HI_NULL) {
+ return HI_NULL;
@@ -253197,38 +321698,38 @@ index 0000000..5503967
+ return mem->dma_virt;
+}
+
-+hi_s32 crypto_copy_from_user(void *to, const void *from, unsigned long n)
++hi_s32 crypto_copy_from_user(hi_void *to, const hi_void *from, unsigned long n)
+{
+ if (n == 0) {
+ return HI_SUCCESS;
+ }
+
-+ HI_LOG_CHECK_PARAM(to == HI_NULL);
-+ HI_LOG_CHECK_PARAM(from == HI_NULL);
-+ HI_LOG_CHECK_PARAM(n > MAX_COPY_FROM_USER_SIZE);
++ hi_log_chk_param_return(to == HI_NULL);
++ hi_log_chk_param_return(from == HI_NULL);
++ hi_log_chk_param_return(n > MAX_COPY_FROM_USER_SIZE);
+
+ return copy_from_user(to, from, n);
+}
+
-+hi_s32 crypto_copy_to_user(void *to, const void *from, unsigned long n)
++hi_s32 crypto_copy_to_user(hi_void *to, const hi_void *from, unsigned long n)
+{
+ if (n == 0) {
+ return HI_SUCCESS;
+ }
+
-+ HI_LOG_CHECK_PARAM(to == HI_NULL);
-+ HI_LOG_CHECK_PARAM(from == HI_NULL);
-+ HI_LOG_CHECK_PARAM(n > MAX_COPY_FROM_USER_SIZE);
++ hi_log_chk_param_return(to == HI_NULL);
++ hi_log_chk_param_return(from == HI_NULL);
++ hi_log_chk_param_return(n > MAX_COPY_FROM_USER_SIZE);
+
+ return copy_to_user(to, from, n);
+}
+
-+hi_u32 crypto_is_sec_cpu(void)
++hi_u32 crypto_is_sec_cpu(hi_void)
+{
+ return module_get_secure();
+}
+
-+void smmu_get_table_addr(hi_u64 *rdaddr, hi_u64 *wraddr, hi_u64 *table)
++hi_void smmu_get_table_addr(hi_u64 *rdaddr, hi_u64 *wraddr, hi_u64 *table)
+{
+#ifdef CRYPTO_SMMU_SUPPORT
+ hi_u32 smmu_e_raddr, smmu_e_waddr, mmu_pgtbl;
@@ -253244,7 +321745,7 @@ index 0000000..5503967
+#endif
+}
+
-+hi_s32 crypto_waitdone_callback(void *param)
++hi_s32 crypto_waitdone_callback(hi_void *param)
+{
+ hi_u32 *done = param;
+
@@ -253260,33 +321761,33 @@ index 0000000..5503967
+ /* Check wether the start address is within the MMZ range of the current system. */
+ mmb = hil_mmb_getby_phys_2(phy_addr, &mmb_offset);
+ if (mmb != NULL) {
-+ /* Check wether the end address is within the MMZ range of the current system */
++ /* Check wether the end address is within the MMZ range of the current system. */
+ mmb = hil_mmb_getby_phys_2(phy_addr + length - 1, &mmb_offset);
+ if (mmb == NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(hil_mmb_getby_phys_2, HI_FAILURE);
-+ return HI_FAILURE;
++ hi_log_print_func_err(hil_mmb_getby_phys_2, HI_ERR_CIPHER_INVALID_ADDR);
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ }
-+ } else { /* Whether the starting address is within the MMZ range of other systems */
++ } else { /* Whether the starting address is within the MMZ range of other systems. */
+ if (hil_map_mmz_check_phys(phy_addr, length)) {
-+ HI_LOG_PRINT_FUNC_ERR(hil_map_mmz_check_phys, HI_FAILURE);
-+ return HI_FAILURE;
++ hi_log_print_func_err(hil_map_mmz_check_phys, HI_ERR_CIPHER_INVALID_ADDR);
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ }
+ }
+#endif
+
+#ifdef CIPHER_BUILDIN
-+ /*check physical addr is ram region*/
++ /* check physical addr is ram region. */
+ if (pfn_valid(phy_addr >> PAGE_SHIFT) || pfn_valid(length + (phy_addr >> PAGE_SHIFT))) {
+#if defined(CONFIG_CMA) && defined(CONFIG_ARCH_HISI_BVT)
+ if (is_hicma_address(phy_addr, length)) {
+ return HI_SUCCESS;
+ } else {
-+ HI_LOG_PRINT_FUNC_ERR(is_hicma_address, HI_FAILURE);
-+ return HI_FAILURE;
++ hi_log_print_func_err(is_hicma_address, HI_ERR_CIPHER_INVALID_ADDR);
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ }
+#endif
-+ HI_LOG_ERROR("physical addr is ram region.\n");
-+ return HI_FAILURE;
++ hi_log_error("physical addr is ram region.\n");
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ } else {
+ return HI_SUCCESS;
+ }
@@ -253294,38 +321795,21 @@ index 0000000..5503967
+
+ return HI_SUCCESS;
+}
-+
-+/** @}*/ /** <!-- ==== API Code end ====*/
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_sys_liteos.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_sys_liteos.c
new file mode 100644
-index 0000000..15db139
+index 0000000..5bf5134
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/drv_osal_sys_liteos.c
-@@ -0,0 +1,420 @@
+@@ -0,0 +1,384 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv osal sys liteos adapt for cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#include "drv_osal_lib.h"
+
-+/************************* Internal Structure Definition *********************/
-+/** \addtogroup base type*/
-+/** @{*/ /** <!-- [base]*/
-+
+/* under TEE, we only can malloc secure mmz at system steup,
+ * then map the mmz to Smmu, but the smmu can't map to cpu address,
+ * so we must save the cpu address in a static table when malloc and map mmz.
@@ -253340,32 +321824,26 @@ index 0000000..15db139
+ void *via;
+} crypto_mem_map_table;
+
-+static crypto_mem_map_table loacl_map_table[CRYPTO_MEM_MAP_TABLE_DEPTH];
++static crypto_mem_map_table g_loacl_map_table[CRYPTO_MEM_MAP_TABLE_DEPTH];
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-+
-+/******************************* API Code *****************************/
-+/** \addtogroup base*/
-+/** @{*/ /** <!--[base]*/
-+
-+/*****************************************************************
++/* ***************************************************************
+ * mmz/mmu api *
-+ *****************************************************************/
-+
-+/*brief allocate and map a mmz or smmu memory
-+* we can't allocate smmu directly during TEE boot period.
-+* in addition, the buffer of cipher node list must be mmz.
-+* so here we have to allocate a mmz memory then map to smmu if necessary.
-+*/
-+hi_s32 crypto_mmz_malloc_nocache(hi_char* mmz_name, hi_char* buf_name,
-+ hi_u64* phy_addr, hi_void** vir_addr,
++ * ***************************************************************
++ *
++ * brief allocate and map a mmz or smmu memory
++ * we can't allocate smmu directly during TEE boot period.
++ * in addition, the buffer of cipher node list must be mmz.
++ * so here we have to allocate a mmz memory then map to smmu if necessary.
++ */
++hi_s32 crypto_mmz_malloc_nocache(hi_char *mmz_name, hi_char *buf_name,
++ hi_u64 *phy_addr, hi_void **vir_addr,
+ hi_ulong length)
+{
+ hil_mmb_t *pmmb = NULL;
+
+ pmmb = hil_mmb_alloc(buf_name, length, 0, 0, mmz_name);
+ if (pmmb == NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(hil_mmb_alloc, HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_print_func_err(hil_mmb_alloc, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
@@ -253374,7 +321852,7 @@ index 0000000..15db139
+ if (*phy_addr == 0) {
+ hil_mmb_free(pmmb);
+ pmmb = NULL;
-+ HI_LOG_PRINT_FUNC_ERR(hil_mmb_phys, HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_print_func_err(hil_mmb_phys, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
@@ -253382,14 +321860,14 @@ index 0000000..15db139
+ if (*vir_addr == NULL) {
+ hil_mmb_free(pmmb);
+ pmmb = NULL;
-+ HI_LOG_PRINT_FUNC_ERR(hil_mmb_map2kern, HI_ERR_CIPHER_FAILED_MEM);
++ hi_log_print_func_err(hil_mmb_map2kern, HI_ERR_CIPHER_FAILED_MEM);
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
+ return HI_SUCCESS;
+}
+
-+hi_void crypto_mmz_free(hi_u64 phy_addr, hi_void* vir_addr)
++hi_void crypto_mmz_free(hi_u64 phy_addr, hi_void *vir_addr)
+{
+ if (vir_addr != NULL) {
+ hil_mmb_t *pmmb = hil_mmb_getby_kvirt(vir_addr);
@@ -253405,35 +321883,34 @@ index 0000000..15db139
+ }
+}
+
-+static hi_s32 crypto_mem_alloc_remap(crypto_mem *mem, hi_u32 type, char const *name, hi_u32 size)
++static hi_s32 crypto_mem_alloc_remap(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size)
+{
-+ hi_s32 ret = HI_FAILURE;
++ hi_s32 ret;
+ hi_u32 i;
+ crypto_memset(mem, sizeof(crypto_mem), 0, sizeof(crypto_mem));
+
-+ HI_LOG_DEBUG("mem_alloc_remap()- name %s, size 0x%x\n", name, size);
++ hi_log_debug("mem_alloc_remap()- name %s, size 0x%x\n", name, size);
+
-+ ret = crypto_mmz_malloc_nocache(NULL, (char *)name, &ADDR_U64(mem->mmz_addr), (void **)&mem->dma_virt, size);
++ ret = crypto_mmz_malloc_nocache(NULL, (char *)name, &addr_u64(mem->mmz_addr), (void **)&mem->dma_virt, size);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_PRINT_FUNC_ERR(crypto_mmz_malloc_nocache, ret);
++ hi_log_print_func_err(crypto_mmz_malloc_nocache, ret);
+ return ret;
+ }
-+ ADDR_U64(mem->dma_addr) = ADDR_U64(mem->mmz_addr);
++ addr_u64(mem->dma_addr) = addr_u64(mem->mmz_addr);
+ mem->dma_size = size;
+
-+ HI_LOG_DEBUG("MMZ/MMU malloc, MMZ 0x%x, MMZ/MMU 0x%x, VIA 0x%p, SIZE 0x%x\n",
-+ ADDR_U64(mem->mmz_addr), ADDR_U64(mem->dma_addr), mem->dma_virt, size);
++ hi_log_debug("MMZ/MMU malloc, MMZ 0x%x, MMZ/MMU 0x%x, VIA 0x%p, SIZE 0x%x\n",
++ addr_u64(mem->mmz_addr), addr_u64(mem->dma_addr), mem->dma_virt, size);
+
+ mem->user_buf = HI_NULL;
+
+ /* save the map info */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if (loacl_map_table[i].valid == HI_FALSE) {
-+ ADDR_U64(loacl_map_table[i].dma) = ADDR_U64(mem->dma_addr);
-+ loacl_map_table[i].via = mem->dma_virt;
-+ loacl_map_table[i].valid = HI_TRUE;
-+ HI_LOG_DEBUG("map local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid == HI_FALSE) {
++ addr_u64(g_loacl_map_table[i].dma) = addr_u64(mem->dma_addr);
++ g_loacl_map_table[i].via = mem->dma_virt;
++ g_loacl_map_table[i].valid = HI_TRUE;
++ hi_log_debug("map local map %d, dam 0x%x, via 0x%p\n", i, addr_u64(mem->dma_addr), mem->dma_virt);
+ break;
+ }
+ }
@@ -253441,21 +321918,19 @@ index 0000000..15db139
+ return HI_SUCCESS;
+}
+
-+/*brief release and unmap a mmz or smmu memory */
++/* brief release and unmap a mmz or smmu memory. */
+static hi_s32 crypto_mem_release_unmap(crypto_mem *mem)
+{
+ hi_u32 i;
-+ crypto_mmz_free(ADDR_U64(mem->mmz_addr), mem->dma_virt);
++ crypto_mmz_free(addr_u64(mem->mmz_addr), mem->dma_virt);
+
+ /* remove the map info */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if ( loacl_map_table[i].valid &&
-+ ADDR_U64(loacl_map_table[i].dma) == ADDR_U64(mem->dma_addr)) {
-+ ADDR_U64(loacl_map_table[i].dma) = 0x00;
-+ loacl_map_table[i].via = HI_NULL;
-+ loacl_map_table[i].valid = HI_FALSE;
-+ HI_LOG_DEBUG("unmap local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid && addr_u64(g_loacl_map_table[i].dma) == addr_u64(mem->dma_addr)) {
++ addr_u64(g_loacl_map_table[i].dma) = 0x00;
++ g_loacl_map_table[i].via = HI_NULL;
++ g_loacl_map_table[i].valid = HI_FALSE;
++ hi_log_debug("unmap local map %d, dam 0x%x, via 0x%p\n", i, addr_u64(mem->dma_addr), mem->dma_virt);
+ break;
+ }
+ }
@@ -253464,110 +321939,100 @@ index 0000000..15db139
+ return HI_SUCCESS;
+}
+
-+/*brief map a mmz or smmu memory */
++/* brief map a mmz or smmu memory. */
+static hi_s32 crypto_mem_map(crypto_mem *mem)
+{
+ hi_u32 i;
+
-+ HI_LOG_DEBUG("crypto_mem_map()- dma 0x%x, size 0x%x\n",
-+ ADDR_U64(mem->dma_addr), mem->dma_size);
++ hi_log_debug("crypto_mem_map()- dma 0x%x, size 0x%x\n",
++ addr_u64(mem->dma_addr), mem->dma_size);
+
+ /* try to query the table to get cpu address firstly,
+ * if can't get cpu address from the table, then call system api to map it.
+ */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if ( loacl_map_table[i].valid &&
-+ ADDR_U64(loacl_map_table[i].dma) == ADDR_U64(mem->dma_addr)) {
-+ mem->dma_virt = loacl_map_table[i].via;
-+ HI_LOG_DEBUG("local map %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ if (g_loacl_map_table[i].valid && addr_u64(g_loacl_map_table[i].dma) == addr_u64(mem->dma_addr)) {
++ mem->dma_virt = g_loacl_map_table[i].via;
++ hi_log_debug("local map %d, dam 0x%x, via 0x%p\n", i, addr_u64(mem->dma_addr), mem->dma_virt);
+ return HI_SUCCESS;
+ }
+ }
+
-+ mem->dma_virt = (hi_u8 *)crypto_osal_ioremap_nocache(ADDR_U64(mem->dma_addr), mem->dma_size);
++ mem->dma_virt = (hi_u8 *)crypto_osal_ioremap_nocache(addr_u64(mem->dma_addr), mem->dma_size);
+ if (mem->dma_virt == HI_NULL) {
+ return HI_ERR_CIPHER_FAILED_MEM;
+ }
+
-+ HI_LOG_INFO("crypto_mem_map()- via 0x%p\n", mem->dma_virt);
-+
++ hi_log_info("crypto_mem_map()- via 0x%p\n", mem->dma_virt);
+ return HI_SUCCESS;
-+
+}
+
-+/*brief unmap a mmz or smmu memory */
++/* brief unmap a mmz or smmu memory. */
+static hi_s32 crypto_mem_unmap(crypto_mem *mem)
+{
+ hi_u32 i;
+
-+ HI_LOG_DEBUG("crypto_mem_unmap()- dma 0x%x, size 0x%x\n",
-+ ADDR_U64(mem->dma_addr), mem->dma_size);
++ hi_log_debug("crypto_mem_unmap()- dma 0x%x, size 0x%x\n", addr_u64(mem->dma_addr), mem->dma_size);
+
+ /* try to query the table to ummap cpu address firstly,
+ * if can't get cpu address from the table, then call system api to unmap it.
+ */
+ for (i = 0; i < CRYPTO_MEM_MAP_TABLE_DEPTH; i++) {
-+ if ( loacl_map_table[i].valid &&
-+ ADDR_U64(loacl_map_table[i].dma) == ADDR_U64(mem->dma_addr)) {
++ if (g_loacl_map_table[i].valid && addr_u64(g_loacl_map_table[i].dma) == addr_u64(mem->dma_addr)) {
+ /* this api can't unmap the dma within the map table */
-+ HI_LOG_DEBUG("local unmap %d, dam 0x%x, via 0x%p\n",
-+ i, ADDR_U64(mem->dma_addr), mem->dma_virt);
++ hi_log_debug("local unmap %d, dam 0x%x, via 0x%p\n", i, addr_u64(mem->dma_addr), mem->dma_virt);
+ return HI_SUCCESS;
+ }
+ }
+
+ crypto_osal_iounmap(mem->dma_virt);
-+
+ return HI_SUCCESS;
+}
+
+void crypto_mem_init(void)
+{
-+ crypto_memset(&loacl_map_table, sizeof(loacl_map_table), 0, sizeof(loacl_map_table));
++ crypto_memset(&g_loacl_map_table, sizeof(g_loacl_map_table), 0, sizeof(g_loacl_map_table));
+}
+
+void crypto_mem_deinit(void)
+{
-+
+}
+
-+void crypto_cpuc_flush_dcache_area(void *kvir, hi_u32 length)
++void crypto_cpuc_flush_dcache_area(hi_void *kvir, hi_u32 length)
+{
-+
+}
+
+hi_s32 crypto_mem_create(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return crypto_mem_alloc_remap(mem, type, name, size);
+}
+
+hi_s32 crypto_mem_destory(crypto_mem *mem)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return crypto_mem_release_unmap(mem);
+}
+
+hi_s32 hash_mem_create(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return crypto_mem_alloc_remap(mem, type, name, size);
+}
+
+hi_s32 hash_mem_destory(crypto_mem *mem)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ return crypto_mem_release_unmap(mem);
+}
+
+hi_s32 crypto_mem_open(crypto_mem *mem, compat_addr dma_addr, hi_u32 dma_size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ mem->dma_addr = dma_addr;
+ mem->dma_size = dma_size;
@@ -253577,14 +322042,14 @@ index 0000000..15db139
+
+hi_s32 crypto_mem_close(crypto_mem *mem)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
-+ return crypto_mem_unmap(mem);;
++ return crypto_mem_unmap(mem);
+}
+
-+hi_s32 crypto_mem_attach(crypto_mem *mem, void *buffer)
++hi_s32 crypto_mem_attach(crypto_mem *mem, hi_void *buffer)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
+ mem->user_buf = buffer;
+
@@ -253593,17 +322058,16 @@ index 0000000..15db139
+
+hi_s32 crypto_mem_flush(crypto_mem *mem, hi_u32 dma2user, hi_u32 offset, hi_u32 data_size)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
-+ HI_LOG_CHECK_PARAM(mem->dma_virt == HI_NULL);
-+ HI_LOG_CHECK_PARAM(mem->user_buf == HI_NULL);
-+ HI_LOG_CHECK_PARAM(data_size + offset > mem->dma_size);
++ hi_log_chk_param_return(mem == HI_NULL);
++ hi_log_chk_param_return(mem->dma_virt == HI_NULL);
++ hi_log_chk_param_return(mem->user_buf == HI_NULL);
++ hi_log_chk_param_return(data_size + offset < data_size);
++ hi_log_chk_param_return(data_size + offset > mem->dma_size);
+
+ if (dma2user) {
-+ crypto_memcpy((hi_u8 *)mem->user_buf + offset, data_size,
-+ (hi_u8 *)mem->dma_virt + offset, data_size);
++ crypto_memcpy((hi_u8 *)mem->user_buf + offset, data_size, (hi_u8 *)mem->dma_virt + offset, data_size);
+ } else {
-+ crypto_memcpy((hi_u8 *)mem->dma_virt + offset, data_size,
-+ (hi_u8 *)mem->user_buf + offset, data_size);
++ crypto_memcpy((hi_u8 *)mem->dma_virt + offset, data_size, (hi_u8 *)mem->user_buf + offset, data_size);
+ }
+
+ return HI_SUCCESS;
@@ -253611,9 +322075,9 @@ index 0000000..15db139
+
+hi_s32 crypto_mem_phys(crypto_mem *mem, compat_addr *dma_addr)
+{
-+ HI_LOG_CHECK_PARAM(mem == HI_NULL);
++ hi_log_chk_param_return(mem == HI_NULL);
+
-+ dma_addr->phy = ADDR_U64(mem->dma_addr);
++ dma_addr->phy = addr_u64(mem->dma_addr);
+
+ return HI_SUCCESS;
+}
@@ -253627,26 +322091,26 @@ index 0000000..15db139
+ return mem->dma_virt;
+}
+
-+hi_s32 crypto_copy_from_user(void *to, const void *from, unsigned long n)
++hi_s32 crypto_copy_from_user(hi_void *to, const hi_void *from, unsigned long n)
+{
+ if (n == 0) {
+ return HI_SUCCESS;
+ }
+
-+ HI_LOG_CHECK_PARAM(to == HI_NULL);
-+ HI_LOG_CHECK_PARAM(from == HI_NULL);
++ hi_log_chk_param_return(to == HI_NULL);
++ hi_log_chk_param_return(from == HI_NULL);
+
+ return osal_copy_from_user(to, from, n);
+}
+
-+hi_s32 crypto_copy_to_user(void *to, const void *from, unsigned long n)
++hi_s32 crypto_copy_to_user(hi_void *to, const hi_void *from, unsigned long n)
+{
+ if (n == 0) {
+ return HI_SUCCESS;
+ }
+
-+ HI_LOG_CHECK_PARAM(to == HI_NULL);
-+ HI_LOG_CHECK_PARAM(from == HI_NULL);
++ hi_log_chk_param_return(to == HI_NULL);
++ hi_log_chk_param_return(from == HI_NULL);
+
+ return osal_copy_to_user(to, from, n);
+}
@@ -253672,7 +322136,7 @@ index 0000000..15db139
+#endif
+}
+
-+hi_s32 crypto_waitdone_callback(void *param)
++hi_s32 crypto_waitdone_callback(hi_void *param)
+{
+ hi_u32 *pbDone = param;
+
@@ -253691,29 +322155,29 @@ index 0000000..15db139
+ /* Check wether the end address is within the MMZ range of the current system */
+ mmb = hil_mmb_getby_phys_2(phy_addr + length - 1, &mmb_offset);
+ if (mmb == NULL) {
-+ HI_LOG_PRINT_FUNC_ERR(hil_mmb_getby_phys_2, HI_FAILURE);
-+ return HI_FAILURE;
++ hi_log_print_func_err(hil_mmb_getby_phys_2, HI_ERR_CIPHER_INVALID_ADDR);
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ }
+ } else { /* Whether the starting address is within the MMZ range of other systems */
+ if (hil_map_mmz_check_phys(phy_addr, length)) {
-+ HI_LOG_PRINT_FUNC_ERR(hil_map_mmz_check_phys, HI_FAILURE);
-+ return HI_FAILURE;
++ hi_log_print_func_err(hil_map_mmz_check_phys, HI_ERR_CIPHER_INVALID_ADDR);
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ }
+ }
+#else
+
-+ /*check physical addr is ram region*/
++ /* check physical addr is ram region. */
+ if (pfn_valid(phy_addr >> PAGE_SHIFT) || pfn_valid(length + (phy_addr >> PAGE_SHIFT))) {
+#if defined(CONFIG_CMA) && defined(CONFIG_ARCH_HISI_BVT)
+ if (is_hicma_address(phy_addr, length)) {
+ return HI_SUCCESS;
+ } else {
-+ HI_LOG_PRINT_FUNC_ERR(is_hicma_address, HI_FAILURE);
-+ return HI_FAILURE;
++ hi_log_print_func_err(is_hicma_address, HI_ERR_CIPHER_INVALID_ADDR);
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ }
+#endif
-+ HI_LOG_ERROR("physical addr is ram region.\n");
-+ return HI_FAILURE;
++ hi_log_error("physical addr is ram region.\n");
++ return HI_ERR_CIPHER_INVALID_ADDR;
+ } else {
+ return HI_SUCCESS;
+ }
@@ -253721,58 +322185,137 @@ index 0000000..15db139
+
+ return HI_SUCCESS;
+}
-+/** @}*/ /** <!-- ==== API Code end ====*/
+diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_cipher_define.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_cipher_define.h
+new file mode 100644
+index 0000000..d4c1f86
+--- /dev/null
++++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_cipher_define.h
+@@ -0,0 +1,85 @@
++/*
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cipher define.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
++ */
++
++#ifndef __DRV_CIPHER_DEFINE_H__
++#define __DRV_CIPHER_DEFINE_H__
++
++#ifdef __cplusplus
++#if __cplusplus
++extern "C"{
++#endif
++#endif /* __cplusplus */
++
++/* word index number. */
++#define WORD_IDX_0 0
++#define WORD_IDX_1 1
++#define WORD_IDX_2 2
++#define WORD_IDX_3 3
++#define WORD_IDX_4 4
++#define WORD_IDX_5 5
++#define WORD_IDX_6 6
++#define WORD_IDX_7 7
++
++/* Boundary value 1. */
++#define BOUND_VAL_1 1
++
++/* multiple value */
++#define MUL_VAL_1 1
++#define MUL_VAL_2 2
++#define MUL_VAL_3 3
++#define MUL_VAL_4 4
++
++#define SHIFT_1BITS 1
++#define SHIFT_2BITS 2
++#define SHIFT_3BITS 3
++#define SHIFT_4BITS 4
++#define SHIFT_5BITS 5
++#define SHIFT_6BITS 6
++#define SHIFT_8BITS 8
++#define SHIFT_9BITS 9
++#define SHIFT_13BITS 13
++#define SHIFT_15BITS 15
++#define SHIFT_16BITS 16
++#define SHIFT_17BITS 17
++#define SHIFT_21BITS 21
++#define SHIFT_23BITS 23
++#define SHIFT_24BITS 24
++#define SHIFT_29BITS 29
++#define SHIFT_32BITS 32
++
++#define MAX_LOW_2BITS 3
++#define MAX_LOW_3BITS 7
++#define MAX_LOW_4BITS 0xF
++#define MAX_LOW_8BITS 0xFF
++
++#define WORD_WIDTH 4
++
++/* width of word. */
++#define WORD_BIT_WIDTH 32
++#define U32_MAX_SIZE 0xFFFFFFFF
++
++/* width of double word. */
++#define DOUBLE_WORD_WIDTH 8
++
++#define BYTE_BITS 8
++/* The offset in one byte. */
++#define BYTE_2BIT 2
++#define BYTE_4BIT 4
++#define BYTE_6BIT 6
++
++#define CRYPTO_NUM_1 1
++#define CRYPTO_NUM_2 2
++#define CRYPTO_NUM_3 3
++
++#ifdef __cplusplus
++#if __cplusplus
++}
++#endif
++#endif /* __cplusplus */
++
++#endif /* __DRV_CIPHER_DEFINE_H__ */
++
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3516cv500.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3516cv500.h
new file mode 100644
-index 0000000..c8340af
+index 0000000..7673150
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3516cv500.h
-@@ -0,0 +1,280 @@
+@@ -0,0 +1,278 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv osal hi3516cv500 configuration of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_HI3516CV500_H__
+#define __DRV_OSAL_HI3516CV500_H__
+
-+/* the total cipher hard channel which we can used*/
-+#define CIPHER_HARD_CHANNEL_CNT (0x07)
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_CHANNEL_MASK (0xFE)
++/* the total cipher hard channel which we can used. */
++#define CIPHER_HARD_CHANNEL_CNT 0x07
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_CHANNEL_MASK 0xFE
+
-+/* the total hash hard channel which we can used*/
-+#define HASH_HARD_CHANNEL_CNT (0x01)
++/* the total hash hard channel which we can used. */
++#define HASH_HARD_CHANNEL_CNT 0x01
+
-+#ifdef __HuaweiLite__
+/* liteos resource config */
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x04)
-+#define HASH_HARD_CHANNEL (0x02)
++#ifdef __HuaweiLite__
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x04
++#define HASH_HARD_CHANNEL 0x02
+#else
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x02)
-+#define HASH_HARD_CHANNEL (0x01)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x02
++#define HASH_HARD_CHANNEL 0x01
+#endif
+
-+/* the total cipher hard key channel which we can used*/
-+#define CIPHER_HARD_KEY_CHANNEL_CNT (0x04)
++/* the total cipher hard key channel which we can used. */
++#define CIPHER_HARD_KEY_CHANNEL_CNT 0x04
+
-+/* mask which cipher hard key channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_KEY_CHANNEL_MASK (0xF0)
++/* mask which cipher hard key channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_KEY_CHANNEL_MASK 0xF0
+
+/* support read IRQ number from DTS */
+#define IRQ_DTS_SUPPORT
@@ -253780,29 +322323,32 @@ index 0000000..c8340af
+/* support OTP load key */
+#define OTP_SUPPORT
+
-+/* support smmu*/
-+//#define CRYPTO_SMMU_SUPPORT
-+
-+/* support reducing power dissipation*/
++/* support reducing power dissipation. */
+#define CRYPTO_CORE_AUTO_CKEN_SUPPORT
+
+#ifndef __HuaweiLite__
-+/* support interrupt*/
++/* support interrupt. */
+#define CRYPTO_OS_INT_SUPPORT
+#endif
+
-+/* RSA RAND Mask*/
-+//#define RSA_RAND_MASK
-+
-+/* secure cpu*/
-+//#define CRYPTO_SEC_CPU
-+
+/* the hardware version */
+#define CHIP_SYMC_VER_V200
+#define CHIP_HASH_VER_V200
-+//#define CHIP_TRNG_VER_V200
++#define CHIP_TRNG_VER_V200
+#define CHIP_IFEP_RSA_VER_V100
-+//#define CHIP_SM2_VER_V100
++
++/*
++ * SMP version linux is sec config
++ * moudle unsupport, we need set the table.
++ */
++#define BASE_TABLE_NULL { \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 0, \
++.crg_valid = 0, \
++.ver_valid = 0, \
++.int_valid = 0, \
++}
+
+/* support des */
+#define CHIP_DES_SUPPORT
@@ -253810,180 +322356,187 @@ index 0000000..c8340af
+/* support 3des */
+#define CHIP_3DES_SUPPORT
+
-+/* supoort odd key */
-+//#define CHIP_SYMC_ODD_KEY_SUPPORT
-+
-+/* supoort SM1 */
-+//#define CHIP_SYMC_SM1_SUPPORT
-+
-+/* the hardware capacity */
-+//#define CHIP_AES_CCM_GCM_SUPPORT
-+
-+/* the software capacity */
-+//#define SOFT_AES_SUPPORT
-+//#define SOFT_TDES_SUPPORT
-+//#define SOFT_AES_CCM_GCM_SUPPORT
-+//#define SOFT_SHA1_SUPPORT
-+//#define SOFT_SHA256_SUPPORT
-+//#define SOFT_SHA512_SUPPORT
-+//#define SOFT_SM2_SUPPORT
-+//#define SOFT_SM3_SUPPORT
-+//#define SOFT_ECC_SUPPORT
-+//#define SOFT_AES_CTS_SUPPORT
-+
-+/* SMP version linux is sec config */
-+/* moudle unsupport, we need set the table*/
-+#define BASE_TABLE_NULL {\
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 0, \
-+ .crg_valid = 0, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ }
-+
++/* supoort trng version v200.
++ * CHIP_TRNG_VER_V200
++ *
++ * supoort odd key.
++ * CHIP_SYMC_ODD_KEY_SUPPORT
++ *
++ * supoort SM1.
++ * CHIP_SYMC_SM1_SUPPORT
++ *
++ * the hardware capacity.
++ * CHIP_AES_CCM_GCM_SUPPORT
++ *
++ * supoort sm2 ver v100.
++ * CHIP_SM2_VER_V100
++ *
++ * RSA rand mask.
++ * RSA_RAND_MASK
++ *
++ * support smmu.
++ * CRYPTO_SMMU_SUPPORT
++ *
++ * support secure cpu
++ * CRYPTO_SEC_CPU
++ *
++ * support switch cpu.
++ * CRYPTO_SWITCH_CPU
++ *
++ * the software capacity.
++ * SOFT_AES_SUPPORT
++ * SOFT_TDES_SUPPORT
++ * SOFT_AES_CCM_GCM_SUPPORT
++ * SOFT_SHA1_SUPPORT
++ * SOFT_SHA256_SUPPORT
++ * SOFT_SHA512_SUPPORT
++ * SOFT_SM2_SUPPORT
++ * SOFT_SM3_SUPPORT
++ * SOFT_ECC_SUPPORT
++ * SOFT_AES_CTS_SUPPORT
++ */
+#if defined(ARCH_TYPE_amp) && !defined(AMP_NONSECURE_VERSION) && !defined(__HuaweiLite__)
+
-+/* linux of AMP use non-secure config */
++/* linux of AMP use non-secure config. */
+#define HARD_INFO_TRNG BASE_TABLE_NULL
+
-+#define HARD_INFO_CIPHER {\
-+ .name = "nonsec_cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 104, \
-+ .reset_bit = 8, \
-+ .clk_bit = 9, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x2018121, \
-+ .reg_addr_phy = 0x100C0000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
++#define HARD_INFO_CIPHER { \
++.name = "nonsec_cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 104, \
++.reset_bit = 8, \
++.clk_bit = 9, \
++.version_reg = 0x308, \
++.version_val = 0x2018121, \
++.reg_addr_phy = 0x100C0000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x120101A0, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "nonsec_hash", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 104, \
-+ .reset_bit = 8, \
-+ .clk_bit = 9, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x2018121, \
-+ .reg_addr_phy = 0x100C0000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "nonsec_hash", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 104, \
++.reset_bit = 8, \
++.clk_bit = 9, \
++.version_reg = 0x308, \
++.version_val = 0x2018121, \
++.reg_addr_phy = 0x100C0000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x120101A0, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for IFEP RSA*/
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "nonsec_rsa", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 0, \
-+ .reg_addr_phy = 0x100D0000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x120101A0, \
-+ .reset_bit = 6, \
-+ .clk_bit = 7, \
-+ .version_reg = 0x90, \
-+ .version_val = 0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for IFEP RSA. */
++#define HARD_INFO_IFEP_RSA { \
++.name = "nonsec_rsa", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 0, \
++.reg_addr_phy = 0x100D0000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x120101A0, \
++.reset_bit = 6, \
++.clk_bit = 7, \
++.version_reg = 0x90, \
++.version_val = 0, \
++}
+#else
-+/* SMP, liteos of secure AMP, linux of non-secure AMP use secure config */
++/* SMP, liteos of secure AMP, linux of non-secure AMP use secure config. */
+#define CRYPTO_SEC_CPU
+
+#define CHIP_TRNG_VER_V200
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_CIPHER {\
-+ .name = "cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 103, \
-+ .reset_bit = 8, \
-+ .clk_bit = 9, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x2018121, \
-+ .reg_addr_phy = 0x100C0000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_CIPHER { \
++.name = "cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 103, \
++.reset_bit = 8, \
++.clk_bit = 9, \
++.version_reg = 0x308, \
++.version_val = 0x2018121, \
++.reg_addr_phy = 0x100C0000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x120101A0, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "hash", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 103, \
-+ .reset_bit = 8, \
-+ .clk_bit = 9, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x2018121, \
-+ .reg_addr_phy = 0x100C0000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "hash", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 103, \
++.reset_bit = 8, \
++.clk_bit = 9, \
++.version_reg = 0x308, \
++.version_val = 0x2018121, \
++.reg_addr_phy = 0x100C0000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x120101A0, \
++}
+
-+/* define sec rsa1 for SMP VERSION */
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "rsa0", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 0, \
-+ .reg_addr_phy = 0x10080000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x120101A0, \
-+ .reset_bit = 4, \
-+ .clk_bit = 5, \
-+ .version_reg = 0x90, \
-+ .version_val = 0, \
-+ }
++/* define sec rsa1 for SMP VERSION. */
++#define HARD_INFO_IFEP_RSA { \
++.name = "rsa0", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 0, \
++.reg_addr_phy = 0x10080000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x120101A0, \
++.reset_bit = 4, \
++.clk_bit = 5, \
++.version_reg = 0x90, \
++.version_val = 0, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for HASH*/
-+#define HARD_INFO_TRNG {\
-+ .name = "trng", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ .reset_bit = 2, \
-+ .clk_bit = 3, \
-+ .reg_addr_phy = 0x10090200, \
-+ .reg_addr_size = 0x100, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for HASH. */
++#define HARD_INFO_TRNG { \
++.name = "trng", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 0, \
++.int_valid = 0, \
++.reset_bit = 2, \
++.clk_bit = 3, \
++.reg_addr_phy = 0x10090200, \
++.reg_addr_size = 0x100, \
++.crg_addr_phy = 0x120101A0, \
++}
+#endif
+
-+#define KLAD_REG_BASE_ADDR_PHY (0x10070000)
-+#define OTP_REG_BASE_ADDR_PHY (0x100B0000)
-+#define KLAD_CRG_ADDR_PHY (0x120101A0)
-+#define REG_SYS_OTP_CLK_ADDR_PHY (0x120101BC)
++#define KLAD_REG_BASE_ADDR_PHY 0x10070000
++#define OTP_REG_BASE_ADDR_PHY 0x100B0000
++#define KLAD_CRG_ADDR_PHY 0x120101A0
++#define REG_SYS_OTP_CLK_ADDR_PHY 0x120101BC
+
+#define OTP_CRG_CLOCK_BIT (0x01 << 1)
+
@@ -253996,7 +322549,6 @@ index 0000000..c8340af
+#define HARD_INFO_SM4 BASE_TABLE_NULL
+#define HARD_INFO_SM2 BASE_TABLE_NULL
+
-+//#define CRYPTO_SWITCH_CPU
+#define NSEC_HARD_INFO_CIPHER BASE_TABLE_NULL
+#define NSEC_HARD_INFO_HASH BASE_TABLE_NULL
+#define NSEC_HARD_INFO_IFEP_RSA BASE_TABLE_NULL
@@ -254010,67 +322562,51 @@ index 0000000..c8340af
+#endif /* __DRV_OSAL_HI3516CV500_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3516ev200.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3516ev200.h
new file mode 100644
-index 0000000..0211d5d
+index 0000000..5f50707
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3516ev200.h
-@@ -0,0 +1,203 @@
+@@ -0,0 +1,198 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv osal hi3516ev200 configuration of cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_HI3516EV200_H__
+#define __DRV_OSAL_HI3516EV200_H__
+
-+/* the total cipher hard channel which we can used*/
-+#define CIPHER_HARD_CHANNEL_CNT (0x02)
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_CHANNEL_MASK (0x06)
++/* the total cipher hard channel which we can used. */
++#define CIPHER_HARD_CHANNEL_CNT 0x02
+
-+/* the total hash hard channel which we can used*/
-+#define HASH_HARD_CHANNEL_CNT (0x01)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_CHANNEL_MASK 0x06
+
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x02)
-+#define HASH_HARD_CHANNEL (0x01)
++/* the total hash hard channel which we can used. */
++#define HASH_HARD_CHANNEL_CNT 0x01
+
-+/* the total cipher hard key channel which we can used*/
-+#define CIPHER_HARD_KEY_CHANNEL_CNT (0x04)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x02
++#define HASH_HARD_CHANNEL 0x01
+
-+/* mask which cipher hard key channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_KEY_CHANNEL_MASK (0xF0)
++/* the total cipher hard key channel which we can used. */
++#define CIPHER_HARD_KEY_CHANNEL_CNT 0x04
+
-+/* support read IRQ number from DTS */
++/* mask which cipher hard key channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_KEY_CHANNEL_MASK 0xF0
++
++/* support read IRQ number from DTS. */
+#define IRQ_DTS_SUPPORT
+
-+/* support OTP load key */
++/* support OTP load key. */
+#define OTP_SUPPORT
+
-+/* support smmu*/
-+//#define CRYPTO_SMMU_SUPPORT
-+
+#ifndef __HuaweiLite__
-+/* support interrupt*/
++/* support interrupt. */
+#define CRYPTO_OS_INT_SUPPORT
+#endif
+
-+/* RSA RAND Mask*/
-+//#define RSA_RAND_MASK
-+
-+/* secure cpu*/
++/* secure cpu. */
+#define CRYPTO_SEC_CPU
+
+/* the hardware version */
@@ -254078,196 +322614,196 @@ index 0000000..0211d5d
+#define CHIP_HASH_VER_V200
+#define CHIP_TRNG_VER_V200
+#define CHIP_IFEP_RSA_VER_V100
-+//#define CHIP_SM2_VER_V100
+
-+/* support des */
-+//#define CHIP_DES_SUPPORT
++/*
++ * SMP version linux is sec config.
++ * moudle unsupport, we need set the table.
++ */
++#define BASE_TABLE_NULL { \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 0, \
++.crg_valid = 0, \
++.ver_valid = 0, \
++.int_valid = 0, \
++}
+
-+/* support 3des */
-+//#define CHIP_3DES_SUPPORT
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_CIPHER { \
++.name = "cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 66, \
++.reset_bit = 8, \
++.clk_bit = 9, \
++.version_reg = 0x308, \
++.version_val = 0x2018121, \
++.reg_addr_phy = 0x10050000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x120101A0, \
++}
+
-+/* supoort odd key */
-+//#define CHIP_SYMC_ODD_KEY_SUPPORT
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "hash", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 66, \
++.reset_bit = 8, \
++.clk_bit = 9, \
++.version_reg = 0x308, \
++.version_val = 0x2018121, \
++.reg_addr_phy = 0x10050000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x120101A0, \
++}
+
-+/* supoort SM1 */
-+//#define CHIP_SYMC_SM1_SUPPORT
++/* define initial value of struct sys_arch_boot_dts for HASH. */
++#define HARD_INFO_TRNG { \
++.name = "trng", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 0, \
++.int_valid = 0, \
++.reset_bit = 2, \
++.clk_bit = 3, \
++.reg_addr_phy = 0x10080200, \
++.reg_addr_size = 0x100, \
++.crg_addr_phy = 0x120101A0, \
++}
+
-+/* the hardware capacity */
-+//#define CHIP_AES_CCM_GCM_SUPPORT
++/* define sec rsa1 for SMP VERSION. */
++#define HARD_INFO_IFEP_RSA { \
++.name = "rsa0", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 0, \
++.reg_addr_phy = 0x10070000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x120101A0, \
++.reset_bit = 4, \
++.clk_bit = 5, \
++.version_reg = 0x90, \
++.version_val = 0, \
++}
+
-+/* the software capacity */
-+//#define SOFT_AES_SUPPORT
-+//#define SOFT_TDES_SUPPORT
-+//#define SOFT_AES_CCM_GCM_SUPPORT
-+//#define SOFT_SHA1_SUPPORT
-+//#define SOFT_SHA256_SUPPORT
-+//#define SOFT_SHA512_SUPPORT
-+//#define SOFT_SM2_SUPPORT
-+//#define SOFT_SM3_SUPPORT
-+//#define SOFT_ECC_SUPPORT
-+//#define SOFT_AES_CTS_SUPPORT
-+
-+/* SMP version linux is sec config */
-+/* moudle unsupport, we need set the table*/
-+#define BASE_TABLE_NULL {\
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 0, \
-+ .crg_valid = 0, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ }
-+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_CIPHER {\
-+ .name = "cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 66, \
-+ .reset_bit = 8, \
-+ .clk_bit = 9, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x2018121, \
-+ .reg_addr_phy = 0x10050000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
-+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "hash", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 66, \
-+ .reset_bit = 8, \
-+ .clk_bit = 9, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x2018121, \
-+ .reg_addr_phy = 0x10050000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
-+
-+/* define initial value of struct sys_arch_boot_dts for HASH*/
-+#define HARD_INFO_TRNG {\
-+ .name = "trng", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ .reset_bit = 2, \
-+ .clk_bit = 3, \
-+ .reg_addr_phy = 0x10080200, \
-+ .reg_addr_size = 0x100, \
-+ .crg_addr_phy = 0x120101A0, \
-+ }
-+
-+/* define sec rsa1 for SMP VERSION */
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "rsa0", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 0, \
-+ .reg_addr_phy = 0x10070000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x120101A0, \
-+ .reset_bit = 4, \
-+ .clk_bit = 5, \
-+ .version_reg = 0x90, \
-+ .version_val = 0, \
-+ }
-+
-+#define KLAD_REG_BASE_ADDR_PHY (0x10060000)
-+#define OTP_REG_BASE_ADDR_PHY (0x10090000)
-+#define KLAD_CRG_ADDR_PHY (0x120101A0)
-+#define REG_SYS_OTP_CLK_ADDR_PHY (0x120101BC)
++#define KLAD_REG_BASE_ADDR_PHY 0x10060000
++#define OTP_REG_BASE_ADDR_PHY 0x10090000
++#define KLAD_CRG_ADDR_PHY 0x120101A0
++#define REG_SYS_OTP_CLK_ADDR_PHY 0x120101BC
+
+#define OTP_CRG_CLOCK_BIT (0x01 << 1)
+
+#define KLAD_CRG_CLOCK_BIT (0x01 << 1)
+#define KLAD_CRG_RESET_BIT (0x01 << 0)
+
-+#define HARD_INFO_SMMU BASE_TABLE_NULL
-+#define HARD_INFO_SIC_RSA BASE_TABLE_NULL
-+#define HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
-+#define HARD_INFO_SM4 BASE_TABLE_NULL
-+#define HARD_INFO_SM2 BASE_TABLE_NULL
++/* support des.
++ * CHIP_DES_SUPPORT
++ *
++ * support 3des.
++ * CHIP_3DES_SUPPORT
++ *
++ * supoort odd key.
++ * CHIP_SYMC_ODD_KEY_SUPPORT
++ *
++ * supoort SM1.
++ * CHIP_SYMC_SM1_SUPPORT
++ *
++ * the hardware capacity.
++ * CHIP_AES_CCM_GCM_SUPPORT
++ *
++ * supoort sm2 ver v100.
++ * CHIP_SM2_VER_V100
++ *
++ * RSA rand mask.
++ * RSA_RAND_MASK
++ *
++ * support smmu.
++ * CRYPTO_SMMU_SUPPORT
++ *
++ *
++ * the software capacity.
++ * SOFT_AES_SUPPORT
++ * SOFT_TDES_SUPPORT
++ * SOFT_AES_CCM_GCM_SUPPORT
++ * SOFT_SHA1_SUPPORT
++ * SOFT_SHA256_SUPPORT
++ * SOFT_SHA512_SUPPORT
++ * SOFT_SM2_SUPPORT
++ * SOFT_SM3_SUPPORT
++ * SOFT_ECC_SUPPORT
++ * SOFT_AES_CTS_SUPPORT
++ */
++#define HARD_INFO_SMMU BASE_TABLE_NULL
++#define HARD_INFO_SIC_RSA BASE_TABLE_NULL
++#define HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
++#define HARD_INFO_SM4 BASE_TABLE_NULL
++#define HARD_INFO_SM2 BASE_TABLE_NULL
+
-+#define NSEC_HARD_INFO_CIPHER BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_HASH BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_IFEP_RSA BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_SMMU BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_SIC_RSA BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_SM4 BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_SM2 BASE_TABLE_NULL
-+#define NSEC_HARD_INFO_TRNG BASE_TABLE_NULL
++#define NSEC_HARD_INFO_CIPHER BASE_TABLE_NULL
++#define NSEC_HARD_INFO_HASH BASE_TABLE_NULL
++#define NSEC_HARD_INFO_IFEP_RSA BASE_TABLE_NULL
++#define NSEC_HARD_INFO_SMMU BASE_TABLE_NULL
++#define NSEC_HARD_INFO_SIC_RSA BASE_TABLE_NULL
++#define NSEC_HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
++#define NSEC_HARD_INFO_SM4 BASE_TABLE_NULL
++#define NSEC_HARD_INFO_SM2 BASE_TABLE_NULL
++#define NSEC_HARD_INFO_TRNG BASE_TABLE_NULL
+
+#endif /* __DRV_OSAL_HI3516EV200_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3519av100.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3519av100.h
new file mode 100644
-index 0000000..da8be73
+index 0000000..e548831
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3519av100.h
-@@ -0,0 +1,277 @@
+@@ -0,0 +1,272 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cipher drv osal configuration to hi3519av100.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_HI3519AV100_H__
+#define __DRV_OSAL_HI3519AV100_H__
+
-+/* the total cipher hard channel which we can used*/
-+#define CIPHER_HARD_CHANNEL_CNT (0x07)
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_CHANNEL_MASK (0xFE)
++/* the total cipher hard channel which we can used. */
++#define CIPHER_HARD_CHANNEL_CNT 0x07
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_CHANNEL_MASK 0xFE
+
-+/* the total hash hard channel which we can used*/
-+#define HASH_HARD_CHANNEL_CNT (0x01)
++/* the total hash hard channel which we can used. */
++#define HASH_HARD_CHANNEL_CNT 0x01
+
+#ifdef __HuaweiLite__
+/* liteos resource config */
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x04)
-+#define HASH_HARD_CHANNEL (0x02)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x04
++#define HASH_HARD_CHANNEL 0x02
+#else
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x02)
-+#define HASH_HARD_CHANNEL (0x01)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x02
++#define HASH_HARD_CHANNEL 0x01
+#endif
+
-+/* the total cipher hard key channel which we can used*/
-+#define CIPHER_HARD_KEY_CHANNEL_CNT (0x04)
++/* the total cipher hard key channel which we can used. */
++#define CIPHER_HARD_KEY_CHANNEL_CNT 0x04
+
-+/* mask which cipher hard key channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_KEY_CHANNEL_MASK (0xF0)
++/* mask which cipher hard key channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_KEY_CHANNEL_MASK 0xF0
+
+/* support read IRQ number from DTS */
+#define IRQ_DTS_SUPPORT
@@ -254275,22 +322811,15 @@ index 0000000..da8be73
+/* support OTP load key */
+#define OTP_SUPPORT
+
-+/* support smmu*/
-+//#define CRYPTO_SMMU_SUPPORT
-+
+#ifndef __HuaweiLite__
-+/* support interrupt*/
++/* support interrupt. */
+#define CRYPTO_OS_INT_SUPPORT
+#endif
+
-+/* RSA RAND Mask*/
-+//#define RSA_RAND_MASK
-+
+/* the hardware version */
+#define CHIP_SYMC_VER_V200
+#define CHIP_HASH_VER_V200
+#define CHIP_IFEP_RSA_VER_V100
-+//#define CHIP_SM2_VER_V100
+
+/* support des */
+#define CHIP_DES_SUPPORT
@@ -254298,181 +322827,163 @@ index 0000000..da8be73
+/* support 3des */
+#define CHIP_3DES_SUPPORT
+
-+/* supoort odd key */
-+//#define CHIP_SYMC_ODD_KEY_SUPPORT
-+
-+/* supoort SM1 */
-+//#define CHIP_SYMC_SM1_SUPPORT
-+
+/* the hardware capacity */
+#define CHIP_AES_CCM_GCM_SUPPORT
+
-+/* the software capacity */
-+//#define SOFT_AES_SUPPORT
-+//#define SOFT_TDES_SUPPORT
-+//#define SOFT_AES_CCM_GCM_SUPPORT
-+//#define SOFT_SHA1_SUPPORT
-+//#define SOFT_SHA256_SUPPORT
-+//#define SOFT_SHA512_SUPPORT
-+//#define SOFT_SM2_SUPPORT
-+//#define SOFT_SM3_SUPPORT
-+//#define SOFT_ECC_SUPPORT
-+//#define SOFT_AES_CTS_SUPPORT
-+
-+/* moudle unsupport, we need set the table*/
-+#define BASE_TABLE_NULL {\
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 0, \
-+ .crg_valid = 0, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ }
++/* moudle unsupport, we need set the table. */
++#define BASE_TABLE_NULL { \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 0, \
++.crg_valid = 0, \
++.ver_valid = 0, \
++.int_valid = 0, \
++}
+
+#if defined(ARCH_TYPE_amp) && !defined(AMP_NONSECURE_VERSION) && !defined(__HuaweiLite__)
+
+/* linux of AMP use non-secure config */
+#define HARD_INFO_TRNG BASE_TABLE_NULL
+
-+#define HARD_INFO_CIPHER {\
-+ .name = "nonsec_cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 126, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x04060000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x0451016c, \
-+ }
++#define HARD_INFO_CIPHER { \
++.name = "nonsec_cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 126, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x04060000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x0451016c, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "nonsec_hash", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 126, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x04060000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x0451016c, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "nonsec_hash", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 126, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x04060000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x0451016c, \
++}
+
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "nonsec_rsa", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .reg_addr_phy = 0x04080000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x04510194, \
-+ .reset_bit = 14, \
-+ .clk_bit = 15, \
-+ .int_num = 117, \
-+ .version_reg = 0x90, \
-+ .version_val = 0x20160907, \
-+ }
++#define HARD_INFO_IFEP_RSA { \
++.name = "nonsec_rsa", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.reg_addr_phy = 0x04080000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x04510194, \
++.reset_bit = 14, \
++.clk_bit = 15, \
++.int_num = 117, \
++.version_reg = 0x90, \
++.version_val = 0x20160907, \
++}
+#else
+/* SMP, liteos of secure AMP, linux of non-secure AMP use secure config */
+#define CRYPTO_SEC_CPU
+
+#define CHIP_TRNG_VER_V200
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_CIPHER {\
-+ .name = "cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 125, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x04060000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x0451016c, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_CIPHER { \
++.name = "cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 125, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x04060000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x0451016c, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "hash", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 125, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x04060000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x0451016c, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "hash", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 125, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x04060000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x0451016c, \
++}
+
+/* linux use rsa0, liteos use rsa1 */
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "rsa", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .reg_addr_phy = 0x04088000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x04510194, \
-+ .reset_bit = 22, \
-+ .clk_bit = 23, \
-+ .int_num = 127, \
-+ .version_reg = 0x90, \
-+ .version_val = 0x20160907, \
-+ }
++#define HARD_INFO_IFEP_RSA { \
++.name = "rsa", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.reg_addr_phy = 0x04088000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x04510194, \
++.reset_bit = 22, \
++.clk_bit = 23, \
++.int_num = 127, \
++.version_reg = 0x90, \
++.version_val = 0x20160907, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for HASH*/
-+#define HARD_INFO_TRNG {\
-+ .name = "trng", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ .reset_bit = 12, \
-+ .clk_bit = 13, \
-+ .reg_addr_phy = 0x04090200, \
-+ .reg_addr_size = 0x100, \
-+ .crg_addr_phy = 0x04510194, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for HASH. */
++#define HARD_INFO_TRNG { \
++.name = "trng", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 0, \
++.int_valid = 0, \
++.reset_bit = 12, \
++.clk_bit = 13, \
++.reg_addr_phy = 0x04090200, \
++.reg_addr_size = 0x100, \
++.crg_addr_phy = 0x04510194, \
++}
+#endif
+
-+#define KLAD_REG_BASE_ADDR_PHY (0x04070000)
-+#define OTP_REG_BASE_ADDR_PHY (0x040A0000)
-+#define KLAD_CRG_ADDR_PHY (0x04510194)
-+#define REG_SYS_OTP_CLK_ADDR_PHY (0x04510194)
-+#define SPACC_PROT_BYPASS_N (0x04C50004)
++#define KLAD_REG_BASE_ADDR_PHY 0x04070000
++#define OTP_REG_BASE_ADDR_PHY 0x040A0000
++#define KLAD_CRG_ADDR_PHY 0x04510194
++#define REG_SYS_OTP_CLK_ADDR_PHY 0x04510194
++#define SPACC_PROT_BYPASS_N 0x04C50004
+
+#define SPACC_PROT_BYPASS_N_BIT (0x01 << 12)
+#define RSA1_PROT_BYPASS_N_BIT (0x01 << 18)
@@ -254482,13 +322993,44 @@ index 0000000..da8be73
+#define KLAD_CRG_CLOCK_BIT (0x01 << 11)
+#define KLAD_CRG_RESET_BIT (0x01 << 10)
+
++/* support smmu.
++ * CRYPTO_SMMU_SUPPORT
++ *
++ * RSA rand mask.
++ * RSA_RAND_MASK
++ *
++ * support chip sm2.
++ * CHIP_SM2_VER_V100
++ *
++ * supoort odd key.
++ * CHIP_SYMC_ODD_KEY_SUPPORT
++ *
++ * supoort SM1
++ * CHIP_SYMC_SM1_SUPPORT
++ *
++ *
++ * the software capacity.
++ * SOFT_AES_SUPPORT
++ * SOFT_TDES_SUPPORT
++ * SOFT_AES_CCM_GCM_SUPPORT
++ * SOFT_SHA1_SUPPORT
++ * SOFT_SHA256_SUPPORT
++ * SOFT_SHA512_SUPPORT
++ * SOFT_SM2_SUPPORT
++ * SOFT_SM3_SUPPORT
++ * SOFT_ECC_SUPPORT
++ * SOFT_AES_CTS_SUPPORT
++ */
+#define HARD_INFO_SMMU BASE_TABLE_NULL
+#define HARD_INFO_SIC_RSA BASE_TABLE_NULL
+#define HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
+#define HARD_INFO_SM4 BASE_TABLE_NULL
+#define HARD_INFO_SM2 BASE_TABLE_NULL
+
-+//#define CRYPTO_SWITCH_CPU
++/*
++ * supoort switch cpu
++ * CRYPTO_SWITCH_CPU
++ */
+#define NSEC_HARD_INFO_CIPHER BASE_TABLE_NULL
+#define NSEC_HARD_INFO_HASH BASE_TABLE_NULL
+#define NSEC_HARD_INFO_IFEP_RSA BASE_TABLE_NULL
@@ -254502,76 +323044,52 @@ index 0000000..da8be73
+#endif /* __DRV_OSAL_HI3519AV100_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3559.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3559.h
new file mode 100644
-index 0000000..d60c8a0
+index 0000000..6e7f899
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3559.h
-@@ -0,0 +1,367 @@
+@@ -0,0 +1,359 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : drivers for drv osal hi3559av100 configuration for cipher.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_HI3559AV100_H__
+#define __DRV_OSAL_HI3559AV100_H__
+
-+#ifdef __HuaweiLite__
+/* liteos use non-secure CPU */
++#ifdef __HuaweiLite__
++/* the total cipher hard channel which we can used. */
++#define CIPHER_HARD_CHANNEL_CNT 0x07
+
-+/* the total cipher hard channel which we can used*/
-+#define CIPHER_HARD_CHANNEL_CNT (0x07)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_CHANNEL_MASK 0xFE
+
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_CHANNEL_MASK (0xFE)
++/* the total hash hard channel which we can used. */
++#define HASH_HARD_CHANNEL_CNT 0x01
+
-+/* the total hash hard channel which we can used*/
-+#define HASH_HARD_CHANNEL_CNT (0x01)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x02
++#define HASH_HARD_CHANNEL 0x01
+
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x02)
-+#define HASH_HARD_CHANNEL (0x01)
++/* the total cipher hard key channel which we can used. */
++#define CIPHER_HARD_KEY_CHANNEL_CNT 0x04
+
-+/* the total cipher hard key channel which we can used*/
-+#define CIPHER_HARD_KEY_CHANNEL_CNT (0x04)
++/* mask which cipher hard key channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_KEY_CHANNEL_MASK 0xF0
+
-+/* mask which cipher hard key channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_KEY_CHANNEL_MASK (0xF0)
-+
-+/* support OTP load key */
++/* support OTP load key. */
+#define OTP_SUPPORT
+
-+/* support read IRQ number from DTS */
-+
-+/* support smmu*/
-+//#define CRYPTO_SMMU_SUPPORT
-+
-+/* support interrupt*/
++/* support interrupt. */
+#define CRYPTO_OS_INT_SUPPORT
+
-+/* RSA RAND Mask*/
-+//#define RSA_RAND_MASK
-+
-+/* secure cpu*/
-+//#define CRYPTO_SEC_CPU
-+
+/* the hardware version */
+#define CHIP_SYMC_VER_V200
+#define CHIP_HASH_VER_V200
+#define CHIP_TRNG_VER_V200
+#define CHIP_IFEP_RSA_VER_V100
-+//#define CHIP_SM2_VER_V100
+
+/* support des */
+#define CHIP_DES_SUPPORT
@@ -254579,145 +323097,158 @@ index 0000000..d60c8a0
+/* support 3des */
+#define CHIP_3DES_SUPPORT
+
-+/* supoort odd key */
-+//#define CHIP_SYMC_ODD_KEY_SUPPORT
-+
-+/* supoort SM1 */
-+#define CHIP_SYMC_SM1_SUPPORT
-+
+/* the hardware capacity */
+#define CHIP_AES_CCM_GCM_SUPPORT
+
-+/* the software capacity */
-+//#define SOFT_AES_SUPPORT
-+//#define SOFT_TDES_SUPPORT
-+//#define SOFT_AES_CCM_GCM_SUPPORT
-+//#define SOFT_SHA1_SUPPORT
-+//#define SOFT_SHA256_SUPPORT
-+//#define SOFT_SHA512_SUPPORT
-+//#define SOFT_SM2_SUPPORT
-+//#define SOFT_SM3_SUPPORT
-+//#define SOFT_ECC_SUPPORT
-+//#define SOFT_AES_CTS_SUPPORT
++/* moudle unsupport, we need set the table. */
++#define BASE_TABLE_NULL { \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 0, \
++.crg_valid = 0, \
++.ver_valid = 0, \
++.int_valid = 0, \
++}
+
-+/* moudle unsupport, we need set the table*/
-+#define BASE_TABLE_NULL {\
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 0, \
-+ .crg_valid = 0, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_CIPHER { \
++.name = "cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 62, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x10200000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x1201016C, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_CIPHER {\
-+ .name = "cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 62, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x10200000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x1201016C, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "cipher", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 62, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x10200000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x1201016C, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "cipher", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 62, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x10200000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x1201016C, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for HASH. */
++#define HARD_INFO_TRNG { \
++.name = "trng", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 0, \
++.int_valid = 0, \
++.reset_bit = 12, \
++.clk_bit = 13, \
++.reg_addr_phy = 0x10230200, \
++.reg_addr_size = 0x100, \
++.crg_addr_phy = 0x12010194, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for HASH*/
-+#define HARD_INFO_TRNG {\
-+ .name = "trng", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ .reset_bit = 12, \
-+ .clk_bit = 13, \
-+ .reg_addr_phy = 0x10230200, \
-+ .reg_addr_size = 0x100, \
-+ .crg_addr_phy = 0x12010194, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for IFEP RSA. */
++#define HARD_INFO_IFEP_RSA { \
++.name = "rsa", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.reg_addr_phy = 0x10220000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x12010194, \
++.reset_bit = 14, \
++.clk_bit = 15, \
++.int_num = 136, \
++.version_reg = 0x90, \
++.version_val = 0x20160907, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for IFEP RSA*/
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "rsa", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .reg_addr_phy = 0x10220000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x12010194, \
-+ .reset_bit = 14, \
-+ .clk_bit = 15, \
-+ .int_num = 136, \
-+ .version_reg = 0x90, \
-+ .version_val = 0x20160907, \
-+ }
++#define KLAD_REG_BASE_ADDR_PHY 0x10210000
++#define OTP_REG_BASE_ADDR_PHY 0x10240000
++#define KLAD_CRG_ADDR_PHY 0x12010194
++#define REG_SYS_OTP_CLK_ADDR_PHY 0x12010194
+
-+#define KLAD_REG_BASE_ADDR_PHY (0x10210000)
-+#define OTP_REG_BASE_ADDR_PHY (0x10240000)
-+#define KLAD_CRG_ADDR_PHY (0x12010194)
-+#define REG_SYS_OTP_CLK_ADDR_PHY (0x12010194)
-+
-+#define OTP_CRG_CLOCK_BIT (0x01 << 7)
-+#define OTP_CRG_RESET_BIT (0x01 << 6)
++#define OTP_CRG_CLOCK_BIT (0x01 << 7)
++#define OTP_CRG_RESET_BIT (0x01 << 6)
+
+#define KLAD_CRG_CLOCK_BIT (0x01 << 11)
+#define KLAD_CRG_RESET_BIT (0x01 << 10)
+
++/* support smmu.
++ * CRYPTO_SMMU_SUPPORT
++ *
++ * RSA rand mask.
++ * RSA_RAND_MASK
++ *
++ * secure cpu.
++ * CRYPTO_SEC_CPU
++ *
++ * support chip sm2.
++ * CHIP_SM2_VER_V100
++ *
++ * supoort odd key.
++ * CHIP_SYMC_ODD_KEY_SUPPORT
++ *
++ * supoort SM1
++ * CHIP_SYMC_SM1_SUPPORT
++ *
++ *
++ * the software capacity.
++ * SOFT_AES_SUPPORT
++ * SOFT_TDES_SUPPORT
++ * SOFT_AES_CCM_GCM_SUPPORT
++ * SOFT_SHA1_SUPPORT
++ * SOFT_SHA256_SUPPORT
++ * SOFT_SHA512_SUPPORT
++ * SOFT_SM2_SUPPORT
++ * SOFT_SM3_SUPPORT
++ * SOFT_ECC_SUPPORT
++ * SOFT_AES_CTS_SUPPORT
++ */
+#define HARD_INFO_SMMU BASE_TABLE_NULL
+#define HARD_INFO_SIC_RSA BASE_TABLE_NULL
+#define HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
+#define HARD_INFO_SM4 BASE_TABLE_NULL
+#define HARD_INFO_SM2 BASE_TABLE_NULL
+#else
-+/* the total cipher hard channel which we can used*/
-+#define CIPHER_HARD_CHANNEL_CNT (0x07)
++/* the total cipher hard channel which we can used. */
++#define CIPHER_HARD_CHANNEL_CNT 0x07
+
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_CHANNEL_MASK (0xFE)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_CHANNEL_MASK 0xFE
+
-+/* the total hash hard channel which we can used*/
-+#define HASH_HARD_CHANNEL_CNT (0x01)
++/* the total hash hard channel which we can used. */
++#define HASH_HARD_CHANNEL_CNT 0x01
+
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x02)
-+#define HASH_HARD_CHANNEL (0x01)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x02
++#define HASH_HARD_CHANNEL 0x01
+
-+/* the total cipher hard key channel which we can used*/
-+#define CIPHER_HARD_KEY_CHANNEL_CNT (0x04)
++/* the total cipher hard key channel which we can used. */
++#define CIPHER_HARD_KEY_CHANNEL_CNT 0x04
+
-+/* mask which cipher hard key channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_KEY_CHANNEL_MASK (0xF0)
++/* mask which cipher hard key channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_KEY_CHANNEL_MASK 0xF0
+
+/* support OTP load key */
+#define OTP_SUPPORT
@@ -254725,24 +323256,14 @@ index 0000000..d60c8a0
+/* support read IRQ number from DTS */
+#define IRQ_DTS_SUPPORT
+
-+/* support smmu*/
-+//#define CRYPTO_SMMU_SUPPORT
-+
-+/* support interrupt*/
++/* support interrupt. */
+#define CRYPTO_OS_INT_SUPPORT
+
-+/* RSA RAND Mask*/
-+//#define RSA_RAND_MASK
-+
-+/* secure cpu*/
-+//#define CRYPTO_SEC_CPU
-+
+/* the hardware version */
+#define CHIP_SYMC_VER_V200
+#define CHIP_HASH_VER_V200
+#define CHIP_TRNG_VER_V200
+#define CHIP_IFEP_RSA_VER_V100
-+//#define CHIP_SM2_VER_V100
+
+/* support des */
+#define CHIP_DES_SUPPORT
@@ -254750,121 +323271,134 @@ index 0000000..d60c8a0
+/* support 3des */
+#define CHIP_3DES_SUPPORT
+
-+/* supoort odd key */
-+//#define CHIP_SYMC_ODD_KEY_SUPPORT
-+
-+/* supoort SM1 */
-+#define CHIP_SYMC_SM1_SUPPORT
-+
+/* the hardware capacity */
+#define CHIP_AES_CCM_GCM_SUPPORT
+
-+/* the software capacity */
-+//#define SOFT_AES_SUPPORT
-+//#define SOFT_TDES_SUPPORT
-+//#define SOFT_AES_CCM_GCM_SUPPORT
-+//#define SOFT_SHA1_SUPPORT
-+//#define SOFT_SHA256_SUPPORT
-+//#define SOFT_SHA512_SUPPORT
-+//#define SOFT_SM2_SUPPORT
-+//#define SOFT_SM3_SUPPORT
-+//#define SOFT_ECC_SUPPORT
-+//#define SOFT_AES_CTS_SUPPORT
++/* moudle unsupport, we need set the table. */
++#define BASE_TABLE_NULL { \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 0, \
++.crg_valid = 0, \
++.ver_valid = 0, \
++.int_valid = 0, \
++}
+
-+/* moudle unsupport, we need set the table*/
-+#define BASE_TABLE_NULL {\
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 0, \
-+ .crg_valid = 0, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_CIPHER { \
++.name = "cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 62, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x10200000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x1201016C, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_CIPHER {\
-+ .name = "cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 62, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x10200000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x1201016C, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "hash", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 62, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20170609, \
++.reg_addr_phy = 0x10200000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x1201016C, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "hash", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 62, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20170609, \
-+ .reg_addr_phy = 0x10200000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x1201016C, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for HASH. */
++#define HARD_INFO_TRNG { \
++.name = "trng", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 0, \
++.int_valid = 0, \
++.reset_bit = 12, \
++.clk_bit = 13, \
++.reg_addr_phy = 0x10230200, \
++.reg_addr_size = 0x100, \
++.crg_addr_phy = 0x12010194, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for HASH*/
-+#define HARD_INFO_TRNG {\
-+ .name = "trng", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ .reset_bit = 12, \
-+ .clk_bit = 13, \
-+ .reg_addr_phy = 0x10230200, \
-+ .reg_addr_size = 0x100, \
-+ .crg_addr_phy = 0x12010194, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for IFEP RSA. */
++#define HARD_INFO_IFEP_RSA { \
++.name = "rsa", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.reg_addr_phy = 0x10220000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x12010194, \
++.reset_bit = 14, \
++.clk_bit = 15, \
++.int_num = 136, \
++.version_reg = 0x90, \
++.version_val = 0x20160907, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for IFEP RSA*/
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "rsa", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .reg_addr_phy = 0x10220000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x12010194, \
-+ .reset_bit = 14, \
-+ .clk_bit = 15, \
-+ .int_num = 136, \
-+ .version_reg = 0x90, \
-+ .version_val = 0x20160907, \
-+ }
++#define KLAD_REG_BASE_ADDR_PHY 0x10210000
++#define OTP_REG_BASE_ADDR_PHY 0x10240000
++#define KLAD_CRG_ADDR_PHY 0x12010194
++#define REG_SYS_OTP_CLK_ADDR_PHY 0x12010194
+
-+#define KLAD_REG_BASE_ADDR_PHY (0x10210000)
-+#define OTP_REG_BASE_ADDR_PHY (0x10240000)
-+#define KLAD_CRG_ADDR_PHY (0x12010194)
-+#define REG_SYS_OTP_CLK_ADDR_PHY (0x12010194)
-+
-+#define OTP_CRG_CLOCK_BIT (0x01 << 7)
-+#define OTP_CRG_RESET_BIT (0x01 << 6)
++#define OTP_CRG_CLOCK_BIT (0x01 << 7)
++#define OTP_CRG_RESET_BIT (0x01 << 6)
+
+#define KLAD_CRG_CLOCK_BIT (0x01 << 11)
+#define KLAD_CRG_RESET_BIT (0x01 << 10)
+
++/* support smmu.
++ * CRYPTO_SMMU_SUPPORT
++ *
++ * RSA rand mask.
++ * RSA_RAND_MASK
++ *
++ * secure cpu.
++ * CRYPTO_SEC_CPU
++ *
++ * support chip sm2.
++ * CHIP_SM2_VER_V100
++ *
++ * supoort odd key.
++ * CHIP_SYMC_ODD_KEY_SUPPORT
++ *
++ * supoort SM1
++ * CHIP_SYMC_SM1_SUPPORT
++ *
++ *
++ * the software capacity.
++ * SOFT_AES_SUPPORT
++ * SOFT_TDES_SUPPORT
++ * SOFT_AES_CCM_GCM_SUPPORT
++ * SOFT_SHA1_SUPPORT
++ * SOFT_SHA256_SUPPORT
++ * SOFT_SHA512_SUPPORT
++ * SOFT_SM2_SUPPORT
++ * SOFT_SM3_SUPPORT
++ * SOFT_ECC_SUPPORT
++ * SOFT_AES_CTS_SUPPORT
++ */
+#define HARD_INFO_SMMU BASE_TABLE_NULL
+#define HARD_INFO_SIC_RSA BASE_TABLE_NULL
+#define HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
@@ -254875,63 +323409,46 @@ index 0000000..d60c8a0
+#endif /* __DRV_OSAL_HI3559AV100_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3559aes.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3559aes.h
new file mode 100644
-index 0000000..daf9d28
+index 0000000..4d32e2c
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_hi3559aes.h
-@@ -0,0 +1,186 @@
+@@ -0,0 +1,178 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for drv osal hi3559aes configuration.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_HI3559AES_H__
+#define __DRV_OSAL_HI3559AES_H__
+
-+/* the total cipher hard channel which we can used*/
-+#define CIPHER_HARD_CHANNEL_CNT (0x07)
++/* the total cipher hard channel which we can used. */
++#define CIPHER_HARD_CHANNEL_CNT 0x07
+
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_CHANNEL_MASK (0xFE)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_CHANNEL_MASK 0xFE
+
-+/* the total hash hard channel which we can used*/
-+#define HASH_HARD_CHANNEL_CNT (0x01)
++/* the total hash hard channel which we can used. */
++#define HASH_HARD_CHANNEL_CNT 0x01
+
-+/* mask which cipher channel we can used, bit0 means channel 0*/
-+#define HASH_HARD_CHANNEL_MASK (0x02)
-+#define HASH_HARD_CHANNEL (0x01)
++/* mask which cipher channel we can used, bit0 means channel 0. */
++#define HASH_HARD_CHANNEL_MASK 0x02
++#define HASH_HARD_CHANNEL 0x01
+
-+/* the total cipher hard key channel which we can used*/
-+#define CIPHER_HARD_KEY_CHANNEL_CNT (0x04)
++/* the total cipher hard key channel which we can used. */
++#define CIPHER_HARD_KEY_CHANNEL_CNT 0x04
+
-+/* mask which cipher hard key channel we can used, bit0 means channel 0*/
-+#define CIPHER_HARD_KEY_CHANNEL_MASK (0xF0)
++/* mask which cipher hard key channel we can used, bit0 means channel 0. */
++#define CIPHER_HARD_KEY_CHANNEL_MASK 0xF0
+
-+/* support EFUSE load key */
++/* support EFUSE load key. */
+#define EFUSE_SUPPORT
+
-+/* support smmu*/
-+//#define CRYPTO_SMMU_SUPPORT
-+
-+/* support interrupt*/
++/* support interrupt. */
+#define CRYPTO_OS_INT_SUPPORT
+
-+/* RSA RAND Mask*/
-+//#define RSA_RAND_MASK
-+
-+/* secure cpu*/
++/* secure cpu. */
+#define CRYPTO_SEC_CPU
+
+/* the hardware version */
@@ -254939,125 +323456,134 @@ index 0000000..daf9d28
+#define CHIP_HASH_VER_V200
+#define CHIP_TRNG_VER_V200
+#define CHIP_IFEP_RSA_VER_V100
-+//#define CHIP_SM2_VER_V100
+
-+/* support des */
++/* support des. */
+#define CHIP_DES_SUPPORT
+
-+/* support 3des */
++/* support 3des. */
+#define CHIP_3DES_SUPPORT
+
-+/* supoort odd key */
-+//#define CHIP_SYMC_ODD_KEY_SUPPORT
-+
-+/* supoort SM1 */
-+#define CHIP_SYMC_SM1_SUPPORT
-+
-+/* the hardware capacity */
++/* the hardware capacity. */
+#define CHIP_AES_CCM_GCM_SUPPORT
+
-+/* the software capacity */
-+//#define SOFT_AES_SUPPORT
-+//#define SOFT_TDES_SUPPORT
-+//#define SOFT_AES_CCM_GCM_SUPPORT
-+//#define SOFT_SHA1_SUPPORT
-+//#define SOFT_SHA256_SUPPORT
-+//#define SOFT_SHA512_SUPPORT
-+//#define SOFT_SM2_SUPPORT
-+//#define SOFT_SM3_SUPPORT
-+//#define SOFT_ECC_SUPPORT
-+//#define SOFT_AES_CTS_SUPPORT
++/* moudle unsupport, we need set the table. */
++#define BASE_TABLE_NULL { \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 0, \
++.crg_valid = 0, \
++.ver_valid = 0, \
++.int_valid = 0, \
++}
+
-+/* moudle unsupport, we need set the table*/
-+#define BASE_TABLE_NULL {\
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 0, \
-+ .crg_valid = 0, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_CIPHER { \
++.name = "cipher", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 59, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20161117, \
++.reg_addr_phy = 0x10200000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x1201016C, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_CIPHER {\
-+ .name = "cipher", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 59, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20161117, \
-+ .reg_addr_phy = 0x10200000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x1201016C, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for cipher. */
++#define HARD_INFO_HASH { \
++.name = "cipher", \
++.reset_valid = 0, \
++.clk_valid = 0, \
++.phy_valid = 1, \
++.crg_valid = 0, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.int_num = 59, \
++.reset_bit = 0, \
++.clk_bit = 1, \
++.version_reg = 0x308, \
++.version_val = 0x20161117, \
++.reg_addr_phy = 0x10200000, \
++.reg_addr_size = 0x4000, \
++.crg_addr_phy = 0x1201016C, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for cipher*/
-+#define HARD_INFO_HASH {\
-+ .name = "cipher", \
-+ .reset_valid = 0, \
-+ .clk_valid = 0, \
-+ .phy_valid = 1, \
-+ .crg_valid = 0, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .int_num = 59, \
-+ .reset_bit = 0, \
-+ .clk_bit = 1, \
-+ .version_reg = 0x308, \
-+ .version_val = 0x20161117, \
-+ .reg_addr_phy = 0x10200000, \
-+ .reg_addr_size = 0x4000, \
-+ .crg_addr_phy = 0x1201016C, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for HASH. */
++#define HARD_INFO_TRNG { \
++.name = "trng", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 0, \
++.int_valid = 0, \
++.reset_bit = 12, \
++.clk_bit = 13, \
++.reg_addr_phy = 0x10230200, \
++.reg_addr_size = 0x100, \
++.crg_addr_phy = 0x12010194, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for HASH*/
-+#define HARD_INFO_TRNG {\
-+ .name = "trng", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 0, \
-+ .int_valid = 0, \
-+ .reset_bit = 12, \
-+ .clk_bit = 13, \
-+ .reg_addr_phy = 0x10230200, \
-+ .reg_addr_size = 0x100, \
-+ .crg_addr_phy = 0x12010194, \
-+ }
++/* define initial value of struct sys_arch_boot_dts for IFEP RSA. */
++#define HARD_INFO_IFEP_RSA { \
++.name = "rsa", \
++.reset_valid = 1, \
++.clk_valid = 1, \
++.phy_valid = 1, \
++.crg_valid = 1, \
++.ver_valid = 1, \
++.int_valid = 1, \
++.reg_addr_phy = 0x10220000, \
++.reg_addr_size = 0x1000, \
++.crg_addr_phy = 0x12010194, \
++.reset_bit = 14, \
++.clk_bit = 15, \
++.int_num = 136, \
++.version_reg = 0x90, \
++.version_val = 0x20160907, \
++}
+
-+/* define initial value of struct sys_arch_boot_dts for IFEP RSA*/
-+#define HARD_INFO_IFEP_RSA {\
-+ .name = "rsa", \
-+ .reset_valid = 1, \
-+ .clk_valid = 1, \
-+ .phy_valid = 1, \
-+ .crg_valid = 1, \
-+ .ver_valid = 1, \
-+ .int_valid = 1, \
-+ .reg_addr_phy = 0x10220000, \
-+ .reg_addr_size = 0x1000,\
-+ .crg_addr_phy = 0x12010194, \
-+ .reset_bit = 14, \
-+ .clk_bit = 15, \
-+ .int_num = 136, \
-+ .version_reg = 0x90, \
-+ .version_val = 0x20160907, \
-+ }
-+
-+#define KLAD_REG_BASE_ADDR_PHY (0x10210000)
-+#define ENFUSE_REG_BASE_ADDR_PHY (0x10250000)
-+#define KLAD_CRG_ADDR_PHY (0x12010194)
++#define KLAD_REG_BASE_ADDR_PHY 0x10210000
++#define ENFUSE_REG_BASE_ADDR_PHY 0x10250000
++#define KLAD_CRG_ADDR_PHY 0x12010194
+
+#define KLAD_CRG_CLOCK_BIT (0x01 << 11)
+#define KLAD_CRG_RESET_BIT (0x01 << 10)
+
++/* rsa rand mask.
++ * RSA_RAND_MASK
++ *
++ * support smmu.
++ * CRYPTO_SMMU_SUPPORT
++ *
++ * supoort sm2 v100.
++ * CHIP_SM2_VER_V100
++ *
++ * supoort odd key.
++ * CHIP_SYMC_ODD_KEY_SUPPORT
++ *
++ * supoort sm1.
++ * CHIP_SYMC_SM1_SUPPORT
++ *
++ *
++ * the software capacity.
++ * SOFT_AES_SUPPORT
++ * SOFT_TDES_SUPPORT
++ * SOFT_AES_CCM_GCM_SUPPORT
++ * SOFT_SHA1_SUPPORT
++ * SOFT_SHA256_SUPPORT
++ * SOFT_SHA512_SUPPORT
++ * SOFT_SM2_SUPPORT
++ * SOFT_SM3_SUPPORT
++ * SOFT_ECC_SUPPORT
++ * SOFT_AES_CTS_SUPPORT
++ */
+#define HARD_INFO_SMMU BASE_TABLE_NULL
+#define HARD_INFO_SIC_RSA BASE_TABLE_NULL
+#define HARD_INFO_CIPHER_KEY BASE_TABLE_NULL
@@ -255067,31 +323593,21 @@ index 0000000..daf9d28
+#endif /* __DRV_OSAL_HI3559AES_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib.h
new file mode 100644
-index 0000000..3a3b2f1
+index 0000000..3e393ac
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib.h
-@@ -0,0 +1,474 @@
+@@ -0,0 +1,499 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (C), Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for cipher drv osal lib.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_LIB_H__
+#define __DRV_OSAL_LIB_H__
+
++#include "drv_cipher_define.h"
+#ifdef __HuaweiLite__
+#include "drv_osal_lib_liteos.h"
+#else
@@ -255109,26 +323625,29 @@ index 0000000..3a3b2f1
+extern int is_hicma_address(phys_addr_t phys, unsigned long size);
+#endif
+
-+/*! \return uuid */
-+#define CHECK_OWNER(local) \
++/* return uuid */
++#define crypto_chk_owner_err_return(local) \
+ do { \
+ crypto_owner owner;\
+ crypto_get_owner(&owner); \
-+ if (0 != memcmp(&owner, local, sizeof(owner))) { \
-+ HI_LOG_ERROR("return user uuid failed\n"); \
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_ILLEGAL_UUID);\
++ if (memcmp(&owner, local, sizeof(owner)) != 0) { \
++ hi_log_error("return user uuid failed\n"); \
++ hi_log_print_err_code(HI_ERR_CIPHER_ILLEGAL_UUID);\
+ return HI_ERR_CIPHER_ILLEGAL_UUID; \
+ } \
+ } while (0)
+
-+/*! \max length module name */
-+#define CRYPTO_MODULE_NAME_LEN (16)
++/* max length module name */
++#define CRYPTO_MODULE_NAME_LEN 16
+
-+/*! \the max cipher hard channel count*/
-+#define CRYPTO_HARD_CHANNEL_MAX (0x08)
++/* the max cipher hard channel count. */
++#define CRYPTO_HARD_CHANNEL_MAX 0x08
+
-+/*! \serure mmz or not, not used */
-+#define SEC_MMZ (0x00)
++/* serure mmz or not, not used */
++#define SEC_MMZ 0x00
++
++/* Cipher cmd param buffer size for ioctrl. */
++#define CRYPTO_CMD_PARAM_SIZE 256
+
+#ifdef DISABLE_DEBUG_INFO
+#define HI_PROC_SUPPORT 0
@@ -255136,437 +323655,458 @@ index 0000000..3a3b2f1
+#define HI_PROC_SUPPORT 1
+#endif
+
-+/*! \struct channel
++/* struct channel
+ * the context of hardware channel.
-+*/
++ */
+typedef struct {
-+ /*the state of instance, open or closed.*/
++ /* the state of instance, open or closed. */
+ hi_u32 open;
+
-+ /*the context of channel, which is defined by specific module*/
++ /* the context of channel, which is defined by specific module. */
+ hi_void *ctx;
+} channel_context;
+
-+/*! \struct of crypto_mem*/
++/* struct of crypto_mem. */
+typedef struct {
-+ compat_addr dma_addr; /*!< dam addr, may be mmz or smmu */
-+ compat_addr mmz_addr; /*!< mmz addr, sometimes the smmu must maped from mmz */
-+ hi_void *dma_virt; /*!< cpu virtual addr maped from dam addr */
-+ hi_u32 dma_size; /*!< dma memory size */
-+ hi_void *user_buf; /*!< buffer of user */
++ compat_addr dma_addr; /* dam addr, may be mmz or smmu */
++ compat_addr mmz_addr; /* mmz addr, sometimes the smmu must maped from mmz */
++ hi_void *dma_virt; /* cpu virtual addr maped from dam addr */
++ hi_u32 dma_size; /* dma memory size */
++ hi_void *user_buf; /* buffer of user */
+} crypto_mem;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
++#define hi_handle_makehandle(mod, private_data, chnid) \
++ (hi_handle)((((mod) & 0xffff) << 16) | ((((private_data) & 0xff) << 8)) | (((chnid) & 0xff)))
++#define hi_handle_get_modid(handle) (((handle) >> 16) & 0xffff)
++#define hi_handle_get_private_data(handle) (((handle) >> 8) & 0xff)
++#define hi_handle_get_chnid(handle) (((handle)) & 0xff)
+
-+/*! \****************************** API Declaration *****************************/
-+/*! \addtogroup osal lib */
-+/** @{ */ /** <!--[osal]*/
++/* cipher drv mode init. */
++hi_s32 cipher_drv_mod_init(hi_void);
+
++/* cipher drv mode deinit. */
++hi_void cipher_drv_mod_exit(hi_void);
++
++/* cipher check addr. */
+hi_s32 cipher_check_mmz_phy_addr(hi_u64 phy_addr, hi_u64 length);
+
-+/**
-+\brief cipher get device.
-+*/
++/* cipher crypto ioctl. */
++hi_s32 crypto_ioctl(hi_u32 cmd, hi_void *argp);
++
++/* cipher crypto entry for module init. */
++hi_s32 crypto_entry(void);
++
++/* cipher crypto entry for module exit. */
++hi_s32 crypto_exit(void);
++
++/* cipher crypto release. */
++hi_s32 crypto_release(void);
++
++/*
++ * \brief cipher get device.
++ */
+hi_void *cipher_get_device(hi_void);
+
-+/**
-+\brief init dma memory.
-+*/
++/*
++ * \brief init dma memory.
++ */
+hi_void crypto_mem_init(hi_void);
+
-+/**
-+\brief deinit dma memory.
-+*/
++/*
++ * \brief deinit dma memory.
++ */
+hi_void crypto_mem_deinit(hi_void);
+
-+/**
-+\brief crypto cpuc flush dcache area.
-+*/
++/*
++ * \brief crypto cpuc flush dcache area.
++ */
+hi_void crypto_cpuc_flush_dcache_area(hi_void *kvir, hi_u32 length);
+
-+/**
-+\brief allocate and map a dma memory.
-+\param[in] mem The struct of crypto_mem.
-+\param[in] size The size of mem.
-+\param[in] name The name of mem.
-+\return HI_SUCCESS if successful, or HI_BASE_ERR_MALLOC_FAILED.
-+*/
++/*
++ * \brief allocate and map a dma memory.
++ * \param[in] mem The struct of crypto_mem.
++ * \param[in] size The size of mem.
++ * \param[in] name The name of mem.
++ * \return HI_SUCCESS if successful, or HI_BASE_ERR_MALLOC_FAILED.
++ */
+hi_s32 crypto_mem_create(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size);
+
-+/**
-+\brief destory and unmap a dma memory.
-+\param[in] mem The struct of crypto_mem.
-+\return 0 if successful, or HI_BASE_ERR_UNMAP_FAILED.
-+*/
++/*
++ * \brief destory and unmap a dma memory.
++ * \param[in] mem The struct of crypto_mem.
++ * \return 0 if successful, or HI_BASE_ERR_UNMAP_FAILED.
++ */
+hi_s32 crypto_mem_destory(crypto_mem *mem);
+
-+/**
-+\brief allocate and map a dma memory.
-+\param[in] mem The struct of crypto_mem.
-+\param[in] size The size of mem.
-+\param[in] name The name of mem.
-+\return HI_SUCCESS if successful, or HI_BASE_ERR_MALLOC_FAILED.
-+*/
++/*
++ * \brief allocate and map a dma memory.
++ * \param[in] mem The struct of crypto_mem.
++ * \param[in] size The size of mem.
++ * \param[in] name The name of mem.
++ * \return HI_SUCCESS if successful, or HI_BASE_ERR_MALLOC_FAILED.
++ */
+hi_s32 hash_mem_create(crypto_mem *mem, hi_u32 type, const char *name, hi_u32 size);
+
-+/**
-+\brief destory and unmap a dma memory.
-+\param[in] mem The struct of crypto_mem.
-+\return 0 if successful, or HI_BASE_ERR_UNMAP_FAILED.
-+*/
++/*
++ * \brief destory and unmap a dma memory.
++ * \param[in] mem The struct of crypto_mem.
++ * \return 0 if successful, or HI_BASE_ERR_UNMAP_FAILED.
++ */
+hi_s32 hash_mem_destory(crypto_mem *mem);
+
-+/**
-+\brief map a dma memory.
-+\param[in] mem The struct of crypto_mem.
-+\param[in] dma_ddr The address of dma mem.
-+\param[in] dma_size The size of dma mem.
-+\return HI_SUCCESS if successful, or HI_BASE_ERR_MAP_FAILED.
-+*/
++/*
++ * \brief map a dma memory.
++ * \param[in] mem The struct of crypto_mem.
++ * \param[in] dma_ddr The address of dma mem.
++ * \param[in] dma_size The size of dma mem.
++ * \return HI_SUCCESS if successful, or HI_BASE_ERR_MAP_FAILED.
++ */
+hi_s32 crypto_mem_open(crypto_mem *mem, compat_addr dma_ddr, hi_u32 dma_size);
+
-+/**
-+\brief unmap a dma memory.
-+\param[in] mem The struct of crypto_mem.
-+\param[in] dma_ddr The address of dma mem.
-+\return HI_SUCCESS if successful, or HI_BASE_ERR_UNMAP_FAILED.
-+*/
++/*
++ * \brief unmap a dma memory.
++ * \param[in] mem The struct of crypto_mem.
++ * \param[in] dma_ddr The address of dma mem.
++ * \return HI_SUCCESS if successful, or HI_BASE_ERR_UNMAP_FAILED.
++ */
+hi_s32 crypto_mem_close(crypto_mem *mem);
+
-+/**
-+\brief attach a cpu buffer with dma memory.
-+\param[in] mem The struct of crypto_mem.
-+\param[in] buffer The user's buffer.
-+\return HI_SUCCESS if successful, or HI_FAILURE.
-+*/
++/*
++ * \brief attach a cpu buffer with dma memory.
++ * \param[in] mem The struct of crypto_mem.
++ * \param[in] buffer The user's buffer.
++ * \return HI_SUCCESS if successful, or HI_FAILURE.
++ */
+hi_s32 crypto_mem_attach(crypto_mem *mem, hi_void *buffer);
+
-+/**
-+\brief flush dma memory,
-+*\param[in] mem The struct of crypto_mem.
-+*\param[in] dma2user 1-data from dma to user, 0-data from user to dma.
-+*\param[in] offset The offset of data to be flush.
-+*\param[in] data_size The size of data to be flush.
-+\return HI_SUCCESS if successful, or HI_FAILURE.
-+*/
++/*
++ * \brief flush dma memory,
++ * \param[in] mem The struct of crypto_mem.
++ * \param[in] dma2user 1-data from dma to user, 0-data from user to dma.
++ * \param[in] offset The offset of data to be flush.
++ * \param[in] data_size The size of data to be flush.
++ * \return HI_SUCCESS if successful, or HI_FAILURE.
++ */
+hi_s32 crypto_mem_flush(crypto_mem *mem, hi_u32 dma2user, hi_u32 offset, hi_u32 data_size);
+
-+/**
-+\brief get dma memory physical address
-+*\param[in] mem The struct of crypto_mem.
-+\return dma_addr if successful, or zero.
-+*/
++/*
++ * \brief get dma memory physical address
++ * \param[in] mem The struct of crypto_mem.
++ * \return dma_addr if successful, or zero.
++ */
+hi_s32 crypto_mem_phys(crypto_mem *mem, compat_addr *dma_addr);
+
-+/**
-+\brief get dma memory virtual address
-+*\param[in] mem The struct of crypto_mem.
-+\return dma_addr if successful, or zero.
-+*/
++/*
++ * \brief get dma memory virtual address
++ * \param[in] mem The struct of crypto_mem.
++ * \return dma_addr if successful, or zero.
++ */
+hi_void *crypto_mem_virt(crypto_mem *mem);
+
-+/**
-+\brief check whether cpu is secure or not.
-+\retval secure cpu, true is returned otherwise false is returned.
-+*/
++/*
++ * \brief check whether cpu is secure or not.
++ * \retval secure cpu, true is returned otherwise false is returned.
++ */
+hi_u32 crypto_is_sec_cpu(hi_void);
+
-+/**
-+\brief map the physics addr to cpu within the base table, contains the base addr and crg addr.
-+\retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.*/
++/*
++ * \brief map the physics addr to cpu within the base table, contains the base addr and crg addr.
++ * \retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 module_addr_map(hi_void);
+
-+/**
-+\brief unmap the physics addr to cpu within the base table, contains the base addr and crg addr.
-+\retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.*/
++/*
++ * \brief unmap the physics addr to cpu within the base table, contains the base addr and crg addr.
++ * \retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 module_addr_unmap(hi_void);
+
-+/**
-+\brief get secure cpu type.
-+*/
++/*
++ * \brief get secure cpu type.
++ */
+hi_u32 module_get_secure(hi_void);
+
-+/**
-+\brief enable a module, open clock and remove reset signal.
-+\param[in] id The module id.
-+\retval NA */
++/*
++ * \brief enable a module, open clock and remove reset signal.
++ * \param[in] id The module id.
++ * \retval NA
++ */
+hi_void module_enable(module_id id);
+
-+/**
-+\brief disable a module, close clock and set reset signal.
-+\param[in] id The module id.
-+\retval NA */
++/*
++ * \brief disable a module, close clock and set reset signal.
++ * \param[in] id The module id.
++ * \retval NA
++ */
+hi_void module_disable(module_id id);
+
-+/**
-+\brief get attribute of module.
-+\param[in] id The module id.
-+\param[out] int_valid enable interrupt or not.
-+\param[out] int_num interrupt number of module.
-+\param[out] name name of module.
-+\retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.*/
++/*
++ * \brief get attribute of module.
++ * \param[in] id The module id.
++ * \param[out] int_valid enable interrupt or not.
++ * \param[out] int_num interrupt number of module.
++ * \param[out] name name of module.
++ * \retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_void module_get_attr(module_id id, hi_u32 *int_valid, hi_u32 *int_num, const char **name);
+
-+/**
-+\brief set irq number.
-+\param[in] id The module id.
-+\param[in] irq irq numbert.
-+\retval NA.*/
++/*
++ * \brief set irq number.
++ * \param[in] id The module id.
++ * \param[in] irq irq numbert.
++ * \retval NA.
++ */
+hi_void module_set_irq(module_id id, hi_u32 irq);
+
-+/**
-+\brief read a register.
-+\param[in] id The module id.
-+\param[in] offset The module id.
-+\retval the value of register*/
++/*
++ * \brief read a register.
++ * \param[in] id The module id.
++ * \param[in] offset The module id.
++ * \retval the value of register
++ */
+hi_u32 module_reg_read(module_id id, hi_u32 offset);
+
-+/**
-+\brief hex to string.
-+\param[in] buf The string buffer.
-+\param[in] val The value of hex.
-+\retval NA */
-+hi_void hex2str(char buf[2], hi_u8 val);
++/*
++ * \brief hex to string.
++ * \param[in] buf The string buffer.
++ * \param[in] val The value of hex.
++ * \retval NA
++ */
++hi_void hex2str(char buf[MUL_VAL_2], hi_u32 buf_len, hi_u8 val);
+
-+/**
-+\brief Implementation that should never be optimized out by the compiler
-+\param[in] buf The string buffer.
-+\param[in] the length of the buf.
-+\retval NA */
-+hi_void crypto_zeroize( hi_void *buf, hi_u32 len );
++/*
++ * \brief Implementation that should never be optimized out by the compiler
++ * \param[in] buf The string buffer.
++ * \param[in] the length of the buf.
++ * \retval NA
++ */
++hi_void crypto_zeroize(hi_void *buf, hi_u32 len);
+
-+/**
-+\brief write a register.
-+\param[in] id The module id.
-+\retval NA */
++/*
++ * \brief write a register.
++ * \param[in] id The module id.
++ * \retval NA
++ */
+hi_void module_reg_write(module_id id, hi_u32 offset, hi_u32 val);
+
+/* cipher module read and write a register */
-+#define SYMC_READ(offset) module_reg_read(CRYPTO_MODULE_ID_SYMC, offset)
-+#define SYMC_WRITE(offset, val) module_reg_write(CRYPTO_MODULE_ID_SYMC, offset, val)
++#define symc_read(offset) module_reg_read(CRYPTO_MODULE_ID_SYMC, offset)
++#define symc_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_SYMC, offset, val)
+
+/* hash module read and write a register */
-+#define HASH_READ(offset) module_reg_read(CRYPTO_MODULE_ID_HASH, offset)
-+#define HASH_WRITE(offset, val) module_reg_write(CRYPTO_MODULE_ID_HASH, offset, val)
++#define hash_read(offset) module_reg_read(CRYPTO_MODULE_ID_HASH, offset)
++#define hash_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_HASH, offset, val)
+
+/* rsa module read and write a register */
-+#define IFEP_RSA_READ(offset) module_reg_read(CRYPTO_MODULE_ID_IFEP_RSA, offset)
-+#define IFEP_RSA_WRITE(offset, val) module_reg_write(CRYPTO_MODULE_ID_IFEP_RSA, offset, val)
++#define ifep_rsa_read(offset) module_reg_read(CRYPTO_MODULE_ID_IFEP_RSA, offset)
++#define ifep_rsa_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_IFEP_RSA, offset, val)
+
+/* trng module read and write a register */
-+#define TRNG_READ(offset) module_reg_read(CRYPTO_MODULE_ID_TRNG, offset)
-+#define TRNG_WRITE(offset, val) module_reg_write(CRYPTO_MODULE_ID_TRNG, offset, val)
++#define trng_read(offset) module_reg_read(CRYPTO_MODULE_ID_TRNG, offset)
++#define trng_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_TRNG, offset, val)
+
+/* sm2 module read and write a register */
-+#define SM2_READ(offset) module_reg_read(CRYPTO_MODULE_ID_SM2, offset)
-+#define SM2_WRITE(offset, val) module_reg_write(CRYPTO_MODULE_ID_SM2, offset, val)
++#define sm2_read(offset) module_reg_read(CRYPTO_MODULE_ID_SM2, offset)
++#define sm2_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_SM2, offset, val)
+
+/* smmu module read and write a register */
-+#define SMMU_READ(offset) module_reg_read(CRYPTO_MODULE_ID_SMMU, offset)
-+#define SMMU_WRITE(offset, val) module_reg_write(CRYPTO_MODULE_ID_SMMU, offset, val)
++#define smmu_read(offset) module_reg_read(CRYPTO_MODULE_ID_SMMU, offset)
++#define smmu_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_SMMU, offset, val)
+
-+/**
-+\brief Initialize the channel list.
-+\param[in] ctx The context of channel.
-+\param[in] num The channel numbers, max is 32.
-+\param[in] ctx_size The size of context.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief Initialize the channel list.
++ * \param[in] ctx The context of channel.
++ * \param[in] num The channel numbers, max is 32.
++ * \param[in] ctx_size The size of context.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 crypto_channel_init(channel_context *ctx, hi_u32 num, hi_u32 ctx_size);
+
-+/**
-+\brief Deinitialize the channel list.
-+\param[in] ctx The context of channel.
-+\param[in] num The channel numbers, max is 32.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief Deinitialize the channel list.
++ * \param[in] ctx The context of channel.
++ * \param[in] num The channel numbers, max is 32.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 crypto_channel_deinit(channel_context *ctx, hi_u32 num);
+
-+/**
-+\brief allocate a channel.
-+\param[in] ctx The context of channel.
-+\param[in] num The channel numbers, max is 32.
-+\param[in] mask Mask whick channel allowed be alloc, max is 32.
-+\param[out] id The id of channel.
-+\retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief allocate a channel.
++ * \param[in] ctx The context of channel.
++ * \param[in] num The channel numbers, max is 32.
++ * \param[in] mask Mask whick channel allowed be alloc, max is 32.
++ * \param[out] id The id of channel.
++ * \retval On success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_s32 crypto_channel_alloc(channel_context *ctx, hi_u32 num, hi_u32 mask, hi_u32 *id);
+
-+/**
-+\brief free a channel.
-+\param[in] ctx The context of channel.
-+\param[in] num The channel numbers, max is 32.
-+\param[in] id The id of channel.
-+\retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
-+*/
++/*
++ * \brief free a channel.
++ * \param[in] ctx The context of channel.
++ * \param[in] num The channel numbers, max is 32.
++ * \param[in] id The id of channel.
++ * \retval on success, HI_SUCCESS is returned. On error, HI_FAILURE is returned.
++ */
+hi_void crypto_channel_free(channel_context *ctx, hi_u32 num, hi_u32 id);
+
-+/**
-+\brief get the private data of hard channel.
-+\param[in] ctx The context of channel.
-+\param[in] num The channel numbers, max is 32.
-+\param[in] id The id of channel.
-+\retval on success, the address of context is returned. On error, NULL is returned..
-+*/
++/*
++ * \brief get the private data of hard channel.
++ * \param[in] ctx The context of channel.
++ * \param[in] num The channel numbers, max is 32.
++ * \param[in] id The id of channel.
++ * \retval on success, the address of context is returned. On error, NULL is returned..
++ */
+hi_void *crypto_channel_get_context(channel_context *ctx, hi_u32 num, hi_u32 id);
+
-+/**
-+\brief get the rang.
-+\retval random number.
-+*/
++/*
++ * \brief get the rang.
++ * \retval random number.
++ */
+hi_u32 get_rand(hi_void);
+
+hi_void smmu_get_table_addr(hi_u64 *rdaddr, hi_u64 *wraddr, hi_u64 *table);
+
-+/**< allow modules to modify, default value is HI_ID_STB, the general module id*/
++/* allow modules to modify, default value is HI_ID_STB, the general module id. */
+#define LOG_D_MODULE_ID HI_ID_CIPHER
-+#define LOG_D_FUNCTRACE (0)
-+#define LOG_D_UNFTRACE (0)
++#define LOG_D_FUNCTRACE 0
++#define LOG_D_UNFTRACE 0
+
-+/**< allow modules to define internel error code, from 0x1000*/
-+#define LOG_ERRCODE_DEF(errid) (hi_u32)(((LOG_D_MODULE_ID) << 16) | (errid))
++/* allow modules to define internel error code, from 0x1000. */
++#define log_errcode_def(errid) (hi_u32)(((LOG_D_MODULE_ID) << 16) | (errid))
+
-+/**< General Error Code, All modules can extend according to the rule */
-+#define HI_LOG_ERR_MEM LOG_ERRCODE_DEF(0x0001) /**< Memory Operation Error */
-+#define HI_LOG_ERR_SEM LOG_ERRCODE_DEF(0x0002) /**< Semaphore Operation Error */
-+#define HI_LOG_ERR_FILE LOG_ERRCODE_DEF(0x0003) /**< File Operation Error */
-+#define HI_LOG_ERR_LOCK LOG_ERRCODE_DEF(0x0004) /**< Lock Operation Error */
-+#define HI_LOG_ERR_PARAM LOG_ERRCODE_DEF(0x0005) /**< Invalid Parameter */
-+#define HI_LOG_ERR_TIMER LOG_ERRCODE_DEF(0x0006) /**< Timer error */
-+#define HI_LOG_ERR_THREAD LOG_ERRCODE_DEF(0x0007) /**< Thread Operation Error */
-+#define HI_LOG_ERR_TIMEOUT LOG_ERRCODE_DEF(0x0008) /**< Time Out Error */
-+#define HI_LOG_ERR_DEVICE LOG_ERRCODE_DEF(0x0009) /**< Device Operation Error */
-+#define HI_LOG_ERR_STATUS LOG_ERRCODE_DEF(0x0010) /**< Status Error */
-+#define HI_LOG_ERR_IOCTRL LOG_ERRCODE_DEF(0x0011) /**< IO Operation Error */
-+#define HI_LOG_ERR_INUSE LOG_ERRCODE_DEF(0x0012) /**< In use */
-+#define HI_LOG_ERR_EXIST LOG_ERRCODE_DEF(0x0013) /**< Have exist */
-+#define HI_LOG_ERR_NOEXIST LOG_ERRCODE_DEF(0x0014) /**< no exist */
-+#define HI_LOG_ERR_UNSUPPORTED LOG_ERRCODE_DEF(0x0015) /**< Unsupported */
-+#define HI_LOG_ERR_UNAVAILABLE LOG_ERRCODE_DEF(0x0016) /**< Unavailable */
-+#define HI_LOG_ERR_UNINITED LOG_ERRCODE_DEF(0x0017) /**< Uninited */
-+#define HI_LOG_ERR_DATABASE LOG_ERRCODE_DEF(0x0018) /**< Database Operation Error */
-+#define HI_LOG_ERR_OVERFLOW LOG_ERRCODE_DEF(0x0019) /**< Overflow */
-+#define HI_LOG_ERR_EXTERNAL LOG_ERRCODE_DEF(0x0020) /**< External Error */
-+#define HI_LOG_ERR_UNKNOWNED LOG_ERRCODE_DEF(0x0021) /**< Unknow Error */
-+#define HI_LOG_ERR_FLASH LOG_ERRCODE_DEF(0x0022) /**< Flash Operation Error*/
-+#define HI_LOG_ERR_ILLEGAL_IMAGE LOG_ERRCODE_DEF(0x0023) /**< Illegal Image */
-+#define HI_LOG_ERR_ILLEGAL_UUID LOG_ERRCODE_DEF(0x0023) /**< Illegal UUID */
-+#define HI_LOG_ERR_NOPERMISSION LOG_ERRCODE_DEF(0x0023) /**< No Permission */
++/* General Error Code, All modules can extend according to the rule */
++#define HI_LOG_ERR_MEM log_errcode_def(0x0001) /* Memory Operation Error */
++#define HI_LOG_ERR_SEM log_errcode_def(0x0002) /* Semaphore Operation Error */
++#define HI_LOG_ERR_FILE log_errcode_def(0x0003) /* File Operation Error */
++#define HI_LOG_ERR_LOCK log_errcode_def(0x0004) /* Lock Operation Error */
++#define HI_LOG_ERR_PARAM log_errcode_def(0x0005) /* Invalid Parameter */
++#define HI_LOG_ERR_TIMER log_errcode_def(0x0006) /* Timer error */
++#define HI_LOG_ERR_THREAD log_errcode_def(0x0007) /* Thread Operation Error */
++#define HI_LOG_ERR_TIMEOUT log_errcode_def(0x0008) /* Time Out Error */
++#define HI_LOG_ERR_DEVICE log_errcode_def(0x0009) /* Device Operation Error */
++#define HI_LOG_ERR_STATUS log_errcode_def(0x0010) /* Status Error */
++#define HI_LOG_ERR_IOCTRL log_errcode_def(0x0011) /* IO Operation Error */
++#define HI_LOG_ERR_INUSE log_errcode_def(0x0012) /* In use */
++#define HI_LOG_ERR_EXIST log_errcode_def(0x0013) /* Have exist */
++#define HI_LOG_ERR_NOEXIST log_errcode_def(0x0014) /* no exist */
++#define HI_LOG_ERR_UNSUPPORTED log_errcode_def(0x0015) /* Unsupported */
++#define HI_LOG_ERR_UNAVAILABLE log_errcode_def(0x0016) /* Unavailable */
++#define HI_LOG_ERR_UNINITED log_errcode_def(0x0017) /* Uninited */
++#define HI_LOG_ERR_DATABASE log_errcode_def(0x0018) /* Database Operation Error */
++#define HI_LOG_ERR_OVERFLOW log_errcode_def(0x0019) /* Overflow */
++#define HI_LOG_ERR_EXTERNAL log_errcode_def(0x0020) /* External Error */
++#define HI_LOG_ERR_UNKNOWNED log_errcode_def(0x0021) /* Unknow Error */
++#define HI_LOG_ERR_FLASH log_errcode_def(0x0022) /* Flash Operation Error. */
++#define HI_LOG_ERR_ILLEGAL_IMAGE log_errcode_def(0x0023) /* Illegal Image */
++#define HI_LOG_ERR_ILLEGAL_UUID log_errcode_def(0x0023) /* Illegal UUID */
++#define HI_LOG_ERR_NOPERMISSION log_errcode_def(0x0023) /* No Permission */
+
-+/**< Function trace log, strictly prohibited to expand */
-+#define HI_LOG_PRINT_FUNC_WAR(Func, ErrCode) HI_LOG_WARN("Call %s return [0x%08X]\n", #Func, (unsigned int)ErrCode);
-+#define HI_LOG_PRINT_FUNC_ERR(Func, ErrCode) HI_LOG_ERROR("Call %s return [0x%08X]\n", #Func, (unsigned int)ErrCode);
-+#define HI_LOG_PRINT_ERR_CODE(ErrCode) HI_LOG_ERROR("Error Code: [0x%08X]\n", (unsigned int)ErrCode);
++/* Function trace log, strictly prohibited to expand */
++#define hi_log_print_func_war(Func, ErrCode) hi_log_warn("Call %s return [0x%08X]\n", #Func, (unsigned int)(ErrCode));
++#define hi_log_print_func_err(Func, ErrCode) hi_log_error("Call %s return [0x%08X]\n", #Func, (unsigned int)(ErrCode));
++#define hi_log_print_err_code(ErrCode) hi_log_error("Error Code: [0x%08X]\n", (unsigned int)(ErrCode));
+
-+/**< Used for displaying more detailed error information */
-+#define HI_ERR_PRINT_S32(val) HI_LOG_ERROR("%s = %d\n", #val, val)
-+#define HI_ERR_PRINT_U32(val) HI_LOG_ERROR("%s = %u\n", #val, val)
-+#define HI_ERR_PRINT_S64(val) HI_LOG_ERROR("%s = %lld\n", #val, val)
-+#define HI_ERR_PRINT_U64(val) HI_LOG_ERROR("%s = %llu\n", #val, val)
-+#define HI_ERR_PRINT_H32(val) HI_LOG_ERROR("%s = 0x%08X\n", #val, val)
-+#define HI_ERR_PRINT_H64(val) HI_LOG_ERROR("%s = 0x%016llX\n", #val, val)
-+#define HI_ERR_PRINT_STR(val) HI_LOG_ERROR("%s = %s\n", #val, val)
-+#define HI_ERR_PRINT_VOID(val) HI_LOG_ERROR("%s = %p\n", #val, val)
-+#define HI_ERR_PRINT_FLOAT(val) HI_LOG_ERROR("%s = %f\n", #val, val)
-+#define HI_ERR_PRINT_INFO(val) HI_LOG_ERROR("<%s>\n", val)
++/* Used for displaying more detailed error information */
++#define hi_err_print_s32(val) hi_log_error("%s = %d\n", #val, (val))
++#define hi_err_print_u32(val) hi_log_error("%s = %u\n", #val, (val))
++#define hi_err_print_s64(val) hi_log_error("%s = %lld\n", #val, (val))
++#define hi_err_print_u64(val) hi_log_error("%s = %llu\n", #val, (val))
++#define hi_err_print_h32(val) hi_log_error("%s = 0x%08X\n", #val, (val))
++#define hi_err_print_h64(val) hi_log_error("%s = 0x%016llX\n", #val, (val))
++#define hi_err_print_str(val) hi_log_error("%s = %s\n", #val, (val))
++#define hi_err_print_void(val) hi_log_error("%s = %p\n", #val, (val))
++#define hi_err_print_float(val) hi_log_error("%s = %f\n", #val, (val))
++#define hi_err_print_info(val) hi_log_error("<%s>\n", (val))
+
-+/**< Used for displaying more detailed warning information */
-+#define HI_LOG_PRINT_S32(val) HI_LOG_WARN("%s = %d\n", #val, val)
-+#define HI_LOG_PRINT_U32(val) HI_LOG_WARN("%s = %u\n", #val, val)
-+#define HI_LOG_PRINT_S64(val) HI_LOG_WARN("%s = %lld\n", #val, val)
-+#define HI_LOG_PRINT_U64(val) HI_LOG_WARN("%s = %llu\n", #val, val)
-+#define HI_LOG_PRINT_H32(val) HI_LOG_WARN("%s = 0x%08X\n", #val, val)
-+#define HI_LOG_PRINT_H64(val) HI_LOG_WARN("%s = 0x%016llX\n", #val, val)
-+#define HI_LOG_PRINT_STR(val) HI_LOG_WARN("%s = %s\n", #val, val)
-+#define HI_LOG_PRINT_VOID(val) HI_LOG_WARN("%s = %p\n", #val, val)
-+#define HI_LOG_PRINT_FLOAT(val) HI_LOG_WARN("%s = %f\n", #val, val)
-+#define HI_LOG_PRINT_INFO(val) HI_LOG_WARN("<%s>\n", val)
++/* Used for displaying more detailed warning information */
++#define hi_log_print_s32(val) hi_log_warn("%s = %d\n", #val, (val))
++#define hi_log_print_u32(val) hi_log_warn("%s = %u\n", #val, (val))
++#define hi_log_print_s64(val) hi_log_warn("%s = %lld\n", #val, (val))
++#define hi_log_print_u64(val) hi_log_warn("%s = %llu\n", #val, (val))
++#define hi_log_print_h32(val) hi_log_warn("%s = 0x%08X\n", #val, (val))
++#define hi_log_print_h64(val) hi_log_warn("%s = 0x%016llX\n", #val, (val))
++#define hi_log_print_str(val) hi_log_warn("%s = %s\n", #val, (val))
++#define hi_log_print_void(val) hi_log_warn("%s = %p\n", #val, (val))
++#define hi_log_print_float(val) hi_log_warn("%s = %f\n", #val, (val))
++#define hi_log_print_info(val) hi_log_warn("<%s>\n", (val))
+
-+/**< Only used for self debug, Can be expanded as needed */
-+#define HI_DBG_PRINT_S32(val) HI_LOG_DEBUG("%s = %d\n", #val, val)
-+#define HI_DBG_PRINT_U32(val) HI_LOG_DEBUG("%s = %u\n", #val, val)
-+#define HI_DBG_PRINT_S64(val) HI_LOG_DEBUG("%s = %lld\n", #val, val)
-+#define HI_DBG_PRINT_U64(val) HI_LOG_DEBUG("%s = %llu\n", #val, val)
-+#define HI_DBG_PRINT_H32(val) HI_LOG_DEBUG("%s = 0x%08X\n", #val, val)
-+#define HI_DBG_PRINT_H64(val) HI_LOG_DEBUG("%s = 0x%016llX\n",#val, val)
-+#define HI_DBG_PRINT_STR(val) HI_LOG_DEBUG("%s = %s\n", #val, val)
-+#define HI_DBG_PRINT_VOID(val) HI_LOG_DEBUG("%s = %p\n", #val, val)
-+#define HI_DBG_PRINT_FLOAT(val) HI_LOG_DEBUG("%s = %f\n", #val, val)
-+#define HI_DBG_PRINT_INFO(val) HI_LOG_DEBUG("<%s>\n", val)
++/* Only used for self debug, Can be expanded as needed */
++#define hi_dbg_print_s32(val) hi_log_debug("%s = %d\n", #val, (val))
++#define hi_dbg_print_u32(val) hi_log_debug("%s = %u\n", #val, (val))
++#define hi_dbg_print_s64(val) hi_log_debug("%s = %lld\n", #val, (val))
++#define hi_dbg_print_u64(val) hi_log_debug("%s = %llu\n", #val, (val))
++#define hi_dbg_print_h32(val) hi_log_debug("%s = 0x%08X\n", #val, (val))
++#define hi_dbg_print_h64(val) hi_log_debug("%s = 0x%016llX\n", #val, (val))
++#define hi_dbg_print_str(val) hi_log_debug("%s = %s\n", #val, (val))
++#define hi_dbg_print_void(val) hi_log_debug("%s = %p\n", #val, (val))
++#define hi_dbg_print_float(val) hi_log_debug("%s = %f\n", #val, (val))
++#define hi_dbg_print_info(val) hi_log_debug("<%s>\n", (val))
+
+#if (LOG_D_FUNCTRACE == 1) || (LOG_D_UNFTRACE == 1)
-+#define HI_UNF_FUNC_ENTER() HI_LOG_DEBUG(" >>>>>>[Enter]\n") /**< Only used for unf interface */
-+#define HI_UNF_FUNC_EXIT() HI_LOG_DEBUG(" <<<<<<[Exit]\n") /**< Only used for unf interface */
++/* Only used for unf interface */
++#define hi_unf_func_enter() hi_log_debug(" >>>>>>[Enter]\n")
++#define hi_unf_func_exit() hi_log_debug(" <<<<<<[Exit]\n")
+#else
-+#define HI_UNF_FUNC_ENTER()
-+#define HI_UNF_FUNC_EXIT()
++#define hi_unf_func_enter()
++#define hi_unf_func_exit()
+#endif
+
+#if LOG_D_FUNCTRACE
-+#define HI_LOG_FUNC_ENTER() HI_LOG_DEBUG(" =====>[Enter]\n") /**< Used for all interface except unf */
-+#define HI_LOG_FUNC_EXIT() HI_LOG_DEBUG(" =====>[Exit]\n") /**< Used for all interface except unf */
++/* Used for all interface except unf */
++#define hi_log_func_enter() hi_log_debug(" =====>[Enter]\n")
++#define hi_log_func_exit() hi_log_debug(" =====>[Exit]\n")
+#else
-+#define HI_LOG_FUNC_ENTER()
-+#define HI_LOG_FUNC_EXIT()
++#define hi_log_func_enter()
++#define hi_log_func_exit()
+#endif
+
-+#define HI_LOG_CHECK(fn_func) \
-+ do \
-+ { \
++#define hi_log_check(fn_func) \
++ do { \
+ hi_s32 _ierr_code = fn_func; \
-+ if (HI_SUCCESS != _ierr_code) \
-+ { \
-+ HI_LOG_PRINT_FUNC_ERR(#fn_func, _ierr_code); \
++ if (_ierr_code != HI_SUCCESS) { \
++ hi_log_print_func_err(#fn_func, _ierr_code); \
+ } \
+ } while (0)
+
+
-+#define HI_LOG_CHECK_PARAM(_val) \
-+ do \
-+ { \
-+ if (_val) \
-+ { \
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_INVALID_PARA);\
++#define hi_log_chk_param_return(_val) \
++ do { \
++ if (_val) { \
++ hi_log_print_err_code(HI_ERR_CIPHER_INVALID_PARA);\
+ return HI_ERR_CIPHER_INVALID_PARA; \
+ } \
+ } while (0)
+
+
-+#define HI_LOG_CHECK_INITED(_init_count) \
-+ do \
-+ { \
-+ if (0 == _init_count) \
-+ { \
-+ HI_LOG_PRINT_ERR_CODE(HI_ERR_CIPHER_NOT_INIT); \
++#define hi_log_chk_init_err_return(_init_count) \
++ do { \
++ if ((_init_count) == 0) { \
++ hi_log_print_err_code(HI_ERR_CIPHER_NOT_INIT); \
+ return HI_ERR_CIPHER_NOT_INIT; \
+ } \
+ } while (0)
+
-+#define HI_LOG_PRINT_BLOCK(data, length)
++#ifdef CIPHER_DEBUG_TEST_SUPPORT
+
-+#endif /* End of #ifndef __DRV_OSAL_LIB_H__*/
++#define PRINT_HEX_BLOCK_LEN 16
++void crypto_print_hex(const hi_char *name, hi_u8 *str, hi_u32 len);
++#define HI_PRINT_HEX(name, str, len) crypto_print_hex((const hi_char *)name, (hi_u8 *)str, (hi_u32)len)
++#else
++#define HI_PRINT_HEX print_string
++#endif
++
++#endif /* End of #ifndef __DRV_OSAL_LIB_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib_linux.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib_linux.h
new file mode 100644
-index 0000000..b60d200
+index 0000000..d74bf90
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib_linux.h
-@@ -0,0 +1,135 @@
+@@ -0,0 +1,125 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for linux cipher drv osal lib.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_LIB_LINUX_H__
@@ -255599,21 +324139,21 @@ index 0000000..b60d200
+
+#define crypto_memset(s, sn, c, n) \
+ do { \
-+ if (sn >= n) { \
++ if ((sn) >= (n)) { \
+ memset(s, c, n); \
-+ }else { \
-+ HI_LOG_ERROR("error, memset overflow\n"); \
-+ }\
-+ }while(0)
++ } else { \
++ hi_log_error("error, memset overflow\n"); \
++ } \
++ } while (0)
+
+#define crypto_memcpy(s, sn, c, n) \
+ do { \
-+ if (sn >= n) { \
++ if ((sn) >= (n)) { \
+ memcpy(s, c, n); \
-+ }else { \
-+ HI_LOG_ERROR("error, memcpy overflow\n"); \
++ } else { \
++ hi_log_error("error, memcpy overflow\n"); \
+ } \
-+ }while(0)
++ } while (0)
+
+#define crypto_ioremap_nocache(addr, size) ioremap_nocache(addr, size)
+#define crypto_iounmap(addr, size) iounmap(addr)
@@ -255624,7 +324164,7 @@ index 0000000..b60d200
+#define crypto_msleep(msec) msleep(msec)
+#define crypto_udelay(msec) udelay(msec)
+
-+#define MAX_MALLOC_BUF_SIZE (0x10000)
++#define MAX_MALLOC_BUF_SIZE 0x10000
+hi_void *crypto_calloc(size_t n, size_t size);
+#define crypto_malloc(x) ((x) > 0 ? kzalloc((x), GFP_KERNEL) : HI_NULL)
+#define crypto_free(x) \
@@ -255632,9 +324172,10 @@ index 0000000..b60d200
+ if ((x) != HI_NULL) { \
+ kfree((x)); \
+ }\
-+ }while(0)
++ } while (0)
+
-+#define MAX_COPY_FROM_USER_SIZE (0x20000000) /* 512M */
++/* 512M */
++#define MAX_COPY_FROM_USER_SIZE 0x20000000
+hi_s32 crypto_copy_from_user(hi_void *to, const hi_void *from, unsigned long n);
+hi_s32 crypto_copy_to_user(hi_void *to, const hi_void *from, unsigned long n);
+hi_u32 get_rand(hi_void);
@@ -255655,10 +324196,10 @@ index 0000000..b60d200
+ wait_event_interruptible_timeout(head, *(con), time)
+
+#define crypto_request_irq(irq, func, name) \
-+ request_irq(irq, func, IRQF_SHARED, name, (hi_void*)name)
++ request_irq(irq, func, IRQF_SHARED, name, (hi_void *)(name))
+
+#define crypto_free_irq(irq, name) \
-+ free_irq(irq, (hi_void*)name)
++ free_irq(irq, (hi_void *)(name))
+
+typedef struct semaphore crypto_mutex;
+#define crypto_mutex_init(x) sema_init(x, 1)
@@ -255667,47 +324208,36 @@ index 0000000..b60d200
+#define crypto_mutex_destroy(x)
+
+#define crypto_owner pid_t
-+#define crypto_get_owner(x) *x = task_tgid_nr(current)
++#define crypto_get_owner(x) *(x) = task_tgid_nr(current)
+
+#define HI_PRINT(fmt...) printk(fmt)
-+#define HI_LOG_FATAL(fmt...) \
++#define hi_log_fatal(fmt...) \
+ do{ \
-+ printk("[FATAL-HI_CIPHER]:%s[%d]:",(hi_u8*)__FUNCTION__,__LINE__); \
++ printk("[FATAL-HI_CIPHER]:%s[%d]:", __FUNCTION__, __LINE__); \
+ printk(fmt); \
-+ }while(0)
-+#define HI_LOG_ERROR(fmt...) \
++ } while (0)
++#define hi_log_error(fmt...) \
+ do{ \
-+ printk("[ERROR-HI_CIPHER]:%s[%d]:",(hi_u8*)__FUNCTION__,__LINE__); \
++ printk("[ERROR-HI_CIPHER]:%s[%d]:", __FUNCTION__, __LINE__); \
+ printk(fmt); \
-+ }while(0)
++ } while (0)
+
-+#define HI_LOG_WARN(fmt...)
-+#define HI_LOG_INFO(fmt...)
-+#define HI_LOG_DEBUG(fmt...)
++#define hi_log_warn(fmt...)
++#define hi_log_info(fmt...)
++#define hi_log_debug(fmt...)
+
-+#endif /* End of #ifndef __DRV_OSAL_LIB_LINUX_H__*/
++#endif /* End of #ifndef __DRV_OSAL_LIB_LINUX_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib_liteos.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib_liteos.h
new file mode 100644
-index 0000000..89af8a6
+index 0000000..03019fd
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include/drv_osal_lib_liteos.h
-@@ -0,0 +1,111 @@
+@@ -0,0 +1,95 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for liteos cipher drv osal lib.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
+#ifndef __DRV_OSAL_LIB_LITEOS_H__
@@ -255719,32 +324249,32 @@ index 0000000..89af8a6
+#include "hi_math.h"
+#include "hi_common.h"
+#include "osal_mmz.h"
++#include <linux/interrupt.h>
+
+/* osal_ioremap_nocache is adpat to ioremap_wc wiith cache in Linux */
+#define crypto_ioremap_nocache(addr, size) osal_ioremap_nocache(addr, size)
+#define crypto_iounmap(addr, size) osal_iounmap(addr)
+
-+#define crypto_memset(s, sn, c, n) { if (sn >= n) memset(s, c, n); else HI_LOG_ERROR("error, memset overflow\n");}
-+#define crypto_memcpy(s, sn, c, n) { if (sn >= n) memcpy(s, c, n); else HI_LOG_ERROR("error, memcpy overflow\n");}
++#define crypto_memset(s, sn, c, n) { if ((sn) >= (n)) memset(s, c, n); else hi_log_error("error, memset overflow\n"); }
++#define crypto_memcpy(s, sn, c, n) { if ((sn) >= (n)) memcpy(s, c, n); else hi_log_error("error, memcpy overflow\n"); }
+
+#define crypto_read(addr) (*(volatile unsigned int *)(addr))
+#define crypto_write(addr, val) (*(volatile unsigned int *)(addr) = (val))
-+#define crypto_read_fifo(id, addr) crypto_read((hi_u8*)(module_get_base_address(id) + addr))
-+#define crypto_write_fifo(id, addr, val) crypto_write((hi_u8*)(module_get_base_address(id)+ addr), val)
++#define crypto_read_fifo(id, addr) crypto_read((hi_u8 *)(module_get_base_address(id) + (addr)))
++#define crypto_write_fifo(id, addr, val) crypto_write((hi_u8 *)(module_get_base_address(id) + (addr)), val)
+
-+hi_s32 crypto_mmz_malloc_nocache(hi_char* mmz_name, hi_char* buf_name,
-+ hi_u64* phy_addr, hi_void** vir_addr,
-+ hi_ulong length);
++hi_s32 crypto_mmz_malloc_nocache(hi_char *mmz_name, hi_char *buf_name, hi_u64 *phy_addr, hi_void **vir_addr,
++ hi_ulong length);
+
-+hi_void crypto_mmz_free(hi_u64 phy_addr, hi_void* vir_addr);
++hi_void crypto_mmz_free(hi_u64 phy_addr, hi_void *vir_addr);
+
+#define crypto_msleep(msec) osal_msleep(msec)
+#define crypto_udelay(msec) osal_udelay(msec)
+
-+#define MAX_MALLOC_BUF_SIZE (0x10000)
++#define MAX_MALLOC_BUF_SIZE 0x10000
+hi_void *crypto_calloc(size_t n, size_t size);
+#define crypto_malloc(x) ((x) > 0 ? osal_kmalloc(x, osal_gfp_atomic) : HI_NULL)
-+#define crypto_free(x) {if ((x) != HI_NULL) osal_kfree(x);}
++#define crypto_free(x) { if ((x) != HI_NULL) osal_kfree(x); }
+
+#define copy_from_user osal_copy_from_user
+#define copy_to_user osal_copy_to_user
@@ -255757,10 +324287,12 @@ index 0000000..89af8a6
+#define crypto_queue_head osal_wait_t
+#define crypto_queue_init(x) osal_wait_init(x)
+#define crypto_queue_wait_up(x) osal_wakeup(x)
-+#define crypto_queue_wait_timeout(head, con, time) osal_wait_event_timeout_interruptible(&head, crypto_waitdone_callback, con, time)
++#define crypto_queue_wait_timeout(head, con, time) \
++ osal_wait_event_timeout_interruptible(&(head), crypto_waitdone_callback, con, time)
+
-+#define crypto_request_irq(irq, func, name) request_irq(irq, (irq_handler_t)func, IRQF_SHARED, name, (hi_void*)name)
-+#define crypto_free_irq(irq, name) osal_free_irq(irq, (hi_void*)name)
++#define crypto_request_irq(irq, func, name) \
++ osal_request_irq(irq, (irq_handler_t)(func), IRQF_SHARED, name, (hi_void *)(name))
++#define crypto_free_irq(irq, name) osal_free_irq(irq, (hi_void *)(name))
+
+#define crypto_mutex osal_mutex_t
+#define crypto_mutex_init(x) osal_mutex_init(x)
@@ -255773,200 +324305,190 @@ index 0000000..89af8a6
+#define flush_cache()
+
+#define crypto_owner hi_u32
-+#define crypto_get_owner(x) *x = 0
++#define crypto_get_owner(x) *(x) = 0
+
+#define PROC_PRINT osal_seq_printf
+
-+#define irqreturn_t int
++#define irqreturn_t hi_s32
+#define IRQ_HANDLED OSAL_IRQ_HANDLED
+#define IRQ_NONE OSAL_IRQ_NONE
+
+#define HI_PRINT(fmt...) osal_printk(fmt)
-+#define HI_LOG_FATAL(fmt...) \
++#define hi_log_fatal(fmt...) \
+ do{ \
-+ osal_printk("[FATAL-HI_CIPHER]:%s[%d]:",(hi_u8*)__FUNCTION__,__LINE__); \
++ osal_printk("[FATAL-HI_CIPHER]:%s[%d]:", __FUNCTION__, __LINE__); \
+ osal_printk(fmt); \
-+ }while(0)
-+#define HI_LOG_ERROR(fmt...) \
++ } while (0)
++#define hi_log_error(fmt...) \
+ do{ \
-+ osal_printk("[ERROR-HI_CIPHER]:%s[%d]:",(hi_u8*)__FUNCTION__,__LINE__); \
++ osal_printk("[ERROR-HI_CIPHER]:%s[%d]:", __FUNCTION__, __LINE__); \
+ osal_printk(fmt); \
-+ }while(0)
-+#define HI_LOG_WARN(fmt...)
-+#define HI_LOG_INFO(fmt...)
-+#define HI_LOG_DEBUG(fmt...)
-+
-+/* auto test for cipher_test */
-+//#define HI_CIPHER_TEST_SUPPORT
-+#ifdef HI_CIPHER_TEST_SUPPORT
-+#define CIPHER_LITEOS_TEST_SUPPORT
-+#endif
-+
-+#endif /* End of #ifndef __DRV_OSAL_LIB_LITEOS_H__*/
++ } while (0)
++#define hi_log_warn(fmt...)
++#define hi_log_info(fmt...)
++#define hi_log_debug(fmt...)
++#endif /* End of #ifndef __DRV_OSAL_LIB_LITEOS_H__ */
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/build.mak b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/build.mak
new file mode 100644
-index 0000000..d69ac5b
+index 0000000..3f7f51c
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/build.mak
-@@ -0,0 +1,7 @@
+@@ -0,0 +1,6 @@
+CIPHER_CFLAGS += -I$(CIPHER_DIR)/drv/cipher_v1.0/test
+CIPHER_CFLAGS += -DKAPI_TEST_SUPPORT
+
-+CIPHER_OBJS += drv/cipher_v1.0/test/kapi_test_main.o
+CIPHER_OBJS += drv/cipher_v1.0/test/kapi_symc_test.o
+
+
diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_symc_test.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_symc_test.c
new file mode 100644
-index 0000000..479a630
+index 0000000..5a693f9
--- /dev/null
+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_symc_test.c
-@@ -0,0 +1,227 @@
+@@ -0,0 +1,243 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : cipher test cases for kapi symc.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
-+#include "drv_osal_lib.h"
++#include "kapi_symc_test.h"
+
-+/* kapi_test end*/
-+static hi_s32 set_cipher_config(hi_handle handle,
-+ hi_bool key_by_ca,
-+ hi_cipher_ca_type ca_type,
-+ hi_cipher_alg alg,
-+ hi_cipher_work_mode mode,
-+ hi_cipher_key_length keyLen,
-+ const hi_u8 key_buf[16],
-+ const hi_u8 iv_buf[16])
++#define TEST_BLOCK_LEN 16
++#define KEY_128BITS_LEN 16
++
++typedef struct {
++ hi_handle handle;
++ hi_bool key_by_ca;
++ hi_cipher_ca_type ca_type;
++ hi_cipher_alg alg;
++ hi_cipher_work_mode mode;
++ hi_cipher_key_len key_len;
++ hi_u8 *key;
++ hi_u32 klen;
++ hi_u8 *iv;
++ hi_u32 ivlen;
++} kapi_test_cipher_cfg;
++
++typedef struct {
++ hi_bool key_by_ca;
++ hi_cipher_work_mode mode;
++ hi_u8 *key;
++ hi_u32 klen;
++ hi_u8 *iv;
++ hi_u32 ivlen;
++ hi_u8 *in;
++ hi_u8 *out;
++ hi_u8 *expect_buf;
++ hi_u32 buf_len;
++} kapi_test_crypt_pack;
++
++
++/* kapi_test end */
++static hi_s32 set_cipher_config(kapi_test_cipher_cfg *set_cfg)
+{
-+ hi_u32 ivlen = AES_IV_SIZE;
-+ hi_s32 ret = HI_SUCCESS;
-+ hi_u32 hard_key = 0;
-+ hi_cipher_ctrl cipher_ctrl;
-+ compat_addr aad;
++ hi_s32 ret;
++ symc_cfg_t cfg;
+
-+ memset(&cipher_ctrl, 0, sizeof(hi_cipher_ctrl));
-+ cipher_ctrl.alg = alg;
-+ cipher_ctrl.work_mode = mode;
-+ cipher_ctrl.bit_width = HI_CIPHER_BIT_WIDTH_128BIT;
-+ cipher_ctrl.key_len = keyLen;
-+ cipher_ctrl.key_by_ca = key_by_ca;
-+ cipher_ctrl.ca_type = ca_type;
-+ if (cipher_ctrl.work_mode != HI_CIPHER_WORK_MODE_ECB) {
-+ cipher_ctrl.change_flags.bit1_iv = 1; //must set for CBC , CFB mode
-+ memcpy(cipher_ctrl.iv, iv_buf, 16);
++ memset(&cfg, 0, sizeof(cfg));
++
++ cfg.id = (hi_u32)set_cfg->handle;
++ cfg.alg = set_cfg->alg;
++ cfg.mode = set_cfg->mode;
++ cfg.width = HI_CIPHER_BIT_WIDTH_128BIT;
++ cfg.klen = set_cfg->key_len;
++ cfg.hard_key = (set_cfg->ca_type & MAX_LOW_8BITS) << BITS_IN_BYTE;
++ cfg.hard_key |= ((hi_u32)set_cfg->key_by_ca & MAX_LOW_8BITS);
++
++ if (cfg.mode != HI_CIPHER_WORK_MODE_ECB) {
++ cfg.iv_usage = 1; /* must set for CBC , CFB mode */
++ memcpy(cfg.iv, set_cfg->iv, set_cfg->ivlen);
+ }
+
-+ memcpy(cipher_ctrl.key, key_buf, 16);
++ memcpy(cfg.fkey, set_cfg->key, set_cfg->klen);
+
-+ if (HI_TRUE == cipher_ctrl.key_by_ca) {
-+ if (HI_CIPHER_KEY_SRC_BUTT <= cipher_ctrl.ca_type) {
-+ pr_err("Invalid ca_type with key_by_ca is HI_TRUE.\n");
-+ return HI_ERR_CIPHER_INVALID_PARA;
-+
-+ }
-+ hard_key = (cipher_ctrl.ca_type & 0xFF) << BITS_IN_BYTE;
-+ hard_key |= 0x01;
++ addr_u64(cfg.aad) = 0x00;
++ if ((cfg.alg == HI_CIPHER_ALG_3DES) || (cfg.alg == HI_CIPHER_ALG_DES)) {
++ cfg.ivlen = DES_IV_SIZE;
++ } else {
++ cfg.ivlen = AES_IV_SIZE;
+ }
+
-+ ADDR_U64(aad) = 0x00;
-+
-+ if ((cipher_ctrl.alg == HI_CIPHER_ALG_3DES)
-+ || (cipher_ctrl.alg == HI_CIPHER_ALG_DES)) {
-+ ivlen = DES_IV_SIZE;
-+ }
-+
-+ ret = kapi_symc_config(handle, hard_key,
-+ cipher_ctrl.alg, cipher_ctrl.work_mode,
-+ cipher_ctrl.bit_width, cipher_ctrl.key_len,
-+ 0, (hi_u8 *)cipher_ctrl.key, HI_NULL,
-+ (hi_u8 *)cipher_ctrl.iv, ivlen,
-+ cipher_ctrl.change_flags.bit1_iv,
-+ aad, 0, 0);
-+ if (HI_SUCCESS != ret) {
-+ return HI_FAILURE;
-+ }
-+
-+ return HI_SUCCESS;
-+}
-+
-+static hi_s32 set_cipher_crypt(hi_handle handle, hi_size_t src_phy_addr,
-+ hi_size_t dest_phy_addr, hi_u32 byte_length,
-+ hi_u32 operation)
-+{
-+ compat_addr input;
-+ compat_addr output;
-+ hi_s32 ret = HI_FAILURE;
-+
-+ ADDR_U64(input) = src_phy_addr;
-+ ADDR_U64(output) = dest_phy_addr;
-+
-+ ret = kapi_symc_crypto_via(handle, input, output, byte_length, operation, 0, 0);
++ ret = kapi_symc_cfg(&cfg);
+ if (ret != HI_SUCCESS) {
++ pr_err("kapi_symc_cfg failed.\n");
+ return ret;
+ }
+
+ return HI_SUCCESS;
+}
+
-+static hi_s32 cipher_aes_decrypt(hi_bool key_by_ca,
-+ hi_cipher_work_mode mode,
-+ const unsigned char *key,
-+ const unsigned char *iv,
-+ const unsigned char *in_buf,
-+ const unsigned char *out_buf,
-+ const unsigned char *expect_buf,
-+ const unsigned int buf_len)
++static hi_s32 set_cipher_crypt(hi_handle handle, hi_phys_addr_t src_phys_addr,
++ hi_phys_addr_t dst_phys_addr, hi_u32 byte_len,
++ hi_u32 operation)
+{
-+ int ret = 0;
++ hi_s32 ret;
++ symc_encrypt_t crypt;
++
++ memset(&crypt, 0, sizeof(symc_encrypt_t));
++ crypt.id = handle;
++ crypt.len = byte_len;
++ addr_u64(crypt.in) = src_phys_addr;
++ addr_u64(crypt.out) = dst_phys_addr;
++ crypt.last = 0;
++ crypt.operation = operation;
++
++ ret = kapi_symc_crypto_via(&crypt, 0);
++ if (ret != HI_SUCCESS) {
++ pr_err("call kapi_symc_crypto_via failed.\n");
++ return ret;
++ }
++
++ return HI_SUCCESS;
++}
++
++static hi_s32 cipher_aes_decrypt(kapi_test_crypt_pack *pcak)
++{
++ int ret;
+ hi_handle test_chnid;
++ kapi_test_cipher_cfg cfg;
+
+ ret = kapi_symc_create(&test_chnid);
-+ if (0 != ret) {
-+ HI_LOG_ERROR("Error: CreateHandle failed!\n");
-+ return HI_FAILURE;
++ if (ret != HI_SUCCESS) {
++ hi_log_error("Error: CreateHandle failed!\n");
++ return ret;
+ }
+
+ /* For decrypt */
-+
-+ ret = set_cipher_config(test_chnid,
-+ key_by_ca,
-+ HI_CIPHER_KEY_SRC_KLAD_1,
-+ HI_CIPHER_ALG_AES,
-+ mode,
-+ HI_CIPHER_KEY_AES_128BIT,
-+ key,
-+ iv);
-+ if (0 != ret) {
-+ HI_LOG_ERROR("Set config info failed.\n");
++ cfg.handle = test_chnid;
++ cfg.key_by_ca = pcak->key_by_ca;
++ cfg.ca_type = HI_CIPHER_KEY_SRC_KLAD_1;
++ cfg.alg = HI_CIPHER_ALG_AES;
++ cfg.mode = pcak->mode;
++ cfg.key_len = HI_CIPHER_KEY_AES_128BIT;
++ cfg.key = pcak->key;
++ cfg.klen = pcak->klen;
++ cfg.iv = pcak->iv;
++ cfg.ivlen = pcak->ivlen;
++ ret = set_cipher_config(&cfg);
++ if (ret != 0) {
++ hi_log_error("Set config info failed.\n");
+ goto __CIPHER_EXIT__;
+ }
+
-+ ret = set_cipher_crypt(test_chnid, (hi_size_t)in_buf, (hi_size_t)out_buf,
-+ buf_len, SYMC_OPERATION_DECRYPT);
-+ if (0 != ret) {
-+ HI_LOG_ERROR("[5]wrong data!\n");
++ ret = set_cipher_crypt(test_chnid, (hi_phys_addr_t)pcak->in, (hi_phys_addr_t)pcak->out,
++ pcak->buf_len, SYMC_OPERATION_DECRYPT);
++ if (ret != 0) {
++ hi_log_error("[5]wrong data!\n");
+ ret = -1;
+ goto __CIPHER_EXIT__;
+ }
+
+ /* compare */
-+ if ( 0 != memcmp(out_buf, expect_buf, 16) ) {
-+ HI_LOG_ERROR("Memcmp failed!\n");
-+ ret = HI_FAILURE;
++ if (memcmp(pcak->out, pcak->expect_buf, pcak->buf_len) != 0) {
++ hi_log_error("Memcmp failed!\n");
++ ret = HI_ERR_CIPHER_ILLEGAL_DATA;
+ goto __CIPHER_EXIT__;
+ }
+
@@ -255977,718 +324499,130 @@ index 0000000..479a630
+}
+
+/* otp key is be written, then excute tihs test */
-+static hi_s32 kapi_test1(void)
++static hi_s32 kapi_test1(hi_void)
+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u8 aes_128_enc_key[16] = {0xc1, 0x1b, 0x54, 0x4a, 0x12, 0x9c, 0x08, 0xa5,
-+ 0xcc, 0xd3, 0xeb, 0xec, 0x7a, 0x3b, 0x00, 0x2b};
-+ hi_u8 aes_128_cbc_IV[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
-+ hi_u8 aes_128_src_buf[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96,
-+ 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A};
-+ hi_u8 aes_128_dst_buf[16] = {0xb0, 0x1b, 0x77, 0x09, 0xe8, 0xdc, 0xf9, 0xef,
-+ 0x37, 0x13, 0x0b, 0x13, 0xda, 0x11, 0xbf, 0x24};
-+ hi_u8 aes_128_src2_buf[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
-+
-+ HI_LOG_ERROR("klad test!\n");
-+ ret = cipher_aes_decrypt(HI_TRUE,
-+ HI_CIPHER_WORK_MODE_CBC,
-+ aes_128_enc_key,
-+ aes_128_cbc_IV,
-+ aes_128_dst_buf,
-+ aes_128_src2_buf,
-+ aes_128_src_buf,
-+ 16);
-+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("klad failed!\n");
-+ return -1;
-+ }
-+
-+ HI_LOG_ERROR("klad success!\n");
-+ return HI_SUCCESS;
-+}
-+
-+static hi_s32 kapi_test2(void)
-+{
-+ hi_s32 ret = HI_FAILURE;
-+ hi_u8 aes_key[16] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6,
-+ 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C};
-+ hi_u8 aes_IV[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++ hi_s32 ret;
++ kapi_test_crypt_pack pack;
++ hi_u8 aes_128_enc_key[TEST_BLOCK_LEN] = {0xc1, 0x1b, 0x54, 0x4a, 0x12, 0x9c, 0x08, 0xa5,
++ 0xcc, 0xd3, 0xeb, 0xec, 0x7a, 0x3b, 0x00, 0x2b};
++ hi_u8 aes_128_cbc_IV[TEST_BLOCK_LEN] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
-+ hi_u8 aes_src[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96,
++ hi_u8 aes_128_src_buf[TEST_BLOCK_LEN] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96,
+ 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A};
-+ hi_u8 aes_dst[16] = {0x76, 0x49, 0xAB, 0xAC, 0x81, 0x19, 0xB2, 0x46,
-+ 0xCE, 0xE9, 0x8E, 0x9B, 0x12, 0xE9, 0x19, 0x7D};
-+ hi_u8 aes_src2[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++ hi_u8 aes_128_dst_buf[TEST_BLOCK_LEN] = {0xb0, 0x1b, 0x77, 0x09, 0xe8, 0xdc, 0xf9, 0xef,
++ 0x37, 0x13, 0x0b, 0x13, 0xda, 0x11, 0xbf, 0x24};
++ hi_u8 aes_128_src2_buf[TEST_BLOCK_LEN] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
+
-+ HI_LOG_ERROR("cbc test!\n");
-+ ret = cipher_aes_decrypt(
-+ HI_FALSE,
-+ HI_CIPHER_WORK_MODE_CBC,
-+ aes_key, aes_IV,
-+ aes_dst, aes_src2,
-+ aes_src,
-+ 16);
++ hi_log_error("klad test!\n");
++ pack.key_by_ca = HI_TRUE;
++ pack.mode = HI_CIPHER_WORK_MODE_CBC;
++ pack.key = aes_128_enc_key;
++ pack.klen = sizeof(aes_128_enc_key);
++ pack.iv = aes_128_cbc_IV;
++ pack.ivlen = sizeof(aes_128_cbc_IV);
++ pack.in = aes_128_dst_buf;
++ pack.out = aes_128_src2_buf;
++ pack.expect_buf = aes_128_src_buf;
++ pack.buf_len = sizeof(aes_128_src_buf);
++ ret = cipher_aes_decrypt(&pack);
+ if (ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("cbc failed!\n");
++ hi_log_error("klad failed!\n");
+ return -1;
+ }
+
-+ HI_LOG_ERROR("cbc success!\n");
++ hi_log_error("klad success!\n");
+ return HI_SUCCESS;
+}
+
-+void kapi_test(void)
++static hi_s32 kapi_test2(hi_void)
+{
-+ kapi_test1();
-+ kapi_test2();
++ hi_s32 ret;
++ kapi_test_crypt_pack pack;
++ hi_u8 aes_key[TEST_BLOCK_LEN] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6,
++ 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C};
++ hi_u8 aes_IV[TEST_BLOCK_LEN] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
++ hi_u8 aes_src[TEST_BLOCK_LEN] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96,
++ 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A};
++ hi_u8 aes_dst[TEST_BLOCK_LEN] = {0x76, 0x49, 0xAB, 0xAC, 0x81, 0x19, 0xB2, 0x46,
++ 0xCE, 0xE9, 0x8E, 0x9B, 0x12, 0xE9, 0x19, 0x7D};
++ hi_u8 aes_src2[TEST_BLOCK_LEN] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
++
++ hi_log_error("cbc test!\n");
++
++ pack.key_by_ca = HI_FALSE;
++ pack.mode = HI_CIPHER_WORK_MODE_CBC;
++ pack.key = aes_key;
++ pack.klen = sizeof(aes_key);
++ pack.iv = aes_IV;
++ pack.ivlen = sizeof(aes_IV);
++ pack.in = aes_dst;
++ pack.out = aes_src2;
++ pack.expect_buf = aes_src;
++ pack.buf_len = sizeof(aes_src);
++ ret = cipher_aes_decrypt(&pack);
++ if (ret != HI_SUCCESS) {
++ hi_log_error("cbc failed!\n");
++ return -1;
++ }
++
++ hi_log_error("cbc success!\n");
++ return HI_SUCCESS;
+}
+
-+/* kapi_test end */
++static hi_void kapi_test(hi_void)
++{
++ hi_s32 ret;
+
-+/** @}*/ /** <!-- ==== Structure Definition end ====*/
-diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_test_main.c b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_test_main.c
++ ret = kapi_test1();
++ if (ret != HI_SUCCESS)
++ hi_log_error("kapi_test1 failed!\n");
++
++ ret = kapi_test2();
++ if (ret != HI_SUCCESS)
++ hi_log_error("kapi_test2 failed!\n");
++}
++
++hi_void kapi_test_main(hi_void)
++{
++ kapi_test();
++}
+diff --git a/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_symc_test.h b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_symc_test.h
new file mode 100644
-index 0000000..a2ba09b
+index 0000000..472681d
--- /dev/null
-+++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_test_main.c
-@@ -0,0 +1,28 @@
-+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
-+ */
-+
-+#include "drv_osal_lib.h"
-+
-+extern hi_void kapi_test(hi_void);
-+
-+hi_s32 kapi_test_main(hi_void)
-+{
-+ kapi_test();
-+
-+ return 0;
-+}
-diff --git a/drivers/crypto/hisi-otp/Kconfig b/drivers/crypto/hisi-otp/Kconfig
-new file mode 100644
-index 0000000..5d67630
---- /dev/null
-+++ b/drivers/crypto/hisi-otp/Kconfig
-@@ -0,0 +1,14 @@
-+#
-+# Copyright (C) Hisilicon 2018
-+# License terms: GNU General Public License (GPL) version 2
-+#
-+
-+menuconfig CRYPTO_DEV_HISI_OTP
-+ bool "Hisi Otp Support"
-+ depends on CRYPTO_HW
-+ default n
-+ help
-+ This driver interfaces with the hardware hisi otp.Supporting
-+ otp writekey and crc.
-+ To compile this driver as a module,
-+ This select support:the module will be called hisi-otp.
-\ No newline at end of file
-diff --git a/drivers/crypto/hisi-otp/Makefile b/drivers/crypto/hisi-otp/Makefile
-new file mode 100644
-index 0000000..c7dbab0
---- /dev/null
-+++ b/drivers/crypto/hisi-otp/Makefile
-@@ -0,0 +1,59 @@
-+
-+cflags-y += -I$(srctree)/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/osal/include
-+cflags-y += -I$(srctree)/drivers/crypto/hisi-cipher/include
-+cflags-y += -I$(srctree)/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/drivers/core/include
-+cflags-y += -I$(srctree)/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/compat/
-+
-+ifeq ($(CONFIG_ARCH_HI3519AV100),y)
-+cflags-y += -DCHIP_TYPE_hi3519av100
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3556AV100),y)
-+cflags-y += -DCHIP_TYPE_hi3556av100
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3559AV100),y)
-+cflags-y += -DCHIP_TYPE_hi3559av100
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516CV500),y)
-+cflags-y += -DCHIP_TYPE_hi3516cv500
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516DV300),y)
-+cflags-y += -DCHIP_TYPE_hi3516dv300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3556V200),y)
-+cflags-y += -DCHIP_TYPE_hi3556v200
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3559V200),y)
-+cflags-y += -DCHIP_TYPE_hi3559v200
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516AV300),y)
-+cflags-y += -DCHIP_TYPE_hi3516av300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516EV200),y)
-+cflags-y += -DCHIP_TYPE_hi3516ev200
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516EV300),y)
-+cflags-y += -DCHIP_TYPE_hi3516ev300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3518EV300),y)
-+cflags-y += -DCHIP_TYPE_hi3518ev300
-+endif
-+
-+ifeq ($(CONFIG_ARCH_HI3516DV200),y)
-+cflags-y += -DCHIP_TYPE_hi3516dv200
-+endif
-+
-+ccflags-y += $(cflags-y)
-+HOSTCFLAGS += $(cflags-y)
-+CPPFLAGS += $(cflags-y)
-+
-+obj-y += hal_otp.o
-diff --git a/drivers/crypto/hisi-otp/hal_otp.c b/drivers/crypto/hisi-otp/hal_otp.c
-new file mode 100644
-index 0000000..ca307cd
---- /dev/null
-+++ b/drivers/crypto/hisi-otp/hal_otp.c
-@@ -0,0 +1,394 @@
++++ b/drivers/crypto/hisi-cipher/src/drv/cipher_v1.0/test/kapi_symc_test.h
+@@ -0,0 +1,27 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
++ * Description : head file for kapi symc test.
++ * Author : Hisilicon multimedia software group
++ * Create : 2017-10-20
+ */
+
-+#include "hi_types.h"
++#ifndef __KAPI_SYMC_TEST_H__
++#define __KAPI_SYMC_TEST_H__
++
+#include "drv_osal_lib.h"
-+#include "hal_otp.h"
+
-+#ifdef OTP_SUPPORT
-+
-+hi_u8 *efuse_otp_reg_base = HI_NULL;
-+
-+/* OTP init */
-+hi_s32 hal_efuse_otp_init(hi_void)
-+{
-+ hi_u32 crg_value = 0;
-+ hi_u32 *sys_addr = HI_NULL;
-+
-+ sys_addr = ioremap_nocache(REG_SYS_OTP_CLK_ADDR_PHY, 0x100);
-+ if (sys_addr == HI_NULL) {
-+ HI_LOG_ERROR("ERROR: sys_addr ioremap with nocache failed!!\n");
-+ return HI_FAILURE;
-+ }
-+
-+ HAL_CIPHER_READ_REG(sys_addr, &crg_value);
-+#if defined(CHIP_TYPE_hi3559av100)
-+ crg_value |= OTP_CRG_RESET_BIT; /* reset */
-+ crg_value |= OTP_CRG_CLOCK_BIT; /* set the bit 0, clock opened */
-+ HAL_CIPHER_WRITE_REG(sys_addr, crg_value);
-+
-+ /* clock select and cancel reset 0x30100*/
-+ crg_value &= (~OTP_CRG_RESET_BIT); /* cancel reset */
++#ifdef __cplusplus
++#if __cplusplus
++extern "C"{
+#endif
-+ crg_value |= OTP_CRG_CLOCK_BIT; /* set the bit 0, clock opened */
-+ HAL_CIPHER_WRITE_REG(sys_addr, crg_value);
++#endif /* __cplusplus */
+
-+ iounmap(sys_addr);
-+ sys_addr = HI_NULL;
++hi_void kapi_test_main(hi_void);
+
-+ efuse_otp_reg_base = ioremap_nocache(OTP_REG_BASE_ADDR_PHY, 0x100);
-+ if (efuse_otp_reg_base == HI_NULL) {
-+ HI_LOG_ERROR("ERROR: osal_ioremap_nocache for OTP failed!!\n");
-+ return HI_FAILURE;
-+ }
-+
-+ return HI_SUCCESS;
-+}
-+EXPORT_SYMBOL(hal_efuse_otp_init);
-+
-+/* CRC16 */
-+static unsigned short calculate_crc16 (const unsigned char* data_array_ptr, unsigned long data_array_length)
-+{
-+ unsigned short crc_value = 0xffff; /* init value 0xffff */
-+ unsigned short polynomial = 0x8005; /* polynomial 0x8005 */
-+ unsigned short data_index = 0;
-+ int l = 0;
-+ unsigned char stored_buf[data_array_length];
-+ hi_u32 *iter_ptr;
-+
-+ if (data_array_ptr == 0) {
-+ return crc_value;
-+ }
-+ if (data_array_length == 0) {
-+ return crc_value;
-+ }
-+
-+ memset(stored_buf, 0, data_array_length);
-+ iter_ptr = (hi_u32 *)stored_buf;
-+ for(data_index = 0; data_index < data_array_length/4; data_index++) {
-+ *iter_ptr++ = ntohl(*((unsigned int *)data_array_ptr + data_index));
-+ }
-+
-+ /* data_array_length=17 */
-+ for (data_index = 0; data_index < data_array_length; data_index++) {
-+ unsigned char byte0 = stored_buf[data_index];
-+ crc_value ^= byte0 * 256;
-+ for (l=0;l<8;l++) {
-+ HI_BOOL flag = ((crc_value & 0x8000)==32768);
-+ crc_value = (crc_value & 0x7FFF)*2;
-+ if (flag == HI_TRUE) {
-+ crc_value ^= polynomial;
-+ }
-+ }
-+ }
-+ return crc_value;
-+};
-+
-+static hi_s32 hal_otp_wait_free(hi_void)
-+{
-+ hi_u32 time_out_cnt = 0;
-+ hi_u32 reg_value = 0;
-+
-+ while(1) {
-+ HAL_CIPHER_READ_REG(OTP_USER_CTRL_STA, ®_value);
-+
-+ /* bit0:otp_op_busy 0:idle, 1:busy */
-+ if((reg_value&0x1)==0) {
-+ return HI_SUCCESS;
-+ }
-+
-+ time_out_cnt++;
-+ if(time_out_cnt >= 10000) {
-+ HI_LOG_ERROR("Otp wait free time out!\n");
-+ break;
-+ }
-+ }
-+ return HI_FAILURE;
-+}
-+
-+static hi_s32 hal_otp_set_mode(otp_user_work_mode otp_mode)
-+{
-+ hi_u32 reg_value = otp_mode;
-+
-+ if(otp_mode >= OTP_UNKOOWN_MODE) {
-+ HI_LOG_ERROR("Mode Unknown!\n");
-+ return HI_FAILURE;
-+ }
-+
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_WORK_MODE, reg_value);
-+ return HI_SUCCESS;
-+}
-+
-+static hi_void hal_otp_op_start(hi_void)
-+{
-+ hi_u32 reg_value = 0x1acce551;
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_OP_START, reg_value);
-+}
-+
-+static hi_s32 hal_otp_wait_op_done(hi_void)
-+{
-+ hi_u32 time_out_cnt = 0;
-+ hi_u32 reg_value = 0;
-+
-+ while(1) {
-+ HAL_CIPHER_READ_REG(OTP_USER_CTRL_STA, ®_value);
-+ if(reg_value & 0x2) {
-+ return HI_SUCCESS;
-+ }
-+
-+ time_out_cnt++;
-+ if(time_out_cnt >= 10000) {
-+ HI_LOG_ERROR("OTP_Wait_OP_done TimeOut!\n");
-+ break;
-+ }
-+ }
-+ return HI_FAILURE;
-+}
-+
-+static hi_u32 hal_get_otp_lock_status_by_type(otp_lock_sta_type lock_status_type)
-+{
-+ hi_u32 reg_addr = 0;
-+ hi_u32 reg_value = 0;
-+
-+ if (lock_status_type == OTP_USER_LOCK_STA0_TYPE) {
-+ reg_addr = (hi_u32)(hi_uintptr_t)OTP_USER_LOCK_STA0;
-+ } else {
-+ reg_addr = (hi_u32)(hi_uintptr_t)OTP_USER_LOCK_STA1;
-+ }
-+
-+ HAL_CIPHER_READ_REG(reg_addr, ®_value);
-+
-+ return reg_value;
-+}
-+
-+static hi_void hal_choose_otp_key(otp_user_key_index which_key)
-+{
-+ hi_u32 reg_value = 0;
-+
-+ reg_value = which_key;
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_INDEX, reg_value);
-+}
-+
-+/* write data to otp */
-+static hi_s32 hal_write_key(otp_user_key_length key_length,
-+ hi_u32 *key_data_buf, hi_u32 use_crc)
-+{
-+ hi_u32 crc16 = 0;
-+
-+ switch(key_length) {
-+ case OTP_KEY_LENGTH_64BIT: {
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA0, key_data_buf[0]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA1, key_data_buf[1]);
-+ if(use_crc==HI_TRUE) {
-+ /* computer user key crc16. */
-+ crc16 = calculate_crc16((hi_u8 *)key_data_buf,8);
-+ crc16&=0xffff;
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA2, crc16);
-+ }
-+ break;
-+ }
-+ case OTP_KEY_LENGTH_128BIT: {
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA0, key_data_buf[0]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA1, key_data_buf[1]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA2, key_data_buf[2]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA3, key_data_buf[3]);
-+ if(use_crc == HI_TRUE) {
-+ /* computer user key crc16. */
-+ crc16 = calculate_crc16((hi_u8*)key_data_buf,16);
-+ crc16&=0xffff;
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA4, crc16);
-+ }
-+ break;
-+ }
-+ case OTP_KEY_LENGTH_256BIT: {
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA0, key_data_buf[0]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA1, key_data_buf[1]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA2, key_data_buf[2]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA3, key_data_buf[3]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA4, key_data_buf[4]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA5, key_data_buf[5]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA6, key_data_buf[6]);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA7, key_data_buf[7]);
-+ if(use_crc == HI_TRUE) {
-+ crc16 = calculate_crc16((hi_u8*)key_data_buf, 32);
-+ crc16&=0xffff;
-+ HI_LOG_ERROR("crc: 0x%x\n",crc16);
-+ (hi_void)HAL_CIPHER_WRITE_REG(OTP_USER_KEY_DATA8, crc16);
-+ }
-+ break;
-+ }
-+ default:
-+ break;
-+ }
-+ return HI_SUCCESS;
-+}
-+
-+static hi_s32 hal_get_otp_lock_status(otp_lock_sta_type lock_status_type,
-+ hi_u32 *status)
-+{
-+ hi_s32 ret = HI_FAILURE;
-+
-+ if(lock_status_type >= OTP_USER_LOCK_UNKNOWN_STA) {
-+ return HI_FAILURE;
-+ }
-+
-+ ret = hal_otp_wait_free();
-+ if(ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("hal otp wait free failed.\n");
-+ return ret;
-+ }
-+
-+ ret = hal_otp_set_mode(OTP_READ_LOCK_STA_MODE);
-+ if(ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("hal otp set mode failed.\n");
-+ return ret;
-+ }
-+
-+ hal_otp_op_start();
-+
-+ ret = hal_otp_wait_op_done();
-+ if(ret != HI_SUCCESS) {
-+ HI_LOG_ERROR("hal otp wait op done failed.\n");
-+ return ret;
-+ }
-+
-+ *status = hal_get_otp_lock_status_by_type(lock_status_type);
-+ return HI_SUCCESS;
-+}
-+
-+static hi_s32 is_locked(otp_user_key_index which_key, hi_u32 lock_sta)
-+{
-+ hi_u32 status = lock_sta;
-+
-+ if(which_key>OTP_USER_KEY3) {
-+ HI_LOG_ERROR("Unsupport key!\n");
-+ return HI_FAILURE;
-+ }
-+
-+ if((status >> (which_key+5))&0x1) {
-+ HI_LOG_ERROR("Key%d was locked!\n", which_key);
-+ return HI_FAILURE;
-+ }
-+ return HI_SUCCESS;
-+}
-+
-+/* set user key to otp */
-+hi_s32 hal_write_key_to_otp(otp_user_key_index which_key,
-+ hi_u32 *key_data_buf, hi_u32 use_crc)
-+{
-+ hi_u32 lock_sta0 = 0;
-+
-+ if(which_key > OTP_USER_KEY3) {
-+ return HI_FAILURE;
-+ }
-+ hal_get_otp_lock_status(OTP_USER_LOCK_STA0_TYPE, &lock_sta0);
-+
-+ if(is_locked(which_key,lock_sta0)) {
-+ return HI_FAILURE;
-+ }
-+
-+ if(HI_FAILURE == hal_otp_wait_free()) {
-+ return HI_FAILURE;
-+ }
-+
-+ hal_choose_otp_key(which_key);
-+
-+ hal_write_key(OTP_KEY_LENGTH_128BIT, key_data_buf, HI_TRUE);
-+
-+ if(hal_otp_set_mode(OTP_WRITE_KEY_ID_OR_PASSWD_MODE)) {
-+ return HI_FAILURE;
-+ }
-+ hal_otp_op_start();
-+
-+ if(HI_FAILURE == hal_otp_wait_op_done()) {
-+ return HI_FAILURE;
-+ }
-+ return HI_SUCCESS;
-+}
-+EXPORT_SYMBOL(hal_write_key_to_otp);
-+
-+/* check otp key crc */
-+static hi_s32 hal_is_crc_check_ok(hi_void)
-+{
-+ hi_u32 reg_value = 0;
-+
-+ HAL_CIPHER_READ_REG(OTP_USER_CTRL_STA, ®_value);
-+ if(reg_value&0x10) {
-+ return HI_SUCCESS;
-+ }
-+ return HI_FAILURE;
-+}
-+
-+hi_s32 hal_key_crc_check_out(otp_user_key_index which_key,hi_u32 *result)
-+{
-+
-+ if(which_key > OTP_USER_KEY3) {
-+ return HI_FAILURE;
-+ }
-+
-+ if(HI_FAILURE == hal_otp_wait_free()) {
-+ return HI_FAILURE;
-+ }
-+
-+ hal_choose_otp_key(which_key);
-+
-+ if(hal_otp_set_mode(OTP_KEY_ID_OR_PASSWD_CRC_MODE)) {
-+ return HI_FAILURE;
-+ }
-+ hal_otp_op_start();
-+
-+ if(HI_FAILURE == hal_otp_wait_op_done()) {
-+ return HI_FAILURE;
-+ }
-+
-+ *result = hal_is_crc_check_ok();
-+ if((*result) != HI_SUCCESS) {
-+ HI_LOG_ERROR("CRC Error!!!!!!!!!!!!\n");
-+ return HI_FAILURE;
-+ }
-+
-+ return HI_SUCCESS;
-+}
-+EXPORT_SYMBOL(hal_key_crc_check_out);
-+
-+/* set otp key to klad */
-+hi_s32 hal_efuse_otp_load_cipher_key(hi_u32 chn_id, hi_u32 opt_id)
-+{
-+ if(opt_id > OTP_USER_KEY3) {
-+ opt_id = OTP_USER_KEY0;
-+ }
-+
-+ if(HI_FAILURE == hal_otp_wait_free()) {
-+ return HI_FAILURE;
-+ }
-+ hal_choose_otp_key(opt_id);
-+
-+ if(hal_otp_set_mode(OTP_LOCK_CIPHER_KEY_MODE)) {
-+ return HI_FAILURE;
-+ }
-+
-+ hal_otp_op_start();
-+
-+ if(HI_FAILURE == hal_otp_wait_op_done()) {
-+ return HI_FAILURE;
-+ }
-+
-+ return HI_SUCCESS;
++#ifdef __cplusplus
++#if __cplusplus
+}
+#endif
++#endif /* __cplusplus */
+
-diff --git a/drivers/crypto/hisi-otp/hal_otp.h b/drivers/crypto/hisi-otp/hal_otp.h
-new file mode 100644
-index 0000000..b5b89e6
---- /dev/null
-+++ b/drivers/crypto/hisi-otp/hal_otp.h
-@@ -0,0 +1,114 @@
-+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
-+ */
-+
-+#ifndef __HAL_OTP_H__
-+#define __HAL_OTP_H__
-+
-+#include "hi_types.h"
-+#include "hal_efuse.h"
-+
-+#define OTP_USER_IF_BASE efuse_otp_reg_base
-+#define OTP_USER_WORK_MODE (OTP_USER_IF_BASE+0x0000)
-+#define OTP_USER_OP_START (OTP_USER_IF_BASE+0x0004)
-+#define OTP_USER_KEY_INDEX (OTP_USER_IF_BASE+0x0008)
-+#define OTP_USER_KEY_DATA0 (OTP_USER_IF_BASE+0x000c)
-+#define OTP_USER_KEY_DATA1 (OTP_USER_IF_BASE+0x0010)
-+#define OTP_USER_KEY_DATA2 (OTP_USER_IF_BASE+0x0014)
-+#define OTP_USER_KEY_DATA3 (OTP_USER_IF_BASE+0x0018)
-+#define OTP_USER_KEY_DATA4 (OTP_USER_IF_BASE+0x001c)
-+#define OTP_USER_KEY_DATA5 (OTP_USER_IF_BASE+0x0020)
-+#define OTP_USER_KEY_DATA6 (OTP_USER_IF_BASE+0x0024)
-+#define OTP_USER_KEY_DATA7 (OTP_USER_IF_BASE+0x0028)
-+#define OTP_USER_KEY_DATA8 (OTP_USER_IF_BASE+0x002c)
-+#define OTP_USER_FLAG_VALUE (OTP_USER_IF_BASE+0x0030)
-+#define OTP_USER_FLAG_INDEX (OTP_USER_IF_BASE+0x0034)
-+#define OTP_USER_REV_ADDR (OTP_USER_IF_BASE+0x0038)
-+#define OTP_USER_REV_WDATA (OTP_USER_IF_BASE+0x003c)
-+#define OTP_USER_REV_RDATA (OTP_USER_IF_BASE+0x0040)
-+#define OTP_USER_LOCK_STA0 (OTP_USER_IF_BASE+0x0044)
-+#define OTP_USER_LOCK_STA1 (OTP_USER_IF_BASE+0x0048)
-+#define OTP_USER_CTRL_STA (OTP_USER_IF_BASE+0x004c)
-+
-+#if defined(CONFIG_TARGET_HI3519AV100) || defined(CONFIG_TARGET_HI3556AV100)
-+#define REG_SYS_OTP_CLK_ADDR_PHY 0x04510194
-+#define OTP_CRG_CLOCK_BIT (0x01 << 7)
-+#elif defined(CONFIG_TARGET_HI3559AV100)
-+#define REG_SYS_OTP_CLK_ADDR_PHY 0x12010194
-+#define OTP_CRG_CLOCK_BIT (0x01 << 7)
-+#define OTP_CRG_RESET_BIT (0x01 << 6)
-+#define OTP_CRG_RESET_SUPPORT
-+#elif (defined(CONFIG_TARGET_HI3516DV300) || \
-+ defined(CONFIG_TARGET_HI3516CV500) || \
-+ defined(CONFIG_TARGET_HI3556V200) || \
-+ defined(CONFIG_TARGET_HI3559V200))
-+#define REG_SYS_OTP_CLK_ADDR_PHY 0x120101BC
-+#define OTP_CRG_CLOCK_BIT (0x01 << 1)
-+#elif (defined(CONFIG_TARGET_HI3516EV200) || \
-+ defined(CONFIG_TARGET_HI3516EV300) || \
-+ defined(CONFIG_TARGET_HI3516DV200) || \
-+ defined(CONFIG_TARGET_HI3518EV300))
-+#define REG_SYS_OTP_CLK_ADDR_PHY 0x120101BC
-+#define OTP_CRG_CLOCK_BIT (0x01 << 1)
-+#endif
-+
-+typedef enum hiotp_lock_sta_type
-+{
-+ OTP_USER_LOCK_STA0_TYPE,
-+ OTP_USER_LOCK_STA1_TYPE,
-+ OTP_USER_LOCK_UNKNOWN_STA,
-+}otp_lock_sta_type;
-+
-+typedef enum hiotp_user_work_mode
-+{
-+ OTP_READ_LOCK_STA_MODE,
-+ OTP_LOCK_CIPHER_KEY_MODE,
-+ OTP_WRITE_KEY_ID_OR_PASSWD_MODE,
-+ OTP_KEY_ID_OR_PASSWD_CRC_MODE,
-+ OTP_SET_FLAG_ENABLE_MODE,
-+ OTP_WRITE_USER_ROOM_MODE,
-+ OTP_Read_USER_ROOM_MODE,
-+ OTP_UNKOOWN_MODE,
-+}otp_user_work_mode;
-+
-+typedef enum hiotp_user_key_index
-+{
-+ OTP_USER_KEY0,
-+ OTP_USER_KEY1,
-+ OTP_USER_KEY2,
-+ OTP_USER_KEY3,
-+ OTP_USER_KEY_JTAG_PW_ID,
-+ OTP_USER_KEY_JTAG_PW,
-+ OTP_USER_KEY_ROOTKEY,
-+ OTP_USER_KEY_UNKNOWN,
-+}otp_user_key_index;
-+
-+typedef enum hiotp_user_key_length
-+{
-+ OTP_KEY_LENGTH_64BIT,
-+ OTP_KEY_LENGTH_128BIT,
-+ OTP_KEY_LENGTH_256BIT,
-+ OTP_KEY_LENGTH_UNSUPPORT,
-+}otp_user_key_length;
-+
-+hi_s32 hal_efuse_otp_init(hi_void);
-+hi_s32 hal_efuse_otp_load_cipher_key(hi_u32 chn_id, hi_u32 opt_id);
-+hi_s32 hal_write_key_to_otp(otp_user_key_index which_key,hi_u32 *key_data_buf,hi_u32 use_crc);
-+hi_s32 hal_key_crc_check_out(otp_user_key_index which_key,hi_u32 *result);
-+//unsigned short CalculateCRC16 (const unsigned char* data_array_ptr, unsigned long data_array_length);
-+
-+#endif
++#endif /* __KAPI_SYMC_TEST_H__ */
+\ No newline at end of file
diff --git a/drivers/dma-buf/_sw_sync.h b/drivers/dma-buf/_sw_sync.h
new file mode 100644
index 0000000..9b5d486
@@ -257175,10 +325109,10 @@ index 0000000..357493a
+#endif /* _LINUX_SW_SYNC_H */
diff --git a/drivers/dma-buf/sync.c b/drivers/dma-buf/sync.c
new file mode 100644
-index 0000000..ac2f640
+index 0000000..aa407fe
--- /dev/null
+++ b/drivers/dma-buf/sync.c
-@@ -0,0 +1,737 @@
+@@ -0,0 +1,738 @@
+/*
+ * drivers/base/sync.c
+ *
@@ -257217,7 +325151,7 @@ index 0000000..ac2f640
+struct sync_timeline *hi_sync_timeline_create(const struct sync_timeline_ops *ops,
+ int size, const char *name)
+{
-+ struct sync_timeline *obj;
++ struct sync_timeline *obj = NULL;
+
+ if (size < sizeof(struct sync_timeline))
+ return NULL;
@@ -257286,7 +325220,8 @@ index 0000000..ac2f640
+{
+ unsigned long flags;
+ LIST_HEAD(signaled_pts);
-+ struct sync_pt *pt, *next;
++ struct sync_pt *pt = NULL;
++ struct sync_pt *next = NULL;
+
+ spin_lock_irqsave(&obj->child_list_lock, flags);
+
@@ -257307,7 +325242,7 @@ index 0000000..ac2f640
+struct sync_pt *hi_sync_pt_create(struct sync_timeline *obj, int size)
+{
+ unsigned long flags;
-+ struct sync_pt *pt;
++ struct sync_pt *pt = NULL;
+
+ if (size < sizeof(struct sync_pt))
+ return NULL;
@@ -258431,7 +326366,7 @@ index b29a9e8..7cc0d72 100644
return sync_file_ioctl_merge(sync_file, arg);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
-index 141aefb..b029725 100644
+index 141aefb..e6b59d6 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -564,6 +564,19 @@ config ZX_DMA
@@ -258440,7 +326375,7 @@ index 141aefb..b029725 100644
+config HIEDMACV310
+ tristate "Hisilicon EDMAC Controller support"
-+ depends on (ARCH_HI3559AV100 || ARCH_HI3519AV100 || ARCH_HI3556AV100 || ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3559V200 || ARCH_HI3556V200 || ARCH_HI3516EV300 || ARCH_HI3516EV200 || ARCH_HI3518EV300 || ARCH_HI3516DV200)
++ depends on (ARCH_HI3559AV100 || ARCH_HI3519AV100 || ARCH_HI3556AV100 || ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3559V200 || ARCH_HI3556V200 || ARCH_HI3516EV300 || ARCH_HI3516EV200 || ARCH_HI3518EV300 || ARCH_HI3516DV200 || ARCH_HI3569V100)
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
@@ -258468,10 +326403,10 @@ index e4dc9ca..b6c8cca 100644
obj-y += xilinx/
diff --git a/drivers/dma/hiedmacv310.c b/drivers/dma/hiedmacv310.c
new file mode 100644
-index 0000000..ced0702
+index 0000000..7f6b4f6
--- /dev/null
+++ b/drivers/dma/hiedmacv310.c
-@@ -0,0 +1,1300 @@
+@@ -0,0 +1,1302 @@
+/*
+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -258520,97 +326455,97 @@ index 0000000..ced0702
+int hiedmacv310_trace_level = HIEDMACV310_TRACE_LEVEL;
+
+typedef struct hiedmac_lli {
-+ u64 next_lli;
-+ u32 reserved[5];
-+ u32 count;
-+ u64 src_addr;
-+ u64 dest_addr;
-+ u32 config;
-+ u32 pad[3];
++ u64 next_lli;
++ u32 reserved[5];
++ u32 count;
++ u64 src_addr;
++ u64 dest_addr;
++ u32 config;
++ u32 pad[3];
+} hiedmac_lli;
+
+struct hiedmac_sg {
-+ dma_addr_t src_addr;
-+ dma_addr_t dst_addr;
-+ size_t len;
-+ struct list_head node;
++ dma_addr_t src_addr;
++ dma_addr_t dst_addr;
++ size_t len;
++ struct list_head node;
+};
+
+struct transfer_desc {
-+ struct virt_dma_desc virt_desc;
++ struct virt_dma_desc virt_desc;
+
-+ dma_addr_t llis_busaddr;
-+ u64 *llis_vaddr;
-+ u32 ccfg;
-+ size_t size;
-+ bool done;
-+ bool cyclic;
++ dma_addr_t llis_busaddr;
++ u64 *llis_vaddr;
++ u32 ccfg;
++ size_t size;
++ bool done;
++ bool cyclic;
+};
+
+enum edmac_dma_chan_state {
-+ HIEDMAC_CHAN_IDLE,
-+ HIEDMAC_CHAN_RUNNING,
-+ HIEDMAC_CHAN_PAUSED,
-+ HIEDMAC_CHAN_WAITING,
++ HIEDMAC_CHAN_IDLE,
++ HIEDMAC_CHAN_RUNNING,
++ HIEDMAC_CHAN_PAUSED,
++ HIEDMAC_CHAN_WAITING,
+};
+
+struct hiedmacv310_dma_chan {
-+ bool slave;
-+ int signal;
-+ int id;
-+ struct virt_dma_chan virt_chan;
-+ struct hiedmacv310_phy_chan *phychan;
-+ struct dma_slave_config cfg;
-+ struct transfer_desc *at;
-+ struct hiedmacv310_driver_data *host;
-+ enum edmac_dma_chan_state state;
++ bool slave;
++ int signal;
++ int id;
++ struct virt_dma_chan virt_chan;
++ struct hiedmacv310_phy_chan *phychan;
++ struct dma_slave_config cfg;
++ struct transfer_desc *at;
++ struct hiedmacv310_driver_data *host;
++ enum edmac_dma_chan_state state;
+};
+
+struct hiedmacv310_phy_chan {
-+ unsigned int id;
-+ void __iomem *base;
-+ spinlock_t lock;
-+ struct hiedmacv310_dma_chan *serving;
++ unsigned int id;
++ void __iomem *base;
++ spinlock_t lock;
++ struct hiedmacv310_dma_chan *serving;
+};
+
+struct hiedmacv310_driver_data {
-+ struct platform_device *dev;
-+ struct dma_device slave;
-+ struct dma_device memcpy;
-+ void __iomem *base;
-+ struct regmap *misc_regmap;
-+ void __iomem *crg_ctrl;
-+ struct hiedmacv310_phy_chan *phy_chans;
-+ struct dma_pool *pool;
-+ unsigned int misc_ctrl_base;
-+ int irq;
-+ unsigned int id;
-+ struct clk *clk;
-+ struct clk *axi_clk;
-+ struct reset_control *rstc;
-+ unsigned int channels;
-+ unsigned int slave_requests;
-+ unsigned int max_transfer_size;
++ struct platform_device *dev;
++ struct dma_device slave;
++ struct dma_device memcpy;
++ void __iomem *base;
++ struct regmap *misc_regmap;
++ void __iomem *crg_ctrl;
++ struct hiedmacv310_phy_chan *phy_chans;
++ struct dma_pool *pool;
++ unsigned int misc_ctrl_base;
++ int irq;
++ unsigned int id;
++ struct clk *clk;
++ struct clk *axi_clk;
++ struct reset_control *rstc;
++ unsigned int channels;
++ unsigned int slave_requests;
++ unsigned int max_transfer_size;
+};
+
+#ifdef DEBUG_HIEDMAC
+void dump_lli(u64 *llis_vaddr, unsigned int num)
+{
+
-+ hiedmac_lli *plli = (hiedmac_lli *)llis_vaddr;
-+ unsigned int i;
++ hiedmac_lli *plli = (hiedmac_lli *)llis_vaddr;
++ unsigned int i;
+
-+ hiedmacv310_trace(3, "lli num = 0%d\n", num);
-+ for (i = 0; i < num; i++) {
-+ printk("lli%d:lli_L: 0x%llx\n", i, plli[i].next_lli & 0xffffffff);
-+ printk("lli%d:lli_H: 0x%llx\n", i, plli[i].next_lli >> 32 & 0xffffffff);
-+ printk("lli%d:count: 0x%llx\n", i, plli[i].count);
-+ printk("lli%d:src_addr_L: 0x%llx\n", i, plli[i].src_addr & 0xffffffff);
-+ printk("lli%d:src_addr_H: 0x%llx\n", i, plli[i].src_addr >> 32 & 0xffffffff);
-+ printk("lli%d:dst_addr_L: 0x%llx\n", i, plli[i].dest_addr & 0xffffffff);
-+ printk("lli%d:dst_addr_H: 0x%llx\n", i, plli[i].dest_addr >> 32 & 0xffffffff);
-+ printk("lli%d:CONFIG: 0x%llx\n", i, plli[i].config);
-+ }
++ hiedmacv310_trace(3, "lli num = 0%d\n", num);
++ for (i = 0; i < num; i++) {
++ printk("lli%d:lli_L: 0x%llx\n", i, plli[i].next_lli & 0xffffffff);
++ printk("lli%d:lli_H: 0x%llx\n", i, plli[i].next_lli >> 32 & 0xffffffff);
++ printk("lli%d:count: 0x%llx\n", i, plli[i].count);
++ printk("lli%d:src_addr_L: 0x%llx\n", i, plli[i].src_addr & 0xffffffff);
++ printk("lli%d:src_addr_H: 0x%llx\n", i, plli[i].src_addr >> 32 & 0xffffffff);
++ printk("lli%d:dst_addr_L: 0x%llx\n", i, plli[i].dest_addr & 0xffffffff);
++ printk("lli%d:dst_addr_H: 0x%llx\n", i, plli[i].dest_addr >> 32 & 0xffffffff);
++ printk("lli%d:CONFIG: 0x%llx\n", i, plli[i].config);
++ }
+}
+
+#else
@@ -258621,957 +326556,959 @@ index 0000000..ced0702
+
+static inline struct hiedmacv310_dma_chan *to_edamc_chan(struct dma_chan *chan)
+{
-+ return container_of(chan, struct hiedmacv310_dma_chan, virt_chan.chan);
++ return container_of(chan, struct hiedmacv310_dma_chan, virt_chan.chan);
+}
+
+static inline struct transfer_desc *to_edmac_transfer_desc(struct dma_async_tx_descriptor *tx)
+{
-+ return container_of(tx, struct transfer_desc, virt_desc.tx);
++ return container_of(tx, struct transfer_desc, virt_desc.tx);
+}
+
+static struct dma_chan *hiedmac_find_chan_id(struct hiedmacv310_driver_data *hiedmac,
-+ int request_num)
++ int request_num)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = NULL;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = NULL;
+
-+ list_for_each_entry(edmac_dma_chan, &hiedmac->slave.channels, virt_chan.chan.device_node) {
-+ if (edmac_dma_chan->id == request_num) {
-+ return &edmac_dma_chan->virt_chan.chan;
-+ }
-+ }
-+ return NULL;
++ list_for_each_entry(edmac_dma_chan, &hiedmac->slave.channels, virt_chan.chan.device_node) {
++ if (edmac_dma_chan->id == request_num) {
++ return &edmac_dma_chan->virt_chan.chan;
++ }
++ }
++ return NULL;
+}
+
+static struct dma_chan *hiedma_of_xlate(struct of_phandle_args *dma_spec,
-+ struct of_dma *ofdma)
++ struct of_dma *ofdma)
+{
-+ struct hiedmacv310_driver_data *hiedmac = ofdma->of_dma_data;
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = NULL;
-+ struct dma_chan *dma_chan;
-+ struct regmap *misc = NULL;
-+ unsigned int signal = 0, request_num = 0;
-+ unsigned int reg = 0, offset = 0;
++ struct hiedmacv310_driver_data *hiedmac = ofdma->of_dma_data;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = NULL;
++ struct dma_chan *dma_chan = NULL;
++ struct regmap *misc = NULL;
++ unsigned int signal = 0, request_num = 0;
++ unsigned int reg = 0, offset = 0;
+
-+ if (!hiedmac) {
-+ return NULL;
-+ }
++ if (!hiedmac) {
++ return NULL;
++ }
+
-+ misc = hiedmac->misc_regmap;
++ misc = hiedmac->misc_regmap;
+
-+ if (dma_spec->args_count != 2) {
-+ hiedmacv310_error("args count not true!\n");
-+ return NULL;
-+ }
++ if (dma_spec->args_count != 2) {
++ hiedmacv310_error("args count not true!\n");
++ return NULL;
++ }
+
-+ request_num = dma_spec->args[0];
-+ signal = dma_spec->args[1];
++ request_num = dma_spec->args[0];
++ signal = dma_spec->args[1];
+
-+ hiedmacv310_trace(3, "host->id = %d,signal = %d, request_num = %d\n", hiedmac->id, signal, request_num);
++ hiedmacv310_trace(3, "host->id = %d,signal = %d, request_num = %d\n", hiedmac->id, signal, request_num);
+
-+ if (misc != NULL) {
-+ #ifdef CONFIG_ACCESS_M7_DEV
-+ offset = hiedmac->misc_ctrl_base;
-+ reg = 0xc0;
-+ regmap_write(misc, offset, reg);
-+ #else
-+ offset = hiedmac->misc_ctrl_base + (request_num & (~0x3));
-+ regmap_read(misc, offset, ®);
-+ reg &= ~(0x3f << ((request_num & 0x3) << 3));
-+ reg |= signal << ((request_num & 0x3) << 3);
-+ regmap_write(misc, offset, reg);
-+ #endif
-+ }
++ if (misc != NULL) {
++#ifdef CONFIG_ACCESS_M7_DEV
++ offset = hiedmac->misc_ctrl_base;
++ reg = 0xc0;
++ regmap_write(misc, offset, reg);
++#else
++ offset = hiedmac->misc_ctrl_base + (request_num & (~0x3));
++ regmap_read(misc, offset, ®);
++ reg &= ~(0x3f << ((request_num & 0x3) << 3));
++ reg |= signal << ((request_num & 0x3) << 3);
++ regmap_write(misc, offset, reg);
++#endif
++ }
+
-+ hiedmacv310_trace(3, "offset = 0x%x, reg = 0x%x\n", offset, reg);
++ hiedmacv310_trace(3, "offset = 0x%x, reg = 0x%x\n", offset, reg);
+
-+ dma_chan = hiedmac_find_chan_id(hiedmac, request_num);
-+ if (!dma_chan) {
-+ hiedmacv310_error("DMA slave channel is not found!\n");
-+ return NULL;
-+ }
++ dma_chan = hiedmac_find_chan_id(hiedmac, request_num);
++ if (!dma_chan) {
++ hiedmacv310_error("DMA slave channel is not found!\n");
++ return NULL;
++ }
+
-+ edmac_dma_chan = to_edamc_chan(dma_chan);
-+ edmac_dma_chan->signal = request_num;
++ edmac_dma_chan = to_edamc_chan(dma_chan);
++ edmac_dma_chan->signal = request_num;
+
-+ return dma_get_slave_channel(dma_chan);
++ return dma_get_slave_channel(dma_chan);
+}
+
+
+static int get_of_probe(struct hiedmacv310_driver_data *hiedmac)
+{
-+ struct resource *res;
-+ struct platform_device *platdev = hiedmac->dev;
-+ struct device_node *np = platdev->dev.of_node;
-+ int ret;
++ struct resource *res = NULL;
++ struct platform_device *platdev = hiedmac->dev;
++ struct device_node *np = platdev->dev.of_node;
++ int ret;
+
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "devid", &(hiedmac->id));
-+ if (ret) {
-+ hiedmacv310_error("get hiedmac id fail\n");
-+ return -ENODEV;
-+ }
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "devid", &(hiedmac->id));
++ if (ret) {
++ hiedmacv310_error("get hiedmac id fail\n");
++ return -ENODEV;
++ }
+
-+ hiedmac->clk = devm_clk_get(&(platdev->dev), "apb_pclk");
-+ if (IS_ERR(hiedmac->clk)) {
-+ return PTR_ERR(hiedmac->clk);
-+ }
++ hiedmac->clk = devm_clk_get(&(platdev->dev), "apb_pclk");
++ if (IS_ERR(hiedmac->clk)) {
++ return PTR_ERR(hiedmac->clk);
++ }
+
-+ hiedmac->axi_clk = devm_clk_get(&(platdev->dev), "axi_aclk");
-+ if (IS_ERR(hiedmac->axi_clk)) {
-+ return PTR_ERR(hiedmac->axi_clk);
-+ }
++ hiedmac->axi_clk = devm_clk_get(&(platdev->dev), "axi_aclk");
++ if (IS_ERR(hiedmac->axi_clk)) {
++ return PTR_ERR(hiedmac->axi_clk);
++ }
+
-+ hiedmac->rstc = devm_reset_control_get(&(platdev->dev), "dma-reset");
-+ if (IS_ERR(hiedmac->rstc)) {
-+ return PTR_ERR(hiedmac->rstc);
-+ }
++ hiedmac->rstc = devm_reset_control_get(&(platdev->dev), "dma-reset");
++ if (IS_ERR(hiedmac->rstc)) {
++ return PTR_ERR(hiedmac->rstc);
++ }
+
-+ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ hiedmacv310_error("no reg resource\n");
-+ return -ENODEV;
-+ }
++ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ hiedmacv310_error("no reg resource\n");
++ return -ENODEV;
++ }
+
-+ hiedmac->base = devm_ioremap_resource(&(platdev->dev), res);
-+ if (IS_ERR(hiedmac->base)) {
-+ return PTR_ERR(hiedmac->base);
-+ }
++ hiedmac->base = devm_ioremap_resource(&(platdev->dev), res);
++ if (IS_ERR(hiedmac->base)) {
++ return PTR_ERR(hiedmac->base);
++ }
+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
-+ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
+ defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || \
-+ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
-+ hiedmac->misc_regmap = 0;
-+ np = np ;
++ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
++ hiedmac->misc_regmap = 0;
++ (void)np;
+#else
-+ hiedmac->misc_regmap = syscon_regmap_lookup_by_phandle(np, "misc_regmap");
-+ if (IS_ERR(hiedmac->misc_regmap)) {
-+ return PTR_ERR(hiedmac->misc_regmap);
-+ }
++ hiedmac->misc_regmap = syscon_regmap_lookup_by_phandle(np, "misc_regmap");
++ if (IS_ERR(hiedmac->misc_regmap)) {
++ return PTR_ERR(hiedmac->misc_regmap);
++ }
+
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "misc_ctrl_base", &(hiedmac->misc_ctrl_base));
-+ if (ret) {
-+ hiedmacv310_error( "get dma-misc_ctrl_base fail\n");
-+ return -ENODEV;
-+ }
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "misc_ctrl_base", &(hiedmac->misc_ctrl_base));
++ if (ret) {
++ hiedmacv310_error( "get dma-misc_ctrl_base fail\n");
++ return -ENODEV;
++ }
+#endif
-+ hiedmac->irq = platform_get_irq(platdev, 0);
-+ if (unlikely(hiedmac->irq < 0)) {
-+ return -ENODEV;
-+ }
++ hiedmac->irq = platform_get_irq(platdev, 0);
++ if (unlikely(hiedmac->irq < 0)) {
++ return -ENODEV;
++ }
+
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "dma-channels", &(hiedmac->channels));
-+ if (ret) {
-+ hiedmacv310_error( "get dma-channels fail\n");
-+ return -ENODEV;
-+ }
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "dma-requests", &(hiedmac->slave_requests));
-+ if (ret) {
-+ hiedmacv310_error( "get dma-requests fail\n");
-+ return -ENODEV;
-+ }
-+ hiedmacv310_trace(2, "dma-channels = %d, dma-requests = %d\n",
-+ hiedmac->channels, hiedmac->slave_requests);
-+ return of_dma_controller_register(platdev->dev.of_node, hiedma_of_xlate, hiedmac);
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "dma-channels", &(hiedmac->channels));
++ if (ret) {
++ hiedmacv310_error( "get dma-channels fail\n");
++ return -ENODEV;
++ }
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "dma-requests", &(hiedmac->slave_requests));
++ if (ret) {
++ hiedmacv310_error( "get dma-requests fail\n");
++ return -ENODEV;
++ }
++ hiedmacv310_trace(2, "dma-channels = %d, dma-requests = %d\n",
++ hiedmac->channels, hiedmac->slave_requests);
++ return of_dma_controller_register(platdev->dev.of_node, hiedma_of_xlate, hiedmac);
+}
+
+static void hiedmac_free_chan_resources(struct dma_chan *chan)
+{
-+ vchan_free_chan_resources(to_virt_chan(chan));
++ vchan_free_chan_resources(to_virt_chan(chan));
+}
+
+static enum dma_status hiedmac_tx_status(struct dma_chan *chan,
-+ dma_cookie_t cookie, struct dma_tx_state *txstate)
++ dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
-+ enum dma_status ret = DMA_COMPLETE;
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct virt_dma_desc *vd;
-+ struct transfer_desc *tsf_desc;
-+ unsigned long flags;
-+ size_t bytes = 0;
-+ u64 curr_lli = 0, curr_residue_bytes = 0, temp = 0;
-+ hiedmac_lli *plli;
-+ unsigned int i = 0, index = 0;
++ enum dma_status ret = DMA_COMPLETE;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct virt_dma_desc *vd = NULL;
++ struct transfer_desc *tsf_desc = NULL;
++ unsigned long flags;
++ size_t bytes = 0;
++ u64 curr_lli = 0, curr_residue_bytes = 0, temp = 0;
++ hiedmac_lli *plli = NULL;
++ unsigned int i = 0, index = 0;
+
-+ ret = dma_cookie_status(chan, cookie, txstate);
-+ if (ret == DMA_COMPLETE) {
-+ return ret;
-+ }
++ ret = dma_cookie_status(chan, cookie, txstate);
++ if (ret == DMA_COMPLETE) {
++ return ret;
++ }
+
-+ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
-+ vd = vchan_find_desc(&edmac_dma_chan->virt_chan, cookie);
-+ if (vd) {
-+ /* no been trasfer */
-+ tsf_desc = to_edmac_transfer_desc(&vd->tx);
-+ bytes = tsf_desc->size;
-+ } else {
-+ /* trasfering */
-+ tsf_desc = edmac_dma_chan->at;
++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
++ vd = vchan_find_desc(&edmac_dma_chan->virt_chan, cookie);
++ if (vd) {
++ /* no been trasfer */
++ tsf_desc = to_edmac_transfer_desc(&vd->tx);
++ bytes = tsf_desc->size;
++ } else {
++ /* trasfering */
++ tsf_desc = edmac_dma_chan->at;
+
-+ if (!phychan || !tsf_desc) {
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
-+ goto out;
-+ }
-+ curr_lli = (hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_LLI_L(phychan->id)) & (~(HIEDMAC_LLI_ALIGN - 1)));
-+ curr_lli |= ((u64)(hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_LLI_H(phychan->id)) & 0xffffffff) << 32);
-+ curr_residue_bytes = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CURR_CNT0(phychan->id));
-+ if (curr_lli == 0) {
-+ /* It means non-lli mode */
-+ bytes = curr_residue_bytes;
-+ } else {
-+ /* It means lli mode */
-+ index = (curr_lli - tsf_desc->llis_busaddr) / sizeof(hiedmac_lli) - 1;
-+ plli = (hiedmac_lli *)(tsf_desc->llis_vaddr);
-+ for (i = 0; i < index; i++) {
-+ temp += plli[i].count;
-+ }
-+ temp += plli[i].count - curr_residue_bytes;
-+ bytes = tsf_desc->size - temp;
-+ }
-+ }
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ if (!phychan || !tsf_desc) {
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ goto out;
++ }
++ curr_lli = (hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_LLI_L(phychan->id)) & (~(HIEDMAC_LLI_ALIGN - 1)));
++ curr_lli |= ((u64)(hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_LLI_H(phychan->id)) & 0xffffffff) << 32);
++ curr_residue_bytes = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CURR_CNT0(phychan->id));
++ if (curr_lli == 0) {
++ /* It means non-lli mode */
++ bytes = curr_residue_bytes;
++ } else {
++ /* It means lli mode */
++ index = (curr_lli - tsf_desc->llis_busaddr) / sizeof(hiedmac_lli) - 1;
++ plli = (hiedmac_lli *)(tsf_desc->llis_vaddr);
++ for (i = 0; i < index; i++) {
++ temp += plli[i].count;
++ }
++ temp += plli[i].count - curr_residue_bytes;
++ bytes = tsf_desc->size - temp;
++ }
++ }
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
+
-+ dma_set_residue(txstate, bytes);
++ dma_set_residue(txstate, bytes);
+
-+ if (edmac_dma_chan->state == HIEDMAC_CHAN_PAUSED && ret == DMA_IN_PROGRESS) {
-+ ret = DMA_PAUSED;
-+ return ret;
-+ }
++ if (edmac_dma_chan->state == HIEDMAC_CHAN_PAUSED && ret == DMA_IN_PROGRESS) {
++ ret = DMA_PAUSED;
++ return ret;
++ }
+
+out:
-+ return ret;
++ return ret;
+}
+
+static struct hiedmacv310_phy_chan *hiedmac_get_phy_channel(
-+ struct hiedmacv310_driver_data *hiedmac,
-+ struct hiedmacv310_dma_chan *edmac_dma_chan)
++ struct hiedmacv310_driver_data *hiedmac,
++ struct hiedmacv310_dma_chan *edmac_dma_chan)
+{
-+ struct hiedmacv310_phy_chan *ch = NULL;
-+ unsigned long flags;
-+ int i;
++ struct hiedmacv310_phy_chan *ch = NULL;
++ unsigned long flags;
++ int i;
+
-+ for (i = 0; i < hiedmac->channels; i++) {
-+ ch = &hiedmac->phy_chans[i];
++ for (i = 0; i < hiedmac->channels; i++) {
++ ch = &hiedmac->phy_chans[i];
+
-+ spin_lock_irqsave(&ch->lock, flags);
++ spin_lock_irqsave(&ch->lock, flags);
+
-+ if (!ch->serving) {
-+ ch->serving = edmac_dma_chan;
-+ spin_unlock_irqrestore(&ch->lock, flags);
-+ break;
-+ }
-+ spin_unlock_irqrestore(&ch->lock, flags);
-+ }
++ if (!ch->serving) {
++ ch->serving = edmac_dma_chan;
++ spin_unlock_irqrestore(&ch->lock, flags);
++ break;
++ }
++ spin_unlock_irqrestore(&ch->lock, flags);
++ }
+
-+ if (i == hiedmac->channels) {
-+ return NULL;
-+ }
++ if (i == hiedmac->channels) {
++ return NULL;
++ }
+
-+ return ch;
++ return ch;
+}
+
+static void hiedmac_write_lli(struct hiedmacv310_driver_data *hiedmac,
-+ struct hiedmacv310_phy_chan *phychan,
-+ struct transfer_desc *tsf_desc)
++ struct hiedmacv310_phy_chan *phychan,
++ struct transfer_desc *tsf_desc)
+{
+
-+ hiedmac_lli *plli = (hiedmac_lli *)tsf_desc->llis_vaddr;
++ hiedmac_lli *plli = (hiedmac_lli *)tsf_desc->llis_vaddr;
+
-+ if (plli->next_lli != 0x0) {
-+ hiedmacv310_writel((plli->next_lli & 0xffffffff) | HIEDMAC_LLI_ENABLE, hiedmac->base + HIEDMAC_Cx_LLI_L(phychan->id));
-+ } else {
-+ hiedmacv310_writel((plli->next_lli & 0xffffffff), hiedmac->base + HIEDMAC_Cx_LLI_L(phychan->id));
-+ }
++ if (plli->next_lli != 0x0) {
++ hiedmacv310_writel((plli->next_lli & 0xffffffff) | HIEDMAC_LLI_ENABLE, hiedmac->base + HIEDMAC_Cx_LLI_L(phychan->id));
++ } else {
++ hiedmacv310_writel((plli->next_lli & 0xffffffff), hiedmac->base + HIEDMAC_Cx_LLI_L(phychan->id));
++ }
+
-+ hiedmacv310_writel(((plli->next_lli >> 32) & 0xffffffff), hiedmac->base + HIEDMAC_Cx_LLI_H(phychan->id));
-+ hiedmacv310_writel(plli->count, hiedmac->base + HIEDMAC_Cx_CNT0(phychan->id));
-+ hiedmacv310_writel(plli->src_addr & 0xffffffff, hiedmac->base + HIEDMAC_Cx_SRC_ADDR_L(phychan->id));
-+ hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff, hiedmac->base + HIEDMAC_Cx_SRC_ADDR_H(phychan->id));
-+ hiedmacv310_writel(plli->dest_addr & 0xffffffff, hiedmac->base + HIEDMAC_Cx_DEST_ADDR_L(phychan->id));
-+ hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff, hiedmac->base + HIEDMAC_Cx_DEST_ADDR_H(phychan->id));
-+ hiedmacv310_writel(plli->config, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ hiedmacv310_writel(((plli->next_lli >> 32) & 0xffffffff), hiedmac->base + HIEDMAC_Cx_LLI_H(phychan->id));
++ hiedmacv310_writel(plli->count, hiedmac->base + HIEDMAC_Cx_CNT0(phychan->id));
++ hiedmacv310_writel(plli->src_addr & 0xffffffff, hiedmac->base + HIEDMAC_Cx_SRC_ADDR_L(phychan->id));
++ hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff, hiedmac->base + HIEDMAC_Cx_SRC_ADDR_H(phychan->id));
++ hiedmacv310_writel(plli->dest_addr & 0xffffffff, hiedmac->base + HIEDMAC_Cx_DEST_ADDR_L(phychan->id));
++ hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff, hiedmac->base + HIEDMAC_Cx_DEST_ADDR_H(phychan->id));
++ hiedmacv310_writel(plli->config, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
+}
+
+static void hiedmac_start_next_txd(struct hiedmacv310_dma_chan *edmac_dma_chan)
+{
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
-+ struct virt_dma_desc *vd = vchan_next_desc(&edmac_dma_chan->virt_chan);
-+ struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx);
-+ unsigned int val = 0;
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
++ struct virt_dma_desc *vd = vchan_next_desc(&edmac_dma_chan->virt_chan);
++ struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx);
++ unsigned int val = 0;
+
-+ list_del(&tsf_desc->virt_desc.node);
++ list_del(&tsf_desc->virt_desc.node);
+
-+ edmac_dma_chan->at = tsf_desc;
++ edmac_dma_chan->at = tsf_desc;
+
-+ hiedmac_write_lli(hiedmac, phychan, tsf_desc);
++ hiedmac_write_lli(hiedmac, phychan, tsf_desc);
+
-+ val = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ val = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
+
-+ hiedmacv310_trace(2, " HIEDMAC_Cx_CONFIG = 0x%x\n", val);
-+ hiedmacv310_writel(val | HIEDMAC_CxCONFIG_LLI_START, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ hiedmacv310_trace(2, " HIEDMAC_Cx_CONFIG = 0x%x\n", val);
++ hiedmacv310_writel(val | HIEDMAC_CxCONFIG_LLI_START, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
+}
+
+static void hiedmac_start(struct hiedmacv310_dma_chan * edmac_dma_chan)
+{
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct hiedmacv310_phy_chan *ch;
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct hiedmacv310_phy_chan *ch;
+
-+ ch = hiedmac_get_phy_channel(hiedmac, edmac_dma_chan);
-+ if (!ch) {
-+ hiedmacv310_error("no phy channel available !\n");
-+ edmac_dma_chan->state = HIEDMAC_CHAN_WAITING;
-+ return;
-+ }
++ ch = hiedmac_get_phy_channel(hiedmac, edmac_dma_chan);
++ if (!ch) {
++ hiedmacv310_error("no phy channel available !\n");
++ edmac_dma_chan->state = HIEDMAC_CHAN_WAITING;
++ return;
++ }
+
-+ edmac_dma_chan->phychan = ch;
-+ edmac_dma_chan->state = HIEDMAC_CHAN_RUNNING;
++ edmac_dma_chan->phychan = ch;
++ edmac_dma_chan->state = HIEDMAC_CHAN_RUNNING;
+
-+ hiedmac_start_next_txd(edmac_dma_chan);
++ hiedmac_start_next_txd(edmac_dma_chan);
+}
+
+static void hiedmac_issue_pending(struct dma_chan *chan)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ unsigned long flags;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ unsigned long flags;
+
-+ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
-+ if (vchan_issue_pending(&edmac_dma_chan->virt_chan)) {
-+ if (!edmac_dma_chan->phychan && edmac_dma_chan->state != HIEDMAC_CHAN_WAITING) {
-+ hiedmac_start(edmac_dma_chan);
-+ }
-+ }
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
++ if (vchan_issue_pending(&edmac_dma_chan->virt_chan)) {
++ if (!edmac_dma_chan->phychan && edmac_dma_chan->state != HIEDMAC_CHAN_WAITING) {
++ hiedmac_start(edmac_dma_chan);
++ }
++ }
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
+}
+
+static void hiedmac_free_txd_list(struct hiedmacv310_dma_chan *edmac_dma_chan)
+{
-+ LIST_HEAD(head);
++ LIST_HEAD(head);
+
-+ vchan_get_all_descriptors(&edmac_dma_chan->virt_chan, &head);
-+ vchan_dma_desc_free_list(&edmac_dma_chan->virt_chan, &head);
++ vchan_get_all_descriptors(&edmac_dma_chan->virt_chan, &head);
++ vchan_dma_desc_free_list(&edmac_dma_chan->virt_chan, &head);
+}
+
+static int hiedmac_config(struct dma_chan *chan,
-+ struct dma_slave_config *config)
++ struct dma_slave_config *config)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
+
-+ if (!edmac_dma_chan->slave) {
-+ hiedmacv310_error("slave is null!");
-+ return -EINVAL;
-+ }
++ if (!edmac_dma_chan->slave) {
++ hiedmacv310_error("slave is null!");
++ return -EINVAL;
++ }
+
-+ edmac_dma_chan->cfg = *config;
++ edmac_dma_chan->cfg = *config;
+
-+ return 0;
++ return 0;
+}
+
+static void hiedmac_pause_phy_chan(struct hiedmacv310_dma_chan *edmac_dma_chan)
+{
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
-+ unsigned int val;
-+ int timeout;
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
++ unsigned int val;
++ int timeout;
+
+
-+ val = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
-+ val &= ~CCFG_EN;
-+ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ val = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ val &= ~CCFG_EN;
++ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
+
-+ /* Wait for channel inactive */
-+ for (timeout = 2000; timeout > 0; timeout--) {
-+ if (!(0x1 << phychan->id & hiedmacv310_readl(hiedmac->base + HIEDMAC_CH_STAT))) {
-+ break;
-+ }
-+ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
-+ udelay(1);
-+ }
++ /* Wait for channel inactive */
++ for (timeout = 2000; timeout > 0; timeout--) {
++ if (!(0x1 << phychan->id & hiedmacv310_readl(hiedmac->base + HIEDMAC_CH_STAT))) {
++ break;
++ }
++ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ udelay(1);
++ }
+
-+ if (timeout == 0) {
-+ hiedmacv310_error(":channel%u timeout waiting for pause, timeout:%d\n",
-+ phychan->id, timeout);
-+ }
++ if (timeout == 0) {
++ hiedmacv310_error(":channel%u timeout waiting for pause, timeout:%d\n",
++ phychan->id, timeout);
++ }
+}
+
+static int hiedmac_pause(struct dma_chan *chan)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ unsigned long flags;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ unsigned long flags;
+
-+ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
+
-+ if (!edmac_dma_chan->phychan) {
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
-+ return 0;
-+ }
++ if (!edmac_dma_chan->phychan) {
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ return 0;
++ }
+
-+ hiedmac_pause_phy_chan(edmac_dma_chan);
-+ edmac_dma_chan->state = HIEDMAC_CHAN_PAUSED;
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ hiedmac_pause_phy_chan(edmac_dma_chan);
++ edmac_dma_chan->state = HIEDMAC_CHAN_PAUSED;
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
+
-+ return 0;
++ return 0;
+}
+
+static void hiedmac_resume_phy_chan(struct hiedmacv310_dma_chan *edmac_dma_chan)
+{
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
-+ unsigned int val;
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
++ unsigned int val;
+
-+ val = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
-+ val |= CCFG_EN;
-+ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ val = hiedmacv310_readl(hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
++ val |= CCFG_EN;
++ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_Cx_CONFIG(phychan->id));
+}
+
+static int hiedmac_resume(struct dma_chan *chan)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ unsigned long flags;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ unsigned long flags;
+
-+ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
+
-+ if (!edmac_dma_chan->phychan) {
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
-+ return 0;
-+ }
++ if (!edmac_dma_chan->phychan) {
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ return 0;
++ }
+
-+ hiedmac_resume_phy_chan(edmac_dma_chan);
-+ edmac_dma_chan->state = HIEDMAC_CHAN_RUNNING;
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ hiedmac_resume_phy_chan(edmac_dma_chan);
++ edmac_dma_chan->state = HIEDMAC_CHAN_RUNNING;
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
+
-+ return 0;
++ return 0;
+}
+
+void hiedmac_phy_free(struct hiedmacv310_dma_chan *chan);
+static void hiedmac_desc_free(struct virt_dma_desc *vd);
+static int hiedmac_terminate_all(struct dma_chan *chan)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ unsigned long flags;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ unsigned long flags;
+
-+ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
-+ if (!edmac_dma_chan->phychan && !edmac_dma_chan->at) {
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
-+ return 0;
-+ }
++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
++ if (!edmac_dma_chan->phychan && !edmac_dma_chan->at) {
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ return 0;
++ }
+
-+ edmac_dma_chan->state = HIEDMAC_CHAN_IDLE;
++ edmac_dma_chan->state = HIEDMAC_CHAN_IDLE;
+
-+ if (edmac_dma_chan->phychan) {
-+ hiedmac_phy_free(edmac_dma_chan);
-+ }
++ if (edmac_dma_chan->phychan) {
++ hiedmac_phy_free(edmac_dma_chan);
++ }
+
-+ if (edmac_dma_chan->at) {
-+ hiedmac_desc_free(&edmac_dma_chan->at->virt_desc);
-+ edmac_dma_chan->at = NULL;
-+ }
-+ hiedmac_free_txd_list(edmac_dma_chan);
++ if (edmac_dma_chan->at) {
++ hiedmac_desc_free(&edmac_dma_chan->at->virt_desc);
++ edmac_dma_chan->at = NULL;
++ }
++ hiedmac_free_txd_list(edmac_dma_chan);
+
-+ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
+
-+ return 0;
++ return 0;
+}
+
+static struct transfer_desc *hiedmac_get_tsf_desc(struct hiedmacv310_driver_data *plchan)
+{
-+ struct transfer_desc *tsf_desc = kzalloc(sizeof(struct transfer_desc), GFP_NOWAIT);
++ struct transfer_desc *tsf_desc = kzalloc(sizeof(struct transfer_desc), GFP_NOWAIT);
+
-+ if (tsf_desc) {
-+ tsf_desc->ccfg = 0;
-+ }
++ if (tsf_desc) {
++ tsf_desc->ccfg = 0;
++ }
+
-+ return tsf_desc;
++ return tsf_desc;
+}
+
+static void hiedmac_free_tsf_desc(struct hiedmacv310_driver_data *hiedmac,
-+ struct transfer_desc *tsf_desc)
++ struct transfer_desc *tsf_desc)
+{
-+ if (tsf_desc->llis_vaddr) {
-+ dma_pool_free(hiedmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr);
-+ }
++ if (tsf_desc->llis_vaddr) {
++ dma_pool_free(hiedmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr);
++ }
+
-+ kfree(tsf_desc);
++ kfree(tsf_desc);
+}
+
+static u32 get_width(enum dma_slave_buswidth width)
+{
-+ switch (width) {
-+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
-+ return HIEDMAC_WIDTH_8BIT;
-+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
-+ return HIEDMAC_WIDTH_16BIT;
-+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
-+ return HIEDMAC_WIDTH_32BIT;
-+ case DMA_SLAVE_BUSWIDTH_8_BYTES:
-+ return HIEDMAC_WIDTH_64BIT;
-+ default:
-+ hiedmacv310_error("check here, width warning!\n");
-+ return ~0;
-+ }
++ switch (width) {
++ case DMA_SLAVE_BUSWIDTH_1_BYTE:
++ return HIEDMAC_WIDTH_8BIT;
++ case DMA_SLAVE_BUSWIDTH_2_BYTES:
++ return HIEDMAC_WIDTH_16BIT;
++ case DMA_SLAVE_BUSWIDTH_4_BYTES:
++ return HIEDMAC_WIDTH_32BIT;
++ case DMA_SLAVE_BUSWIDTH_8_BYTES:
++ return HIEDMAC_WIDTH_64BIT;
++ default:
++ hiedmacv310_error("check here, width warning!\n");
++ return ~0;
++ }
+}
+
+struct transfer_desc *hiedmac_init_tsf_desc (
-+ struct dma_chan *chan,
-+ enum dma_transfer_direction direction,
-+ dma_addr_t *slave_addr)
++ struct dma_chan *chan,
++ enum dma_transfer_direction direction,
++ dma_addr_t *slave_addr)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct transfer_desc *tsf_desc;
-+ unsigned int config = 0, burst = 0;
-+ unsigned int addr_width = 0, maxburst = 0;
-+ unsigned int width = 0;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct transfer_desc *tsf_desc;
++ unsigned int config = 0, burst = 0;
++ unsigned int addr_width = 0, maxburst = 0;
++ unsigned int width = 0;
+
-+ tsf_desc = hiedmac_get_tsf_desc(hiedmac);
-+ if (!tsf_desc) {
-+ hiedmacv310_error("get tsf desc fail!\n");
-+ return NULL;
-+ }
++ tsf_desc = hiedmac_get_tsf_desc(hiedmac);
++ if (!tsf_desc) {
++ hiedmacv310_error("get tsf desc fail!\n");
++ return NULL;
++ }
+
-+ if (direction == DMA_MEM_TO_DEV) {
-+ config = HIEDMAC_CONFIG_SRC_INC;
-+ *slave_addr = edmac_dma_chan->cfg.dst_addr;
-+ addr_width = edmac_dma_chan->cfg.dst_addr_width;
-+ maxburst = edmac_dma_chan->cfg.dst_maxburst;
-+ } else if (direction == DMA_DEV_TO_MEM) {
-+ config = HIEDMAC_CONFIG_DST_INC;
-+ *slave_addr = edmac_dma_chan->cfg.src_addr;
-+ addr_width = edmac_dma_chan->cfg.src_addr_width;
-+ maxburst = edmac_dma_chan->cfg.src_maxburst;
-+ } else {
-+ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
-+ hiedmacv310_error("direction unsupported!\n");
-+ return NULL;
-+ }
++ if (direction == DMA_MEM_TO_DEV) {
++ config = HIEDMAC_CONFIG_SRC_INC;
++ *slave_addr = edmac_dma_chan->cfg.dst_addr;
++ addr_width = edmac_dma_chan->cfg.dst_addr_width;
++ maxburst = edmac_dma_chan->cfg.dst_maxburst;
++ } else if (direction == DMA_DEV_TO_MEM) {
++ config = HIEDMAC_CONFIG_DST_INC;
++ *slave_addr = edmac_dma_chan->cfg.src_addr;
++ addr_width = edmac_dma_chan->cfg.src_addr_width;
++ maxburst = edmac_dma_chan->cfg.src_maxburst;
++ } else {
++ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
++ hiedmacv310_error("direction unsupported!\n");
++ return NULL;
++ }
+
-+ hiedmacv310_trace(3, "addr_width = 0x%x\n", addr_width);
-+ width = get_width(addr_width);
-+ hiedmacv310_trace(3, "width = 0x%x\n", width);
-+ config |= width << HIEDMAC_CONFIG_SRC_WIDTH_SHIFT;
-+ config |= width << HIEDMAC_CONFIG_DST_WIDTH_SHIFT;
-+ hiedmacv310_trace(2, "tsf_desc->ccfg = 0x%x\n", config);
++ hiedmacv310_trace(3, "addr_width = 0x%x\n", addr_width);
++ width = get_width(addr_width);
++ hiedmacv310_trace(3, "width = 0x%x\n", width);
++ config |= width << HIEDMAC_CONFIG_SRC_WIDTH_SHIFT;
++ config |= width << HIEDMAC_CONFIG_DST_WIDTH_SHIFT;
++ hiedmacv310_trace(2, "tsf_desc->ccfg = 0x%x\n", config);
+
-+ hiedmacv310_trace(3, "maxburst = 0x%x\n", maxburst);
-+ if (maxburst > (HIEDMAC_MAX_BURST_WIDTH)) {
-+ burst |= (HIEDMAC_MAX_BURST_WIDTH - 1);
-+ } else if (maxburst == 0) {
-+ burst |= HIEDMAC_MIN_BURST_WIDTH;
-+ } else {
-+ burst |= (maxburst - 1);
-+ }
-+ hiedmacv310_trace(3, "burst = 0x%x\n", burst);
-+ config |= burst << HIEDMAC_CONFIG_SRC_BURST_SHIFT;
-+ config |= burst << HIEDMAC_CONFIG_DST_BURST_SHIFT;
++ hiedmacv310_trace(3, "maxburst = 0x%x\n", maxburst);
++ if (maxburst > (HIEDMAC_MAX_BURST_WIDTH)) {
++ burst |= (HIEDMAC_MAX_BURST_WIDTH - 1);
++ } else if (maxburst == 0) {
++ burst |= HIEDMAC_MIN_BURST_WIDTH;
++ } else {
++ burst |= (maxburst - 1);
++ }
++ hiedmacv310_trace(3, "burst = 0x%x\n", burst);
++ config |= burst << HIEDMAC_CONFIG_SRC_BURST_SHIFT;
++ config |= burst << HIEDMAC_CONFIG_DST_BURST_SHIFT;
+
-+ if (edmac_dma_chan->signal >= 0) {
-+ hiedmacv310_trace(2, "edmac_dma_chan->signal = %d\n", edmac_dma_chan->signal);
-+ config |= (unsigned int)edmac_dma_chan->signal << HIEDMAC_CXCONFIG_SIGNAL_SHIFT;
-+ }
++ if (edmac_dma_chan->signal >= 0) {
++ hiedmacv310_trace(2, "edmac_dma_chan->signal = %d\n", edmac_dma_chan->signal);
++ config |= (unsigned int)edmac_dma_chan->signal << HIEDMAC_CXCONFIG_SIGNAL_SHIFT;
++ }
+
-+ config |= HIEDMAC_CXCONFIG_DEV_MEM_TYPE << HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT;
-+ tsf_desc->ccfg = config;
-+ hiedmacv310_trace(2, "tsf_desc->ccfg = 0x%x\n", tsf_desc->ccfg);
++ config |= HIEDMAC_CXCONFIG_DEV_MEM_TYPE << HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT;
++ tsf_desc->ccfg = config;
++ hiedmacv310_trace(2, "tsf_desc->ccfg = 0x%x\n", tsf_desc->ccfg);
+
-+ return tsf_desc;
++ return tsf_desc;
+}
+
+static void hiedmac_fill_desc(struct transfer_desc *tsf_desc, dma_addr_t src,
-+ dma_addr_t dst, unsigned int length, unsigned int num)
++ dma_addr_t dst, unsigned int length, unsigned int num)
+{
-+ hiedmac_lli *plli;
++ hiedmac_lli *plli;
+
-+ plli = (hiedmac_lli *)(tsf_desc->llis_vaddr);
-+ memset(&plli[num], 0x0, sizeof(hiedmac_lli));
++ plli = (hiedmac_lli *)(tsf_desc->llis_vaddr);
++ memset(&plli[num], 0x0, sizeof(hiedmac_lli));
+
-+ plli[num].src_addr = src;
-+ plli[num].dest_addr = dst;
-+ plli[num].config = tsf_desc->ccfg;
-+ plli[num].count = length;
-+ tsf_desc->size += length;
++ plli[num].src_addr = src;
++ plli[num].dest_addr = dst;
++ plli[num].config = tsf_desc->ccfg;
++ plli[num].count = length;
++ tsf_desc->size += length;
+
-+ if (num > 0) {
-+ plli[num - 1].next_lli = (tsf_desc->llis_busaddr + (num) * sizeof(hiedmac_lli)) & (~(HIEDMAC_LLI_ALIGN - 1));
-+ plli[num - 1].next_lli |= HIEDMAC_LLI_ENABLE;
-+ }
++ if (num > 0) {
++ plli[num - 1].next_lli = (tsf_desc->llis_busaddr + (num) * sizeof(hiedmac_lli)) & (~(HIEDMAC_LLI_ALIGN - 1));
++ plli[num - 1].next_lli |= HIEDMAC_LLI_ENABLE;
++ }
+}
+
+static struct dma_async_tx_descriptor *hiedmac_perp_slave_sg(
-+ struct dma_chan *chan, struct scatterlist *sgl,
-+ unsigned int sg_len, enum dma_transfer_direction direction,
-+ unsigned long flags, void *context)
++ struct dma_chan *chan, struct scatterlist *sgl,
++ unsigned int sg_len, enum dma_transfer_direction direction,
++ unsigned long flags, void *context)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct transfer_desc *tsf_desc;
-+ struct scatterlist *sg;
-+ int tmp;
-+ dma_addr_t src = 0, dst = 0, addr = 0, slave_addr = 0;
-+ unsigned int length = 0, num = 0;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct transfer_desc *tsf_desc = NULL;
++ struct scatterlist *sg = NULL;
++ int tmp = 0;
++ dma_addr_t src = 0, dst = 0, addr = 0, slave_addr = 0;
++ unsigned int length = 0, num = 0;
+
-+ hiedmac_lli *last_plli = NULL;
++ hiedmac_lli *last_plli = NULL;
+
-+ if (sgl == NULL) {
-+ hiedmacv310_error("sgl is null!\n");
-+ return NULL;
-+ }
++ if (sgl == NULL) {
++ hiedmacv310_error("sgl is null!\n");
++ return NULL;
++ }
+
-+ tsf_desc = hiedmac_init_tsf_desc(chan, direction, &slave_addr);
-+ if (!tsf_desc) {
-+ hiedmacv310_error("desc init fail\n");
-+ return NULL;
-+ }
++ tsf_desc = hiedmac_init_tsf_desc(chan, direction, &slave_addr);
++ if (!tsf_desc) {
++ hiedmacv310_error("desc init fail\n");
++ return NULL;
++ }
+
-+ tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT, &tsf_desc->llis_busaddr);
-+ if (!tsf_desc->llis_vaddr) {
-+ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
-+ hiedmacv310_error("malloc memory from pool fail !\n");
-+ return 0;
-+ }
++ tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT, &tsf_desc->llis_busaddr);
++ if (!tsf_desc->llis_vaddr) {
++ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
++ hiedmacv310_error("malloc memory from pool fail !\n");
++ return 0;
++ }
+
-+ for_each_sg(sgl, sg, sg_len, tmp) {
-+ addr = sg_dma_address(sg);
-+ length = sg_dma_len(sg);
-+ if (direction == DMA_MEM_TO_DEV) {
-+ src = addr;
-+ dst = slave_addr;
-+ } else if (direction == DMA_DEV_TO_MEM) {
-+ src = slave_addr;
-+ dst = addr;
-+ }
-+ hiedmac_fill_desc(tsf_desc, src, dst, length, num);
-+ num++;
-+ }
++ for_each_sg(sgl, sg, sg_len, tmp) {
++ addr = sg_dma_address(sg);
++ length = sg_dma_len(sg);
++ if (direction == DMA_MEM_TO_DEV) {
++ src = addr;
++ dst = slave_addr;
++ } else if (direction == DMA_DEV_TO_MEM) {
++ src = slave_addr;
++ dst = addr;
++ }
++ hiedmac_fill_desc(tsf_desc, src, dst, length, num);
++ num++;
++ }
+
-+ last_plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num - 1) * sizeof(hiedmac_lli));
-+ last_plli->next_lli |= HIEDMAC_LLI_DISABLE;
-+ dump_lli(tsf_desc->llis_vaddr, num);
++ last_plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num - 1) * sizeof(hiedmac_lli));
++ last_plli->next_lli |= HIEDMAC_LLI_DISABLE;
++ dump_lli(tsf_desc->llis_vaddr, num);
+
-+ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
++ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
+}
+
+static struct dma_async_tx_descriptor *hiedmac_prep_dma_memcpy(
-+ struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
-+ size_t len, unsigned long flags)
++ struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
++ size_t len, unsigned long flags)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct transfer_desc *tsf_desc;
-+ u32 config = 0;
-+ size_t num = 0;
-+ size_t length = 0;
-+ hiedmac_lli *last_plli = NULL;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct transfer_desc *tsf_desc = NULL;
++ u32 config = 0;
++ size_t num = 0;
++ size_t length = 0;
++ hiedmac_lli *last_plli = NULL;
+
-+ if (!len) {
-+ return NULL;
-+ }
++ if (!len) {
++ return NULL;
++ }
+
-+ tsf_desc = hiedmac_get_tsf_desc(hiedmac);
-+ if (!tsf_desc) {
-+ hiedmacv310_error("get tsf desc fail!\n");
-+ return NULL;
-+ }
++ tsf_desc = hiedmac_get_tsf_desc(hiedmac);
++ if (!tsf_desc) {
++ hiedmacv310_error("get tsf desc fail!\n");
++ return NULL;
++ }
+
-+ tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT, &tsf_desc->llis_busaddr);
-+ if (!tsf_desc->llis_vaddr) {
-+ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
-+ hiedmacv310_error("malloc memory from pool fail !\n");
-+ return 0;
-+ }
++ tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT, &tsf_desc->llis_busaddr);
++ if (!tsf_desc->llis_vaddr) {
++ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
++ hiedmacv310_error("malloc memory from pool fail !\n");
++ return 0;
++ }
+
-+ config |= HIEDMAC_CONFIG_SRC_INC | HIEDMAC_CONFIG_DST_INC;
-+ config |= HIEDMAC_CXCONFIG_MEM_TYPE << HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT;
++ config |= HIEDMAC_CONFIG_SRC_INC | HIEDMAC_CONFIG_DST_INC;
++ config |= HIEDMAC_CXCONFIG_MEM_TYPE << HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT;
+
-+ /* max burst width is 16 ,but reg value set 0xf */
-+ config |= (HIEDMAC_MAX_BURST_WIDTH - 1) << HIEDMAC_CONFIG_SRC_BURST_SHIFT;
-+ config |= (HIEDMAC_MAX_BURST_WIDTH - 1) << HIEDMAC_CONFIG_DST_BURST_SHIFT;
++ /* max burst width is 16 ,but reg value set 0xf */
++ config |= (HIEDMAC_MAX_BURST_WIDTH - 1) << HIEDMAC_CONFIG_SRC_BURST_SHIFT;
++ config |= (HIEDMAC_MAX_BURST_WIDTH - 1) << HIEDMAC_CONFIG_DST_BURST_SHIFT;
+
-+ tsf_desc->ccfg = config;
++ tsf_desc->ccfg = config;
+
-+ do {
-+ length = min_t(size_t, len, MAX_TRANSFER_BYTES);
-+ hiedmac_fill_desc(tsf_desc, src, dest, length, num);
++ do {
++ length = min_t(size_t, len, MAX_TRANSFER_BYTES);
++ hiedmac_fill_desc(tsf_desc, src, dest, length, num);
+
-+ src += length;
-+ dest += length;
-+ len -= length;
-+ num++;
-+ } while(len);
++ src += length;
++ dest += length;
++ len -= length;
++ num++;
++ } while(len);
+
-+ last_plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num - 1) * sizeof(hiedmac_lli));
-+ last_plli->next_lli |= HIEDMAC_LLI_DISABLE;
-+ dump_lli(tsf_desc->llis_vaddr, num);
++ last_plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num - 1) * sizeof(hiedmac_lli));
++ last_plli->next_lli |= HIEDMAC_LLI_DISABLE;
++ dump_lli(tsf_desc->llis_vaddr, num);
+
-+ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
++ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
+}
+
+
+
+static struct dma_async_tx_descriptor *hiemdac_prep_dma_cyclic(
-+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
-+ size_t period_len, enum dma_transfer_direction direction,
-+ unsigned long flags)
++ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
++ size_t period_len, enum dma_transfer_direction direction,
++ unsigned long flags)
+{
-+ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
-+ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
-+ struct transfer_desc *tsf_desc;
-+ dma_addr_t src = 0, dst = 0, addr = 0, slave_addr = 0;
-+ size_t length = 0, since = 0, total = 0, num = 0, len = 0;
-+ hiedmac_lli *last_plli = NULL;
-+ hiedmac_lli *plli = NULL;
++ struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan);
++ struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
++ struct transfer_desc *tsf_desc;
++ dma_addr_t src = 0, dst = 0, addr = 0, slave_addr = 0;
++ size_t length = 0, since = 0, total = 0, num = 0, len = 0;
++ hiedmac_lli *last_plli = NULL;
++ hiedmac_lli *plli = NULL;
+
-+ tsf_desc = hiedmac_init_tsf_desc(chan, direction, &slave_addr);
-+ if (!tsf_desc) {
-+ hiedmacv310_error("desc init fail\n");
-+ return NULL;
-+ }
++ tsf_desc = hiedmac_init_tsf_desc(chan, direction, &slave_addr);
++ if (!tsf_desc) {
++ hiedmacv310_error("desc init fail\n");
++ return NULL;
++ }
+
-+ tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT, &tsf_desc->llis_busaddr);
-+ if (!tsf_desc->llis_vaddr) {
-+ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
-+ hiedmacv310_error("malloc memory from pool fail !\n");
-+ return 0;
-+ }
++ tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT, &tsf_desc->llis_busaddr);
++ if (!tsf_desc->llis_vaddr) {
++ hiedmac_free_tsf_desc(hiedmac, tsf_desc);
++ hiedmacv310_error("malloc memory from pool fail !\n");
++ return 0;
++ }
+
-+ tsf_desc->cyclic = true;
-+ addr = buf_addr;
-+ total = buf_len;
++ tsf_desc->cyclic = true;
++ addr = buf_addr;
++ total = buf_len;
+
-+ if (period_len < MAX_TRANSFER_BYTES) {
-+ len = period_len;
-+ }
-+ do {
-+ length = min_t(size_t, total, len);
++ if (period_len < MAX_TRANSFER_BYTES) {
++ len = period_len;
++ }
++ do {
++ length = min_t(size_t, total, len);
+
-+ if (direction == DMA_MEM_TO_DEV) {
-+ src = addr;
-+ dst = slave_addr;
-+ } else if (direction == DMA_DEV_TO_MEM) {
-+ src = slave_addr;
-+ dst = addr;
-+ }
++ if (direction == DMA_MEM_TO_DEV) {
++ src = addr;
++ dst = slave_addr;
++ } else if (direction == DMA_DEV_TO_MEM) {
++ src = slave_addr;
++ dst = addr;
++ }
+
-+ hiedmac_fill_desc(tsf_desc, src, dst, length, num);
++ hiedmac_fill_desc(tsf_desc, src, dst, length, num);
+
-+ since += length;
-+ if (since >= period_len) {
-+ plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num) * sizeof(hiedmac_lli));
-+ plli->config |= HIEDMAC_CXCONFIG_ITC_EN << HIEDMAC_CXCONFIG_ITC_EN_SHIFT;
-+ since -= period_len;
-+ }
-+ addr += length;
-+ total -= length;
-+ num++;
-+ } while(total);
++ since += length;
++ if (since >= period_len) {
++ plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num) * sizeof(hiedmac_lli));
++ plli->config |= HIEDMAC_CXCONFIG_ITC_EN << HIEDMAC_CXCONFIG_ITC_EN_SHIFT;
++ since -= period_len;
++ }
++ addr += length;
++ total -= length;
++ num++;
++ } while(total);
+
-+ last_plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num - 1) * sizeof(hiedmac_lli));
++ last_plli = (hiedmac_lli *)((unsigned long)tsf_desc->llis_vaddr + (num - 1) * sizeof(hiedmac_lli));
+
-+ last_plli->next_lli = (unsigned long)(tsf_desc->llis_vaddr);
++ last_plli->next_lli = (unsigned long)(tsf_desc->llis_vaddr);
+
-+ dump_lli(tsf_desc->llis_vaddr, num);
++ dump_lli(tsf_desc->llis_vaddr, num);
+
-+ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
++ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
+}
+
+
+static void hiedmac_phy_reassign(struct hiedmacv310_phy_chan *phy_chan,
-+ struct hiedmacv310_dma_chan *chan)
++ struct hiedmacv310_dma_chan *chan)
+{
-+ phy_chan->serving = chan;
-+ chan->phychan = phy_chan;
-+ chan->state = HIEDMAC_CHAN_RUNNING;
++ phy_chan->serving = chan;
++ chan->phychan = phy_chan;
++ chan->state = HIEDMAC_CHAN_RUNNING;
+
-+ hiedmac_start_next_txd(chan);
++ hiedmac_start_next_txd(chan);
+}
+
+static void hiedmac_terminate_phy_chan(struct hiedmacv310_driver_data *hiedmac,
-+ struct hiedmacv310_dma_chan *edmac_dma_chan)
++ struct hiedmacv310_dma_chan *edmac_dma_chan)
+{
-+ unsigned int val;
-+ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
++ unsigned int val;
++ struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
+
-+ hiedmac_pause_phy_chan(edmac_dma_chan);
++ hiedmac_pause_phy_chan(edmac_dma_chan);
+
-+ val = 0x1 << phychan->id;
++ val = 0x1 << phychan->id;
+
-+ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_TC1_RAW);
-+ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
-+ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
++ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_TC1_RAW);
++ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
++ hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
+}
+
+void hiedmac_phy_free(struct hiedmacv310_dma_chan *chan)
+{
-+ struct hiedmacv310_driver_data *hiedmac = chan->host;
-+ struct hiedmacv310_dma_chan *p, *next = NULL;
++ struct hiedmacv310_driver_data *hiedmac = chan->host;
++ struct hiedmacv310_dma_chan *p = NULL;
++ struct hiedmacv310_dma_chan *next = NULL;
+
-+ list_for_each_entry(p, &hiedmac->memcpy.channels, virt_chan.chan.device_node) {
-+ if (p->state == HIEDMAC_CHAN_WAITING) {
-+ next = p;
-+ break;
-+ }
-+ }
++ list_for_each_entry(p, &hiedmac->memcpy.channels, virt_chan.chan.device_node) {
++ if (p->state == HIEDMAC_CHAN_WAITING) {
++ next = p;
++ break;
++ }
++ }
+
-+ if (!next) {
-+ list_for_each_entry(p, &hiedmac->slave.channels, virt_chan.chan.device_node) {
-+ if (p->state == HIEDMAC_CHAN_WAITING) {
-+ next = p;
-+ break;
-+ }
-+ }
-+ }
-+ hiedmac_terminate_phy_chan(hiedmac, chan);
++ if (!next) {
++ list_for_each_entry(p, &hiedmac->slave.channels, virt_chan.chan.device_node) {
++ if (p->state == HIEDMAC_CHAN_WAITING) {
++ next = p;
++ break;
++ }
++ }
++ }
++ hiedmac_terminate_phy_chan(hiedmac, chan);
+
-+ if (next) {
-+ spin_lock(&next->virt_chan.lock);
-+ hiedmac_phy_reassign(chan->phychan, next);
-+ spin_unlock(&next->virt_chan.lock);
-+ } else {
-+ chan->phychan->serving = NULL;
-+ }
++ if (next) {
++ spin_lock(&next->virt_chan.lock);
++ hiedmac_phy_reassign(chan->phychan, next);
++ spin_unlock(&next->virt_chan.lock);
++ } else {
++ chan->phychan->serving = NULL;
++ }
+
-+ chan->phychan = NULL;
-+ chan->state = HIEDMAC_CHAN_IDLE;
++ chan->phychan = NULL;
++ chan->state = HIEDMAC_CHAN_IDLE;
+}
+
+static irqreturn_t hiemdacv310_irq(int irq, void *dev)
+{
-+ struct hiedmacv310_driver_data *hiedmac = (struct hiedmacv310_driver_data *)dev;
-+ struct hiedmacv310_dma_chan *chan = NULL;
-+ struct hiedmacv310_phy_chan *phy_chan = NULL;
-+ struct transfer_desc * tsf_desc = NULL;
++ struct hiedmacv310_driver_data *hiedmac = (struct hiedmacv310_driver_data *)dev;
++ struct hiedmacv310_dma_chan *chan = NULL;
++ struct hiedmacv310_phy_chan *phy_chan = NULL;
++ struct transfer_desc * tsf_desc = NULL;
+
-+ u32 mask = 0;
-+ unsigned int channel_err_status[3];
-+ unsigned int channel_status = 0;
-+ unsigned int temp = 0;
-+ unsigned int channel_tc_status = -1;
-+ unsigned int i = 0;
++ u32 mask = 0;
++ unsigned int channel_err_status[3];
++ unsigned int channel_status = 0;
++ unsigned int temp = 0;
++ unsigned int channel_tc_status = -1;
++ unsigned int i = 0;
+
-+ channel_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_STAT);
++ channel_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_STAT);
+
-+ if (!channel_status) {
-+ hiedmacv310_error("channel_status = 0x%x\n", channel_status);
-+ return IRQ_NONE;
-+ }
++ if (!channel_status) {
++ hiedmacv310_error("channel_status = 0x%x\n", channel_status);
++ return IRQ_NONE;
++ }
+
-+ for (i = 0; i < hiedmac->channels; i++) {
-+ temp = (channel_status >> i) & 0x1;
-+ if (temp) {
-+ phy_chan = &hiedmac->phy_chans[i];
-+ chan = phy_chan->serving;
-+ if (!chan) {
-+ hiedmacv310_error("error interrupt on chan: %d!\n", i);
-+ continue;
-+ }
-+ tsf_desc = chan->at;
++ for (i = 0; i < hiedmac->channels; i++) {
++ temp = (channel_status >> i) & 0x1;
++ if (temp) {
++ phy_chan = &hiedmac->phy_chans[i];
++ chan = phy_chan->serving;
++ if (!chan) {
++ hiedmacv310_error("error interrupt on chan: %d!\n", i);
++ continue;
++ }
++ tsf_desc = chan->at;
+
-+ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC1_RAW);
-+ channel_tc_status = (channel_tc_status >> i) & 0x01;
-+ if (channel_tc_status) {
-+ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC1_RAW);
-+ }
++ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC1_RAW);
++ channel_tc_status = (channel_tc_status >> i) & 0x01;
++ if (channel_tc_status) {
++ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC1_RAW);
++ }
+
-+ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC2);
-+ channel_tc_status = (channel_tc_status >> i) & 0x01;
-+ if (channel_tc_status) {
-+ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC2_RAW);
-+ }
++ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC2);
++ channel_tc_status = (channel_tc_status >> i) & 0x01;
++ if (channel_tc_status) {
++ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC2_RAW);
++ }
+
-+ channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
-+ channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
-+ channel_err_status[1] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR2);
-+ channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
-+ channel_err_status[2] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR3);
-+ channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
-+ if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
-+ hiedmacv310_error("Error in hiedmac %d finish!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
-+ i, channel_err_status[0], channel_err_status[1], channel_err_status[2]);
-+ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
-+ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
-+ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
-+ }
++ channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
++ channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
++ channel_err_status[1] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR2);
++ channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
++ channel_err_status[2] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR3);
++ channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
++ if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
++ hiedmacv310_error("Error in hiedmac %d finish!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
++ i, channel_err_status[0], channel_err_status[1], channel_err_status[2]);
++ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
++ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
++ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
++ }
+
-+ spin_lock(&chan->virt_chan.lock);
++ spin_lock(&chan->virt_chan.lock);
+
-+ if (tsf_desc->cyclic) {
-+ vchan_cyclic_callback(&tsf_desc->virt_desc);
-+ spin_unlock(&chan->virt_chan.lock);
-+ continue;
-+ }
-+ chan->at = NULL;
-+ tsf_desc->done = true;
-+ vchan_cookie_complete(&tsf_desc->virt_desc);
++ if (tsf_desc->cyclic) {
++ vchan_cyclic_callback(&tsf_desc->virt_desc);
++ spin_unlock(&chan->virt_chan.lock);
++ continue;
++ }
++ chan->at = NULL;
++ tsf_desc->done = true;
++ vchan_cookie_complete(&tsf_desc->virt_desc);
+
-+ if (vchan_next_desc(&chan->virt_chan)) {
-+ hiedmac_start_next_txd(chan);
-+ } else {
-+ hiedmac_phy_free(chan);
-+ }
++ if (vchan_next_desc(&chan->virt_chan)) {
++ hiedmac_start_next_txd(chan);
++ } else {
++ hiedmac_phy_free(chan);
++ }
+
-+ spin_unlock(&chan->virt_chan.lock);
-+ mask |= (1 << i);
-+ }
-+ }
++ spin_unlock(&chan->virt_chan.lock);
++ mask |= (1 << i);
++ }
++ }
+
-+ return mask ? IRQ_HANDLED : IRQ_NONE;
++ return mask ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static void hiedmac_dma_slave_init(struct hiedmacv310_dma_chan *chan)
+{
-+ chan->slave = true;
++ chan->slave = true;
+}
+
+static void hiedmac_desc_free(struct virt_dma_desc *vd)
+{
-+ struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx);
-+ struct hiedmacv310_dma_chan * edmac_dma_chan = to_edamc_chan(vd->tx.chan);
++ struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx);
++ struct hiedmacv310_dma_chan * edmac_dma_chan = to_edamc_chan(vd->tx.chan);
+
-+ dma_descriptor_unmap(&vd->tx);
-+ hiedmac_free_tsf_desc(edmac_dma_chan->host, tsf_desc);
++ dma_descriptor_unmap(&vd->tx);
++ hiedmac_free_tsf_desc(edmac_dma_chan->host, tsf_desc);
+}
+
+static int hiedmac_init_virt_channels(struct hiedmacv310_driver_data *hiedmac,
-+ struct dma_device *dmadev, unsigned int channels, bool slave)
++ struct dma_device *dmadev, unsigned int channels, bool slave)
+{
-+ struct hiedmacv310_dma_chan *chan;
-+ int i;
-+ INIT_LIST_HEAD(&dmadev->channels);
++ struct hiedmacv310_dma_chan *chan = NULL;
++ int i;
++ INIT_LIST_HEAD(&dmadev->channels);
+
-+ for (i = 0; i < channels; i++) {
-+ chan = kzalloc(sizeof(struct hiedmacv310_dma_chan), GFP_KERNEL);
-+ if (!chan) {
-+ hiedmacv310_error("fail to allocate memory for virt channels!");
-+ return -1;
-+ }
++ for (i = 0; i < channels; i++) {
++ chan = kzalloc(sizeof(struct hiedmacv310_dma_chan), GFP_KERNEL);
++ if (!chan) {
++ hiedmacv310_error("fail to allocate memory for virt channels!");
++ return -1;
++ }
+
-+ chan->host = hiedmac;
-+ chan->state = HIEDMAC_CHAN_IDLE;
-+ chan->signal = -1;
++ chan->host = hiedmac;
++ chan->state = HIEDMAC_CHAN_IDLE;
++ chan->signal = -1;
+
-+ if (slave) {
-+ chan->id = i;
-+ hiedmac_dma_slave_init(chan);
-+ }
-+ chan->virt_chan.desc_free = hiedmac_desc_free;
-+ vchan_init(&chan->virt_chan, dmadev);
-+ }
-+ return 0;
++ if (slave) {
++ chan->id = i;
++ hiedmac_dma_slave_init(chan);
++ }
++ chan->virt_chan.desc_free = hiedmac_desc_free;
++ vchan_init(&chan->virt_chan, dmadev);
++ }
++ return 0;
+}
+
+void hiedmac_free_virt_channels(struct dma_device *dmadev)
+{
-+ struct hiedmacv310_dma_chan *chan = NULL;
-+ struct hiedmacv310_dma_chan *next;
++ struct hiedmacv310_dma_chan *chan = NULL;
++ struct hiedmacv310_dma_chan *next = NULL;
+
-+ list_for_each_entry_safe(chan,
-+ next, &dmadev->channels, virt_chan.chan.device_node) {
-+ list_del(&chan->virt_chan.chan.device_node);
-+ kfree(chan);
-+ }
++ list_for_each_entry_safe(chan,
++ next, &dmadev->channels, virt_chan.chan.device_node) {
++ list_del(&chan->virt_chan.chan.device_node);
++ kfree(chan);
++ }
+}
+
+
@@ -259582,191 +327519,191 @@ index 0000000..ced0702
+static int __init hiedmacv310_probe(struct platform_device *pdev)
+{
+
-+ int ret = 0, i = 0;
-+ struct hiedmacv310_driver_data *hiedmac = NULL;
-+ size_t trasfer_size = 0;
++ int ret = 0, i = 0;
++ struct hiedmacv310_driver_data *hiedmac = NULL;
++ size_t trasfer_size = 0;
+
-+ ret = dma_set_mask_and_coherent(&(pdev->dev), DMA_BIT_MASK(64));
-+ if (ret) {
-+ return ret;
-+ }
++ ret = dma_set_mask_and_coherent(&(pdev->dev), DMA_BIT_MASK(64));
++ if (ret) {
++ return ret;
++ }
+
-+ hiedmac = kzalloc(sizeof(*hiedmac), GFP_KERNEL);
-+ if (!hiedmac) {
-+ hiedmacv310_error("malloc for hiedmac fail!");
-+ ret = -ENOMEM;
-+ return ret;
-+ }
-+ hiedmac->dev = pdev;
++ hiedmac = kzalloc(sizeof(*hiedmac), GFP_KERNEL);
++ if (!hiedmac) {
++ hiedmacv310_error("malloc for hiedmac fail!");
++ ret = -ENOMEM;
++ return ret;
++ }
++ hiedmac->dev = pdev;
+
-+ ret = get_of_probe(hiedmac);
-+ if (ret) {
-+ hiedmacv310_error("get dts info fail!");
-+ goto free_hiedmac;
-+ }
++ ret = get_of_probe(hiedmac);
++ if (ret) {
++ hiedmacv310_error("get dts info fail!");
++ goto free_hiedmac;
++ }
+
+
-+ clk_prepare_enable(hiedmac->clk);
-+ clk_prepare_enable(hiedmac->axi_clk);
++ clk_prepare_enable(hiedmac->clk);
++ clk_prepare_enable(hiedmac->axi_clk);
+
-+ reset_control_deassert(hiedmac->rstc);
++ reset_control_deassert(hiedmac->rstc);
+
-+ dma_cap_set(DMA_MEMCPY, hiedmac->memcpy.cap_mask);
-+ hiedmac->memcpy.dev = &pdev->dev;
-+ hiedmac->memcpy.device_free_chan_resources = hiedmac_free_chan_resources;
-+ hiedmac->memcpy.device_prep_dma_memcpy = hiedmac_prep_dma_memcpy;
-+ hiedmac->memcpy.device_tx_status = hiedmac_tx_status;
-+ hiedmac->memcpy.device_issue_pending = hiedmac_issue_pending;
-+ hiedmac->memcpy.device_config = hiedmac_config;
-+ hiedmac->memcpy.device_pause = hiedmac_pause;
-+ hiedmac->memcpy.device_resume = hiedmac_resume;
-+ hiedmac->memcpy.device_terminate_all = hiedmac_terminate_all;
-+ hiedmac->memcpy.directions = BIT(DMA_MEM_TO_MEM);
-+ hiedmac->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
++ dma_cap_set(DMA_MEMCPY, hiedmac->memcpy.cap_mask);
++ hiedmac->memcpy.dev = &pdev->dev;
++ hiedmac->memcpy.device_free_chan_resources = hiedmac_free_chan_resources;
++ hiedmac->memcpy.device_prep_dma_memcpy = hiedmac_prep_dma_memcpy;
++ hiedmac->memcpy.device_tx_status = hiedmac_tx_status;
++ hiedmac->memcpy.device_issue_pending = hiedmac_issue_pending;
++ hiedmac->memcpy.device_config = hiedmac_config;
++ hiedmac->memcpy.device_pause = hiedmac_pause;
++ hiedmac->memcpy.device_resume = hiedmac_resume;
++ hiedmac->memcpy.device_terminate_all = hiedmac_terminate_all;
++ hiedmac->memcpy.directions = BIT(DMA_MEM_TO_MEM);
++ hiedmac->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+
-+ dma_cap_set(DMA_SLAVE, hiedmac->slave.cap_mask);
-+ dma_cap_set(DMA_CYCLIC, hiedmac->slave.cap_mask);
-+ hiedmac->slave.dev = &pdev->dev;
-+ hiedmac->slave.device_free_chan_resources = hiedmac_free_chan_resources;
-+ hiedmac->slave.device_tx_status = hiedmac_tx_status;
-+ hiedmac->slave.device_issue_pending = hiedmac_issue_pending;
-+ hiedmac->slave.device_prep_slave_sg = hiedmac_perp_slave_sg;
-+ hiedmac->slave.device_prep_dma_cyclic = hiemdac_prep_dma_cyclic;
-+ hiedmac->slave.device_config = hiedmac_config;
-+ hiedmac->slave.device_resume = hiedmac_resume;
-+ hiedmac->slave.device_pause = hiedmac_pause;
-+ hiedmac->slave.device_terminate_all = hiedmac_terminate_all;
-+ hiedmac->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
-+ hiedmac->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
++ dma_cap_set(DMA_SLAVE, hiedmac->slave.cap_mask);
++ dma_cap_set(DMA_CYCLIC, hiedmac->slave.cap_mask);
++ hiedmac->slave.dev = &pdev->dev;
++ hiedmac->slave.device_free_chan_resources = hiedmac_free_chan_resources;
++ hiedmac->slave.device_tx_status = hiedmac_tx_status;
++ hiedmac->slave.device_issue_pending = hiedmac_issue_pending;
++ hiedmac->slave.device_prep_slave_sg = hiedmac_perp_slave_sg;
++ hiedmac->slave.device_prep_dma_cyclic = hiemdac_prep_dma_cyclic;
++ hiedmac->slave.device_config = hiedmac_config;
++ hiedmac->slave.device_resume = hiedmac_resume;
++ hiedmac->slave.device_pause = hiedmac_pause;
++ hiedmac->slave.device_terminate_all = hiedmac_terminate_all;
++ hiedmac->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
++ hiedmac->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+
-+ hiedmac->max_transfer_size = MAX_TRANSFER_BYTES;
-+ trasfer_size = MAX_TSFR_LLIS * EDMACV300_LLI_WORDS * sizeof(u32);
++ hiedmac->max_transfer_size = MAX_TRANSFER_BYTES;
++ trasfer_size = MAX_TSFR_LLIS * EDMACV300_LLI_WORDS * sizeof(u32);
+
-+ hiedmac->pool = dma_pool_create(DRIVER_NAME, &(pdev->dev),
-+ trasfer_size, EDMACV300_POOL_ALIGN, 0);
-+ if (!hiedmac->pool) {
-+ hiedmacv310_error("create pool fail!");
-+ ret = -ENOMEM;
-+ goto free_hiedmac;
-+ }
++ hiedmac->pool = dma_pool_create(DRIVER_NAME, &(pdev->dev),
++ trasfer_size, EDMACV300_POOL_ALIGN, 0);
++ if (!hiedmac->pool) {
++ hiedmacv310_error("create pool fail!");
++ ret = -ENOMEM;
++ goto free_hiedmac;
++ }
+
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC1_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC2_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC1_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC2_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
+
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC1_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC2_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR1_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR2_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR3_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC1_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC2_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR1_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR2_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR3_MASK);
+
-+ ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
-+ if (ret) {
-+ hiedmacv310_error("fail to request irq");
-+ goto free_pool;
-+ }
++ ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
++ if (ret) {
++ hiedmacv310_error("fail to request irq");
++ goto free_pool;
++ }
+
-+ hiedmac->phy_chans = kzalloc((hiedmac->channels * sizeof(struct hiedmacv310_phy_chan)),
-+ GFP_KERNEL);
-+ if (!hiedmac->phy_chans) {
-+ hiedmacv310_error("malloc for phy chans fail!");
-+ ret = -ENOMEM;
-+ goto free_irq_res;
-+ }
++ hiedmac->phy_chans = kzalloc((hiedmac->channels * sizeof(struct hiedmacv310_phy_chan)),
++ GFP_KERNEL);
++ if (!hiedmac->phy_chans) {
++ hiedmacv310_error("malloc for phy chans fail!");
++ ret = -ENOMEM;
++ goto free_irq_res;
++ }
+
-+ /* initialize the phy chan */
-+ for (i = 0; i < hiedmac->channels; i++) {
-+ struct hiedmacv310_phy_chan* phy_ch = &hiedmac->phy_chans[i];
-+ phy_ch->id = i;
-+ phy_ch->base = hiedmac->base + HIEDMAC_Cx_BASE(i);
-+ spin_lock_init(&phy_ch->lock);
-+ phy_ch->serving = NULL;
-+ }
++ /* initialize the phy chan */
++ for (i = 0; i < hiedmac->channels; i++) {
++ struct hiedmacv310_phy_chan* phy_ch = &hiedmac->phy_chans[i];
++ phy_ch->id = i;
++ phy_ch->base = hiedmac->base + HIEDMAC_Cx_BASE(i);
++ spin_lock_init(&phy_ch->lock);
++ phy_ch->serving = NULL;
++ }
+
-+ /* initialize the memory virt chan */
-+ ret = hiedmac_init_virt_channels(hiedmac, &hiedmac->memcpy, hiedmac->channels, false);
-+ if (ret) {
-+ hiedmacv310_error("fail to init memory virt channels!");
-+ goto free_phychans;
-+ }
++ /* initialize the memory virt chan */
++ ret = hiedmac_init_virt_channels(hiedmac, &hiedmac->memcpy, hiedmac->channels, false);
++ if (ret) {
++ hiedmacv310_error("fail to init memory virt channels!");
++ goto free_phychans;
++ }
+
-+ /* initialize the slave virt chan */
-+ ret = hiedmac_init_virt_channels(hiedmac, &hiedmac->slave, hiedmac->slave_requests, true);
-+ if (ret) {
-+ hiedmacv310_error("fail to init slave virt channels!");
-+ goto free_memory_virt_channels;
++ /* initialize the slave virt chan */
++ ret = hiedmac_init_virt_channels(hiedmac, &hiedmac->slave, hiedmac->slave_requests, true);
++ if (ret) {
++ hiedmacv310_error("fail to init slave virt channels!");
++ goto free_memory_virt_channels;
+
-+ }
++ }
+
-+ ret = dma_async_device_register(&hiedmac->memcpy);
-+ if (ret) {
-+ hiedmacv310_error(
-+ "%s failed to register memcpy as an async device - %d\n",
-+ __func__, ret);
-+ goto free_slave_virt_channels;
-+ }
++ ret = dma_async_device_register(&hiedmac->memcpy);
++ if (ret) {
++ hiedmacv310_error(
++ "%s failed to register memcpy as an async device - %d\n",
++ __func__, ret);
++ goto free_slave_virt_channels;
++ }
+
-+ ret = dma_async_device_register(&hiedmac->slave);
-+ if (ret) {
-+ hiedmacv310_error(
-+ "%s failed to register slave as an async device - %d\n",
-+ __func__, ret);
-+ goto free_memcpy_device;
-+ }
++ ret = dma_async_device_register(&hiedmac->slave);
++ if (ret) {
++ hiedmacv310_error(
++ "%s failed to register slave as an async device - %d\n",
++ __func__, ret);
++ goto free_memcpy_device;
++ }
+
-+ return 0;
++ return 0;
+
+free_memcpy_device:
-+ dma_async_device_unregister(&hiedmac->memcpy);
++ dma_async_device_unregister(&hiedmac->memcpy);
+free_slave_virt_channels:
-+ hiedmac_free_virt_channels(&hiedmac->slave);
++ hiedmac_free_virt_channels(&hiedmac->slave);
+free_memory_virt_channels:
-+ hiedmac_free_virt_channels(&hiedmac->memcpy);
++ hiedmac_free_virt_channels(&hiedmac->memcpy);
+free_phychans:
-+ kfree(hiedmac->phy_chans);
++ kfree(hiedmac->phy_chans);
+free_irq_res:
-+ free_irq(hiedmac->irq, hiedmac);
++ free_irq(hiedmac->irq, hiedmac);
+free_pool:
-+ dma_pool_destroy(hiedmac->pool);
++ dma_pool_destroy(hiedmac->pool);
+free_hiedmac:
-+ kfree(hiedmac);
++ kfree(hiedmac);
+
-+ return ret;
++ return ret;
+}
+
+
+static int hiemda_remove(struct platform_device *pdev)
+{
-+ int err = 0;
-+ return err;
++ int err = 0;
++ return err;
+}
+
+
+static const struct of_device_id hiedmacv310_match[] = {
-+ { .compatible = "hisilicon,hiedmacv310" },
-+ {},
++ { .compatible = "hisilicon,hiedmacv310" },
++ {},
+};
+
+
+static struct platform_driver hiedmacv310_driver = {
-+ .remove = hiemda_remove,
-+ .driver = {
-+ .name = "hiedmacv310",
-+ .of_match_table = hiedmacv310_match,
-+ },
++ .remove = hiemda_remove,
++ .driver = {
++ .name = "hiedmacv310",
++ .of_match_table = hiedmacv310_match,
++ },
+};
+
+static int __init hiedmacv310_init(void)
+{
-+ return platform_driver_probe(&hiedmacv310_driver, hiedmacv310_probe);
++ return platform_driver_probe(&hiedmacv310_driver, hiedmacv310_probe);
+}
+subsys_initcall(hiedmacv310_init);
+
+static void __exit hiedmacv310_exit(void)
+{
-+ platform_driver_unregister(&hiedmacv310_driver);
++ platform_driver_unregister(&hiedmacv310_driver);
+}
+module_exit(hiedmacv310_exit);
+
@@ -260237,7 +328174,7 @@ index 0000000..e964c75
+#endif /* _UAPI_LINUX_SYNC_H */
diff --git a/drivers/hi_fence/sw_sync.c b/drivers/hi_fence/sw_sync.c
new file mode 100644
-index 0000000..8029218
+index 0000000..db9f7be
--- /dev/null
+++ b/drivers/hi_fence/sw_sync.c
@@ -0,0 +1,277 @@
@@ -260383,7 +328320,7 @@ index 0000000..8029218
+/* opening sw_sync create a new sync obj */
+static int sw_sync_open(struct inode *inode, struct file *file)
+{
-+ struct sw_sync_timeline *obj;
++ struct sw_sync_timeline *obj = NULL;
+ char task_comm[TASK_COMM_LEN];
+
+ get_task_comm(task_comm, current);
@@ -260410,11 +328347,11 @@ index 0000000..8029218
+{
+ int fd = get_unused_fd_flags(O_CLOEXEC);
+ int err;
-+ struct sync_pt *pt;
++ struct sync_pt *pt = NULL;
+ #if 0
+ struct sync_fence *fence;
+ #else
-+ struct sync_file *fence;
++ struct sync_file *fence = NULL;
+ #endif
+ struct sw_sync_create_fence_data data;
+
@@ -260449,7 +328386,7 @@ index 0000000..8029218
+ #if 0
+ hi_sync_fence_put(fence);
+ #else
-+ fput(fence->file);
++ fput(fence->file);
+ #endif
+ err = -EFAULT;
+ goto err;
@@ -260458,7 +328395,7 @@ index 0000000..8029218
+ #if 0
+ hi_sync_fence_install(fence, fd);
+ #else
-+ fd_install(fd, fence->file);
++ fd_install(fd, fence->file);
+ #endif
+
+ return 0;
@@ -260586,10 +328523,10 @@ index 0000000..93a26f0
+#endif /* _LINUX_SW_SYNC_H */
diff --git a/drivers/hi_fence/sync.c b/drivers/hi_fence/sync.c
new file mode 100644
-index 0000000..912feda
+index 0000000..4190011
--- /dev/null
+++ b/drivers/hi_fence/sync.c
-@@ -0,0 +1,739 @@
+@@ -0,0 +1,740 @@
+/*
+ * drivers/base/sync.c
+ *
@@ -260628,7 +328565,7 @@ index 0000000..912feda
+struct sync_timeline *hi_sync_timeline_create(const struct sync_timeline_ops *ops,
+ int size, const char *name)
+{
-+ struct sync_timeline *obj;
++ struct sync_timeline *obj = NULL;
+
+ if (size < sizeof(struct sync_timeline))
+ return NULL;
@@ -260697,7 +328634,8 @@ index 0000000..912feda
+{
+ unsigned long flags;
+ LIST_HEAD(signaled_pts);
-+ struct sync_pt *pt, *next;
++ struct sync_pt *pt = NULL;
++ struct sync_pt *next = NULL;
+
+ spin_lock_irqsave(&obj->child_list_lock, flags);
+
@@ -260718,7 +328656,7 @@ index 0000000..912feda
+struct sync_pt *hi_sync_pt_create(struct sync_timeline *obj, int size)
+{
+ unsigned long flags;
-+ struct sync_pt *pt;
++ struct sync_pt *pt = NULL;
+
+ if (size < sizeof(struct sync_pt))
+ return NULL;
@@ -261700,7 +329638,7 @@ index 0000000..f189501
+#endif /* _LINUX_SYNC_H */
diff --git a/drivers/hi_fence/sync_debug.c b/drivers/hi_fence/sync_debug.c
new file mode 100644
-index 0000000..e3c019a
+index 0000000..35cb240
--- /dev/null
+++ b/drivers/hi_fence/sync_debug.c
@@ -0,0 +1,259 @@
@@ -261830,7 +329768,7 @@ index 0000000..e3c019a
+
+static void sync_print_obj(struct seq_file *s, struct sync_timeline *obj)
+{
-+ struct list_head *pos;
++ struct list_head *pos = NULL;
+ unsigned long flags;
+
+ seq_printf(s, "%s %s", obj->name, obj->ops->driver_name);
@@ -261887,7 +329825,7 @@ index 0000000..e3c019a
+static int sync_debugfs_show(struct seq_file *s, void *unused)
+{
+ unsigned long flags;
-+ struct list_head *pos;
++ struct list_head *pos = NULL;
+
+ seq_puts(s, "objs:\n--------------\n");
+
@@ -262005,7 +329943,7 @@ index 0000000..ccac799
+obj-$(CONFIG_HI_VDMA_MISC_DEV) += hi_vdmav100_misc.o
diff --git a/drivers/hi_vdmav100/hi_vdma.h b/drivers/hi_vdmav100/hi_vdma.h
new file mode 100644
-index 0000000..5b71ecd
+index 0000000..851e366
--- /dev/null
+++ b/drivers/hi_vdmav100/hi_vdma.h
@@ -0,0 +1,41 @@
@@ -262030,38 +329968,37 @@ index 0000000..5b71ecd
+#define __VDMA_USER_H__
+
+struct hivdmac_host {
-+ struct device *dev;
-+ struct clk *clk;
-+ struct reset_control *rstc;
-+ void __iomem *regbase;
++ struct device *dev;
++ struct clk *clk;
++ struct reset_control *rstc;
++ void __iomem *regbase;
+
-+ int irq;
++ int irq;
+};
+
+#define VDMA_DATA_CMD 0x6
+
+struct dmac_user_para {
-+ unsigned int src;
-+ unsigned int dst;
-+ unsigned int size;
++ unsigned int src;
++ unsigned int dst;
++ unsigned int size;
+};
+
-+extern int hi_memcpy(void *dst, const void *src, size_t count);
++extern int hi_vdma_m2m_copy(void *dst, const void *src, size_t count);
+
+
+#endif
diff --git a/drivers/hi_vdmav100/hi_vdmav100.c b/drivers/hi_vdmav100/hi_vdmav100.c
new file mode 100644
-index 0000000..f53513e
+index 0000000..7415b79
--- /dev/null
+++ b/drivers/hi_vdmav100/hi_vdmav100.c
-@@ -0,0 +1,546 @@
+@@ -0,0 +1,558 @@
+/*
+ * clock driver for hisilicon hi3519 or hi3559 soc
+ *
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
-+ * Authors: yanghongwei@hisilicon.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -262111,8 +330048,8 @@ index 0000000..f53513e
+#include "hi_vdmav100.h"
+#include "hi_vdma.h"
+
-+#define user_addr(ptr) (((unsigned int)ptr < TASK_SIZE) \
-+ && ((unsigned int)ptr > 0))
++#define user_addr(ptr) (((uintptr_t)ptr < TASK_SIZE) \
++ && ((uintptr_t)ptr > 0))
+
+
+
@@ -262139,53 +330076,53 @@ index 0000000..f53513e
+irqreturn_t vdma_isr(int irq, void *dev_id)
+{
+
-+ unsigned int dma_intr_status, channel_intr_status;
-+ unsigned int i;
++ unsigned int dma_intr_status, channel_intr_status;
++ unsigned int i;
+
-+ dmac_readw(hi_reg_vdma_base_va + DMAC_INT_STATUS, dma_intr_status);
++ dmac_readw(hi_reg_vdma_base_va + DMAC_INT_STATUS, dma_intr_status);
+
-+ /* decide which channel has trigger the interrupt */
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ if (((dma_intr_status >> i) & 0x1) == 1) {
-+ dmac_readw(hi_reg_vdma_base_va
-+ + DMAC_CxINTR_RAW(i),
-+ channel_intr_status);
++ /* decide which channel has trigger the interrupt */
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ if (((dma_intr_status >> i) & 0x1) == 1) {
++ dmac_readw(hi_reg_vdma_base_va
++ + DMAC_CxINTR_RAW(i),
++ channel_intr_status);
+
-+ /* clear the channel error interrupt */
-+ dmac_writew(hi_reg_vdma_base_va
-+ + DMAC_CxINTR_RAW(i),
-+ channel_intr_status);
++ /* clear the channel error interrupt */
++ dmac_writew(hi_reg_vdma_base_va
++ + DMAC_CxINTR_RAW(i),
++ channel_intr_status);
+
-+ if ((channel_intr_status & CX_INT_STAT)
-+ == CX_INT_STAT) {
-+ /* transfer finish interrupt */
-+ if ((channel_intr_status & CX_INT_TC_RAW)
-+ == CX_INT_TC_RAW) {
-+ wake_channel_flag[i] = DMA_TRANS_OK;
++ if ((channel_intr_status & CX_INT_STAT)
++ == CX_INT_STAT) {
++ /* transfer finish interrupt */
++ if ((channel_intr_status & CX_INT_TC_RAW)
++ == CX_INT_TC_RAW) {
++ wake_channel_flag[i] = DMA_TRANS_OK;
+
-+ /* save the current channel transfer *
-+ * status to hi_g_channel_status[i] */
-+ hi_g_channel_status[i] =
-+ DMAC_CHN_SUCCESS;
++ /* save the current channel transfer *
++ * status to hi_g_channel_status[i] */
++ hi_g_channel_status[i] =
++ DMAC_CHN_SUCCESS;
+
-+ wake_up(&dmac_wait_queue[i]);
-+ goto exit;
-+ }
++ wake_up(&dmac_wait_queue[i]);
++ goto exit;
++ }
+
-+ wake_channel_flag[i] = DMA_TRANS_FAULT;
-+ pr_err("%d channel!,intr_raw=%x\n",
-+ i, channel_intr_status);
-+ hi_g_channel_status[i] =
-+ -DMAC_CHN_CONFIG_ERROR;
++ wake_channel_flag[i] = DMA_TRANS_FAULT;
++ pr_err("%d channel!,intr_raw=%x\n",
++ i, channel_intr_status);
++ hi_g_channel_status[i] =
++ -DMAC_CHN_CONFIG_ERROR;
+
-+ wake_up(&dmac_wait_queue[i]);
-+ goto exit;
-+ }
-+ }
-+ }
++ wake_up(&dmac_wait_queue[i]);
++ goto exit;
++ }
++ }
++ }
+
+exit:
-+ return IRQ_HANDLED;
++ return IRQ_HANDLED;
+}
+
+
@@ -262194,29 +330131,29 @@ index 0000000..f53513e
+ */
+int hi_vdma_channel_allocate(void *pisr)
+{
-+ unsigned int i, channelinfo, tmp, channel_intr;
-+ unsigned long flags;
++ unsigned int i, channelinfo, tmp, channel_intr;
++ unsigned long flags;
+
-+ spin_lock_irqsave(&my_lock, flags);
++ spin_lock_irqsave(&my_lock, flags);
+
-+ dmac_readw(hi_reg_vdma_base_va + DMAC_CHANNEL_STATUS, channelinfo);
++ dmac_readw(hi_reg_vdma_base_va + DMAC_CHANNEL_STATUS, channelinfo);
+
-+ for (i = 0; i < CHANNEL_NUM; i++) {
-+ if (hi_g_channel_status[i] == DMAC_CHN_VACANCY) {
-+ dmac_readw(hi_reg_vdma_base_va + DMAC_CxINTR_RAW(i),
-+ channel_intr);
-+ tmp = channelinfo >> i;
-+ /* check the vdma channel data transfer is finished ? */
-+ if ((0x00 == (tmp & 0x01)) & (channel_intr == 0x00)) {
-+ hi_g_channel_status[i] = DMAC_CHN_ALLOCAT;
-+ spin_unlock_irqrestore(&my_lock, flags);
-+ return i;/* return channel number */
-+ }
-+ }
-+ }
++ for (i = 0; i < CHANNEL_NUM; i++) {
++ if (hi_g_channel_status[i] == DMAC_CHN_VACANCY) {
++ dmac_readw(hi_reg_vdma_base_va + DMAC_CxINTR_RAW(i),
++ channel_intr);
++ tmp = channelinfo >> i;
++ /* check the vdma channel data transfer is finished ? */
++ if ((0x00 == (tmp & 0x01)) & (channel_intr == 0x00)) {
++ hi_g_channel_status[i] = DMAC_CHN_ALLOCAT;
++ spin_unlock_irqrestore(&my_lock, flags);
++ return i;/* return channel number */
++ }
++ }
++ }
+
-+ spin_unlock_irqrestore(&my_lock, flags);
-+ return DMAC_CHANNEL_INVALID;
++ spin_unlock_irqrestore(&my_lock, flags);
++ return DMAC_CHANNEL_INVALID;
+}
+
+
@@ -262225,9 +330162,9 @@ index 0000000..f53513e
+ */
+int hi_vdma_channel_free(unsigned int channel)
+{
-+ hi_g_channel_status[channel] = DMAC_CHN_VACANCY;
++ hi_g_channel_status[channel] = DMAC_CHN_VACANCY;
+
-+ return 0;
++ return 0;
+}
+
+
@@ -262236,61 +330173,61 @@ index 0000000..f53513e
+ * start a vdma transfer immediately
+ */
+int hi_vdma_channelstart(unsigned int channel,
-+ unsigned int *src, unsigned int *dest)
++ unsigned int *src, unsigned int *dest)
+{
-+ struct mm_struct *mm;
-+ unsigned int reg[DMAC_MAX_CHANNELS];
++ struct mm_struct *mm = NULL;
++ unsigned int reg[DMAC_MAX_CHANNELS];
+
-+ if (channel >= DMAC_MAX_CHANNELS) {
-+ pr_err("channel number is out of scope(%d).\n",
-+ DMAC_MAX_CHANNELS);
-+ return -EINVAL;
-+ }
++ if (channel >= DMAC_MAX_CHANNELS) {
++ pr_err("channel number is out of scope(%d).\n",
++ DMAC_MAX_CHANNELS);
++ return -EINVAL;
++ }
+
-+ hi_g_channel_status[channel] = DMAC_NOT_FINISHED;
++ hi_g_channel_status[channel] = DMAC_NOT_FINISHED;
+
-+ mm = current->mm;
-+ if (!mm) {
-+ mm = &init_mm;
-+ }
++ mm = current->mm;
++ if (!mm) {
++ mm = &init_mm;
++ }
+
-+ /* set ttbr */
-+ /* get TTBR from the page */
-+ reg[channel] = __pa(mm->pgd);
++ /* set ttbr */
++ /* get TTBR from the page */
++ reg[channel] = __pa(mm->pgd);
+
-+ /* only [31:10] is the ttbr */
-+ reg[channel] &= 0xfffffc00;
++ /* only [31:10] is the ttbr */
++ reg[channel] &= 0xfffffc00;
+
-+ /* set the RGN,AFE,AFFD,TRE */
-+ reg[channel] |= TTB_RGN | AFE | TRE;
++ /* set the RGN,AFE,AFFD,TRE */
++ reg[channel] |= TTB_RGN | AFE | TRE;
+
-+ if (user_addr(dest)) {
-+ reg[channel] &= ~DEST_IS_KERNEL;
-+ } else {
-+ reg[channel] |= DEST_IS_KERNEL;
-+ }
++ if (user_addr(dest)) {
++ reg[channel] &= ~DEST_IS_KERNEL;
++ } else {
++ reg[channel] |= DEST_IS_KERNEL;
++ }
+
-+ if (user_addr(src)) {
-+ reg[channel] &= ~SRC_IS_KERNEL;
-+ } else {
-+ reg[channel] |= SRC_IS_KERNEL;
-+ }
++ if (user_addr(src)) {
++ reg[channel] &= ~SRC_IS_KERNEL;
++ } else {
++ reg[channel] |= SRC_IS_KERNEL;
++ }
+
-+ if (in_atomic() || in_interrupt()) {
-+ /* disable the channel interrupt */
-+ reg[channel] &= ~DMAC_INTR_ENABLE;
++ if (in_atomic() || in_interrupt()) {
++ /* disable the channel interrupt */
++ reg[channel] &= ~DMAC_INTR_ENABLE;
+
-+ } else {
-+ /* enable the channel interrupt */
-+ reg[channel] |= DMAC_INTR_ENABLE;
-+ }
++ } else {
++ /* enable the channel interrupt */
++ reg[channel] |= DMAC_INTR_ENABLE;
++ }
+
-+ reg[channel] |= DMAC_CHANNEL_ENABLE;
++ reg[channel] |= DMAC_CHANNEL_ENABLE;
+
-+ /* set the TTBR register */
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_CxTTBR(channel),
-+ reg[channel]);
-+ return 0;
++ /* set the TTBR register */
++ dmac_writew(hi_reg_vdma_base_va + DMAC_CxTTBR(channel),
++ reg[channel]);
++ return 0;
+}
+
+/*
@@ -262299,45 +330236,45 @@ index 0000000..f53513e
+ */
+int hi_vdma_driver_init(struct hivdmac_host *dma)
+{
-+ unsigned int i, tmp_reg = 0;
++ unsigned int i, tmp_reg = 0;
+
+
-+ dmac_readw(hi_reg_vdma_base_va + DMAC_GLOBLE_CTRL, tmp_reg);
-+ tmp_reg |= AUTO_CLK_GT_EN;
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_GLOBLE_CTRL, tmp_reg);
++ dmac_readw(hi_reg_vdma_base_va + DMAC_GLOBLE_CTRL, tmp_reg);
++ tmp_reg |= AUTO_CLK_GT_EN;
++ dmac_writew(hi_reg_vdma_base_va + DMAC_GLOBLE_CTRL, tmp_reg);
+
-+ /* set rd dust address is ram 0 */
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_RD_DUSTB_ADDR, 0x04c11000);
++ /* set rd dust address is ram 0 */
++ dmac_writew(hi_reg_vdma_base_va + DMAC_RD_DUSTB_ADDR, 0x04c11000);
+
-+ /* set wr dust address is ram 0x1000 */
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_WR_DUSTB_ADDR, 0x04c11000);
++ /* set wr dust address is ram 0x1000 */
++ dmac_writew(hi_reg_vdma_base_va + DMAC_WR_DUSTB_ADDR, 0x04c11000);
+
-+ /* set prrr register */
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_MMU_PRRR, PRRR);
-+ /* set nmrr register */
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_MMU_NMRR, NMRR);
++ /* set prrr register */
++ dmac_writew(hi_reg_vdma_base_va + DMAC_MMU_PRRR, PRRR);
++ /* set nmrr register */
++ dmac_writew(hi_reg_vdma_base_va + DMAC_MMU_NMRR, NMRR);
+
-+ /*if (request_irq(dma->irq, &vdma_isr,
-+ 0, "Hisilicon Vdma", NULL)) {
-+ pr_err("DMA Irq %d request failed\n", dma->irq);
-+ return -1;
-+ }*/
++ /*if (request_irq(dma->irq, &vdma_isr,
++ 0, "Hisilicon Vdma", NULL)) {
++ pr_err("DMA Irq %d request failed\n", dma->irq);
++ return -1;
++ }*/
+
-+ /* config global reg for VDMA */
-+ tmp_reg |= EVENT_BROADCAST_EN | WR_CMD_NUM_PER_ARB |
-+ RD_CMD_NUM_PER_ARB | WR_OTD_NUM | RD_OTD_NUM | WFE_EN;
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_GLOBLE_CTRL, tmp_reg);
++ /* config global reg for VDMA */
++ tmp_reg |= EVENT_BROADCAST_EN | WR_CMD_NUM_PER_ARB |
++ RD_CMD_NUM_PER_ARB | WR_OTD_NUM | RD_OTD_NUM | WFE_EN;
++ dmac_writew(hi_reg_vdma_base_va + DMAC_GLOBLE_CTRL, tmp_reg);
+
-+ for (i = 0; i < CHANNEL_NUM; i++) {
-+ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
-+ init_waitqueue_head(&dmac_wait_queue[i]);
++ for (i = 0; i < CHANNEL_NUM; i++) {
++ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
++ init_waitqueue_head(&dmac_wait_queue[i]);
+
-+ }
++ }
+
-+ spin_lock_init(&my_lock);
-+ spin_lock_init(®_lock);
++ spin_lock_init(&my_lock);
++ spin_lock_init(®_lock);
+
-+ return 0;
++ return 0;
+}
+
+
@@ -262346,48 +330283,48 @@ index 0000000..f53513e
+ */
+int hi_vdma_wait(unsigned int channel)
+{
-+ unsigned long data_jiffies_timeout = jiffies + DMA_TIMEOUT_HZ;
-+ unsigned int channel_intr_raw;
++ unsigned long data_jiffies_timeout = jiffies + DMA_TIMEOUT_HZ;
++ unsigned int channel_intr_raw;
+
-+ while (1) {
-+ /*wfe();*/
-+ /* read the status of current interrupt */
-+ dmac_readw(hi_reg_vdma_base_va + DMAC_CxINTR_RAW(channel),
-+ channel_intr_raw);
++ while (1) {
++ /*wfe();*/
++ /* read the status of current interrupt */
++ dmac_readw(hi_reg_vdma_base_va + DMAC_CxINTR_RAW(channel),
++ channel_intr_raw);
+
-+ /* clear the interrupt */
-+ dmac_writew(hi_reg_vdma_base_va
-+ + DMAC_CxINTR_RAW(channel),
-+ channel_intr_raw);
++ /* clear the interrupt */
++ dmac_writew(hi_reg_vdma_base_va
++ + DMAC_CxINTR_RAW(channel),
++ channel_intr_raw);
+
-+ /*save the current channel transfer status to*
-+ *hi_g_channel_status[i]*/
-+ if ((channel_intr_raw & CX_INT_STAT) == CX_INT_STAT) {
-+ /* transfer finish interrupt */
-+ if ((channel_intr_raw & CX_INT_TC_RAW) ==
-+ CX_INT_TC_RAW) {
-+ hi_g_channel_status[channel] = DMAC_CHN_SUCCESS;
-+ return DMAC_CHN_SUCCESS;
-+ }
++ /*save the current channel transfer status to*
++ *hi_g_channel_status[i]*/
++ if ((channel_intr_raw & CX_INT_STAT) == CX_INT_STAT) {
++ /* transfer finish interrupt */
++ if ((channel_intr_raw & CX_INT_TC_RAW) ==
++ CX_INT_TC_RAW) {
++ hi_g_channel_status[channel] = DMAC_CHN_SUCCESS;
++ return DMAC_CHN_SUCCESS;
++ }
+
-+ /* transfer abort interrupt */
-+ pr_debug("data transfer error in VDMA %x channel!",
-+ channel);
-+ pr_debug("intr_raw=%x\n", channel_intr_raw);
-+ hi_g_channel_status[channel] =
-+ -DMAC_CHN_CONFIG_ERROR;
-+ return -DMAC_CHN_CONFIG_ERROR;
-+ }
++ /* transfer abort interrupt */
++ pr_debug("data transfer error in VDMA %x channel!",
++ channel);
++ pr_debug("intr_raw=%x\n", channel_intr_raw);
++ hi_g_channel_status[channel] =
++ -DMAC_CHN_CONFIG_ERROR;
++ return -DMAC_CHN_CONFIG_ERROR;
++ }
+
-+ if (!time_before(jiffies, data_jiffies_timeout)) { /* timeout */
-+ pr_err("wait interrupt timeout, channel=%d, func:%s, line:%d\n",
-+ channel, __func__, __LINE__);
-+ return -1;
-+ }
-+ }
++ if (!time_before(jiffies, data_jiffies_timeout)) { /* timeout */
++ pr_err("wait interrupt timeout, channel=%d, func:%s, line:%d\n",
++ channel, __func__, __LINE__);
++ return -1;
++ }
++ }
+
+
-+ return -1;
++ return -1;
+}
+
+
@@ -262395,206 +330332,219 @@ index 0000000..f53513e
+ * execute memory to memory vdma transfer
+ */
+static int hi_vdma_m2m_transfer(unsigned int *psource,
-+ unsigned int *pdest,
-+ unsigned int uwtransfersize)
++ unsigned int *pdest,
++ unsigned int uwtransfersize)
+{
-+ unsigned int ulchnn;
-+ int ret = 0;
++ unsigned int ulchnn;
++ int ret = 0;
+
-+ ulchnn = hi_vdma_channel_allocate(NULL);
++ ulchnn = hi_vdma_channel_allocate(NULL);
+
-+ if (ulchnn == DMAC_CHANNEL_INVALID) {
-+ pr_err("DMAC_CHANNEL_INVALID.\n");
++ if (ulchnn == DMAC_CHANNEL_INVALID) {
++ pr_err("DMAC_CHANNEL_INVALID.\n");
+
-+ return -1;
-+ }
++ return -1;
++ }
+
-+ wake_channel_flag[ulchnn] = 0;
++ wake_channel_flag[ulchnn] = 0;
+
+
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_CxLENGTH(ulchnn),
-+ uwtransfersize);
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_CxSRCADDR(ulchnn),
-+ (unsigned int)psource);
-+ dmac_writew(hi_reg_vdma_base_va + DMAC_CxDESTADDR(ulchnn),
-+ (unsigned int)pdest);
++ dmac_writew(hi_reg_vdma_base_va + DMAC_CxLENGTH(ulchnn),
++ uwtransfersize);
++ dmac_writew(hi_reg_vdma_base_va + DMAC_CxSRCADDR(ulchnn),
++ (uintptr_t)psource);
++ dmac_writew(hi_reg_vdma_base_va + DMAC_CxDESTADDR(ulchnn),
++ (uintptr_t)pdest);
+
-+ if (hi_vdma_channelstart(ulchnn, psource, pdest) != 0) {
-+ ret = -1;
-+ goto exit;
-+ }
++ if (hi_vdma_channelstart(ulchnn, psource, pdest) != 0) {
++ ret = -1;
++ goto exit;
++ }
+
-+ /*if (in_atomic() || in_interrupt()) {*/
++ /*if (in_atomic() || in_interrupt()) {*/
+
-+ if (hi_vdma_wait(ulchnn) != DMAC_CHN_SUCCESS) {
++ if (hi_vdma_wait(ulchnn) != DMAC_CHN_SUCCESS) {
+
-+ ret = -1;
-+ goto exit;
-+ }
++ ret = -1;
++ goto exit;
++ }
+
+
-+ /*} else {
-+ ret = wait_event_timeout(dmac_wait_queue[ulchnn],
-+ (wake_channel_flag[ulchnn] != 0),
-+ DMA_TIMEOUT_HZ);
-+ if (ret == 0) {
-+ ret = -1;
-+ goto exit;
-+ }
++ /*} else {
++ ret = wait_event_timeout(dmac_wait_queue[ulchnn],
++ (wake_channel_flag[ulchnn] != 0),
++ DMA_TIMEOUT_HZ);
++ if (ret == 0) {
++ ret = -1;
++ goto exit;
++ }
+
-+ if (wake_channel_flag[ulchnn] == DMA_TRANS_FAULT) {
++ if (wake_channel_flag[ulchnn] == DMA_TRANS_FAULT) {
+
-+ ret = -1;
-+ goto exit;
-+ }
-+ }*/
++ ret = -1;
++ goto exit;
++ }
++ }*/
+
+exit:
-+ hi_vdma_channel_free(ulchnn);
++ hi_vdma_channel_free(ulchnn);
+
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(hi_vdma_m2m_transfer);
+
-+int hi_memcpy(void *dst, const void *src, size_t count)
++int hi_vdma_m2m_copy(void *dst, const void *src, size_t count)
+{
-+ int ret;
++ int ret;
+
-+ ret = hi_vdma_m2m_transfer((unsigned int *)src, dst, count);
++ if (((uintptr_t)dst & 0xff) || ((uintptr_t)src & 0xff)) {
++ return -1;
++ }
++ if (((uintptr_t)src < (uintptr_t)dst) && (((uintptr_t)src + count) > (uintptr_t)dst)) {
++ return -1;
++ }
++ if (((uintptr_t)src >= (uintptr_t)dst) && ((uintptr_t)src < ((uintptr_t)dst + count))) {
++ return -1;
++ }
++ if (abs((uintptr_t)dst - (uintptr_t)src) < PAGE_SIZE) {
++ return -1;
++ }
+
-+ if (ret < 0) {
-+ return ret;
-+ } else {
-+ return 0;
-+ }
++ ret = hi_vdma_m2m_transfer((unsigned int *)src, dst, count);
++
++ if (ret < 0) {
++ return ret;
++ } else {
++ return 0;
++ }
+}
-+EXPORT_SYMBOL(hi_memcpy);
++EXPORT_SYMBOL(hi_vdma_m2m_copy);
+
+static int hivdmac_probe(struct platform_device *platdev)
+{
-+ unsigned int i;
-+ struct hivdmac_host *dma;
-+ struct resource *res;
-+ int ret;
-+ dma = devm_kzalloc(&platdev->dev, sizeof(*dma), GFP_KERNEL);
-+ if (!dma) {
-+ return -ENOMEM;
-+ }
++ unsigned int i;
++ struct hivdmac_host *dma = NULL;
++ struct resource *res = NULL;
++ int ret;
++ dma = devm_kzalloc(&platdev->dev, sizeof(*dma), GFP_KERNEL);
++ if (!dma) {
++ return -ENOMEM;
++ }
+
-+ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&platdev->dev, "no mmio resource\n");
-+ return -ENODEV;
-+ }
++ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&platdev->dev, "no mmio resource\n");
++ return -ENODEV;
++ }
+
-+ dma->regbase = devm_ioremap_resource(&platdev->dev, res);
-+ if (IS_ERR(dma->regbase)) {
-+ return PTR_ERR(dma->regbase);
-+ }
++ dma->regbase = devm_ioremap_resource(&platdev->dev, res);
++ if (IS_ERR(dma->regbase)) {
++ return PTR_ERR(dma->regbase);
++ }
+
-+ dma->clk = devm_clk_get(&platdev->dev, NULL);
-+ if (IS_ERR(dma->clk)) {
-+ return PTR_ERR(dma->clk);
-+ }
++ dma->clk = devm_clk_get(&platdev->dev, NULL);
++ if (IS_ERR(dma->clk)) {
++ return PTR_ERR(dma->clk);
++ }
+
-+ clk_prepare_enable(dma->clk);
++ clk_prepare_enable(dma->clk);
+
-+ dma->rstc = devm_reset_control_get(&platdev->dev, "dma-reset");
-+ if (IS_ERR(dma->rstc)) {
-+ return PTR_ERR(dma->rstc);
-+ }
++ dma->rstc = devm_reset_control_get(&platdev->dev, "dma-reset");
++ if (IS_ERR(dma->rstc)) {
++ return PTR_ERR(dma->rstc);
++ }
+
-+ dma->irq = platform_get_irq(platdev, 0);
-+ if (unlikely(dma->irq < 0)) {
-+ return -ENODEV;
-+ }
-+ hi_reg_vdma_base_va = dma->regbase;
-+ pr_debug("vdma reg base is %p\n", hi_reg_vdma_base_va);
-+ dma->dev = &platdev->dev;
++ dma->irq = platform_get_irq(platdev, 0);
++ if (unlikely(dma->irq < 0)) {
++ return -ENODEV;
++ }
++ hi_reg_vdma_base_va = dma->regbase;
++ pr_debug("vdma reg base is %p\n", hi_reg_vdma_base_va);
++ dma->dev = &platdev->dev;
+
-+ ret = hi_vdma_driver_init(dma);
-+ if (ret) {
-+ return -ENODEV;
-+ }
++ ret = hi_vdma_driver_init(dma);
++ if (ret) {
++ return -ENODEV;
++ }
+
-+ platform_set_drvdata(platdev, dma);
++ platform_set_drvdata(platdev, dma);
+
-+ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
-+ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
++ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ vdma_flag = 1;
-+ printk("hivdmav100 driver inited.\n");
-+ return ret;
++ vdma_flag = 1;
++ printk("hivdmav100 driver inited.\n");
++ return ret;
+}
+
+static int hivdmac_remove(struct platform_device *platdev)
+{
-+ int i;
-+ struct hivdmac_host *dma = platform_get_drvdata(platdev);
++ int i;
++ struct hivdmac_host *dma = platform_get_drvdata(platdev);
+
-+ clk_disable_unprepare(dma->clk);
++ clk_disable_unprepare(dma->clk);
+
-+ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
-+ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
++ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ vdma_flag = 0;
-+ printk("hivdmav100 driver deinited.\n");
++ vdma_flag = 0;
++ printk("hivdmav100 driver deinited.\n");
+
-+ return 0;
++ return 0;
+}
+
+static int hivdmac_suspend(struct platform_device *platdev,
-+ pm_message_t state)
++ pm_message_t state)
+{
-+ int i;
-+ struct hivdmac_host *dma = platform_get_drvdata(platdev);
++ int i;
++ struct hivdmac_host *dma = platform_get_drvdata(platdev);
+
-+ clk_prepare_enable(dma->clk);
++ clk_prepare_enable(dma->clk);
+
-+ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
-+ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
++ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ clk_disable_unprepare(dma->clk);
++ clk_disable_unprepare(dma->clk);
+
-+ vdma_flag = 0;
++ vdma_flag = 0;
+
-+ return 0;
++ return 0;
+}
+
+static int hivdmac_resume(struct platform_device *platdev)
+{
-+ int i;
-+ struct hivdmac_host *dma = platform_get_drvdata(platdev);
++ int i;
++ struct hivdmac_host *dma = platform_get_drvdata(platdev);
+
-+ hi_vdma_driver_init(dma);
++ hi_vdma_driver_init(dma);
+
-+ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
-+ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
++ hi_g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ vdma_flag = 1;
++ vdma_flag = 1;
+
-+ return 0;
++ return 0;
+}
+
+static const struct of_device_id hisi_vdmac_dt_ids[] = {
-+ { .compatible = "hisilicon,hisi-vdmac"},
-+ { },
++ { .compatible = "hisilicon,hisi-vdmac"},
++ { },
+};
+MODULE_DEVICE_TABLE(of, hisi_vdmac_dt_ids);
+
+static struct platform_driver hisi_vdmac_driver = {
-+ .driver = {
-+ .name = "hisi-vdmac",
-+ .of_match_table = hisi_vdmac_dt_ids,
-+ },
-+ .probe = hivdmac_probe,
-+ .remove = hivdmac_remove,
-+ .suspend = hivdmac_suspend,
-+ .resume = hivdmac_resume,
++ .driver = {
++ .name = "hisi-vdmac",
++ .of_match_table = hisi_vdmac_dt_ids,
++ },
++ .probe = hivdmac_probe,
++ .remove = hivdmac_remove,
++ .suspend = hivdmac_suspend,
++ .resume = hivdmac_resume,
+};
+
+module_platform_driver(hisi_vdmac_driver);
@@ -262741,7 +330691,7 @@ index 0000000..b3f384e
+#endif /* End of #ifndef __HI_INC_ECSDMACC_H__ */
diff --git a/drivers/hi_vdmav100/hi_vdmav100_misc.c b/drivers/hi_vdmav100/hi_vdmav100_misc.c
new file mode 100644
-index 0000000..4e4b22d
+index 0000000..0e0ba25
--- /dev/null
+++ b/drivers/hi_vdmav100/hi_vdmav100_misc.c
@@ -0,0 +1,109 @@
@@ -262791,63 +330741,63 @@ index 0000000..4e4b22d
+
+
+static long hi_vdma_ioctl(struct file *filep, unsigned int cmd,
-+ unsigned long arg)
++ unsigned long arg)
+{
-+ long ret = 0;
-+ struct dmac_user_para para;
++ long ret = 0;
++ struct dmac_user_para para;
+
-+ if (copy_from_user((void *)¶, (void *)arg, sizeof(para))) {
-+ return -EINVAL;
-+ }
++ if (copy_from_user((void *)¶, (void *)arg, sizeof(para))) {
++ return -EINVAL;
++ }
+
-+ switch (cmd) {
-+ case VDMA_DATA_CMD:
-+ ret = hi_memcpy((void *)para.dst, (void *)para.src, para.size);
-+ break;
-+ default:
-+ hidmac_error("unknown command :%x\n", cmd);
-+ ret = -1;
-+ break;
-+ }
++ switch (cmd) {
++ case VDMA_DATA_CMD:
++ ret = hi_vdma_m2m_copy((void *)para.dst, (void *)para.src, para.size);
++ break;
++ default:
++ hidmac_error("unknown command :%x\n", cmd);
++ ret = -1;
++ break;
++ }
+
-+ return ret;
++ return ret;
+}
+
+static int hi_vdma_open(struct inode *inode, struct file *file)
+{
-+ return 0;
++ return 0;
+}
+
+static int hi_vdma_release(struct inode *inode, struct file *file)
+{
-+ return 0;
++ return 0;
+}
+
+static const struct file_operations hi_vdma_fops = {
-+ .owner = THIS_MODULE,
-+ .unlocked_ioctl = hi_vdma_ioctl,
-+ .open = hi_vdma_open,
-+ .release = hi_vdma_release,
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = hi_vdma_ioctl,
++ .open = hi_vdma_open,
++ .release = hi_vdma_release,
+};
+
+static struct miscdevice hi_vdma_misc_device = {
-+ .minor = MISC_DYNAMIC_MINOR,
-+ .name = "hi_vdma",
-+ .fops = &hi_vdma_fops,
++ .minor = MISC_DYNAMIC_MINOR,
++ .name = "hi_vdma",
++ .fops = &hi_vdma_fops,
+};
+
+static int __init hi_vdma_init(void)
+{
-+ int ret;
++ int ret;
+
-+ ret = misc_register(&hi_vdma_misc_device);
++ ret = misc_register(&hi_vdma_misc_device);
+
-+ return ret;
++ return ret;
+}
+
+static void __exit hi_vdma_exit(void)
+{
-+ misc_deregister(&hi_vdma_misc_device);
++ misc_deregister(&hi_vdma_misc_device);
+}
+
+module_init(hi_vdma_init);
@@ -262895,7 +330845,7 @@ index 0000000..7e41f4c
+
diff --git a/drivers/hidmac/hi_pl08x.c b/drivers/hidmac/hi_pl08x.c
new file mode 100644
-index 0000000..7f2c0e5
+index 0000000..0db4416
--- /dev/null
+++ b/drivers/hidmac/hi_pl08x.c
@@ -0,0 +1,1314 @@
@@ -262980,19 +330930,19 @@ index 0000000..7f2c0e5
+ *Define Memory range
+ */
+mem_addr mem_num[MEM_MAX_NUM] = {
-+ {DDRAM_ADRS, DDRAM_SIZE},
-+ {FLASH_BASE, FLASH_SIZE}
++ {DDRAM_ADRS, DDRAM_SIZE},
++ {FLASH_BASE, FLASH_SIZE}
+};
+
+typedef void REG_ISR(int *p_dma_chn, int *p_dma_status);
+REG_ISR *function[CHANNEL_NUM];
+
+struct hidmac_host {
-+ struct clk *clk;
-+ struct reset_control *rstc;
-+ void __iomem *regbase;
++ struct clk *clk;
++ struct reset_control *rstc;
++ void __iomem *regbase;
+
-+ int irq;
++ int irq;
+};
+
+void __iomem *dma_regbase;
@@ -263021,54 +330971,54 @@ index 0000000..7f2c0e5
+ */
+irqreturn_t dmac_isr(int irq, void *dev_id)
+{
-+ struct hidmac_host *dma = dev_id;
-+ unsigned int channel_status;
-+ unsigned int channel_tc_status, channel_err_status;
-+ unsigned int i;
++ struct hidmac_host *dma = dev_id;
++ unsigned int channel_status;
++ unsigned int channel_tc_status, channel_err_status;
++ unsigned int i;
+
-+ /*read the status of current interrupt */
-+ dmac_readw(dma->regbase + DMAC_INTSTATUS, channel_status);
++ /*read the status of current interrupt */
++ dmac_readw(dma->regbase + DMAC_INTSTATUS, channel_status);
+
-+ /*decide which channel has trigger the interrupt*/
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ if ((((channel_status >> i) & 0x1) == 0x01)) {
-+ /* The INT status should be read first then clear it */
-+ /* CLR_INT(i); */
-+ dmac_readw(dma->regbase + DMAC_INTTCSTATUS, channel_tc_status);
-+ dmac_readw(dma->regbase + DMAC_INTERRORSTATUS, channel_err_status);
-+ CLR_INT(i);
-+ if (g_channel_status[i] == DMAC_CHN_VACANCY
-+ && (function[i]) == NULL) {
-+ if ((0x01 == ((channel_tc_status >> i) & 0x01)))
-+ dmac_writew(dma->regbase + DMAC_INTTCCLEAR,
-+ (0x01 << i));
-+ else if ((0x01 == ((channel_err_status
-+ >> i) & 0x01)))
-+ dmac_writew(dma->regbase + DMAC_INTERRCLR,
-+ (0x01 << i));
-+ continue;
-+ }
++ /*decide which channel has trigger the interrupt*/
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ if ((((channel_status >> i) & 0x1) == 0x01)) {
++ /* The INT status should be read first then clear it */
++ /* CLR_INT(i); */
++ dmac_readw(dma->regbase + DMAC_INTTCSTATUS, channel_tc_status);
++ dmac_readw(dma->regbase + DMAC_INTERRORSTATUS, channel_err_status);
++ CLR_INT(i);
++ if (g_channel_status[i] == DMAC_CHN_VACANCY
++ && (function[i]) == NULL) {
++ if ((0x01 == ((channel_tc_status >> i) & 0x01)))
++ dmac_writew(dma->regbase + DMAC_INTTCCLEAR,
++ (0x01 << i));
++ else if ((0x01 == ((channel_err_status
++ >> i) & 0x01)))
++ dmac_writew(dma->regbase + DMAC_INTERRCLR,
++ (0x01 << i));
++ continue;
++ }
+
-+ /* save the current channel transfer */
-+ /* status to g_channel_status[i] */
-+ if ((0x01 == ((channel_tc_status >> i) & 0x01))) {
-+ g_channel_status[i] = DMAC_CHN_SUCCESS;
-+ dmac_writew(dma->regbase + DMAC_INTTCCLEAR, (0x01 << i));
-+ } else if ((0x01 == ((channel_err_status >> i) & 0x01))) {
-+ g_channel_status[i] = -DMAC_CHN_ERROR;
-+ dmac_writew(dma->regbase + DMAC_INTERRCLR, (0x01 << i));
-+ } else {
-+ pr_err("Isr Error in DMAC_IntHandeler");
-+ pr_err("%d! channel\n", i);
-+ }
++ /* save the current channel transfer */
++ /* status to g_channel_status[i] */
++ if ((0x01 == ((channel_tc_status >> i) & 0x01))) {
++ g_channel_status[i] = DMAC_CHN_SUCCESS;
++ dmac_writew(dma->regbase + DMAC_INTTCCLEAR, (0x01 << i));
++ } else if ((0x01 == ((channel_err_status >> i) & 0x01))) {
++ g_channel_status[i] = -DMAC_CHN_ERROR;
++ dmac_writew(dma->regbase + DMAC_INTERRCLR, (0x01 << i));
++ } else {
++ pr_err("Isr Error in DMAC_IntHandeler");
++ pr_err("%d! channel\n", i);
++ }
+
-+ if ((function[i]) != NULL) {
-+ function[i](&i, &g_channel_status[i]);
-+ }
-+ }
-+ }
++ if ((function[i]) != NULL) {
++ function[i](&i, &g_channel_status[i]);
++ }
++ }
++ }
+
-+ return IRQ_RETVAL(1);
++ return IRQ_RETVAL(1);
+}
+
+/*
@@ -263078,43 +331028,43 @@ index 0000000..7f2c0e5
+static int dma_update_status(unsigned int channel)
+{
+
-+ unsigned int channel_status;
-+ unsigned int channel_tc_status[3];
-+ unsigned int channel_err_status[3];
-+ unsigned int i = channel, j, time = 0;
++ unsigned int channel_status;
++ unsigned int channel_tc_status[3];
++ unsigned int channel_err_status[3];
++ unsigned int i = channel, j, time = 0;
+
+
-+ while (1) {
-+ for (j = 0; j < 3; j++) {
-+ dmac_readw(dma_regbase + DMAC_RAWINTTCSTATUS, channel_status);
-+ channel_tc_status[j] = (channel_status >> i) & 0x01;
-+ dmac_readw(dma_regbase + DMAC_RAWINTERRORSTATUS, channel_status);
-+ channel_err_status[j] = (channel_status >> i) & 0x01;
-+ }
++ while (1) {
++ for (j = 0; j < 3; j++) {
++ dmac_readw(dma_regbase + DMAC_RAWINTTCSTATUS, channel_status);
++ channel_tc_status[j] = (channel_status >> i) & 0x01;
++ dmac_readw(dma_regbase + DMAC_RAWINTERRORSTATUS, channel_status);
++ channel_err_status[j] = (channel_status >> i) & 0x01;
++ }
+
-+ if ((channel_tc_status[0] == 0x1) &&
-+ (channel_tc_status[1] == 0x1) &&
-+ (channel_tc_status[2] == 0x1)) {
-+ g_channel_status[i] = DMAC_CHN_SUCCESS;
-+ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << i));
-+ break;
-+ } else if ((channel_err_status[0] == 0x1) &&
-+ (channel_err_status[1] == 0x1) &&
-+ (channel_err_status[2] == 0x1)) {
-+ g_channel_status[i] = -DMAC_CHN_ERROR;
-+ dma_err("Error in DMAC %d finish!\n", i);
-+ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << i));
-+ break;
-+ }
++ if ((channel_tc_status[0] == 0x1) &&
++ (channel_tc_status[1] == 0x1) &&
++ (channel_tc_status[2] == 0x1)) {
++ g_channel_status[i] = DMAC_CHN_SUCCESS;
++ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << i));
++ break;
++ } else if ((channel_err_status[0] == 0x1) &&
++ (channel_err_status[1] == 0x1) &&
++ (channel_err_status[2] == 0x1)) {
++ g_channel_status[i] = -DMAC_CHN_ERROR;
++ dma_err("Error in DMAC %d finish!\n", i);
++ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << i));
++ break;
++ }
+
-+ if (++time == HI_DMA_UPDATE_TIMEOUT) {
-+ dma_err("Timeout in DMAC %d!\n", i);
-+ g_channel_status[i] = -DMAC_CHN_TIMEOUT;
-+ break;
-+ }
-+ }
++ if (++time == HI_DMA_UPDATE_TIMEOUT) {
++ dma_err("Timeout in DMAC %d!\n", i);
++ g_channel_status[i] = -DMAC_CHN_TIMEOUT;
++ break;
++ }
++ }
+
-+ return g_channel_status[i];
++ return g_channel_status[i];
+}
+
+
@@ -263123,32 +331073,32 @@ index 0000000..7f2c0e5
+ */
+static int dmac_check_over(unsigned int channel)
+{
-+ int status = 0;
++ int status = 0;
+
-+ if (-DMAC_CHN_ERROR == g_channel_status[channel]) {
-+ dma_err("Error transfer %d finished\n", channel);
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), DMAC_CxDISABLE);
-+ g_channel_status[channel] = DMAC_CHN_VACANCY;
-+ status = -DMAC_CHN_ERROR;
-+ } else if (g_channel_status[channel] == DMAC_NOT_FINISHED) {
-+ status = DMAC_NOT_FINISHED;
-+ } else if (g_channel_status[channel] == DMAC_CHN_ALLOCAT) {
-+ status = DMAC_CHN_ALLOCAT;
-+ } else if (g_channel_status[channel] == DMAC_CHN_VACANCY) {
-+ status = DMAC_CHN_VACANCY;
-+ } else if (-DMAC_CHN_TIMEOUT == g_channel_status[channel]) {
-+ dma_err("transfer %d timeout!\n", channel);
-+ status = -DMAC_CHN_TIMEOUT;
-+ } else if (g_channel_status[channel] == DMAC_CHN_SUCCESS)
-+ /*The transfer of Channel %d has finished successfully!*/
-+ {
-+ status = DMAC_CHN_SUCCESS;
-+ } else {
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), DMAC_CxDISABLE);
-+ g_channel_status[channel] = DMAC_CHN_VACANCY;
-+ status = -DMAC_CHN_ERROR;
-+ }
-+ return status;
++ if (-DMAC_CHN_ERROR == g_channel_status[channel]) {
++ dma_err("Error transfer %d finished\n", channel);
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), DMAC_CxDISABLE);
++ g_channel_status[channel] = DMAC_CHN_VACANCY;
++ status = -DMAC_CHN_ERROR;
++ } else if (g_channel_status[channel] == DMAC_NOT_FINISHED) {
++ status = DMAC_NOT_FINISHED;
++ } else if (g_channel_status[channel] == DMAC_CHN_ALLOCAT) {
++ status = DMAC_CHN_ALLOCAT;
++ } else if (g_channel_status[channel] == DMAC_CHN_VACANCY) {
++ status = DMAC_CHN_VACANCY;
++ } else if (-DMAC_CHN_TIMEOUT == g_channel_status[channel]) {
++ dma_err("transfer %d timeout!\n", channel);
++ status = -DMAC_CHN_TIMEOUT;
++ } else if (g_channel_status[channel] == DMAC_CHN_SUCCESS)
++ /*The transfer of Channel %d has finished successfully!*/
++ {
++ status = DMAC_CHN_SUCCESS;
++ } else {
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), DMAC_CxDISABLE);
++ g_channel_status[channel] = DMAC_CHN_VACANCY;
++ status = -DMAC_CHN_ERROR;
++ }
++ return status;
+}
+
+spinlock_t my_lcok = __SPIN_LOCK_UNLOCKED(old_style_spin_init);
@@ -263159,57 +331109,57 @@ index 0000000..7f2c0e5
+ */
+int dmac_channel_allocate(void *pisr)
+{
-+ unsigned int i, channelinfo, g_channelinfo;
++ unsigned int i, channelinfo, g_channelinfo;
+
-+ for (i = 0; i < CHANNEL_NUM; i++) {
-+ dmac_check_over(dmac_channel[i]);
-+ }
++ for (i = 0; i < CHANNEL_NUM; i++) {
++ dmac_check_over(dmac_channel[i]);
++ }
+
-+ dmac_readw(dma_regbase + DMAC_ENBLDCHNS, g_channelinfo);
-+ g_channelinfo = g_channelinfo & 0x00ff;
++ dmac_readw(dma_regbase + DMAC_ENBLDCHNS, g_channelinfo);
++ g_channelinfo = g_channelinfo & 0x00ff;
+
-+ for (i = 0; i < CHANNEL_NUM; i++) {
-+ if (g_channel_status[dmac_channel[i]] == DMAC_CHN_VACANCY) {
-+ channelinfo = g_channelinfo >> dmac_channel[i];
-+ if (0x00 == (channelinfo & 0x01)) {
-+ /*clear the interrupt in this channel */
-+ dmac_writew(dma_regbase + DMAC_INTERRCLR,
-+ (0x01 << dmac_channel[i]));
-+ dmac_writew(dma_regbase + DMAC_INTTCCLEAR,
-+ (0x01 << dmac_channel[i]));
++ for (i = 0; i < CHANNEL_NUM; i++) {
++ if (g_channel_status[dmac_channel[i]] == DMAC_CHN_VACANCY) {
++ channelinfo = g_channelinfo >> dmac_channel[i];
++ if (0x00 == (channelinfo & 0x01)) {
++ /*clear the interrupt in this channel */
++ dmac_writew(dma_regbase + DMAC_INTERRCLR,
++ (0x01 << dmac_channel[i]));
++ dmac_writew(dma_regbase + DMAC_INTTCCLEAR,
++ (0x01 << dmac_channel[i]));
+
-+ g_channel_status[dmac_channel[i]]
-+ = DMAC_CHN_ALLOCAT;
-+ return dmac_channel[i];
-+ }
-+ }
-+ }
++ g_channel_status[dmac_channel[i]]
++ = DMAC_CHN_ALLOCAT;
++ return dmac_channel[i];
++ }
++ }
++ }
+
-+ dma_err("no to alloc\n");
-+ return -EINVAL;
++ dma_err("no to alloc\n");
++ return -EINVAL;
+}
+EXPORT_SYMBOL(dmac_channel_allocate);
+
+int dmac_register_isr(unsigned int channel, void *pisr)
+{
-+ if (channel > CHANNEL_NUM - 1) {
-+ dma_err("channel which choosed %d is error !\n", channel);
-+ return -1;
-+ }
++ if (channel > CHANNEL_NUM - 1) {
++ dma_err("channel which choosed %d is error !\n", channel);
++ return -1;
++ }
+
-+ if (g_channel_status[channel] != DMAC_CHN_VACANCY) {
-+ dma_err("dma chn %d is in used!\n", channel);
-+ return -1;
-+ }
++ if (g_channel_status[channel] != DMAC_CHN_VACANCY) {
++ dma_err("dma chn %d is in used!\n", channel);
++ return -1;
++ }
+
-+ /*clear the interrupt in this channel */
-+ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << channel));
-+ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << channel));
++ /*clear the interrupt in this channel */
++ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << channel));
++ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << channel));
+
-+ function[channel] = (void *)pisr;
-+ g_channel_status[channel] = DMAC_CHN_ALLOCAT;
++ function[channel] = (void *)pisr;
++ g_channel_status[channel] = DMAC_CHN_ALLOCAT;
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_register_isr);
+
@@ -263218,30 +331168,30 @@ index 0000000..7f2c0e5
+ */
+int dmac_channel_free(unsigned int channel)
+{
-+ if (channel >= DMAC_MAX_CHANNELS) {
-+ dma_err("channel larger than total.\n");
-+ return -EINVAL;
-+ }
++ if (channel >= DMAC_MAX_CHANNELS) {
++ dma_err("channel larger than total.\n");
++ return -EINVAL;
++ }
+
-+ g_channel_status[channel] = DMAC_CHN_VACANCY;
-+ return 0;
++ g_channel_status[channel] = DMAC_CHN_VACANCY;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_channel_free);
+
+static unsigned int dmac_check_request(unsigned int peripheral_addr,
-+ int direction)
++ int direction)
+{
-+ int i;
-+ /* check request pipe with peripheral_addr */
-+ for (i = direction; i < DMAC_MAX_PERIPHERALS; i = i + 2) {
-+ if (g_peripheral[i].peri_addr == peripheral_addr) {
-+ return i;
-+ }
-+ }
++ int i;
++ /* check request pipe with peripheral_addr */
++ for (i = direction; i < DMAC_MAX_PERIPHERALS; i = i + 2) {
++ if (g_peripheral[i].peri_addr == peripheral_addr) {
++ return i;
++ }
++ }
+
-+ dma_err("Invalid devaddr\n");
++ dma_err("Invalid devaddr\n");
+
-+ return -1;
++ return -1;
+}
+
+/*
@@ -263251,39 +331201,39 @@ index 0000000..7f2c0e5
+ */
+int dmac_init(struct hidmac_host *dma)
+{
-+ unsigned int i, tempvalue;
-+ int ret;
++ unsigned int i, tempvalue;
++ int ret;
+
-+ clk_prepare_enable(dma->clk);
-+ reset_control_deassert(dma->rstc);
++ clk_prepare_enable(dma->clk);
++ reset_control_deassert(dma->rstc);
+
-+ dmac_readw(dma->regbase + DMAC_CONFIG, tempvalue);
-+ if (tempvalue == 0) {
-+ dmac_writew(dma->regbase + DMAC_CONFIG,
-+ DMAC_CONFIG_VAL);
-+ dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
-+ dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ dmac_writew(dma->regbase + DMAC_CxCONFIG(i),
-+ DMAC_CxDISABLE);
-+ function[i] = NULL;
-+ }
-+ }
++ dmac_readw(dma->regbase + DMAC_CONFIG, tempvalue);
++ if (tempvalue == 0) {
++ dmac_writew(dma->regbase + DMAC_CONFIG,
++ DMAC_CONFIG_VAL);
++ dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
++ dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ dmac_writew(dma->regbase + DMAC_CxCONFIG(i),
++ DMAC_CxDISABLE);
++ function[i] = NULL;
++ }
++ }
+
-+ /* creat LLI */
-+ /* alloc space for dma lli, as the source is uncontinuous, so... */
-+ ret = allocate_dmalli_space(pllihead, 1);
-+ if (ret < 0) {
-+ return -1;
-+ }
++ /* creat LLI */
++ /* alloc space for dma lli, as the source is uncontinuous, so... */
++ ret = allocate_dmalli_space(pllihead, 1);
++ if (ret < 0) {
++ return -1;
++ }
+
-+ if (request_irq(dma->irq, dmac_isr, 0, "hi_dma", dma)) {
-+ dma_err("DMA Irq %d request failed\n", dma->irq);
-+ free_dmalli_space(pllihead, 1);
-+ return -1;
-+ }
++ if (request_irq(dma->irq, dmac_isr, 0, "hi_dma", dma)) {
++ dma_err("DMA Irq %d request failed\n", dma->irq);
++ free_dmalli_space(pllihead, 1);
++ return -1;
++ }
+
-+ return 0;
++ return 0;
+}
+
+
@@ -263296,20 +331246,20 @@ index 0000000..7f2c0e5
+ */
+int allocate_dmalli_space(unsigned int *ppheadlli, unsigned int page_num)
+{
-+ dma_addr_t dma_phys;
-+ void *dma_virt;
++ dma_addr_t dma_phys;
++ void *dma_virt;
+
-+ dma_virt = dma_alloc_coherent(NULL, page_num * PAGE_SIZE,
-+ &dma_phys, GFP_DMA | GFP_KERNEL);
-+ if (dma_virt == NULL) {
-+ dma_err("can't get dma mem from system\n");
-+ return -1;
-+ }
++ dma_virt = dma_alloc_coherent(NULL, page_num * PAGE_SIZE,
++ &dma_phys, GFP_DMA | GFP_KERNEL);
++ if (dma_virt == NULL) {
++ dma_err("can't get dma mem from system\n");
++ return -1;
++ }
+
-+ ppheadlli[0] = (unsigned int)(dma_phys);
-+ ppheadlli[1] = (unsigned int)(dma_virt);
++ ppheadlli[0] = (unsigned int)(dma_phys);
++ ppheadlli[1] = (unsigned int)(dma_virt);
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(allocate_dmalli_space);
+
@@ -263318,18 +331268,18 @@ index 0000000..7f2c0e5
+ */
+int free_dmalli_space(unsigned int *ppheadlli, unsigned int page_num)
+{
-+ dma_addr_t dma_phys;
-+ unsigned int dma_virt;
++ dma_addr_t dma_phys;
++ unsigned int dma_virt;
+
-+ dma_phys = (dma_addr_t)(ppheadlli[0]);
-+ dma_virt = ppheadlli[1];
++ dma_phys = (dma_addr_t)(ppheadlli[0]);
++ dma_virt = ppheadlli[1];
+
-+ dma_free_coherent(NULL, page_num * PAGE_SIZE,
-+ (void *)dma_virt, dma_phys);
++ dma_free_coherent(NULL, page_num * PAGE_SIZE,
++ (void *)dma_virt, dma_phys);
+
-+ ppheadlli[0] = 0;
-+ ppheadlli[1] = 0;
-+ return 0;
++ ppheadlli[0] = 0;
++ ppheadlli[1] = 0;
++ return 0;
+}
+EXPORT_SYMBOL(free_dmalli_space);
+
@@ -263339,33 +331289,33 @@ index 0000000..7f2c0e5
+ * it is necessary to call dmac_channelstart for channel enable
+ */
+int dmac_start_m2m(unsigned int channel, unsigned int psource,
-+ unsigned int pdest, unsigned int uwnumtransfers)
++ unsigned int pdest, unsigned int uwnumtransfers)
+{
-+ unsigned int uwchannel_num, tmp_trasnsfer;
++ unsigned int uwchannel_num, tmp_trasnsfer;
+
-+ if (uwnumtransfers > (MAXTRANSFERSIZE << 2)) {
-+ dma_err("Invalidate transfer size,size=%x\n", uwnumtransfers);
-+ return -EINVAL;
-+ }
++ if (uwnumtransfers > (MAXTRANSFERSIZE << 2)) {
++ dma_err("Invalidate transfer size,size=%x\n", uwnumtransfers);
++ return -EINVAL;
++ }
+
-+ uwchannel_num = channel;
++ uwchannel_num = channel;
+
-+ if ((uwchannel_num == DMAC_CHANNEL_INVALID)
-+ || (uwchannel_num > CHANNEL_NUM)) {
-+ pr_err("failure of DMAC channel allocation in M2M function!\n");
-+ return -EFAULT;
-+ }
++ if ((uwchannel_num == DMAC_CHANNEL_INVALID)
++ || (uwchannel_num > CHANNEL_NUM)) {
++ pr_err("failure of DMAC channel allocation in M2M function!\n");
++ return -EFAULT;
++ }
+
-+ /* dmac_writew (DMAC_CxCONFIG(uwchannel_num), DMAC_CxDISABLE); */
-+ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num), psource);
-+ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num), pdest);
-+ dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num), 0);
-+ tmp_trasnsfer = (uwnumtransfers >> 2) & 0xfff;
-+ tmp_trasnsfer = tmp_trasnsfer | (DMAC_CxCONTROL_M2M & (~0xfff));
-+ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num), tmp_trasnsfer);
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num), DMAC_CxCONFIG_M2M);
++ /* dmac_writew (DMAC_CxCONFIG(uwchannel_num), DMAC_CxDISABLE); */
++ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num), psource);
++ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num), pdest);
++ dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num), 0);
++ tmp_trasnsfer = (uwnumtransfers >> 2) & 0xfff;
++ tmp_trasnsfer = tmp_trasnsfer | (DMAC_CxCONTROL_M2M & (~0xfff));
++ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num), tmp_trasnsfer);
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num), DMAC_CxCONFIG_M2M);
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_start_m2m);
+
@@ -263376,19 +331326,19 @@ index 0000000..7f2c0e5
+int dmac_channelstart(unsigned int u32channel)
+{
+
-+ unsigned int reg_value;
++ unsigned int reg_value;
+
-+ if (u32channel >= DMAC_MAX_CHANNELS) {
-+ dma_err("channel larger %d\n", DMAC_MAX_CHANNELS);
-+ return -EINVAL;
-+ }
++ if (u32channel >= DMAC_MAX_CHANNELS) {
++ dma_err("channel larger %d\n", DMAC_MAX_CHANNELS);
++ return -EINVAL;
++ }
+
-+ g_channel_status[u32channel] = DMAC_NOT_FINISHED;
-+ dmac_readw(dma_regbase + DMAC_CxCONFIG(u32channel), reg_value);
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(u32channel),
-+ (reg_value | DMAC_CHANNEL_ENABLE));
++ g_channel_status[u32channel] = DMAC_NOT_FINISHED;
++ dmac_readw(dma_regbase + DMAC_CxCONFIG(u32channel), reg_value);
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(u32channel),
++ (reg_value | DMAC_CHANNEL_ENABLE));
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_channelstart);
+
@@ -263397,37 +331347,37 @@ index 0000000..7f2c0e5
+ */
+int dmac_wait(int channel)
+{
-+ int ret_result, ret = 0;
++ int ret_result, ret = 0;
+
-+ if (channel < 0) {
-+ return -1;
-+ }
++ if (channel < 0) {
++ return -1;
++ }
+
-+ while (1) {
-+ ret_result = dma_update_status(channel);
-+ if (ret_result == -DMAC_CHN_ERROR) {
-+ dma_err("Transfer Error.\n");
-+ ret = -1;
-+ goto end;
-+ } else if (ret_result == DMAC_NOT_FINISHED) {
-+ udelay(10);
-+ } else if (ret_result == DMAC_CHN_SUCCESS) {
-+ ret = DMAC_CHN_SUCCESS;
-+ goto end;
-+ } else if (ret_result == DMAC_CHN_VACANCY) {
-+ ret = DMAC_CHN_SUCCESS;
-+ goto end;
-+ } else if (ret_result == -DMAC_CHN_TIMEOUT) {
-+ dma_err("Timeout.\n");
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), DMAC_CxDISABLE);
-+ g_channel_status[channel] = DMAC_CHN_VACANCY;
-+ ret = -1;
-+ goto end;
-+ }
-+ }
++ while (1) {
++ ret_result = dma_update_status(channel);
++ if (ret_result == -DMAC_CHN_ERROR) {
++ dma_err("Transfer Error.\n");
++ ret = -1;
++ goto end;
++ } else if (ret_result == DMAC_NOT_FINISHED) {
++ udelay(10);
++ } else if (ret_result == DMAC_CHN_SUCCESS) {
++ ret = DMAC_CHN_SUCCESS;
++ goto end;
++ } else if (ret_result == DMAC_CHN_VACANCY) {
++ ret = DMAC_CHN_SUCCESS;
++ goto end;
++ } else if (ret_result == -DMAC_CHN_TIMEOUT) {
++ dma_err("Timeout.\n");
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), DMAC_CxDISABLE);
++ g_channel_status[channel] = DMAC_CHN_VACANCY;
++ ret = -1;
++ goto end;
++ }
++ }
+end:
-+ dmac_channelclose(channel);
-+ return ret;
++ dmac_channelclose(channel);
++ return ret;
+}
+EXPORT_SYMBOL(dmac_wait);
+
@@ -263435,54 +331385,54 @@ index 0000000..7f2c0e5
+ * buile LLI for memory to memory DMA transfer
+ */
+int dmac_buildllim2m_isp(unsigned int *ppheadlli, unsigned int *psource,
-+ unsigned int *pdest, unsigned int *length,
-+ unsigned int lli_num)
++ unsigned int *pdest, unsigned int *length,
++ unsigned int lli_num)
+{
-+ unsigned int address, phy_address;
-+ unsigned int j;
++ unsigned int address, phy_address;
++ unsigned int j;
+
-+ if (ppheadlli != NULL) {
-+ phy_address = (unsigned int)(ppheadlli[0]);
-+ dma_debug("phy_address: 0x%X\n", phy_address);
-+ address = (unsigned int)(ppheadlli[1]);
-+ dma_debug("address: 0x%X\n", address);
-+ for (j = 0; j < lli_num; j++) {
-+ dma_debug("psource[%d]: 0x%X\n", j, psource[j]);
-+ dmac_writew(address, psource[j]);
-+ address += 4;
-+ phy_address += 4;
-+ dma_debug("pdest[%d]: 0x%X\n", j, pdest[j]);
-+ dmac_writew(address, pdest[j]);
-+ address += 4;
-+ phy_address += 4;
++ if (ppheadlli != NULL) {
++ phy_address = (unsigned int)(ppheadlli[0]);
++ dma_debug("phy_address: 0x%X\n", phy_address);
++ address = (unsigned int)(ppheadlli[1]);
++ dma_debug("address: 0x%X\n", address);
++ for (j = 0; j < lli_num; j++) {
++ dma_debug("psource[%d]: 0x%X\n", j, psource[j]);
++ dmac_writew(address, psource[j]);
++ address += 4;
++ phy_address += 4;
++ dma_debug("pdest[%d]: 0x%X\n", j, pdest[j]);
++ dmac_writew(address, pdest[j]);
++ address += 4;
++ phy_address += 4;
+
-+ /* if the last node, next_lli_addr = 0*/
-+ if (j == (lli_num - 1)) {
-+ dmac_writew(address, 0);
-+ } else
-+ dmac_writew(address,
-+ (((phy_address + 8) & (~0x03))
-+ | DMAC_CxLLI_LM));
++ /* if the last node, next_lli_addr = 0*/
++ if (j == (lli_num - 1)) {
++ dmac_writew(address, 0);
++ } else
++ dmac_writew(address,
++ (((phy_address + 8) & (~0x03))
++ | DMAC_CxLLI_LM));
+
-+ address += 4;
-+ phy_address += 4;
++ address += 4;
++ phy_address += 4;
+
-+ if (j == (lli_num - 1)) {
-+ dmac_writew(address, ((DMAC_CxCONTROL_LLIM2M_ISP
-+ & (~0xfff)) | (length[j])
-+ | 0x80000000));
-+ } else {
-+ dmac_writew(address,
-+ (((DMAC_CxCONTROL_LLIM2M_ISP & (~0xfff)) |
-+ (length[j])) & 0x7fffffff));
-+ }
++ if (j == (lli_num - 1)) {
++ dmac_writew(address, ((DMAC_CxCONTROL_LLIM2M_ISP
++ & (~0xfff)) | (length[j])
++ | 0x80000000));
++ } else {
++ dmac_writew(address,
++ (((DMAC_CxCONTROL_LLIM2M_ISP & (~0xfff)) |
++ (length[j])) & 0x7fffffff));
++ }
+
-+ address += 4;
-+ phy_address += 4;
-+ }
-+ }
++ address += 4;
++ phy_address += 4;
++ }
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_buildllim2m_isp);
+
@@ -263490,61 +331440,61 @@ index 0000000..7f2c0e5
+ * buile LLI for memory to memory DMA transfer
+ */
+int dmac_buildllim2m(unsigned int *ppheadlli, unsigned int pdest,
-+ unsigned int psource, unsigned int totaltransfersize,
-+ unsigned int uwnumtransfers)
++ unsigned int psource, unsigned int totaltransfersize,
++ unsigned int uwnumtransfers)
+{
-+ unsigned int lli_num = 0;
-+ unsigned int last_lli = 0;
-+ unsigned int address, phy_address, srcaddr, denstaddr;
-+ unsigned int j;
++ unsigned int lli_num = 0;
++ unsigned int last_lli = 0;
++ unsigned int address, phy_address, srcaddr, denstaddr;
++ unsigned int j;
+
-+ lli_num = (totaltransfersize / uwnumtransfers);
++ lli_num = (totaltransfersize / uwnumtransfers);
+
-+ if ((totaltransfersize % uwnumtransfers) != 0) {
-+ last_lli = 1, ++lli_num;
-+ }
++ if ((totaltransfersize % uwnumtransfers) != 0) {
++ last_lli = 1, ++lli_num;
++ }
+
-+ if (ppheadlli != NULL) {
-+ phy_address = (unsigned int)(ppheadlli[0]);
-+ address = (unsigned int)(ppheadlli[1]);
-+ for (j = 0; j < lli_num; j++) {
-+ srcaddr = (psource + (j * uwnumtransfers));
-+ dmac_writew(address, srcaddr);
-+ address += 4;
-+ phy_address += 4;
-+ denstaddr = (pdest + (j * uwnumtransfers));
-+ dmac_writew(address, denstaddr);
-+ address += 4;
-+ phy_address += 4;
-+ if (j == (lli_num - 1)) {
-+ dmac_writew(address, 0);
-+ } else
-+ dmac_writew(address,
-+ (((phy_address + 8) & (~0x03))
-+ | DMAC_CxLLI_LM));
++ if (ppheadlli != NULL) {
++ phy_address = (unsigned int)(ppheadlli[0]);
++ address = (unsigned int)(ppheadlli[1]);
++ for (j = 0; j < lli_num; j++) {
++ srcaddr = (psource + (j * uwnumtransfers));
++ dmac_writew(address, srcaddr);
++ address += 4;
++ phy_address += 4;
++ denstaddr = (pdest + (j * uwnumtransfers));
++ dmac_writew(address, denstaddr);
++ address += 4;
++ phy_address += 4;
++ if (j == (lli_num - 1)) {
++ dmac_writew(address, 0);
++ } else
++ dmac_writew(address,
++ (((phy_address + 8) & (~0x03))
++ | DMAC_CxLLI_LM));
+
-+ address += 4;
-+ phy_address += 4;
++ address += 4;
++ phy_address += 4;
+
-+ if ((j == (lli_num - 1)) && (last_lli == 0))
-+ dmac_writew(address, ((DMAC_CxCONTROL_LLIM2M
-+ & (~0xfff)) | (uwnumtransfers >> 2)
-+ | 0x80000000));
-+ else if ((j == (lli_num - 1)) && (last_lli == 1))
-+ dmac_writew(address, ((DMAC_CxCONTROL_LLIM2M
-+ & (~0xfff)) | ((totaltransfersize
-+ % uwnumtransfers) >> 2) | 0x80000000));
-+ else
-+ dmac_writew(address,
-+ (((DMAC_CxCONTROL_LLIM2M & (~0xfff)) |
-+ (uwnumtransfers >> 2)) & 0x7fffffff));
++ if ((j == (lli_num - 1)) && (last_lli == 0))
++ dmac_writew(address, ((DMAC_CxCONTROL_LLIM2M
++ & (~0xfff)) | (uwnumtransfers >> 2)
++ | 0x80000000));
++ else if ((j == (lli_num - 1)) && (last_lli == 1))
++ dmac_writew(address, ((DMAC_CxCONTROL_LLIM2M
++ & (~0xfff)) | ((totaltransfersize
++ % uwnumtransfers) >> 2) | 0x80000000));
++ else
++ dmac_writew(address,
++ (((DMAC_CxCONTROL_LLIM2M & (~0xfff)) |
++ (uwnumtransfers >> 2)) & 0x7fffffff));
+
-+ address += 4;
-+ phy_address += 4;
-+ }
-+ }
++ address += 4;
++ phy_address += 4;
++ }
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_buildllim2m);
+
@@ -263554,46 +331504,46 @@ index 0000000..7f2c0e5
+ */
+int dmac_channelclose(unsigned int channel)
+{
-+ unsigned int reg_value, count;
++ unsigned int reg_value, count;
+
-+ if (channel >= DMAC_MAX_CHANNELS) {
-+ dma_err("channel larger than total.\n");
-+ return -EINVAL;
-+ }
++ if (channel >= DMAC_MAX_CHANNELS) {
++ dma_err("channel larger than total.\n");
++ return -EINVAL;
++ }
+
-+ dmac_readw(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
++ dmac_readw(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
+
+#define CHANNEL_CLOSE_IMMEDIATE
+#ifdef CHANNEL_CLOSE_IMMEDIATE
-+ reg_value &= 0xFFFFFFFE;
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
++ reg_value &= 0xFFFFFFFE;
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
+#else
-+ reg_value |= DMAC_CONFIGURATIONx_HALT_DMA_ENABLE;
-+ /*ignore incoming dma request*/
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
-+ dmac_readw(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
-+ /*if FIFO is empty*/
-+ while ((reg_value & DMAC_CONFIGURATIONx_ACTIVE)
-+ == DMAC_CONFIGURATIONx_ACTIVE) {
-+ dmac_readw(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
-+ }
-+ reg_value &= 0xFFFFFFFE;
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
++ reg_value |= DMAC_CONFIGURATIONx_HALT_DMA_ENABLE;
++ /*ignore incoming dma request*/
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
++ dmac_readw(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
++ /*if FIFO is empty*/
++ while ((reg_value & DMAC_CONFIGURATIONx_ACTIVE)
++ == DMAC_CONFIGURATIONx_ACTIVE) {
++ dmac_readw(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
++ }
++ reg_value &= 0xFFFFFFFE;
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(channel), reg_value);
+#endif
+
-+ dmac_readw(dma_regbase + DMAC_ENBLDCHNS, reg_value);
-+ reg_value = reg_value & 0x00ff;
-+ count = 0;
-+ while (((reg_value >> channel) & 0x1) == 1) {
-+ dmac_readw(dma_regbase + DMAC_ENBLDCHNS, reg_value);
-+ reg_value = reg_value & 0x00ff;
-+ if (count++ > 10000) {
-+ dma_err("close failure.\n");
-+ return -1;
-+ }
-+ }
++ dmac_readw(dma_regbase + DMAC_ENBLDCHNS, reg_value);
++ reg_value = reg_value & 0x00ff;
++ count = 0;
++ while (((reg_value >> channel) & 0x1) == 1) {
++ dmac_readw(dma_regbase + DMAC_ENBLDCHNS, reg_value);
++ reg_value = reg_value & 0x00ff;
++ if (count++ > 10000) {
++ dma_err("close failure.\n");
++ return -1;
++ }
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_channelclose);
+
@@ -263602,49 +331552,49 @@ index 0000000..7f2c0e5
+ */
+int dmac_start_llim2m(unsigned int channel, unsigned int *pfirst_lli)
+{
-+ unsigned int uwchannel_num;
-+ dmac_lli plli;
-+ unsigned int first_lli;
++ unsigned int uwchannel_num;
++ dmac_lli plli;
++ unsigned int first_lli;
+
-+ if (pfirst_lli == NULL) {
-+ dma_err("Invalidate LLI head!\n");
-+ return -EFAULT;
-+ }
++ if (pfirst_lli == NULL) {
++ dma_err("Invalidate LLI head!\n");
++ return -EFAULT;
++ }
+
-+ uwchannel_num = channel;
-+ if ((uwchannel_num == DMAC_CHANNEL_INVALID) ||
-+ (uwchannel_num > 7)) {
-+ dma_err("failure of DMAC channel allocation in");
-+ dma_err("LLIM2M function,channel=%x!\n ", uwchannel_num);
-+ return -EINVAL;
-+ }
++ uwchannel_num = channel;
++ if ((uwchannel_num == DMAC_CHANNEL_INVALID) ||
++ (uwchannel_num > 7)) {
++ dma_err("failure of DMAC channel allocation in");
++ dma_err("LLIM2M function,channel=%x!\n ", uwchannel_num);
++ return -EINVAL;
++ }
+
-+ memset(&plli, 0, sizeof(plli));
-+ first_lli = (unsigned int)pfirst_lli[1];
-+ dmac_readw(first_lli, plli.src_addr);
-+ dmac_readw(first_lli + 4, plli.dst_addr);
-+ dmac_readw(first_lli + 8, plli.next_lli);
-+ dmac_readw(first_lli + 12, plli.lli_transfer_ctrl);
++ memset(&plli, 0, sizeof(plli));
++ first_lli = (unsigned int)pfirst_lli[1];
++ dmac_readw(first_lli, plli.src_addr);
++ dmac_readw(first_lli + 4, plli.dst_addr);
++ dmac_readw(first_lli + 8, plli.next_lli);
++ dmac_readw(first_lli + 12, plli.lli_transfer_ctrl);
+
-+ dmac_channelclose(uwchannel_num);
-+ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
++ dmac_channelclose(uwchannel_num);
++ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
+
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
-+ DMAC_CxDISABLE);
-+ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num),
-+ (unsigned int)(plli.src_addr));
-+ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num),
-+ (unsigned int)(plli.dst_addr));
-+ dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num),
-+ (unsigned int)(plli.next_lli));
-+ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
-+ (unsigned int)(plli.lli_transfer_ctrl));
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
-+ DMAC_CxCONFIG_LLIM2M);
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
++ DMAC_CxDISABLE);
++ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num),
++ (unsigned int)(plli.src_addr));
++ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num),
++ (unsigned int)(plli.dst_addr));
++ dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num),
++ (unsigned int)(plli.next_lli));
++ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
++ (unsigned int)(plli.lli_transfer_ctrl));
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
++ DMAC_CxCONFIG_LLIM2M);
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_start_llim2m);
+
@@ -263652,50 +331602,50 @@ index 0000000..7f2c0e5
+ * load configuration from LLI for memory and peripheral
+ */
+int dmac_start_llim2p(unsigned int channel, unsigned int *pfirst_lli,
-+ unsigned int uwperipheralid)
++ unsigned int uwperipheralid)
+{
-+ unsigned int uwchannel_num;
-+ dmac_lli plli;
-+ unsigned int first_lli;
-+ unsigned int temp = 0;
++ unsigned int uwchannel_num;
++ dmac_lli plli;
++ unsigned int first_lli;
++ unsigned int temp = 0;
+
-+ if (pfirst_lli == NULL) {
-+ dma_err("Invalidate LLI head!\n");
-+ return -EINVAL;
-+ }
-+ uwchannel_num = channel;
-+ if ((uwchannel_num == DMAC_CHANNEL_INVALID) ||
-+ (uwchannel_num > CHANNEL_NUM)) {
-+ dma_err("failure of DMAC channel allocation in");
-+ dma_err("LLIM2P function, channel=%x!\n ", uwchannel_num);
-+ return -EINVAL;
-+ }
++ if (pfirst_lli == NULL) {
++ dma_err("Invalidate LLI head!\n");
++ return -EINVAL;
++ }
++ uwchannel_num = channel;
++ if ((uwchannel_num == DMAC_CHANNEL_INVALID) ||
++ (uwchannel_num > CHANNEL_NUM)) {
++ dma_err("failure of DMAC channel allocation in");
++ dma_err("LLIM2P function, channel=%x!\n ", uwchannel_num);
++ return -EINVAL;
++ }
+
-+ memset(&plli, 0, sizeof(plli));
-+ first_lli = (unsigned int)pfirst_lli[1];
-+ dmac_readw(first_lli, plli.src_addr);
-+ dmac_readw(first_lli + 4, plli.dst_addr);
-+ dmac_readw(first_lli + 8, plli.next_lli);
-+ dmac_readw(first_lli + 12, plli.lli_transfer_ctrl);
++ memset(&plli, 0, sizeof(plli));
++ first_lli = (unsigned int)pfirst_lli[1];
++ dmac_readw(first_lli, plli.src_addr);
++ dmac_readw(first_lli + 4, plli.dst_addr);
++ dmac_readw(first_lli + 8, plli.next_lli);
++ dmac_readw(first_lli + 12, plli.lli_transfer_ctrl);
+
-+ dmac_channelclose(uwchannel_num);
-+ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
++ dmac_channelclose(uwchannel_num);
++ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
+
-+ dmac_readw(dma_regbase + DMAC_CxCONFIG(uwchannel_num), temp);
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
-+ temp | DMAC_CxDISABLE);
-+ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num),
-+ plli.src_addr);
-+ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num),
-+ plli.dst_addr);
-+ dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num),
-+ plli.next_lli);
-+ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
-+ plli.lli_transfer_ctrl);
++ dmac_readw(dma_regbase + DMAC_CxCONFIG(uwchannel_num), temp);
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
++ temp | DMAC_CxDISABLE);
++ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num),
++ plli.src_addr);
++ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num),
++ plli.dst_addr);
++ dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num),
++ plli.next_lli);
++ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
++ plli.lli_transfer_ctrl);
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_start_llim2p);
+
@@ -263705,57 +331655,57 @@ index 0000000..7f2c0e5
+ * it is necessary to call dmac_channelstart to enable channel
+ */
+int dmac_start_m2p(unsigned int channel, unsigned int memaddr,
-+ unsigned int uwperipheralid, unsigned int uwnumtransfers,
-+ unsigned int next_lli_addr)
++ unsigned int uwperipheralid, unsigned int uwnumtransfers,
++ unsigned int next_lli_addr)
+{
+
-+ unsigned int uwtrans_control = 0;
-+ unsigned int addtmp, tmp;
-+ unsigned int uwdst_addr = 0, uwsrc_addr = 0;
-+ unsigned int uwwidth;
-+ int uwchannel_num;
++ unsigned int uwtrans_control = 0;
++ unsigned int addtmp, tmp;
++ unsigned int uwdst_addr = 0, uwsrc_addr = 0;
++ unsigned int uwwidth;
++ int uwchannel_num;
+
-+ addtmp = memaddr;
++ addtmp = memaddr;
+
-+ if ((uwperipheralid > 15)) {
-+ dma_err("Invalid peripheral id%x\n", uwperipheralid);
-+ return -EINVAL;
-+ }
++ if ((uwperipheralid > 15)) {
++ dma_err("Invalid peripheral id%x\n", uwperipheralid);
++ return -EINVAL;
++ }
+
-+ uwchannel_num = (int)channel;
-+ if ((uwchannel_num == DMAC_CHANNEL_INVALID)
-+ || (uwchannel_num > CHANNEL_NUM) || (uwchannel_num < 0)) {
-+ dma_err("failure alloc\n");
-+ return -EFAULT;
-+ }
++ uwchannel_num = (int)channel;
++ if ((uwchannel_num == DMAC_CHANNEL_INVALID)
++ || (uwchannel_num > CHANNEL_NUM) || (uwchannel_num < 0)) {
++ dma_err("failure alloc\n");
++ return -EFAULT;
++ }
+
-+ /* must modified with different peripheral */
-+ uwwidth = g_peripheral[uwperipheralid].transfer_width;
++ /* must modified with different peripheral */
++ uwwidth = g_peripheral[uwperipheralid].transfer_width;
+
-+ /* check transfer direction *
-+ * even number-->TX, odd number-->RX*/
-+ uwsrc_addr = memaddr;
-+ uwdst_addr = (unsigned int)(g_peripheral[uwperipheralid].peri_addr);
++ /* check transfer direction *
++ * even number-->TX, odd number-->RX*/
++ uwsrc_addr = memaddr;
++ uwdst_addr = (unsigned int)(g_peripheral[uwperipheralid].peri_addr);
+
-+ tmp = uwnumtransfers >> uwwidth;
-+ if (tmp & (~0x0fff)) {
-+ dma_err("Invalidate size%x\n", uwnumtransfers);
-+ return -EINVAL;
-+ }
++ tmp = uwnumtransfers >> uwwidth;
++ if (tmp & (~0x0fff)) {
++ dma_err("Invalidate size%x\n", uwnumtransfers);
++ return -EINVAL;
++ }
+
-+ tmp = tmp & 0xfff;
-+ uwtrans_control = tmp |
-+ (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
-+ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << (unsigned int)uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num), (unsigned int)uwsrc_addr);
-+ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num), (unsigned int)uwdst_addr);
-+ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
-+ (unsigned int)uwtrans_control);
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
-+ (g_peripheral[uwperipheralid].transfer_cfg));
++ tmp = tmp & 0xfff;
++ uwtrans_control = tmp |
++ (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
++ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << (unsigned int)uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num), (unsigned int)uwsrc_addr);
++ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num), (unsigned int)uwdst_addr);
++ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
++ (unsigned int)uwtrans_control);
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
++ (g_peripheral[uwperipheralid].transfer_cfg));
+
-+ return 0;
++ return 0;
+}
+
+/*
@@ -263764,110 +331714,110 @@ index 0000000..7f2c0e5
+ * it is necessary to call dmac_channelstart to enable channel
+ */
+int dmac_start_p2m(unsigned int channel, unsigned int memaddr,
-+ unsigned int uwperipheralid, unsigned int uwnumtransfers,
-+ unsigned int next_lli_addr)
++ unsigned int uwperipheralid, unsigned int uwnumtransfers,
++ unsigned int next_lli_addr)
+{
-+ unsigned int uwtrans_control = 0;
-+ unsigned int addtmp, tmp;
-+ unsigned int uwdst_addr = 0, uwsrc_addr = 0;
-+ unsigned int uwwidth;
-+ int uwchannel_num;
++ unsigned int uwtrans_control = 0;
++ unsigned int addtmp, tmp;
++ unsigned int uwdst_addr = 0, uwsrc_addr = 0;
++ unsigned int uwwidth;
++ int uwchannel_num;
+
-+ addtmp = memaddr;
++ addtmp = memaddr;
+
-+ if ((uwperipheralid > 15)) {
-+ dma_err("Invalid peripheral id%x\n", uwperipheralid);
-+ return -EINVAL;
-+ }
++ if ((uwperipheralid > 15)) {
++ dma_err("Invalid peripheral id%x\n", uwperipheralid);
++ return -EINVAL;
++ }
+
-+ uwchannel_num = (int)channel;
-+ if ((uwchannel_num == DMAC_CHANNEL_INVALID)
-+ || (uwchannel_num > 3) || (uwchannel_num < 0)) {
-+ dma_err("failure alloc\n");
-+ return -EFAULT;
-+ }
++ uwchannel_num = (int)channel;
++ if ((uwchannel_num == DMAC_CHANNEL_INVALID)
++ || (uwchannel_num > 3) || (uwchannel_num < 0)) {
++ dma_err("failure alloc\n");
++ return -EFAULT;
++ }
+
-+ /* must modified with different peripheral */
-+ uwwidth = g_peripheral[uwperipheralid].transfer_width;
++ /* must modified with different peripheral */
++ uwwidth = g_peripheral[uwperipheralid].transfer_width;
+
-+ /* check transfer direction *
-+ * even number-->TX, odd number-->RX*/
-+ uwsrc_addr = (unsigned int)(g_peripheral[uwperipheralid].peri_addr);
-+ uwdst_addr = memaddr;
++ /* check transfer direction *
++ * even number-->TX, odd number-->RX*/
++ uwsrc_addr = (unsigned int)(g_peripheral[uwperipheralid].peri_addr);
++ uwdst_addr = memaddr;
+
-+ tmp = uwnumtransfers >> uwwidth;
-+ if (tmp & (~0x0fff)) {
-+ dma_err("Invalidate size%x\n", uwnumtransfers);
-+ return -EINVAL;
-+ }
++ tmp = uwnumtransfers >> uwwidth;
++ if (tmp & (~0x0fff)) {
++ dma_err("Invalidate size%x\n", uwnumtransfers);
++ return -EINVAL;
++ }
+
-+ tmp = tmp & 0xfff;
-+ uwtrans_control = tmp |
-+ (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
-+ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << (unsigned int)uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
-+ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num),
-+ (unsigned int)uwsrc_addr);
-+ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num),
-+ (unsigned int)uwdst_addr);
-+ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
-+ (unsigned int)uwtrans_control);
-+ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
-+ (g_peripheral[uwperipheralid].transfer_cfg));
++ tmp = tmp & 0xfff;
++ uwtrans_control = tmp |
++ (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
++ dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << (unsigned int)uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
++ dmac_writew(dma_regbase + DMAC_CxSRCADDR(uwchannel_num),
++ (unsigned int)uwsrc_addr);
++ dmac_writew(dma_regbase + DMAC_CxDESTADDR(uwchannel_num),
++ (unsigned int)uwdst_addr);
++ dmac_writew(dma_regbase + DMAC_CxCONTROL(uwchannel_num),
++ (unsigned int)uwtrans_control);
++ dmac_writew(dma_regbase + DMAC_CxCONFIG(uwchannel_num),
++ (g_peripheral[uwperipheralid].transfer_cfg));
+
-+ return 0;
++ return 0;
+}
+
+/*
+ * execute memory to memory dma transfer without LLI
+ */
+int dmac_m2m_transfer(unsigned int source, unsigned int dest,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int ulchnn, dma_size = 0;
-+ unsigned int dma_count, left_size;
++ unsigned int ulchnn, dma_size = 0;
++ unsigned int dma_count, left_size;
+
-+ left_size = length;
-+ dma_count = 0;
-+ ulchnn = dmac_channel_allocate(NULL);
++ left_size = length;
++ dma_count = 0;
++ ulchnn = dmac_channel_allocate(NULL);
+
-+ ulchnn = 2;
++ ulchnn = 2;
+
-+ dma_err("use channel %d\n", ulchnn);
++ dma_err("use channel %d\n", ulchnn);
+
-+ while ((left_size >> 2) >= 0xffc) {
-+ dma_size = 0xffc;
-+ left_size -= (dma_size << 2);
-+ dma_err("left_size is %x.", left_size);
-+ dmac_start_m2m(ulchnn, (unsigned int)(source
-+ + dma_count * (dma_size << 2)),
-+ (unsigned int)(dest + dma_count * (dma_size << 2)),
-+ (dma_size << 2));
-+ if (dmac_channelstart(ulchnn) != 0) {
-+ dma_err("start channel error...\n");
-+ return -1;
-+ }
++ while ((left_size >> 2) >= 0xffc) {
++ dma_size = 0xffc;
++ left_size -= (dma_size << 2);
++ dma_err("left_size is %x.", left_size);
++ dmac_start_m2m(ulchnn, (unsigned int)(source
++ + dma_count * (dma_size << 2)),
++ (unsigned int)(dest + dma_count * (dma_size << 2)),
++ (dma_size << 2));
++ if (dmac_channelstart(ulchnn) != 0) {
++ dma_err("start channel error...\n");
++ return -1;
++ }
+
-+ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
-+ dma_err("dma transfer error...\n");
-+ return -1;
-+ }
++ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
++ dma_err("dma transfer error...\n");
++ return -1;
++ }
+
-+ dma_count++;
-+ }
++ dma_count++;
++ }
+
-+ dmac_start_m2m(ulchnn, (source + dma_count * (dma_size << 2)),
-+ (dest + dma_count * (dma_size << 2)), (left_size << 2));
++ dmac_start_m2m(ulchnn, (source + dma_count * (dma_size << 2)),
++ (dest + dma_count * (dma_size << 2)), (left_size << 2));
+
-+ if (dmac_channelstart(ulchnn) != 0) {
-+ return -1;
-+ }
++ if (dmac_channelstart(ulchnn) != 0) {
++ return -1;
++ }
+
-+ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
-+ return -1;
-+ }
++ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
++ return -1;
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_m2m_transfer);
+
@@ -263875,116 +331825,116 @@ index 0000000..7f2c0e5
+ * execute memory to peripheral dma transfer without LLI
+ */
+int dmac_m2p_transfer(unsigned int memaddr, unsigned int uwperipheralid,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int ulchnn, dma_size = 0;
-+ unsigned int dma_count, left_size;
-+ unsigned int uwwidth;
++ unsigned int ulchnn, dma_size = 0;
++ unsigned int dma_count, left_size;
++ unsigned int uwwidth;
+
-+ left_size = length;
-+ dma_count = 0;
++ left_size = length;
++ dma_count = 0;
+
-+ ulchnn = dmac_channel_allocate(NULL);
-+ if (ulchnn == DMAC_CHANNEL_INVALID) {
-+ return -1;
-+ }
++ ulchnn = dmac_channel_allocate(NULL);
++ if (ulchnn == DMAC_CHANNEL_INVALID) {
++ return -1;
++ }
+
-+ uwwidth = g_peripheral[uwperipheralid].transfer_width;
++ uwwidth = g_peripheral[uwperipheralid].transfer_width;
+
-+ while ((left_size >> uwwidth) >= 0xffc) {
-+ dma_size = 0xffc;
-+ left_size -= (dma_size << uwwidth);
++ while ((left_size >> uwwidth) >= 0xffc) {
++ dma_size = 0xffc;
++ left_size -= (dma_size << uwwidth);
+
-+ if (dmac_start_m2p(ulchnn,
-+ (unsigned int)(memaddr + dma_count * dma_size),
-+ uwperipheralid, (dma_size << uwwidth), 0) < 0) {
-+ return -1;
-+ }
++ if (dmac_start_m2p(ulchnn,
++ (unsigned int)(memaddr + dma_count * dma_size),
++ uwperipheralid, (dma_size << uwwidth), 0) < 0) {
++ return -1;
++ }
+
-+ if (dmac_channelstart(ulchnn) != 0) {
-+ return -1;
-+ }
++ if (dmac_channelstart(ulchnn) != 0) {
++ return -1;
++ }
+
-+ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
-+ dmac_channel_free(ulchnn);
-+ return -1;
-+ }
++ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
++ dmac_channel_free(ulchnn);
++ return -1;
++ }
+
-+ dma_count++;
-+ }
++ dma_count++;
++ }
+
-+ pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr
-+ + dma_count * dma_size));
++ pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr
++ + dma_count * dma_size));
+
-+ if (dmac_start_m2p(ulchnn,
-+ (unsigned int)(memaddr + dma_count * dma_size),
-+ uwperipheralid, left_size, 0) < 0) {
-+ return -1;
-+ }
++ if (dmac_start_m2p(ulchnn,
++ (unsigned int)(memaddr + dma_count * dma_size),
++ uwperipheralid, left_size, 0) < 0) {
++ return -1;
++ }
+
-+ if (dmac_channelstart(ulchnn) != 0) {
-+ return -1;
-+ }
++ if (dmac_channelstart(ulchnn) != 0) {
++ return -1;
++ }
+
-+ return ulchnn;
++ return ulchnn;
+}
+
+/*
+ * execute memory to peripheral dma transfer without LLI
+ */
+int dmac_p2m_transfer(unsigned int memaddr, unsigned int uwperipheralid,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int ulchnn, dma_size = 0;
-+ unsigned int dma_count, left_size;
-+ unsigned int uwwidth;
++ unsigned int ulchnn, dma_size = 0;
++ unsigned int dma_count, left_size;
++ unsigned int uwwidth;
+
-+ left_size = length;
-+ dma_count = 0;
++ left_size = length;
++ dma_count = 0;
+
-+ ulchnn = dmac_channel_allocate(NULL);
-+ if (ulchnn == DMAC_CHANNEL_INVALID) {
-+ return -1;
-+ }
++ ulchnn = dmac_channel_allocate(NULL);
++ if (ulchnn == DMAC_CHANNEL_INVALID) {
++ return -1;
++ }
+
-+ uwwidth = g_peripheral[uwperipheralid].transfer_width;
++ uwwidth = g_peripheral[uwperipheralid].transfer_width;
+
-+ while ((left_size >> uwwidth) >= 0xffc) {
-+ dma_size = 0xffc;
-+ left_size -= (dma_size << uwwidth);
++ while ((left_size >> uwwidth) >= 0xffc) {
++ dma_size = 0xffc;
++ left_size -= (dma_size << uwwidth);
+
-+ if (dmac_start_p2m(ulchnn,
-+ (unsigned int)(memaddr + dma_count * dma_size),
-+ uwperipheralid, (dma_size << uwwidth), 0) < 0) {
-+ return -1;
-+ }
++ if (dmac_start_p2m(ulchnn,
++ (unsigned int)(memaddr + dma_count * dma_size),
++ uwperipheralid, (dma_size << uwwidth), 0) < 0) {
++ return -1;
++ }
+
-+ if (dmac_channelstart(ulchnn) != 0) {
-+ return -1;
-+ }
++ if (dmac_channelstart(ulchnn) != 0) {
++ return -1;
++ }
+
-+ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
-+ dmac_channel_free(ulchnn);
-+ return -1;
-+ }
++ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
++ dmac_channel_free(ulchnn);
++ return -1;
++ }
+
-+ dma_count++;
-+ }
++ dma_count++;
++ }
+
-+ pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr
-+ + dma_count * dma_size));
++ pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr
++ + dma_count * dma_size));
+
-+ if (dmac_start_p2m(ulchnn,
-+ (unsigned int)(memaddr + dma_count * dma_size),
-+ uwperipheralid, left_size, 0) < 0) {
-+ return -1;
-+ }
++ if (dmac_start_p2m(ulchnn,
++ (unsigned int)(memaddr + dma_count * dma_size),
++ uwperipheralid, left_size, 0) < 0) {
++ return -1;
++ }
+
-+ if (dmac_channelstart(ulchnn) != 0) {
-+ return -1;
-+ }
++ if (dmac_channelstart(ulchnn) != 0) {
++ return -1;
++ }
+
-+ return ulchnn;
++ return ulchnn;
+}
+
+/*
@@ -263996,78 +331946,78 @@ index 0000000..7f2c0e5
+ * @num
+ * */
+int do_dma_llim2m_isp(unsigned int *source,
-+ unsigned int *dest,
-+ unsigned int *length,
-+ unsigned int num)
++ unsigned int *dest,
++ unsigned int *length,
++ unsigned int num)
+{
-+ unsigned int chnn;
-+ int ret = 0;
++ unsigned int chnn;
++ int ret = 0;
+
-+ /* the dma channel is default using 2 */
-+ chnn = 2;
++ /* the dma channel is default using 2 */
++ chnn = 2;
+
-+ ret = dmac_buildllim2m_isp(pllihead, source, dest, length, num);
++ ret = dmac_buildllim2m_isp(pllihead, source, dest, length, num);
+
-+ if (ret) {
-+ dma_err("build lli error...\n");
-+ return -1;
-+ }
++ if (ret) {
++ dma_err("build lli error...\n");
++ return -1;
++ }
+
-+ /* dmac_register_isr(chnn, dmac_channel_close); */
-+ ret = dmac_start_llim2m(chnn, pllihead);
-+ if (ret) {
-+ return -1;
-+ }
++ /* dmac_register_isr(chnn, dmac_channel_close); */
++ ret = dmac_start_llim2m(chnn, pllihead);
++ if (ret) {
++ return -1;
++ }
+
-+ if (dmac_channelstart(chnn) != 0) {
-+ dma_err("start channel error...\n");
-+ return -1;
-+ }
++ if (dmac_channelstart(chnn) != 0) {
++ dma_err("start channel error...\n");
++ return -1;
++ }
+
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(do_dma_llim2m_isp);
+
+int do_dma_m2p(unsigned int memaddr, unsigned int peripheral_addr,
-+ unsigned int length)
++ unsigned int length)
+{
-+ int ret = 0;
-+ int uwperipheralid;
++ int ret = 0;
++ int uwperipheralid;
+
-+ uwperipheralid = dmac_check_request(peripheral_addr, TX);
-+ if (uwperipheralid < 0) {
-+ dma_err("m2p:Invalid devaddr\n");
-+ return -1;
-+ }
++ uwperipheralid = dmac_check_request(peripheral_addr, TX);
++ if (uwperipheralid < 0) {
++ dma_err("m2p:Invalid devaddr\n");
++ return -1;
++ }
+
-+ ret = dmac_m2p_transfer(memaddr, uwperipheralid, length);
-+ if (ret == -1) {
-+ dma_err("m2p:trans err\n");
-+ return -1;
-+ }
++ ret = dmac_m2p_transfer(memaddr, uwperipheralid, length);
++ if (ret == -1) {
++ dma_err("m2p:trans err\n");
++ return -1;
++ }
+
-+ return ret;
++ return ret;
+}
+
+int do_dma_p2m(unsigned int memaddr, unsigned int peripheral_addr,
-+ unsigned int length)
++ unsigned int length)
+{
-+ int ret = -1;
-+ int uwperipheralid;
++ int ret = -1;
++ int uwperipheralid;
+
-+ uwperipheralid = dmac_check_request(peripheral_addr, RX);
-+ if (uwperipheralid < 0) {
-+ dma_err("p2m:Invalid devaddr.\n");
-+ return -1;
-+ }
++ uwperipheralid = dmac_check_request(peripheral_addr, RX);
++ if (uwperipheralid < 0) {
++ dma_err("p2m:Invalid devaddr.\n");
++ return -1;
++ }
+
-+ ret = dmac_p2m_transfer(memaddr, uwperipheralid, length);
-+ if (ret == -1) {
-+ dma_err("p2m:trans err\n");
-+ return -1;
-+ }
++ ret = dmac_p2m_transfer(memaddr, uwperipheralid, length);
++ if (ret == -1) {
++ dma_err("p2m:trans err\n");
++ return -1;
++ }
+
-+ return ret;
++ return ret;
+}
+
+/*
@@ -264076,136 +332026,136 @@ index 0000000..7f2c0e5
+ */
+static int hi_dmac_probe(struct platform_device *platdev)
+{
-+ unsigned int i;
-+ struct hidmac_host *dma;
-+ struct resource *res;
-+ int ret;
++ unsigned int i;
++ struct hidmac_host *dma;
++ struct resource *res;
++ int ret;
+
-+ dma = devm_kzalloc(&platdev->dev, sizeof(*dma), GFP_KERNEL);
-+ if (!dma) {
-+ return -ENOMEM;
-+ }
++ dma = devm_kzalloc(&platdev->dev, sizeof(*dma), GFP_KERNEL);
++ if (!dma) {
++ return -ENOMEM;
++ }
+
-+ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&platdev->dev, "no mmio resource\n");
-+ return -ENODEV;
-+ }
++ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&platdev->dev, "no mmio resource\n");
++ return -ENODEV;
++ }
+
-+ dma->regbase = devm_ioremap_resource(&platdev->dev, res);
-+ if (IS_ERR(dma->regbase)) {
-+ return PTR_ERR(dma->regbase);
-+ }
++ dma->regbase = devm_ioremap_resource(&platdev->dev, res);
++ if (IS_ERR(dma->regbase)) {
++ return PTR_ERR(dma->regbase);
++ }
+
-+ dma->clk = devm_clk_get(&platdev->dev, NULL);
-+ if (IS_ERR(dma->clk)) {
-+ return PTR_ERR(dma->clk);
-+ }
++ dma->clk = devm_clk_get(&platdev->dev, NULL);
++ if (IS_ERR(dma->clk)) {
++ return PTR_ERR(dma->clk);
++ }
+
-+ dma->rstc = devm_reset_control_get(&platdev->dev, "dma-reset");
-+ if (IS_ERR(dma->rstc)) {
-+ return PTR_ERR(dma->rstc);
-+ }
++ dma->rstc = devm_reset_control_get(&platdev->dev, "dma-reset");
++ if (IS_ERR(dma->rstc)) {
++ return PTR_ERR(dma->rstc);
++ }
+
-+ dma->irq = platform_get_irq(platdev, 0);
-+ if (unlikely(dma->irq < 0)) {
-+ return -ENODEV;
-+ }
++ dma->irq = platform_get_irq(platdev, 0);
++ if (unlikely(dma->irq < 0)) {
++ return -ENODEV;
++ }
+
-+ dma_regbase = dma->regbase;
++ dma_regbase = dma->regbase;
+
-+ ret = dmac_init(dma);
-+ if (ret) {
-+ return -ENODEV;
-+ }
++ ret = dmac_init(dma);
++ if (ret) {
++ return -ENODEV;
++ }
+
-+ platform_set_drvdata(platdev, dma);
++ platform_set_drvdata(platdev, dma);
+
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ dev_info(&platdev->dev, "hidmac probe!\n");
-+ return ret;
++ dev_info(&platdev->dev, "hidmac probe!\n");
++ return ret;
+}
+
+static int hi_dmac_remove(struct platform_device *platdev)
+{
-+ int i;
-+ struct hidmac_host *dma = platform_get_drvdata(platdev);
++ int i;
++ struct hidmac_host *dma = platform_get_drvdata(platdev);
+
-+ clk_disable_unprepare(dma->clk);
++ clk_disable_unprepare(dma->clk);
+
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ free_dmalli_space(pllihead, 1);
++ free_dmalli_space(pllihead, 1);
+
-+ return 0;
++ return 0;
+}
+
+static int hi_dmac_suspend(struct platform_device *platdev,
-+ pm_message_t state)
++ pm_message_t state)
+{
-+ int i;
-+ struct hidmac_host *dma = platform_get_drvdata(platdev);
++ int i;
++ struct hidmac_host *dma = platform_get_drvdata(platdev);
+
-+ clk_prepare_enable(dma->clk);
++ clk_prepare_enable(dma->clk);
+
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ clk_disable_unprepare(dma->clk);
++ clk_disable_unprepare(dma->clk);
+
-+ return 0;
++ return 0;
+}
+
+static int hi_dmac_resume(struct platform_device *platdev)
+{
-+ int i;
-+ struct hidmac_host *dma = platform_get_drvdata(platdev);
-+ unsigned int tempvalue;
++ int i;
++ struct hidmac_host *dma = platform_get_drvdata(platdev);
++ unsigned int tempvalue;
+
-+ clk_prepare_enable(dma->clk);
-+ reset_control_deassert(dma->rstc);
++ clk_prepare_enable(dma->clk);
++ reset_control_deassert(dma->rstc);
+
-+ dmac_readw(dma->regbase + DMAC_CONFIG, tempvalue);
-+ if (tempvalue == 0) {
-+ dmac_writew(dma->regbase + DMAC_CONFIG,
-+ DMAC_CONFIG_VAL);
-+ dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
-+ dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ dmac_writew(dma->regbase + DMAC_CxCONFIG(i),
-+ DMAC_CxDISABLE);
-+ function[i] = NULL;
-+ }
-+ }
++ dmac_readw(dma->regbase + DMAC_CONFIG, tempvalue);
++ if (tempvalue == 0) {
++ dmac_writew(dma->regbase + DMAC_CONFIG,
++ DMAC_CONFIG_VAL);
++ dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
++ dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ dmac_writew(dma->regbase + DMAC_CxCONFIG(i),
++ DMAC_CxDISABLE);
++ function[i] = NULL;
++ }
++ }
+
-+ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
-+ g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
++ g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static const struct of_device_id hisi_dmac_dt_ids[] = {
-+ { .compatible = "hisilicon,hisi-dmac"},
-+ { /* sentinel */ }
++ { .compatible = "hisilicon,hisi-dmac"},
++ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, hisi_dmac_dt_ids);
+
+static struct platform_driver hisi_dmac_driver = {
-+ .driver = {
-+ .name = "hisi-dmac",
-+ .of_match_table = hisi_dmac_dt_ids,
-+ },
-+ .probe = hi_dmac_probe,
-+ .remove = hi_dmac_remove,
-+ .suspend = hi_dmac_suspend,
-+ .resume = hi_dmac_resume,
++ .driver = {
++ .name = "hisi-dmac",
++ .of_match_table = hisi_dmac_dt_ids,
++ },
++ .probe = hi_dmac_probe,
++ .remove = hi_dmac_remove,
++ .suspend = hi_dmac_suspend,
++ .resume = hi_dmac_resume,
+};
+
+module_platform_driver(hisi_dmac_driver);
@@ -264215,7 +332165,7 @@ index 0000000..7f2c0e5
+MODULE_DESCRIPTION("HiSilicon DMA Controller driver");
diff --git a/drivers/hidmac/hi_pl08x.h b/drivers/hidmac/hi_pl08x.h
new file mode 100644
-index 0000000..1427d8a
+index 0000000..06cb5d3
--- /dev/null
+++ b/drivers/hidmac/hi_pl08x.h
@@ -0,0 +1,91 @@
@@ -264289,21 +332239,21 @@ index 0000000..1427d8a
+
+/*DMAC peripheral structure*/
+typedef struct dmac_peripheral {
-+ /* peripherial ID*/
-+ unsigned int peri_id;
-+ /*peripheral data register address*/
-+ unsigned int peri_addr;
-+ /*default channel control word*/
-+ unsigned int transfer_ctrl;
-+ /*default channel configuration word*/
-+ unsigned int transfer_cfg;
-+ /*default channel configuration word*/
-+ unsigned int transfer_width;
++ /* peripherial ID*/
++ unsigned int peri_id;
++ /*peripheral data register address*/
++ unsigned int peri_addr;
++ /*default channel control word*/
++ unsigned int transfer_ctrl;
++ /*default channel configuration word*/
++ unsigned int transfer_cfg;
++ /*default channel configuration word*/
++ unsigned int transfer_width;
+} dmac_peripheral;
+
+typedef struct mem_addr {
-+ unsigned int addr_base;
-+ unsigned int size;
++ unsigned int addr_base;
++ unsigned int size;
+} mem_addr;
+
+typedef unsigned int dma_addr_t;
@@ -264312,7 +332262,7 @@ index 0000000..1427d8a
+#endif /* End of #ifndef __HI_INC_ECSDMACC_H__ */
diff --git a/drivers/hidmac/hidmac_hi3516a.h b/drivers/hidmac/hidmac_hi3516a.h
new file mode 100644
-index 0000000..6bfd881
+index 0000000..9d0fc94
--- /dev/null
+++ b/drivers/hidmac/hidmac_hi3516a.h
@@ -0,0 +1,176 @@
@@ -264444,57 +332394,57 @@ index 0000000..6bfd881
+ * DREQ, FIFO, CONTROL, CONFIG, BITWIDTH
+ */
+dmac_peripheral g_peripheral[DMAC_MAX_PERIPHERALS] = {
-+ /* DREQ, FIFO, CONTROL, CONFIG, WIDTH */
-+ /*periphal 0: I2C0/I2C1 RX*/
-+ { 0, I2C0_DATA_REG, 0x99000000, 0x1000, PERI_8BIT_MODE},
-+ /*periphal 1: I2C0/I2C1 TX*/
-+ { 1, I2C0_DATA_REG, 0x96000000, 0x0840, PERI_8BIT_MODE},
-+ /*periphal 2: I2C1/I2C2 RX*/
-+ { 2, I2C1_DATA_REG, 0x99000000, 0x1004, PERI_8BIT_MODE}, /* 8bit width */
-+ /*periphal 3: I2C1/I2C2 TX*/
-+ { 3, I2C1_DATA_REG, 0x96000000, 0x08c0, PERI_8BIT_MODE}, /* 8bit width */
++ /* DREQ, FIFO, CONTROL, CONFIG, WIDTH */
++ /*periphal 0: I2C0/I2C1 RX*/
++ { 0, I2C0_DATA_REG, 0x99000000, 0x1000, PERI_8BIT_MODE},
++ /*periphal 1: I2C0/I2C1 TX*/
++ { 1, I2C0_DATA_REG, 0x96000000, 0x0840, PERI_8BIT_MODE},
++ /*periphal 2: I2C1/I2C2 RX*/
++ { 2, I2C1_DATA_REG, 0x99000000, 0x1004, PERI_8BIT_MODE}, /* 8bit width */
++ /*periphal 3: I2C1/I2C2 TX*/
++ { 3, I2C1_DATA_REG, 0x96000000, 0x08c0, PERI_8BIT_MODE}, /* 8bit width */
+
-+ /*periphal 4: UART0 RX*/
-+ { 4, UART0_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (4 << 1), PERI_8BIT_MODE},
++ /*periphal 4: UART0 RX*/
++ { 4, UART0_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (4 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 5: UART0 TX*/
-+ { 5, UART0_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (5 << 1), PERI_8BIT_MODE},
++ /*periphal 5: UART0 TX*/
++ { 5, UART0_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (5 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 6: UART1 RX*/
-+ { 6, UART1_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (6 << 1), PERI_8BIT_MODE},
++ /*periphal 6: UART1 RX*/
++ { 6, UART1_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (6 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 7: UART1 TX*/
-+ { 7, UART1_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (7 << 1), PERI_8BIT_MODE},
++ /*periphal 7: UART1 TX*/
++ { 7, UART1_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (7 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 8: UART2 RX*/
-+ { 8, UART2_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (8 << 1), PERI_8BIT_MODE},
++ /*periphal 8: UART2 RX*/
++ { 8, UART2_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (8 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 9: UART2 TX*/
-+ { 9, UART2_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (9 << 1), PERI_8BIT_MODE},
++ /*periphal 9: UART2 TX*/
++ { 9, UART2_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (9 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 10: UART3 RX*/
-+ { 10, UART3_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (10 << 1), PERI_8BIT_MODE},
++ /*periphal 10: UART3 RX*/
++ { 10, UART3_DATA_REG, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (10 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 11: UART0 TX*/
-+ { 11, UART3_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (11 << 1), PERI_8BIT_MODE},
++ /*periphal 11: UART0 TX*/
++ { 11, UART3_DATA_REG, DMAC_CxCONTROL_LLIM2P, DMAC_CxCONFIG_M2P | (11 << 1), PERI_8BIT_MODE},
+
-+ /*periphal 12: SSP1 RX*/
-+ { 12, 0, 0, 0, 0},
++ /*periphal 12: SSP1 RX*/
++ { 12, 0, 0, 0, 0},
+
-+ /*periphal 13: SSP1 TX*/
-+ { 13, 0, 0, 0, 0},
++ /*periphal 13: SSP1 TX*/
++ { 13, 0, 0, 0, 0},
+
-+ /*periphal 14: SSP0 RX*/
-+ { 14, 0, 0, 0, 0},
++ /*periphal 14: SSP0 RX*/
++ { 14, 0, 0, 0, 0},
+
-+ /*periphal 15: SSP0 TX*/
-+ { 15, 0, 0, 0, 0},
++ /*periphal 15: SSP0 TX*/
++ { 15, 0, 0, 0, 0},
+};
+
+#endif
diff --git a/drivers/hidmac/hidmac_hi3518ev20x.h b/drivers/hidmac/hidmac_hi3518ev20x.h
new file mode 100644
-index 0000000..f67dc3c
+index 0000000..0e6071c
--- /dev/null
+++ b/drivers/hidmac/hidmac_hi3518ev20x.h
@@ -0,0 +1,168 @@
@@ -264617,58 +332567,58 @@ index 0000000..f67dc3c
+ * DREQ, FIFO, CONTROL, CONFIG, BITWIDTH
+ */
+dmac_peripheral g_peripheral[DMAC_MAX_PERIPHERALS] = {
-+ /* periphal 0: I2C0 RX, 8bit width */
-+ {0, I2C0_DATA_REG, 0x99000000, 0x1000, 0},
++ /* periphal 0: I2C0 RX, 8bit width */
++ {0, I2C0_DATA_REG, 0x99000000, 0x1000, 0},
+
-+ /* periphal 1: I2C0 TX, 8bit width */
-+ {1, I2C0_DATA_REG, 0x96000000, 0x0840, 0},
++ /* periphal 1: I2C0 TX, 8bit width */
++ {1, I2C0_DATA_REG, 0x96000000, 0x0840, 0},
+
-+ /*periphal 2: I2C1 RX, 8bit width */
-+ {2, I2C1_DATA_REG, 0x99000000, 0x1004, 0},
++ /*periphal 2: I2C1 RX, 8bit width */
++ {2, I2C1_DATA_REG, 0x99000000, 0x1004, 0},
+
-+ /*periphal 3: I2C1 TX, 8bit width */
-+ {3, I2C1_DATA_REG, 0x96000000, 0x08c0, 0},
++ /*periphal 3: I2C1 TX, 8bit width */
++ {3, I2C1_DATA_REG, 0x96000000, 0x08c0, 0},
+
-+ /*periphal 4: UART0 RX, 8bit width */
-+ {4, UART0_DATA_REG, 0x99000000, 0xd008, 0},
++ /*periphal 4: UART0 RX, 8bit width */
++ {4, UART0_DATA_REG, 0x99000000, 0xd008, 0},
+
-+ /*periphal 5: UART0 TX, 8bit width */
-+ {5, UART0_DATA_REG, 0x96000000, 0xc940, 0},
++ /*periphal 5: UART0 TX, 8bit width */
++ {5, UART0_DATA_REG, 0x96000000, 0xc940, 0},
+
-+ /*periphal 6: UART1 RX, 8bit width */
-+ {6, UART1_DATA_REG, 0x99000000, 0xd00c, 0},
++ /*periphal 6: UART1 RX, 8bit width */
++ {6, UART1_DATA_REG, 0x99000000, 0xd00c, 0},
+
-+ /*periphal 7: UART1 TX, 8bit width */
-+ {7, UART1_DATA_REG, 0x96000000, 0xc9c0, 0},
++ /*periphal 7: UART1 TX, 8bit width */
++ {7, UART1_DATA_REG, 0x96000000, 0xc9c0, 0},
+
-+ /*periphal 8: UART2 RX, 8bit width */
-+ {8, UART2_DATA_REG, 0x99000000, 0xd010, 0},
++ /*periphal 8: UART2 RX, 8bit width */
++ {8, UART2_DATA_REG, 0x99000000, 0xd010, 0},
+
-+ /*periphal 9: UART2 TX, 8bit width */
-+ {9, UART2_DATA_REG, 0x96000000, 0xca40, 0},
++ /*periphal 9: UART2 TX, 8bit width */
++ {9, UART2_DATA_REG, 0x96000000, 0xca40, 0},
+
-+ /*periphal 10: I2C2 RX, 8bit width */
-+ {10, I2C2_DATA_REG, 0x99000000, 0x1014, 0},
++ /*periphal 10: I2C2 RX, 8bit width */
++ {10, I2C2_DATA_REG, 0x99000000, 0x1014, 0},
+
-+ /*periphal 11: I2C2 TX, 8bit width */
-+ {11, I2C2_DATA_REG, 0x96000000, 0x0ac0, 0},
++ /*periphal 11: I2C2 TX, 8bit width */
++ {11, I2C2_DATA_REG, 0x96000000, 0x0ac0, 0},
+
-+ /*periphal 12: SSP1 RX, 8bit width */
-+ {12, 0, 0x99000000, 0xd018, 0},
++ /*periphal 12: SSP1 RX, 8bit width */
++ {12, 0, 0x99000000, 0xd018, 0},
+
-+ /*periphal 13: SSP1 TX, 8bit width */
-+ {13, 0, 0x96000000, 0xcb40, 0},
++ /*periphal 13: SSP1 TX, 8bit width */
++ {13, 0, 0x96000000, 0xcb40, 0},
+
-+ /*periphal 14: SSP0 RX, 8bit width */
-+ {14, 0, 0x99000000, 0xd01c, 0},
++ /*periphal 14: SSP0 RX, 8bit width */
++ {14, 0, 0x99000000, 0xd01c, 0},
+
-+ /*periphal 15: SSP0 TX, 8bit width */
-+ {15, 0, 0x96000000, 0xcbc0, 0},
++ /*periphal 15: SSP0 TX, 8bit width */
++ {15, 0, 0x96000000, 0xcbc0, 0},
+};
+#endif
diff --git a/drivers/hidmac/hidmac_hi3521a.h b/drivers/hidmac/hidmac_hi3521a.h
new file mode 100644
-index 0000000..234bae8
+index 0000000..0d045b0
--- /dev/null
+++ b/drivers/hidmac/hidmac_hi3521a.h
@@ -0,0 +1,152 @@
@@ -264792,41 +332742,41 @@ index 0000000..234bae8
+ * Request ID, peripheral data register address, Control, Config, width
+ */
+dmac_peripheral g_peripheral[DMAC_MAX_PERIPHERALS] = {
-+ /* Request 0: UART0 Rx 8bit width */
-+ { 0, UART0_DATA_REG, 0x99000000, 0xd000, 0},
++ /* Request 0: UART0 Rx 8bit width */
++ { 0, UART0_DATA_REG, 0x99000000, 0xd000, 0},
+
-+ /* Request 1: UART0 Tx 8bit width */
-+ { 1, UART0_DATA_REG, 0x96000000, 0xc840, 0},
++ /* Request 1: UART0 Tx 8bit width */
++ { 1, UART0_DATA_REG, 0x96000000, 0xc840, 0},
+
-+ /* Request 2: UART1 Rx 8bit width */
-+ { 2, UART1_DATA_REG, 0x99000000, 0xd004, 0},
++ /* Request 2: UART1 Rx 8bit width */
++ { 2, UART1_DATA_REG, 0x99000000, 0xd004, 0},
+
-+ /* Request 3: UART1 Tx 8bit width */
-+ { 3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0},
++ /* Request 3: UART1 Tx 8bit width */
++ { 3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0},
+
-+ /* Request 4: UART2 Rx 8bit width */
-+ { 4, UART2_DATA_REG, 0x99000000, 0xd008, 0},
++ /* Request 4: UART2 Rx 8bit width */
++ { 4, UART2_DATA_REG, 0x99000000, 0xd008, 0},
+
-+ /* Request 5: UART2 Tx 8bit width */
-+ { 5, UART2_DATA_REG, 0x96000000, 0xc940, 0},
++ /* Request 5: UART2 Tx 8bit width */
++ { 5, UART2_DATA_REG, 0x96000000, 0xc940, 0},
+
-+ /* Request 6: SSP Rx */
-+ { 6, SSP_DATA_REG, 0x99000000, 0xd00c, 0},
++ /* Request 6: SSP Rx */
++ { 6, SSP_DATA_REG, 0x99000000, 0xd00c, 0},
+
-+ /* Request 7: SSP Tx */
-+ { 7, SSP_DATA_REG, 0x96000000, 0xc9c0, 0},
++ /* Request 7: SSP Tx */
++ { 7, SSP_DATA_REG, 0x96000000, 0xc9c0, 0},
+
-+ /* Request 8: I2C Rx 8bit width */
-+ { 8, I2C_DATA_REG, 0x99000000, 0x1010, 0},
++ /* Request 8: I2C Rx 8bit width */
++ { 8, I2C_DATA_REG, 0x99000000, 0x1010, 0},
+
-+ /* Request 9: I2C Tx 8bit width */
-+ { 9, I2C_DATA_REG, 0x96000000, 0x0a40, 0},
++ /* Request 9: I2C Tx 8bit width */
++ { 9, I2C_DATA_REG, 0x96000000, 0x0a40, 0},
+};
+#endif /* End of __HI_DMAC_HI3521A_H__ */
+
diff --git a/drivers/hidmac/hidmac_hi3531a.h b/drivers/hidmac/hidmac_hi3531a.h
new file mode 100644
-index 0000000..1d3fe73
+index 0000000..441f17e
--- /dev/null
+++ b/drivers/hidmac/hidmac_hi3531a.h
@@ -0,0 +1,167 @@
@@ -264953,53 +332903,53 @@ index 0000000..1d3fe73
+ * Request ID, peripheral data register address, Control, Config, width
+ */
+dmac_peripheral g_peripheral[DMAC_MAX_PERIPHERALS] = {
-+ /* Request 0: UART0 Rx 8bit width */
-+ { 0, UART0_DATA_REG, 0x99000000, 0xd000, 0},
++ /* Request 0: UART0 Rx 8bit width */
++ { 0, UART0_DATA_REG, 0x99000000, 0xd000, 0},
+
-+ /* Request 1: UART0 Tx 8bit width */
-+ { 1, UART0_DATA_REG, 0x96000000, 0xc840, 0},
++ /* Request 1: UART0 Tx 8bit width */
++ { 1, UART0_DATA_REG, 0x96000000, 0xc840, 0},
+
-+ /* Request 2: UART1 Rx 8bit width */
-+ { 2, UART1_DATA_REG, 0x99000000, 0xd004, 0},
++ /* Request 2: UART1 Rx 8bit width */
++ { 2, UART1_DATA_REG, 0x99000000, 0xd004, 0},
+
-+ /* Request 3: UART1 Tx 8bit width */
-+ { 3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0},
++ /* Request 3: UART1 Tx 8bit width */
++ { 3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0},
+
-+ /* Request 4: UART2 Rx 8bit width */
-+ { 4, UART2_DATA_REG, 0x99000000, 0xd008, 0},
++ /* Request 4: UART2 Rx 8bit width */
++ { 4, UART2_DATA_REG, 0x99000000, 0xd008, 0},
+
-+ /* Request 5: UART2 Tx 8bit width */
-+ { 5, UART2_DATA_REG, 0x96000000, 0xc940, 0},
++ /* Request 5: UART2 Tx 8bit width */
++ { 5, UART2_DATA_REG, 0x96000000, 0xc940, 0},
+
-+ /* Request 6: SSP Rx */
-+ { 6, SSP_DATA_REG, 0x99000000, 0xd00c, 0},
++ /* Request 6: SSP Rx */
++ { 6, SSP_DATA_REG, 0x99000000, 0xd00c, 0},
+
-+ /* Request 7: SSP Tx */
-+ { 7, SSP_DATA_REG, 0x96000000, 0xc9c0, 0},
++ /* Request 7: SSP Tx */
++ { 7, SSP_DATA_REG, 0x96000000, 0xc9c0, 0},
+
-+ /* Request 8: I2C0 Rx 8bit width */
-+ { 8, I2C0_DATA_REG, 0x99000000, 0x1010, 0},
++ /* Request 8: I2C0 Rx 8bit width */
++ { 8, I2C0_DATA_REG, 0x99000000, 0x1010, 0},
+
-+ /* Request 9: I2C0 Tx 8bit width */
-+ { 9, I2C0_DATA_REG, 0x96000000, 0x0a40, 0},
++ /* Request 9: I2C0 Tx 8bit width */
++ { 9, I2C0_DATA_REG, 0x96000000, 0x0a40, 0},
+
-+ /* Request 10: UART3 Rx 8bit width */
-+ { 10, UART3_DATA_REG, 0x99000000, 0xd014, 0},
++ /* Request 10: UART3 Rx 8bit width */
++ { 10, UART3_DATA_REG, 0x99000000, 0xd014, 0},
+
-+ /* Request 11: UART3 Tx 8bit width */
-+ { 11, UART3_DATA_REG, 0x96000000, 0xcac0, 0},
++ /* Request 11: UART3 Tx 8bit width */
++ { 11, UART3_DATA_REG, 0x96000000, 0xcac0, 0},
+
-+ /* Request 12: I2C1 Rx 8bit width */
-+ { 12, I2C1_DATA_REG, 0x99000000, 0x1018, 0},
++ /* Request 12: I2C1 Rx 8bit width */
++ { 12, I2C1_DATA_REG, 0x99000000, 0x1018, 0},
+
-+ /* Request 13: I2C0 Tx 8bit width */
-+ { 13, I2C1_DATA_REG, 0x96000000, 0x0b40, 0},
++ /* Request 13: I2C0 Tx 8bit width */
++ { 13, I2C1_DATA_REG, 0x96000000, 0x0b40, 0},
+};
+#endif
+
diff --git a/drivers/hidmac/hidmac_hi3536dv100.h b/drivers/hidmac/hidmac_hi3536dv100.h
new file mode 100644
-index 0000000..3368162
+index 0000000..ccc1e46
--- /dev/null
+++ b/drivers/hidmac/hidmac_hi3536dv100.h
@@ -0,0 +1,131 @@
@@ -265108,35 +333058,35 @@ index 0000000..3368162
+extern int g_channel_status[CHANNEL_NUM];
+
+dmac_peripheral g_peripheral[DMAC_MAX_PERIPHERALS] = {
-+ /*periphal 0: UART0 RX, 8bit width */
-+ {0, UART0_DATA_REG, 0x99000000, 0xd000, 0},
++ /*periphal 0: UART0 RX, 8bit width */
++ {0, UART0_DATA_REG, 0x99000000, 0xd000, 0},
+
-+ /*periphal 1: UART0 TX, 8bit width */
-+ {1, UART0_DATA_REG, 0x96000000, 0xc840, 0},
++ /*periphal 1: UART0 TX, 8bit width */
++ {1, UART0_DATA_REG, 0x96000000, 0xc840, 0},
+
-+ /*periphal 2: UART1 RX, 8bit width */
-+ {2, UART1_DATA_REG, 0x99000000, 0xd004, 0},
++ /*periphal 2: UART1 RX, 8bit width */
++ {2, UART1_DATA_REG, 0x99000000, 0xd004, 0},
+
-+ /*periphal 3: UART1 TX, 8bit width */
-+ {3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0},
++ /*periphal 3: UART1 TX, 8bit width */
++ {3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0},
+
-+ /*periphal 4: UART2 RX, 8bit width */
-+ {4, UART2_DATA_REG, 0x99000000, 0xd008, 0},
++ /*periphal 4: UART2 RX, 8bit width */
++ {4, UART2_DATA_REG, 0x99000000, 0xd008, 0},
+
-+ /*periphal 5: UART2 TX, 8bit width */
-+ {5, UART2_DATA_REG, 0x96000000, 0xc940, 0},
++ /*periphal 5: UART2 TX, 8bit width */
++ {5, UART2_DATA_REG, 0x96000000, 0xc940, 0},
+
-+ /*periphal 6: I2C0 RX, 8bit width */
-+ {6, I2C0_DATA_RXF, 0x99000000, 0x100c, 0},
++ /*periphal 6: I2C0 RX, 8bit width */
++ {6, I2C0_DATA_RXF, 0x99000000, 0x100c, 0},
+
-+ /*periphal 7: I2C0 TX, 8bit width */
-+ {7, I2C0_DATA_TXF, 0x96000000, 0x9c0, 0},
++ /*periphal 7: I2C0 TX, 8bit width */
++ {7, I2C0_DATA_TXF, 0x96000000, 0x9c0, 0},
+};
+
+#endif
diff --git a/drivers/hiedmac/Kconfig b/drivers/hiedmac/Kconfig
new file mode 100644
-index 0000000..01d7186
+index 0000000..d9011f0
--- /dev/null
+++ b/drivers/hiedmac/Kconfig
@@ -0,0 +1,23 @@
@@ -265146,7 +333096,7 @@ index 0000000..01d7186
+
+config HIEDMAC
+ tristate "Hisilicon EDMAC Controller support"
-+ depends on (ARCH_HI3559AV100 || ARCH_HI3519AV100 || ARCH_HI3556AV100) || ((ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200) && !HIEDMACV310) || ((ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV200) && !HIEDMACV310)
++ depends on (ARCH_HI3559AV100 || ARCH_HI3569V100 || ARCH_HI3519AV100 || ARCH_HI3556AV100) || ((ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200 || ARCH_HI3562V100 || ARCH_HI3566V100) && !HIEDMACV310) || ((ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV200) && !HIEDMACV310)
+ help
+ The Direction Memory Access(EDMA) is a high-speed data transfer
+ operation. It supports data read/write between peripherals and
@@ -265175,7 +333125,7 @@ index 0000000..a1b4b8b
+obj-$(CONFIG_HIEDMAC) += hiedmacv310.o
diff --git a/drivers/hiedmac/hiedma_hi3516cv500.h b/drivers/hiedmac/hiedma_hi3516cv500.h
new file mode 100644
-index 0000000..88d3398
+index 0000000..7596326
--- /dev/null
+++ b/drivers/hiedmac/hiedma_hi3516cv500.h
@@ -0,0 +1,107 @@
@@ -265252,43 +333202,43 @@ index 0000000..88d3398
+#define EDMAC_RX 1
+
+edmac_peripheral g_peripheral[EDMAC_MAX_PERIPHERALS] = {
-+ {0, I2C0_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {1, I2C0_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {2, I2C1_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {3, I2C1_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {4, I2C2_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {5, I2C2_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {6, I2C3_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {7, I2C3_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {8, I2C4_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {9, I2C4_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {10, I2C5_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {11, I2C5_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {12, I2C6_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {13, I2C6_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {14, I2C7_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {15, I2C7_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {16, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {17, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {18, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {19, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {20, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {21, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {22, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {23, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {24, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {25, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {26, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {27, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {28, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {29, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {30, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {31, 0, DMAC_NOT_USE, 0, 0, 0},
++ {0, I2C0_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {1, I2C0_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {2, I2C1_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {3, I2C1_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {4, I2C2_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {5, I2C2_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {6, I2C3_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {7, I2C3_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {8, I2C4_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {9, I2C4_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {10, I2C5_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {11, I2C5_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {12, I2C6_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {13, I2C6_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {14, I2C7_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {15, I2C7_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {16, 0, DMAC_NOT_USE, 0, 0, 0},
++ {17, 0, DMAC_NOT_USE, 0, 0, 0},
++ {18, 0, DMAC_NOT_USE, 0, 0, 0},
++ {19, 0, DMAC_NOT_USE, 0, 0, 0},
++ {20, 0, DMAC_NOT_USE, 0, 0, 0},
++ {21, 0, DMAC_NOT_USE, 0, 0, 0},
++ {22, 0, DMAC_NOT_USE, 0, 0, 0},
++ {23, 0, DMAC_NOT_USE, 0, 0, 0},
++ {24, 0, DMAC_NOT_USE, 0, 0, 0},
++ {25, 0, DMAC_NOT_USE, 0, 0, 0},
++ {26, 0, DMAC_NOT_USE, 0, 0, 0},
++ {27, 0, DMAC_NOT_USE, 0, 0, 0},
++ {28, 0, DMAC_NOT_USE, 0, 0, 0},
++ {29, 0, DMAC_NOT_USE, 0, 0, 0},
++ {30, 0, DMAC_NOT_USE, 0, 0, 0},
++ {31, 0, DMAC_NOT_USE, 0, 0, 0},
+};
+#endif
diff --git a/drivers/hiedmac/hiedma_hi3516ev200.h b/drivers/hiedmac/hiedma_hi3516ev200.h
new file mode 100644
-index 0000000..74e73f3
+index 0000000..b0ccb6b
--- /dev/null
+++ b/drivers/hiedmac/hiedma_hi3516ev200.h
@@ -0,0 +1,83 @@
@@ -265341,43 +333291,43 @@ index 0000000..74e73f3
+#define EDMAC_RX 1
+
+edmac_peripheral g_peripheral[EDMAC_MAX_PERIPHERALS] = {
-+ {0, I2C0_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {1, I2C0_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {2, I2C1_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {3, I2C1_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {4, I2C2_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
-+ {5, I2C2_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
-+ {6, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {7, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {8, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {9, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {10, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {11, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {12, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {13, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {14, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {15, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {16, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {17, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {18, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {19, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {20, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {21, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {22, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {23, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {24, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {25, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {26, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {27, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {28, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {29, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {30, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {31, 0, DMAC_NOT_USE, 0, 0, 0},
++ {0, I2C0_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {1, I2C0_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {2, I2C1_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {3, I2C1_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {4, I2C2_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
++ {5, I2C2_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
++ {6, 0, DMAC_NOT_USE, 0, 0, 0},
++ {7, 0, DMAC_NOT_USE, 0, 0, 0},
++ {8, 0, DMAC_NOT_USE, 0, 0, 0},
++ {9, 0, DMAC_NOT_USE, 0, 0, 0},
++ {10, 0, DMAC_NOT_USE, 0, 0, 0},
++ {11, 0, DMAC_NOT_USE, 0, 0, 0},
++ {12, 0, DMAC_NOT_USE, 0, 0, 0},
++ {13, 0, DMAC_NOT_USE, 0, 0, 0},
++ {14, 0, DMAC_NOT_USE, 0, 0, 0},
++ {15, 0, DMAC_NOT_USE, 0, 0, 0},
++ {16, 0, DMAC_NOT_USE, 0, 0, 0},
++ {17, 0, DMAC_NOT_USE, 0, 0, 0},
++ {18, 0, DMAC_NOT_USE, 0, 0, 0},
++ {19, 0, DMAC_NOT_USE, 0, 0, 0},
++ {20, 0, DMAC_NOT_USE, 0, 0, 0},
++ {21, 0, DMAC_NOT_USE, 0, 0, 0},
++ {22, 0, DMAC_NOT_USE, 0, 0, 0},
++ {23, 0, DMAC_NOT_USE, 0, 0, 0},
++ {24, 0, DMAC_NOT_USE, 0, 0, 0},
++ {25, 0, DMAC_NOT_USE, 0, 0, 0},
++ {26, 0, DMAC_NOT_USE, 0, 0, 0},
++ {27, 0, DMAC_NOT_USE, 0, 0, 0},
++ {28, 0, DMAC_NOT_USE, 0, 0, 0},
++ {29, 0, DMAC_NOT_USE, 0, 0, 0},
++ {30, 0, DMAC_NOT_USE, 0, 0, 0},
++ {31, 0, DMAC_NOT_USE, 0, 0, 0},
+};
+#endif
diff --git a/drivers/hiedmac/hiedma_hi3519av100.h b/drivers/hiedmac/hiedma_hi3519av100.h
new file mode 100644
-index 0000000..2748281
+index 0000000..0b3028b
--- /dev/null
+++ b/drivers/hiedmac/hiedma_hi3519av100.h
@@ -0,0 +1,156 @@
@@ -265471,75 +333421,75 @@ index 0000000..2748281
+#define EDMAC_RX 1
+
+edmac_peripheral g_peripheral[EDMAC_MAX_PERIPHERALS] = {
-+ {0, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {1, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {2, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {3, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {4, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {5, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {6, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {7, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {8, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {9, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {10, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {11, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {12, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {13, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {14, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {15, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {16, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {17, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {18, I2C2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {19, I2C2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {20, I2C3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {21, I2C3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {22, I2C4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {23, I2C4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {24, I2C5_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {25, I2C5_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {26, I2C6_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {27, I2C6_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {28, I2C7_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {29, I2C7_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {30, I2C8_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {31, I2C8_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {32, I2C9_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {33, I2C9_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {34, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {35, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {36, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {37, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {38, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {39, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {40, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {41, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {42, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {43, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {44, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {45, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {46, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {47, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {48, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {49, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {50, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {51, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {52, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {53, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {54, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {55, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {56, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {57, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {58, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {59, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {60, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {61, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {62, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {63, 0, DMAC_NOT_USE, 0, 0, 0},
++ {0, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {1, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {2, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {3, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {4, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {5, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {6, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {7, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {8, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {9, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {10, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {11, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {12, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {13, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {14, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {15, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {16, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {17, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {18, I2C2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {19, I2C2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {20, I2C3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {21, I2C3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {22, I2C4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {23, I2C4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {24, I2C5_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {25, I2C5_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {26, I2C6_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {27, I2C6_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {28, I2C7_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {29, I2C7_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {30, I2C8_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {31, I2C8_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {32, I2C9_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {33, I2C9_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {34, 0, DMAC_NOT_USE, 0, 0, 0},
++ {35, 0, DMAC_NOT_USE, 0, 0, 0},
++ {36, 0, DMAC_NOT_USE, 0, 0, 0},
++ {37, 0, DMAC_NOT_USE, 0, 0, 0},
++ {38, 0, DMAC_NOT_USE, 0, 0, 0},
++ {39, 0, DMAC_NOT_USE, 0, 0, 0},
++ {40, 0, DMAC_NOT_USE, 0, 0, 0},
++ {41, 0, DMAC_NOT_USE, 0, 0, 0},
++ {42, 0, DMAC_NOT_USE, 0, 0, 0},
++ {43, 0, DMAC_NOT_USE, 0, 0, 0},
++ {44, 0, DMAC_NOT_USE, 0, 0, 0},
++ {45, 0, DMAC_NOT_USE, 0, 0, 0},
++ {46, 0, DMAC_NOT_USE, 0, 0, 0},
++ {47, 0, DMAC_NOT_USE, 0, 0, 0},
++ {48, 0, DMAC_NOT_USE, 0, 0, 0},
++ {49, 0, DMAC_NOT_USE, 0, 0, 0},
++ {50, 0, DMAC_NOT_USE, 0, 0, 0},
++ {51, 0, DMAC_NOT_USE, 0, 0, 0},
++ {52, 0, DMAC_NOT_USE, 0, 0, 0},
++ {53, 0, DMAC_NOT_USE, 0, 0, 0},
++ {54, 0, DMAC_NOT_USE, 0, 0, 0},
++ {55, 0, DMAC_NOT_USE, 0, 0, 0},
++ {56, 0, DMAC_NOT_USE, 0, 0, 0},
++ {57, 0, DMAC_NOT_USE, 0, 0, 0},
++ {58, 0, DMAC_NOT_USE, 0, 0, 0},
++ {59, 0, DMAC_NOT_USE, 0, 0, 0},
++ {60, 0, DMAC_NOT_USE, 0, 0, 0},
++ {61, 0, DMAC_NOT_USE, 0, 0, 0},
++ {62, 0, DMAC_NOT_USE, 0, 0, 0},
++ {63, 0, DMAC_NOT_USE, 0, 0, 0},
+};
+#endif
diff --git a/drivers/hiedmac/hiedma_hi3559av100.h b/drivers/hiedmac/hiedma_hi3559av100.h
new file mode 100644
-index 0000000..a175f66
+index 0000000..ae63fe2
--- /dev/null
+++ b/drivers/hiedmac/hiedma_hi3559av100.h
@@ -0,0 +1,140 @@
@@ -265633,62 +333583,62 @@ index 0000000..a175f66
+#define EDMAC_RX 1
+
+edmac_peripheral g_peripheral[EDMAC_MAX_PERIPHERALS] = {
-+ {0, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {1, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {2, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {3, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {4, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {5, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {6, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {7, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {8, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {9, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
-+ {10, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {11, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {12, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {13, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {14, I2C2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {15, I2C2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {16, I2C3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {17, I2C3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {18, I2C4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {19, I2C4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {20, I2C5_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {21, I2C5_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {22, I2C6_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {23, I2C6_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {24, I2C7_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {25, I2C7_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {26, I2C8_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {27, I2C8_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {28, I2C9_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {29, I2C9_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {30, I2C10_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {31, I2C10_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {32, I2C11_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
-+ {33, I2C11_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
-+ {34, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {35, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {36, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {37, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {38, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {39, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {40, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {41, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {42, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {43, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {44, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {45, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {46, 0, DMAC_NOT_USE, 0, 0, 0},
-+ {47, 0, DMAC_NOT_USE, 0, 0, 0},
++ {0, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {1, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {2, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {3, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {4, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {5, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {6, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {7, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {8, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {9, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
++ {10, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {11, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {12, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {13, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {14, I2C2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {15, I2C2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {16, I2C3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {17, I2C3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {18, I2C4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {19, I2C4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {20, I2C5_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {21, I2C5_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {22, I2C6_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {23, I2C6_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {24, I2C7_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {25, I2C7_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {26, I2C8_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {27, I2C8_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {28, I2C9_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {29, I2C9_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {30, I2C10_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {31, I2C10_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {32, I2C11_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
++ {33, I2C11_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
++ {34, 0, DMAC_NOT_USE, 0, 0, 0},
++ {35, 0, DMAC_NOT_USE, 0, 0, 0},
++ {36, 0, DMAC_NOT_USE, 0, 0, 0},
++ {37, 0, DMAC_NOT_USE, 0, 0, 0},
++ {38, 0, DMAC_NOT_USE, 0, 0, 0},
++ {39, 0, DMAC_NOT_USE, 0, 0, 0},
++ {40, 0, DMAC_NOT_USE, 0, 0, 0},
++ {41, 0, DMAC_NOT_USE, 0, 0, 0},
++ {42, 0, DMAC_NOT_USE, 0, 0, 0},
++ {43, 0, DMAC_NOT_USE, 0, 0, 0},
++ {44, 0, DMAC_NOT_USE, 0, 0, 0},
++ {45, 0, DMAC_NOT_USE, 0, 0, 0},
++ {46, 0, DMAC_NOT_USE, 0, 0, 0},
++ {47, 0, DMAC_NOT_USE, 0, 0, 0},
+};
+#endif
diff --git a/drivers/hiedmac/hiedmacv310.c b/drivers/hiedmac/hiedmacv310.c
new file mode 100644
-index 0000000..63bfce6
+index 0000000..62769fd
--- /dev/null
+++ b/drivers/hiedmac/hiedmacv310.c
-@@ -0,0 +1,911 @@
+@@ -0,0 +1,920 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -265729,7 +333679,7 @@ index 0000000..63bfce6
+
+#include "hiedmacv310.h"
+
-+#ifdef CONFIG_ARCH_HI3559AV100
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+#include "hiedma_hi3559av100.h"
+#endif
+
@@ -265737,11 +333687,14 @@ index 0000000..63bfce6
+#include "hiedma_hi3519av100.h"
+#endif
+
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+#include "hiedma_hi3516cv500.h"
+#endif
+
-+#if defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
++#if defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || \
++ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
+#include "hiedma_hi3516ev200.h"
+#endif
+
@@ -265752,35 +333705,35 @@ index 0000000..63bfce6
+int hiedmacv310_trace_level_n = HIEDMACV310_TRACE_LEVEL;
+
+struct hiedmac_host {
-+ struct platform_device *pdev;
-+ void __iomem *base;
-+ struct regmap *misc_regmap;
-+ unsigned int misc_ctrl_base;
-+ void __iomem *crg_ctrl;
-+ unsigned int id;
-+ struct clk *clk;
-+ struct clk *axi_clk;
-+ unsigned int irq;
-+ struct reset_control *rstc;
-+ unsigned int channels;
-+ unsigned int slave_requests;
++ struct platform_device *pdev;
++ void __iomem *base;
++ struct regmap *misc_regmap;
++ unsigned int misc_ctrl_base;
++ void __iomem *crg_ctrl;
++ unsigned int id;
++ struct clk *clk;
++ struct clk *axi_clk;
++ unsigned int irq;
++ struct reset_control *rstc;
++ unsigned int channels;
++ unsigned int slave_requests;
+};
+
+#define DRIVER_NAME "hiedmacv310"
+
+int dmac_channel_allocate(void)
+{
-+ unsigned int i;
++ unsigned int i;
+
-+ for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++) {
-+ if (g_channel_status[i] == DMAC_CHN_VACANCY) {
-+ g_channel_status[i] = DMAC_CHN_ALLOCAT;
-+ return i;
-+ }
-+ }
++ for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++) {
++ if (g_channel_status[i] == DMAC_CHN_VACANCY) {
++ g_channel_status[i] = DMAC_CHN_ALLOCAT;
++ return i;
++ }
++ }
+
-+ hiedmacv310_error("no to alloc\n");
-+ return -1;
++ hiedmacv310_error("no to alloc\n");
++ return -1;
+}
+EXPORT_SYMBOL(dmac_channel_allocate);
+
@@ -265790,62 +333743,62 @@ index 0000000..63bfce6
+static int hiedmac_update_status(unsigned int channel)
+{
+
-+ unsigned int channel_status;
-+ unsigned int channel_tc_status;
-+ unsigned int channel_err_status[3];
-+ unsigned int i = channel;
-+ unsigned long update_jiffies_timeout;
++ unsigned int channel_status;
++ unsigned int channel_tc_status;
++ unsigned int channel_err_status[3];
++ unsigned int i = channel;
++ unsigned long update_jiffies_timeout;
+
-+ update_jiffies_timeout = jiffies + HIEDMAC_UPDATE_TIMEOUT;
++ update_jiffies_timeout = jiffies + HIEDMAC_UPDATE_TIMEOUT;
+
-+ while (1) {
-+ channel_status = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_STAT);
-+ channel_status = (channel_status >> i) & 0x01;
-+ if (channel_status) {
-+ channel_tc_status = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_TC1);
-+ channel_tc_status = (channel_tc_status >> i) & 0x01;
-+ if (channel_tc_status) {
-+ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_TC1_RAW);
-+ g_channel_status[i] = DMAC_CHN_SUCCESS;
-+ break;
-+ }
++ while (1) {
++ channel_status = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_STAT);
++ channel_status = (channel_status >> i) & 0x01;
++ if (channel_status) {
++ channel_tc_status = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_TC1);
++ channel_tc_status = (channel_tc_status >> i) & 0x01;
++ if (channel_tc_status) {
++ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_TC1_RAW);
++ g_channel_status[i] = DMAC_CHN_SUCCESS;
++ break;
++ }
+
-+ channel_tc_status = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_TC2);
-+ channel_tc_status = (channel_tc_status >> i) & 0x01;
-+ if (channel_tc_status) {
-+ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_TC2_RAW);
-+ g_channel_status[i] = DMAC_CHN_SUCCESS;
-+ break;
-+ }
++ channel_tc_status = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_TC2);
++ channel_tc_status = (channel_tc_status >> i) & 0x01;
++ if (channel_tc_status) {
++ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_TC2_RAW);
++ g_channel_status[i] = DMAC_CHN_SUCCESS;
++ break;
++ }
+
-+ channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
-+ channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
-+ channel_err_status[1] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR2);
-+ channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
-+ channel_err_status[2] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR3);
-+ channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
++ channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
++ channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
++ channel_err_status[1] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR2);
++ channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
++ channel_err_status[2] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR3);
++ channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
+
-+ if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
-+ hiedmacv310_error("Error in HIEDMAC %d finish!\n", i);
-+ channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
-+ channel_err_status[1] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR2);
-+ channel_err_status[2] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR3);
-+ g_channel_status[i] = -DMAC_CHN_ERROR;
-+ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_ERR1_RAW);
-+ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_ERR2_RAW);
-+ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_ERR3_RAW);
-+ break;
-+ }
-+ }
++ if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
++ hiedmacv310_error("Error in HIEDMAC %d finish!\n", i);
++ channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
++ channel_err_status[1] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR2);
++ channel_err_status[2] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR3);
++ g_channel_status[i] = -DMAC_CHN_ERROR;
++ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_ERR1_RAW);
++ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_ERR2_RAW);
++ hiedmacv310_writel(1 << i, dma_regbase + HIEDMAC_INT_ERR3_RAW);
++ break;
++ }
++ }
+
-+ if (!time_before(jiffies, update_jiffies_timeout)) {
-+ hiedmacv310_error("Timeout in DMAC %d!\n", i);
-+ g_channel_status[i] = -DMAC_CHN_TIMEOUT;
-+ break;
-+ }
-+ }
++ if (!time_before(jiffies, update_jiffies_timeout)) {
++ hiedmacv310_error("Timeout in DMAC %d!\n", i);
++ g_channel_status[i] = -DMAC_CHN_TIMEOUT;
++ break;
++ }
++ }
+
-+ return g_channel_status[i];
++ return g_channel_status[i];
+}
+
+/*
@@ -265853,14 +333806,14 @@ index 0000000..63bfce6
+ */
+int dmac_register_isr(unsigned int channel, void *pisr)
+{
-+ if (channel < 0 || channel > HIEDMAC_CHANNEL_NUM - 1) {
-+ hiedmacv310_error("invalid channel,channel=%0d\n", channel);
-+ return -EINVAL;
-+ }
++ if (channel < 0 || channel > HIEDMAC_CHANNEL_NUM - 1) {
++ hiedmacv310_error("invalid channel,channel=%0d\n", channel);
++ return -EINVAL;
++ }
+
-+ function[channel] = (void *)pisr;
++ function[channel] = (void *)pisr;
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_register_isr);
+
@@ -265869,66 +333822,66 @@ index 0000000..63bfce6
+ */
+int dmac_channel_free(unsigned int channel)
+{
-+ g_channel_status[channel] = DMAC_CHN_VACANCY;
-+ return 0;
++ g_channel_status[channel] = DMAC_CHN_VACANCY;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_channel_free);
+
+static unsigned int dmac_check_request(unsigned int peripheral_addr, int direction)
+{
-+ int i;
++ int i;
+
-+ for (i = direction; i < EDMAC_MAX_PERIPHERALS; i += 2) {
-+ if (g_peripheral[i].peri_addr == peripheral_addr) {
-+ return i;
-+ }
-+ }
-+ hiedmacv310_error("Invalid devaddr\n");
-+ return -1;
++ for (i = direction; i < EDMAC_MAX_PERIPHERALS; i += 2) {
++ if (g_peripheral[i].peri_addr == peripheral_addr) {
++ return i;
++ }
++ }
++ hiedmacv310_error("Invalid devaddr\n");
++ return -1;
+}
+
+void edmac_channel_free(int channel)
+{
-+ g_channel_status[channel] = DMAC_CHN_VACANCY;
++ g_channel_status[channel] = DMAC_CHN_VACANCY;
+}
+/*
+ * wait for transfer end
+ */
+int dmac_wait(int channel)
+{
-+ int ret_result;
-+ int ret = 0;
++ int ret_result;
++ int ret = 0;
+
-+ if (channel < 0) {
-+ return -1;
-+ }
++ if (channel < 0) {
++ return -1;
++ }
+
-+ while (1) {
-+ ret_result = hiedmac_update_status(channel);
-+ if (ret_result == -DMAC_CHN_ERROR) {
-+ hiedmacv310_error("Transfer Error.\n");
-+ ret = -1;
-+ goto end;
-+ } else if (ret_result == DMAC_NOT_FINISHED) {
-+ udelay(10);
-+ } else if (ret_result == DMAC_CHN_SUCCESS) {
-+ ret = DMAC_CHN_SUCCESS;
-+ goto end;
-+ } else if (ret_result == DMAC_CHN_VACANCY) {
-+ ret = DMAC_CHN_SUCCESS;
-+ goto end;
-+ } else if (ret_result == -DMAC_CHN_TIMEOUT) {
-+ hiedmacv310_error("Timeout.\n");
-+ hiedmacv310_writel(HIEDMAC_Cx_DISABLE, dma_regbase + HIEDMAC_Cx_CONFIG(channel));
-+ g_channel_status[channel] = DMAC_CHN_VACANCY;
-+ ret = -1;
-+ return ret;
-+ }
-+ }
++ while (1) {
++ ret_result = hiedmac_update_status(channel);
++ if (ret_result == -DMAC_CHN_ERROR) {
++ hiedmacv310_error("Transfer Error.\n");
++ ret = -1;
++ goto end;
++ } else if (ret_result == DMAC_NOT_FINISHED) {
++ udelay(10);
++ } else if (ret_result == DMAC_CHN_SUCCESS) {
++ ret = DMAC_CHN_SUCCESS;
++ goto end;
++ } else if (ret_result == DMAC_CHN_VACANCY) {
++ ret = DMAC_CHN_SUCCESS;
++ goto end;
++ } else if (ret_result == -DMAC_CHN_TIMEOUT) {
++ hiedmacv310_error("Timeout.\n");
++ hiedmacv310_writel(HIEDMAC_Cx_DISABLE, dma_regbase + HIEDMAC_Cx_CONFIG(channel));
++ g_channel_status[channel] = DMAC_CHN_VACANCY;
++ ret = -1;
++ return ret;
++ }
++ }
+end:
-+ hiedmacv310_writel(HIEDMAC_Cx_DISABLE, dma_regbase + HIEDMAC_Cx_CONFIG(channel));
-+ edmac_channel_free(channel);
-+ return ret;
++ hiedmacv310_writel(HIEDMAC_Cx_DISABLE, dma_regbase + HIEDMAC_Cx_CONFIG(channel));
++ edmac_channel_free(channel);
++ return ret;
+}
+EXPORT_SYMBOL(dmac_wait);
+
@@ -265936,142 +333889,142 @@ index 0000000..63bfce6
+ * execute memory to peripheral dma transfer without LLI
+ */
+int dmac_m2p_transfer(unsigned long long memaddr, unsigned int uwperipheralid,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int ulchnn;
-+ unsigned int uwwidth;
-+ unsigned int temp;
++ unsigned int ulchnn;
++ unsigned int uwwidth;
++ unsigned int temp;
+
-+ ulchnn = dmac_channel_allocate();
-+ if (-1 == ulchnn) {
-+ return -1;
-+ }
++ ulchnn = dmac_channel_allocate();
++ if (-1 == ulchnn) {
++ return -1;
++ }
+
-+ hiedmacv310_trace(4, "ulchnn = %d\n", ulchnn);
-+ uwwidth = g_peripheral[uwperipheralid].transfer_width;
-+ if (length >> uwwidth >= HIEDMAC_TRANS_MAXSIZE) {
-+ hiedmacv310_error("The length is more than 64k!\n");
-+ return -1;
-+ }
++ hiedmacv310_trace(4, "ulchnn = %d\n", ulchnn);
++ uwwidth = g_peripheral[uwperipheralid].transfer_width;
++ if (length >> uwwidth >= HIEDMAC_TRANS_MAXSIZE) {
++ hiedmacv310_error("The length is more than 64k!\n");
++ return -1;
++ }
+
-+ hiedmacv310_writel(memaddr & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn));
++ hiedmacv310_writel(memaddr & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((memaddr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(ulchnn));
++ hiedmacv310_writel((memaddr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(ulchnn));
+#endif
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn)));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn)));
+
-+ hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
-+ dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn));
++ hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
++ dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((g_peripheral[uwperipheralid].peri_addr >> 32) & 0xffffffff,
-+ dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(ulchnn));
++ hiedmacv310_writel((g_peripheral[uwperipheralid].peri_addr >> 32) & 0xffffffff,
++ dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(ulchnn));
+#endif
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn)));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn)));
+
-+ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn)));
++ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn)));
+
-+ hiedmacv310_writel(length, dma_regbase + HIEDMAC_Cx_CNT0(ulchnn));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_CNT0(ulchnn)));
++ hiedmacv310_writel(length, dma_regbase + HIEDMAC_Cx_CNT0(ulchnn));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_CNT0(ulchnn)));
+
-+ temp = g_peripheral[uwperipheralid].transfer_cfg | uwwidth << EDMA_SRC_WIDTH_OFFSET
-+ | (g_peripheral[uwperipheralid].dynamic_periphery_num << PERI_ID_OFFSET)
-+ | EDMA_CH_ENABLE;
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
-+ hiedmacv310_writel(temp, dma_regbase + HIEDMAC_Cx_CONFIG(ulchnn));
-+ return ulchnn;
++ temp = g_peripheral[uwperipheralid].transfer_cfg | uwwidth << EDMA_SRC_WIDTH_OFFSET
++ | (g_peripheral[uwperipheralid].dynamic_periphery_num << PERI_ID_OFFSET)
++ | EDMA_CH_ENABLE;
++ hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
++ hiedmacv310_writel(temp, dma_regbase + HIEDMAC_Cx_CONFIG(ulchnn));
++ return ulchnn;
+}
+
+/*
+ * execute memory to peripheral dma transfer without LLI
+ */
+int dmac_p2m_transfer(unsigned long memaddr, unsigned int uwperipheralid,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int ulchnn;
-+ unsigned int uwwidth;
-+ unsigned int temp;
++ unsigned int ulchnn;
++ unsigned int uwwidth;
++ unsigned int temp;
+
-+ ulchnn = dmac_channel_allocate();
-+ if (-1 == ulchnn) {
-+ return -1;
-+ }
++ ulchnn = dmac_channel_allocate();
++ if (-1 == ulchnn) {
++ return -1;
++ }
+
-+ hiedmacv310_trace(4, "ulchnn = %d\n", ulchnn);
-+ uwwidth = g_peripheral[uwperipheralid].transfer_width;
-+ if (length >> uwwidth >= HIEDMAC_TRANS_MAXSIZE) {
-+ hiedmacv310_error("The length is more than 64k!\n");
-+ return -1;
-+ }
++ hiedmacv310_trace(4, "ulchnn = %d\n", ulchnn);
++ uwwidth = g_peripheral[uwperipheralid].transfer_width;
++ if (length >> uwwidth >= HIEDMAC_TRANS_MAXSIZE) {
++ hiedmacv310_error("The length is more than 64k!\n");
++ return -1;
++ }
+
-+ hiedmacv310_writel(memaddr & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn));
++ hiedmacv310_writel(memaddr & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((memaddr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(ulchnn));
++ hiedmacv310_writel((memaddr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(ulchnn));
+#endif
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn)));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(ulchnn)));
+
-+ hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
-+ dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn));
++ hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
++ dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(ulchnn));
++ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(ulchnn));
+#endif
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn)));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(ulchnn)));
+
-+ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn)));
++ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn)));
+
-+ hiedmacv310_writel(length, dma_regbase + HIEDMAC_Cx_CNT0(ulchnn));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_CNT0(ulchnn)));
++ hiedmacv310_writel(length, dma_regbase + HIEDMAC_Cx_CNT0(ulchnn));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_CNT0(ulchnn)));
+
-+ temp = g_peripheral[uwperipheralid].transfer_cfg | uwwidth << EDMA_SRC_WIDTH_OFFSET
-+ | (g_peripheral[uwperipheralid].dynamic_periphery_num << PERI_ID_OFFSET)
-+ | EDMA_CH_ENABLE;
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
-+ hiedmacv310_writel(temp, dma_regbase + HIEDMAC_Cx_CONFIG(ulchnn));
-+ return ulchnn;
++ temp = g_peripheral[uwperipheralid].transfer_cfg | uwwidth << EDMA_SRC_WIDTH_OFFSET
++ | (g_peripheral[uwperipheralid].dynamic_periphery_num << PERI_ID_OFFSET)
++ | EDMA_CH_ENABLE;
++ hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
++ hiedmacv310_writel(temp, dma_regbase + HIEDMAC_Cx_CONFIG(ulchnn));
++ return ulchnn;
+}
+
+int do_dma_m2p(unsigned long long memaddr, unsigned int peripheral_addr,
-+ unsigned int length)
++ unsigned int length)
+{
-+ int ret = 0;
-+ int uwperipheralid;
++ int ret = 0;
++ int uwperipheralid;
+
-+ uwperipheralid = dmac_check_request(peripheral_addr, EDMAC_TX);
-+ if (uwperipheralid < 0) {
-+ hiedmacv310_error("m2p:Invalid devaddr\n");
-+ return -1;
-+ }
++ uwperipheralid = dmac_check_request(peripheral_addr, EDMAC_TX);
++ if (uwperipheralid < 0) {
++ hiedmacv310_error("m2p:Invalid devaddr\n");
++ return -1;
++ }
+
-+ ret = dmac_m2p_transfer(memaddr, uwperipheralid, length);
-+ if (ret == -1) {
-+ hiedmacv310_error("m2p:trans err\n");
-+ return -1;
-+ }
++ ret = dmac_m2p_transfer(memaddr, uwperipheralid, length);
++ if (ret == -1) {
++ hiedmacv310_error("m2p:trans err\n");
++ return -1;
++ }
+
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(do_dma_m2p);
+
+int do_dma_p2m(unsigned long memaddr, unsigned int peripheral_addr,
-+ unsigned int length)
++ unsigned int length)
+{
-+ int ret = -1;
-+ int uwperipheralid;
++ int ret = -1;
++ int uwperipheralid;
+
-+ uwperipheralid = dmac_check_request(peripheral_addr, EDMAC_RX);
-+ if (uwperipheralid < 0) {
-+ hiedmacv310_error("p2m:Invalid devaddr.\n");
-+ return -1;
-+ }
++ uwperipheralid = dmac_check_request(peripheral_addr, EDMAC_RX);
++ if (uwperipheralid < 0) {
++ hiedmacv310_error("p2m:Invalid devaddr.\n");
++ return -1;
++ }
+
-+ ret = dmac_p2m_transfer(memaddr, uwperipheralid, length);
-+ if (ret == -1) {
-+ hiedmacv310_error("p2m:trans err\n");
-+ return -1;
-+ }
++ ret = dmac_p2m_transfer(memaddr, uwperipheralid, length);
++ if (ret == -1) {
++ hiedmacv310_error("p2m:trans err\n");
++ return -1;
++ }
+
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(do_dma_p2m);
+
@@ -266079,52 +334032,57 @@ index 0000000..63bfce6
+ * buile LLI for memory to memory DMA transfer
+ */
+int dmac_buildllim2m(unsigned long *ppheadlli,
-+ unsigned long psource,
-+ unsigned long pdest,
-+ unsigned int totaltransfersize,
-+ unsigned int uwnumtransfers)
++ unsigned long psource,
++ unsigned long pdest,
++ unsigned int totaltransfersize,
++ unsigned int uwnumtransfers)
+{
-+ int lli_num = 0;
-+ unsigned long phy_address;
-+ int j;
-+ dmac_lli *plli;
++ int lli_num = 0;
++ unsigned long phy_address;
++ int j;
++ dmac_lli *plli = NULL;
+
-+ lli_num = (totaltransfersize / uwnumtransfers);
-+ if ((totaltransfersize % uwnumtransfers) != 0) {
-+ lli_num++;
-+ }
++ if (uwnumtransfers == 0) {
++ hiedmacv310_error("Invalidate value for uwnumtransfers\n");
++ return -EINVAL;
++ }
+
-+ hiedmacv310_trace(4, "lli_num:%d\n", lli_num);
++ lli_num = (totaltransfersize / uwnumtransfers);
++ if ((totaltransfersize % uwnumtransfers) != 0) {
++ lli_num++;
++ }
+
-+ phy_address = ppheadlli[0];
-+ plli = (dmac_lli *)ppheadlli[1];
-+ hiedmacv310_trace(4, "phy_address: 0x%lx\n", phy_address);
-+ hiedmacv310_trace(4, "address: 0x%p\n", plli);
-+ for (j = 0; j < lli_num; j++) {
-+ memset(plli, 0x0, sizeof(dmac_lli));
-+ /*
-+ * at the last transfer, chain_en should be set to 0x0;
-+ * others tansfer,chain_en should be set to 0x2;
-+ */
-+ plli->next_lli = (phy_address + (j + 1) * sizeof(dmac_lli)) & (~(HIEDMAC_LLI_ALIGN - 1));
-+ if (j < lli_num - 1) {
-+ plli->next_lli |= HIEDMAC_LLI_ENABLE;
-+ plli->count = uwnumtransfers;
-+ } else {
-+ plli->next_lli |= HIEDMAC_LLI_DISABLE;
-+ plli->count = totaltransfersize % uwnumtransfers;
-+ }
++ hiedmacv310_trace(4, "lli_num:%d\n", lli_num);
+
-+ plli->src_addr = psource;
-+ plli->dest_addr = pdest;
-+ plli->config = HIEDMAC_CxCONFIG_M2M_LLI;
++ phy_address = ppheadlli[0];
++ plli = (dmac_lli *)ppheadlli[1];
++ hiedmacv310_trace(4, "phy_address: 0x%lx\n", phy_address);
++ hiedmacv310_trace(4, "address: 0x%p\n", plli);
++ for (j = 0; j < lli_num; j++) {
++ memset(plli, 0x0, sizeof(dmac_lli));
++ /*
++ * at the last transfer, chain_en should be set to 0x0;
++ * others tansfer,chain_en should be set to 0x2;
++ */
++ plli->next_lli = (phy_address + (j + 1) * sizeof(dmac_lli)) & (~(HIEDMAC_LLI_ALIGN - 1));
++ if (j < lli_num - 1) {
++ plli->next_lli |= HIEDMAC_LLI_ENABLE;
++ plli->count = uwnumtransfers;
++ } else {
++ plli->next_lli |= HIEDMAC_LLI_DISABLE;
++ plli->count = totaltransfersize % uwnumtransfers;
++ }
+
-+ psource += uwnumtransfers;
-+ pdest += uwnumtransfers;
-+ plli++;
-+ }
++ plli->src_addr = psource;
++ plli->dest_addr = pdest;
++ plli->config = HIEDMAC_CxCONFIG_M2M_LLI;
+
-+ return 0;
++ psource += uwnumtransfers;
++ pdest += uwnumtransfers;
++ plli++;
++ }
++
++ return 0;
+}
+EXPORT_SYMBOL(dmac_buildllim2m);
+
@@ -266133,33 +334091,33 @@ index 0000000..63bfce6
+ */
+int dmac_start_llim2m(unsigned int channel, unsigned long *pfirst_lli)
+{
-+ unsigned int i = channel;
-+ dmac_lli *plli;
++ unsigned int i = channel;
++ dmac_lli *plli;
+
-+ plli = (dmac_lli *)pfirst_lli[1];
-+ hiedmacv310_trace(4, "plli.src_addr: 0x%lx\n", plli->src_addr);
-+ hiedmacv310_trace(4, "plli.dst_addr: 0x%lx\n", plli->dest_addr);
-+ hiedmacv310_trace(4, "plli.next_lli: 0x%lx\n", plli->next_lli);
-+ hiedmacv310_trace(4, "plli.count: 0x%d\n", plli->count);
++ plli = (dmac_lli *)pfirst_lli[1];
++ hiedmacv310_trace(4, "plli.src_addr: 0x%lx\n", plli->src_addr);
++ hiedmacv310_trace(4, "plli.dst_addr: 0x%lx\n", plli->dest_addr);
++ hiedmacv310_trace(4, "plli.next_lli: 0x%lx\n", plli->next_lli);
++ hiedmacv310_trace(4, "plli.count: 0x%d\n", plli->count);
+
+
-+ hiedmacv310_writel(plli->dest_addr & 0xffffffff, dma_regbase + HIEDMAC_Cx_LLI_L(i));
++ hiedmacv310_writel(plli->dest_addr & 0xffffffff, dma_regbase + HIEDMAC_Cx_LLI_L(i));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_LLI_H(i));
++ hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_LLI_H(i));
+#endif
-+ hiedmacv310_writel(plli->count, dma_regbase + HIEDMAC_Cx_CNT0(i));
++ hiedmacv310_writel(plli->count, dma_regbase + HIEDMAC_Cx_CNT0(i));
+
-+ hiedmacv310_writel(plli->src_addr & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(i));
++ hiedmacv310_writel(plli->src_addr & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(i));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(i));
++ hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(i));
+#endif
-+ hiedmacv310_writel(plli->dest_addr & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i));
++ hiedmacv310_writel(plli->dest_addr & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(i));
++ hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(i));
+#endif
-+ hiedmacv310_writel(plli->config | EDMA_CH_ENABLE, dma_regbase + HIEDMAC_Cx_CONFIG(i));
++ hiedmacv310_writel(plli->config | EDMA_CH_ENABLE, dma_regbase + HIEDMAC_Cx_CONFIG(i));
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_start_llim2m);
+
@@ -266167,36 +334125,36 @@ index 0000000..63bfce6
+ * config register for memory to memory DMA transfer without LLI
+ */
+int dmac_start_m2m(unsigned int channel, unsigned long psource,
-+ unsigned long pdest, unsigned int uwnumtransfers)
++ unsigned long pdest, unsigned int uwnumtransfers)
+{
-+ unsigned int i = channel;
++ unsigned int i = channel;
+
-+ if (uwnumtransfers > HIEDMAC_TRANS_MAXSIZE || uwnumtransfers == 0) {
-+ hiedmacv310_error("Invalidate transfer size,size=%x\n", uwnumtransfers);
-+ return -EINVAL;
-+ }
-+ hiedmacv310_trace(4, "channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
-+ channel, psource, pdest, uwnumtransfers);
++ if (uwnumtransfers > HIEDMAC_TRANS_MAXSIZE || uwnumtransfers == 0) {
++ hiedmacv310_error("Invalidate transfer size,size=%x\n", uwnumtransfers);
++ return -EINVAL;
++ }
++ hiedmacv310_trace(4, "channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
++ channel, psource, pdest, uwnumtransfers);
+
-+ hiedmacv310_writel(psource & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(i));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(i)));
++ hiedmacv310_writel(psource & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(i));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_L(i)));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((psource >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(i));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_H = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(i)));
++ hiedmacv310_writel((psource >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(i));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_H = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(i)));
+#endif
-+ hiedmacv310_writel(pdest & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i)));
++ hiedmacv310_writel(pdest & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i)));
+#ifdef CONFIG_ARM64
-+ hiedmacv310_writel((pdest >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(i));
-+ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_H = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(i)));
++ hiedmacv310_writel((pdest >> 32) & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(i));
++ hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_H = 0x%x\n", hiedmacv310_readl(dma_regbase + HIEDMAC_Cx_DEST_ADDR_H(i)));
+#endif
-+ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(i));
++ hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(i));
+
-+ hiedmacv310_writel(uwnumtransfers, dma_regbase + HIEDMAC_Cx_CNT0(i));
++ hiedmacv310_writel(uwnumtransfers, dma_regbase + HIEDMAC_Cx_CNT0(i));
+
-+ hiedmacv310_writel(HIEDMAC_CxCONFIG_M2M | EDMA_CH_ENABLE, dma_regbase + HIEDMAC_Cx_CONFIG(i));
++ hiedmacv310_writel(HIEDMAC_CxCONFIG_M2M | EDMA_CH_ENABLE, dma_regbase + HIEDMAC_Cx_CONFIG(i));
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_start_m2m);
+
@@ -266204,43 +334162,43 @@ index 0000000..63bfce6
+ * execute memory to memory dma transfer without LLI
+ */
+int dmac_m2m_transfer(unsigned long source, unsigned long dest,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int ulchnn;
-+ unsigned int dma_size = 0;
-+ unsigned int dma_count, left_size;
++ unsigned int ulchnn;
++ unsigned int dma_size = 0;
++ unsigned int dma_count, left_size;
+
-+ left_size = length;
-+ dma_count = 0;
-+ ulchnn = dmac_channel_allocate();
-+ if (ulchnn < 0) {
-+ return -EINVAL;
-+ }
++ left_size = length;
++ dma_count = 0;
++ ulchnn = dmac_channel_allocate();
++ if (ulchnn < 0) {
++ return -EINVAL;
++ }
+
-+ hiedmacv310_trace(6, "using channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
-+ ulchnn, source, dest, length);
++ hiedmacv310_trace(6, "using channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
++ ulchnn, source, dest, length);
+
-+ while (left_size) {
-+ if (left_size >= HIEDMAC_TRANS_MAXSIZE) {
-+ dma_size = HIEDMAC_TRANS_MAXSIZE;
-+ } else {
-+ dma_size = left_size;
-+ }
-+ dmac_start_m2m(ulchnn,
-+ source + dma_count * dma_size,
-+ dest + dma_count * dma_size,
-+ dma_size);
++ while (left_size) {
++ if (left_size >= HIEDMAC_TRANS_MAXSIZE) {
++ dma_size = HIEDMAC_TRANS_MAXSIZE;
++ } else {
++ dma_size = left_size;
++ }
++ dmac_start_m2m(ulchnn,
++ source + dma_count * dma_size,
++ dest + dma_count * dma_size,
++ dma_size);
+
-+ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
-+ hiedmacv310_error("dma transfer error...\n");
-+ return -1;
-+ }
-+ left_size -= dma_size;
-+ dma_count++;
-+ hiedmacv310_trace(4, "left_size is %d.\n", left_size);
-+ }
++ if (dmac_wait(ulchnn) != DMAC_CHN_SUCCESS) {
++ hiedmacv310_error("dma transfer error...\n");
++ return -1;
++ }
++ left_size -= dma_size;
++ dma_count++;
++ hiedmacv310_trace(4, "left_size is %d.\n", left_size);
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(dmac_m2m_transfer);
+
@@ -266253,40 +334211,40 @@ index 0000000..63bfce6
+ * @length
+ * */
+int do_dma_llim2m(unsigned long source,
-+ unsigned long dest,
-+ unsigned long length)
++ unsigned long dest,
++ unsigned long length)
+{
-+ int ret = 0;
-+ unsigned chnn;
++ int ret = 0;
++ unsigned chnn;
+
-+ chnn = dmac_channel_allocate();
-+ if (chnn < 0) {
-+ ret = -1;
-+ goto end;
-+ }
-+ hiedmacv310_trace(4, "chnn:%d,src:%lx,dst:%lx,len:%ld.\n", chnn, source, dest, length);
++ chnn = dmac_channel_allocate();
++ if (chnn < 0) {
++ ret = -1;
++ goto end;
++ }
++ hiedmacv310_trace(4, "chnn:%d,src:%lx,dst:%lx,len:%ld.\n", chnn, source, dest, length);
+
-+ if (pllihead[0] == 0) {
-+ hiedmacv310_error("ppheadlli[0] is NULL.\n");
-+ ret = -ENOMEM;
-+ goto end;
-+ }
++ if (pllihead[0] == 0) {
++ hiedmacv310_error("ppheadlli[0] is NULL.\n");
++ ret = -ENOMEM;
++ goto end;
++ }
+
-+ ret = dmac_buildllim2m(pllihead, source, dest, length, HIEDMAC_TRANS_MAXSIZE);
-+ if (ret) {
-+ hiedmacv310_error("build lli error...\n");
-+ ret = -EIO;
-+ goto end;
-+ }
-+ ret = dmac_start_llim2m(chnn, pllihead);
-+ if (ret) {
-+ hiedmacv310_error("start lli error...\n");
-+ ret = -EIO;
-+ goto end;
-+ }
++ ret = dmac_buildllim2m(pllihead, source, dest, length, HIEDMAC_TRANS_MAXSIZE);
++ if (ret) {
++ hiedmacv310_error("build lli error...\n");
++ ret = -EIO;
++ goto end;
++ }
++ ret = dmac_start_llim2m(chnn, pllihead);
++ if (ret) {
++ hiedmacv310_error("start lli error...\n");
++ ret = -EIO;
++ goto end;
++ }
+
+end:
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(do_dma_llim2m);
+
@@ -266298,303 +334256,304 @@ index 0000000..63bfce6
+ *
+ */
+int allocate_dmalli_space(struct device *dev, unsigned long *ppheadlli,
-+ unsigned int page_num)
++ unsigned int page_num)
+{
-+ dma_addr_t dma_phys;
-+ void *dma_virt;
++ dma_addr_t dma_phys;
++ void *dma_virt;
+
-+ dma_virt = dma_alloc_coherent(dev, page_num * PAGE_SIZE,
-+ &dma_phys, GFP_DMA);
-+ if (dma_virt == NULL) {
-+ hiedmacv310_error("can't get dma mem from system\n");
-+ return -1;
-+ }
++ dma_virt = dma_alloc_coherent(dev, page_num * PAGE_SIZE,
++ &dma_phys, GFP_DMA);
++ if (dma_virt == NULL) {
++ hiedmacv310_error("can't get dma mem from system\n");
++ return -1;
++ }
+
-+ ppheadlli[0] = (unsigned long)(dma_phys);
-+ ppheadlli[1] = (unsigned long)(dma_virt);
++ ppheadlli[0] = (unsigned long)(dma_phys);
++ ppheadlli[1] = (unsigned long)(dma_virt);
+
-+ if (dma_phys & (HIEDMAC_LLI_ALIGN - 1)) {
-+ return -1;
-+ }
++ if (dma_phys & (HIEDMAC_LLI_ALIGN - 1)) {
++ return -1;
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(allocate_dmalli_space);
+
+
+
+static int hiedmac_priv_init(struct hiedmac_host *hiedmac,
-+ edmac_peripheral* peripheral_info)
++ edmac_peripheral* peripheral_info)
+{
-+ struct regmap *misc = hiedmac->misc_regmap;
-+ int i = 0;
-+ unsigned int count = 0;
-+ unsigned int offset = 0;
-+ unsigned ctrl = 0;
++ struct regmap *misc = hiedmac->misc_regmap;
++ int i = 0;
++ unsigned int count = 0;
++ unsigned int offset = 0;
++ unsigned ctrl = 0;
+
-+ for (i = 0; i < EDMAC_MAX_PERIPHERALS; i++) {
-+ if (peripheral_info[i].host_sel == hiedmac->id) {
-+ if (count > 32) {
-+ hiedmacv310_error("request table is not true!\n");
-+ return -1;
-+ }
-+ if (misc != NULL) {
-+ offset = hiedmac->misc_ctrl_base + (count & (~0x3));
-+ regmap_read(misc, offset, &ctrl);
-+ ctrl &= ~(0x3f << ((count & 0x3) << 3));
-+ ctrl |= peripheral_info[i].peri_id << ((count & 0x3) << 3);
-+ regmap_write(misc, offset, ctrl);
-+ }
-+ peripheral_info[i].dynamic_periphery_num = count;
-+ count++;
-+ }
-+ }
++ for (i = 0; i < EDMAC_MAX_PERIPHERALS; i++) {
++ if (peripheral_info[i].host_sel == hiedmac->id) {
++ if (count > 32) {
++ hiedmacv310_error("request table is not true!\n");
++ return -1;
++ }
++ if (misc != NULL) {
++ offset = hiedmac->misc_ctrl_base + (count & (~0x3));
++ regmap_read(misc, offset, &ctrl);
++ ctrl &= ~(0x3f << ((count & 0x3) << 3));
++ ctrl |= peripheral_info[i].peri_id << ((count & 0x3) << 3);
++ regmap_write(misc, offset, ctrl);
++ }
++ peripheral_info[i].dynamic_periphery_num = count;
++ count++;
++ }
++ }
+
-+ return 0;
++ return 0;
+}
+
+static int get_of_probe(struct hiedmac_host *hiedmac)
+{
-+ struct resource *res;
-+ struct platform_device *platdev = hiedmac->pdev;
-+ struct device_node *np = platdev->dev.of_node;
-+ int ret;
++ struct resource *res = NULL;
++ struct platform_device *platdev = hiedmac->pdev;
++ struct device_node *np = platdev->dev.of_node;
++ int ret;
+
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "devid", &(hiedmac->id));
-+ if (ret) {
-+ hiedmacv310_error("get hiedmac id fail\n");
-+ return -ENODEV;
-+ }
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "devid", &(hiedmac->id));
++ if (ret) {
++ hiedmacv310_error("get hiedmac id fail\n");
++ return -ENODEV;
++ }
+
-+ hiedmac->clk = devm_clk_get(&(platdev->dev), "apb_pclk");
-+ if (IS_ERR(hiedmac->clk)) {
-+ hiedmacv310_error("get hiedmac clk fail\n");
-+ return PTR_ERR(hiedmac->clk);
-+ }
++ hiedmac->clk = devm_clk_get(&(platdev->dev), "apb_pclk");
++ if (IS_ERR(hiedmac->clk)) {
++ hiedmacv310_error("get hiedmac clk fail\n");
++ return PTR_ERR(hiedmac->clk);
++ }
+
-+ hiedmac->axi_clk = devm_clk_get(&(platdev->dev), "axi_aclk");
-+ if (IS_ERR(hiedmac->axi_clk)) {
-+ hiedmacv310_error("get hiedmac axi clk fail\n");
-+ return PTR_ERR(hiedmac->axi_clk);
-+ }
++ hiedmac->axi_clk = devm_clk_get(&(platdev->dev), "axi_aclk");
++ if (IS_ERR(hiedmac->axi_clk)) {
++ hiedmacv310_error("get hiedmac axi clk fail\n");
++ return PTR_ERR(hiedmac->axi_clk);
++ }
+
-+ hiedmac->rstc = devm_reset_control_get(&(platdev->dev), "dma-reset");
-+ if (IS_ERR(hiedmac->rstc)) {
-+ hiedmacv310_error("get hiedmac rstc fail\n");
-+ return PTR_ERR(hiedmac->rstc);
-+ }
++ hiedmac->rstc = devm_reset_control_get(&(platdev->dev), "dma-reset");
++ if (IS_ERR(hiedmac->rstc)) {
++ hiedmacv310_error("get hiedmac rstc fail\n");
++ return PTR_ERR(hiedmac->rstc);
++ }
+
-+ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ hiedmacv310_error("no reg resource\n");
-+ return -ENODEV;
-+ }
++ res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ hiedmacv310_error("no reg resource\n");
++ return -ENODEV;
++ }
+
-+ hiedmac->base = devm_ioremap_resource(&(platdev->dev), res);
-+ if (IS_ERR(hiedmac->base)) {
-+ hiedmacv310_error("get hiedmac base fail\n");
-+ return PTR_ERR(hiedmac->base);
-+ }
++ hiedmac->base = devm_ioremap_resource(&(platdev->dev), res);
++ if (IS_ERR(hiedmac->base)) {
++ hiedmacv310_error("get hiedmac base fail\n");
++ return PTR_ERR(hiedmac->base);
++ }
+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
+ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
+ defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || \
-+ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
++ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+ hiedmac->misc_regmap = 0;
-+ np = np ;
++ (void)np ;
+#else
-+ hiedmac->misc_regmap = syscon_regmap_lookup_by_phandle(np, "misc_regmap");
-+ if (IS_ERR(hiedmac->misc_regmap)) {
-+ hiedmacv310_error("get hiedmac misc fail\n");
-+ return PTR_ERR(hiedmac->misc_regmap);
-+ }
++ hiedmac->misc_regmap = syscon_regmap_lookup_by_phandle(np, "misc_regmap");
++ if (IS_ERR(hiedmac->misc_regmap)) {
++ hiedmacv310_error("get hiedmac misc fail\n");
++ return PTR_ERR(hiedmac->misc_regmap);
++ }
+
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "misc_ctrl_base", &(hiedmac->misc_ctrl_base));
-+ if (ret) {
-+ hiedmacv310_error( "get dma-misc_ctrl_base fail\n");
-+ return -ENODEV;
-+ }
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "misc_ctrl_base", &(hiedmac->misc_ctrl_base));
++ if (ret) {
++ hiedmacv310_error( "get dma-misc_ctrl_base fail\n");
++ return -ENODEV;
++ }
+#endif
-+ hiedmac->irq = platform_get_irq(platdev, 0);
-+ if (unlikely(hiedmac->irq < 0)) {
-+ return -ENODEV;
-+ }
++ hiedmac->irq = platform_get_irq(platdev, 0);
++ if (unlikely(hiedmac->irq < 0)) {
++ return -ENODEV;
++ }
+
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "dma-channels", &(hiedmac->channels));
-+ if (ret) {
-+ hiedmacv310_error( "get dma-channels fail\n");
-+ return -ENODEV;
-+ }
-+ ret = of_property_read_u32((&platdev->dev)->of_node,
-+ "dma-requests", &(hiedmac->slave_requests));
-+ if (ret) {
-+ hiedmacv310_error( "get dma-requests fail\n");
-+ return -ENODEV;
-+ }
-+ hiedmacv310_trace(2, "dma-channels = %d, dma-requests = %d\n",
-+ hiedmac->channels, hiedmac->slave_requests);
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "dma-channels", &(hiedmac->channels));
++ if (ret) {
++ hiedmacv310_error( "get dma-channels fail\n");
++ return -ENODEV;
++ }
++ ret = of_property_read_u32((&platdev->dev)->of_node,
++ "dma-requests", &(hiedmac->slave_requests));
++ if (ret) {
++ hiedmacv310_error( "get dma-requests fail\n");
++ return -ENODEV;
++ }
++ hiedmacv310_trace(2, "dma-channels = %d, dma-requests = %d\n",
++ hiedmac->channels, hiedmac->slave_requests);
+
-+ hiedmac_priv_init(hiedmac, (edmac_peripheral*)&g_peripheral);
++ hiedmac_priv_init(hiedmac, (edmac_peripheral*)&g_peripheral);
+
-+ return 0;
++ return 0;
+}
+
+/* Don't need irq mode now */
+#if 0
+static irqreturn_t hiemdacv310_irq(int irq, void *dev)
+{
-+ struct hiedmac_host* hiedmac = (struct hiedmac_host*)dev;
-+ unsigned int channel_err_status[3];
-+ unsigned int channel_tc_status = 0;
-+ unsigned int channel_status = 0;
-+ unsigned int temp = 0;
-+ int i = 0;
-+ unsigned int mask = 0;
++ struct hiedmac_host* hiedmac = (struct hiedmac_host*)dev;
++ unsigned int channel_err_status[3];
++ unsigned int channel_tc_status = 0;
++ unsigned int channel_status = 0;
++ unsigned int temp = 0;
++ int i = 0;
++ unsigned int mask = 0;
+
-+ channel_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_STAT);
-+ if (!channel_status) {
-+ hiedmacv310_error("channel_status = 0x%x\n", channel_status);
-+ return IRQ_NONE;
-+ }
++ channel_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_STAT);
++ if (!channel_status) {
++ hiedmacv310_error("channel_status = 0x%x\n", channel_status);
++ return IRQ_NONE;
++ }
+
-+ for (i = 0; i < hiedmac->channels; i++) {
-+ temp = (channel_status >> i) & 0x1;
-+ if (temp) {
-+ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC1_RAW);
-+ channel_tc_status = (channel_tc_status >> i) & 0x01;
-+ if (channel_tc_status) {
-+ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC1_RAW);
-+ }
++ for (i = 0; i < hiedmac->channels; i++) {
++ temp = (channel_status >> i) & 0x1;
++ if (temp) {
++ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC1_RAW);
++ channel_tc_status = (channel_tc_status >> i) & 0x01;
++ if (channel_tc_status) {
++ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC1_RAW);
++ }
+
-+ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC2);
-+ channel_tc_status = (channel_tc_status >> i) & 0x01;
-+ if (channel_tc_status) {
-+ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC2_RAW);
-+ }
++ channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC2);
++ channel_tc_status = (channel_tc_status >> i) & 0x01;
++ if (channel_tc_status) {
++ hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC2_RAW);
++ }
+
-+ channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
-+ channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
-+ channel_err_status[1] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR2);
-+ channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
-+ channel_err_status[2] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR3);
-+ channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
++ channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
++ channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
++ channel_err_status[1] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR2);
++ channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
++ channel_err_status[2] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR3);
++ channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
+
-+ if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
-+ hiedmacv310_error("Error in hiedmac %d finish!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
-+ i, channel_err_status[0], channel_err_status[1], channel_err_status[2]);
-+ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
-+ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
-+ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
-+ }
-+ if ((function[i]) != NULL) {
-+ function[i](i, g_channel_status[i]);
-+ }
++ if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
++ hiedmacv310_error("Error in hiedmac %d finish!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
++ i, channel_err_status[0], channel_err_status[1], channel_err_status[2]);
++ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
++ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
++ hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
++ }
++ if ((function[i]) != NULL) {
++ function[i](i, g_channel_status[i]);
++ }
+
-+ mask |= (1 << i);
-+ }
-+ }
++ mask |= (1 << i);
++ }
++ }
+
-+ return mask ? IRQ_HANDLED : IRQ_NONE;
++ return mask ? IRQ_HANDLED : IRQ_NONE;
+}
+#endif
+
+static int __init hiedmacv310_probe(struct platform_device *pdev)
+{
-+ int ret = 0;
-+ int i = 0;
-+ struct hiedmac_host *hiedmac = NULL;
++ int ret = 0;
++ int i = 0;
++ struct hiedmac_host *hiedmac = NULL;
+
-+ hiedmac = kzalloc(sizeof(*hiedmac), GFP_KERNEL);
-+ if (!hiedmac) {
-+ hiedmacv310_error("malloc for hiedmac fail!");
-+ ret = -ENOMEM;
-+ return ret;
-+ }
-+ hiedmac->pdev = pdev;
++ hiedmac = kzalloc(sizeof(*hiedmac), GFP_KERNEL);
++ if (!hiedmac) {
++ hiedmacv310_error("malloc for hiedmac fail!");
++ ret = -ENOMEM;
++ return ret;
++ }
++ hiedmac->pdev = pdev;
+
-+ ret = get_of_probe(hiedmac);
-+ if (ret) {
-+ hiedmacv310_error("get dts info fail!");
-+ goto free_hiedmac;
-+ }
++ ret = get_of_probe(hiedmac);
++ if (ret) {
++ hiedmacv310_error("get dts info fail!");
++ goto free_hiedmac;
++ }
+
-+ clk_prepare_enable(hiedmac->clk);
-+ clk_prepare_enable(hiedmac->axi_clk);
++ clk_prepare_enable(hiedmac->clk);
++ clk_prepare_enable(hiedmac->axi_clk);
+
-+ reset_control_deassert(hiedmac->rstc);
++ reset_control_deassert(hiedmac->rstc);
+
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC1_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC2_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
-+ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC1_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC2_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
++ hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
+
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC1_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC2_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR1_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR2_MASK);
-+ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR3_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC1_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_TC2_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR1_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR2_MASK);
++ hiedmacv310_writel(HIEDMAC_INT_ENABLE_ALL_CHAN, hiedmac->base + HIEDMAC_INT_ERR3_MASK);
+
-+ for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++) {
-+ g_channel_status[i] = DMAC_CHN_VACANCY;
-+ }
++ for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++) {
++ g_channel_status[i] = DMAC_CHN_VACANCY;
++ }
+
-+ dma_regbase = hiedmac->base;
++ dma_regbase = hiedmac->base;
+
-+ ret = allocate_dmalli_space(&(hiedmac->pdev->dev), pllihead, HIEDMAC_LLI_PAGE_NUM);
-+ if (ret < 0) {
-+ goto free_hiedmac;
-+ }
++ ret = allocate_dmalli_space(&(hiedmac->pdev->dev), pllihead, HIEDMAC_LLI_PAGE_NUM);
++ if (ret < 0) {
++ goto free_hiedmac;
++ }
+
+#if 0
-+ /* register irq if necessary ! */
-+ ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
-+ if (ret) {
-+ hiedmacv310_error("fail to request irq");
-+ goto free_hiedmac;
-+ }
++ /* register irq if necessary ! */
++ ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
++ if (ret) {
++ hiedmacv310_error("fail to request irq");
++ goto free_hiedmac;
++ }
+#endif
-+ return 0;
++ return 0;
+
+free_hiedmac:
-+ kfree(hiedmac);
++ kfree(hiedmac);
+
-+ return ret;
++ return ret;
+}
+
+
+static int hiemda_remove(struct platform_device *pdev)
+{
-+ int err = 0;
-+ return err;
++ int err = 0;
++ return err;
+}
+
+
+static const struct of_device_id hiedmacv310_match[] = {
-+ { .compatible = "hisilicon,hiedmacv310_n" },
-+ {},
++ { .compatible = "hisilicon,hiedmacv310_n" },
++ {},
+};
+
+
+static struct platform_driver hiedmacv310_driver = {
-+ .remove = hiemda_remove,
-+ .driver = {
-+ .name = "hiedmacv310_n",
-+ .of_match_table = hiedmacv310_match,
-+ },
++ .remove = hiemda_remove,
++ .driver = {
++ .name = "hiedmacv310_n",
++ .of_match_table = hiedmacv310_match,
++ },
+};
+
+static int __init hiedmacv310_init(void)
+{
-+ return platform_driver_probe(&hiedmacv310_driver, hiedmacv310_probe);
++ return platform_driver_probe(&hiedmacv310_driver, hiedmacv310_probe);
+}
+subsys_initcall(hiedmacv310_init);
+
+static void __exit hiedmacv310_exit(void)
+{
-+ platform_driver_unregister(&hiedmacv310_driver);
++ platform_driver_unregister(&hiedmacv310_driver);
+}
+module_exit(hiedmacv310_exit);
+
@@ -266602,7 +334561,7 @@ index 0000000..63bfce6
+MODULE_AUTHOR("Hisilicon");
diff --git a/drivers/hiedmac/hiedmacv310.h b/drivers/hiedmac/hiedmacv310.h
new file mode 100644
-index 0000000..dc988fa
+index 0000000..1a5f09c
--- /dev/null
+++ b/drivers/hiedmac/hiedmacv310.h
@@ -0,0 +1,192 @@
@@ -266769,20 +334728,20 @@ index 0000000..dc988fa
+
+/* DMAC peripheral structure */
+typedef struct edmac_peripheral {
-+ /* peripherial ID */
-+ unsigned int peri_id;
-+ /* peripheral data register address */
-+ unsigned long peri_addr;
-+ /* config requset */
-+ int host_sel;
++ /* peripherial ID */
++ unsigned int peri_id;
++ /* peripheral data register address */
++ unsigned long peri_addr;
++ /* config requset */
++ int host_sel;
+#define DMAC_HOST0 0
+#define DMAC_HOST1 1
+#define DMAC_NOT_USE (-1)
-+ /* default channel configuration word */
-+ unsigned int transfer_cfg;
-+ /* default channel configuration word */
-+ unsigned int transfer_width;
-+ unsigned int dynamic_periphery_num;
++ /* default channel configuration word */
++ unsigned int transfer_cfg;
++ /* default channel configuration word */
++ unsigned int transfer_width;
++ unsigned int dynamic_periphery_num;
+} edmac_peripheral;
+
+
@@ -266847,208 +334806,203 @@ index 0000000..eefda7f
+obj-$(CONFIG_CMA) += hi_cma.o
diff --git a/drivers/hisilicon/cma/hi_cma.c b/drivers/hisilicon/cma/hi_cma.c
new file mode 100644
-index 0000000..f88254d
+index 0000000..8830558
--- /dev/null
+++ b/drivers/hisilicon/cma/hi_cma.c
-@@ -0,0 +1,198 @@
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dma-contiguous.h>
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/cma.h>
-+
-+#define NAME_LEN_MAX 64
-+#define ZONE_MAX 64
-+
-+struct cma_zone {
-+ struct device pdev;
-+ char name[NAME_LEN_MAX];
-+ gfp_t gfp;
-+ phys_addr_t phys_start;
-+ phys_addr_t nbytes;
-+ u32 alloc_type;
-+ u32 block_align;
-+};
+@@ -0,0 +1,193 @@
++/*
++ * hi_cma.c
++ *
++ * Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++#include <linux/hi_cma.h>
+
+static u32 num_zones;
+static struct cma_zone hisi_zone[ZONE_MAX];
-+
+static int use_bootargs;
+
+unsigned int get_cma_size(void)
+{
-+ int i;
-+ u64 total = 0;
++ int i;
++ u64 total = 0;
+
-+ for (i = 0; i < num_zones; i++) {
-+ total += hisi_zone[i].nbytes;
-+ }
++ for (i = 0; i < num_zones; i++) {
++ total += hisi_zone[i].nbytes;
++ }
+
-+ /* unit is M */
-+ return (unsigned int)(total >> 20);
++ /* unit is M */
++ return (unsigned int)(total >> 20);
+}
+
+int is_hicma_address(phys_addr_t phys, unsigned long size)
+{
-+ phys_addr_t start, end;
-+ int i;
++ phys_addr_t start, end;
++ int i;
+
-+ for (i = 0; i < num_zones; i++) {
-+ start = hisi_zone[i].phys_start;
-+ end = hisi_zone[i].phys_start + hisi_zone[i].nbytes;
++ for (i = 0; i < num_zones; i++) {
++ start = hisi_zone[i].phys_start;
++ end = hisi_zone[i].phys_start + hisi_zone[i].nbytes;
+
-+ if ((phys >= start) && ((phys + size) <= end)) {
-+ /*
-+ * Yes, found!
-+ */
-+ return 1;
-+ }
-+ }
++ if ((phys >= start) && ((phys + size) <= end)) {
++ /*
++ * Yes, found!
++ */
++ return 1;
++ }
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(is_hicma_address);
+
+static int __init hisi_mmz_parse_cmdline(char *s)
+{
-+ char *line, *tmp;
-+ char tmpline[256];
++ char *line = NULL;
++ char *tmp = NULL;
++ char tmpline[256];
+
-+ if (s == NULL) {
-+ pr_info("There is no cma zone!\n");
-+ return 0;
-+ }
-+ strncpy(tmpline, s, sizeof(tmpline));
-+ tmpline[sizeof(tmpline) - 1] = '\0';
-+ tmp = tmpline;
++ if (s == NULL) {
++ pr_info("There is no cma zone!\n");
++ return 0;
++ }
++ strncpy(tmpline, s, sizeof(tmpline));
++ tmpline[sizeof(tmpline) - 1] = '\0';
++ tmp = tmpline;
+
-+ while ((line = strsep(&tmp, ":")) != NULL) {
-+ int i;
-+ char *argv[6];
++ while ((line = strsep(&tmp, ":")) != NULL) {
++ int i;
++ char *argv[6];
+
-+ for (i = 0; (argv[i] = strsep(&line, ",")) != NULL;)
-+ if (++i == ARRAY_SIZE(argv)) {
-+ break;
-+ }
++ for (i = 0; (argv[i] = strsep(&line, ",")) != NULL;)
++ if (++i == ARRAY_SIZE(argv)) {
++ break;
++ }
+
-+ hisi_zone[num_zones].pdev.coherent_dma_mask = DMA_BIT_MASK(64);
-+ if (i == 4) {
-+ strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
-+ hisi_zone[num_zones].gfp = memparse(argv[1], NULL);
-+ hisi_zone[num_zones].phys_start = memparse(argv[2], NULL);
-+ hisi_zone[num_zones].nbytes = memparse(argv[3], NULL);
-+ }
++ hisi_zone[num_zones].pdev.coherent_dma_mask = DMA_BIT_MASK(64);
++ if (i == 4) {
++ strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
++ hisi_zone[num_zones].gfp = memparse(argv[1], NULL);
++ hisi_zone[num_zones].phys_start = memparse(argv[2], NULL);
++ hisi_zone[num_zones].nbytes = memparse(argv[3], NULL);
++ }
+
-+ else if (i == 6) {
-+ strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
-+ hisi_zone[num_zones].gfp = memparse(argv[1], NULL);
-+ hisi_zone[num_zones].phys_start = memparse(argv[2], NULL);
-+ hisi_zone[num_zones].nbytes = memparse(argv[3], NULL);
-+ hisi_zone[num_zones].alloc_type = memparse(argv[4], NULL);
-+ hisi_zone[num_zones].block_align = memparse(argv[5], NULL);
-+ } else {
-+ pr_err("hisi ion parameter is not correct\n");
-+ continue;
-+ }
++ else if (i == 6) {
++ strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
++ hisi_zone[num_zones].gfp = memparse(argv[1], NULL);
++ hisi_zone[num_zones].phys_start = memparse(argv[2], NULL);
++ hisi_zone[num_zones].nbytes = memparse(argv[3], NULL);
++ hisi_zone[num_zones].alloc_type = memparse(argv[4], NULL);
++ hisi_zone[num_zones].block_align = memparse(argv[5], NULL);
++ } else {
++ pr_err("hisi ion parameter is not correct\n");
++ continue;
++ }
+
-+ num_zones++;
-+ }
-+ if (num_zones != 0) {
-+ use_bootargs = 1;
-+ }
++ num_zones++;
++ }
++ if (num_zones != 0) {
++ use_bootargs = 1;
++ }
+
-+ return 0;
++ return 0;
+}
+early_param("mmz", hisi_mmz_parse_cmdline);
+
-+#include <linux/memblock.h>
+phys_addr_t hisi_get_zones_start(void)
+{
-+ int i;
-+ phys_addr_t lowest_zone_base = memblock_end_of_DRAM();
++ int i;
++ phys_addr_t lowest_zone_base = memblock_end_of_DRAM();
+
-+ for (i = 0; i < num_zones; i++) {
-+ if (lowest_zone_base > hisi_zone[i].phys_start) {
-+ lowest_zone_base = hisi_zone[i].phys_start;
-+ }
-+ }
++ for (i = 0; i < num_zones; i++) {
++ if (lowest_zone_base > hisi_zone[i].phys_start) {
++ lowest_zone_base = hisi_zone[i].phys_start;
++ }
++ }
+
-+ return lowest_zone_base;
++ return lowest_zone_base;
+}
+EXPORT_SYMBOL(hisi_get_zones_start);
+
+struct cma_zone *hisi_get_cma_zone(const char *name)
+{
-+ int i = 0;
++ int i = 0;
+
-+ for (i = 0; i < num_zones; i++)
-+ if (strcmp(hisi_zone[i].name, name) == 0) {
-+ break;
-+ }
++ for (i = 0; i < num_zones; i++)
++ if (strcmp(hisi_zone[i].name, name) == 0) {
++ break;
++ }
+
-+ if (i == num_zones) {
-+ return NULL;
-+ }
++ if (i == num_zones) {
++ return NULL;
++ }
+
-+ return &hisi_zone[i];
++ return &hisi_zone[i];
+}
+EXPORT_SYMBOL(hisi_get_cma_zone);
+
+struct device *hisi_get_cma_device(const char *name)
+{
-+ int i = 0;
++ int i = 0;
+
-+ for (i = 0; i < num_zones; i++)
-+ if (strcmp(hisi_zone[i].name, name) == 0) {
-+ break;
-+ }
++ for (i = 0; i < num_zones; i++)
++ if (strcmp(hisi_zone[i].name, name) == 0) {
++ break;
++ }
+
-+ if (i == num_zones) {
-+ return NULL;
-+ }
++ if (i == num_zones) {
++ return NULL;
++ }
+
-+ return &hisi_zone[i].pdev;
++ return &hisi_zone[i].pdev;
+}
+EXPORT_SYMBOL(hisi_get_cma_device);
+
+int __init hisi_declare_heap_memory(void)
+{
-+ int i;
-+ int ret = 0;
++ int i;
++ int ret = 0;
+
-+ if (use_bootargs == 0) {
-+ pr_info("cmz zone is not set!\n");
-+ return ret;
-+ }
++ if (use_bootargs == 0) {
++ pr_info("cma zone is not set!\n");
++ return ret;
++ }
+
-+ for (i = 0; i < num_zones; i++) {
-+ ret = dma_declare_contiguous(&hisi_zone[i].pdev,
-+ hisi_zone[i].nbytes, hisi_zone[i].phys_start, 0);
-+ if (ret) {
-+ panic("declare cma zone %s base: %lux size:%lux MB failed. ret:%d",
-+ hisi_zone[i].name, (unsigned long)hisi_zone[i].phys_start,
-+ (unsigned long)hisi_zone[i].nbytes >> 20, ret);
-+ }
-+ hisi_zone[i].phys_start = cma_get_base(hisi_zone[i].pdev.cma_area);
-+ hisi_zone[i].nbytes = cma_get_size(hisi_zone[i].pdev.cma_area);
++ for (i = 0; i < num_zones; i++) {
++ ret = dma_declare_contiguous(&hisi_zone[i].pdev,
++ hisi_zone[i].nbytes, hisi_zone[i].phys_start, 0);
++ if (ret) {
++ panic("declare cma zone %s base: %lux size:%lux MB failed. ret:%d",
++ hisi_zone[i].name, (unsigned long)hisi_zone[i].phys_start,
++ (unsigned long)hisi_zone[i].nbytes >> 20, ret);
++ }
++ hisi_zone[i].phys_start = cma_get_base(hisi_zone[i].pdev.cma_area);
++ hisi_zone[i].nbytes = cma_get_size(hisi_zone[i].pdev.cma_area);
+
-+ /* FIXME need to fix dma_declare_contiguous return value &&value type */
-+ }
++ /* FIXME need to fix dma_declare_contiguous return value &&value type */
++ }
+
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(hisi_declare_heap_memory);
+
-+#include <linux/of.h>
-+#include <linux/of_fdt.h>
-+#include <linux/of_reserved_mem.h>
+static int hisi_mmz_setup(struct reserved_mem *rmem)
+{
-+ return 0;
++ return 0;
+}
+RESERVEDMEM_OF_DECLARE(cma, "hisi-mmz", hisi_mmz_setup);
-+
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d252276..a6473c8 100644
--- a/drivers/i2c/busses/Kconfig
@@ -267120,16 +335074,15 @@ index 29764cc..f96cde3 100644
ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
diff --git a/drivers/i2c/busses/i2c-hibvt.c b/drivers/i2c/busses/i2c-hibvt.c
new file mode 100644
-index 0000000..da38db1
+index 0000000..f71465d
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hibvt.c
-@@ -0,0 +1,1144 @@
+@@ -0,0 +1,1156 @@
+/*
+ * Hisilicon BVT I2C Controller Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
-+ * Authors: wenpan@hisilicon.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -267248,26 +335201,26 @@ index 0000000..da38db1
+
+
+struct hibvt_i2c_dev {
-+ struct device *dev;
-+ struct i2c_adapter adap;
-+ resource_size_t phybase;
-+ void __iomem *base;
-+ struct clk *clk;
-+ int irq;
++ struct device *dev;
++ struct i2c_adapter adap;
++ resource_size_t phybase;
++ void __iomem *base;
++ struct clk *clk;
++ int irq;
+
-+ unsigned int freq;
-+ struct i2c_msg *msg;
-+ unsigned int msg_num;
-+ unsigned int msg_idx;
-+ unsigned int msg_buf_ptr;
-+ struct completion msg_complete;
++ unsigned int freq;
++ struct i2c_msg *msg;
++ unsigned int msg_num;
++ unsigned int msg_idx;
++ unsigned int msg_buf_ptr;
++ struct completion msg_complete;
+
-+ spinlock_t lock;
-+ int status;
++ spinlock_t lock;
++ int status;
+};
+static inline void hibvt_i2c_disable(struct hibvt_i2c_dev *i2c);
+static inline void hibvt_i2c_cfg_irq(struct hibvt_i2c_dev *i2c,
-+ unsigned int flag);
++ unsigned int flag);
+static inline unsigned int hibvt_i2c_clr_irq(struct hibvt_i2c_dev *i2c);
+static inline void hibvt_i2c_enable(struct hibvt_i2c_dev *i2c);
+
@@ -267278,108 +335231,108 @@ index 0000000..da38db1
+
+static void hibvt_i2c_rescue(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int val;
-+ unsigned int time_cnt;
-+ int index;
++ unsigned int val;
++ unsigned int time_cnt;
++ int index;
+
-+ hibvt_i2c_disable(i2c);
-+ hibvt_i2c_cfg_irq(i2c, 0);
-+ hibvt_i2c_clr_irq(i2c);
++ hibvt_i2c_disable(i2c);
++ hibvt_i2c_cfg_irq(i2c, 0);
++ hibvt_i2c_clr_irq(i2c);
+
-+ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
-+ writel(val, i2c->base + HIBVT_I2C_CTRL2);
++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
++ writel(val, i2c->base + HIBVT_I2C_CTRL2);
+
-+ time_cnt = 0;
-+ do {
-+ for (index = 0; index < 9; index++) {
-+ val = (0x1 << GPIO_MODE_SHIFT) | 0x1;
-+ writel(val, i2c->base + HIBVT_I2C_CTRL2);
++ time_cnt = 0;
++ do {
++ for (index = 0; index < 9; index++) {
++ val = (0x1 << GPIO_MODE_SHIFT) | 0x1;
++ writel(val, i2c->base + HIBVT_I2C_CTRL2);
+
-+ udelay(5);
++ udelay(5);
+
-+ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
-+ writel(val, i2c->base + HIBVT_I2C_CTRL2);
++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
++ writel(val, i2c->base + HIBVT_I2C_CTRL2);
+
-+ udelay(5);
-+ }
++ udelay(5);
++ }
+
-+ time_cnt++;
-+ if (time_cnt > I2C_WAIT_TIMEOUT) {
-+ dev_err(i2c->dev, "wait Timeout!\n");
-+ goto disable_rescue;
-+ }
++ time_cnt++;
++ if (time_cnt > I2C_WAIT_TIMEOUT) {
++ dev_err(i2c->dev, "wait Timeout!\n");
++ goto disable_rescue;
++ }
+
-+ val = readl(i2c->base + HIBVT_I2C_CTRL2);
-+ } while(!(val & (0x1 << CHECK_SDA_IN_SHIFT)));
++ val = readl(i2c->base + HIBVT_I2C_CTRL2);
++ } while(!(val & (0x1 << CHECK_SDA_IN_SHIFT)));
+
+
-+ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
-+ writel(val, i2c->base + HIBVT_I2C_CTRL2);
++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
++ writel(val, i2c->base + HIBVT_I2C_CTRL2);
+
-+ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT);
-+ writel(val, i2c->base + HIBVT_I2C_CTRL2);
++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT);
++ writel(val, i2c->base + HIBVT_I2C_CTRL2);
+
-+ udelay(10);
++ udelay(10);
+
-+ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
-+ writel(val, i2c->base + HIBVT_I2C_CTRL2);
++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | (0x1 << FORCE_SDA_OEN_SHIFT);
++ writel(val, i2c->base + HIBVT_I2C_CTRL2);
+
+disable_rescue:
-+ val = (0x1 << FORCE_SCL_OEN_SHIFT) | 0x1;
-+ writel(val, i2c->base + HIBVT_I2C_CTRL2);
++ val = (0x1 << FORCE_SCL_OEN_SHIFT) | 0x1;
++ writel(val, i2c->base + HIBVT_I2C_CTRL2);
+}
+
+static inline void hibvt_i2c_disable(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(i2c->base + HIBVT_I2C_GLB);
-+ val &= ~GLB_EN_MASK;
-+ writel(val, i2c->base + HIBVT_I2C_GLB);
++ val = readl(i2c->base + HIBVT_I2C_GLB);
++ val &= ~GLB_EN_MASK;
++ writel(val, i2c->base + HIBVT_I2C_GLB);
+}
+
+static inline void hibvt_i2c_enable(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(i2c->base + HIBVT_I2C_GLB);
-+ val |= GLB_EN_MASK;
-+ writel(val, i2c->base + HIBVT_I2C_GLB);
++ val = readl(i2c->base + HIBVT_I2C_GLB);
++ val |= GLB_EN_MASK;
++ writel(val, i2c->base + HIBVT_I2C_GLB);
+}
+
+static inline void hibvt_i2c_cfg_irq(struct hibvt_i2c_dev *i2c,
-+ unsigned int flag)
++ unsigned int flag)
+{
-+ writel(flag, i2c->base + HIBVT_I2C_INTR_EN);
++ writel(flag, i2c->base + HIBVT_I2C_INTR_EN);
+}
+
+static inline void hibvt_i2c_disable_irq(struct hibvt_i2c_dev *i2c,
-+ unsigned int flag)
++ unsigned int flag)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(i2c->base + HIBVT_I2C_INTR_EN);
-+ val &= ~flag;
-+ writel(val, i2c->base + HIBVT_I2C_INTR_EN);
++ val = readl(i2c->base + HIBVT_I2C_INTR_EN);
++ val &= ~flag;
++ writel(val, i2c->base + HIBVT_I2C_INTR_EN);
+}
+
+static inline unsigned int hibvt_i2c_clr_irq(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(i2c->base + HIBVT_I2C_INTR_STAT);
-+ writel(INTR_ALL_MASK, i2c->base + HIBVT_I2C_INTR_RAW);
++ val = readl(i2c->base + HIBVT_I2C_INTR_STAT);
++ writel(INTR_ALL_MASK, i2c->base + HIBVT_I2C_INTR_RAW);
+
-+ return val;
++ return val;
+}
+
+static inline void hibvt_i2c_cmdreg_set(struct hibvt_i2c_dev *i2c,
-+ unsigned int cmd, unsigned int *offset)
++ unsigned int cmd, unsigned int *offset)
+{
-+ dev_dbg(i2c->dev, "hii2c reg: offset=0x%x, cmd=0x%x...\n",
-+ *offset * 4, cmd);
-+ writel(cmd, i2c->base + HIBVT_I2C_CMD_BASE + *offset * 4);
-+ (*offset)++;
++ dev_dbg(i2c->dev, "hii2c reg: offset=0x%x, cmd=0x%x...\n",
++ *offset * 4, cmd);
++ writel(cmd, i2c->base + HIBVT_I2C_CMD_BASE + *offset * 4);
++ (*offset)++;
+}
+
+/*
@@ -267387,26 +335340,26 @@ index 0000000..da38db1
+ */
+static inline void hibvt_i2c_set_addr(struct hibvt_i2c_dev *i2c)
+{
-+ struct i2c_msg *msg = i2c->msg;
-+ u16 addr;
++ struct i2c_msg *msg = i2c->msg;
++ u16 addr;
+
-+ if (msg->flags & I2C_M_TEN) {
-+ /* First byte is 11110XX0 where XX is upper 2 bits */
-+ addr = ((msg->addr & 0x300) << 1) | 0xf000;
-+ if (msg->flags & I2C_M_RD) {
-+ addr |= 1 << 8;
-+ }
++ if (msg->flags & I2C_M_TEN) {
++ /* First byte is 11110XX0 where XX is upper 2 bits */
++ addr = ((msg->addr & 0x300) << 1) | 0xf000;
++ if (msg->flags & I2C_M_RD) {
++ addr |= 1 << 8;
++ }
+
-+ /* Second byte is the remaining 8 bits */
-+ addr |= msg->addr & 0xff;
-+ } else {
-+ addr = (msg->addr & 0x7f) << 1;
-+ if (msg->flags & I2C_M_RD) {
-+ addr |= 1;
-+ }
-+ }
++ /* Second byte is the remaining 8 bits */
++ addr |= msg->addr & 0xff;
++ } else {
++ addr = (msg->addr & 0x7f) << 1;
++ if (msg->flags & I2C_M_RD) {
++ addr |= 1;
++ }
++ }
+
-+ writel(addr, i2c->base + HIBVT_I2C_DATA1);
++ writel(addr, i2c->base + HIBVT_I2C_DATA1);
+}
+
+/*
@@ -267414,118 +335367,126 @@ index 0000000..da38db1
+ */
+static inline void hibvt_i2c_start_cmd(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(i2c->base + HIBVT_I2C_CTRL1);
-+ val |= CTRL1_CMD_START_MASK;
-+ writel(val, i2c->base + HIBVT_I2C_CTRL1);
++ val = readl(i2c->base + HIBVT_I2C_CTRL1);
++ val |= CTRL1_CMD_START_MASK;
++ writel(val, i2c->base + HIBVT_I2C_CTRL1);
+}
+
+static int hibvt_i2c_wait_rx_noempty(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int time_cnt = 0;
-+ unsigned int val;
++ unsigned int time_cnt = 0;
++ unsigned int val;
+
-+ do {
-+ val = readl(i2c->base + HIBVT_I2C_STAT);
-+ if (val & STAT_RXF_NOE_MASK) {
-+ return 0;
-+ }
++ do {
++ val = readl(i2c->base + HIBVT_I2C_STAT);
++ if (val & STAT_RXF_NOE_MASK) {
++ return 0;
++ }
+
-+ udelay(50);
-+ } while (time_cnt++ < I2C_WAIT_TIMEOUT);
++ udelay(50);
++ } while (time_cnt++ < I2C_WAIT_TIMEOUT);
+
-+ hibvt_i2c_rescue(i2c);
++ hibvt_i2c_rescue(i2c);
+
-+ dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
-+ readl(i2c->base + HIBVT_I2C_INTR_RAW), val);
-+ return -EIO;
++ dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
++ readl(i2c->base + HIBVT_I2C_INTR_RAW), val);
++ return -EIO;
+}
+
+static int hibvt_i2c_wait_tx_nofull(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int time_cnt = 0;
-+ unsigned int val;
++ unsigned int time_cnt = 0;
++ unsigned int val;
+
-+ do {
-+ val = readl(i2c->base + HIBVT_I2C_STAT);
-+ if (val & STAT_TXF_NOF_MASK) {
-+ return 0;
-+ }
++ do {
++ val = readl(i2c->base + HIBVT_I2C_STAT);
++ if (val & STAT_TXF_NOF_MASK) {
++ return 0;
++ }
+
-+ udelay(50);
-+ } while (time_cnt++ < I2C_WAIT_TIMEOUT);
++ udelay(50);
++ } while (time_cnt++ < I2C_WAIT_TIMEOUT);
+
-+ hibvt_i2c_rescue(i2c);
++ hibvt_i2c_rescue(i2c);
+
-+ dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
-+ readl(i2c->base + HIBVT_I2C_INTR_RAW), val);
-+ return -EIO;
++ dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
++ readl(i2c->base + HIBVT_I2C_INTR_RAW), val);
++ return -EIO;
+}
+
+static int hibvt_i2c_wait_idle(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int time_cnt = 0;
-+ unsigned int val;
++ unsigned int time_cnt = 0;
++ unsigned int val;
+
-+ do {
-+ val = readl(i2c->base + HIBVT_I2C_INTR_RAW);
-+ if (val & (INTR_ABORT_MASK)) {
-+ dev_err(i2c->dev, "wait idle abort!, RIS: 0x%x\n",
-+ val);
-+ return -EIO;
-+ }
++ do {
++ val = readl(i2c->base + HIBVT_I2C_INTR_RAW);
++ if (val & (INTR_ABORT_MASK)) {
++ dev_err(i2c->dev, "wait idle abort!, RIS: 0x%x\n",
++ val);
++ return -EIO;
++ }
+
-+ if (val & INTR_CMD_DONE_MASK) {
-+ return 0;
-+ }
++ if (val & INTR_CMD_DONE_MASK) {
++ return 0;
++ }
+
-+ udelay(50);
-+ } while (time_cnt++ < I2C_WAIT_TIMEOUT);
++ udelay(50);
++ } while (time_cnt++ < I2C_WAIT_TIMEOUT);
+
-+ hibvt_i2c_rescue(i2c);
++ hibvt_i2c_rescue(i2c);
+
-+ dev_err(i2c->dev, "wait idle timeout, RIS: 0x%x, SR: 0x%x\n",
-+ val, readl(i2c->base + HIBVT_I2C_STAT));
++ dev_err(i2c->dev, "wait idle timeout, RIS: 0x%x, SR: 0x%x\n",
++ val, readl(i2c->base + HIBVT_I2C_STAT));
+
-+ return -EIO;
++ return -EIO;
+}
+
+static void hibvt_i2c_set_freq(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int max_freq, freq;
-+ unsigned int clk_rate;
-+ unsigned int val;
++ unsigned int max_freq, freq;
++ unsigned int clk_rate;
++ unsigned int val;
+
-+ freq = i2c->freq;
-+ clk_rate = clk_get_rate(i2c->clk);
-+ max_freq = clk_rate >> 1;
++ freq = i2c->freq;
++ clk_rate = clk_get_rate(i2c->clk);
++ max_freq = clk_rate >> 1;
+
-+ if (freq > max_freq) {
-+ i2c->freq = max_freq;
-+ freq = i2c->freq;
-+ }
++ if (freq > max_freq) {
++ i2c->freq = max_freq;
++ freq = i2c->freq;
++ }
+
-+ if (!freq) {
-+ pr_err("hibvt_i2c_set_freq:freq can't be zero!");
-+ return;
-+ }
++ if (!freq) {
++ pr_err("hibvt_i2c_set_freq:freq can't be zero!");
++ return;
++ }
+
-+ if (freq <= 100000) {
-+ val = clk_rate / (freq * 2);
-+ writel(val, i2c->base + HIBVT_I2C_SCL_H);
-+ writel(val, i2c->base + HIBVT_I2C_SCL_L);
-+ } else {
-+ val = (clk_rate * 36) / (freq * 100);
-+ writel(val, i2c->base + HIBVT_I2C_SCL_H);
-+ val = (clk_rate * 64) / (freq * 100);
-+ writel(val, i2c->base + HIBVT_I2C_SCL_L);
-+ }
++ if (freq <= 100000) {
++ /* in normal mode F_scl: freq
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5
++ */
++ val = clk_rate / (freq * 2);
++ writel(val, i2c->base + HIBVT_I2C_SCL_H);
++ writel(val, i2c->base + HIBVT_I2C_SCL_L);
++ } else {
++ /* in fast mode F_scl: freq
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.36
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.64
++ */
++ val = ((clk_rate / 100) * 36) / freq;
++ writel(val, i2c->base + HIBVT_I2C_SCL_H);
++ val = ((clk_rate / 100) * 64) / freq;
++ writel(val, i2c->base + HIBVT_I2C_SCL_L);
++ }
+
-+ val = readl(i2c->base + HIBVT_I2C_GLB);
-+ val &= ~GLB_SDA_HOLD_MASK;
-+ val |= ((0xa << GLB_SDA_HOLD_SHIFT) & GLB_SDA_HOLD_MASK);
-+ writel(val, i2c->base + HIBVT_I2C_GLB);
++ val = readl(i2c->base + HIBVT_I2C_GLB);
++ val &= ~GLB_SDA_HOLD_MASK;
++ val |= ((0xa << GLB_SDA_HOLD_SHIFT) & GLB_SDA_HOLD_MASK);
++ writel(val, i2c->base + HIBVT_I2C_GLB);
+}
+
+/*
@@ -267533,8 +335494,8 @@ index 0000000..da38db1
+ */
+static inline void hibvt_i2c_set_water(struct hibvt_i2c_dev *i2c)
+{
-+ writel(I2C_TXF_WATER, i2c->base + HIBVT_I2C_TX_WATER);
-+ writel(I2C_RXF_WATER, i2c->base + HIBVT_I2C_RX_WATER);
++ writel(I2C_TXF_WATER, i2c->base + HIBVT_I2C_TX_WATER);
++ writel(I2C_RXF_WATER, i2c->base + HIBVT_I2C_RX_WATER);
+}
+
+/*
@@ -267542,10 +335503,10 @@ index 0000000..da38db1
+ */
+static void hibvt_i2c_hw_init(struct hibvt_i2c_dev *i2c)
+{
-+ hibvt_i2c_disable(i2c);
-+ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
-+ hibvt_i2c_set_freq(i2c);
-+ hibvt_i2c_set_water(i2c);
++ hibvt_i2c_disable(i2c);
++ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
++ hibvt_i2c_set_freq(i2c);
++ hibvt_i2c_set_water(i2c);
+}
+
+/*
@@ -267557,428 +335518,428 @@ index 0000000..da38db1
+ */
+static void hibvt_i2c_cfg_cmd(struct hibvt_i2c_dev *i2c)
+{
-+ struct i2c_msg *msg = i2c->msg;
-+ int offset = 0;
++ struct i2c_msg *msg = i2c->msg;
++ int offset = 0;
+
-+ if (i2c->msg_idx == 0) {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_S, &offset);
-+ } else {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_RS, &offset);
-+ }
++ if (i2c->msg_idx == 0) {
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_S, &offset);
++ } else {
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_RS, &offset);
++ }
+
-+ if (msg->flags & I2C_M_TEN) {
-+ if (i2c->msg_idx == 0) {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset);
-+ } else {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset);
-+ }
-+ } else {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset);
-+ }
++ if (msg->flags & I2C_M_TEN) {
++ if (i2c->msg_idx == 0) {
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset);
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset);
++ } else {
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset);
++ }
++ } else {
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset);
++ }
+
-+ if (msg->flags & I2C_M_IGNORE_NAK) {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset);
-+ } else {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset);
-+ }
++ if (msg->flags & I2C_M_IGNORE_NAK) {
++ hibvt_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset);
++ } else {
++ hibvt_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset);
++ }
+
-+ if (msg->flags & I2C_M_RD) {
-+ if (msg->len >= 2) {
-+ writel(offset, i2c->base + HIBVT_I2C_DST1);
-+ writel(msg->len - 2, i2c->base + HIBVT_I2C_LOOP1);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_ACK, &offset);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_JMP1, &offset);
-+ }
-+ hibvt_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_NACK, &offset);
-+ } else {
-+ writel(offset, i2c->base + HIBVT_I2C_DST1);
-+ writel(msg->len - 1, i2c->base + HIBVT_I2C_LOOP1);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_UP_TXF, &offset);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_FIFO, &offset);
++ if (msg->flags & I2C_M_RD) {
++ if (msg->len >= 2) {
++ writel(offset, i2c->base + HIBVT_I2C_DST1);
++ writel(msg->len - 2, i2c->base + HIBVT_I2C_LOOP1);
++ hibvt_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset);
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_ACK, &offset);
++ hibvt_i2c_cmdreg_set(i2c, CMD_JMP1, &offset);
++ }
++ hibvt_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset);
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_NACK, &offset);
++ } else {
++ writel(offset, i2c->base + HIBVT_I2C_DST1);
++ writel(msg->len - 1, i2c->base + HIBVT_I2C_LOOP1);
++ hibvt_i2c_cmdreg_set(i2c, CMD_UP_TXF, &offset);
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_FIFO, &offset);
+
-+ if (msg->flags & I2C_M_IGNORE_NAK) {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset);
-+ } else {
-+ hibvt_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset);
-+ }
++ if (msg->flags & I2C_M_IGNORE_NAK) {
++ hibvt_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset);
++ } else {
++ hibvt_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset);
++ }
+
-+ hibvt_i2c_cmdreg_set(i2c, CMD_JMP1, &offset);
-+ }
++ hibvt_i2c_cmdreg_set(i2c, CMD_JMP1, &offset);
++ }
+
-+ if ((i2c->msg_idx == (i2c->msg_num - 1)) || (msg->flags & I2C_M_STOP)) {
-+ dev_dbg(i2c->dev, "run to %s %d...TX STOP\n",
-+ __func__, __LINE__);
-+ hibvt_i2c_cmdreg_set(i2c, CMD_TX_P, &offset);
-+ }
++ if ((i2c->msg_idx == (i2c->msg_num - 1)) || (msg->flags & I2C_M_STOP)) {
++ dev_dbg(i2c->dev, "run to %s %d...TX STOP\n",
++ __func__, __LINE__);
++ hibvt_i2c_cmdreg_set(i2c, CMD_TX_P, &offset);
++ }
+
-+ hibvt_i2c_cmdreg_set(i2c, CMD_EXIT, &offset);
++ hibvt_i2c_cmdreg_set(i2c, CMD_EXIT, &offset);
+}
+
+#if defined(CONFIG_HI_DMAC) || defined(CONFIG_HIEDMAC)
+int dma_to_i2c(unsigned long src, unsigned int dst, unsigned int length)
+{
-+ int chan;
++ int chan;
+
-+ chan = do_dma_m2p(src, dst, length);
-+ if (chan == -1) {
-+ pr_err("dma_to_i2c error\n");
-+ }
++ chan = do_dma_m2p(src, dst, length);
++ if (chan == -1) {
++ pr_err("dma_to_i2c error\n");
++ }
+
-+ return chan;
++ return chan;
+}
+
+int i2c_to_dma(unsigned int src, unsigned long dst,
-+ unsigned int length)
++ unsigned int length)
+{
-+ int chan;
++ int chan;
+
-+ chan = do_dma_p2m(dst, src, length);
-+ if (chan == -1) {
-+ pr_err("dma_p2m error...\n");
-+ }
++ chan = do_dma_p2m(dst, src, length);
++ if (chan == -1) {
++ pr_err("dma_p2m error...\n");
++ }
+
-+ return chan;
++ return chan;
+}
+
+static int hibvt_i2c_do_dma_write(struct hibvt_i2c_dev *i2c,
-+ unsigned long dma_dst_addr)
++ unsigned long dma_dst_addr)
+{
-+ int chan, val, status = 0;
-+ struct i2c_msg *msg = i2c->msg;
++ int chan, val, status = 0;
++ struct i2c_msg *msg = i2c->msg;
+
-+ hibvt_i2c_set_freq(i2c);
-+ writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
-+ hibvt_i2c_enable(i2c);
-+ hibvt_i2c_clr_irq(i2c);
-+ hibvt_i2c_set_addr(i2c);
-+ hibvt_i2c_cfg_cmd(i2c);
++ hibvt_i2c_set_freq(i2c);
++ writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
++ hibvt_i2c_enable(i2c);
++ hibvt_i2c_clr_irq(i2c);
++ hibvt_i2c_set_addr(i2c);
++ hibvt_i2c_cfg_cmd(i2c);
+
-+ /* transmit DATA from DMAC to I2C in DMA mode */
-+ chan = dma_to_i2c(dma_dst_addr, (i2c->phybase + HIBVT_I2C_TXF),
-+ msg->len);
-+ if (chan == -1) {
-+ status = -1;
-+ goto fail_0;
-+ }
++ /* transmit DATA from DMAC to I2C in DMA mode */
++ chan = dma_to_i2c(dma_dst_addr, (i2c->phybase + HIBVT_I2C_TXF),
++ msg->len);
++ if (chan == -1) {
++ status = -1;
++ goto fail_0;
++ }
+
-+ val = readl(i2c->base + HIBVT_I2C_CTRL1);
-+ val &= ~CTRL1_DMA_OP_MASK;
-+ val |= CTRL1_DMA_W | CTRL1_CMD_START_MASK;
-+ writel(val, i2c->base + HIBVT_I2C_CTRL1);
++ val = readl(i2c->base + HIBVT_I2C_CTRL1);
++ val &= ~CTRL1_DMA_OP_MASK;
++ val |= CTRL1_DMA_W | CTRL1_CMD_START_MASK;
++ writel(val, i2c->base + HIBVT_I2C_CTRL1);
+
-+ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
-+ status = -1;
-+ goto fail_1;
-+ }
++ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
++ status = -1;
++ goto fail_1;
++ }
+
-+ status = hibvt_i2c_wait_idle(i2c);
++ status = hibvt_i2c_wait_idle(i2c);
+
+fail_1:
-+ dmac_channel_free((unsigned int)chan);
++ dmac_channel_free((unsigned int)chan);
+fail_0:
-+ hibvt_i2c_disable(i2c);
++ hibvt_i2c_disable(i2c);
+
-+ return status;
++ return status;
+}
+
+static int hibvt_i2c_do_dma_read(struct hibvt_i2c_dev *i2c,
-+ unsigned long dma_dst_addr)
++ unsigned long dma_dst_addr)
+{
-+ int val, chan, status = 0;
-+ struct i2c_msg *msg = i2c->msg;
++ int val, chan, status = 0;
++ struct i2c_msg *msg = i2c->msg;
+
-+ hibvt_i2c_set_freq(i2c);
-+ writel(0x0, i2c->base + HIBVT_I2C_RX_WATER);
-+ hibvt_i2c_enable(i2c);
-+ hibvt_i2c_clr_irq(i2c);
-+ hibvt_i2c_set_addr(i2c);
-+ hibvt_i2c_cfg_cmd(i2c);
++ hibvt_i2c_set_freq(i2c);
++ writel(0x0, i2c->base + HIBVT_I2C_RX_WATER);
++ hibvt_i2c_enable(i2c);
++ hibvt_i2c_clr_irq(i2c);
++ hibvt_i2c_set_addr(i2c);
++ hibvt_i2c_cfg_cmd(i2c);
+
-+ /* transmit DATA from I2C to DMAC in DMA mode */
-+ chan = i2c_to_dma((i2c->phybase + HIBVT_I2C_RXF),
-+ dma_dst_addr, msg->len);
-+ if (chan == -1) {
-+ status = -1;
-+ goto fail_0;
-+ }
++ /* transmit DATA from I2C to DMAC in DMA mode */
++ chan = i2c_to_dma((i2c->phybase + HIBVT_I2C_RXF),
++ dma_dst_addr, msg->len);
++ if (chan == -1) {
++ status = -1;
++ goto fail_0;
++ }
+
-+ val = readl(i2c->base + HIBVT_I2C_CTRL1);
-+ val &= ~CTRL1_DMA_OP_MASK;
-+ val |= CTRL1_CMD_START_MASK | CTRL1_DMA_R;
-+ writel(val, i2c->base + HIBVT_I2C_CTRL1);
++ val = readl(i2c->base + HIBVT_I2C_CTRL1);
++ val &= ~CTRL1_DMA_OP_MASK;
++ val |= CTRL1_CMD_START_MASK | CTRL1_DMA_R;
++ writel(val, i2c->base + HIBVT_I2C_CTRL1);
+
-+ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
-+ status = -1;
-+ goto fail_1;
-+ }
++ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
++ status = -1;
++ goto fail_1;
++ }
+
-+ status = hibvt_i2c_wait_idle(i2c);
++ status = hibvt_i2c_wait_idle(i2c);
+
+fail_1:
-+ dmac_channel_free((unsigned int)chan);
++ dmac_channel_free((unsigned int)chan);
+fail_0:
-+ hibvt_i2c_disable(i2c);
++ hibvt_i2c_disable(i2c);
+
-+ return status;
++ return status;
+}
+static int hibvt_i2c_dma_xfer_one_msg(struct hibvt_i2c_dev *i2c)
+{
-+ unsigned int status;
-+ struct i2c_msg *msg = i2c->msg;
-+ dma_addr_t dma_dst_addr;
++ unsigned int status;
++ struct i2c_msg *msg = i2c->msg;
++ dma_addr_t dma_dst_addr;
+
+
-+ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
-+ __func__, __LINE__, msg->flags, msg->len);
++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
++ __func__, __LINE__, msg->flags, msg->len);
+
-+ if (msg->flags & I2C_M_RD) {
-+ dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
-+ msg->len, DMA_FROM_DEVICE);
-+ if (dma_mapping_error(i2c->dev, dma_dst_addr)) {
-+ dev_err(i2c->dev, "DMA mapping failed\n");
-+ return -EINVAL;
-+ }
++ if (msg->flags & I2C_M_RD) {
++ dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
++ msg->len, DMA_FROM_DEVICE);
++ if (dma_mapping_error(i2c->dev, dma_dst_addr)) {
++ dev_err(i2c->dev, "DMA mapping failed\n");
++ return -EINVAL;
++ }
+
-+ status = hibvt_i2c_do_dma_read(i2c, dma_dst_addr);
++ status = hibvt_i2c_do_dma_read(i2c, dma_dst_addr);
+
-+ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_FROM_DEVICE);
++ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_FROM_DEVICE);
+
-+ } else {
-+ dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
-+ msg->len, DMA_TO_DEVICE);
++ } else {
++ dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
++ msg->len, DMA_TO_DEVICE);
+
-+ if (dma_mapping_error(i2c->dev, dma_dst_addr)) {
-+ dev_err(i2c->dev, "DMA mapping failed\n");
-+ return -EINVAL;
-+ }
++ if (dma_mapping_error(i2c->dev, dma_dst_addr)) {
++ dev_err(i2c->dev, "DMA mapping failed\n");
++ return -EINVAL;
++ }
+
-+ status = hibvt_i2c_do_dma_write(i2c, dma_dst_addr);
-+ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_TO_DEVICE);
-+ }
-+ status = hibvt_i2c_wait_idle(i2c);
-+ hibvt_i2c_disable(i2c);
++ status = hibvt_i2c_do_dma_write(i2c, dma_dst_addr);
++ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_TO_DEVICE);
++ }
++ status = hibvt_i2c_wait_idle(i2c);
++ hibvt_i2c_disable(i2c);
+
-+ return status;
++ return status;
+}
+#endif
+static int hibvt_i2c_polling_xfer_one_msg(struct hibvt_i2c_dev *i2c)
+{
-+ int status;
-+ unsigned int val;
-+ struct i2c_msg *msg = i2c->msg;
++ int status;
++ unsigned int val;
++ struct i2c_msg *msg = i2c->msg;
+
-+ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
-+ __func__, __LINE__, msg->flags, msg->len);
++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
++ __func__, __LINE__, msg->flags, msg->len);
+
-+ hibvt_i2c_enable(i2c);
-+ hibvt_i2c_clr_irq(i2c);
-+ hibvt_i2c_set_addr(i2c);
-+ hibvt_i2c_cfg_cmd(i2c);
-+ hibvt_i2c_start_cmd(i2c);
++ hibvt_i2c_enable(i2c);
++ hibvt_i2c_clr_irq(i2c);
++ hibvt_i2c_set_addr(i2c);
++ hibvt_i2c_cfg_cmd(i2c);
++ hibvt_i2c_start_cmd(i2c);
+
-+ i2c->msg_buf_ptr = 0;
++ i2c->msg_buf_ptr = 0;
+
-+ if (msg->flags & I2C_M_RD) {
-+ while (i2c->msg_buf_ptr < msg->len) {
-+ status = hibvt_i2c_wait_rx_noempty(i2c);
-+ if (status) {
-+ goto end;
-+ }
++ if (msg->flags & I2C_M_RD) {
++ while (i2c->msg_buf_ptr < msg->len) {
++ status = hibvt_i2c_wait_rx_noempty(i2c);
++ if (status) {
++ goto end;
++ }
+
-+ val = readl(i2c->base + HIBVT_I2C_RXF);
-+ msg->buf[i2c->msg_buf_ptr] = val;
-+ i2c->msg_buf_ptr++;
++ val = readl(i2c->base + HIBVT_I2C_RXF);
++ msg->buf[i2c->msg_buf_ptr] = val;
++ i2c->msg_buf_ptr++;
+
-+ }
-+ } else {
-+ while (i2c->msg_buf_ptr < msg->len) {
-+ status = hibvt_i2c_wait_tx_nofull(i2c);
-+ if (status) {
-+ goto end;
-+ }
++ }
++ } else {
++ while (i2c->msg_buf_ptr < msg->len) {
++ status = hibvt_i2c_wait_tx_nofull(i2c);
++ if (status) {
++ goto end;
++ }
+
-+ val = msg->buf[i2c->msg_buf_ptr];
-+ writel(val, i2c->base + HIBVT_I2C_TXF);
-+ i2c->msg_buf_ptr++;
-+ }
-+ }
++ val = msg->buf[i2c->msg_buf_ptr];
++ writel(val, i2c->base + HIBVT_I2C_TXF);
++ i2c->msg_buf_ptr++;
++ }
++ }
+
-+ status = hibvt_i2c_wait_idle(i2c);
++ status = hibvt_i2c_wait_idle(i2c);
+end:
-+ hibvt_i2c_disable(i2c);
++ hibvt_i2c_disable(i2c);
+
-+ return status;
++ return status;
+}
+
+static irqreturn_t hibvt_i2c_isr(int irq, void *dev_id)
+{
-+ struct hibvt_i2c_dev *i2c = dev_id;
-+ unsigned int irq_status;
-+ struct i2c_msg *msg = i2c->msg;
++ struct hibvt_i2c_dev *i2c = dev_id;
++ unsigned int irq_status;
++ struct i2c_msg *msg = i2c->msg;
+
-+ spin_lock(&i2c->lock);
++ spin_lock(&i2c->lock);
+
-+ irq_status = hibvt_i2c_clr_irq(i2c);
-+ dev_dbg(i2c->dev, "%s RIS: 0x%x\n", __func__, irq_status);
++ irq_status = hibvt_i2c_clr_irq(i2c);
++ dev_dbg(i2c->dev, "%s RIS: 0x%x\n", __func__, irq_status);
+
-+ if (!irq_status) {
-+ dev_dbg(i2c->dev, "no irq\n");
-+ goto end;
-+ }
++ if (!irq_status) {
++ dev_dbg(i2c->dev, "no irq\n");
++ goto end;
++ }
+
-+ if (irq_status & INTR_ABORT_MASK) {
-+ dev_err(i2c->dev, "irq handle abort, RIS: 0x%x\n",
-+ irq_status);
-+ i2c->status = -EIO;
-+ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
++ if (irq_status & INTR_ABORT_MASK) {
++ dev_err(i2c->dev, "irq handle abort, RIS: 0x%x\n",
++ irq_status);
++ i2c->status = -EIO;
++ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
+
-+ complete(&i2c->msg_complete);
-+ goto end;
-+ }
++ complete(&i2c->msg_complete);
++ goto end;
++ }
+
-+ if (msg->flags & I2C_M_RD) {
-+ while ((readl(i2c->base + HIBVT_I2C_STAT) & STAT_RXF_NOE_MASK)
-+ && (i2c->msg_buf_ptr < msg->len)) {
-+ msg->buf[i2c->msg_buf_ptr] =
-+ readl(i2c->base + HIBVT_I2C_RXF);
-+ i2c->msg_buf_ptr++;
-+ }
-+ } else {
-+ while ((readl(i2c->base + HIBVT_I2C_STAT) & STAT_TXF_NOF_MASK)
-+ && (i2c->msg_buf_ptr < msg->len)) {
-+ writel(msg->buf[i2c->msg_buf_ptr],
-+ i2c->base + HIBVT_I2C_TXF);
-+ i2c->msg_buf_ptr++;
-+ }
-+ }
++ if (msg->flags & I2C_M_RD) {
++ while ((readl(i2c->base + HIBVT_I2C_STAT) & STAT_RXF_NOE_MASK)
++ && (i2c->msg_buf_ptr < msg->len)) {
++ msg->buf[i2c->msg_buf_ptr] =
++ readl(i2c->base + HIBVT_I2C_RXF);
++ i2c->msg_buf_ptr++;
++ }
++ } else {
++ while ((readl(i2c->base + HIBVT_I2C_STAT) & STAT_TXF_NOF_MASK)
++ && (i2c->msg_buf_ptr < msg->len)) {
++ writel(msg->buf[i2c->msg_buf_ptr],
++ i2c->base + HIBVT_I2C_TXF);
++ i2c->msg_buf_ptr++;
++ }
++ }
+
-+ if (i2c->msg_buf_ptr >= msg->len) {
-+ hibvt_i2c_disable_irq(i2c, INTR_TX_MASK | INTR_RX_MASK);
-+ }
++ if (i2c->msg_buf_ptr >= msg->len) {
++ hibvt_i2c_disable_irq(i2c, INTR_TX_MASK | INTR_RX_MASK);
++ }
+
-+ if (irq_status & INTR_CMD_DONE_MASK) {
-+ dev_dbg(i2c->dev, "cmd done\n");
-+ i2c->status = 0;
-+ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
++ if (irq_status & INTR_CMD_DONE_MASK) {
++ dev_dbg(i2c->dev, "cmd done\n");
++ i2c->status = 0;
++ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
+
-+ complete(&i2c->msg_complete);
-+ }
++ complete(&i2c->msg_complete);
++ }
+
+end:
-+ spin_unlock(&i2c->lock);
++ spin_unlock(&i2c->lock);
+
-+ return IRQ_HANDLED;
++ return IRQ_HANDLED;
+}
+
+static int hibvt_i2c_interrupt_xfer_one_msg(struct hibvt_i2c_dev *i2c)
+{
-+ int status;
-+ struct i2c_msg *msg = i2c->msg;
-+ unsigned long timeout;
-+ unsigned long flags;
++ int status;
++ struct i2c_msg *msg = i2c->msg;
++ unsigned long timeout;
++ unsigned long flags;
+
-+ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
-+ __func__, __LINE__, msg->flags, msg->len);
++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
++ __func__, __LINE__, msg->flags, msg->len);
+
-+ reinit_completion(&i2c->msg_complete);
-+ i2c->msg_buf_ptr = 0;
-+ i2c->status = -EIO;
++ reinit_completion(&i2c->msg_complete);
++ i2c->msg_buf_ptr = 0;
++ i2c->status = -EIO;
+
-+ spin_lock_irqsave(&i2c->lock, flags);
-+ hibvt_i2c_enable(i2c);
-+ hibvt_i2c_clr_irq(i2c);
-+ if (msg->flags & I2C_M_RD) {
-+ hibvt_i2c_cfg_irq(i2c, INTR_USE_MASK & ~INTR_TX_MASK);
-+ } else {
-+ hibvt_i2c_cfg_irq(i2c, INTR_USE_MASK & ~INTR_RX_MASK);
-+ }
++ spin_lock_irqsave(&i2c->lock, flags);
++ hibvt_i2c_enable(i2c);
++ hibvt_i2c_clr_irq(i2c);
++ if (msg->flags & I2C_M_RD) {
++ hibvt_i2c_cfg_irq(i2c, INTR_USE_MASK & ~INTR_TX_MASK);
++ } else {
++ hibvt_i2c_cfg_irq(i2c, INTR_USE_MASK & ~INTR_RX_MASK);
++ }
+
-+ hibvt_i2c_set_addr(i2c);
-+ hibvt_i2c_cfg_cmd(i2c);
-+ hibvt_i2c_start_cmd(i2c);
-+ spin_unlock_irqrestore(&i2c->lock, flags);
++ hibvt_i2c_set_addr(i2c);
++ hibvt_i2c_cfg_cmd(i2c);
++ hibvt_i2c_start_cmd(i2c);
++ spin_unlock_irqrestore(&i2c->lock, flags);
+
-+ timeout = wait_for_completion_timeout(&i2c->msg_complete,
-+ I2C_IRQ_TIMEOUT);
++ timeout = wait_for_completion_timeout(&i2c->msg_complete,
++ I2C_IRQ_TIMEOUT);
+
-+ spin_lock_irqsave(&i2c->lock, flags);
-+ if (timeout == 0) {
-+ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
-+ status = -EIO;
-+ dev_err(i2c->dev, "%s timeout\n",
-+ msg->flags & I2C_M_RD ? "rx" : "tx");
-+ } else {
-+ status = i2c->status;
-+ }
++ spin_lock_irqsave(&i2c->lock, flags);
++ if (timeout == 0) {
++ hibvt_i2c_disable_irq(i2c, INTR_ALL_MASK);
++ status = -EIO;
++ dev_err(i2c->dev, "%s timeout\n",
++ msg->flags & I2C_M_RD ? "rx" : "tx");
++ } else {
++ status = i2c->status;
++ }
+
-+ hibvt_i2c_disable(i2c);
++ hibvt_i2c_disable(i2c);
+
-+ spin_unlock_irqrestore(&i2c->lock, flags);
-+ return status;
++ spin_unlock_irqrestore(&i2c->lock, flags);
++ return status;
+}
+
+/*
+ * Master transfer function
+ */
+static int hibvt_i2c_xfer(struct i2c_adapter *adap,
-+ struct i2c_msg *msgs, int num)
++ struct i2c_msg *msgs, int num)
+{
-+ struct hibvt_i2c_dev *i2c = i2c_get_adapdata(adap);
-+ int status = -EINVAL;
-+ unsigned long flags;
++ struct hibvt_i2c_dev *i2c = i2c_get_adapdata(adap);
++ int status = -EINVAL;
++ unsigned long flags;
+
-+ if (!msgs || (num <= 0)) {
-+ dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
-+ return -EINVAL;
-+ }
++ if (!msgs || (num <= 0)) {
++ dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
++ return -EINVAL;
++ }
+
-+ spin_lock_irqsave(&i2c->lock, flags);
++ spin_lock_irqsave(&i2c->lock, flags);
+
-+ i2c->msg = msgs;
-+ i2c->msg_num = num;
-+ i2c->msg_idx = 0;
++ i2c->msg = msgs;
++ i2c->msg_num = num;
++ i2c->msg_idx = 0;
+
-+ /* FIXME: The wait_for_completion_timeout in hibvt_i2c_interrupt_xfer_one_msg
-+ * function can not be locked by spin_lock_irqsave. And actually I2C interrupt
-+ * tranfer is rarely used, so we ignore the irq setting to limit the interrupt
-+ * way. But we keep these codes below, reserve for future modifications */
++ /* FIXME: The wait_for_completion_timeout in hibvt_i2c_interrupt_xfer_one_msg
++ * function can not be locked by spin_lock_irqsave. And actually I2C interrupt
++ * tranfer is rarely used, so we ignore the irq setting to limit the interrupt
++ * way. But we keep these codes below, reserve for future modifications */
+
-+ while (i2c->msg_idx < i2c->msg_num) {
++ while (i2c->msg_idx < i2c->msg_num) {
+#if defined(CONFIG_HI_DMAC) || defined(CONFIG_HIEDMAC)
-+ if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) {
-+ status = hibvt_i2c_dma_xfer_one_msg(i2c);
-+ if (status) {
-+ break;
-+ }
-+ } else if (i2c->irq >= 0) {
++ if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) {
++ status = hibvt_i2c_dma_xfer_one_msg(i2c);
++ if (status) {
++ break;
++ }
++ } else if (i2c->irq >= 0) {
+#else
-+ if (i2c->irq >= 0) {
++ if (i2c->irq >= 0) {
+#endif
-+ spin_unlock_irqrestore(&i2c->lock, flags);
-+ status = hibvt_i2c_interrupt_xfer_one_msg(i2c);
-+ spin_lock_irqsave(&i2c->lock, flags);
-+ if (status) {
-+ break;
-+ }
-+ } else {
-+ status = hibvt_i2c_polling_xfer_one_msg(i2c);
-+ if (status) {
-+ break;
-+ }
-+ }
-+ i2c->msg++;
-+ i2c->msg_idx++;
-+ }
++ spin_unlock_irqrestore(&i2c->lock, flags);
++ status = hibvt_i2c_interrupt_xfer_one_msg(i2c);
++ spin_lock_irqsave(&i2c->lock, flags);
++ if (status) {
++ break;
++ }
++ } else {
++ status = hibvt_i2c_polling_xfer_one_msg(i2c);
++ if (status) {
++ break;
++ }
++ }
++ i2c->msg++;
++ i2c->msg_idx++;
++ }
+
-+ if (!status || i2c->msg_idx > 0) {
-+ status = i2c->msg_idx;
-+ }
++ if (!status || i2c->msg_idx > 0) {
++ status = i2c->msg_idx;
++ }
+
-+ spin_unlock_irqrestore(&i2c->lock, flags);
-+ return status;
++ spin_unlock_irqrestore(&i2c->lock, flags);
++ return status;
+}
+
+/* hibvt_i2c_break_polling_xfer
@@ -267986,41 +335947,41 @@ index 0000000..da38db1
+ * I2c polling independent branch, Shielding interrupt interface
+ */
+static int hibvt_i2c_break_polling_xfer(struct i2c_adapter *adap,
-+ struct i2c_msg *msgs, int num)
++ struct i2c_msg *msgs, int num)
+{
-+ struct hibvt_i2c_dev *i2c = i2c_get_adapdata(adap);
-+ int status = -EINVAL;
-+ unsigned long flags;
-+ if (!msgs || (num <= 0)) {
-+ dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
-+ return -EINVAL;
-+ }
-+ spin_lock_irqsave(&i2c->lock, flags);
-+ i2c->msg = msgs;
-+ i2c->msg_num = num;
-+ i2c->msg_idx = 0;
-+ while (i2c->msg_idx < i2c->msg_num) {
++ struct hibvt_i2c_dev *i2c = i2c_get_adapdata(adap);
++ int status = -EINVAL;
++ unsigned long flags;
++ if (!msgs || (num <= 0)) {
++ dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
++ return -EINVAL;
++ }
++ spin_lock_irqsave(&i2c->lock, flags);
++ i2c->msg = msgs;
++ i2c->msg_num = num;
++ i2c->msg_idx = 0;
++ while (i2c->msg_idx < i2c->msg_num) {
+#if defined(CONFIG_HI_DMAC) || defined(CONFIG_HIEDMAC)
-+ if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) {
-+ status = hibvt_i2c_dma_xfer_one_msg(i2c);
-+ if (status) {
-+ break;
-+ }
-+ }
++ if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) {
++ status = hibvt_i2c_dma_xfer_one_msg(i2c);
++ if (status) {
++ break;
++ }
++ }
+#else
-+ status = hibvt_i2c_polling_xfer_one_msg(i2c);
-+ if (status) {
-+ break;
-+ }
++ status = hibvt_i2c_polling_xfer_one_msg(i2c);
++ if (status) {
++ break;
++ }
+#endif
-+ i2c->msg++;
-+ i2c->msg_idx++;
-+ }
-+ if (!status || i2c->msg_idx > 0) {
-+ status = i2c->msg_idx;
-+ }
-+ spin_unlock_irqrestore(&i2c->lock, flags);
-+ return status;
++ i2c->msg++;
++ i2c->msg_idx++;
++ }
++ if (!status || i2c->msg_idx > 0) {
++ status = i2c->msg_idx;
++ }
++ spin_unlock_irqrestore(&i2c->lock, flags);
++ return status;
+}
+/* HI I2C READ *
+ * hi_i2c_master_recv - issue a single I2C message in master receive mode
@@ -268031,12 +335992,12 @@ index 0000000..da38db1
+ * Returns negative errno, or else the number of bytes read.
+ */
+int hi_i2c_master_recv(const struct i2c_client *client, char *buf,
-+ int count)
++ int count)
+{
-+ printk("Wrong interface call."
-+ "hi_i2c_transfer is the only interface to i2c read!!!\n");
++ printk("Wrong interface call."
++ "hi_i2c_transfer is the only interface to i2c read!!!\n");
+
-+ return -EIO;
++ return -EIO;
+}
+EXPORT_SYMBOL(hi_i2c_master_recv);
+
@@ -268049,31 +336010,31 @@ index 0000000..da38db1
+ * Returns negative errno, or else the number of bytes written.
+ */
+int hi_i2c_master_send(const struct i2c_client *client,
-+ const char *buf, int count)
++ const char *buf, int count)
+{
-+ struct i2c_adapter *adap = client->adapter;
-+ struct i2c_msg msg;
-+ int msgs_count;
++ struct i2c_adapter *adap = client->adapter;
++ struct i2c_msg msg;
++ int msgs_count;
+
-+ if ((client->addr > 0x3ff)
-+ || (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
-+ printk(KERN_ERR "dev address out of range\n");
-+ return -EINVAL;
-+ }
++ if ((client->addr > 0x3ff)
++ || (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
++ printk(KERN_ERR "dev address out of range\n");
++ return -EINVAL;
++ }
+
-+ msg.addr = client->addr;
-+ msg.flags = client->flags;
-+ msg.len = count;
++ msg.addr = client->addr;
++ msg.flags = client->flags;
++ msg.len = count;
+
-+ if (!buf) {
-+ printk(KERN_ERR "Invalid buf == NULL!!!\n");
-+ return -EINVAL;
-+ }
-+ msg.buf = (__u8 *)buf;
++ if ((!buf)||(count < 0)) {
++ printk(KERN_ERR "buf == NULL || count < 0, Invalid argument!\n");
++ return -EINVAL;
++ }
++ msg.buf = (__u8 *)buf;
+
-+ msgs_count = hibvt_i2c_break_polling_xfer(adap, &msg, 1);
++ msgs_count = hibvt_i2c_break_polling_xfer(adap, &msg, 1);
+
-+ return (msgs_count == 1) ? count : -EIO;
++ return (msgs_count == 1) ? count : -EIO;
+}
+EXPORT_SYMBOL(hi_i2c_master_send);
+
@@ -268090,182 +336051,187 @@ index 0000000..da38db1
+ * the same slave address, although that is the most common model.
+ */
+int hi_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
-+ int num)
++ int num)
+{
-+ int msgs_count;
++ int msgs_count;
++
++ if((!adap)||(!msgs)) {
++ printk(KERN_ERR "adap == NULL || msgs == NULL, Invalid argument!\n");
++ return -EINVAL;
++ }
+
-+ if ((msgs[0].addr > 0x3ff)
-+ || (((msgs[0].flags & I2C_M_TEN) == 0) && (msgs[0].addr > 0x7f))) {
-+ printk(KERN_ERR "msgs[0] dev address out of range\n");
-+ return -EINVAL;
-+ }
++ if ((msgs[0].addr > 0x3ff)
++ || (((msgs[0].flags & I2C_M_TEN) == 0) && (msgs[0].addr > 0x7f))) {
++ printk(KERN_ERR "msgs[0] dev address out of range\n");
++ return -EINVAL;
++ }
+
-+ if ((msgs[1].addr > 0x3ff)
-+ || (((msgs[1].flags & I2C_M_TEN) == 0) && (msgs[1].addr > 0x7f))) {
-+ printk(KERN_ERR "msgs[1] dev address out of range\n");
-+ return -EINVAL;
-+ }
++ if ((msgs[1].addr > 0x3ff)
++ || (((msgs[1].flags & I2C_M_TEN) == 0) && (msgs[1].addr > 0x7f))) {
++ printk(KERN_ERR "msgs[1] dev address out of range\n");
++ return -EINVAL;
++ }
+
-+ msgs_count = hibvt_i2c_xfer(adap, msgs, num);
++ msgs_count = hibvt_i2c_xfer(adap, msgs, num);
+
-+ return msgs_count;
++ return msgs_count;
+}
+EXPORT_SYMBOL(hi_i2c_transfer);
+
+static u32 hibvt_i2c_func(struct i2c_adapter *adap)
+{
-+ return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR
-+ | I2C_FUNC_PROTOCOL_MANGLING
-+ | I2C_FUNC_SMBUS_WORD_DATA
-+ | I2C_FUNC_SMBUS_BYTE_DATA
-+ | I2C_FUNC_SMBUS_BYTE
-+ | I2C_FUNC_SMBUS_I2C_BLOCK;
++ return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR
++ | I2C_FUNC_PROTOCOL_MANGLING
++ | I2C_FUNC_SMBUS_WORD_DATA
++ | I2C_FUNC_SMBUS_BYTE_DATA
++ | I2C_FUNC_SMBUS_BYTE
++ | I2C_FUNC_SMBUS_I2C_BLOCK;
+}
+
+static const struct i2c_algorithm hibvt_i2c_algo = {
-+ .master_xfer = hibvt_i2c_xfer,
-+ .functionality = hibvt_i2c_func,
++ .master_xfer = hibvt_i2c_xfer,
++ .functionality = hibvt_i2c_func,
+};
+
+static int hibvt_i2c_probe(struct platform_device *pdev)
+{
-+ int status;
-+ struct hibvt_i2c_dev *i2c;
-+ struct i2c_adapter *adap;
-+ struct resource *res;
++ int status;
++ struct hibvt_i2c_dev *i2c = NULL;
++ struct i2c_adapter *adap = NULL;
++ struct resource *res = NULL;
+
-+ i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
-+ if (!i2c) {
-+ return -ENOMEM;
-+ }
++ i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
++ if (!i2c) {
++ return -ENOMEM;
++ }
+
-+ platform_set_drvdata(pdev, i2c);
-+ i2c->dev = &pdev->dev;
-+ spin_lock_init(&i2c->lock);
-+ init_completion(&i2c->msg_complete);
++ platform_set_drvdata(pdev, i2c);
++ i2c->dev = &pdev->dev;
++ spin_lock_init(&i2c->lock);
++ init_completion(&i2c->msg_complete);
+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(i2c->dev, "Invalid mem resource./n");
-+ return -ENODEV;
-+ }
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(i2c->dev, "Invalid mem resource./n");
++ return -ENODEV;
++ }
+
-+ i2c->phybase = res->start;
-+ i2c->base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(i2c->base)) {
-+ dev_err(i2c->dev, "cannot ioremap resource\n");
-+ return -ENOMEM;
-+ }
++ i2c->phybase = res->start;
++ i2c->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(i2c->base)) {
++ dev_err(i2c->dev, "cannot ioremap resource\n");
++ return -ENOMEM;
++ }
+
-+ i2c->clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(i2c->clk)) {
-+ dev_err(i2c->dev, "cannot get clock\n");
-+ return -ENOENT;
-+ }
-+ clk_prepare_enable(i2c->clk);
++ i2c->clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(i2c->clk)) {
++ dev_err(i2c->dev, "cannot get clock\n");
++ return -ENOENT;
++ }
++ clk_prepare_enable(i2c->clk);
+
-+ if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
-+ &i2c->freq)) {
-+ dev_warn(i2c->dev, "setting default clock-frequency@%dHz\n",
-+ I2C_DEFAULT_FREQUENCY);
-+ i2c->freq = I2C_DEFAULT_FREQUENCY;
-+ }
++ if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
++ &i2c->freq)) {
++ dev_warn(i2c->dev, "setting default clock-frequency@%dHz\n",
++ I2C_DEFAULT_FREQUENCY);
++ i2c->freq = I2C_DEFAULT_FREQUENCY;
++ }
+
-+ /* i2c controller initialization, disable interrupt */
-+ hibvt_i2c_hw_init(i2c);
++ /* i2c controller initialization, disable interrupt */
++ hibvt_i2c_hw_init(i2c);
+
-+ i2c->irq = platform_get_irq(pdev, 0);
-+ status = devm_request_irq(&pdev->dev, i2c->irq, hibvt_i2c_isr,
-+ IRQF_SHARED, dev_name(&pdev->dev), i2c);
-+ if (status) {
-+ dev_dbg(i2c->dev, "falling back to polling mode");
-+ i2c->irq = -1;
-+ }
++ i2c->irq = platform_get_irq(pdev, 0);
++ status = devm_request_irq(&pdev->dev, i2c->irq, hibvt_i2c_isr,
++ IRQF_SHARED, dev_name(&pdev->dev), i2c);
++ if (status) {
++ dev_dbg(i2c->dev, "falling back to polling mode");
++ i2c->irq = -1;
++ }
+
-+ adap = &i2c->adap;
-+ i2c_set_adapdata(adap, i2c);
-+ adap->owner = THIS_MODULE;
-+ strlcpy(adap->name, "hibvt-i2c", sizeof(adap->name));
-+ adap->dev.parent = &pdev->dev;
-+ adap->dev.of_node = pdev->dev.of_node;
-+ adap->algo = &hibvt_i2c_algo;
++ adap = &i2c->adap;
++ i2c_set_adapdata(adap, i2c);
++ adap->owner = THIS_MODULE;
++ strlcpy(adap->name, "hibvt-i2c", sizeof(adap->name));
++ adap->dev.parent = &pdev->dev;
++ adap->dev.of_node = pdev->dev.of_node;
++ adap->algo = &hibvt_i2c_algo;
+
-+ /* Add the i2c adapter */
-+ status = i2c_add_adapter(adap);
-+ if (status) {
-+ dev_err(i2c->dev, "failed to add bus to i2c core\n");
-+ goto err_add_adapter;
-+ }
++ /* Add the i2c adapter */
++ status = i2c_add_adapter(adap);
++ if (status) {
++ dev_err(i2c->dev, "failed to add bus to i2c core\n");
++ goto err_add_adapter;
++ }
+
-+ dev_info(i2c->dev, "%s%d@%dhz registered\n",
-+ adap->name, adap->nr, i2c->freq);
++ dev_info(i2c->dev, "%s%d@%dhz registered\n",
++ adap->name, adap->nr, i2c->freq);
+
-+ return 0;
++ return 0;
+
+err_add_adapter:
-+ clk_disable_unprepare(i2c->clk);
-+ return status;
++ clk_disable_unprepare(i2c->clk);
++ return status;
+}
+
+static int hibvt_i2c_remove(struct platform_device *pdev)
+{
-+ struct hibvt_i2c_dev *i2c = platform_get_drvdata(pdev);
++ struct hibvt_i2c_dev *i2c = platform_get_drvdata(pdev);
+
-+ clk_disable_unprepare(i2c->clk);
-+ i2c_del_adapter(&i2c->adap);
++ clk_disable_unprepare(i2c->clk);
++ i2c_del_adapter(&i2c->adap);
+
-+ return 0;
++ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int hibvt_i2c_suspend(struct device *dev)
+{
-+ struct hibvt_i2c_dev *i2c = dev_get_drvdata(dev);
++ struct hibvt_i2c_dev *i2c = dev_get_drvdata(dev);
+
-+ i2c_lock_adapter(&i2c->adap);
-+ clk_disable_unprepare(i2c->clk);
-+ i2c_unlock_adapter(&i2c->adap);
++ i2c_lock_adapter(&i2c->adap);
++ clk_disable_unprepare(i2c->clk);
++ i2c_unlock_adapter(&i2c->adap);
+
-+ return 0;
++ return 0;
+}
+
+static int hibvt_i2c_resume(struct device *dev)
+{
-+ struct hibvt_i2c_dev *i2c = dev_get_drvdata(dev);
++ struct hibvt_i2c_dev *i2c = dev_get_drvdata(dev);
+
-+ i2c_lock_adapter(&i2c->adap);
-+ clk_prepare_enable(i2c->clk);
-+ hibvt_i2c_hw_init(i2c);
-+ i2c_unlock_adapter(&i2c->adap);
++ i2c_lock_adapter(&i2c->adap);
++ clk_prepare_enable(i2c->clk);
++ hibvt_i2c_hw_init(i2c);
++ i2c_unlock_adapter(&i2c->adap);
+
-+ return 0;
++ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(hibvt_i2c_dev_pm, hibvt_i2c_suspend,
-+ hibvt_i2c_resume);
++ hibvt_i2c_resume);
+
+static const struct of_device_id hibvt_i2c_match[] = {
-+ { .compatible = "hisilicon,hibvt-i2c"},
-+ { .compatible = "hisilicon,hi3516cv300-i2c"},
-+ { .compatible = "hisilicon,hi3536dv100-i2c"},
-+ {},
++ { .compatible = "hisilicon,hibvt-i2c"},
++ { .compatible = "hisilicon,hi3516cv300-i2c"},
++ { .compatible = "hisilicon,hi3536dv100-i2c"},
++ {},
+};
+MODULE_DEVICE_TABLE(of, hibvt_i2c_match);
+
+static struct platform_driver hibvt_i2c_driver = {
-+ .driver = {
-+ .name = "hibvt-i2c",
-+ .of_match_table = hibvt_i2c_match,
-+ .pm = &hibvt_i2c_dev_pm,
-+ },
-+ .probe = hibvt_i2c_probe,
-+ .remove = hibvt_i2c_remove,
++ .driver = {
++ .name = "hibvt-i2c",
++ .of_match_table = hibvt_i2c_match,
++ .pm = &hibvt_i2c_dev_pm,
++ },
++ .probe = hibvt_i2c_probe,
++ .remove = hibvt_i2c_remove,
+};
+
+module_platform_driver(hibvt_i2c_driver);
+
-+MODULE_AUTHOR("Pan Wen, <wenpan@hisilicon.com>");
++MODULE_AUTHOR("Hisilicon");
+MODULE_DESCRIPTION("HISILICON BVT I2C Bus driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-highlander.c b/drivers/i2c/busses/i2c-highlander.c
@@ -269071,7 +337037,7 @@ index 56dc69e..d72fc7d 100644
+ "Delay between data read cycles (default 0 ms)");
diff --git a/drivers/i2c/busses/i2c-hisilicon.c b/drivers/i2c/busses/i2c-hisilicon.c
new file mode 100644
-index 0000000..e53d541
+index 0000000..5d847a4
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hisilicon.c
@@ -0,0 +1,1185 @@
@@ -269158,451 +337124,451 @@ index 0000000..e53d541
+#define I2C_DFT_RATE (100000)
+
+struct hi_i2c {
-+ unsigned char __iomem *regbase;
-+ struct device *dev;
-+ struct resource *mem;
-+ struct clk *clk;
-+ unsigned int irq;
-+ struct i2c_adapter adap;
-+ struct i2c_msg *msg;
-+ struct hi_platform_i2c *pdata;
-+ unsigned int g_last_dev_addr;
-+ unsigned int g_last_mode;
-+ spinlock_t spinlock;
++ unsigned char __iomem *regbase;
++ struct device *dev;
++ struct resource *mem;
++ struct clk *clk;
++ unsigned int irq;
++ struct i2c_adapter adap;
++ struct i2c_msg *msg;
++ struct hi_platform_i2c *pdata;
++ unsigned int g_last_dev_addr;
++ unsigned int g_last_mode;
++ spinlock_t spinlock;
+};
+
+static int hi_i2c_abortprocess(struct hi_i2c *pinfo)
+{
-+ unsigned int auto_status;
-+ unsigned int tx_src;
++ unsigned int auto_status;
++ unsigned int tx_src;
+
-+ tx_src = readl(pinfo->regbase + I2C_TX_ABRT_SRC);
-+ hi_err("tx_abrt_src is %x.\n", tx_src);
++ tx_src = readl(pinfo->regbase + I2C_TX_ABRT_SRC);
++ hi_err("tx_abrt_src is %x.\n", tx_src);
+
-+ auto_status = readl(pinfo->regbase + I2C_AUTO_REG);
++ auto_status = readl(pinfo->regbase + I2C_AUTO_REG);
+
-+ /* clear 0xB0 err status */
-+ /* auto_mst_tx_abrt_clr
-+ auto_tx_cmd_fifo_over_clr
-+ auto_rx_cmd_fifo_under_clr
-+ auto_rx_cmd_fifo_over_clr
-+ */
-+ auto_status |= 0x0f000000;
-+ writel(auto_status, pinfo->regbase + I2C_AUTO_REG);
-+ writel(0x1, pinfo->regbase + I2C_CLR_INTR_REG);
++ /* clear 0xB0 err status */
++ /* auto_mst_tx_abrt_clr
++ auto_tx_cmd_fifo_over_clr
++ auto_rx_cmd_fifo_under_clr
++ auto_rx_cmd_fifo_over_clr
++ */
++ auto_status |= 0x0f000000;
++ writel(auto_status, pinfo->regbase + I2C_AUTO_REG);
++ writel(0x1, pinfo->regbase + I2C_CLR_INTR_REG);
+
-+ /* disable i2c */
-+ writel(0, pinfo->regbase + I2C_ENABLE_REG);
++ /* disable i2c */
++ writel(0, pinfo->regbase + I2C_ENABLE_REG);
+
-+ /* enable i2c */
-+ writel(0x1, pinfo->regbase + I2C_ENABLE_REG);
++ /* enable i2c */
++ writel(0x1, pinfo->regbase + I2C_ENABLE_REG);
+
-+ return 0;
++ return 0;
+}
+
+void hi_i2c_set_rate(struct hi_i2c *pinfo)
+{
-+ unsigned int apb_clk, scl_h, scl_l, hold;
++ unsigned int apb_clk, scl_h, scl_l, hold;
+
-+ /* get apb bus clk for diff plat */
-+ apb_clk = clk_get_rate(pinfo->clk);
++ /* get apb bus clk for diff plat */
++ apb_clk = clk_get_rate(pinfo->clk);
+
-+ /* set SCLH and SCLL depend on apb_clk and def_rate */
-+ if (pinfo->pdata->clk_limit <= I2C_DFT_RATE) {
-+ /* in normal mode F_scl: def_rate
-+ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5
-+ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5
-+ */
-+ scl_h = (apb_clk / I2C_DFT_RATE) / 2;
-+ scl_l = scl_h;
-+ } else {
-+ /* in fast mode F_scl: def_rate
-+ i2c_scl_hcnt = (F_i2c / F_scl) * 0.36
-+ i2c_scl_hcnt = (F_i2c / F_scl) * 0.64
-+ */
-+ scl_h = ((apb_clk / 100) * 36) / pinfo->pdata->clk_limit;
-+ scl_l = ((apb_clk / 100) * 64) / pinfo->pdata->clk_limit;
-+ }
++ /* set SCLH and SCLL depend on apb_clk and def_rate */
++ if (pinfo->pdata->clk_limit <= I2C_DFT_RATE) {
++ /* in normal mode F_scl: def_rate
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5
++ */
++ scl_h = (apb_clk / I2C_DFT_RATE) / 2;
++ scl_l = scl_h;
++ } else {
++ /* in fast mode F_scl: def_rate
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.36
++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.64
++ */
++ scl_h = ((apb_clk / 100) * 36) / pinfo->pdata->clk_limit;
++ scl_l = ((apb_clk / 100) * 64) / pinfo->pdata->clk_limit;
++ }
+
-+ writel(scl_h, pinfo->regbase + I2C_SCL_H_REG);
-+ writel(scl_l, pinfo->regbase + I2C_SCL_L_REG);
++ writel(scl_h, pinfo->regbase + I2C_SCL_H_REG);
++ writel(scl_l, pinfo->regbase + I2C_SCL_L_REG);
+
-+ /* set hi_i2c hold time */
-+ hold = scl_h / 2;
-+ writel(hold, pinfo->regbase + I2C_SDA_HOLD_REG);
++ /* set hi_i2c hold time */
++ hold = scl_h / 2;
++ writel(hold, pinfo->regbase + I2C_SDA_HOLD_REG);
+}
+
+void hi_i2c_hw_init(struct hi_i2c *pinfo)
+{
-+ unsigned int temp, rx_fifo, tx_fifo;
++ unsigned int temp, rx_fifo, tx_fifo;
+
-+ /* unlock hi_i2c controller to access */
-+ writel(HI_I2C_UNLOCK_VALUE, pinfo->regbase + I2C_LOCK_REG);
++ /* unlock hi_i2c controller to access */
++ writel(HI_I2C_UNLOCK_VALUE, pinfo->regbase + I2C_LOCK_REG);
+
-+ /* disable hi_i2c controller */
-+ temp = readl(pinfo->regbase + I2C_ENABLE_REG);
-+ writel((temp & ~HI_I2C_ENABLE), pinfo->regbase + I2C_ENABLE_REG);
++ /* disable hi_i2c controller */
++ temp = readl(pinfo->regbase + I2C_ENABLE_REG);
++ writel((temp & ~HI_I2C_ENABLE), pinfo->regbase + I2C_ENABLE_REG);
+
-+ /* disable hi_i2c auto_mode */
-+ writel(HI_I2C_AUTO_MODE_OFF, pinfo->regbase + I2C_AUTO_REG);
++ /* disable hi_i2c auto_mode */
++ writel(HI_I2C_AUTO_MODE_OFF, pinfo->regbase + I2C_AUTO_REG);
+
-+ /* set hi_i2c in fast mode */
-+ writel(HI_I2C_FAST_MODE, pinfo->regbase + I2C_CON_REG);
++ /* set hi_i2c in fast mode */
++ writel(HI_I2C_FAST_MODE, pinfo->regbase + I2C_CON_REG);
+
-+ /* set hi_i2c rate */
-+ hi_i2c_set_rate(pinfo);
++ /* set hi_i2c rate */
++ hi_i2c_set_rate(pinfo);
+
-+ rx_fifo = HI_I2C_RX_FIFO;
-+ tx_fifo = HI_I2C_TX_FIFO;
++ rx_fifo = HI_I2C_RX_FIFO;
++ tx_fifo = HI_I2C_TX_FIFO;
+
-+ /* set hi_i2c fifo */
-+ writel(rx_fifo, pinfo->regbase + I2C_RX_TL_REG);
-+ writel(tx_fifo, pinfo->regbase + I2C_TX_TL_REG);
++ /* set hi_i2c fifo */
++ writel(rx_fifo, pinfo->regbase + I2C_RX_TL_REG);
++ writel(tx_fifo, pinfo->regbase + I2C_TX_TL_REG);
+
-+ /* enable interrupt mask */
-+ writel(DISABLE_ALL_INTERRUPTS, pinfo->regbase + I2C_INTR_MASK_REG);
++ /* enable interrupt mask */
++ writel(DISABLE_ALL_INTERRUPTS, pinfo->regbase + I2C_INTR_MASK_REG);
+
-+ /* enable hi_i2c controller */
-+ temp = readl(pinfo->regbase + I2C_ENABLE_REG);
-+ writel((temp | HI_I2C_ENABLE), pinfo->regbase + I2C_ENABLE_REG);
++ /* enable hi_i2c controller */
++ temp = readl(pinfo->regbase + I2C_ENABLE_REG);
++ writel((temp | HI_I2C_ENABLE), pinfo->regbase + I2C_ENABLE_REG);
+
-+ pinfo->g_last_dev_addr = 0;
-+ pinfo->g_last_mode = I2C_MODE_NONE;
++ pinfo->g_last_dev_addr = 0;
++ pinfo->g_last_mode = I2C_MODE_NONE;
+
-+ pinfo->msg = NULL;
++ pinfo->msg = NULL;
+}
+
+int hi_i2c_wait_idle(struct hi_i2c *pinfo)
+{
-+ unsigned int val;
-+ unsigned int time_cnt;
++ unsigned int val;
++ unsigned int time_cnt;
+
-+ time_cnt = 0;
-+ do {
-+ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
-+ if (val & I2C_RAW_TX_ABORT) {
-+ hi_err("wait last i2c fifo is empty abort! "\
-+ "int_raw_status: %#x!\n", val);
-+ return hi_i2c_abortprocess(pinfo);
-+ }
++ time_cnt = 0;
++ do {
++ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
++ if (val & I2C_RAW_TX_ABORT) {
++ hi_err("wait last i2c fifo is empty abort! "\
++ "int_raw_status: %#x!\n", val);
++ return hi_i2c_abortprocess(pinfo);
++ }
+
-+ val = readl(pinfo->regbase + I2C_AUTO_REG);
-+ if (!IS_RX_FIFO_EMPTY(val)) {
-+ readl(pinfo->regbase + I2C_TX_RX_REG);
-+ }
++ val = readl(pinfo->regbase + I2C_AUTO_REG);
++ if (!IS_RX_FIFO_EMPTY(val)) {
++ readl(pinfo->regbase + I2C_TX_RX_REG);
++ }
+
-+ if (IS_FIFO_EMPTY(val)) {
-+ break;
-+ }
++ if (IS_FIFO_EMPTY(val)) {
++ break;
++ }
+
-+ if (time_cnt > I2C_WAIT_TIME_OUT) {
-+ hi_err("wait last i2c fifo is empty timeout! "\
-+ "auto_status: %#x\n", val);
-+ return -EBUSY;
-+ }
-+ time_cnt++;
-+ udelay(50);
-+ } while (1);
++ if (time_cnt > I2C_WAIT_TIME_OUT) {
++ hi_err("wait last i2c fifo is empty timeout! "\
++ "auto_status: %#x\n", val);
++ return -EBUSY;
++ }
++ time_cnt++;
++ udelay(50);
++ } while (1);
+
-+ udelay(10);
++ udelay(10);
+
-+ time_cnt = 0;
-+ do {
-+ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
-+ if (val & I2C_RAW_TX_ABORT) {
-+ hi_err("wait last i2c is idle abort! "\
-+ "int_raw_status: %#x!\n", val);
-+ return hi_i2c_abortprocess(pinfo);
-+ }
++ time_cnt = 0;
++ do {
++ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
++ if (val & I2C_RAW_TX_ABORT) {
++ hi_err("wait last i2c is idle abort! "\
++ "int_raw_status: %#x!\n", val);
++ return hi_i2c_abortprocess(pinfo);
++ }
+
-+ val = readl(pinfo->regbase + I2C_STATUS_REG);
-+ if (IS_I2C_IDLE(val)) {
-+ break;
-+ }
++ val = readl(pinfo->regbase + I2C_STATUS_REG);
++ if (IS_I2C_IDLE(val)) {
++ break;
++ }
+
-+ if (time_cnt > I2C_WAIT_TIME_OUT) {
-+ hi_err("wait last i2c is idle timeout! "\
-+ "auto_status: %#x\n", val);
-+ return -EBUSY;
-+ }
-+ time_cnt++;
-+ udelay(50);
-+ } while (1);
++ if (time_cnt > I2C_WAIT_TIME_OUT) {
++ hi_err("wait last i2c is idle timeout! "\
++ "auto_status: %#x\n", val);
++ return -EBUSY;
++ }
++ time_cnt++;
++ udelay(50);
++ } while (1);
+
-+ return 0;
++ return 0;
+}
+
+/* wait until tx fifo is not full */
+int hi_i2c_wait_txfifo_notfull(struct hi_i2c *pinfo)
+{
-+ unsigned int val;
-+ unsigned int time_cnt;
++ unsigned int val;
++ unsigned int time_cnt;
+
-+ time_cnt = 0;
-+ do {
-+ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
-+ if (val & I2C_RAW_TX_ABORT) {
-+ hi_err("abort! last int_raw_status: %#x!\n", val);
-+ return hi_i2c_abortprocess(pinfo);
-+ }
++ time_cnt = 0;
++ do {
++ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
++ if (val & I2C_RAW_TX_ABORT) {
++ hi_err("abort! last int_raw_status: %#x!\n", val);
++ return hi_i2c_abortprocess(pinfo);
++ }
+
-+ val = readl(pinfo->regbase + I2C_AUTO_REG);
-+ if (!IS_RX_FIFO_EMPTY(val)) {
-+ readl(pinfo->regbase + I2C_TX_RX_REG);
-+ }
++ val = readl(pinfo->regbase + I2C_AUTO_REG);
++ if (!IS_RX_FIFO_EMPTY(val)) {
++ readl(pinfo->regbase + I2C_TX_RX_REG);
++ }
+
-+ if (val & I2c_AUTO_TX_FIFO_NOT_FULL) {
-+ break;
-+ }
++ if (val & I2c_AUTO_TX_FIFO_NOT_FULL) {
++ break;
++ }
+
-+ if (time_cnt > I2C_WAIT_TIME_OUT) {
-+ hi_err("timeout! last auto_status: %#x\n", val);
-+ return -EBUSY;
-+ }
-+ time_cnt++;
-+ udelay(50);
-+ } while (1);
++ if (time_cnt > I2C_WAIT_TIME_OUT) {
++ hi_err("timeout! last auto_status: %#x\n", val);
++ return -EBUSY;
++ }
++ time_cnt++;
++ udelay(50);
++ } while (1);
+
-+ return 0;
++ return 0;
+}
+
+/* wait until tx fifo is not empty */
+int hi_i2c_wait_rxfifo_notempty(struct hi_i2c *pinfo)
+{
-+ unsigned int val;
-+ unsigned int time_cnt;
++ unsigned int val;
++ unsigned int time_cnt;
+
-+ time_cnt = 0;
-+ do {
-+ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
-+ if ((val & I2C_RAW_TX_ABORT) == I2C_RAW_TX_ABORT) {
-+ hi_err("abort! int_raw_status: %#x!\n", val);
-+ hi_i2c_abortprocess(pinfo);
-+ return -EIO;
-+ }
++ time_cnt = 0;
++ do {
++ val = readl(pinfo->regbase + I2C_INTR_RAW_REG);
++ if ((val & I2C_RAW_TX_ABORT) == I2C_RAW_TX_ABORT) {
++ hi_err("abort! int_raw_status: %#x!\n", val);
++ hi_i2c_abortprocess(pinfo);
++ return -EIO;
++ }
+
-+ val = readl(pinfo->regbase + I2C_AUTO_REG);
-+ if (!IS_RX_FIFO_EMPTY(val)) {
-+ break;
-+ }
++ val = readl(pinfo->regbase + I2C_AUTO_REG);
++ if (!IS_RX_FIFO_EMPTY(val)) {
++ break;
++ }
+
-+ if (time_cnt > I2C_WAIT_TIME_OUT) {
-+ hi_err("timeout! auto_status: %#x\n", val);
-+ hi_i2c_abortprocess(pinfo);
-+ return -EBUSY;
-+ }
-+ time_cnt++;
-+ udelay(50);
-+ } while (1);
++ if (time_cnt > I2C_WAIT_TIME_OUT) {
++ hi_err("timeout! auto_status: %#x\n", val);
++ hi_i2c_abortprocess(pinfo);
++ return -EBUSY;
++ }
++ time_cnt++;
++ udelay(50);
++ } while (1);
+
-+ return 0;
++ return 0;
+}
+
+static inline int hi_i2c_set_dev_addr_and_mode(struct hi_i2c *pinfo,
-+ unsigned int work_mode)
++ unsigned int work_mode)
+{
-+ unsigned int dev_addr = pinfo->msg->addr;
++ unsigned int dev_addr = pinfo->msg->addr;
+
-+ if ((pinfo->g_last_dev_addr == dev_addr)
-+ && (pinfo->g_last_mode == work_mode)) {
-+ return 0;
-+ }
++ if ((pinfo->g_last_dev_addr == dev_addr)
++ && (pinfo->g_last_mode == work_mode)) {
++ return 0;
++ }
+
-+ /* wait until all cmd in fifo is finished and i2c is idle */
-+ if (hi_i2c_wait_idle(pinfo) < 0) {
-+ return -1;
-+ }
++ /* wait until all cmd in fifo is finished and i2c is idle */
++ if (hi_i2c_wait_idle(pinfo) < 0) {
++ return -1;
++ }
+
-+ /* disable i2c */
-+ writel(0x0, pinfo->regbase + I2C_ENABLE_REG);
-+ /* clear interrupt */
-+ writel(0x1, pinfo->regbase + I2C_CLR_INTR_REG);
-+ /* enable interrupt mask */
-+ writel(DISABLE_ALL_INTERRUPTS, pinfo->regbase + I2C_INTR_MASK_REG);
-+ /* clear err status */
-+ writel(0x0f000000, pinfo->regbase + I2C_AUTO_REG);
++ /* disable i2c */
++ writel(0x0, pinfo->regbase + I2C_ENABLE_REG);
++ /* clear interrupt */
++ writel(0x1, pinfo->regbase + I2C_CLR_INTR_REG);
++ /* enable interrupt mask */
++ writel(DISABLE_ALL_INTERRUPTS, pinfo->regbase + I2C_INTR_MASK_REG);
++ /* clear err status */
++ writel(0x0f000000, pinfo->regbase + I2C_AUTO_REG);
+
-+ /* different device, need to reinit i2c ctrl */
-+ if ((pinfo->g_last_dev_addr) != dev_addr) {
-+ /* set slave dev addr */
-+ writel((dev_addr & 0xff) >> 1, pinfo->regbase + I2C_TAR_REG);
-+ pinfo->g_last_dev_addr = dev_addr;
-+ }
++ /* different device, need to reinit i2c ctrl */
++ if ((pinfo->g_last_dev_addr) != dev_addr) {
++ /* set slave dev addr */
++ writel((dev_addr & 0xff) >> 1, pinfo->regbase + I2C_TAR_REG);
++ pinfo->g_last_dev_addr = dev_addr;
++ }
+
-+ if (pinfo->g_last_mode != work_mode) {
++ if (pinfo->g_last_mode != work_mode) {
+
-+ /* set auto mode */
-+ if (work_mode == I2C_MODE_AUTO) {
-+ writel(0x0, pinfo->regbase + I2C_DMA_CMD0);
-+ writel(0x80000000, pinfo->regbase + I2C_AUTO_REG);
-+ pinfo->g_last_mode = work_mode;
-+ } else if (work_mode == I2C_MODE_DMA) {
-+ writel(0x0, pinfo->regbase + I2C_AUTO_REG);
-+ pinfo->g_last_mode = work_mode;
-+ } else {
-+ hi_err("invalid i2c mode\n");
-+ return -1;
-+ }
-+ }
++ /* set auto mode */
++ if (work_mode == I2C_MODE_AUTO) {
++ writel(0x0, pinfo->regbase + I2C_DMA_CMD0);
++ writel(0x80000000, pinfo->regbase + I2C_AUTO_REG);
++ pinfo->g_last_mode = work_mode;
++ } else if (work_mode == I2C_MODE_DMA) {
++ writel(0x0, pinfo->regbase + I2C_AUTO_REG);
++ pinfo->g_last_mode = work_mode;
++ } else {
++ hi_err("invalid i2c mode\n");
++ return -1;
++ }
++ }
+
-+ /* enable i2c */
-+ writel(0x1, pinfo->regbase + I2C_ENABLE_REG);
++ /* enable i2c */
++ writel(0x1, pinfo->regbase + I2C_ENABLE_REG);
+
-+ hi_msg("\n@@@@@@@@@@\n");
++ hi_msg("\n@@@@@@@@@@\n");
+
-+ return 0;
++ return 0;
+}
+
+int hi_i2c_write(struct hi_i2c *pinfo)
+{
-+ unsigned int reg_val;
-+ unsigned int temp_reg;
-+ unsigned int temp_data;
-+ unsigned int temp_auto_reg;
-+ unsigned int min_msgs_len = 0;
-+ struct i2c_msg *msg = pinfo->msg;
-+ unsigned int msg_buf_ptr = 0;
++ unsigned int reg_val;
++ unsigned int temp_reg;
++ unsigned int temp_data;
++ unsigned int temp_auto_reg;
++ unsigned int min_msgs_len = 0;
++ struct i2c_msg *msg = pinfo->msg;
++ unsigned int msg_buf_ptr = 0;
+
-+ min_msgs_len = (msg->flags & I2C_M_16BIT_REG) ? 2 : 1;
-+ min_msgs_len += (msg->flags & I2C_M_16BIT_DATA) ? 2 : 1;
-+ if (msg->len < min_msgs_len) {
-+ hi_err("Unsupported this length: %d!\n", msg->len);
-+ return -1;
-+ }
++ min_msgs_len = (msg->flags & I2C_M_16BIT_REG) ? 2 : 1;
++ min_msgs_len += (msg->flags & I2C_M_16BIT_DATA) ? 2 : 1;
++ if (msg->len < min_msgs_len) {
++ hi_err("Unsupported this length: %d!\n", msg->len);
++ return -1;
++ }
+
-+ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_AUTO) < 0) {
-+ return -1;
-+ }
++ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_AUTO) < 0) {
++ return -1;
++ }
+
-+ temp_auto_reg = HI_I2C_WRITE;
++ temp_auto_reg = HI_I2C_WRITE;
+
-+ if (msg->flags & I2C_M_16BIT_REG) {
-+ /* 16bit reg addr */
-+ temp_auto_reg |= I2C_AUTO_ADDR;
++ if (msg->flags & I2C_M_16BIT_REG) {
++ /* 16bit reg addr */
++ temp_auto_reg |= I2C_AUTO_ADDR;
+
-+ /* switch high byte and low byte */
-+ temp_reg = msg->buf[msg_buf_ptr] << 8;
++ /* switch high byte and low byte */
++ temp_reg = msg->buf[msg_buf_ptr] << 8;
+
-+ msg_buf_ptr++;
++ msg_buf_ptr++;
+
-+ temp_reg |= msg->buf[msg_buf_ptr];
++ temp_reg |= msg->buf[msg_buf_ptr];
+
-+ msg_buf_ptr++;
-+ } else {
-+ temp_reg = msg->buf[msg_buf_ptr];
-+ msg_buf_ptr++;
-+ }
++ msg_buf_ptr++;
++ } else {
++ temp_reg = msg->buf[msg_buf_ptr];
++ msg_buf_ptr++;
++ }
+
-+ if (msg->flags & I2C_M_16BIT_DATA) {
-+ /* 16bit data */
-+ temp_auto_reg |= I2C_AUTO_DATA;
++ if (msg->flags & I2C_M_16BIT_DATA) {
++ /* 16bit data */
++ temp_auto_reg |= I2C_AUTO_DATA;
+
-+ /* switch high byte and low byte */
-+ temp_data = msg->buf[msg_buf_ptr] << 8;
++ /* switch high byte and low byte */
++ temp_data = msg->buf[msg_buf_ptr] << 8;
+
-+ msg_buf_ptr++;
++ msg_buf_ptr++;
+
-+ temp_data |= msg->buf[msg_buf_ptr];
++ temp_data |= msg->buf[msg_buf_ptr];
+
-+ msg_buf_ptr++;
-+ } else {
-+ temp_data = msg->buf[msg_buf_ptr];
-+ msg_buf_ptr++;
-+ }
++ msg_buf_ptr++;
++ } else {
++ temp_data = msg->buf[msg_buf_ptr];
++ msg_buf_ptr++;
++ }
+
-+ writel(temp_auto_reg, pinfo->regbase + I2C_AUTO_REG);
-+ hi_msg("temp_auto_reg: 0x%x\n", temp_auto_reg);
++ writel(temp_auto_reg, pinfo->regbase + I2C_AUTO_REG);
++ hi_msg("temp_auto_reg: 0x%x\n", temp_auto_reg);
+
-+ /* set write reg&data */
-+ reg_val = (temp_reg << REG_SHIFT) | temp_data;
++ /* set write reg&data */
++ reg_val = (temp_reg << REG_SHIFT) | temp_data;
+
-+ /* wait until tx fifo not full */
-+ if (hi_i2c_wait_txfifo_notfull(pinfo) < 0) {
-+ return -1;
-+ }
++ /* wait until tx fifo not full */
++ if (hi_i2c_wait_txfifo_notfull(pinfo) < 0) {
++ return -1;
++ }
+
-+ hi_msg("reg_val = %x\n", reg_val);
++ hi_msg("reg_val = %x\n", reg_val);
+
-+ writel(reg_val, pinfo->regbase + I2C_TX_RX_REG);
++ writel(reg_val, pinfo->regbase + I2C_TX_RX_REG);
+
-+ hi_msg("dev_addr =%x, reg_addr = %x, Data = %x\n",
-+ pinfo->msg->addr, pinfo->msg->buf[0], pinfo->msg->buf[1]);
++ hi_msg("dev_addr =%x, reg_addr = %x, Data = %x\n",
++ pinfo->msg->addr, pinfo->msg->buf[0], pinfo->msg->buf[1]);
+
-+ return 0;
++ return 0;
+}
+
+unsigned int hi_i2c_read(struct hi_i2c *pinfo)
+{
-+ unsigned int reg_val;
-+ unsigned int temp_reg;
-+ unsigned int ret_data = 0xffff;
-+ unsigned int temp_auto_reg;
-+ unsigned int min_msgs_len = 0;
-+ struct i2c_msg *msg = pinfo->msg;
++ unsigned int reg_val;
++ unsigned int temp_reg;
++ unsigned int ret_data = 0xffff;
++ unsigned int temp_auto_reg;
++ unsigned int min_msgs_len = 0;
++ struct i2c_msg *msg = pinfo->msg;
+
-+ min_msgs_len = (msg->flags & I2C_M_16BIT_REG) ? 2 : 1;
-+ if (msg->len < min_msgs_len) {
-+ hi_err("Unsupported this length: %d!\n", msg->len);
-+ return -1;
-+ }
++ min_msgs_len = (msg->flags & I2C_M_16BIT_REG) ? 2 : 1;
++ if (msg->len < min_msgs_len) {
++ hi_err("Unsupported this length: %d!\n", msg->len);
++ return -1;
++ }
+
-+ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_AUTO) < 0) {
-+ return -1;
-+ }
++ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_AUTO) < 0) {
++ return -1;
++ }
+
-+ temp_auto_reg = HI_I2C_READ;
++ temp_auto_reg = HI_I2C_READ;
+
-+ if (msg->flags & I2C_M_16BIT_REG) {
-+ /* 16bit reg addr */
-+ temp_auto_reg |= I2C_AUTO_ADDR;
++ if (msg->flags & I2C_M_16BIT_REG) {
++ /* 16bit reg addr */
++ temp_auto_reg |= I2C_AUTO_ADDR;
+
-+ /* switch high byte and low byte */
-+ temp_reg = msg->buf[0] << 8;
-+ temp_reg |= msg->buf[1];
-+ } else {
-+ temp_reg = msg->buf[0];
-+ }
++ /* switch high byte and low byte */
++ temp_reg = msg->buf[0] << 8;
++ temp_reg |= msg->buf[1];
++ } else {
++ temp_reg = msg->buf[0];
++ }
+
-+ if (msg->flags & I2C_M_16BIT_DATA)
-+ /* 16bit data */
-+ {
-+ temp_auto_reg |= I2C_AUTO_DATA;
-+ }
++ if (msg->flags & I2C_M_16BIT_DATA)
++ /* 16bit data */
++ {
++ temp_auto_reg |= I2C_AUTO_DATA;
++ }
+
-+ writel(temp_auto_reg, pinfo->regbase + I2C_AUTO_REG);
-+ hi_msg("temp_auto_reg: 0x%x\n", temp_auto_reg);
++ writel(temp_auto_reg, pinfo->regbase + I2C_AUTO_REG);
++ hi_msg("temp_auto_reg: 0x%x\n", temp_auto_reg);
+
-+ /* 1. write addr */
-+ reg_val = temp_reg << REG_SHIFT;
-+ hi_msg("reg_val %x\n", reg_val);
++ /* 1. write addr */
++ reg_val = temp_reg << REG_SHIFT;
++ hi_msg("reg_val %x\n", reg_val);
+
-+ /* wait until tx fifo not full */
-+ if (hi_i2c_wait_txfifo_notfull(pinfo) < 0) {
-+ return -1;
-+ }
++ /* wait until tx fifo not full */
++ if (hi_i2c_wait_txfifo_notfull(pinfo) < 0) {
++ return -1;
++ }
+
-+ /* regaddr */
-+ writel(reg_val, pinfo->regbase + I2C_TX_RX_REG);
++ /* regaddr */
++ writel(reg_val, pinfo->regbase + I2C_TX_RX_REG);
+
-+ /* 2. read return data */
-+ /* wait until rx fifo not empty */
-+ if (hi_i2c_wait_rxfifo_notempty(pinfo) < 0) {
-+ return -1;
-+ }
++ /* 2. read return data */
++ /* wait until rx fifo not empty */
++ if (hi_i2c_wait_rxfifo_notempty(pinfo) < 0) {
++ return -1;
++ }
+
-+ ret_data = readl(pinfo->regbase + I2C_TX_RX_REG) & DATA_16BIT_MASK;
-+ hi_msg("ret_data = %x\n", ret_data);
++ ret_data = readl(pinfo->regbase + I2C_TX_RX_REG) & DATA_16BIT_MASK;
++ hi_msg("ret_data = %x\n", ret_data);
+
-+ if (msg->flags & I2C_M_16BIT_DATA) {
-+ pinfo->msg->buf[0] = ret_data & DATA_8BIT_MASK;
-+ pinfo->msg->buf[1] = (ret_data >> 8) & DATA_8BIT_MASK;
-+ } else {
-+ pinfo->msg->buf[0] = ret_data & DATA_8BIT_MASK;
-+ }
++ if (msg->flags & I2C_M_16BIT_DATA) {
++ pinfo->msg->buf[0] = ret_data & DATA_8BIT_MASK;
++ pinfo->msg->buf[1] = (ret_data >> 8) & DATA_8BIT_MASK;
++ } else {
++ pinfo->msg->buf[0] = ret_data & DATA_8BIT_MASK;
++ }
+
-+ writel(0x1, pinfo->regbase + I2C_CLR_INTR_REG);
++ writel(0x1, pinfo->regbase + I2C_CLR_INTR_REG);
+
-+ return 0;
++ return 0;
+}
+
+/************************************
@@ -269611,329 +337577,329 @@ index 0000000..e53d541
+#ifdef CONFIG_HI_DMAC
+void hi_i2c_dma_start(struct hi_i2c *pinfo, unsigned int dir)
+{
-+ writel((1 << dir), pinfo->regbase + I2C_DMA_CTRL_REG);
++ writel((1 << dir), pinfo->regbase + I2C_DMA_CTRL_REG);
+}
+
+void hi_i2c_dmac_config(struct hi_i2c *pinfo, unsigned int dir)
+{
-+ /* 1. enable RX(0) or TX(1) in DMA mode */
-+ hi_i2c_dma_start(pinfo, dir);
++ /* 1. enable RX(0) or TX(1) in DMA mode */
++ hi_i2c_dma_start(pinfo, dir);
+
-+ /* 2. set dma fifo */
-+ writel(4, pinfo->regbase + I2C_DMA_TDLR);
-+ writel(4, pinfo->regbase + I2C_DMA_RDLR);
++ /* 2. set dma fifo */
++ writel(4, pinfo->regbase + I2C_DMA_TDLR);
++ writel(4, pinfo->regbase + I2C_DMA_RDLR);
+}
+
+void hi_i2c_start_rx(struct hi_i2c *pinfo, unsigned int reg_addr,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ writel(reg_addr, pinfo->regbase + I2C_DMA_CMD1);
-+ writel(length, pinfo->regbase + I2C_DMA_CMD2);
++ writel(reg_addr, pinfo->regbase + I2C_DMA_CMD1);
++ writel(length, pinfo->regbase + I2C_DMA_CMD2);
+
-+ reg = readl(pinfo->regbase + I2C_DMA_CMD0);
++ reg = readl(pinfo->regbase + I2C_DMA_CMD0);
+
-+ /*start tx*/
-+ reg &= ~0x40000000;
-+ writel((0x80000000 | reg), pinfo->regbase + I2C_DMA_CMD0);
++ /*start tx*/
++ reg &= ~0x40000000;
++ writel((0x80000000 | reg), pinfo->regbase + I2C_DMA_CMD0);
+}
+
+void hi_i2c_start_tx(struct hi_i2c *pinfo, unsigned int reg_addr,
-+ unsigned int length)
++ unsigned int length)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ writel(reg_addr, pinfo->regbase + I2C_DMA_CMD1);
-+ writel(length, pinfo->regbase + I2C_DMA_CMD2);
++ writel(reg_addr, pinfo->regbase + I2C_DMA_CMD1);
++ writel(length, pinfo->regbase + I2C_DMA_CMD2);
+
-+ reg = readl(pinfo->regbase + I2C_DMA_CMD0);
++ reg = readl(pinfo->regbase + I2C_DMA_CMD0);
+
-+ /*start rx*/
-+ writel((0xc0000000 | reg), pinfo->regbase + I2C_DMA_CMD0);
++ /*start rx*/
++ writel((0xc0000000 | reg), pinfo->regbase + I2C_DMA_CMD0);
+}
+
+int dma_to_i2c(unsigned int src, unsigned int dst, unsigned int length)
+{
-+ int chan;
++ int chan;
+
-+ chan = do_dma_m2p(src, dst, length);
-+ if (chan == -1) {
-+ hi_err("dma_to_i2c error\n");
-+ }
++ chan = do_dma_m2p(src, dst, length);
++ if (chan == -1) {
++ hi_err("dma_to_i2c error\n");
++ }
+
-+ return chan;
++ return chan;
+}
+
+
+int i2c_to_dma(unsigned int src, unsigned int dst, unsigned int length)
+{
-+ int chan;
++ int chan;
+
-+ chan = do_dma_p2m(dst, src, length);
-+ if (chan == -1) {
-+ hi_err("dma_p2m error...\n");
-+ }
++ chan = do_dma_p2m(dst, src, length);
++ if (chan == -1) {
++ hi_err("dma_p2m error...\n");
++ }
+
-+ return chan;
++ return chan;
+}
+
+static int hi_i2c_do_dma_write(struct hi_i2c *pinfo,
-+ unsigned int reg_addr, unsigned int reg_addr_num,
-+ unsigned int dma_buf, unsigned int length)
++ unsigned int reg_addr, unsigned int reg_addr_num,
++ unsigned int dma_buf, unsigned int length)
+{
-+ unsigned int temp_reg = reg_addr;
-+ int chan;
++ unsigned int temp_reg = reg_addr;
++ int chan;
+
-+ /* 1. switch i2c devaddr and dma mode*/
-+ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_DMA) < 0) {
-+ return -1;
-+ }
++ /* 1. switch i2c devaddr and dma mode*/
++ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_DMA) < 0) {
++ return -1;
++ }
+
-+ if (2 == reg_addr_num) {
-+ /* switch high byte and low byte */
-+ temp_reg = REVERT_HL_BYTE(reg_addr);
-+ writel(0x10000000, pinfo->regbase + I2C_DMA_CMD0);
-+ } else {
-+ writel(0x0, pinfo->regbase + I2C_DMA_CMD0);
-+ }
++ if (2 == reg_addr_num) {
++ /* switch high byte and low byte */
++ temp_reg = REVERT_HL_BYTE(reg_addr);
++ writel(0x10000000, pinfo->regbase + I2C_DMA_CMD0);
++ } else {
++ writel(0x0, pinfo->regbase + I2C_DMA_CMD0);
++ }
+
-+ /* 2. config i2c into DMA mode */
-+ hi_i2c_dmac_config(pinfo, 0x1);
++ /* 2. config i2c into DMA mode */
++ hi_i2c_dmac_config(pinfo, 0x1);
+
-+ /* 3. start i2c logic to write */
-+ hi_i2c_start_tx(pinfo, temp_reg, length - 1);
++ /* 3. start i2c logic to write */
++ hi_i2c_start_tx(pinfo, temp_reg, length - 1);
+
-+ /* 4. transmit DATA from DMAC to I2C in DMA mode */
-+ chan = dma_to_i2c(dma_buf, (pinfo->mem->start + I2C_DATA_CMD_REG),
-+ length);
++ /* 4. transmit DATA from DMAC to I2C in DMA mode */
++ chan = dma_to_i2c(dma_buf, (pinfo->mem->start + I2C_DATA_CMD_REG),
++ length);
+
-+ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
-+ hi_err("dma wait failed\n");
-+ dmac_channel_free(chan);
-+ return -1;
-+ }
++ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
++ hi_err("dma wait failed\n");
++ dmac_channel_free(chan);
++ return -1;
++ }
+
-+ dmac_channel_free(chan);
++ dmac_channel_free(chan);
+
-+ return 0;
++ return 0;
+}
+
+static int hi_i2c_do_dma_read(struct hi_i2c *pinfo,
-+ unsigned int reg_addr, unsigned int reg_addr_num,
-+ unsigned int dma_buf, unsigned int length)
++ unsigned int reg_addr, unsigned int reg_addr_num,
++ unsigned int dma_buf, unsigned int length)
+{
-+ unsigned int temp_reg = reg_addr;
-+ int chan;
++ unsigned int temp_reg = reg_addr;
++ int chan;
+
-+ /* 1. switch i2c devaddr and dma mode*/
-+ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_DMA) < 0) {
-+ return -1;
-+ }
++ /* 1. switch i2c devaddr and dma mode*/
++ if (hi_i2c_set_dev_addr_and_mode(pinfo, I2C_MODE_DMA) < 0) {
++ return -1;
++ }
+
-+ if (2 == reg_addr_num) {
-+ /* switch high byte and low byte */
-+ temp_reg = REVERT_HL_BYTE(reg_addr);
-+ writel(0x10000000, pinfo->regbase + I2C_DMA_CMD0);
-+ } else {
-+ writel(0x0, pinfo->regbase + I2C_DMA_CMD0);
-+ }
++ if (2 == reg_addr_num) {
++ /* switch high byte and low byte */
++ temp_reg = REVERT_HL_BYTE(reg_addr);
++ writel(0x10000000, pinfo->regbase + I2C_DMA_CMD0);
++ } else {
++ writel(0x0, pinfo->regbase + I2C_DMA_CMD0);
++ }
+
-+ /* 2. config i2c into DMA mode */
-+ hi_i2c_dmac_config(pinfo, 0x0);
++ /* 2. config i2c into DMA mode */
++ hi_i2c_dmac_config(pinfo, 0x0);
+
-+ /* 3. transmit DATA from I2C to DMAC in DMA mode */
-+ chan = i2c_to_dma((pinfo->mem->start + I2C_DATA_CMD_REG),
-+ dma_buf, length);
++ /* 3. transmit DATA from I2C to DMAC in DMA mode */
++ chan = i2c_to_dma((pinfo->mem->start + I2C_DATA_CMD_REG),
++ dma_buf, length);
+
-+ /* 4. start i2c logic to read */
-+ hi_i2c_start_rx(pinfo, temp_reg, length - 1);
++ /* 4. start i2c logic to read */
++ hi_i2c_start_rx(pinfo, temp_reg, length - 1);
+
-+ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
-+ hi_err("dma wait failed\n");
-+ dmac_channel_free(chan);
-+ return -1;
-+ }
++ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) {
++ hi_err("dma wait failed\n");
++ dmac_channel_free(chan);
++ return -1;
++ }
+
-+ dmac_channel_free(chan);
++ dmac_channel_free(chan);
+
-+ return 0;
++ return 0;
+}
+
+#else
+static int hi_i2c_do_dma_write(struct hi_i2c *pinfo,
-+ unsigned int reg_addr, unsigned int reg_addr_num,
-+ unsigned int dma_buf, unsigned int length)
++ unsigned int reg_addr, unsigned int reg_addr_num,
++ unsigned int dma_buf, unsigned int length)
+{
-+ hi_err("DMA is not enabled!");
-+ return -1;
++ hi_err("DMA is not enabled!");
++ return -1;
+}
+
+static int hi_i2c_do_dma_read(struct hi_i2c *pinfo,
-+ unsigned int reg_addr, unsigned int reg_addr_num,
-+ unsigned int dma_buf, unsigned int length)
++ unsigned int reg_addr, unsigned int reg_addr_num,
++ unsigned int dma_buf, unsigned int length)
+{
-+ hi_err("DMA is not enabled!");
-+ return -1;
++ hi_err("DMA is not enabled!");
++ return -1;
+}
+#endif
+
+int hi_i2c_dma_write(const struct i2c_client *client, unsigned int dma_buf,
-+ unsigned int reg_addr, unsigned int reg_addr_num,
-+ unsigned int length)
++ unsigned int reg_addr, unsigned int reg_addr_num,
++ unsigned int length)
+{
-+ struct i2c_adapter *adap = client->adapter;
-+ struct hi_i2c *pinfo = (struct hi_i2c *)i2c_get_adapdata(adap);
-+ struct i2c_msg msg;
-+ int ret;
-+ unsigned long flags;
++ struct i2c_adapter *adap = client->adapter;
++ struct hi_i2c *pinfo = (struct hi_i2c *)i2c_get_adapdata(adap);
++ struct i2c_msg msg;
++ int ret;
++ unsigned long flags;
+
-+ spin_lock_irqsave(&adap->spinlock, flags);
++ spin_lock_irqsave(&adap->spinlock, flags);
+
-+ memset(&msg, 0x0, sizeof(struct i2c_msg));
-+ msg.addr = client->addr;
-+ msg.flags = client->flags;
-+ msg.len = length;
++ memset(&msg, 0x0, sizeof(struct i2c_msg));
++ msg.addr = client->addr;
++ msg.flags = client->flags;
++ msg.len = length;
+
-+ pinfo->msg = &msg;
++ pinfo->msg = &msg;
+
-+ ret = hi_i2c_do_dma_write(pinfo, reg_addr, reg_addr_num, dma_buf,
-+ length);
++ ret = hi_i2c_do_dma_write(pinfo, reg_addr, reg_addr_num, dma_buf,
++ length);
+
-+ spin_unlock_irqrestore(&adap->spinlock, flags);
++ spin_unlock_irqrestore(&adap->spinlock, flags);
+
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(hi_i2c_dma_write);
+
+int hi_i2c_dma_read(const struct i2c_client *client, unsigned int dma_buf,
-+ unsigned int reg_addr, unsigned int reg_addr_num,
-+ unsigned int length)
++ unsigned int reg_addr, unsigned int reg_addr_num,
++ unsigned int length)
+{
-+ struct i2c_adapter *adap = client->adapter;
-+ struct hi_i2c *pinfo = (struct hi_i2c *)i2c_get_adapdata(adap);
-+ struct i2c_msg msg;
-+ int ret;
-+ unsigned long flags;
++ struct i2c_adapter *adap = client->adapter;
++ struct hi_i2c *pinfo = (struct hi_i2c *)i2c_get_adapdata(adap);
++ struct i2c_msg msg;
++ int ret;
++ unsigned long flags;
+
-+ spin_lock_irqsave(&adap->spinlock, flags);
++ spin_lock_irqsave(&adap->spinlock, flags);
+
-+ memset(&msg, 0x0, sizeof(struct i2c_msg));
-+ msg.addr = client->addr;
-+ msg.flags = client->flags;
-+ msg.flags |= I2C_M_RD;
-+ msg.len = length;
++ memset(&msg, 0x0, sizeof(struct i2c_msg));
++ msg.addr = client->addr;
++ msg.flags = client->flags;
++ msg.flags |= I2C_M_RD;
++ msg.len = length;
+
-+ pinfo->msg = &msg;
++ pinfo->msg = &msg;
+
-+ ret = hi_i2c_do_dma_read(pinfo, reg_addr, reg_addr_num, dma_buf,
-+ length);
++ ret = hi_i2c_do_dma_read(pinfo, reg_addr, reg_addr_num, dma_buf,
++ length);
+
-+ spin_unlock_irqrestore(&adap->spinlock, flags);
++ spin_unlock_irqrestore(&adap->spinlock, flags);
+
-+ return ret;
++ return ret;
+}
+EXPORT_SYMBOL(hi_i2c_dma_read);
+
+static int hi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
-+ int num)
++ int num)
+{
-+ struct hi_i2c *pinfo = (struct hi_i2c *)i2c_get_adapdata(adap);
-+ unsigned int msg_idx;
-+ dma_addr_t dma_buf;
-+ __u16 len;
-+ unsigned int reg_addr;
-+ unsigned int reg_width;
-+ int ret;
-+ unsigned long flags;
++ struct hi_i2c *pinfo = (struct hi_i2c *)i2c_get_adapdata(adap);
++ unsigned int msg_idx;
++ dma_addr_t dma_buf;
++ __u16 len;
++ unsigned int reg_addr;
++ unsigned int reg_width;
++ int ret;
++ unsigned long flags;
+
-+ if (!msgs || (num <= 0)) {
-+ hi_err("msgs == NULL || num <= 0, Invalid argument!\n");
-+ return -EINVAL;
-+ }
++ if (!msgs || (num <= 0)) {
++ hi_err("msgs == NULL || num <= 0, Invalid argument!\n");
++ return -EINVAL;
++ }
+
-+ spin_lock_irqsave(&pinfo->spinlock, flags);
++ spin_lock_irqsave(&pinfo->spinlock, flags);
+
-+ pinfo->msg = msgs;
++ pinfo->msg = msgs;
+
-+ for (msg_idx = 0; msg_idx < num; msg_idx++) {
-+ len = pinfo->msg->len;
-+ if (pinfo->msg->flags & I2C_M_16BIT_REG) {
-+ reg_addr = pinfo->msg->buf[0];
-+ reg_addr |= pinfo->msg->buf[1] << 8;
-+ reg_width = 2;
-+ } else {
-+ reg_addr = pinfo->msg->buf[0];
-+ reg_width = 1;
-+ }
++ for (msg_idx = 0; msg_idx < num; msg_idx++) {
++ len = pinfo->msg->len;
++ if (pinfo->msg->flags & I2C_M_16BIT_REG) {
++ reg_addr = pinfo->msg->buf[0];
++ reg_addr |= pinfo->msg->buf[1] << 8;
++ reg_width = 2;
++ } else {
++ reg_addr = pinfo->msg->buf[0];
++ reg_width = 1;
++ }
+
-+ if (pinfo->msg->flags & I2C_M_DMA) {
-+ if (pinfo->msg->flags & I2C_M_16BIT_DATA) {
-+ hi_err("I2C DMA no support I2C_M_16BIT_DATA\n");
-+ ret = -EINVAL;
-+ goto end;
-+ }
++ if (pinfo->msg->flags & I2C_M_DMA) {
++ if (pinfo->msg->flags & I2C_M_16BIT_DATA) {
++ hi_err("I2C DMA no support I2C_M_16BIT_DATA\n");
++ ret = -EINVAL;
++ goto end;
++ }
+
-+ if (((pinfo->msg->flags & I2C_M_RD) && (len <= 0)) ||
-+ (!(pinfo->msg->flags & I2C_M_RD) &&
-+ (len <= reg_width))) {
-+ hi_err("msg->len == %d, Invalid argument!\n",
-+ len);
-+ ret = -EINVAL;
-+ goto end;
-+ }
++ if (((pinfo->msg->flags & I2C_M_RD) && (len <= 0)) ||
++ (!(pinfo->msg->flags & I2C_M_RD) &&
++ (len <= reg_width))) {
++ hi_err("msg->len == %d, Invalid argument!\n",
++ len);
++ ret = -EINVAL;
++ goto end;
++ }
+
-+ dma_buf = dma_map_single(pinfo->dev,
-+ pinfo->msg->buf, len,
-+ DMA_BIDIRECTIONAL);
-+ if (dma_mapping_error(pinfo->dev, dma_buf)) {
-+ hi_err("DMA mapping failed\n");
-+ ret = -EINVAL;
-+ goto end;
-+ }
++ dma_buf = dma_map_single(pinfo->dev,
++ pinfo->msg->buf, len,
++ DMA_BIDIRECTIONAL);
++ if (dma_mapping_error(pinfo->dev, dma_buf)) {
++ hi_err("DMA mapping failed\n");
++ ret = -EINVAL;
++ goto end;
++ }
+
-+ if (pinfo->msg->flags & I2C_M_RD)
-+ ret = hi_i2c_do_dma_read(pinfo, reg_addr,
-+ reg_width, dma_buf, len);
-+ else
-+ ret = hi_i2c_do_dma_write(pinfo, reg_addr,
-+ reg_width, dma_buf + reg_width,
-+ len - reg_width);
++ if (pinfo->msg->flags & I2C_M_RD)
++ ret = hi_i2c_do_dma_read(pinfo, reg_addr,
++ reg_width, dma_buf, len);
++ else
++ ret = hi_i2c_do_dma_write(pinfo, reg_addr,
++ reg_width, dma_buf + reg_width,
++ len - reg_width);
+
-+ dma_unmap_single(pinfo->dev, dma_buf, len,
-+ DMA_BIDIRECTIONAL);
++ dma_unmap_single(pinfo->dev, dma_buf, len,
++ DMA_BIDIRECTIONAL);
+
-+ if (ret) {
-+ break;
-+ }
-+ } else {
-+ if (pinfo->msg->flags & I2C_M_RD) {
-+ ret = hi_i2c_read(pinfo);
-+ } else {
-+ ret = hi_i2c_write(pinfo);
-+ }
++ if (ret) {
++ break;
++ }
++ } else {
++ if (pinfo->msg->flags & I2C_M_RD) {
++ ret = hi_i2c_read(pinfo);
++ } else {
++ ret = hi_i2c_write(pinfo);
++ }
+
-+ if (ret) {
-+ break;
-+ }
-+ }
-+ pinfo->msg++;
-+ }
++ if (ret) {
++ break;
++ }
++ }
++ pinfo->msg++;
++ }
+
-+ if (!ret || msg_idx > 0) {
-+ ret = msg_idx;
-+ } else {
-+ ret = -EIO;
-+ }
++ if (!ret || msg_idx > 0) {
++ ret = msg_idx;
++ } else {
++ ret = -EIO;
++ }
+
+end:
-+ spin_unlock_irqrestore(&pinfo->spinlock, flags);
++ spin_unlock_irqrestore(&pinfo->spinlock, flags);
+
-+ /*
-+ * If everything went ok (i.e. 1 msg transmitted), (ret = 1) means return #bytes
-+ * transmitted, else return error code. see i2c-core.c
-+ */
-+ return ret;
++ /*
++ * If everything went ok (i.e. 1 msg transmitted), (ret = 1) means return #bytes
++ * transmitted, else return error code. see i2c-core.c
++ */
++ return ret;
+}
+
+/* HI I2C READ *
@@ -269945,51 +337911,51 @@ index 0000000..e53d541
+ * Returns negative errno, or else the number of bytes read.
+ */
+int hi_i2c_master_recv(const struct i2c_client *client, char *buf,
-+ int count)
++ int count)
+{
-+ struct i2c_adapter *adap = client->adapter;
-+ struct i2c_msg msgs;
-+ unsigned int reg_width, data_width, max_width;
-+ int msgs_count;
++ struct i2c_adapter *adap = client->adapter;
++ struct i2c_msg msgs;
++ unsigned int reg_width, data_width, max_width;
++ int msgs_count;
+
-+ memset(&msgs, 0x0, sizeof(struct i2c_msg));
-+ msgs.addr = client->addr;
-+ msgs.flags = client->flags;
-+ msgs.flags |= I2C_M_RD;
++ memset(&msgs, 0x0, sizeof(struct i2c_msg));
++ msgs.addr = client->addr;
++ msgs.flags = client->flags;
++ msgs.flags |= I2C_M_RD;
+
-+ if (client->flags & I2C_M_16BIT_REG) {
-+ reg_width = 2;
-+ } else {
-+ reg_width = 1;
-+ }
++ if (client->flags & I2C_M_16BIT_REG) {
++ reg_width = 2;
++ } else {
++ reg_width = 1;
++ }
+
-+ if (client->flags & I2C_M_16BIT_DATA) {
-+ data_width = 2;
-+ } else {
-+ data_width = 1;
-+ }
++ if (client->flags & I2C_M_16BIT_DATA) {
++ data_width = 2;
++ } else {
++ data_width = 1;
++ }
+
-+ max_width = max_t(size_t, reg_width, data_width);
++ max_width = max_t(size_t, reg_width, data_width);
+
-+ if (count > max_width) {
-+ msgs.flags |= I2C_M_DMA;
-+ msgs.len = count;
-+ } else if (count <= 0 ) {
-+ hi_err("ERR. Invalid count: 0x%d!!!\n", count);
-+ return -EINVAL;
-+ } else {
-+ msgs.len = max_width;
-+ }
++ if (count > max_width) {
++ msgs.flags |= I2C_M_DMA;
++ msgs.len = count;
++ } else if (count <= 0 ) {
++ hi_err("ERR. Invalid count: 0x%d!!!\n", count);
++ return -EINVAL;
++ } else {
++ msgs.len = max_width;
++ }
+
-+ if (!buf) {
-+ hi_err("ERR. Invalid buf == NULL!!!\n");
-+ return -EINVAL;
-+ }
-+ msgs.buf = buf;
++ if (!buf) {
++ hi_err("ERR. Invalid buf == NULL!!!\n");
++ return -EINVAL;
++ }
++ msgs.buf = buf;
+
-+ msgs_count = hi_i2c_xfer(adap, &msgs, 1);
++ msgs_count = hi_i2c_xfer(adap, &msgs, 1);
+
-+ return (msgs_count == 1) ? count : -EIO;
++ return (msgs_count == 1) ? count : -EIO;
+}
+EXPORT_SYMBOL(hi_i2c_master_recv);
+
@@ -270002,47 +337968,47 @@ index 0000000..e53d541
+ * Returns negative errno, or else the number of bytes written.
+ */
+int hi_i2c_master_send(const struct i2c_client *client,
-+ const char *buf, int count)
++ const char *buf, int count)
+{
-+ struct i2c_adapter *adap = client->adapter;
-+ struct i2c_msg msgs;
-+ unsigned int reg_width, data_width;
-+ int msgs_count;
++ struct i2c_adapter *adap = client->adapter;
++ struct i2c_msg msgs;
++ unsigned int reg_width, data_width;
++ int msgs_count;
+
-+ memset(&msgs, 0x0, sizeof(struct i2c_msg));
-+ msgs.addr = client->addr;
-+ msgs.flags = client->flags;
++ memset(&msgs, 0x0, sizeof(struct i2c_msg));
++ msgs.addr = client->addr;
++ msgs.flags = client->flags;
+
-+ if (client->flags & I2C_M_16BIT_REG) {
-+ reg_width = 2;
-+ } else {
-+ reg_width = 1;
-+ }
++ if (client->flags & I2C_M_16BIT_REG) {
++ reg_width = 2;
++ } else {
++ reg_width = 1;
++ }
+
-+ if (client->flags & I2C_M_16BIT_DATA) {
-+ data_width = 2;
-+ } else {
-+ data_width = 1;
-+ }
++ if (client->flags & I2C_M_16BIT_DATA) {
++ data_width = 2;
++ } else {
++ data_width = 1;
++ }
+
-+ if (count - reg_width > data_width) {
-+ msgs.flags |= I2C_M_DMA;
-+ } else if (count - reg_width < data_width) {
-+ hi_err("ERR. Invalid count!!!\n");
-+ return -EINVAL;
-+ }
++ if (count - reg_width > data_width) {
++ msgs.flags |= I2C_M_DMA;
++ } else if (count - reg_width < data_width) {
++ hi_err("ERR. Invalid count!!!\n");
++ return -EINVAL;
++ }
+
-+ msgs.len = count;
++ msgs.len = count;
+
-+ if (!buf) {
-+ hi_err("ERR. Invalid buf! == NULL!!\n");
-+ return -EINVAL;
-+ }
-+ msgs.buf = (__u8 *)buf;
++ if (!buf) {
++ hi_err("ERR. Invalid buf! == NULL!!\n");
++ return -EINVAL;
++ }
++ msgs.buf = (__u8 *)buf;
+
-+ msgs_count = hi_i2c_xfer(adap, &msgs, 1);
++ msgs_count = hi_i2c_xfer(adap, &msgs, 1);
+
-+ return (msgs_count == 1) ? count : -EIO;
++ return (msgs_count == 1) ? count : -EIO;
+}
+EXPORT_SYMBOL(hi_i2c_master_send);
+
@@ -270059,174 +338025,174 @@ index 0000000..e53d541
+ * the same slave address, although that is the most common model.
+ */
+int hi_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
-+ int num)
++ int num)
+{
-+ printk("Wrong interface call."
-+ "hi_i2c_master_recv is the only interface to i2c read!!!\n");
++ printk("Wrong interface call."
++ "hi_i2c_master_recv is the only interface to i2c read!!!\n");
+
-+ return -EIO;
++ return -EIO;
+}
+EXPORT_SYMBOL(hi_i2c_transfer);
+/**************************************************************/
+
+static u32 hi_i2c_func(struct i2c_adapter *adap)
+{
-+ return I2C_FUNC_I2C;
++ return I2C_FUNC_I2C;
+}
+
+static const struct i2c_algorithm hi_i2c_algo = {
-+ .master_xfer = hi_i2c_xfer,
-+ .functionality = hi_i2c_func,
++ .master_xfer = hi_i2c_xfer,
++ .functionality = hi_i2c_func,
+};
+
+static int hi_i2c_probe(struct platform_device *pdev)
+{
-+ int errorcode;
-+ struct hi_i2c *pinfo;
-+ struct i2c_adapter *adap;
-+ struct resource *mem;
-+ struct hi_platform_i2c *platform_info;
-+ int tmp = 0;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = pdev->dev.of_node;
++ int errorcode;
++ struct hi_i2c *pinfo = NULL;
++ struct i2c_adapter *adap = NULL;
++ struct resource *mem = NULL;
++ struct hi_platform_i2c *platform_info = NULL;
++ int tmp = 0;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node;
+
-+ pdev->name = I2C_HISI;
-+ tmp = of_property_read_u32(np, "id", &pdev->id);
-+ if (tmp) {
-+ dev_err(&pdev->dev, "Get id failed!\n");
-+ errorcode = -EBADF;
-+ goto i2c_errorcode_na;
-+ }
++ pdev->name = I2C_HISI;
++ tmp = of_property_read_u32(np, "id", &pdev->id);
++ if (tmp) {
++ dev_err(&pdev->dev, "Get id failed!\n");
++ errorcode = -EBADF;
++ goto i2c_errorcode_na;
++ }
+
-+ platform_info = devm_kzalloc(dev, sizeof(*platform_info), GFP_KERNEL);
-+ if (!platform_info) {
-+ return -ENOMEM;
-+ }
++ platform_info = devm_kzalloc(dev, sizeof(*platform_info), GFP_KERNEL);
++ if (!platform_info) {
++ return -ENOMEM;
++ }
+
-+ mem = devm_kzalloc(dev, sizeof(*mem), GFP_KERNEL);
-+ if (!mem) {
-+ return -ENOMEM;
-+ }
++ mem = devm_kzalloc(dev, sizeof(*mem), GFP_KERNEL);
++ if (!mem) {
++ return -ENOMEM;
++ }
+
-+ tmp = of_property_read_u32(np, "clock-frequency", &platform_info->clk_limit);
-+ if (tmp) {
-+ dev_err(&pdev->dev, "Get clock-frequency failed!\n");
-+ errorcode = -EBADF;
-+ goto i2c_errorcode_na;
-+ }
-+ platform_info->i2c_class = I2C_CLASS_DDC;
++ tmp = of_property_read_u32(np, "clock-frequency", &platform_info->clk_limit);
++ if (tmp) {
++ dev_err(&pdev->dev, "Get clock-frequency failed!\n");
++ errorcode = -EBADF;
++ goto i2c_errorcode_na;
++ }
++ platform_info->i2c_class = I2C_CLASS_DDC;
+
-+ dev->platform_data = platform_info;
++ dev->platform_data = platform_info;
+
-+ pinfo = kzalloc(sizeof(struct hi_i2c), GFP_KERNEL);
-+ if (pinfo == NULL) {
-+ dev_err(&pdev->dev, "Out of memory!\n");
-+ errorcode = -ENOMEM;
-+ goto i2c_errorcode_na;
-+ }
++ pinfo = kzalloc(sizeof(struct hi_i2c), GFP_KERNEL);
++ if (pinfo == NULL) {
++ dev_err(&pdev->dev, "Out of memory!\n");
++ errorcode = -ENOMEM;
++ goto i2c_errorcode_na;
++ }
+
-+ tmp = of_property_read_u32(np, "reg", &mem->start);
-+ if (tmp) {
-+ dev_err(&pdev->dev, "Get reg failed!\n");
-+ errorcode = -ENXIO;
-+ goto i2c_errorcode_na;
-+ }
++ tmp = of_property_read_u32(np, "reg", &mem->start);
++ if (tmp) {
++ dev_err(&pdev->dev, "Get reg failed!\n");
++ errorcode = -ENXIO;
++ goto i2c_errorcode_na;
++ }
+
-+ tmp = of_property_read_u32(np, "io-size", &mem->end);
-+ if (tmp) {
-+ dev_err(&pdev->dev, "Get io-size failed!\n");
-+ errorcode = -EBADF;
-+ goto i2c_errorcode_na;
-+ }
-+ mem->end = mem->start + mem->end - 1;
-+ mem->flags = IORESOURCE_MEM;
-+ pdev->resource = mem;
-+ pinfo->regbase = (unsigned char __iomem *)IO_ADDRESS(mem->start);
-+ pinfo->mem = mem;
-+ /* find the clock and enable it */
-+ pinfo->clk = devm_clk_get(&pdev->dev, NULL);
-+ pinfo->dev = &pdev->dev;
-+ pinfo->pdata = platform_info;
-+ pinfo->g_last_dev_addr = 0;
++ tmp = of_property_read_u32(np, "io-size", &mem->end);
++ if (tmp) {
++ dev_err(&pdev->dev, "Get io-size failed!\n");
++ errorcode = -EBADF;
++ goto i2c_errorcode_na;
++ }
++ mem->end = mem->start + mem->end - 1;
++ mem->flags = IORESOURCE_MEM;
++ pdev->resource = mem;
++ pinfo->regbase = (unsigned char __iomem *)IO_ADDRESS(mem->start);
++ pinfo->mem = mem;
++ /* find the clock and enable it */
++ pinfo->clk = devm_clk_get(&pdev->dev, NULL);
++ pinfo->dev = &pdev->dev;
++ pinfo->pdata = platform_info;
++ pinfo->g_last_dev_addr = 0;
+
-+ spin_lock_init(&pinfo->spinlock);
++ spin_lock_init(&pinfo->spinlock);
+
-+ hi_i2c_hw_init(pinfo);
++ hi_i2c_hw_init(pinfo);
+
-+ platform_set_drvdata(pdev, pinfo);
++ platform_set_drvdata(pdev, pinfo);
+
-+ adap = &pinfo->adap;
-+ i2c_set_adapdata(adap, pinfo);
-+ adap->owner = THIS_MODULE;
-+ adap->class = platform_info->i2c_class;
-+ strlcpy(adap->name, pdev->name, sizeof(adap->name));
-+ adap->algo = &hi_i2c_algo;
-+ adap->dev.parent = &pdev->dev;
-+ adap->nr = pdev->id;
-+ adap->retries = HI_I2C_RETRIES;
-+ errorcode = i2c_add_numbered_adapter(adap);
-+ if (errorcode) {
-+ dev_err(&pdev->dev,
-+ "%s: Adding I2C adapter failed!\n", __func__);
-+ goto i2c_errorcode_free_irq;
-+ }
-+ dev_notice(&pdev->dev,
-+ "Hisilicon [%s] probed!\n",
-+ dev_name(&pinfo->adap.dev));
++ adap = &pinfo->adap;
++ i2c_set_adapdata(adap, pinfo);
++ adap->owner = THIS_MODULE;
++ adap->class = platform_info->i2c_class;
++ strlcpy(adap->name, pdev->name, sizeof(adap->name));
++ adap->algo = &hi_i2c_algo;
++ adap->dev.parent = &pdev->dev;
++ adap->nr = pdev->id;
++ adap->retries = HI_I2C_RETRIES;
++ errorcode = i2c_add_numbered_adapter(adap);
++ if (errorcode) {
++ dev_err(&pdev->dev,
++ "%s: Adding I2C adapter failed!\n", __func__);
++ goto i2c_errorcode_free_irq;
++ }
++ dev_notice(&pdev->dev,
++ "Hisilicon [%s] probed!\n",
++ dev_name(&pinfo->adap.dev));
+
-+ goto i2c_errorcode_na;
++ goto i2c_errorcode_na;
+
+i2c_errorcode_free_irq:
-+ free_irq(pinfo->irq, pinfo);
-+ kfree(pinfo);
++ free_irq(pinfo->irq, pinfo);
++ kfree(pinfo);
+
+i2c_errorcode_na:
-+ return errorcode;
++ return errorcode;
+}
+
+static int hi_i2c_remove(struct platform_device *pdev)
+{
-+ struct hi_i2c *pinfo = NULL;
-+ int errorcode = 0;
++ struct hi_i2c *pinfo = NULL;
++ int errorcode = 0;
+
-+ pinfo = platform_get_drvdata(pdev);
++ pinfo = platform_get_drvdata(pdev);
+
-+ if (pinfo) {
-+ i2c_del_adapter(&pinfo->adap);
++ if (pinfo) {
++ i2c_del_adapter(&pinfo->adap);
+
-+ free_irq(pinfo->irq, pinfo);
++ free_irq(pinfo->irq, pinfo);
+
-+ kfree(pinfo);
-+ }
++ kfree(pinfo);
++ }
+
-+ dev_notice(&pdev->dev,
-+ "Remove Hisilicon Media Processor"
-+ "I2C adapter [%d].\n", errorcode);
++ dev_notice(&pdev->dev,
++ "Remove Hisilicon Media Processor"
++ "I2C adapter [%d].\n", errorcode);
+
-+ return errorcode;
++ return errorcode;
+}
+
+#ifdef CONFIG_PM
+static int hi_i2c_suspend(struct platform_device *pdev, pm_message_t state)
+{
-+ struct hi_i2c *pinfo;
++ struct hi_i2c *pinfo;
+
-+ pinfo = platform_get_drvdata(pdev);
++ pinfo = platform_get_drvdata(pdev);
+
-+ hi_i2c_abortprocess(pinfo);
++ hi_i2c_abortprocess(pinfo);
+
-+ return 0;
++ return 0;
+}
+
+static int hi_i2c_resume(struct platform_device *pdev)
+{
-+ struct hi_i2c *pinfo;
++ struct hi_i2c *pinfo;
+
-+ pinfo = platform_get_drvdata(pdev);
++ pinfo = platform_get_drvdata(pdev);
+
-+ hi_i2c_hw_init(pinfo);
++ hi_i2c_hw_init(pinfo);
+
-+ return 0;
++ return 0;
+}
+#else
+#define hi_i2c_suspend NULL
@@ -270235,23 +338201,23 @@ index 0000000..e53d541
+
+/******************************************************************************/
+static const struct of_device_id hi_i2c_match[] = {
-+ { .compatible = "hisilicon,hisi-i2c-hisilicon"},
-+ {}
++ { .compatible = "hisilicon,hisi-i2c-hisilicon"},
++ {}
+};
+MODULE_DEVICE_TABLE(of, hi_i2c_match);
+/******************************************************************************/
+
+static struct platform_driver hi_i2c_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "hisi-i2c-hisilicon",
-+ .of_match_table = of_match_ptr(hi_i2c_match),
-+ },
-+ .probe = hi_i2c_probe,
-+ .remove = hi_i2c_remove,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "hisi-i2c-hisilicon",
++ .of_match_table = of_match_ptr(hi_i2c_match),
++ },
++ .probe = hi_i2c_probe,
++ .remove = hi_i2c_remove,
+#ifdef CONFIG_PM
-+ .suspend = hi_i2c_suspend,
-+ .resume = hi_i2c_resume,
++ .suspend = hi_i2c_suspend,
++ .resume = hi_i2c_resume,
+#endif
+};
+
@@ -270262,7 +338228,7 @@ index 0000000..e53d541
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-hisilicon.h b/drivers/i2c/busses/i2c-hisilicon.h
new file mode 100644
-index 0000000..e453e78
+index 0000000..e374378
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hisilicon.h
@@ -0,0 +1,129 @@
@@ -270383,15 +338349,15 @@ index 0000000..e453e78
+#define ENABLE_ALL_INTERRUPTS DEFAULT_I2C_REG_IMSC
+
+typedef enum i2c_mode_e {
-+ I2C_MODE_AUTO,
-+ I2C_MODE_DMA,
-+ I2C_MODE_NONE,
++ I2C_MODE_AUTO,
++ I2C_MODE_DMA,
++ I2C_MODE_NONE,
+} i2c_mode_e;
+
+struct hi_platform_i2c {
-+ int clk_limit;
-+ unsigned int i2c_class;
-+ unsigned int clk_rate;
++ int clk_limit;
++ unsigned int i2c_class;
++ unsigned int clk_rate;
+};
+
+#endif
@@ -271516,16 +339482,15 @@ index 6f638bb..d9cd820 100644
funcs = i2c_get_functionality(client->adapter);
return put_user(funcs, (unsigned long __user *)arg);
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
-index 99c0514..0fe8442 100644
+index 99c0514..a548bff 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
-@@ -225,6 +225,16 @@ config HI8435
+@@ -225,6 +225,15 @@ config HI8435
This driver can also be built as a module. If so, the module will be
called hi8435.
+config HIBVT_LSADC
+ tristate "HIBVT LSADC driver"
-+ depends on ARCH_HISI_BVT || COMPILE_TEST
+ help
+ Say yes here to build support for the LSADC found in SoCs from
+ hisilicon BVT chip.
@@ -271550,10 +339515,10 @@ index 7a40c04..6554d92 100644
obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
diff --git a/drivers/iio/adc/hibvt_lsadc.c b/drivers/iio/adc/hibvt_lsadc.c
new file mode 100644
-index 0000000..9304036
+index 0000000..7907490
--- /dev/null
+++ b/drivers/iio/adc/hibvt_lsadc.c
-@@ -0,0 +1,336 @@
+@@ -0,0 +1,334 @@
+/*
+ * Hisilicon BVT Low Speed (LS) A/D Converter
+ * Copyright (C) 2018 HiSilicon Technologies Co., Ltd.
@@ -271637,8 +339602,8 @@ index 0000000..9304036
+};
+
+static int hibvt_lsadc_read_raw(struct iio_dev *indio_dev,
-+ struct iio_chan_spec const *chan,
-+ int *val, int *val2, long mask)
++ struct iio_chan_spec const *chan,
++ int *val, int *val2, long mask)
+{
+ struct hibvt_lsadc *info = iio_priv(indio_dev);
+
@@ -271655,7 +339620,7 @@ index 0000000..9304036
+ info->data->start_conv(info);
+
+ if (!wait_for_completion_timeout(&info->completion,
-+ HIBVT_LSADC_TIMEOUT)) {
++ HIBVT_LSADC_TIMEOUT)) {
+ if (info->data->stop_conv)
+ info->data->stop_conv(info);
+ mutex_unlock(&indio_dev->mlock);
@@ -271690,7 +339655,7 @@ index 0000000..9304036
+
+ /* Read value */
+ info->value = readl(info->regs +
-+ HIBVT_LSADC_CHNDATA + (info->cur_chn << 2));
++ HIBVT_LSADC_CHNDATA + (info->cur_chn << 2));
+ info->value &= GENMASK(info->data->num_bits - 1, 0);
+
+ /* stop adc */
@@ -271719,8 +339684,6 @@ index 0000000..9304036
+static const struct iio_chan_spec hibvt_lsadc_iio_channels[] = {
+ HIBVT_LSADC_CHANNEL(0, "adc0"),
+ HIBVT_LSADC_CHANNEL(1, "adc1"),
-+ HIBVT_LSADC_CHANNEL(2, "adc2"),
-+ HIBVT_LSADC_CHANNEL(3, "adc3"),
+};
+
+static void hibvt_lsadc_clear_irq(struct hibvt_lsadc *info, int mask)
@@ -271740,8 +339703,8 @@ index 0000000..9304036
+ con = readl(info->regs + HIBVT_LSADC_CONFIG);
+ con &= ~HIBVT_CONFIG_RESET;
+ con |= (HIBVT_CONFIG_DEGLITCH | HIBVT_CONFIG_MODE);
-+ con &= ~(HIBVT_CONFIG_CHN0 | HIBVT_CONFIG_CHN1 |
-+ HIBVT_CONFIG_CHN2 | HIBVT_CONFIG_CHN3);
++ con &= ~(HIBVT_CONFIG_CHN0 | HIBVT_CONFIG_CHN1 |
++ HIBVT_CONFIG_CHN2 | HIBVT_CONFIG_CHN3);
+ con |= (HIBVT_CONFIG_CHN0 << info->cur_chn);
+ writel(con, (info->regs + HIBVT_LSADC_CONFIG));
+
@@ -271782,7 +339745,7 @@ index 0000000..9304036
+
+static const struct of_device_id hibvt_lsadc_match[] = {
+ {
-+ .compatible = "hisilicon,hi3519av100-lsadc",
++ .compatible = "hisilicon,hisi-lsadc",
+ .data = &lsadc_data,
+ },
+ {},
@@ -271802,8 +339765,8 @@ index 0000000..9304036
+ struct hibvt_lsadc *info = NULL;
+ struct device_node *np = pdev->dev.of_node;
+ struct iio_dev *indio_dev = NULL;
-+ struct resource *mem;
-+ const struct of_device_id *match;
++ struct resource *mem = NULL;
++ const struct of_device_id *match = NULL;
+ int ret;
+ int irq;
+
@@ -271887,7 +339850,7 @@ index 0000000..9304036
+
+module_platform_driver(hibvt_lsadc_driver);
+
-+MODULE_AUTHOR("Allen Liu <liurenzhong@hisilicon.com>");
++MODULE_AUTHOR("hisilicon");
+MODULE_DESCRIPTION("hisilicon BVT LSADC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
@@ -271932,16 +339895,17 @@ index 19d642e..26e1d7f 100644
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
-index d6c404b..1709f7a 100644
+index d6c404b..d6c999b 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
-@@ -122,7 +122,23 @@ static DEFINE_RAW_SPINLOCK(cpu_map_lock);
+@@ -122,7 +122,24 @@ static DEFINE_RAW_SPINLOCK(cpu_map_lock);
static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
-
-+#if defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)\
-+ || defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300)
++#if defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3516CV500)|| defined(CONFIG_ARCH_HI3516DV300)|| \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+#ifdef CONFIG_ARCH_HISI_BVT_AMP
+/*
+ *Uesed to process gic sgi interrupt *
@@ -271960,12 +339924,13 @@ index d6c404b..1709f7a 100644
static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
static struct gic_kvm_info gic_v2_kvm_info;
-@@ -347,7 +363,27 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
+@@ -347,7 +364,28 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
return IRQ_SET_MASK_OK_DONE;
}
#endif
-+#if defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)\
-+ || defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300)
++#if defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+#ifdef CONFIG_ARCH_HISI_BVT_AMP
+/* used to process dis irq */
+int dis_irq_proc(u32 irqnr, u32 irqstat, struct pt_regs *regs)
@@ -271988,12 +339953,13 @@ index d6c404b..1709f7a 100644
static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
{
u32 irqstat, irqnr;
-@@ -368,6 +404,14 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+@@ -368,6 +406,15 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
if (static_key_true(&supports_deactivate))
writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
-+#if defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)\
-+ || defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300)
++#if defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+#ifdef CONFIG_ARCH_HISI_BVT_AMP
+ /*Call dis irq proccess func*/
+ if (dis_irq_proc(irqnr, irqstat, regs))
@@ -272003,11 +339969,11 @@ index d6c404b..1709f7a 100644
#ifdef CONFIG_SMP
/*
* Ensure any shared data written by the CPU sending
-@@ -466,7 +510,31 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
+@@ -466,7 +513,31 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
}
-+#ifdef CONFIG_ARCH_HI3559AV100
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+#include "irq-map-hi3559av100.h"
+static void gic_dist_init_amp(struct gic_chip_data *gic)
+{
@@ -272035,7 +340001,7 @@ index d6c404b..1709f7a 100644
static void gic_dist_init(struct gic_chip_data *gic)
{
unsigned int i;
-@@ -489,6 +557,7 @@ static void gic_dist_init(struct gic_chip_data *gic)
+@@ -489,6 +560,7 @@ static void gic_dist_init(struct gic_chip_data *gic)
writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
}
@@ -272043,7 +340009,7 @@ index d6c404b..1709f7a 100644
static int gic_cpu_init(struct gic_chip_data *gic)
{
-@@ -1069,7 +1138,9 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
+@@ -1069,7 +1141,9 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
{
irq_hw_number_t hwirq_base;
int gic_irqs, irq_base, ret;
@@ -272054,7 +340020,7 @@ index d6c404b..1709f7a 100644
if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
/* Frankein-GIC without banked registers... */
unsigned int cpu;
-@@ -1149,7 +1220,25 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
+@@ -1149,7 +1223,25 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
goto error;
}
@@ -272069,7 +340035,7 @@ index d6c404b..1709f7a 100644
+
+ if(gic_dist_init_flag != GIC_DIST_INIT_FLAG) {
+ printk("Gic dist init...\n");
-+#ifdef CONFIG_ARCH_HI3559AV100
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+ gic_dist_init_amp(gic);
+#else
+ gic_dist_init(gic);
@@ -272083,7 +340049,7 @@ index d6c404b..1709f7a 100644
goto error;
diff --git a/drivers/irqchip/irq-map-hi3559av100.h b/drivers/irqchip/irq-map-hi3559av100.h
new file mode 100644
-index 0000000..6ce2bd6
+index 0000000..8105537
--- /dev/null
+++ b/drivers/irqchip/irq-map-hi3559av100.h
@@ -0,0 +1,115 @@
@@ -272096,14 +340062,14 @@ index 0000000..6ce2bd6
+#define TO_A73MP1 (1<<0x03)
+#define TO_A53UP_ (1<<0x04) //Local
+const unsigned char irq_map[1024] = {
-+ 0, 0, 0, 0,
-+ 0, 0, 0, 0,
-+ 0, 0, 0, 0,
-+ 0, 0, 0, 0,
-+ 0, 0, 0, 0,
-+ 0, 0, 0, 0,
-+ 0, 0, 0, 0,
-+ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
+ /*time 0 timer 2 timer 4 timer 6 */
+ TO_A53MP0, TO_A53MP0, TO_A53MP0, TO_A53UP_, /* 32 ~ 35 */
+ /*time 8 timer 10 uart 0 uart 1 */
@@ -272158,11 +340124,11 @@ index 0000000..6ce2bd6
+ TO_A53MP0, TO_A53MP0, TO_A53MP0, TO_A53MP0, /* 132 ~ */
+ /*RSA WDG CAN 0 CAN 1 */
+ TO_A53MP0, TO_A53MP0 \
-+ | TO_A53MP0 \
-+ | TO_A53MP1 \
-+ | TO_A73MP0 \
-+ | TO_A73MP1 \
-+ , TO_A53MP0, TO_A53MP0, /* 136 ~ */
++ | TO_A53MP0 \
++ | TO_A53MP1 \
++ | TO_A73MP0 \
++ | TO_A73MP1 \
++ , TO_A53MP0, TO_A53MP0, /* 136 ~ */
+ TO_A53MP0, TO_A53MP0, TO_A53MP0, TO_A53MP0, /* 140 ~ */
+ TO_A53MP0, TO_A53MP0, TO_A53MP0, TO_A53MP0, /* 144 ~ */
+ TO_A53MP0, TO_A53MP0, TO_A53MP0, TO_A53MP0, /* 148 ~ */
@@ -272224,6 +340190,18 @@ index b5589d5..11e0e5f 100644
case USB_SPEED_WIRELESS:
psize = usb_endpoint_maxp(&ep->desc);
return psize;
+diff --git a/drivers/media/v4l2-core/videobuf2-v4l2.c b/drivers/media/v4l2-core/videobuf2-v4l2.c
+index 52ef883..7e45da4 100644
+--- a/drivers/media/v4l2-core/videobuf2-v4l2.c
++++ b/drivers/media/v4l2-core/videobuf2-v4l2.c
+@@ -146,7 +146,6 @@ static void vb2_warn_zero_bytesused(struct vb2_buffer *vb)
+ return;
+
+ check_once = true;
+- WARN_ON(1);
+
+ pr_warn("use of bytesused == 0 is deprecated and will be removed in the future,\n");
+ if (vb->vb2_queue->allow_zero_bytesused)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..327bb5b 100644
--- a/drivers/mfd/Kconfig
@@ -272260,7 +340238,7 @@ index 9834e66..9c6d6ea 100644
obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o
diff --git a/drivers/mfd/hisi_fmc.c b/drivers/mfd/hisi_fmc.c
new file mode 100644
-index 0000000..3f2d5a1
+index 0000000..9bbedc2
--- /dev/null
+++ b/drivers/mfd/hisi_fmc.c
@@ -0,0 +1,139 @@
@@ -272299,105 +340277,105 @@ index 0000000..3f2d5a1
+
+/* ------------------------------------------------------------------------ */
+static const struct mfd_cell hisi_fmc_devs[] = {
-+ {
-+ .name = "hisi_spi_nor",
-+ .of_compatible = "hisilicon,fmc-spi-nor",
-+ },
-+ {
-+ .name = "hisi_spi_nand",
-+ .of_compatible = "hisilicon,fmc-spi-nand",
-+ },
-+ {
-+ .name = "hisi_nand",
-+ .of_compatible = "hisilicon,fmc-nand",
-+ },
++ {
++ .name = "hisi_spi_nor",
++ .of_compatible = "hisilicon,fmc-spi-nor",
++ },
++ {
++ .name = "hisi_spi_nand",
++ .of_compatible = "hisilicon,fmc-spi-nand",
++ },
++ {
++ .name = "hisi_nand",
++ .of_compatible = "hisilicon,fmc-nand",
++ },
+};
+
+static int hisi_fmc_probe(struct platform_device *pdev)
+{
-+ struct hisi_fmc *fmc;
-+ struct resource *res;
-+ struct device *dev = &pdev->dev;
-+ int ret;
++ struct hisi_fmc *fmc;
++ struct resource *res;
++ struct device *dev = &pdev->dev;
++ int ret;
+
-+ fmc = devm_kzalloc(dev, sizeof(*fmc), GFP_KERNEL);
-+ if (!fmc) {
-+ return -ENOMEM;
-+ }
++ fmc = devm_kzalloc(dev, sizeof(*fmc), GFP_KERNEL);
++ if (!fmc) {
++ return -ENOMEM;
++ }
+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
-+ fmc->regbase = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(fmc->regbase)) {
-+ return PTR_ERR(fmc->regbase);
-+ }
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
++ fmc->regbase = devm_ioremap_resource(dev, res);
++ if (IS_ERR(fmc->regbase)) {
++ return PTR_ERR(fmc->regbase);
++ }
+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
-+ fmc->iobase = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(fmc->iobase)) {
-+ return PTR_ERR(fmc->iobase);
-+ }
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
++ fmc->iobase = devm_ioremap_resource(dev, res);
++ if (IS_ERR(fmc->iobase)) {
++ return PTR_ERR(fmc->iobase);
++ }
+
-+ fmc->clk = devm_clk_get(dev, NULL);
-+ if (IS_ERR(fmc->clk)) {
-+ return PTR_ERR(fmc->clk);
-+ }
++ fmc->clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(fmc->clk)) {
++ return PTR_ERR(fmc->clk);
++ }
+
-+ if (of_property_read_u32(dev->of_node, "max-dma-size", &fmc->dma_len)) {
-+ dev_err(dev, "Please set the suitable max-dma-size value !!!\n");
-+ return -ENOMEM;
-+ }
++ if (of_property_read_u32(dev->of_node, "max-dma-size", &fmc->dma_len)) {
++ dev_err(dev, "Please set the suitable max-dma-size value !!!\n");
++ return -ENOMEM;
++ }
+
-+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
-+ if (ret) {
-+ dev_warn(dev, "Unable to set dma mask\n");
-+ return ret;
-+ }
++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
++ if (ret) {
++ dev_warn(dev, "Unable to set dma mask\n");
++ return ret;
++ }
+
-+ fmc->buffer = dmam_alloc_coherent(dev, fmc->dma_len,
-+ &fmc->dma_buffer, GFP_KERNEL);
-+ if (IS_ERR(fmc->buffer)) {
-+ return PTR_ERR(fmc->buffer);
-+ }
++ fmc->buffer = dmam_alloc_coherent(dev, fmc->dma_len,
++ &fmc->dma_buffer, GFP_KERNEL);
++ if (IS_ERR(fmc->buffer)) {
++ return PTR_ERR(fmc->buffer);
++ }
+
-+ mutex_init(&fmc->lock);
++ mutex_init(&fmc->lock);
+
-+ platform_set_drvdata(pdev, fmc);
++ platform_set_drvdata(pdev, fmc);
+
-+ ret = mfd_add_devices(dev, 0, hisi_fmc_devs,
-+ ARRAY_SIZE(hisi_fmc_devs), NULL, 0, NULL);
-+ if (ret) {
-+ dev_err(dev, "add mfd devices failed: %d\n", ret);
-+ return ret;
-+ }
++ ret = mfd_add_devices(dev, 0, hisi_fmc_devs,
++ ARRAY_SIZE(hisi_fmc_devs), NULL, 0, NULL);
++ if (ret) {
++ dev_err(dev, "add mfd devices failed: %d\n", ret);
++ return ret;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static int hisi_fmc_remove(struct platform_device *pdev)
+{
-+ struct hisi_fmc *fmc = platform_get_drvdata(pdev);
++ struct hisi_fmc *fmc = platform_get_drvdata(pdev);
+
-+ dmam_free_coherent(&pdev->dev, fmc->dma_len,
-+ fmc->buffer, fmc->dma_buffer);
-+ mfd_remove_devices(&pdev->dev);
-+ mutex_destroy(&fmc->lock);
++ dmam_free_coherent(&pdev->dev, fmc->dma_len,
++ fmc->buffer, fmc->dma_buffer);
++ mfd_remove_devices(&pdev->dev);
++ mutex_destroy(&fmc->lock);
+
-+ return 0;
++ return 0;
+}
+
+static const struct of_device_id hisi_fmc_of_match_tbl[] = {
-+ { .compatible = "hisilicon,hisi-fmc"},
-+ { }
++ { .compatible = "hisilicon,hisi-fmc"},
++ { }
+};
+MODULE_DEVICE_TABLE(of, hisi_fmc_of_match_tbl);
+
+static struct platform_driver hisi_fmc_driver = {
-+ .driver = {
-+ .name = "hifmc",
-+ .of_match_table = hisi_fmc_of_match_tbl,
-+ },
-+ .probe = hisi_fmc_probe,
-+ .remove = hisi_fmc_remove,
++ .driver = {
++ .name = "hifmc",
++ .of_match_table = hisi_fmc_of_match_tbl,
++ },
++ .probe = hisi_fmc_probe,
++ .remove = hisi_fmc_remove,
+};
+module_platform_driver(hisi_fmc_driver);
+
@@ -274716,7 +342694,7 @@ index bd44ba8..e15db58 100644
+#endif
+
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
-index 5274f50..7f86b2c 100644
+index 5274f50..586d188 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -176,6 +176,17 @@ config MMC_SDHCI_CNS3XXX
@@ -274725,7 +342703,7 @@ index 5274f50..7f86b2c 100644
+config MMC_SDHCI_HISI
+ tristate "SDHCI support on the Hisilicon Hi35xx SoC"
-+ depends on ARCH_HI3559AV100 || ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV200
++ depends on ARCH_HI3559AV100 || ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV200 || ARCH_HI3569V100
+ depends on MMC_SDHCI_PLTFM
+ help
+ This selects the SDHCI support for Hi35xx System-on-Chip devices.
@@ -274781,7 +342759,7 @@ index e2bdaaf..e8d1ba1 100644
+obj-$(CONFIG_HIMCI) += himci/
diff --git a/drivers/mmc/host/cmdq_hci.c b/drivers/mmc/host/cmdq_hci.c
new file mode 100644
-index 0000000..f55f40f
+index 0000000..bccd8b2
--- /dev/null
+++ b/drivers/mmc/host/cmdq_hci.c
@@ -0,0 +1,1116 @@
@@ -275123,7 +343101,7 @@ index 0000000..f55f40f
+{
+ int err = 0;
+ u32 cqcfg;
-+ bool dcmd_enable;
++ bool dcmd_enable = false;
+ struct cmdq_host *cq_host = mmc_cmdq_private(mmc);
+
+ if (!cq_host || !mmc->card || !mmc_card_cmdq(mmc->card)) {
@@ -275362,8 +343340,8 @@ index 0000000..f55f40f
+ int i, sg_count, len;
+ bool end = false;
+ dma_addr_t addr;
-+ u8 *desc;
-+ struct scatterlist *sg;
++ u8 *desc = NULL;
++ struct scatterlist *sg = NULL;
+
+ sg_count = cmdq_dma_map(mrq->host, mrq);
+ if (sg_count < 0) {
@@ -275430,7 +343408,7 @@ index 0000000..f55f40f
+ u64 data = 0;
+ u8 resp_type;
+ u8 *desc;
-+ __le64 *dataddr;
++ __le64 *dataddr == NULL;
+ struct cmdq_host *cq_host = mmc_cmdq_private(mmc);
+ u8 timing;
+
@@ -275555,7 +343533,7 @@ index 0000000..f55f40f
+ unsigned long tag = 0, comp_status;
+ struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc);
+ unsigned long err_info = 0;
-+ struct mmc_request *mrq;
++ struct mmc_request *mrq = NULL;
+ int ret;
+ u32 dbr_set = 0;
+
@@ -275802,9 +343780,9 @@ index 0000000..f55f40f
+
+static void cmdq_post_req(struct mmc_host *mmc, int tag, int err)
+{
-+ struct cmdq_host *cq_host;
-+ struct mmc_request *mrq;
-+ struct mmc_data *data;
++ struct cmdq_host *cq_host = NULL;
++ struct mmc_request *mrq = NULL;
++ struct mmc_data *data = NULL;
+
+ if (WARN_ON(!mmc))
+ return;
@@ -275846,7 +343824,7 @@ index 0000000..f55f40f
+
+struct cmdq_host *cmdq_pltfm_init(struct platform_device *pdev)
+{
-+ struct cmdq_host *cq_host;
++ struct cmdq_host *cq_host = NULL;
+ struct resource *cmdq_memres = NULL;
+
+ /* check and setup CMDQ interface */
@@ -276147,7 +344125,7 @@ index 0000000..393fee6
+#endif
diff --git a/drivers/mmc/host/himci/Kconfig b/drivers/mmc/host/himci/Kconfig
new file mode 100644
-index 0000000..1188879
+index 0000000..f3331c8
--- /dev/null
+++ b/drivers/mmc/host/himci/Kconfig
@@ -0,0 +1,23 @@
@@ -276156,7 +344134,7 @@ index 0000000..1188879
+#
+menuconfig HIMCI
+ tristate "himci driver support"
-+ depends on ARCH_HI3516A || ARCH_HI3518EV20X || ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200
++ depends on ARCH_HI3516A || ARCH_HI3518EV20X || ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200 || ARCH_HI3562V100 || ARCH_HI3566V100
+ default y if ARCH_HI3516A
+ select MMC_UNSAFE_RESUME
+ select MMC_EMBEDDED_SDIO
@@ -276184,10 +344162,10 @@ index 0000000..6858bfc
+hisi_mci-y := himci.o himci_proc.o
diff --git a/drivers/mmc/host/himci/himci.c b/drivers/mmc/host/himci/himci.c
new file mode 100644
-index 0000000..db6811d
+index 0000000..509ad28
--- /dev/null
+++ b/drivers/mmc/host/himci/himci.c
-@@ -0,0 +1,2468 @@
+@@ -0,0 +1,2488 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -276270,6 +344248,14 @@ index 0000000..db6811d
+#include "himci_hi3559v200.c"
+#endif
+
++#ifdef CONFIG_ARCH_HI3562V100
++#include "himci_hi3559v200.c"
++#endif
++
++#ifdef CONFIG_ARCH_HI3566V100
++#include "himci_hi3559v200.c"
++#endif
++
+#define DRIVER_NAME "himci"
+
+#ifndef CONFIG_HISI_MC
@@ -276278,8 +344264,9 @@ index 0000000..db6811d
+#define CMD_DES_PAGE_SIZE (8 * PAGE_SIZE)
+#endif
+
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) ||\
-+ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+void __iomem *crg_ctrl,*misc_ctrl_1;
+#endif
+
@@ -276466,7 +344453,9 @@ index 0000000..db6811d
+ reg &= ~(CCLK_ENABLE << host->port);
+ reg &= ~(CCLK_LOW_POWER << host->port);
+ }
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+ if (host->devid == 2)
+ reg &= ~(CCLK_LOW_POWER << host->port);
+#endif
@@ -276482,7 +344471,9 @@ index 0000000..db6811d
+ cmd_reg.bits.send_auto_stop = 0;
+ cmd_reg.bits.wait_prvdata_complete = 0;
+ cmd_reg.bits.check_response_crc = 0;
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+ cmd_reg.bits.use_hold_reg = 1;
+#endif
+ himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);
@@ -276550,8 +344541,9 @@ index 0000000..db6811d
+
+ himci_sys_reset(host);
+
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) ||\
-+ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+ /* controller config gpio */
+ tmp_reg = himci_readl(host->base + MCI_GPIO);
+ tmp_reg |= DTO_FIX_BYPASS;
@@ -276602,7 +344594,7 @@ index 0000000..db6811d
+ host->data_error_count = 0;
+}
+
-+static void himci_detect_card(unsigned long arg)
++static void himci_detect_card(uintptr_t arg)
+{
+ struct himci_host *host = (struct himci_host *)arg;
+ unsigned int i, curr_status, status[5], detect_retry_count = 0;
@@ -276687,7 +344679,7 @@ index 0000000..db6811d
+ unsigned int i, ret = 0;
+ unsigned int data_size;
+ unsigned int max_des, des_cnt;
-+ struct himci_des *des;
++ struct himci_des *des = NULL;
+
+ himci_trace(2, "begin");
+ himci_assert(host);
@@ -276713,9 +344705,9 @@ index 0000000..db6811d
+ goto out;
+ }
+
-+ himci_trace(2, "host->dma_paddr is 0x%08X,host->dma_vaddr is 0x%08X\n",
-+ (unsigned int)host->dma_paddr,
-+ (unsigned int)host->dma_vaddr);
++ himci_trace(2, "host->dma_paddr is 0x%08lx,host->dma_vaddr is 0x%08lx\n",
++ (uintptr_t)host->dma_paddr,
++ (uintptr_t)host->dma_vaddr);
+
+ max_des = (CMD_DES_PAGE_SIZE/sizeof(struct himci_des));
+ des = (struct himci_des *)host->dma_vaddr;
@@ -276748,7 +344740,7 @@ index 0000000..db6811d
+ }
+
+ himci_trace(2, "des[%d] vaddr is 0x%08X", i,
-+ (unsigned int)&des[i]);
++ (unsigned int)(uintptr_t)&des[i]);
+ himci_trace(2, "des[%d].idmac_des_ctrl is 0x%08X",
+ i, (unsigned int)des[i].idmac_des_ctrl);
+ himci_trace(2, "des[%d].idmac_des_buf_size is 0x%08X",
@@ -276805,9 +344797,12 @@ index 0000000..db6811d
+#endif
+
+ if (cmd == host->mrq->stop ||
-+ cmd->opcode == MMC_STOP_TRANSMISSION) {
++ cmd->opcode == MMC_STOP_TRANSMISSION) {
+ cmd_regs.bits.stop_abort_cmd = 1;
+ cmd_regs.bits.wait_prvdata_complete = 0;
++ } else if (cmd->opcode == MMC_SEND_STATUS) {
++ cmd_regs.bits.stop_abort_cmd = 0;
++ cmd_regs.bits.wait_prvdata_complete = 0;
+ } else {
+ cmd_regs.bits.stop_abort_cmd = 0;
+ cmd_regs.bits.wait_prvdata_complete = 1;
@@ -276926,7 +344921,7 @@ index 0000000..db6811d
+ stat);
+ }
+
-+
++
+ if (((cmd->flags & MMC_RSP_R1) == MMC_RSP_R1) &&
+ ((cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)) {
+ if ((cmd->resp[0] & CMD_ERRORS)&& !host->is_tuning) {
@@ -277253,13 +345248,13 @@ index 0000000..db6811d
+ } else if (host->is_tuning){
+ unsigned int stat;
+ unsigned int wait_retry_count = 0;
-+
++
+ do {
+ stat = himci_readl(host->base + MCI_RINTSTS);
+ if (stat & (HTO_INT_STATUS | DRTO_INT_STATUS |
+ EBE_INT_STATUS | SBE_INT_STATUS |
+ FRUN_INT_STATUS | DCRC_INT_STATUS)){
-+ himci_writel(stat, host->base + MCI_RINTSTS);
++ himci_writel(stat, host->base + MCI_RINTSTS);
+ himci_trace(3, "data status = 0x%x is error!", stat);
+ himci_trace(3, "udelay count = %d is error!", wait_retry_count);
+ break;
@@ -277267,7 +345262,7 @@ index 0000000..db6811d
+ udelay(100);
+ wait_retry_count++;
+ } while (wait_retry_count < 1000);
-+
++
+ /* CMD error in data command */
+ himci_idma_stop(host);
+
@@ -277458,8 +345453,9 @@ index 0000000..db6811d
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
-+#if defined(CONFIG_ARCH_HI3516DV300) || defined(CONFIG_ARCH_HI3516CV500) ||\
-+ defined(CONFIG_ARCH_HI3559V200) || defined(CONFIG_ARCH_HI3556V200)
++#if defined(CONFIG_ARCH_HI3516DV300) || defined(CONFIG_ARCH_HI3516CV500) || \
++ defined(CONFIG_ARCH_HI3559V200) || defined(CONFIG_ARCH_HI3556V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+static void himci_edge_tuning_enable(struct himci_host *host)
+{
+ unsigned int val;
@@ -277511,7 +345507,7 @@ index 0000000..db6811d
+{
+ int err;
+ struct mmc_command cmd = {0};
-+ struct himci_host *host;
++ struct himci_host *host = NULL;
+
+ BUG_ON(!mmc);
+
@@ -277532,7 +345528,10 @@ index 0000000..db6811d
+{
+ int err = 0;
+ struct himci_host *host;
-+ unsigned cmd_count = 100;
++ /* fix a problem that When the I/O voltage is increased to 1.89 V or 1.91V
++ * at high and low temperatures, the system is suspended during the reboot test.
++ */
++ unsigned cmd_count = 1000;
+
+ host = mmc_priv(mmc);
+ himci_control_cclk(host, DISABLE);
@@ -278308,7 +346307,7 @@ index 0000000..db6811d
+
+static int himci_probe(struct platform_device *pdev)
+{
-+ struct mmc_host *mmc;
++ struct mmc_host *mmc = NULL;
+ struct himci_host *host = NULL;
+ struct resource *host_ioaddr_res = NULL;
+ int ret = 0, irq;
@@ -278330,8 +346329,9 @@ index 0000000..db6811d
+
+ mmc->ops = &himci_ops;
+
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) ||\
-+ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+
+ crg_ctrl = ioremap(0x12010000, 0x1000);
+ if (!crg_ctrl){
@@ -278367,11 +346367,11 @@ index 0000000..db6811d
+ }
+
+ /* reload by this controller */
-+#ifndef CONFIG_HISI_MC
++#ifndef CONFIG_HISI_MC
+ mmc->max_blk_count = 2048;
+#else
+ mmc->max_blk_count = 4096;
-+#endif
++#endif
+ mmc->max_segs = 1024;
+ mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
+ mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
@@ -278435,7 +346435,7 @@ index 0000000..db6811d
+
+ init_timer(&host->timer);
+ host->timer.function = himci_detect_card;
-+ host->timer.data = (unsigned long)host;
++ host->timer.data = (uintptr_t)host;
+ host->timer.expires = jiffies + detect_time;
+ add_timer(&host->timer);
+
@@ -278468,8 +346468,9 @@ index 0000000..db6811d
+ }
+ if (mmc)
+ mmc_free_host(mmc);
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) ||\
-+ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+ if (crg_ctrl)
+ iounmap(crg_ctrl);
+#endif
@@ -278498,9 +346499,6 @@ index 0000000..db6811d
+ host->dma_paddr);
+ mmc_free_host(mmc);
+ }
-+
-+ if (crg_ctrl)
-+ iounmap(crg_ctrl);
+ return 0;
+}
+
@@ -278528,7 +346526,7 @@ index 0000000..db6811d
+ pm_message_t state)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
-+ struct himci_host *host;
++ struct himci_host *host = NULL;
+ int ret = 0;
+
+ if (mmc) {
@@ -278545,7 +346543,7 @@ index 0000000..db6811d
+static int himci_pltm_resume(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
-+ struct himci_host *host;
++ struct himci_host *host = NULL;
+ int ret = 0;
+
+ if (mmc) {
@@ -278569,7 +346567,7 @@ index 0000000..db6811d
+
+void hisi_sdio_rescan(int slot)
+{
-+ struct mmc_host *mmc;
++ struct mmc_host *mmc = NULL;
+ struct himci_host *host;
+
+ host = mci_host[slot];
@@ -278658,7 +346656,7 @@ index 0000000..db6811d
+#endif
diff --git a/drivers/mmc/host/himci/himci.h b/drivers/mmc/host/himci/himci.h
new file mode 100644
-index 0000000..c94fd54
+index 0000000..d3561fa
--- /dev/null
+++ b/drivers/mmc/host/himci/himci.h
@@ -0,0 +1,157 @@
@@ -278692,7 +346690,7 @@ index 0000000..c94fd54
+
+#define HI_MCI_DETECT_TIMEOUT (HZ/2)
+
-+#define HI_MCI_REQUEST_TIMEOUT (5 * HZ)
++#define HI_MCI_REQUEST_TIMEOUT (30 * HZ)
+
+#define MAX_RETRY_COUNT 100
+
@@ -278724,13 +346722,13 @@ index 0000000..c94fd54
+ printk("\n"); \
+} while (0)
+
-+#define himci_readl(addr) ({unsigned int reg = readl(IOMEM(addr)); \
-+ himci_trace(1, "readl(0x%04X) = 0x%08X", (unsigned int)addr, reg); \
++#define himci_readl(addr) ({unsigned int reg = readl(IOMEM((uintptr_t)addr)); \
++ himci_trace(1, "readl(0x%04X) = 0x%08X", (unsigned int)(uintptr_t)addr, reg); \
+ reg; })
+
-+#define himci_writel(v, addr) do { writel(v, IOMEM(addr)); \
-+ himci_trace(1, "writel(0x%04X) = 0x%08X", (unsigned int)addr, \
-+ (unsigned int)(v)); \
++#define himci_writel(v, addr) do { writel(v, IOMEM((uintptr_t)addr)); \
++ himci_trace(1, "writel(0x%04X) = 0x%08X", (unsigned int)(uintptr_t)addr, \
++ (unsigned int)(uintptr_t)(v)); \
+} while (0)
+
+struct himci_des {
@@ -278745,7 +346743,7 @@ index 0000000..c94fd54
+ unsigned char timing;
+ unsigned char card_connect;
+#define CARD_CONNECT 1
-+#define CARD_DISCONNECT 0
++#define CARD_DISCONNECT 0
+ unsigned int card_support_clock; /* clock rate */
+ unsigned int card_state; /* (our) card state */
+ unsigned int sd_bus_speed;
@@ -278921,7 +346919,7 @@ index 0000000..bf561f8
+}
diff --git a/drivers/mmc/host/himci/himci_hi3516cv500.c b/drivers/mmc/host/himci/himci_hi3516cv500.c
new file mode 100644
-index 0000000..3b45977
+index 0000000..20fe899
--- /dev/null
+++ b/drivers/mmc/host/himci/himci_hi3516cv500.c
@@ -0,0 +1,163 @@
@@ -279028,7 +347026,7 @@ index 0000000..3b45977
+ pin_drv_cap = sdio1_ds_drv;
+ }
+
-+ start = (unsigned int)(long)ioremap((resource_size_t)pad_ctrl_start[devid], (size_t)0x1000);
++ start = (unsigned int)(uintptr_t)ioremap((resource_size_t)pad_ctrl_start[devid], (size_t)0x1000);
+
+ for (i = start, j = 0; j < 6; i = i+4, j++) {
+ unsigned int reg = himci_readl(i);
@@ -279040,9 +347038,9 @@ index 0000000..3b45977
+ * */
+ reg = reg & (~(0x7f0));
+ reg |= pin_drv_cap[j];
-+ himci_writel(reg, i);
++ himci_writel(reg, (uintptr_t)i);
+ }
-+ iounmap((void *)(long)start);
++ iounmap((void *)(uintptr_t)start);
+}
+
+#define DRV_PHASE_180 (0x4<<23)
@@ -279081,11 +347079,11 @@ index 0000000..3b45977
+ phase_cfg = DRV_PHASE_180 | SMP_PHASE_0;
+ }
+
-+ reg_value = himci_readl(host->base + MCI_UHS_REG_EXT);
++ reg_value = himci_readl((uintptr_t)(host->base) + MCI_UHS_REG_EXT);
+ reg_value &= ~CLK_SMPL_PHS_MASK;
+ reg_value &= ~CLK_DRV_PHS_MASK;
+ reg_value |= phase_cfg;
-+ himci_writel(reg_value, host->base + MCI_UHS_REG_EXT);
++ himci_writel(reg_value, (uintptr_t)(host->base) + MCI_UHS_REG_EXT);
+}
+
diff --git a/drivers/mmc/host/himci/himci_hi3516dv300.c b/drivers/mmc/host/himci/himci_hi3516dv300.c
@@ -279755,7 +347753,7 @@ index 0000000..3b45977
+
diff --git a/drivers/mmc/host/himci/himci_proc.c b/drivers/mmc/host/himci/himci_proc.c
new file mode 100644
-index 0000000..cd936ae
+index 0000000..f24dbc5
--- /dev/null
+++ b/drivers/mmc/host/himci/himci_proc.c
@@ -0,0 +1,302 @@
@@ -279870,8 +347868,8 @@ index 0000000..cd936ae
+ unsigned int clock_value = 0;
+ const char *type = NULL;
+ unsigned int present;
-+ struct himci_host *host;
-+ struct card_info * c_info;
++ struct himci_host *host = NULL;
++ struct card_info * c_info = NULL;
+ const char *uhs_bus_speed_mode = "";
+ u32 speed_class, grade_speed_uhs;
+ static const char *const uhs_speeds[] = {
@@ -279892,7 +347890,7 @@ index 0000000..cd936ae
+ seq_printf(s, "MCI%d", index_mci);
+ }
+ c_info = &host->c_info;
-+
++
+ present = host->mmc->ops->get_cd(host->mmc);
+ if (present) {
+ seq_puts(s, ": pluged");
@@ -280031,7 +348029,7 @@ index 0000000..cd936ae
+
+int mci_proc_init(void)
+{
-+ struct proc_dir_entry *proc_stats_entry;
++ struct proc_dir_entry *proc_stats_entry = NULL;
+
+ proc_mci_dir = proc_mkdir(MCI_PARENT, NULL);
+ if (!proc_mci_dir) {
@@ -280104,10 +348102,10 @@ index 0000000..8840cc6
+#endif /* __MCI_PROC_H__ */
diff --git a/drivers/mmc/host/himci/himci_reg.h b/drivers/mmc/host/himci/himci_reg.h
new file mode 100644
-index 0000000..f9abd63
+index 0000000..4d31f34
--- /dev/null
+++ b/drivers/mmc/host/himci/himci_reg.h
-@@ -0,0 +1,243 @@
+@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -280338,7 +348336,9 @@ index 0000000..f9abd63
+
+
+/* MCI_CARDTHRCTL(0x100) details */
-+#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
+#define RW_THRESHOLD_SIZE (0x2000005)
+#else
+#define RW_THRESHOLD_SIZE (0x2000001)
@@ -280353,10 +348353,10 @@ index 0000000..f9abd63
+#endif
diff --git a/drivers/mmc/host/mci_proc.c b/drivers/mmc/host/mci_proc.c
new file mode 100644
-index 0000000..10f763b
+index 0000000..4ee14a1
--- /dev/null
+++ b/drivers/mmc/host/mci_proc.c
-@@ -0,0 +1,301 @@
+@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -280386,22 +348386,9 @@ index 0000000..10f763b
+
+#define MCI_PARENT "mci"
+#define MCI_STATS_PROC "mci_info"
-+#define MAX_CLOCK_SCALE (4)
-+#define UNSTUFF_BITS(resp,start,size) \
-+ ({ \
-+ const int __size = size; \
-+ const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
-+ const int __off = 3 - ((start) / 32); \
-+ const int __shft = (start) & 31; \
-+ u32 __res; \
-+ \
-+ __res = resp[__off] >> __shft; \
-+ if (__size + __shft > 32) \
-+ __res |= resp[__off-1] << ((32 - __shft) % 32); \
-+ __res & __mask; \
-+ })
++#define MAX_CLOCK_SCALE 4
+
-+unsigned int slot_index = 0;
++unsigned int slot_index;
+struct mmc_host *mci_host[MCI_SLOT_NUM] = {NULL};
+static struct proc_dir_entry *proc_mci_dir;
+
@@ -280421,21 +348408,20 @@ index 0000000..10f763b
+
+static char *mci_get_card_type(unsigned int sd_type)
+{
-+ if (MAX_CARD_TYPE <= sd_type)
++ if (sd_type >= MAX_CARD_TYPE)
+ return card_type[MAX_CARD_TYPE];
+ else
+ return card_type[sd_type];
+}
+
-+static unsigned int analyze_clock_scale(unsigned int clock,
-+ unsigned int *clock_val)
++static unsigned int analyze_clock_scale(unsigned int clock, unsigned int *clock_val)
+{
+ unsigned int scale = 0;
+ unsigned int tmp = clock;
+
+ while (1) {
-+ tmp = tmp / 1000;
-+ if (0 < tmp) {
++ tmp = tmp / 1000; /* 1000 for clk calculate */
++ if (tmp > 0) {
+ *clock_val = tmp;
+ scale++;
+ } else {
@@ -280462,10 +348448,10 @@ index 0000000..10f763b
+ unsigned int clock;
+ unsigned int clock_scale;
+ unsigned int clock_value = 0;
-+ const char *type;
-+ static struct mmc_host *mmc;
++ const char *type = NULL;
++ static struct mmc_host *mmc = NULL;
+ const char *uhs_bus_speed_mode = "";
-+ static const char *const uhs_speeds[] = {
++ static const char *uhs_speeds[] = {
+ [UHS_SDR12_BUS_SPEED] = "SDR12 ",
+ [UHS_SDR25_BUS_SPEED] = "SDR25 ",
+ [UHS_SDR50_BUS_SPEED] = "SDR50 ",
@@ -280473,13 +348459,13 @@ index 0000000..10f763b
+ [UHS_DDR50_BUS_SPEED] = "DDR50 ",
+ };
+ unsigned int speed_class, grade_speed_uhs;
-+ struct card_info *info;
++ struct card_info *info = NULL;
+ unsigned int present;
-+ struct sdhci_host *host;
++ struct sdhci_host *host = NULL;
+
+ for (index_mci = 0; index_mci < MCI_SLOT_NUM; index_mci++) {
+ mmc = mci_host[index_mci];
-+ if (NULL == mmc) {
++ if (mmc == NULL) {
+ seq_printf(s, "MCI%d: invalid\n", index_mci);
+ continue;
+ } else {
@@ -280489,24 +348475,18 @@ index 0000000..10f763b
+ info = &host->c_info;
+
+ present = host->mmc->ops->get_cd(host->mmc);
-+ if (present) {
++ if (present)
+ seq_puts(s, ": pluged");
-+ } else {
++ else
+ seq_puts(s, ": unplugged");
-+ }
+
-+ /*card = mmc->card;
-+ if (NULL == card) {*/
-+ if (CARD_CONNECT != info->card_connect) {
++ if (info->card_connect != CARD_CONNECT) {
+ seq_puts(s, "_disconnected\n");
+ } else {
-+
+ seq_puts(s, "_connected\n");
+
-+ seq_printf(s,
-+ "\tType: %s",
-+ mci_get_card_type(info->card_type)
-+ );
++ seq_printf(s, "\tType: %s",
++ mci_get_card_type(info->card_type));
+
+ if (info->card_state & MMC_STATE_BLOCKADDR) {
+ if (info->card_state & MMC_CARD_SDXC)
@@ -280518,7 +348498,8 @@ index 0000000..10f763b
+
+ if (is_card_uhs(info->timing) &&
+ info->sd_bus_speed < ARRAY_SIZE(uhs_speeds))
-+ uhs_bus_speed_mode = uhs_speeds[info->sd_bus_speed];
++ uhs_bus_speed_mode =
++ uhs_speeds[info->sd_bus_speed];
+
+ seq_printf(s, "\tMode: %s%s%s%s\n",
+ is_card_uhs(info->timing) ? "UHS " :
@@ -280528,20 +348509,20 @@ index 0000000..10f763b
+ info->timing == MMC_TIMING_MMC_DDR52 ? "DDR " : "",
+ uhs_bus_speed_mode);
+
-+ speed_class = UNSTUFF_BITS(info->ssr, 440 - 384, 8);
-+ grade_speed_uhs = UNSTUFF_BITS(info->ssr, 396 - 384, 4);
++ speed_class = UNSTUFF_BITS(info->ssr, 56, 8); /* 56 equal 440 -384 */
++ grade_speed_uhs = UNSTUFF_BITS(info->ssr, 12, 4); /* 12 equal 396 - 384 */
+ seq_printf(s, "\tSpeed Class: Class %s\n",
-+ (0x00 == speed_class) ? "0":
-+ (0x01 == speed_class) ? "2":
-+ (0x02 == speed_class) ? "4":
-+ (0x03 == speed_class) ? "6":
-+ (0x04 == speed_class) ? "10":
++ (speed_class == 0x00) ? "0" :
++ (speed_class == 0x01) ? "2" :
++ (speed_class == 0x02) ? "4" :
++ (speed_class == 0x03) ? "6" :
++ (speed_class == 0x04) ? "10" :
+ "Reserved");
+ seq_printf(s, "\tUhs Speed Grade: %s\n",
-+ (0x00 == grade_speed_uhs)?
++ (grade_speed_uhs == 0x00) ?
+ "Less than 10MB/sec(0h)" :
-+ (0x01 == grade_speed_uhs)?
-+ "10MB/sec and above(1h)":
++ (grade_speed_uhs == 0x01) ?
++ "10MB/sec and above(1h)" :
+ "Reserved");
+
+ clock = info->card_support_clock;
@@ -280553,7 +348534,7 @@ index 0000000..10f763b
+ clock_scale = analyze_clock_scale(clock, &clock_value);
+ seq_printf(s, "\tCard support clock: %d%s\n",
+ clock_value, clock_unit[clock_scale]);
-+
++
+ clock = mmc->actual_clock;
+ clock_scale = analyze_clock_scale(clock, &clock_value);
+ seq_printf(s, "\tCard work clock: %d%s\n",
@@ -280561,7 +348542,7 @@ index 0000000..10f763b
+
+ /* add card read/write error count */
+ seq_printf(s, "\tCard error count: %d\n",
-+ host->error_count);
++ host->error_count);
+ }
+ }
+}
@@ -280612,7 +348593,7 @@ index 0000000..10f763b
+ .show = mci_stats_seq_show
+};
+
-+/* proc file open*/
++/* proc file open */
+static int mci_stats_proc_open(struct inode *inode, struct file *file)
+{
+ return seq_open(file, &mci_stats_seq_ops);
@@ -280628,7 +348609,7 @@ index 0000000..10f763b
+
+int mci_proc_init(void)
+{
-+ struct proc_dir_entry *proc_stats_entry;
++ struct proc_dir_entry *proc_stats_entry = NULL;
+
+ proc_mci_dir = proc_mkdir(MCI_PARENT, NULL);
+ if (!proc_mci_dir) {
@@ -280660,10 +348641,10 @@ index 0000000..10f763b
+}
diff --git a/drivers/mmc/host/mci_proc.h b/drivers/mmc/host/mci_proc.h
new file mode 100644
-index 0000000..b5983f6
+index 0000000..fc5f9d7
--- /dev/null
+++ b/drivers/mmc/host/mci_proc.h
-@@ -0,0 +1,43 @@
+@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -280692,11 +348673,13 @@ index 0000000..b5983f6
+#define MAX_CARD_TYPE 4
+#define MAX_SPEED_MODE 5
+
-+#ifdef CONFIG_ARCH_HI3559AV100
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+ #define MCI_SLOT_NUM 4
+#endif
+
-+#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100) || defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
++#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100) ||\
++ defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) ||\
++ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
+ #define MCI_SLOT_NUM 3
+#endif
+
@@ -280709,63 +348692,64 @@ index 0000000..b5983f6
+#endif /* __MCI_PROC_H__ */
diff --git a/drivers/mmc/host/sdhci-hi3516dv200.c b/drivers/mmc/host/sdhci-hi3516dv200.c
new file mode 100644
-index 0000000..354975a
+index 0000000..288c199
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hi3516dv200.c
-@@ -0,0 +1,482 @@
+@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
+ */
+
-+#define REG_EMMC_DRV_DLL_CTRL 0x1fc /*emmc&sd share emmc0 controller*/
++#define REG_EMMC_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO1_DRV_DLL_CTRL 0x220
-+#define REG_SDIO2_DRV_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_CTRL /* no sdio2 */
+#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
-+#define SDIO_DRV_SEL(phase) ((phase) << 24)
++#define sdio_drv_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DRV_DLL_STATUS 0x210
+#define REG_SDIO0_DRV_DLL_STATUS 0x210
+#define REG_SDIO1_DRV_DLL_STATUS 0x228
-+#define REG_SDIO2_DRV_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_STATUS /* no sdio2 */
+#define SDIO_DRV_DLL_LOCK BIT(15)
+#define SDIO_DRV_DLL_READY BIT(14)
+
+#define REG_EMMC_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
-+#define REG_SDIO2_SAMPL_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_STATUS /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
+
+#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
-+#define REG_SDIO2_SAMPL_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
+
+#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
-+#define REG_SDIO2_SAMPLB_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPLB_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
-+#define SDIO_SAMPLB_SEL(phase) ((phase) << 0)
++#define sdio_samplb_sel(phase) ((phase) << 0)
+
+#define REG_EMMC_DS_DLL_CTRL 0x200
+#define EMMC_DS_DLL_MODE_SSEL BIT(13)
-+#define EMMC_DS_DLL_SSEL_MASK (0x7f)
++#define EMMC_DS_DLL_SSEL_MASK 0x7f
+
+#define REG_EMMC_DS180_DLL_CTRL 0x204
+#define EMMC_DS180_DLL_BYPASS BIT(15)
@@ -280778,17 +348762,17 @@ index 0000000..354975a
+#define REG_EMMC_CLK_CTRL 0x1f4
+#define REG_SDIO0_CLK_CTRL 0x1f4
+#define REG_SDIO1_CLK_CTRL 0x22c
-+#define REG_SDIO2_CLK_CTRL /*no sdio2*/
++#define REG_SDIO2_CLK_CTRL /* no sdio2 */
+#define SDIO_CLK_DRV_DLL_RST BIT(29)
+#define SDIO_CLK_CRG_RST BIT(27)
+
+#define IO_CFG_SR BIT(10)
-+#define IO_CFG_PULL_DOWN BIT(9)
++#define IO_CFG_PULL_DOWN BIT(9)
+#define IO_CFG_PULL_UP BIT(8)
+#define IO_CFG_DRV_STR_MASK (0xf << 4)
-+#define IO_CFG_DRV_STR_SEL(str) ((str) << 4)
++#define io_cfg_drv_str_sel(str) ((str) << 4)
+#define IO_CFG_PIN_MUX_MASK (0xf << 0)
-+#define IO_CFG_PIN_MUX_SEL(type) ((type) << 0)
++#define io_cfg_pin_mux_sel(type) ((type) << 0)
+#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
+#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
+
@@ -280805,10 +348789,12 @@ index 0000000..354975a
+#define REG_CTRL_EMMC_DATA7 0x003c
+#define REG_CTRL_EMMC_DS 0x0058
+#define REG_CTRL_EMMC_RST 0x005c
-+static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
-+ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3,
-+ REG_CTRL_EMMC_DATA4, REG_CTRL_EMMC_DATA5,
-+ REG_CTRL_EMMC_DATA6, REG_CTRL_EMMC_DATA7};
++static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {
++ REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
++ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3,
++ REG_CTRL_EMMC_DATA4, REG_CTRL_EMMC_DATA5,
++ REG_CTRL_EMMC_DATA6, REG_CTRL_EMMC_DATA7
++};
+
+#define IO_CFG_SDIO0_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO0_CLK 0x0040
@@ -280817,8 +348803,10 @@ index 0000000..354975a
+#define REG_CTRL_SDIO0_DATA1 0x004C
+#define REG_CTRL_SDIO0_DATA2 0x0050
+#define REG_CTRL_SDIO0_DATA3 0x0054
-+static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
-+ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3};
++static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
++ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3
++};
+
+#define IO_CFG_SDIO1_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO1_CLK 0x0060
@@ -280827,8 +348815,10 @@ index 0000000..354975a
+#define REG_CTRL_SDIO1_DATA1 0x006C
+#define REG_CTRL_SDIO1_DATA2 0x0070
+#define REG_CTRL_SDIO1_DATA3 0x0074
-+static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
-+ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3};
++static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
++ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3
++};
+
+struct sdhci_hisi_priv {
+ struct reset_control *crg_rst;
@@ -280843,8 +348833,7 @@ index 0000000..354975a
+ unsigned int tuning_phase;
+};
+
-+static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc,
-+ struct mmc_ios *ios)
++static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ u32 ctrl;
+ struct sdhci_host *host = mmc_priv(mmc);
@@ -280866,39 +348855,36 @@ index 0000000..354975a
+ sdhci_writel(host, ctrl, SDHCI_MULTI_CYCLE);
+}
+
-+static int sdhci_hisi_pltfm_init(struct platform_device *pdev,
-+ struct sdhci_host *host)
++static int sdhci_hisi_pltfm_init(struct platform_device *pdev, struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_hisi_priv *hisi_priv = sdhci_pltfm_priv(pltfm_host);
+ struct device_node *np = pdev->dev.of_node;
-+ struct clk *clk;
++ struct clk *clk = NULL;
+ int ret;
+
+ hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
+ dev_err(&pdev->dev, "get crg_rst failed.\n");
-+ return PTR_ERR(hisi_priv->crg_rst);;
++ return PTR_ERR(hisi_priv->crg_rst);
+ }
+
+ hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
+ dev_err(&pdev->dev, "get dll_rst failed.\n");
-+ return PTR_ERR(hisi_priv->dll_rst);;
++ return PTR_ERR(hisi_priv->dll_rst);
+ }
+
+ hisi_priv->sampl_rst = NULL;
+
+ hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
-+ if (IS_ERR(hisi_priv->crg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->crg_regmap)) {
+ dev_err(&pdev->dev, "get crg regmap failed.\n");
+ return PTR_ERR(hisi_priv->crg_regmap);
+ }
+
+ hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
-+ if (IS_ERR(hisi_priv->iocfg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->iocfg_regmap)) {
+ dev_err(&pdev->dev, "get iocfg regmap failed.\n");
+ return PTR_ERR(hisi_priv->iocfg_regmap);
+ }
@@ -280919,19 +348905,23 @@ index 0000000..354975a
+ if (ret)
+ return ret;
+
-+ /* only eMMC has a hw reset, and now eMMC signaling
-+ * is fixed to 180*/
++ /*
++ * Only eMMC has a hw reset, and now eMMC signaling
++ * is fixed to 180
++ */
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ host->flags &= ~SDHCI_SIGNALING_330;
+ host->flags |= SDHCI_SIGNALING_180;
+ }
+
-+ /* we parse the support timings from dts, so we read the
++ /*
++ * We parse the support timings from dts, so we read the
+ * host capabilities early and clear the timing capabilities,
+ * SDHCI_QUIRK_MISSING_CAPS is set so that sdhci driver would
-+ * not read it again */
++ * not read it again
++ */
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-+ host->caps &= ~(SDHCI_CAN_DO_HISPD);
++ host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
+ SDHCI_SUPPORT_DDR50 | SDHCI_CAN_DO_ADMA3);
@@ -280939,7 +348929,8 @@ index 0000000..354975a
+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_SINGLE_POWER_WRITE;
+
-+ host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_hs400_enhanced_strobe;
++ host->mmc_host_ops.hs400_enhanced_strobe =
++ sdhci_hisi_hs400_enhanced_strobe;
+
+ mci_host[slot_index++] = host->mmc;
+
@@ -280948,18 +348939,19 @@ index 0000000..354975a
+
+static void hisi_wait_ds_dll_lock(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_wait_ds_180_dll_ready(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ unsigned int reg, timeout = 20;
++ unsigned int reg;
++ unsigned int timeout = 20;
+
+ do {
+ reg = 0;
-+ regmap_read(hisi_priv->crg_regmap, REG_EMMC_DS180_DLL_STATUS, ®);
++ regmap_read(hisi_priv->crg_regmap,
++ REG_EMMC_DS180_DLL_STATUS, ®);
+ if (reg & EMMC_DS180_DLL_READY)
+ return;
+
@@ -280972,8 +348964,7 @@ index 0000000..354975a
+
+static void hisi_set_ds_dll_delay(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_host_extra_init(struct sdhci_host *host)
@@ -280988,8 +348979,8 @@ index 0000000..354975a
+ mbiiu_ctrl = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
+ mbiiu_ctrl &= ~(SDHCI_GM_WR_OSRC_LMT_MASK | SDHCI_GM_RD_OSRC_LMT_MASK |
+ SDHCI_UNDEFL_INCR_EN);
-+ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(7)
-+ | SDHCI_GM_RD_OSRC_LMT_SEL(7));
++ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) | /* set write outstanding 8 (lmt + 1) */
++ SDHCI_GM_RD_OSRC_LMT_SEL(0x7)); /* set read outstanding 8 (lmt + 1) */
+ sdhci_writel(host, mbiiu_ctrl, SDHCI_AXI_MBIIU_CTRL);
+
+ val = sdhci_readl(host, SDHCI_MULTI_CYCLE);
@@ -281000,17 +348991,21 @@ index 0000000..354975a
+ host->error_count = 0;
+}
+
-+static void hisi_set_drv_str(struct regmap *iocfg_regmap, unsigned int offset,
-+ unsigned int pull_up, unsigned int pull_down, unsigned int sr, unsigned int drv_str)
++static void hisi_set_drv_str(struct regmap *iocfg_regmap,
++ unsigned int offset, unsigned int pull_up,
++ unsigned int pull_down, unsigned int sr,
++ unsigned int drv_str)
+{
+ unsigned int reg = 0;
++
+ regmap_read(iocfg_regmap, offset, ®);
+
-+ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN | IO_CFG_DRV_STR_MASK | IO_CFG_SR);
-+ reg |= (pull_up ? IO_CFG_PULL_UP: 0);
-+ reg |= (pull_down ? IO_CFG_PULL_DOWN: 0);
-+ reg |= (sr ? IO_CFG_SR: 0);
-+ reg |= IO_CFG_DRV_STR_SEL(drv_str);
++ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN |
++ IO_CFG_DRV_STR_MASK | IO_CFG_SR);
++ reg |= (pull_up ? IO_CFG_PULL_UP : 0);
++ reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
++ reg |= (sr ? IO_CFG_SR : 0);
++ reg |= io_cfg_drv_str_sel(drv_str);
+
+ regmap_write(iocfg_regmap, offset, reg);
+}
@@ -281028,50 +349023,46 @@ index 0000000..354975a
+static void hisi_set_mmc_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_MMC_HS400:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 0, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS200:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2); /* set drv level 2 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ }
+}
@@ -281079,26 +349070,24 @@ index 0000000..354975a
+static void hisi_set_sd_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_SD_HS:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7); /* set drv level 7 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ }
+}
@@ -281106,39 +349095,35 @@ index 0000000..354975a
+static void hisi_set_sdio_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio1_data_reg[i], 1, 0, 0, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio1_data_reg[i], 1, 0, 0, 0x7); /* set drv level 7 */
+}
+
+static void hisi_set_io_config(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ unsigned int reg = 0;
+
+ if (devid == 0) {
+ /* For mmc0: eMMC and SD card */
+ regmap_read(iocfg_regmap, REG_CTRL_EMMC_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
+ hisi_set_mmc_drv(host);
-+ }
+
+ regmap_read(iocfg_regmap, REG_CTRL_SDIO0_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_SD))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_SD))
+ hisi_set_sd_drv(host);
-+ }
-+ }
-+ else {
++ } else {
+ /* For mmc1: sdio wifi */
+ hisi_set_sdio_drv(host);
+ }
@@ -281152,34 +349137,34 @@ index 0000000..354975a
+ if (devid == 0) {
+ /* For eMMC and SD card */
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
-+ hisi_priv->drv_phase = 10; /* 112.5 degree */
++ hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
-+ hisi_priv->drv_phase = 23; /* 258.75 degree */
++ hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 0 for 0 degree */
+ } else {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ }
+ } else {
+ /* For SDIO device */
+ if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
+ (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else {
+ /* UHS_SDR12 */
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 0 for 0 degree */
+ }
+ }
+}
@@ -281197,63 +349182,64 @@ index 0000000..354975a
+}
diff --git a/drivers/mmc/host/sdhci-hi3516ev200.c b/drivers/mmc/host/sdhci-hi3516ev200.c
new file mode 100644
-index 0000000..3fdea09
+index 0000000..87fe041
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hi3516ev200.c
-@@ -0,0 +1,474 @@
+@@ -0,0 +1,471 @@
+/*
-+ * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
++ * Copyright (c) 2018 - 2019 HiSilicon Technologies Co., Ltd.
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
+ */
+
-+#define REG_EMMC_DRV_DLL_CTRL 0x1fc /*emmc&sd share emmc0 controller*/
++#define REG_EMMC_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO1_DRV_DLL_CTRL 0x220
-+#define REG_SDIO2_DRV_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_CTRL /* no sdio2 */
+#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
-+#define SDIO_DRV_SEL(phase) ((phase) << 24)
++#define sdio_drv_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DRV_DLL_STATUS 0x210
+#define REG_SDIO0_DRV_DLL_STATUS 0x210
+#define REG_SDIO1_DRV_DLL_STATUS 0x228
-+#define REG_SDIO2_DRV_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_STATUS /* no sdio2 */
+#define SDIO_DRV_DLL_LOCK BIT(15)
+#define SDIO_DRV_DLL_READY BIT(14)
+
+#define REG_EMMC_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
-+#define REG_SDIO2_SAMPL_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_STATUS /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
+
+#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
-+#define REG_SDIO2_SAMPL_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
+
+#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
-+#define REG_SDIO2_SAMPLB_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPLB_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
-+#define SDIO_SAMPLB_SEL(phase) ((phase) << 0)
++#define sdio_samplb_sel(phase) ((phase) << 0)
+
+#define REG_EMMC_DS_DLL_CTRL 0x200
+#define EMMC_DS_DLL_MODE_SSEL BIT(13)
-+#define EMMC_DS_DLL_SSEL_MASK (0x7f)
++#define EMMC_DS_DLL_SSEL_MASK 0x7f
+
+#define REG_EMMC_DS180_DLL_CTRL 0x204
+#define EMMC_DS180_DLL_BYPASS BIT(15)
@@ -281266,17 +349252,17 @@ index 0000000..3fdea09
+#define REG_EMMC_CLK_CTRL 0x1f4
+#define REG_SDIO0_CLK_CTRL 0x1f4
+#define REG_SDIO1_CLK_CTRL 0x22c
-+#define REG_SDIO2_CLK_CTRL /*no sdio2*/
++#define REG_SDIO2_CLK_CTRL /* no sdio2 */
+#define SDIO_CLK_DRV_DLL_RST BIT(29)
+#define SDIO_CLK_CRG_RST BIT(27)
+
+#define IO_CFG_SR BIT(10)
-+#define IO_CFG_PULL_DOWN BIT(9)
++#define IO_CFG_PULL_DOWN BIT(9)
+#define IO_CFG_PULL_UP BIT(8)
+#define IO_CFG_DRV_STR_MASK (0xf << 4)
-+#define IO_CFG_DRV_STR_SEL(str) ((str) << 4)
++#define io_cfg_drv_str_sel(str) ((str) << 4)
+#define IO_CFG_PIN_MUX_MASK (0xf << 0)
-+#define IO_CFG_PIN_MUX_SEL(type) ((type) << 0)
++#define io_cfg_pin_mux_sel(type) ((type) << 0)
+#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
+#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
+
@@ -281287,16 +349273,13 @@ index 0000000..3fdea09
+#define REG_CTRL_EMMC_DATA1 0x0028
+#define REG_CTRL_EMMC_DATA2 0x0024
+#define REG_CTRL_EMMC_DATA3 0x0020
-+/*
-+#define REG_CTRL_EMMC_DATA4 0x0030
-+#define REG_CTRL_EMMC_DATA5 0x0034
-+#define REG_CTRL_EMMC_DATA6 0x0038
-+#define REG_CTRL_EMMC_DATA7 0x003c
-+*/
++
+#define REG_CTRL_EMMC_DS 0x0058
+#define REG_CTRL_EMMC_RST 0x005c
-+static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
-+ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3};
++static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {
++ REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
++ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3
++};
+
+#define IO_CFG_SDIO0_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO0_CLK 0x0040
@@ -281305,8 +349288,10 @@ index 0000000..3fdea09
+#define REG_CTRL_SDIO0_DATA1 0x004C
+#define REG_CTRL_SDIO0_DATA2 0x0050
+#define REG_CTRL_SDIO0_DATA3 0x0054
-+static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
-+ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3};
++static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
++ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3
++};
+
+#define IO_CFG_SDIO1_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO1_CLK 0x0048
@@ -281315,8 +349300,10 @@ index 0000000..3fdea09
+#define REG_CTRL_SDIO1_DATA1 0x0060
+#define REG_CTRL_SDIO1_DATA2 0x005C
+#define REG_CTRL_SDIO1_DATA3 0x0058
-+static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
-+ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3};
++static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
++ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3
++};
+
+struct sdhci_hisi_priv {
+ struct reset_control *crg_rst;
@@ -281331,8 +349318,7 @@ index 0000000..3fdea09
+ unsigned int tuning_phase;
+};
+
-+static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc,
-+ struct mmc_ios *ios)
++static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ u32 ctrl;
+ struct sdhci_host *host = mmc_priv(mmc);
@@ -281346,39 +349332,36 @@ index 0000000..3fdea09
+ sdhci_writel(host, ctrl, SDHCI_EMMC_CTRL);
+}
+
-+static int sdhci_hisi_pltfm_init(struct platform_device *pdev,
-+ struct sdhci_host *host)
++static int sdhci_hisi_pltfm_init(struct platform_device *pdev, struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_hisi_priv *hisi_priv = sdhci_pltfm_priv(pltfm_host);
+ struct device_node *np = pdev->dev.of_node;
-+ struct clk *clk;
++ struct clk *clk = NULL;
+ int ret;
+
+ hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
+ dev_err(&pdev->dev, "get crg_rst failed.\n");
-+ return PTR_ERR(hisi_priv->crg_rst);;
++ return PTR_ERR(hisi_priv->crg_rst);
+ }
+
+ hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
+ dev_err(&pdev->dev, "get dll_rst failed.\n");
-+ return PTR_ERR(hisi_priv->dll_rst);;
++ return PTR_ERR(hisi_priv->dll_rst);
+ }
+
+ hisi_priv->sampl_rst = NULL;
+
+ hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
-+ if (IS_ERR(hisi_priv->crg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->crg_regmap)) {
+ dev_err(&pdev->dev, "get crg regmap failed.\n");
+ return PTR_ERR(hisi_priv->crg_regmap);
+ }
+
+ hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
-+ if (IS_ERR(hisi_priv->iocfg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->iocfg_regmap)) {
+ dev_err(&pdev->dev, "get iocfg regmap failed.\n");
+ return PTR_ERR(hisi_priv->iocfg_regmap);
+ }
@@ -281399,19 +349382,23 @@ index 0000000..3fdea09
+ if (ret)
+ return ret;
+
-+ /* only eMMC has a hw reset, and now eMMC signaling
-+ * is fixed to 180*/
++ /*
++ * Only eMMC has a hw reset, and now eMMC signaling
++ * is fixed to 180
++ */
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ host->flags &= ~SDHCI_SIGNALING_330;
+ host->flags |= SDHCI_SIGNALING_180;
+ }
+
-+ /* we parse the support timings from dts, so we read the
++ /*
++ * We parse the support timings from dts, so we read the
+ * host capabilities early and clear the timing capabilities,
+ * SDHCI_QUIRK_MISSING_CAPS is set so that sdhci driver would
-+ * not read it again */
++ * not read it again
++ */
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-+ host->caps &= ~(SDHCI_CAN_DO_HISPD);
++ host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
+ SDHCI_SUPPORT_DDR50 | SDHCI_CAN_DO_ADMA3);
@@ -281419,7 +349406,8 @@ index 0000000..3fdea09
+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_SINGLE_POWER_WRITE;
+
-+ host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_hs400_enhanced_strobe;
++ host->mmc_host_ops.hs400_enhanced_strobe =
++ sdhci_hisi_hs400_enhanced_strobe;
+
+ mci_host[slot_index++] = host->mmc;
+
@@ -281428,18 +349416,19 @@ index 0000000..3fdea09
+
+static void hisi_wait_ds_dll_lock(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_wait_ds_180_dll_ready(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ unsigned int reg, timeout = 20;
++ unsigned int reg;
++ unsigned int timeout = 20;
+
+ do {
+ reg = 0;
-+ regmap_read(hisi_priv->crg_regmap, REG_EMMC_DS180_DLL_STATUS, ®);
++ regmap_read(hisi_priv->crg_regmap,
++ REG_EMMC_DS180_DLL_STATUS, ®);
+ if (reg & EMMC_DS180_DLL_READY)
+ return;
+
@@ -281452,8 +349441,7 @@ index 0000000..3fdea09
+
+static void hisi_set_ds_dll_delay(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_host_extra_init(struct sdhci_host *host)
@@ -281468,8 +349456,8 @@ index 0000000..3fdea09
+ mbiiu_ctrl = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
+ mbiiu_ctrl &= ~(SDHCI_GM_WR_OSRC_LMT_MASK | SDHCI_GM_RD_OSRC_LMT_MASK |
+ SDHCI_UNDEFL_INCR_EN);
-+ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(7)
-+ | SDHCI_GM_RD_OSRC_LMT_SEL(7));
++ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) | /* set write outstanding 8 (lmt + 1) */
++ SDHCI_GM_RD_OSRC_LMT_SEL(0x7)); /* set read outstanding 8 (lmt + 1) */
+ sdhci_writel(host, mbiiu_ctrl, SDHCI_AXI_MBIIU_CTRL);
+
+ val = sdhci_readl(host, SDHCI_MULTI_CYCLE);
@@ -281480,17 +349468,21 @@ index 0000000..3fdea09
+ host->error_count = 0;
+}
+
-+static void hisi_set_drv_str(struct regmap *iocfg_regmap, unsigned int offset,
-+ unsigned int pull_up, unsigned int pull_down, unsigned int sr, unsigned int drv_str)
++static void hisi_set_drv_str(struct regmap *iocfg_regmap,
++ unsigned int offset, unsigned int pull_up,
++ unsigned int pull_down, unsigned int sr,
++ unsigned int drv_str)
+{
+ unsigned int reg = 0;
++
+ regmap_read(iocfg_regmap, offset, ®);
+
-+ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN | IO_CFG_DRV_STR_MASK | IO_CFG_SR);
-+ reg |= (pull_up ? IO_CFG_PULL_UP: 0);
-+ reg |= (pull_down ? IO_CFG_PULL_DOWN: 0);
-+ reg |= (sr ? IO_CFG_SR: 0);
-+ reg |= IO_CFG_DRV_STR_SEL(drv_str);
++ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN |
++ IO_CFG_DRV_STR_MASK | IO_CFG_SR);
++ reg |= (pull_up ? IO_CFG_PULL_UP : 0);
++ reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
++ reg |= (sr ? IO_CFG_SR : 0);
++ reg |= io_cfg_drv_str_sel(drv_str);
+
+ regmap_write(iocfg_regmap, offset, reg);
+}
@@ -281508,50 +349500,46 @@ index 0000000..3fdea09
+static void hisi_set_mmc_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_MMC_HS400:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 0, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS200:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2); /* set drv level 2 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ }
+}
@@ -281559,26 +349547,24 @@ index 0000000..3fdea09
+static void hisi_set_sd_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_SD_HS:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7); /* set drv level 7 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ }
+}
@@ -281586,39 +349572,35 @@ index 0000000..3fdea09
+static void hisi_set_sdio_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x4);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio1_data_reg[i], 1, 0, 0, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio1_data_reg[i], 1, 0, 0, 0x7); /* set drv level 7 */
+}
+
+static void hisi_set_io_config(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ unsigned int reg = 0;
+
+ if (devid == 0) {
+ /* For mmc0: eMMC and SD card */
+ regmap_read(iocfg_regmap, REG_CTRL_EMMC_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
+ hisi_set_mmc_drv(host);
-+ }
+
+ regmap_read(iocfg_regmap, REG_CTRL_SDIO0_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_SD))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_SD))
+ hisi_set_sd_drv(host);
-+ }
-+ }
-+ else {
++ } else {
+ /* For mmc1: sdio wifi */
+ hisi_set_sdio_drv(host);
+ }
@@ -281632,34 +349614,34 @@ index 0000000..3fdea09
+ if (devid == 0) {
+ /* For eMMC and SD card */
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
-+ hisi_priv->drv_phase = 10; /* 112.5 degree */
++ hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
-+ hisi_priv->drv_phase = 23; /* 258.75 degree */
++ hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 16 for 180 degree */
+ } else {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ }
+ } else {
+ /* For SDIO device */
+ if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
+ (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else {
+ /* UHS_SDR12 */
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 0 for 0 degree */
+ }
+ }
+}
@@ -281677,63 +349659,64 @@ index 0000000..3fdea09
+}
diff --git a/drivers/mmc/host/sdhci-hi3516ev300.c b/drivers/mmc/host/sdhci-hi3516ev300.c
new file mode 100644
-index 0000000..f0e056a
+index 0000000..fc416cc
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hi3516ev300.c
-@@ -0,0 +1,482 @@
+@@ -0,0 +1,484 @@
+/*
-+ * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
++ * Copyright (c) 2018 - 2019 HiSilicon Technologies Co., Ltd.
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
+ */
+
-+#define REG_EMMC_DRV_DLL_CTRL 0x1fc /*emmc&sd share emmc0 controller*/
++#define REG_EMMC_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO1_DRV_DLL_CTRL 0x220
-+#define REG_SDIO2_DRV_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_CTRL /* no sdio2 */
+#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
-+#define SDIO_DRV_SEL(phase) ((phase) << 24)
++#define sdio_drv_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DRV_DLL_STATUS 0x210
+#define REG_SDIO0_DRV_DLL_STATUS 0x210
+#define REG_SDIO1_DRV_DLL_STATUS 0x228
-+#define REG_SDIO2_DRV_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_STATUS /* no sdio2 */
+#define SDIO_DRV_DLL_LOCK BIT(15)
+#define SDIO_DRV_DLL_READY BIT(14)
+
+#define REG_EMMC_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
-+#define REG_SDIO2_SAMPL_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_STATUS /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
+
+#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
-+#define REG_SDIO2_SAMPL_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
+
+#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
-+#define REG_SDIO2_SAMPLB_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPLB_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
-+#define SDIO_SAMPLB_SEL(phase) ((phase) << 0)
++#define sdio_samplb_sel(phase) ((phase) << 0)
+
+#define REG_EMMC_DS_DLL_CTRL 0x200
+#define EMMC_DS_DLL_MODE_SSEL BIT(13)
-+#define EMMC_DS_DLL_SSEL_MASK (0x7f)
++#define EMMC_DS_DLL_SSEL_MASK 0x7f
+
+#define REG_EMMC_DS180_DLL_CTRL 0x204
+#define EMMC_DS180_DLL_BYPASS BIT(15)
@@ -281746,17 +349729,17 @@ index 0000000..f0e056a
+#define REG_EMMC_CLK_CTRL 0x1f4
+#define REG_SDIO0_CLK_CTRL 0x1f4
+#define REG_SDIO1_CLK_CTRL 0x22c
-+#define REG_SDIO2_CLK_CTRL /*no sdio2*/
++#define REG_SDIO2_CLK_CTRL /* no sdio2 */
+#define SDIO_CLK_DRV_DLL_RST BIT(29)
+#define SDIO_CLK_CRG_RST BIT(27)
+
+#define IO_CFG_SR BIT(10)
-+#define IO_CFG_PULL_DOWN BIT(9)
++#define IO_CFG_PULL_DOWN BIT(9)
+#define IO_CFG_PULL_UP BIT(8)
+#define IO_CFG_DRV_STR_MASK (0xf << 4)
-+#define IO_CFG_DRV_STR_SEL(str) ((str) << 4)
++#define io_cfg_drv_str_sel(str) ((str) << 4)
+#define IO_CFG_PIN_MUX_MASK (0xf << 0)
-+#define IO_CFG_PIN_MUX_SEL(type) ((type) << 0)
++#define io_cfg_pin_mux_sel(type) ((type) << 0)
+#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
+#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
+
@@ -281773,10 +349756,12 @@ index 0000000..f0e056a
+#define REG_CTRL_EMMC_DATA7 0x003c
+#define REG_CTRL_EMMC_DS 0x0058
+#define REG_CTRL_EMMC_RST 0x005c
-+static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
-+ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3,
-+ REG_CTRL_EMMC_DATA4, REG_CTRL_EMMC_DATA5,
-+ REG_CTRL_EMMC_DATA6, REG_CTRL_EMMC_DATA7};
++static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {
++ REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
++ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3,
++ REG_CTRL_EMMC_DATA4, REG_CTRL_EMMC_DATA5,
++ REG_CTRL_EMMC_DATA6, REG_CTRL_EMMC_DATA7
++};
+
+#define IO_CFG_SDIO0_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO0_CLK 0x0040
@@ -281785,8 +349770,10 @@ index 0000000..f0e056a
+#define REG_CTRL_SDIO0_DATA1 0x004C
+#define REG_CTRL_SDIO0_DATA2 0x0050
+#define REG_CTRL_SDIO0_DATA3 0x0054
-+static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
-+ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3};
++static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
++ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3
++};
+
+#define IO_CFG_SDIO1_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO1_CLK 0x0060
@@ -281795,8 +349782,10 @@ index 0000000..f0e056a
+#define REG_CTRL_SDIO1_DATA1 0x006C
+#define REG_CTRL_SDIO1_DATA2 0x0070
+#define REG_CTRL_SDIO1_DATA3 0x0074
-+static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
-+ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3};
++static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
++ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3
++};
+
+struct sdhci_hisi_priv {
+ struct reset_control *crg_rst;
@@ -281811,8 +349800,7 @@ index 0000000..f0e056a
+ unsigned int tuning_phase;
+};
+
-+static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc,
-+ struct mmc_ios *ios)
++static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ u32 ctrl;
+ struct sdhci_host *host = mmc_priv(mmc);
@@ -281834,39 +349822,36 @@ index 0000000..f0e056a
+ sdhci_writel(host, ctrl, SDHCI_MULTI_CYCLE);
+}
+
-+static int sdhci_hisi_pltfm_init(struct platform_device *pdev,
-+ struct sdhci_host *host)
++static int sdhci_hisi_pltfm_init(struct platform_device *pdev, struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_hisi_priv *hisi_priv = sdhci_pltfm_priv(pltfm_host);
+ struct device_node *np = pdev->dev.of_node;
-+ struct clk *clk;
++ struct clk *clk = NULL;
+ int ret;
+
+ hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
+ dev_err(&pdev->dev, "get crg_rst failed.\n");
-+ return PTR_ERR(hisi_priv->crg_rst);;
++ return PTR_ERR(hisi_priv->crg_rst);
+ }
+
+ hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
+ dev_err(&pdev->dev, "get dll_rst failed.\n");
-+ return PTR_ERR(hisi_priv->dll_rst);;
++ return PTR_ERR(hisi_priv->dll_rst);
+ }
+
+ hisi_priv->sampl_rst = NULL;
+
+ hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
-+ if (IS_ERR(hisi_priv->crg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->crg_regmap)) {
+ dev_err(&pdev->dev, "get crg regmap failed.\n");
+ return PTR_ERR(hisi_priv->crg_regmap);
+ }
+
+ hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
-+ if (IS_ERR(hisi_priv->iocfg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->iocfg_regmap)) {
+ dev_err(&pdev->dev, "get iocfg regmap failed.\n");
+ return PTR_ERR(hisi_priv->iocfg_regmap);
+ }
@@ -281887,19 +349872,23 @@ index 0000000..f0e056a
+ if (ret)
+ return ret;
+
-+ /* only eMMC has a hw reset, and now eMMC signaling
-+ * is fixed to 180*/
++ /*
++ * Only eMMC has a hw reset, and now eMMC signaling
++ * is fixed to 180
++ */
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ host->flags &= ~SDHCI_SIGNALING_330;
+ host->flags |= SDHCI_SIGNALING_180;
+ }
+
-+ /* we parse the support timings from dts, so we read the
++ /*
++ * We parse the support timings from dts, so we read the
+ * host capabilities early and clear the timing capabilities,
+ * SDHCI_QUIRK_MISSING_CAPS is set so that sdhci driver would
-+ * not read it again */
++ * not read it again
++ */
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-+ host->caps &= ~(SDHCI_CAN_DO_HISPD);
++ host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
+ SDHCI_SUPPORT_DDR50 | SDHCI_CAN_DO_ADMA3);
@@ -281907,7 +349896,8 @@ index 0000000..f0e056a
+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_SINGLE_POWER_WRITE;
+
-+ host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_hs400_enhanced_strobe;
++ host->mmc_host_ops.hs400_enhanced_strobe =
++ sdhci_hisi_hs400_enhanced_strobe;
+
+ mci_host[slot_index++] = host->mmc;
+
@@ -281916,18 +349906,19 @@ index 0000000..f0e056a
+
+static void hisi_wait_ds_dll_lock(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_wait_ds_180_dll_ready(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ unsigned int reg, timeout = 20;
++ unsigned int reg;
++ unsigned int timeout = 20;
+
+ do {
+ reg = 0;
-+ regmap_read(hisi_priv->crg_regmap, REG_EMMC_DS180_DLL_STATUS, ®);
++ regmap_read(hisi_priv->crg_regmap,
++ REG_EMMC_DS180_DLL_STATUS, ®);
+ if (reg & EMMC_DS180_DLL_READY)
+ return;
+
@@ -281940,8 +349931,7 @@ index 0000000..f0e056a
+
+static void hisi_set_ds_dll_delay(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_host_extra_init(struct sdhci_host *host)
@@ -281956,8 +349946,8 @@ index 0000000..f0e056a
+ mbiiu_ctrl = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
+ mbiiu_ctrl &= ~(SDHCI_GM_WR_OSRC_LMT_MASK | SDHCI_GM_RD_OSRC_LMT_MASK |
+ SDHCI_UNDEFL_INCR_EN);
-+ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(7)
-+ | SDHCI_GM_RD_OSRC_LMT_SEL(7));
++ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) | /* set write outstanding 8 (lmt + 1) */
++ SDHCI_GM_RD_OSRC_LMT_SEL(0x7)); /* set read outstanding 8 (lmt + 1) */
+ sdhci_writel(host, mbiiu_ctrl, SDHCI_AXI_MBIIU_CTRL);
+
+ val = sdhci_readl(host, SDHCI_MULTI_CYCLE);
@@ -281968,17 +349958,21 @@ index 0000000..f0e056a
+ host->error_count = 0;
+}
+
-+static void hisi_set_drv_str(struct regmap *iocfg_regmap, unsigned int offset,
-+ unsigned int pull_up, unsigned int pull_down, unsigned int sr, unsigned int drv_str)
++static void hisi_set_drv_str(struct regmap *iocfg_regmap,
++ unsigned int offset, unsigned int pull_up,
++ unsigned int pull_down, unsigned int sr,
++ unsigned int drv_str)
+{
+ unsigned int reg = 0;
++
+ regmap_read(iocfg_regmap, offset, ®);
+
-+ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN | IO_CFG_DRV_STR_MASK | IO_CFG_SR);
-+ reg |= (pull_up ? IO_CFG_PULL_UP: 0);
-+ reg |= (pull_down ? IO_CFG_PULL_DOWN: 0);
-+ reg |= (sr ? IO_CFG_SR: 0);
-+ reg |= IO_CFG_DRV_STR_SEL(drv_str);
++ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN |
++ IO_CFG_DRV_STR_MASK | IO_CFG_SR);
++ reg |= (pull_up ? IO_CFG_PULL_UP : 0);
++ reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
++ reg |= (sr ? IO_CFG_SR : 0);
++ reg |= io_cfg_drv_str_sel(drv_str);
+
+ regmap_write(iocfg_regmap, offset, reg);
+}
@@ -281996,50 +349990,46 @@ index 0000000..f0e056a
+static void hisi_set_mmc_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_MMC_HS400:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 0, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS200:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2); /* set drv level 2 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ }
+}
@@ -282047,26 +350037,24 @@ index 0000000..f0e056a
+static void hisi_set_sd_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_SD_HS:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7); /* set drv level 7 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ }
+}
@@ -282074,39 +350062,35 @@ index 0000000..f0e056a
+static void hisi_set_sdio_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio1_data_reg[i], 1, 0, 0, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio1_data_reg[i], 1, 0, 0, 0x7); /* set drv level 7 */
+}
+
+static void hisi_set_io_config(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ unsigned int reg = 0;
+
+ if (devid == 0) {
+ /* For mmc0: eMMC and SD card */
+ regmap_read(iocfg_regmap, REG_CTRL_EMMC_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
+ hisi_set_mmc_drv(host);
-+ }
+
+ regmap_read(iocfg_regmap, REG_CTRL_SDIO0_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_SD))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_SD))
+ hisi_set_sd_drv(host);
-+ }
-+ }
-+ else {
++ } else {
+ /* For mmc1: sdio wifi */
+ hisi_set_sdio_drv(host);
+ }
@@ -282120,34 +350104,34 @@ index 0000000..f0e056a
+ if (devid == 0) {
+ /* For eMMC and SD card */
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
-+ hisi_priv->drv_phase = 10; /* 112.5 degree */
++ hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
-+ hisi_priv->drv_phase = 23; /* 258.75 degree */
++ hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 0 for 0 degree */
+ } else {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ }
+ } else {
+ /* For SDIO device */
+ if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
+ (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else {
+ /* UHS_SDR12 */
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 0 for 0 degree */
+ }
+ }
+}
@@ -282165,63 +350149,64 @@ index 0000000..f0e056a
+}
diff --git a/drivers/mmc/host/sdhci-hi3518ev300.c b/drivers/mmc/host/sdhci-hi3518ev300.c
new file mode 100644
-index 0000000..4bd5a09
+index 0000000..4b9f8f2
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hi3518ev300.c
-@@ -0,0 +1,474 @@
+@@ -0,0 +1,471 @@
+/*
-+ * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
++ * Copyright (c) 2018 - 2019 HiSilicon Technologies Co., Ltd.
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
+ */
+
-+#define REG_EMMC_DRV_DLL_CTRL 0x1fc /*emmc&sd share emmc0 controller*/
++#define REG_EMMC_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO1_DRV_DLL_CTRL 0x220
-+#define REG_SDIO2_DRV_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_CTRL /* no sdio2 */
+#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
-+#define SDIO_DRV_SEL(phase) ((phase) << 24)
++#define sdio_drv_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DRV_DLL_STATUS 0x210
+#define REG_SDIO0_DRV_DLL_STATUS 0x210
+#define REG_SDIO1_DRV_DLL_STATUS 0x228
-+#define REG_SDIO2_DRV_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_STATUS /* no sdio2 */
+#define SDIO_DRV_DLL_LOCK BIT(15)
+#define SDIO_DRV_DLL_READY BIT(14)
+
+#define REG_EMMC_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
+#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
-+#define REG_SDIO2_SAMPL_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_STATUS /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
+
+#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
+#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
-+#define REG_SDIO2_SAMPL_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
+
+#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
-+#define REG_SDIO2_SAMPLB_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPLB_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
-+#define SDIO_SAMPLB_SEL(phase) ((phase) << 0)
++#define sdio_samplb_sel(phase) ((phase) << 0)
+
+#define REG_EMMC_DS_DLL_CTRL 0x200
+#define EMMC_DS_DLL_MODE_SSEL BIT(13)
-+#define EMMC_DS_DLL_SSEL_MASK (0x7f)
++#define EMMC_DS_DLL_SSEL_MASK 0x7f
+
+#define REG_EMMC_DS180_DLL_CTRL 0x204
+#define EMMC_DS180_DLL_BYPASS BIT(15)
@@ -282234,17 +350219,17 @@ index 0000000..4bd5a09
+#define REG_EMMC_CLK_CTRL 0x1f4
+#define REG_SDIO0_CLK_CTRL 0x1f4
+#define REG_SDIO1_CLK_CTRL 0x22c
-+#define REG_SDIO2_CLK_CTRL /*no sdio2*/
++#define REG_SDIO2_CLK_CTRL /* no sdio2 */
+#define SDIO_CLK_DRV_DLL_RST BIT(29)
+#define SDIO_CLK_CRG_RST BIT(27)
+
+#define IO_CFG_SR BIT(10)
-+#define IO_CFG_PULL_DOWN BIT(9)
++#define IO_CFG_PULL_DOWN BIT(9)
+#define IO_CFG_PULL_UP BIT(8)
+#define IO_CFG_DRV_STR_MASK (0xf << 4)
-+#define IO_CFG_DRV_STR_SEL(str) ((str) << 4)
++#define io_cfg_drv_str_sel(str) ((str) << 4)
+#define IO_CFG_PIN_MUX_MASK (0xf << 0)
-+#define IO_CFG_PIN_MUX_SEL(type) ((type) << 0)
++#define io_cfg_pin_mux_sel(type) ((type) << 0)
+#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
+#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
+
@@ -282255,16 +350240,13 @@ index 0000000..4bd5a09
+#define REG_CTRL_EMMC_DATA1 0x0028
+#define REG_CTRL_EMMC_DATA2 0x0024
+#define REG_CTRL_EMMC_DATA3 0x0020
-+/*
-+#define REG_CTRL_EMMC_DATA4 0x0030
-+#define REG_CTRL_EMMC_DATA5 0x0034
-+#define REG_CTRL_EMMC_DATA6 0x0038
-+#define REG_CTRL_EMMC_DATA7 0x003c
-+*/
++
+#define REG_CTRL_EMMC_DS 0x0058
+#define REG_CTRL_EMMC_RST 0x005c
-+static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
-+ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3};
++static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {
++ REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
++ REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3
++};
+
+#define IO_CFG_SDIO0_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO0_CLK 0x0040
@@ -282273,8 +350255,10 @@ index 0000000..4bd5a09
+#define REG_CTRL_SDIO0_DATA1 0x004C
+#define REG_CTRL_SDIO0_DATA2 0x0050
+#define REG_CTRL_SDIO0_DATA3 0x0054
-+static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
-+ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3};
++static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
++ REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3
++};
+
+#define IO_CFG_SDIO1_DATA_LINE_COUNT 4
+#define REG_CTRL_SDIO1_CLK 0x0048
@@ -282283,8 +350267,10 @@ index 0000000..4bd5a09
+#define REG_CTRL_SDIO1_DATA1 0x0060
+#define REG_CTRL_SDIO1_DATA2 0x005C
+#define REG_CTRL_SDIO1_DATA3 0x0058
-+static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
-+ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3};
++static unsigned int io_sdio1_data_reg[IO_CFG_SDIO1_DATA_LINE_COUNT] = {
++ REG_CTRL_SDIO1_DATA0, REG_CTRL_SDIO1_DATA1,
++ REG_CTRL_SDIO1_DATA2, REG_CTRL_SDIO1_DATA3
++};
+
+struct sdhci_hisi_priv {
+ struct reset_control *crg_rst;
@@ -282299,8 +350285,7 @@ index 0000000..4bd5a09
+ unsigned int tuning_phase;
+};
+
-+static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc,
-+ struct mmc_ios *ios)
++static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ u32 ctrl;
+ struct sdhci_host *host = mmc_priv(mmc);
@@ -282314,39 +350299,36 @@ index 0000000..4bd5a09
+ sdhci_writel(host, ctrl, SDHCI_EMMC_CTRL);
+}
+
-+static int sdhci_hisi_pltfm_init(struct platform_device *pdev,
-+ struct sdhci_host *host)
++static int sdhci_hisi_pltfm_init(struct platform_device *pdev, struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_hisi_priv *hisi_priv = sdhci_pltfm_priv(pltfm_host);
+ struct device_node *np = pdev->dev.of_node;
-+ struct clk *clk;
++ struct clk *clk = NULL;
+ int ret;
+
+ hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
+ dev_err(&pdev->dev, "get crg_rst failed.\n");
-+ return PTR_ERR(hisi_priv->crg_rst);;
++ return PTR_ERR(hisi_priv->crg_rst);
+ }
+
+ hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
+ dev_err(&pdev->dev, "get dll_rst failed.\n");
-+ return PTR_ERR(hisi_priv->dll_rst);;
++ return PTR_ERR(hisi_priv->dll_rst);
+ }
+
+ hisi_priv->sampl_rst = NULL;
+
+ hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
-+ if (IS_ERR(hisi_priv->crg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->crg_regmap)) {
+ dev_err(&pdev->dev, "get crg regmap failed.\n");
+ return PTR_ERR(hisi_priv->crg_regmap);
+ }
+
+ hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
-+ if (IS_ERR(hisi_priv->iocfg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->iocfg_regmap)) {
+ dev_err(&pdev->dev, "get iocfg regmap failed.\n");
+ return PTR_ERR(hisi_priv->iocfg_regmap);
+ }
@@ -282367,19 +350349,23 @@ index 0000000..4bd5a09
+ if (ret)
+ return ret;
+
-+ /* only eMMC has a hw reset, and now eMMC signaling
-+ * is fixed to 180*/
++ /*
++ * Only eMMC has a hw reset, and now eMMC signaling
++ * is fixed to 180
++ */
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ host->flags &= ~SDHCI_SIGNALING_330;
+ host->flags |= SDHCI_SIGNALING_180;
+ }
+
-+ /* we parse the support timings from dts, so we read the
++ /*
++ * We parse the support timings from dts, so we read the
+ * host capabilities early and clear the timing capabilities,
+ * SDHCI_QUIRK_MISSING_CAPS is set so that sdhci driver would
-+ * not read it again */
++ * not read it again
++ */
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-+ host->caps &= ~(SDHCI_CAN_DO_HISPD);
++ host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
+ SDHCI_SUPPORT_DDR50 | SDHCI_CAN_DO_ADMA3);
@@ -282387,7 +350373,8 @@ index 0000000..4bd5a09
+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_SINGLE_POWER_WRITE;
+
-+ host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_hs400_enhanced_strobe;
++ host->mmc_host_ops.hs400_enhanced_strobe =
++ sdhci_hisi_hs400_enhanced_strobe;
+
+ mci_host[slot_index++] = host->mmc;
+
@@ -282396,18 +350383,19 @@ index 0000000..4bd5a09
+
+static void hisi_wait_ds_dll_lock(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_wait_ds_180_dll_ready(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ unsigned int reg, timeout = 20;
++ unsigned int reg;
++ unsigned int timeout = 20;
+
+ do {
+ reg = 0;
-+ regmap_read(hisi_priv->crg_regmap, REG_EMMC_DS180_DLL_STATUS, ®);
++ regmap_read(hisi_priv->crg_regmap,
++ REG_EMMC_DS180_DLL_STATUS, ®);
+ if (reg & EMMC_DS180_DLL_READY)
+ return;
+
@@ -282420,8 +350408,7 @@ index 0000000..4bd5a09
+
+static void hisi_set_ds_dll_delay(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_host_extra_init(struct sdhci_host *host)
@@ -282436,8 +350423,8 @@ index 0000000..4bd5a09
+ mbiiu_ctrl = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
+ mbiiu_ctrl &= ~(SDHCI_GM_WR_OSRC_LMT_MASK | SDHCI_GM_RD_OSRC_LMT_MASK |
+ SDHCI_UNDEFL_INCR_EN);
-+ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(7)
-+ | SDHCI_GM_RD_OSRC_LMT_SEL(7));
++ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) | /* set write outstanding 8 (lmt + 1) */
++ SDHCI_GM_RD_OSRC_LMT_SEL(0x7)); /* set read outstanding 8 (lmt + 1) */
+ sdhci_writel(host, mbiiu_ctrl, SDHCI_AXI_MBIIU_CTRL);
+
+ val = sdhci_readl(host, SDHCI_MULTI_CYCLE);
@@ -282448,17 +350435,21 @@ index 0000000..4bd5a09
+ host->error_count = 0;
+}
+
-+static void hisi_set_drv_str(struct regmap *iocfg_regmap, unsigned int offset,
-+ unsigned int pull_up, unsigned int pull_down, unsigned int sr, unsigned int drv_str)
++static void hisi_set_drv_str(struct regmap *iocfg_regmap,
++ unsigned int offset, unsigned int pull_up,
++ unsigned int pull_down, unsigned int sr,
++ unsigned int drv_str)
+{
+ unsigned int reg = 0;
++
+ regmap_read(iocfg_regmap, offset, ®);
+
-+ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN | IO_CFG_DRV_STR_MASK | IO_CFG_SR);
-+ reg |= (pull_up ? IO_CFG_PULL_UP: 0);
-+ reg |= (pull_down ? IO_CFG_PULL_DOWN: 0);
-+ reg |= (sr ? IO_CFG_SR: 0);
-+ reg |= IO_CFG_DRV_STR_SEL(drv_str);
++ reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN |
++ IO_CFG_DRV_STR_MASK | IO_CFG_SR);
++ reg |= (pull_up ? IO_CFG_PULL_UP : 0);
++ reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
++ reg |= (sr ? IO_CFG_SR : 0);
++ reg |= io_cfg_drv_str_sel(drv_str);
+
+ regmap_write(iocfg_regmap, offset, reg);
+}
@@ -282476,50 +350467,46 @@ index 0000000..4bd5a09
+static void hisi_set_mmc_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_MMC_HS400:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 0, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS200:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4); /* set drv level 4 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x4);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_MMC_HS:
+ hisi_set_emmc_ctrl(host);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4); /* set drv level 4 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_emmc_data_reg[i], 1, 0, 1, 0x6);
-+ }
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3);
++ hisi_set_drv_str(iocfg_regmap,
++ io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
+ break;
+ }
+}
@@ -282527,26 +350514,24 @@ index 0000000..4bd5a09
+static void hisi_set_sd_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
+ switch (host->timing) {
+ case MMC_TIMING_SD_HS:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ case MMC_TIMING_LEGACY:
+ default:
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7); /* set drv level 7 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
+ for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio0_data_reg[i], 1, 0, 1, 0x7);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
+ break;
+ }
+}
@@ -282554,39 +350539,35 @@ index 0000000..4bd5a09
+static void hisi_set_sdio_drv(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ int i;
+
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x3);
-+ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x6);
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1, 0x3); /* set drv level 3 */
++ hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0, 0x6); /* set drv level 6 */
+ for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
-+ {
-+ hisi_set_drv_str(iocfg_regmap, io_sdio1_data_reg[i], 1, 0, 0, 0x6);
-+ }
++ hisi_set_drv_str(iocfg_regmap,
++ io_sdio1_data_reg[i], 1, 0, 0, 0x6); /* set drv level 6 */
+}
+
+static void hisi_set_io_config(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ unsigned int reg = 0;
+
+ if (devid == 0) {
+ /* For mmc0: eMMC and SD card */
+ regmap_read(iocfg_regmap, REG_CTRL_EMMC_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_EMMC))
+ hisi_set_mmc_drv(host);
-+ }
+
+ regmap_read(iocfg_regmap, REG_CTRL_SDIO0_CLK, ®);
-+ if ((reg & IO_CFG_PIN_MUX_MASK) == IO_CFG_PIN_MUX_SEL(IO_CFG_PIN_MUX_TYPE_CLK_SD))
-+ {
++ if ((reg & IO_CFG_PIN_MUX_MASK) ==
++ io_cfg_pin_mux_sel(IO_CFG_PIN_MUX_TYPE_CLK_SD))
+ hisi_set_sd_drv(host);
-+ }
-+ }
-+ else {
++ } else {
+ /* For mmc1: sdio wifi */
+ hisi_set_sdio_drv(host);
+ }
@@ -282600,34 +350581,34 @@ index 0000000..4bd5a09
+ if (devid == 0) {
+ /* For eMMC and SD card */
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
-+ hisi_priv->drv_phase = 10; /* 112.5 degree */
++ hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
-+ hisi_priv->drv_phase = 23; /* 258.75 degree */
++ hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 0 for 0 degree */
+ } else {
-+ hisi_priv->drv_phase = 20; /* 225 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ }
+ } else {
+ /* For SDIO device */
+ if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
+ (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ } else {
+ /* UHS_SDR12 */
-+ hisi_priv->drv_phase = 16; /* 180 degree */
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
++ hisi_priv->sampl_phase = 0; /* 0 for 0 degree */
+ }
+ }
+}
@@ -282645,7 +350626,7 @@ index 0000000..4bd5a09
+}
diff --git a/drivers/mmc/host/sdhci-hi3519av100.c b/drivers/mmc/host/sdhci-hi3519av100.c
new file mode 100644
-index 0000000..3f5c9ec
+index 0000000..3b7aaa6
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hi3519av100.c
@@ -0,0 +1,18 @@
@@ -282665,11 +350646,11 @@ index 0000000..3f5c9ec
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
-+
++
+#include "sdhci-hi3556av100.c"
diff --git a/drivers/mmc/host/sdhci-hi3556av100.c b/drivers/mmc/host/sdhci-hi3556av100.c
new file mode 100644
-index 0000000..b4254a9
+index 0000000..53f10d0
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hi3556av100.c
@@ -0,0 +1,491 @@
@@ -282693,43 +350674,43 @@ index 0000000..b4254a9
+#define REG_EMMC_DRV_DLL_CTRL 0x1b0
+#define REG_SDIO0_DRV_DLL_CTRL 0x1d4
+#define REG_SDIO1_DRV_DLL_CTRL 0x1fc
-+#define REG_SDIO2_DRV_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_CTRL /* no sdio2 */
+#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
-+#define SDIO_DRV_SEL(phase) ((phase) << 24)
++#define sdio_drv_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DRV_DLL_STATUS 0x1c4
+#define REG_SDIO0_DRV_DLL_STATUS 0x1e8
+#define REG_SDIO1_DRV_DLL_STATUS 0x210
-+#define REG_SDIO2_DRV_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_DRV_DLL_STATUS /* no sdio2 */
+#define SDIO_DRV_DLL_LOCK BIT(15)
+
+#define REG_EMMC_SAMPL_DLL_STATUS 0x1bc
+#define REG_SDIO0_SAMPL_DLL_STATUS 0x1e0
+#define REG_SDIO1_SAMPL_DLL_STATUS 0x208
-+#define REG_SDIO2_SAMPL_DLL_STATUS /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_STATUS /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_READY BIT(14)
+
+#define REG_EMMC_SAMPL_DLL_CTRL 0x1a8
+#define REG_SDIO0_SAMPL_DLL_CTRL 0x1ec
+#define REG_SDIO1_SAMPL_DLL_CTRL 0x214
-+#define REG_SDIO2_SAMPL_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPL_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
+
+#define REG_EMMC_SAMPLB_DLL_CTRL 0x1ac
+#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1d0
+#define REG_SDIO1_SAMPLB_DLL_CTRL 0x1f8
-+#define REG_SDIO2_SAMPLB_DLL_CTRL /*no sdio2*/
++#define REG_SDIO2_SAMPLB_DLL_CTRL /* no sdio2 */
+#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 24)
-+#define SDIO_SAMPLB_SEL(phase) ((phase) << 24)
++#define sdio_samplb_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DS_DLL_CTRL 0x1b4
+#define EMMC_DS_DLL_MODE_SSEL BIT(13)
-+#define EMMC_DS_DLL_SSEL_MASK (0x1fff)
++#define EMMC_DS_DLL_SSEL_MASK 0x1fff
+#define REG_EMMC_DS180_DLL_CTRL 0x1b8
+#define EMMC_DS180_DLL_BYPASS BIT(15)
+#define REG_EMMC_DS_DLL_STATUS 0x1c8
+#define EMMC_DS_DLL_LOCK BIT(15)
-+#define EMMC_DS_DLL_MDLY_TAP_MASK (0x1fff)
++#define EMMC_DS_DLL_MDLY_TAP_MASK 0x1fff
+
+#define REG_MISC_CTRL1 0x4
+#define SDIO1_PD_MUX_BYPASS BIT(9)
@@ -282759,20 +350740,20 @@ index 0000000..b4254a9
+
+
+/* SD drive capability */
-+static unsigned int sd_sdr104_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
-+static unsigned int sd_sdr50_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
-+static unsigned int sd_sdr25_hs_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
-+static unsigned int sd_other_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
++static unsigned int sd_sdr104_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
++static unsigned int sd_sdr50_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
++static unsigned int sd_sdr25_hs_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
++static unsigned int sd_other_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
+
+/* SDIO drive capability */
+#ifndef CONFIG_HISI_MC /* hi3519av100 SMP */
-+static unsigned int sdio_sdr104_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
++static unsigned int sdio_sdr104_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
+#else /* hi3519av100 hi3556av100 AMP */
-+static unsigned int sdio_sdr104_drv[] = {0xc0, 0x90, 0x90, 0x90, 0x90, 0x90};
++static unsigned int sdio_sdr104_drv[] = { 0xc0, 0x90, 0x90, 0x90, 0x90, 0x90 };
+#endif
-+static unsigned int sdio_sdr50_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
-+static unsigned int sdio_sdr25_hs_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
-+static unsigned int sdio_other_drv[] = {0x60, 0x20, 0x20, 0x20, 0x20, 0x20};
++static unsigned int sdio_sdr50_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
++static unsigned int sdio_sdr25_hs_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
++static unsigned int sdio_other_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
+
+
+struct sdhci_hisi_priv {
@@ -282816,7 +350797,7 @@ index 0000000..b4254a9
+ ctrl &= ~SDIO0_IO_MODE_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
+
-+ usleep_range(1000, 2000);
++ usleep_range(1000, 2000); /* Sleep between 1000 and 2000us */
+ ctrl &= ~SDIO0_PWRSW_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
+
@@ -282850,17 +350831,18 @@ index 0000000..b4254a9
+ ctrl |= SDIO0_PWRSW_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
+
-+ usleep_range(1000, 2000);
++ usleep_range(1000, 2000); /* Sleep between 1000 and 2000us */
+
+ ctrl |= SDIO0_IO_MODE_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
+
+ regmap_read(misc, REG_MISC_CTRL18, &ctrl);
-+ if ((ctrl & SDIO0_PWRSW_SEL_1V8) && (ctrl & SDIO0_IO_MODE_SEL_1V8))
++ if ((ctrl & SDIO0_PWRSW_SEL_1V8) &&
++ (ctrl & SDIO0_IO_MODE_SEL_1V8))
+ return 0;
+ }
+
-+ if (hisi_priv->devid == 2)
++ if (hisi_priv->devid == 2) /* for device id 2 */
+ return 0;
+
+ pr_warn("%s: 1.8V output did not became stable\n",
@@ -282869,8 +350851,7 @@ index 0000000..b4254a9
+ return -EAGAIN;
+}
+
-+static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc,
-+ struct mmc_ios *ios)
++static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ u32 ctrl;
+ struct sdhci_host *host = mmc_priv(mmc);
@@ -282884,36 +350865,34 @@ index 0000000..b4254a9
+ sdhci_writel(host, ctrl, SDHCI_EMMC_CTRL);
+}
+
-+static int sdhci_hisi_pltfm_init(struct platform_device *pdev,
-+ struct sdhci_host *host)
++static int sdhci_hisi_pltfm_init(struct platform_device *pdev, struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_hisi_priv *hisi_priv = sdhci_pltfm_priv(pltfm_host);
+ struct device_node *np = pdev->dev.of_node;
-+ struct clk *clk;
++ struct clk *clk = NULL;
+ int ret;
+
+ hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
+ dev_err(&pdev->dev, "get crg_rst failed.\n");
-+ return PTR_ERR(hisi_priv->crg_rst);;
++ return PTR_ERR(hisi_priv->crg_rst);
+ }
+
+ hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
+ dev_err(&pdev->dev, "get dll_rst failed.\n");
-+ return PTR_ERR(hisi_priv->dll_rst);;
++ return PTR_ERR(hisi_priv->dll_rst);
+ }
+
+ hisi_priv->sampl_rst = devm_reset_control_get(&pdev->dev, "sampl_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->sampl_rst)) {
+ dev_err(&pdev->dev, "get sampl_rst failed.\n");
-+ return PTR_ERR(hisi_priv->sampl_rst);;
++ return PTR_ERR(hisi_priv->sampl_rst);
+ }
+
+ hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
-+ if (IS_ERR(hisi_priv->crg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->crg_regmap)) {
+ dev_err(&pdev->dev, "get crg regmap failed.\n");
+ return PTR_ERR(hisi_priv->crg_regmap);
+ }
@@ -282957,20 +350936,23 @@ index 0000000..b4254a9
+ ret = sdhci_hisi_parse_dt(host);
+ if (ret)
+ return ret;
-+
-+ /* only eMMC has a hw reset, and now eMMC signaling
-+ * is fixed to 180*/
++ /*
++ * only eMMC has a hw reset, and now eMMC signaling
++ * is fixed to 180
++ */
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ host->flags &= ~SDHCI_SIGNALING_330;
+ host->flags |= SDHCI_SIGNALING_180;
+ }
+
-+ /* we parse the support timings from dts, so we read the
++ /*
++ * we parse the support timings from dts, so we read the
+ * host capabilities early and clear the timing capabilities,
+ * SDHCI_QUIRK_MISSING_CAPS is set so that sdhci driver would
-+ * not read it again */
++ * not read it again
++ */
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-+ host->caps &= ~(SDHCI_CAN_DO_HISPD);
++ host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
+ SDHCI_SUPPORT_DDR50 | SDHCI_CAN_DO_ADMA3);
@@ -282979,7 +350961,8 @@ index 0000000..b4254a9
+ SDHCI_QUIRK_SINGLE_POWER_WRITE;
+
+ host->caps1 |= SDHCI_USE_SDR50_TUNING;
-+ host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_hs400_enhanced_strobe;
++ host->mmc_host_ops.hs400_enhanced_strobe =
++ sdhci_hisi_hs400_enhanced_strobe;
+
+ mci_host[slot_index++] = host->mmc;
+
@@ -282989,7 +350972,8 @@ index 0000000..b4254a9
+static void hisi_wait_ds_dll_lock(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ unsigned int reg, timeout = 20;
++ unsigned int reg;
++ unsigned int timeout = 20; /* default timeout 20ms */
+
+ do {
+ reg = 0;
@@ -283006,31 +350990,28 @@ index 0000000..b4254a9
+
+static void hisi_wait_ds_180_dll_ready(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_set_ds_dll_delay(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
-+static int sdhci_hisi_start_signal_voltage_switch(struct sdhci_host *host,
-+ struct mmc_ios *ios)
++static int sdhci_hisi_start_signal_voltage_switch(struct sdhci_host *host, struct mmc_ios *ios)
+{
+ switch (ios->signal_voltage) {
-+ case MMC_SIGNAL_VOLTAGE_330:
-+ if (!(host->flags & SDHCI_SIGNALING_330))
-+ return -EINVAL;
-+ return hisi_set_signal_voltage_3v3(host);
-+ case MMC_SIGNAL_VOLTAGE_180:
-+ if (!(host->flags & SDHCI_SIGNALING_180))
-+ return -EINVAL;
-+ return hisi_set_signal_voltage_1v8(host);
-+ default:
-+ /* No signal voltage switch required */
-+ return 0;
++ case MMC_SIGNAL_VOLTAGE_330:
++ if (!(host->flags & SDHCI_SIGNALING_330))
++ return -EINVAL;
++ return hisi_set_signal_voltage_3v3(host);
++ case MMC_SIGNAL_VOLTAGE_180:
++ if (!(host->flags & SDHCI_SIGNALING_180))
++ return -EINVAL;
++ return hisi_set_signal_voltage_1v8(host);
++ default:
++ /* No signal voltage switch required */
++ return 0;
+ }
+}
+
@@ -283045,8 +351026,8 @@ index 0000000..b4254a9
+
+ mbiiu_ctrl = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
+ mbiiu_ctrl &= ~(SDHCI_GM_WR_OSRC_LMT_MASK | SDHCI_GM_RD_OSRC_LMT_MASK);
-+ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(7)
-+ | SDHCI_GM_RD_OSRC_LMT_SEL(7));
++ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) | /* set write outstanding 8 (lmt + 1) */
++ SDHCI_GM_RD_OSRC_LMT_SEL(0x7)); /* set read outstanding 8 (lmt + 1) */
+ sdhci_writel(host, mbiiu_ctrl, SDHCI_AXI_MBIIU_CTRL);
+
+ val = sdhci_readl(host, SDHCI_MULTI_CYCLE);
@@ -283059,7 +351040,7 @@ index 0000000..b4254a9
+static void hisi_set_sd_iocfg(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ unsigned int reg_addr;
+ unsigned int *pin_drv_cap = NULL;
+
@@ -283074,7 +351055,7 @@ index 0000000..b4254a9
+ pin_drv_cap = sd_other_drv;
+
+ for (reg_addr = REG_CTRL_SDIO0_CLK;
-+ reg_addr <= REG_CTRL_SDIO0_DATA3; reg_addr += 4) {
++ reg_addr <= REG_CTRL_SDIO0_DATA3; reg_addr += 0x4) {
+ regmap_write_bits(iocfg_regmap, reg_addr, 0xf0, *pin_drv_cap);
+ pin_drv_cap++;
+ }
@@ -283083,7 +351064,7 @@ index 0000000..b4254a9
+static void hisi_set_sdio_iocfg(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ unsigned int reg_addr;
+ unsigned int *pin_drv_cap = NULL;
+
@@ -283098,7 +351079,7 @@ index 0000000..b4254a9
+ pin_drv_cap = sdio_other_drv;
+
+ for (reg_addr = REG_CTRL_SDIO1_CLK;
-+ reg_addr <= REG_CTRL_SDIO1_DATA3; reg_addr += 4) {
++ reg_addr <= REG_CTRL_SDIO1_DATA3; reg_addr += 0x4) {
+ regmap_write_bits(iocfg_regmap, reg_addr, 0xf0, *pin_drv_cap);
+ pin_drv_cap++;
+ }
@@ -283108,7 +351089,7 @@ index 0000000..b4254a9
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ void* phy_addr = hisi_priv->phy_addr;
++ void *phy_addr = hisi_priv->phy_addr;
+ unsigned short reg;
+
+ if (devid == 0) {
@@ -283136,27 +351117,27 @@ index 0000000..b4254a9
+
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
+ host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
-+ hisi_priv->drv_phase = 8; /* 90 degree */
++ hisi_priv->drv_phase = 8; /* 8 for 90 degree */
+ else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
+ host->mmc->ios.timing == MMC_TIMING_UHS_SDR104)
-+ hisi_priv->drv_phase = 20; /* 225 degree */
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
+ else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
-+ hisi_priv->drv_phase = 9; /* 101.25 degree */
++ hisi_priv->drv_phase = 9; /* 9 for 101.25 degree */
+ else
-+ hisi_priv->drv_phase = 16; /* 180 degree */
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
+
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
+ host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
+ else if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
-+ hisi_priv->sampl_phase = 20;
++ hisi_priv->sampl_phase = 20; /* 20 for 225 degree */
+ else if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
+ host->mmc->ios.timing == MMC_TIMING_UHS_SDR25 ||
+ host->mmc->ios.timing == MMC_TIMING_SD_HS ||
+ host->mmc->ios.timing == MMC_TIMING_MMC_HS)
-+ hisi_priv->sampl_phase = 4;
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ else
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->sampl_phase = 0; /* 0 for 0 egree */
+}
+
+static int hisi_support_runtime_pm(struct sdhci_host *host)
@@ -283166,10 +351147,10 @@ index 0000000..b4254a9
+}
diff --git a/drivers/mmc/host/sdhci-hi3559av100.c b/drivers/mmc/host/sdhci-hi3559av100.c
new file mode 100644
-index 0000000..af9003b
+index 0000000..d7a7b71
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hi3559av100.c
-@@ -0,0 +1,496 @@
+@@ -0,0 +1,497 @@
+/*
+ * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
+ *
@@ -283192,7 +351173,7 @@ index 0000000..af9003b
+#define REG_SDIO1_DRV_DLL_CTRL 0x1fc
+#define REG_SDIO2_DRV_DLL_CTRL 0x224
+#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
-+#define SDIO_DRV_SEL(phase) ((phase) << 24)
++#define sdio_drv_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DRV_DLL_STATUS 0x1c4
+#define REG_SDIO0_DRV_DLL_STATUS 0x1e8
@@ -283217,16 +351198,16 @@ index 0000000..af9003b
+#define REG_SDIO1_SAMPLB_DLL_CTRL 0x1f8
+#define REG_SDIO2_SAMPLB_DLL_CTRL 0x220
+#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 24)
-+#define SDIO_SAMPLB_SEL(phase) ((phase) << 24)
++#define sdio_samplb_sel(phase) ((phase) << 24)
+
+#define REG_EMMC_DS_DLL_CTRL 0x1b4
+#define EMMC_DS_DLL_MODE_SSEL BIT(13)
-+#define EMMC_DS_DLL_SSEL_MASK (0x1fff)
++#define EMMC_DS_DLL_SSEL_MASK 0x1fff
+#define REG_EMMC_DS180_DLL_CTRL 0x1b8
+#define EMMC_DS180_DLL_BYPASS BIT(15)
+#define REG_EMMC_DS_DLL_STATUS 0x1c8
+#define EMMC_DS_DLL_LOCK BIT(15)
-+#define EMMC_DS_DLL_MDLY_TAP_MASK (0x1fff)
++#define EMMC_DS_DLL_MDLY_TAP_MASK 0x1fff
+
+#define REG_MISC_CTRL3 0xc
+#define SDIO2_PD_MUX_BYPASS BIT(10)
@@ -283272,9 +351253,9 @@ index 0000000..af9003b
+ REG_CTRL_SDIO2_DATA3
+};
+
-+static unsigned int sdr104_drv[] = {0x60, 0x60, 0x60, 0x60, 0x60, 0x60};
-+static unsigned int sdrxx_drv[] = {0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
-+static unsigned int hs_ds_drv[] = {0x70, 0x40, 0x40, 0x40, 0x40, 0x40};
++static unsigned int sdr104_drv[] = { 0x60, 0x60, 0x60, 0x60, 0x60, 0x60 };
++static unsigned int sdrxx_drv[] = { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40 };
++static unsigned int hs_ds_drv[] = { 0x70, 0x40, 0x40, 0x40, 0x40, 0x40 };
+
+struct sdhci_hisi_priv {
+ struct reset_control *crg_rst;
@@ -283310,7 +351291,7 @@ index 0000000..af9003b
+ unsigned int ctrl;
+
+ /* sdio2: it is fixed to 1v8, so we fake that 3v3 is ok */
-+ if (hisi_priv->devid == 3)
++ if (hisi_priv->devid == 3) /* device id 3 for sdio2 */
+ return 0;
+
+ pr_debug("%s: set voltage to 330\n", mmc_hostname(host->mmc));
@@ -283321,7 +351302,7 @@ index 0000000..af9003b
+ ctrl &= ~SDIO0_IO_MODE_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
+
-+ usleep_range(1000, 2000);
++ usleep_range(1000, 2000); /* Sleep between 1000 and 2000us */
+ ctrl &= ~SDIO0_PWRSW_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
+
@@ -283333,7 +351314,7 @@ index 0000000..af9003b
+ return 0;
+ }
+
-+ if (hisi_priv->devid == 2) {
++ if (hisi_priv->devid == 2) { /* device id 2 for sdio1 */
+ regmap_read(misc, REG_MISC_CTRL18, &ctrl);
+ ctrl &= ~SDIO1_IO_MODE_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
@@ -283357,7 +351338,7 @@ index 0000000..af9003b
+
+ pr_debug("%s: set voltage to 180\n", mmc_hostname(host->mmc));
+
-+ if (hisi_priv->devid == 0 || hisi_priv->devid == 3)
++ if (hisi_priv->devid == 0 || hisi_priv->devid == 3) /* for device id 0 and 3 */
+ return 0;
+
+ if (hisi_priv->devid == 1) {
@@ -283365,7 +351346,7 @@ index 0000000..af9003b
+ ctrl |= SDIO0_PWRSW_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
+
-+ usleep_range(1000, 2000);
++ usleep_range(1000, 2000); /* Sleep between 1000 and 2000us */
+
+ ctrl |= SDIO0_IO_MODE_SEL_1V8;
+ regmap_write(misc, REG_MISC_CTRL18, ctrl);
@@ -283381,8 +351362,7 @@ index 0000000..af9003b
+ return -EAGAIN;
+}
+
-+static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc,
-+ struct mmc_ios *ios)
++static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ u32 ctrl;
+ struct sdhci_host *host = mmc_priv(mmc);
@@ -283396,36 +351376,34 @@ index 0000000..af9003b
+ sdhci_writel(host, ctrl, SDHCI_EMMC_CTRL);
+}
+
-+static int sdhci_hisi_pltfm_init(struct platform_device *pdev,
-+ struct sdhci_host *host)
++static int sdhci_hisi_pltfm_init(struct platform_device *pdev, struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_hisi_priv *hisi_priv = sdhci_pltfm_priv(pltfm_host);
+ struct device_node *np = pdev->dev.of_node;
-+ struct clk *clk;
++ struct clk *clk = NULL;
+ int ret;
+
+ hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
+ dev_err(&pdev->dev, "get crg_rst failed.\n");
-+ return PTR_ERR(hisi_priv->crg_rst);;
++ return PTR_ERR(hisi_priv->crg_rst);
+ }
+
+ hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
+ dev_err(&pdev->dev, "get dll_rst failed.\n");
-+ return PTR_ERR(hisi_priv->dll_rst);;
++ return PTR_ERR(hisi_priv->dll_rst);
+ }
+
+ hisi_priv->sampl_rst = devm_reset_control_get(&pdev->dev, "sampl_reset");
+ if (IS_ERR_OR_NULL(hisi_priv->sampl_rst)) {
+ dev_err(&pdev->dev, "get sampl_rst failed.\n");
-+ return PTR_ERR(hisi_priv->sampl_rst);;
++ return PTR_ERR(hisi_priv->sampl_rst);
+ }
+
+ hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
-+ if (IS_ERR(hisi_priv->crg_regmap))
-+ {
++ if (IS_ERR(hisi_priv->crg_regmap)) {
+ dev_err(&pdev->dev, "get crg regmap failed.\n");
+ return PTR_ERR(hisi_priv->crg_regmap);
+ }
@@ -283470,19 +351448,23 @@ index 0000000..af9003b
+ if (ret)
+ return ret;
+
-+ /* only eMMC has a hw reset, and now eMMC signaling
-+ * is fixed to 180*/
++ /*
++ * only eMMC has a hw reset, and now eMMC signaling
++ * is fixed to 180
++ */
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ host->flags &= ~SDHCI_SIGNALING_330;
+ host->flags |= SDHCI_SIGNALING_180;
+ }
+
-+ /* we parse the support timings from dts, so we read the
++ /*
++ * we parse the support timings from dts, so we read the
+ * host capabilities early and clear the timing capabilities,
+ * SDHCI_QUIRK_MISSING_CAPS is set so that sdhci driver would
-+ * not read it again */
++ * not read it again
++ */
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-+ host->caps &= ~(SDHCI_CAN_DO_HISPD);
++ host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
+ SDHCI_SUPPORT_DDR50 | SDHCI_CAN_DO_ADMA3);
@@ -283491,7 +351473,8 @@ index 0000000..af9003b
+ SDHCI_QUIRK_SINGLE_POWER_WRITE;
+
+ host->caps1 |= SDHCI_USE_SDR50_TUNING;
-+ host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_hs400_enhanced_strobe;
++ host->mmc_host_ops.hs400_enhanced_strobe =
++ sdhci_hisi_hs400_enhanced_strobe;
+
+ mci_host[slot_index++] = host->mmc;
+
@@ -283501,7 +351484,8 @@ index 0000000..af9003b
+static void hisi_wait_ds_dll_lock(struct sdhci_host *host)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
-+ unsigned int reg, timeout = 20;
++ unsigned int reg;
++ unsigned int timeout = 20; /* default timeout 20ms */
+
+ do {
+ reg = 0;
@@ -283518,8 +351502,7 @@ index 0000000..af9003b
+
+static void hisi_wait_ds_180_dll_ready(struct sdhci_host *host)
+{
-+ //Do nothing
-+ return;
++ /* Do nothing */
+}
+
+static void hisi_set_ds_dll_delay(struct sdhci_host *host)
@@ -283532,27 +351515,26 @@ index 0000000..af9003b
+
+ regmap_write_bits(hisi_priv->crg_regmap, REG_EMMC_DS_DLL_CTRL,
+ (EMMC_DS_DLL_SSEL_MASK | EMMC_DS_DLL_MODE_SSEL),
-+ ((mdly_tap / 4 + 12) | EMMC_DS_DLL_MODE_SSEL));
++ ((mdly_tap / 4 + 12) | EMMC_DS_DLL_MODE_SSEL)); /* devide 4 and plus 12 */
+
+ regmap_write_bits(hisi_priv->crg_regmap, REG_EMMC_DS180_DLL_CTRL,
+ EMMC_DS180_DLL_BYPASS, EMMC_DS180_DLL_BYPASS);
+}
+
-+static int sdhci_hisi_start_signal_voltage_switch(struct sdhci_host *host,
-+ struct mmc_ios *ios)
++static int sdhci_hisi_start_signal_voltage_switch(struct sdhci_host *host, struct mmc_ios *ios)
+{
+ switch (ios->signal_voltage) {
-+ case MMC_SIGNAL_VOLTAGE_330:
-+ if (!(host->flags & SDHCI_SIGNALING_330))
-+ return -EINVAL;
-+ return hisi_set_signal_voltage_3v3(host);
-+ case MMC_SIGNAL_VOLTAGE_180:
-+ if (!(host->flags & SDHCI_SIGNALING_180))
-+ return -EINVAL;
-+ return hisi_set_signal_voltage_1v8(host);
-+ default:
-+ /* No signal voltage switch required */
-+ return 0;
++ case MMC_SIGNAL_VOLTAGE_330:
++ if (!(host->flags & SDHCI_SIGNALING_330))
++ return -EINVAL;
++ return hisi_set_signal_voltage_3v3(host);
++ case MMC_SIGNAL_VOLTAGE_180:
++ if (!(host->flags & SDHCI_SIGNALING_180))
++ return -EINVAL;
++ return hisi_set_signal_voltage_1v8(host);
++ default:
++ /* No signal voltage switch required */
++ return 0;
+ }
+}
+
@@ -283567,8 +351549,8 @@ index 0000000..af9003b
+
+ mbiiu_ctrl = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
+ mbiiu_ctrl &= ~(SDHCI_GM_WR_OSRC_LMT_MASK | SDHCI_GM_RD_OSRC_LMT_MASK);
-+ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(3)
-+ | SDHCI_GM_RD_OSRC_LMT_SEL(3));
++ mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x3) | /* set write outstanding 4 (lmt + 1) */
++ SDHCI_GM_RD_OSRC_LMT_SEL(0x3)); /* set read outstanding 4 (lmt + 1) */
+ sdhci_writel(host, mbiiu_ctrl, SDHCI_AXI_MBIIU_CTRL);
+
+ val = sdhci_readl(host, SDHCI_MULTI_CYCLE);
@@ -283582,7 +351564,7 @@ index 0000000..af9003b
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ void* iocfg_regmap = hisi_priv->iocfg_regmap;
++ void *iocfg_regmap = hisi_priv->iocfg_regmap;
+ unsigned int reg_addr, start, end;
+ unsigned int *pin_drv_cap = NULL;
+
@@ -283595,10 +351577,10 @@ index 0000000..af9003b
+ else
+ pin_drv_cap = hs_ds_drv;
+
-+ if (devid == 3) {
++ if (devid == 3) { /* for device id 3 */
+ unsigned int i;
+
-+ for (i = 0; i < 6; i++) {
++ for (i = 0; i < 6; i++) { /* for 6 pins */
+ regmap_write_bits(iocfg_regmap, sdio2_iocfg_reg[i],
+ 0xf0, *pin_drv_cap);
+ pin_drv_cap++;
@@ -283609,7 +351591,7 @@ index 0000000..af9003b
+
+ start = devid == 1 ? REG_CTRL_SDIO0_CLK : REG_CTRL_SDIO1_CLK;
+ end = devid == 1 ? REG_CTRL_SDIO0_DATA3 : REG_CTRL_SDIO1_DATA3;
-+ for (reg_addr = start; reg_addr <= end; reg_addr += 4) {
++ for (reg_addr = start; reg_addr <= end; reg_addr += 0x4) {
+ regmap_write_bits(iocfg_regmap, reg_addr, 0xf0, *pin_drv_cap);
+ pin_drv_cap++;
+ }
@@ -283619,13 +351601,13 @@ index 0000000..af9003b
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ void* phy_addr = hisi_priv->phy_addr;
++ void *phy_addr = hisi_priv->phy_addr;
+ unsigned short reg;
+
+ if (devid == 0) {
-+ if (host->timing == MMC_TIMING_MMC_HS200
-+ || host->timing == MMC_TIMING_MMC_HS400
-+ || host->timing == MMC_TIMING_MMC_HS) {
++ if (host->timing == MMC_TIMING_MMC_HS200 ||
++ host->timing == MMC_TIMING_MMC_HS400 ||
++ host->timing == MMC_TIMING_MMC_HS) {
+ reg = sdhci_readw(host, SDHCI_EMMC_CTRL);
+ reg |= SDHCI_CARD_IS_EMMC;
+ sdhci_writew(host, reg, SDHCI_EMMC_CTRL);
@@ -283643,22 +351625,22 @@ index 0000000..af9003b
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+
-+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400
-+ || host->mmc->ios.timing == MMC_TIMING_MMC_DDR52
-+ || host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
-+ hisi_priv->drv_phase = 8; /*90 degree*/
++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
++ host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
++ host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
++ hisi_priv->drv_phase = 8; /* 8 for 90 degree */
+ else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
-+ hisi_priv->drv_phase = 20; /*225 degree*/
++ hisi_priv->drv_phase = 20; /* 20 for 225 degree */
+ else
-+ hisi_priv->drv_phase = 16; /*180 degree */
++ hisi_priv->drv_phase = 16; /* 16 for 180 degree */
+
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
+ hisi_priv->sampl_phase = hisi_priv->tuning_phase;
-+ else if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52
-+ || host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
-+ hisi_priv->sampl_phase = 4;
++ else if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
++ host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
++ hisi_priv->sampl_phase = 4; /* 4 for 45 degree */
+ else
-+ hisi_priv->sampl_phase = 0;
++ hisi_priv->sampl_phase = 0; /* 0 or 0 degree */
+}
+
+static int hisi_support_runtime_pm(struct sdhci_host *host)
@@ -283668,10 +351650,10 @@ index 0000000..af9003b
+}
diff --git a/drivers/mmc/host/sdhci-hisi.c b/drivers/mmc/host/sdhci-hisi.c
new file mode 100644
-index 0000000..9282041
+index 0000000..0cee84f
--- /dev/null
+++ b/drivers/mmc/host/sdhci-hisi.c
-@@ -0,0 +1,768 @@
+@@ -0,0 +1,789 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -283702,15 +351684,15 @@ index 0000000..9282041
+#include "mci_proc.h"
+
+#define PHASE_SCALE 32
-+#define NOT_FOUND -1
++#define EDGE_TUNING_PHASE_STEP 4
++#define NOT_FOUND (-1)
+#define MAX_TUNING_NUM 1
+#define MAX_FREQ 200000000
+
+#define HISI_MMC_AUTOSUSPEND_DELAY_MS 50
+
+static void hisi_mmc_crg_init(struct sdhci_host *host);
-+static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc,
-+ struct mmc_ios *ios);
++static void sdhci_hisi_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios);
+static int sdhci_hisi_parse_dt(struct sdhci_host *host);
+
+static inline void *sdhci_get_pltfm_priv(struct sdhci_host *host)
@@ -283718,7 +351700,7 @@ index 0000000..9282041
+ return sdhci_pltfm_priv(sdhci_priv(host));
+}
+
-+#ifdef CONFIG_ARCH_HI3559AV100
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+#include "sdhci-hi3559av100.c"
+#endif
+
@@ -283784,29 +351766,30 @@ index 0000000..9282041
+ clk_prepare_enable(pltfm_host->clk);
+ reset_control_assert(hisi_priv->crg_rst);
+ reset_control_assert(hisi_priv->dll_rst);
-+ if(hisi_priv->sampl_rst)
++ if (hisi_priv->sampl_rst)
+ reset_control_assert(hisi_priv->sampl_rst);
+
-+ udelay(25);
++ udelay(25); /* delay 25us */
+ reset_control_deassert(hisi_priv->crg_rst);
-+ udelay(10);
++ udelay(10); /* delay 10us */
+}
+
+static void hisi_set_drv_phase(struct sdhci_host *host, unsigned int phase)
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ unsigned int offset[4] = {REG_EMMC_DRV_DLL_CTRL,
-+ REG_SDIO0_DRV_DLL_CTRL,
-+ REG_SDIO1_DRV_DLL_CTRL,
-+ REG_SDIO2_DRV_DLL_CTRL};
++ unsigned int offset[] = {
++ REG_EMMC_DRV_DLL_CTRL,
++ REG_SDIO0_DRV_DLL_CTRL,
++ REG_SDIO1_DRV_DLL_CTRL,
++ REG_SDIO2_DRV_DLL_CTRL
++ };
+
+ regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
-+ SDIO_DRV_PHASE_SEL_MASK, SDIO_DRV_SEL(phase));
++ SDIO_DRV_PHASE_SEL_MASK, sdio_drv_sel(phase));
+}
+
-+static void hisi_set_sampl_phase(struct sdhci_host *host,
-+ unsigned int phase)
++static void hisi_set_sampl_phase(struct sdhci_host *host, unsigned int phase)
+{
+ unsigned int reg;
+
@@ -283847,10 +351830,12 @@ index 0000000..9282041
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ unsigned int offset[4] = {REG_EMMC_SAMPL_DLL_CTRL,
-+ REG_SDIO0_SAMPL_DLL_CTRL,
-+ REG_SDIO1_SAMPL_DLL_CTRL,
-+ REG_SDIO2_SAMPL_DLL_CTRL};
++ unsigned int offset[] = {
++ REG_EMMC_SAMPL_DLL_CTRL,
++ REG_SDIO0_SAMPL_DLL_CTRL,
++ REG_SDIO1_SAMPL_DLL_CTRL,
++ REG_SDIO2_SAMPL_DLL_CTRL
++ };
+
+ regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
+ SDIO_SAMPL_DLL_SLAVE_EN, SDIO_SAMPL_DLL_SLAVE_EN);
@@ -283860,11 +351845,14 @@ index 0000000..9282041
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ unsigned int reg, timeout = 20;
-+ unsigned int offset[4] = {REG_EMMC_DRV_DLL_STATUS,
-+ REG_SDIO0_DRV_DLL_STATUS,
-+ REG_SDIO1_DRV_DLL_STATUS,
-+ REG_SDIO2_DRV_DLL_STATUS};
++ unsigned int reg;
++ unsigned int timeout = 20;
++ unsigned int offset[] = {
++ REG_EMMC_DRV_DLL_STATUS,
++ REG_SDIO0_DRV_DLL_STATUS,
++ REG_SDIO1_DRV_DLL_STATUS,
++ REG_SDIO2_DRV_DLL_STATUS
++ };
+
+ do {
+ reg = 0;
@@ -283883,11 +351871,14 @@ index 0000000..9282041
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ unsigned int reg, timeout = 20;
-+ unsigned int offset[4] = {REG_EMMC_SAMPL_DLL_STATUS,
-+ REG_SDIO0_SAMPL_DLL_STATUS,
-+ REG_SDIO1_SAMPL_DLL_STATUS,
-+ REG_SDIO2_SAMPL_DLL_STATUS};
++ unsigned int reg;
++ unsigned int timeout = 20;
++ unsigned int offset[] = {
++ REG_EMMC_SAMPL_DLL_STATUS,
++ REG_SDIO0_SAMPL_DLL_STATUS,
++ REG_SDIO1_SAMPL_DLL_STATUS,
++ REG_SDIO2_SAMPL_DLL_STATUS
++ };
+
+ do {
+ reg = 0;
@@ -283916,19 +351907,19 @@ index 0000000..9282041
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_hisi_priv *hisi_priv = sdhci_pltfm_priv(pltfm_host);
+ unsigned long timeout;
-+ u16 clk = 0;
++ u16 clk;
+
+ host->mmc->actual_clock = 0;
+ hisi_disable_card_clk(host);
-+ udelay(25);
++ udelay(25); /* delay 25us */
+ hisi_disable_inter_clk(host);
+ if (clock == 0)
+ return;
+
+ reset_control_assert(hisi_priv->dll_rst);
-+ if(hisi_priv->sampl_rst)
++ if (hisi_priv->sampl_rst)
+ reset_control_assert(hisi_priv->sampl_rst);
-+ udelay(25);
++ udelay(25); /* delay 25us */
+
+ clk_set_rate(pltfm_host->clk, clock);
+ host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
@@ -283937,24 +351928,25 @@ index 0000000..9282041
+ hisi_set_drv_phase(host, hisi_priv->drv_phase);
+ hisi_enable_sample(host);
+ hisi_set_sampl_phase(host, hisi_priv->sampl_phase);
-+ udelay(25);
++ udelay(25); /* delay 25us */
+
+ if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
+ hisi_enable_sampl_dll_slave(host);
+ reset_control_deassert(hisi_priv->dll_rst);
-+ if(hisi_priv->sampl_rst)
++ if (hisi_priv->sampl_rst)
+ reset_control_deassert(hisi_priv->sampl_rst);
+ }
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_PLL_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+ timeout = 20;
-+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
-+ & SDHCI_CLOCK_INT_STABLE)) {
++ timeout = 20; /* default timeout 20ms */
++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
++ while (!(clk & SDHCI_CLOCK_INT_STABLE)) {
++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ if (timeout == 0) {
-+ pr_err("%s: Internal clock never "
-+ "stabilised.\n", mmc_hostname(host->mmc));
++ pr_err("%s: Internal clock never stabilised.\n",
++ mmc_hostname(host->mmc));
+ return;
+ }
+ timeout--;
@@ -283966,13 +351958,12 @@ index 0000000..9282041
+ hisi_wait_sampl_dll_slave_ready(host);
+ }
+
-+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
+ hisi_wait_ds_180_dll_ready(host);
-+ }
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+ udelay(100);
++ udelay(100); /* delay 100us */
+
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
+ hisi_wait_ds_dll_lock(host);
@@ -283980,8 +351971,7 @@ index 0000000..9282041
+ }
+}
+
-+static void hisi_select_sampl_phase(struct sdhci_host *host,
-+ unsigned int phase)
++static void hisi_select_sampl_phase(struct sdhci_host *host, unsigned int phase)
+{
+ hisi_disable_card_clk(host);
+ hisi_set_sampl_phase(host, phase);
@@ -284009,7 +351999,8 @@ index 0000000..9282041
+static void hisi_pre_tuning(struct sdhci_host *host)
+{
+ sdhci_writel(host, host->ier | SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
-+ sdhci_writel(host, host->ier | SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
++ sdhci_writel(host, host->ier | SDHCI_INT_DATA_AVAIL,
++ SDHCI_SIGNAL_ENABLE);
+
+ hisi_wait_drv_dll_lock(host);
+ hisi_enable_sampl_dll_slave(host);
@@ -284033,14 +352024,18 @@ index 0000000..9282041
+#ifndef SDHCI_HISI_EDGE_TUNING
+static int hisi_get_best_sampl(u32 candidates)
+{
-+ int rise = NOT_FOUND, fall = NOT_FOUND;
-+ int win_max_r = NOT_FOUND, win_max_f = NOT_FOUND;
-+ int end_fall = NOT_FOUND, found = NOT_FOUND;
-+ int i, win, win_max = 0;
++ int rise = NOT_FOUND;
++ int fall = NOT_FOUND;
++ int win_max_r = NOT_FOUND;
++ int win_max_f = NOT_FOUND;
++ int end_fall = NOT_FOUND;
++ int found = NOT_FOUND;
++ int win_max = 0;
++ int i, win;
+
-+ for (i = 0; i < 32; i++) {
++ for (i = 0; i < PHASE_SCALE; i++) {
+ if ((candidates & 0x3) == 0x2)
-+ rise = (i + 1) % 32;
++ rise = (i + 1) % PHASE_SCALE;
+
+ if ((candidates & 0x3) == 0x1) {
+ fall = i;
@@ -284048,14 +352043,15 @@ index 0000000..9282041
+ win = fall - rise + 1;
+ if (win > win_max) {
+ win_max = win;
-+ found = (fall + rise) / 2;
++ found = (fall + rise) / 2; /* Get window center by devide 2 */
+ win_max_r = rise;
+ win_max_f = fall;
+ rise = NOT_FOUND;
+ fall = NOT_FOUND;
+ }
-+ } else
++ } else {
+ end_fall = fall;
++ }
+ }
+ candidates = ror32(candidates, 1);
+ }
@@ -284063,18 +352059,18 @@ index 0000000..9282041
+ if (end_fall != NOT_FOUND && rise != NOT_FOUND) {
+ fall = end_fall;
+ if (end_fall < rise)
-+ end_fall += 32;
++ end_fall += PHASE_SCALE;
+
+ win = end_fall - rise + 1;
+ if (win > win_max) {
-+ found = (rise + (win / 2)) % 32;
++ found = (rise + (win / 2)) % PHASE_SCALE; /* Get window center by devide 2 */
+ win_max_r = rise;
+ win_max_f = fall;
+ }
+ }
+
+ if (found != NOT_FOUND)
-+ printk("valid phase shift [%d, %d] Final Phase:%d\n",
++ pr_info("valid phase shift [%d, %d] Final Phase:%d\n",
+ win_max_r, win_max_f, found);
+
+ return found;
@@ -284106,7 +352102,7 @@ index 0000000..9282041
+ phase = hisi_get_best_sampl(candidates);
+ if (phase == NOT_FOUND) {
+ phase = hisi_priv->sampl_phase;
-+ printk("no valid phase shift! use default %d\n", phase);
++ pr_err("no valid phase shift! use default %d\n", phase);
+ }
+
+ hisi_priv->tuning_phase = phase;
@@ -284121,14 +352117,16 @@ index 0000000..9282041
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int devid = hisi_priv->devid;
-+ unsigned int samplb_offset[4] = {REG_EMMC_SAMPLB_DLL_CTRL,
-+ REG_SDIO0_SAMPLB_DLL_CTRL,
-+ REG_SDIO1_SAMPLB_DLL_CTRL,
-+ REG_SDIO2_SAMPLB_DLL_CTRL};
++ unsigned int samplb_offset[] = {
++ REG_EMMC_SAMPLB_DLL_CTRL,
++ REG_SDIO0_SAMPLB_DLL_CTRL,
++ REG_SDIO1_SAMPLB_DLL_CTRL,
++ REG_SDIO2_SAMPLB_DLL_CTRL
++ };
+ unsigned int reg;
+
+ regmap_write_bits(hisi_priv->crg_regmap, samplb_offset[devid],
-+ SDIO_SAMPLB_DLL_CLK_MASK, SDIO_SAMPLB_SEL(8));
++ SDIO_SAMPLB_DLL_CLK_MASK, sdio_samplb_sel(8)); /* 8 for 180 degree */
+
+ reg = sdhci_readl(host, SDHCI_MULTI_CYCLE);
+ reg |= SDHCI_EDGE_DETECT_EN;
@@ -284148,29 +352146,31 @@ index 0000000..9282041
+{
+ struct sdhci_hisi_priv *hisi_priv = sdhci_get_pltfm_priv(host);
+ unsigned int index, val;
-+ unsigned int found = 0, prev_found = 0;
-+ unsigned int edge_p2f, edge_f2p, start, end;
-+ unsigned int phase, fall = NOT_FOUND, rise = NOT_FOUND;
-+ unsigned int fall_updat_flag = 0;
-+ int err, prev_err = 0;
++ unsigned int edge_p2f, edge_f2p, start, end, phase;
++ unsigned int fall, rise, fall_updat_flag;
++ unsigned int found = 0;
++ unsigned int prev_found = 0;
++ int prev_err = 0;
++ int err;
+
+ hisi_pre_tuning(host);
+ hisi_enable_edge_tuning(host);
+
+ start = 0;
-+ end = PHASE_SCALE / 4;
++ end = PHASE_SCALE / EDGE_TUNING_PHASE_STEP;
+
+ edge_p2f = start;
+ edge_f2p = end;
+ for (index = 0; index <= end; index++) {
-+ hisi_select_sampl_phase(host, index * 4);
++ hisi_select_sampl_phase(host, index * EDGE_TUNING_PHASE_STEP);
+
+ err = mmc_send_tuning(host->mmc, opcode, NULL);
+ if (!err) {
+ val = sdhci_readl(host, SDHCI_MULTI_CYCLE);
+ found = val & SDHCI_FOUND_EDGE;
-+ } else
++ } else {
+ found = 1;
++ }
+
+ if (prev_found && !found)
+ edge_f2p = index;
@@ -284192,8 +352192,8 @@ index 0000000..9282041
+
+ hisi_disable_edge_tuning(host);
+
-+ start = edge_p2f * 4;
-+ end = edge_f2p * 4;
++ start = edge_p2f * EDGE_TUNING_PHASE_STEP;
++ end = edge_f2p * EDGE_TUNING_PHASE_STEP;
+ if (end <= start)
+ end += PHASE_SCALE;
+
@@ -284223,9 +352223,8 @@ index 0000000..9282041
+ }
+
+
-+ if (prev_err && !err) {
++ if (prev_err && !err)
+ rise = index;
-+ }
+
+ if (err && index == end)
+ rise = end;
@@ -284234,7 +352233,7 @@ index 0000000..9282041
+ prev_err = err;
+ }
+
-+ phase = ((fall + rise) / 2 + 16) % PHASE_SCALE;
++ phase = ((fall + rise) / 2 + PHASE_SCALE / 2) % PHASE_SCALE; /* Get window center by divide 2 */
+
+ pr_info("%s: tuning done! valid phase shift [%d, %d] Final Phase:%d\n",
+ mmc_hostname(host->mmc), rise % PHASE_SCALE,
@@ -284260,13 +352259,15 @@ index 0000000..9282041
+static void sdhci_hisi_hw_reset(struct sdhci_host *host)
+{
+ sdhci_writel(host, 0x0, SDHCI_EMMC_HW_RESET);
-+ udelay(10);
++ udelay(10); /* delay 10us */
+ sdhci_writel(host, 0x1, SDHCI_EMMC_HW_RESET);
-+ udelay(200);
++ udelay(200); /* delay 200us */
+}
+
-+/* This api is for wifi driver rescan the sdio device,
-+ * ugly but it is needed */
++/*
++ * This api is for wifi driver rescan the sdio device,
++ * ugly but it is needed
++ */
+int hisi_sdio_rescan(int slot)
+{
+ struct mmc_host *mmc = mci_host[slot];
@@ -284288,7 +352289,8 @@ index 0000000..9282041
+ .reset = sdhci_reset,
+ .set_uhs_signaling = sdhci_hisi_set_uhs_signaling,
+ .hw_reset = sdhci_hisi_hw_reset,
-+#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3519AV100)
++#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3559AV100) || \
++ defined(CONFIG_ARCH_HI3519AV100) || defined(CONFIG_ARCH_HI3569V100)
+ .start_signal_voltage_switch =
+ sdhci_hisi_start_signal_voltage_switch,
+#endif
@@ -284312,7 +352314,7 @@ index 0000000..9282041
+static int sdhci_hisi_probe(struct platform_device *pdev)
+{
+ struct sdhci_host *host;
-+ struct sdhci_pltfm_host *pltfm_host;
++ struct sdhci_pltfm_host *pltfm_host = NULL;
+ int ret;
+
+ host = sdhci_pltfm_init(pdev, &sdhci_hisi_pdata,
@@ -284326,7 +352328,8 @@ index 0000000..9282041
+
+ if (hisi_support_runtime_pm(host)) {
+ pm_runtime_get_noresume(&pdev->dev);
-+ pm_runtime_set_autosuspend_delay(&pdev->dev, HISI_MMC_AUTOSUSPEND_DELAY_MS);
++ pm_runtime_set_autosuspend_delay(&pdev->dev,
++ HISI_MMC_AUTOSUSPEND_DELAY_MS);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
@@ -284388,8 +352391,8 @@ index 0000000..9282041
+#endif
+
+static const struct of_device_id sdhci_hisi_match[] = {
-+ { .compatible = "hisi-sdhci" },
-+ { }
++ { .compatible = "hisi-sdhci" },
++ { }
+};
+MODULE_DEVICE_TABLE(of, sdhci_hisi_match);
+
@@ -284482,7 +352485,7 @@ index 3280f20..c205b1b 100644
#endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
-index 7d275e7..b5e6cdf 100644
+index 7d275e7..0485259 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -32,6 +32,7 @@
@@ -284531,7 +352534,7 @@ index 7d275e7..b5e6cdf 100644
sdhci_init(host, 0);
sdhci_enable_card_detection(host);
}
-@@ -522,6 +529,58 @@ static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
+@@ -522,6 +529,60 @@ static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
}
@@ -284573,12 +352576,14 @@ index 7d275e7..b5e6cdf 100644
+
+ sdhci_write_cmd_table(host->cmd_table, data->blocks, ADMA3_CMD_VALID);
+ sdhci_write_cmd_table(host->cmd_table + 0x8, blksz, ADMA3_CMD_VALID);
-+ sdhci_write_cmd_table(host->cmd_table + 0x10, cmd->arg, ADMA3_CMD_VALID);
-+ sdhci_write_cmd_table(host->cmd_table + 0x18, cmd_xfer, ADMA3_CMD_VALID);
++ sdhci_write_cmd_table(host->cmd_table + 0x10,
++ cmd->arg, ADMA3_CMD_VALID);
++ sdhci_write_cmd_table(host->cmd_table + 0x18,
++ cmd_xfer, ADMA3_CMD_VALID);
+ sdhci_adma_write_desc(host, host->cmd_table + 0x20,
+ host->adma_addr, 0x0, ADMA2_LINK_VALID);
-+
-+ sdhci_write_adma3_desc(host, host->adma3_table, host->cmd_addr, ADMA3_END);
++ sdhci_write_adma3_desc(host, host->adma3_table,
++ host->cmd_addr, ADMA3_END);
+
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl_2 |= SDHCI_CTRL_HOST_VER4_ENABLE;
@@ -284590,7 +352595,7 @@ index 7d275e7..b5e6cdf 100644
static void sdhci_adma_mark_end(void *desc)
{
struct sdhci_adma2_64_desc *dma_desc = desc;
-@@ -589,6 +648,17 @@ static void sdhci_adma_table_pre(struct sdhci_host *host,
+@@ -589,6 +650,17 @@ static void sdhci_adma_table_pre(struct sdhci_host *host,
BUG_ON(len > 65536);
if (len) {
@@ -284608,7 +352613,7 @@ index 7d275e7..b5e6cdf 100644
/* tran, valid */
sdhci_adma_write_desc(host, desc, addr, len,
ADMA2_TRAN_VALID);
-@@ -855,10 +925,14 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
+@@ -855,10 +927,14 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ctrl &= ~SDHCI_CTRL_DMA_MASK;
if ((host->flags & SDHCI_REQ_USE_DMA) &&
(host->flags & SDHCI_USE_ADMA)) {
@@ -284616,9 +352621,9 @@ index 7d275e7..b5e6cdf 100644
- ctrl |= SDHCI_CTRL_ADMA64;
- else
- ctrl |= SDHCI_CTRL_ADMA32;
-+ if (host->flags & SDHCI_USE_ADMA3)
++ if (host->flags & SDHCI_USE_ADMA3) {
+ ctrl |= SDHCI_CTRL_ADMA3;
-+ else {
++ } else {
+ if (host->flags & SDHCI_USE_64_BIT_DMA)
+ ctrl |= SDHCI_CTRL_ADMA64;
+ else
@@ -284627,7 +352632,7 @@ index 7d275e7..b5e6cdf 100644
} else {
ctrl |= SDHCI_CTRL_SDMA;
}
-@@ -1121,7 +1195,8 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
+@@ -1121,7 +1197,8 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
sdhci_prepare_data(host, cmd);
@@ -284637,7 +352642,7 @@ index 7d275e7..b5e6cdf 100644
sdhci_set_transfer_mode(host, cmd);
-@@ -1152,10 +1227,26 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
+@@ -1152,10 +1229,29 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA;
@@ -284645,12 +352650,15 @@ index 7d275e7..b5e6cdf 100644
+ if (host->flags & SDHCI_USE_ADMA3 && cmd->data) {
+ sdhci_prep_adma3_desc(host, cmd, flags);
+
-+ sdhci_writel(host, (u32)host->adma3_addr, SDHCI_ADMA3_ID_ADDR_LOW);
++ sdhci_writel(host, (u32)host->adma3_addr,
++ SDHCI_ADMA3_ID_ADDR_LOW);
+ if (host->flags & SDHCI_USE_64_BIT_DMA)
+ sdhci_writel(host, (u32)((u64)host->adma3_addr >> 32),
+ SDHCI_ADMA3_ID_ADDR_HI);
-+ } else
-+ sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
++ } else {
++ sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags),
++ SDHCI_COMMAND);
++ }
}
EXPORT_SYMBOL_GPL(sdhci_send_command);
@@ -284665,29 +352673,23 @@ index 7d275e7..b5e6cdf 100644
static void sdhci_finish_command(struct sdhci_host *host)
{
struct mmc_command *cmd = host->cmd;
-@@ -1177,6 +1268,21 @@ static void sdhci_finish_command(struct sdhci_host *host)
+@@ -1177,6 +1273,15 @@ static void sdhci_finish_command(struct sdhci_host *host)
} else {
cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
}
+
+ if (((cmd->flags & MMC_RSP_R1) == MMC_RSP_R1) &&
+ ((cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)) {
-+ if((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning){
++ if ((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning) {
+ host->error_count++;
-+ /* The return code EACCES is returned to enable core.c to exit the loop of sending requests. */
-+ if (cmd->resp[0] & R1_WP_VIOLATION) {
-+ cmd->error = -EACCES;
-+ } else {
-+ /* FIXME: Subsequent processing of other error codes */
-+ pr_warn_once("command error, cmd->resp[0]: %x \n",cmd->resp[0]);
-+ }
-+
++ cmd->mrq->cmd->error = -EACCES;
++ pr_err("The status of the card is abnormal, cmd->resp[0]: %x", cmd->resp[0]);
+ }
+ }
}
if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
-@@ -1430,6 +1536,12 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
+@@ -1430,6 +1535,12 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
sdhci_runtime_pm_bus_off(host);
@@ -284695,12 +352697,26 @@ index 7d275e7..b5e6cdf 100644
+ * Controllers need an extra 100ms delay to ensure power off
+ * completely
+ */
-+ mdelay(100);
++ msleep(100);
+
} else {
/*
* Spec says that we should clear the power reg before setting
-@@ -1710,7 +1822,9 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+@@ -1568,13 +1679,9 @@ EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
+ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ {
+ struct sdhci_host *host = mmc_priv(mmc);
+- unsigned long flags;
+ u8 ctrl;
+
+- spin_lock_irqsave(&host->lock, flags);
+-
+ if (host->flags & SDHCI_DEVICE_DEAD) {
+- spin_unlock_irqrestore(&host->lock, flags);
+ if (!IS_ERR(mmc->supply.vmmc) &&
+ ios->power_mode == MMC_POWER_OFF)
+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
+@@ -1710,7 +1817,9 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
}
/* Re-enable SD Clock */
@@ -284711,7 +352727,15 @@ index 7d275e7..b5e6cdf 100644
} else
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-@@ -1846,6 +1960,9 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+@@ -1723,7 +1832,6 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+ mmiowb();
+- spin_unlock_irqrestore(&host->lock, flags);
+ }
+
+ static int sdhci_get_cd(struct mmc_host *mmc)
+@@ -1846,6 +1954,9 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
u16 ctrl;
int ret;
@@ -284721,7 +352745,7 @@ index 7d275e7..b5e6cdf 100644
/*
* Signal Voltage Switching is only applicable for Host Controllers
* v3.00 and above.
-@@ -2281,6 +2398,33 @@ static void sdhci_card_event(struct mmc_host *mmc)
+@@ -2281,6 +2392,33 @@ static void sdhci_card_event(struct mmc_host *mmc)
spin_unlock_irqrestore(&host->lock, flags);
}
@@ -284755,7 +352779,7 @@ index 7d275e7..b5e6cdf 100644
static const struct mmc_host_ops sdhci_ops = {
.request = sdhci_request,
.post_req = sdhci_post_req,
-@@ -2296,6 +2440,7 @@ static const struct mmc_host_ops sdhci_ops = {
+@@ -2296,6 +2434,7 @@ static const struct mmc_host_ops sdhci_ops = {
.select_drive_strength = sdhci_select_drive_strength,
.card_event = sdhci_card_event,
.card_busy = sdhci_card_busy,
@@ -284763,7 +352787,7 @@ index 7d275e7..b5e6cdf 100644
};
/*****************************************************************************\
-@@ -2370,6 +2515,9 @@ static bool sdhci_request_done(struct sdhci_host *host)
+@@ -2370,6 +2509,9 @@ static bool sdhci_request_done(struct sdhci_host *host)
host->pending_reset = false;
}
@@ -284773,7 +352797,7 @@ index 7d275e7..b5e6cdf 100644
if (!sdhci_has_requests(host))
sdhci_led_deactivate(host);
-@@ -2460,17 +2608,31 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
+@@ -2460,17 +2602,32 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
*/
if (host->pending_reset)
return;
@@ -284783,13 +352807,14 @@ index 7d275e7..b5e6cdf 100644
mmc_hostname(host->mmc), (unsigned)intmask);
- sdhci_dumpregs(host);
+ sdhci_dumpregs(host);*/
-+
++
return;
}
if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
- SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
-+ SDHCI_INT_END_BIT | SDHCI_INT_INDEX | SDHCI_INT_ACMD_ERR)) {
++ SDHCI_INT_END_BIT | SDHCI_INT_INDEX |
++ SDHCI_INT_ACMD_ERR)) {
if (intmask & SDHCI_INT_TIMEOUT)
host->cmd->error = -ETIMEDOUT;
- else
@@ -284809,19 +352834,16 @@ index 7d275e7..b5e6cdf 100644
host->cmd->error = -EILSEQ;
/*
-@@ -2533,8 +2695,10 @@ static void sdhci_adma_show_error(struct sdhci_host *host) { }
+@@ -2533,6 +2690,8 @@ static void sdhci_adma_show_error(struct sdhci_host *host) { }
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
{
-- u32 command;
-
++
+#ifndef SDHCI_HISI_EDGE_TUNING
-+ u32 command;
-+
+ u32 command;
+
/* CMD19 generates _only_ Buffer Read Ready interrupt */
- if (intmask & SDHCI_INT_DATA_AVAIL) {
- command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
-@@ -2545,6 +2709,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
+@@ -2545,6 +2704,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
return;
}
}
@@ -284829,17 +352851,17 @@ index 7d275e7..b5e6cdf 100644
if (!host->data) {
struct mmc_command *data_cmd = host->data_cmd;
-@@ -2583,6 +2748,9 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
- */
+@@ -2584,6 +2744,9 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
if (host->pending_reset)
return;
-+
+
+ if (host->is_tuning)
+ return;
-
++
pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
mmc_hostname(host->mmc), (unsigned)intmask);
-@@ -2655,6 +2823,58 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
+ sdhci_dumpregs(host);
+@@ -2655,6 +2818,58 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
}
}
@@ -284898,7 +352920,7 @@ index 7d275e7..b5e6cdf 100644
static irqreturn_t sdhci_irq(int irq, void *dev_id)
{
irqreturn_t result = IRQ_NONE;
-@@ -2676,6 +2896,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
+@@ -2676,6 +2891,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
}
do {
@@ -284918,7 +352940,7 @@ index 7d275e7..b5e6cdf 100644
/* Clear selected interrupts. */
mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
SDHCI_INT_BUS_POWER);
-@@ -3093,7 +3326,7 @@ int sdhci_setup_host(struct sdhci_host *host)
+@@ -3093,7 +3321,7 @@ int sdhci_setup_host(struct sdhci_host *host)
override_timeout_clk = host->timeout_clk;
@@ -284927,7 +352949,7 @@ index 7d275e7..b5e6cdf 100644
pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
mmc_hostname(mmc), host->version);
}
-@@ -3121,6 +3354,15 @@ int sdhci_setup_host(struct sdhci_host *host)
+@@ -3121,6 +3349,15 @@ int sdhci_setup_host(struct sdhci_host *host)
host->flags &= ~SDHCI_USE_ADMA;
}
@@ -284943,7 +352965,7 @@ index 7d275e7..b5e6cdf 100644
/*
* It is assumed that a 64-bit capable device has set a 64-bit DMA mask
* and *must* do 64-bit DMA. A driver has the opportunity to change
-@@ -3161,14 +3403,14 @@ int sdhci_setup_host(struct sdhci_host *host)
+@@ -3161,14 +3398,14 @@ int sdhci_setup_host(struct sdhci_host *host)
* all multipled by the descriptor size.
*/
if (host->flags & SDHCI_USE_64_BIT_DMA) {
@@ -284965,7 +352987,7 @@ index 7d275e7..b5e6cdf 100644
host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
-@@ -3191,6 +3433,36 @@ int sdhci_setup_host(struct sdhci_host *host)
+@@ -3191,6 +3428,36 @@ int sdhci_setup_host(struct sdhci_host *host)
host->adma_table = buf + host->align_buffer_sz;
host->adma_addr = dma + host->align_buffer_sz;
}
@@ -285002,7 +353024,7 @@ index 7d275e7..b5e6cdf 100644
}
/*
-@@ -3557,10 +3829,165 @@ int sdhci_setup_host(struct sdhci_host *host)
+@@ -3557,10 +3824,165 @@ int sdhci_setup_host(struct sdhci_host *host)
host->adma_table = NULL;
host->align_buffer = NULL;
@@ -285168,7 +353190,7 @@ index 7d275e7..b5e6cdf 100644
int __sdhci_add_host(struct sdhci_host *host)
{
struct mmc_host *mmc = host->mmc;
-@@ -3605,11 +4032,25 @@ int __sdhci_add_host(struct sdhci_host *host)
+@@ -3605,11 +4027,25 @@ int __sdhci_add_host(struct sdhci_host *host)
if (ret)
goto unled;
@@ -285196,7 +353218,7 @@ index 7d275e7..b5e6cdf 100644
sdhci_enable_card_detection(host);
-@@ -3635,6 +4076,14 @@ int __sdhci_add_host(struct sdhci_host *host)
+@@ -3635,6 +4071,14 @@ int __sdhci_add_host(struct sdhci_host *host)
host->adma_table = NULL;
host->align_buffer = NULL;
@@ -285211,7 +353233,7 @@ index 7d275e7..b5e6cdf 100644
return ret;
}
EXPORT_SYMBOL_GPL(__sdhci_add_host);
-@@ -3672,6 +4121,8 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
+@@ -3672,6 +4116,8 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
sdhci_disable_card_detection(host);
@@ -285220,7 +353242,7 @@ index 7d275e7..b5e6cdf 100644
mmc_remove_host(mmc);
sdhci_led_unregister(host);
-@@ -3681,7 +4132,6 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
+@@ -3681,7 +4127,6 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
sdhci_writel(host, 0, SDHCI_INT_ENABLE);
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
@@ -285228,7 +353250,7 @@ index 7d275e7..b5e6cdf 100644
del_timer_sync(&host->timer);
del_timer_sync(&host->data_timer);
-@@ -3698,6 +4148,14 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
+@@ -3698,6 +4143,14 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
host->adma_table = NULL;
host->align_buffer = NULL;
@@ -285244,20 +353266,24 @@ index 7d275e7..b5e6cdf 100644
EXPORT_SYMBOL_GPL(sdhci_remove_host);
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
-index 2570455..864e2d1 100644
+index 2570455..de6a887 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
-@@ -20,6 +20,9 @@
+@@ -20,6 +20,13 @@
#include <linux/mmc/host.h>
+#ifndef CONFIG_ARCH_HI3559AV100
+#define SDHCI_HISI_EDGE_TUNING /* enable edge tuning */
++#endif
++
++#ifndef CONFIG_ARCH_HI3569V100
++#define SDHCI_HISI_EDGE_TUNING /* enable edge tuning */
+#endif
/*
* Controller registers
*/
-@@ -84,6 +87,7 @@
+@@ -84,6 +91,7 @@
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
@@ -285265,7 +353291,7 @@ index 2570455..864e2d1 100644
#define SDHCI_CTRL_8BITBUS 0x20
#define SDHCI_CTRL_CDTEST_INS 0x40
#define SDHCI_CTRL_CDTEST_EN 0x80
-@@ -108,6 +112,7 @@
+@@ -108,6 +116,7 @@
#define SDHCI_DIV_MASK_LEN 8
#define SDHCI_DIV_HI_MASK 0x300
#define SDHCI_PROG_CLOCK_MODE 0x0020
@@ -285273,7 +353299,7 @@ index 2570455..864e2d1 100644
#define SDHCI_CLOCK_CARD_EN 0x0004
#define SDHCI_CLOCK_INT_STABLE 0x0002
#define SDHCI_CLOCK_INT_EN 0x0001
-@@ -132,6 +137,7 @@
+@@ -132,6 +141,7 @@
#define SDHCI_INT_CARD_REMOVE 0x00000080
#define SDHCI_INT_CARD_INT 0x00000100
#define SDHCI_INT_RETUNE 0x00001000
@@ -285281,7 +353307,7 @@ index 2570455..864e2d1 100644
#define SDHCI_INT_ERROR 0x00008000
#define SDHCI_INT_TIMEOUT 0x00010000
#define SDHCI_INT_CRC 0x00020000
-@@ -141,14 +147,16 @@
+@@ -141,14 +151,16 @@
#define SDHCI_INT_DATA_CRC 0x00200000
#define SDHCI_INT_DATA_END_BIT 0x00400000
#define SDHCI_INT_BUS_POWER 0x00800000
@@ -285300,7 +353326,7 @@ index 2570455..864e2d1 100644
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
-@@ -156,7 +164,13 @@
+@@ -156,7 +168,13 @@
SDHCI_INT_BLK_GAP)
#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
@@ -285315,7 +353341,7 @@ index 2570455..864e2d1 100644
#define SDHCI_HOST_CONTROL2 0x3E
#define SDHCI_CTRL_UHS_MASK 0x0007
-@@ -165,7 +179,7 @@
+@@ -165,7 +183,7 @@
#define SDHCI_CTRL_UHS_SDR50 0x0002
#define SDHCI_CTRL_UHS_SDR104 0x0003
#define SDHCI_CTRL_UHS_DDR50 0x0004
@@ -285324,7 +353350,7 @@ index 2570455..864e2d1 100644
#define SDHCI_CTRL_VDD_180 0x0008
#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
#define SDHCI_CTRL_DRV_TYPE_B 0x0000
-@@ -174,6 +188,9 @@
+@@ -174,6 +192,9 @@
#define SDHCI_CTRL_DRV_TYPE_D 0x0030
#define SDHCI_CTRL_EXEC_TUNING 0x0040
#define SDHCI_CTRL_TUNED_CLK 0x0080
@@ -285334,7 +353360,7 @@ index 2570455..864e2d1 100644
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40
-@@ -195,6 +212,7 @@
+@@ -195,6 +216,7 @@
#define SDHCI_CAN_VDD_300 0x02000000
#define SDHCI_CAN_VDD_180 0x04000000
#define SDHCI_CAN_64BIT 0x10000000
@@ -285342,7 +353368,7 @@ index 2570455..864e2d1 100644
#define SDHCI_SUPPORT_SDR50 0x00000001
#define SDHCI_SUPPORT_SDR104 0x00000002
-@@ -209,6 +227,7 @@
+@@ -209,6 +231,7 @@
#define SDHCI_RETUNING_MODE_SHIFT 14
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
#define SDHCI_CLOCK_MUL_SHIFT 16
@@ -285350,7 +353376,7 @@ index 2570455..864e2d1 100644
#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
#define SDHCI_CAPABILITIES_1 0x44
-@@ -250,6 +269,9 @@
+@@ -250,6 +273,9 @@
#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
@@ -285360,7 +353386,7 @@ index 2570455..864e2d1 100644
#define SDHCI_SLOT_INT_STATUS 0xFC
#define SDHCI_HOST_VERSION 0xFE
-@@ -260,7 +282,38 @@
+@@ -260,7 +286,38 @@
#define SDHCI_SPEC_100 0
#define SDHCI_SPEC_200 1
#define SDHCI_SPEC_300 2
@@ -285400,7 +353426,7 @@ index 2570455..864e2d1 100644
/*
* End of controller registers.
*/
-@@ -273,6 +326,7 @@
+@@ -273,6 +330,7 @@
*/
#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
@@ -285408,7 +353434,7 @@ index 2570455..864e2d1 100644
/* ADMA2 32-bit DMA descriptor size */
#define SDHCI_ADMA2_32_DESC_SZ 8
-@@ -298,6 +352,12 @@ struct sdhci_adma2_32_desc {
+@@ -298,6 +356,12 @@ struct sdhci_adma2_32_desc {
/* ADMA2 64-bit DMA descriptor size */
#define SDHCI_ADMA2_64_DESC_SZ 12
@@ -285421,7 +353447,7 @@ index 2570455..864e2d1 100644
/*
* ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
* aligned.
-@@ -312,6 +372,9 @@ struct sdhci_adma2_64_desc {
+@@ -312,6 +376,9 @@ struct sdhci_adma2_64_desc {
#define ADMA2_TRAN_VALID 0x21
#define ADMA2_NOP_END_VALID 0x3
#define ADMA2_END 0x2
@@ -285431,7 +353457,7 @@ index 2570455..864e2d1 100644
/*
* Maximum segments assuming a 512KiB maximum requisition size and a minimum
-@@ -328,6 +391,18 @@ enum sdhci_cookie {
+@@ -328,6 +395,18 @@ enum sdhci_cookie {
COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
};
@@ -285450,7 +353476,7 @@ index 2570455..864e2d1 100644
struct sdhci_host {
/* Data set by hardware interface driver */
const char *hw_name; /* Hardware bus name */
-@@ -425,6 +500,7 @@ struct sdhci_host {
+@@ -425,6 +504,7 @@ struct sdhci_host {
#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
/* Broken Clock divider zero in controller */
#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
@@ -285458,7 +353484,7 @@ index 2570455..864e2d1 100644
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
-@@ -458,6 +534,8 @@ struct sdhci_host {
+@@ -458,6 +538,8 @@ struct sdhci_host {
#define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
#define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
#define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
@@ -285467,7 +353493,7 @@ index 2570455..864e2d1 100644
unsigned int version; /* SDHCI spec. version */
-@@ -486,14 +564,21 @@ struct sdhci_host {
+@@ -486,14 +568,21 @@ struct sdhci_host {
void *adma_table; /* ADMA descriptor table */
void *align_buffer; /* Bounce buffer */
@@ -285489,7 +353515,7 @@ index 2570455..864e2d1 100644
struct tasklet_struct finish_tasklet; /* Tasklet structures */
-@@ -525,6 +610,10 @@ struct sdhci_host {
+@@ -525,6 +614,10 @@ struct sdhci_host {
#define SDHCI_TUNING_MODE_2 1
#define SDHCI_TUNING_MODE_3 2
@@ -285500,7 +353526,7 @@ index 2570455..864e2d1 100644
unsigned long private[0] ____cacheline_aligned;
};
-@@ -564,6 +653,10 @@ struct sdhci_ops {
+@@ -564,6 +657,10 @@ struct sdhci_ops {
struct mmc_card *card,
unsigned int max_dtr, int host_drv,
int card_drv, int *drv_type);
@@ -285511,6 +353537,25 @@ index 2570455..864e2d1 100644
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+@@ -698,4 +795,18 @@ extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
+ extern int sdhci_runtime_resume_host(struct sdhci_host *host);
+ #endif
+
++#define UNSTUFF_BITS(resp,start,size) \
++ ({ \
++ const int __size = size; \
++ const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
++ const int __off = 3 - ((start) / 32); \
++ const int __shft = (start) & 31; \
++ u32 __res; \
++ \
++ __res = resp[__off] >> __shft; \
++ if (__size + __shft > 32) \
++ __res |= resp[__off-1] << ((32 - __shft) % 32); \
++ __res & __mask; \
++ })
++
+ #endif /* __SDHCI_HW_H */
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 99bb9a1..f46b1cc 100644
--- a/drivers/mtd/Makefile
@@ -285648,10 +353693,10 @@ index 0000000..b1fda5d
+obj-y += hifmc100.o hifmc100_os.o
diff --git a/drivers/mtd/nand/hifmc100/hifmc100.c b/drivers/mtd/nand/hifmc100/hifmc100.c
new file mode 100644
-index 0000000..25576f9
+index 0000000..ba61ec8
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100/hifmc100.c
-@@ -0,0 +1,1218 @@
+@@ -0,0 +1,1216 @@
+/*
+ * The Flash Memory Controller v100 Device Driver for hisilicon
+ *
@@ -285690,797 +353735,797 @@ index 0000000..25576f9
+/*****************************************************************************/
+static void hifmc100_switch_to_spi_nand(struct hifmc_host *host)
+{
-+ u32 reg;
++ u32 reg;
+
-+ reg = hifmc_readl(host, FMC_CFG);
-+ reg &= ~FLASH_TYPE_SEL_MASK;
-+ reg |= FMC_CFG_FLASH_SEL(FLASH_TYPE_SPI_NAND);
-+ hifmc_writel(host, FMC_CFG, reg);
++ reg = hifmc_readl(host, FMC_CFG);
++ reg &= ~FLASH_TYPE_SEL_MASK;
++ reg |= FMC_CFG_FLASH_SEL(FLASH_TYPE_SPI_NAND);
++ hifmc_writel(host, FMC_CFG, reg);
+}
+
+/*****************************************************************************/
+static void hifmc100_set_str_mode(struct hifmc_host *host)
+{
-+ u32 reg;
++ u32 reg;
+
-+ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
-+ reg &= (~FMC_GLOBAL_CFG_DTR_MODE);
-+ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
++ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
++ reg &= (~FMC_GLOBAL_CFG_DTR_MODE);
++ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
+}
+
+/*****************************************************************************/
+static void hifmc100_operation_config(struct hifmc_host *host, int op)
+{
-+ int ret, clkrate = 0;
-+ struct hifmc_spi *spi = host->spi;
++ int ret, clkrate = 0;
++ struct hifmc_spi *spi = host->spi;
+
-+ hifmc100_switch_to_spi_nand(host);
-+ clk_prepare_enable(host->clk);
-+ switch (op) {
-+ case OP_STYPE_WRITE:
-+ clkrate = min((u_long)host->clkrate,
-+ (u_long)CLK_FMC_TO_CRG_MHZ(spi->write->clock));
-+ break;
-+ case OP_STYPE_READ:
-+ clkrate = min((u_long)host->clkrate,
-+ (u_long)CLK_FMC_TO_CRG_MHZ(spi->read->clock));
-+ break;
-+ case OP_STYPE_ERASE:
-+ clkrate = min((u_long)host->clkrate,
-+ (u_long)CLK_FMC_TO_CRG_MHZ(spi->erase->clock));
-+ break;
-+ default:
-+ break;
-+ }
++ hifmc100_switch_to_spi_nand(host);
++ clk_prepare_enable(host->clk);
++ switch (op) {
++ case OP_STYPE_WRITE:
++ clkrate = min((u_long)host->clkrate,
++ (u_long)CLK_FMC_TO_CRG_MHZ(spi->write->clock));
++ break;
++ case OP_STYPE_READ:
++ clkrate = min((u_long)host->clkrate,
++ (u_long)CLK_FMC_TO_CRG_MHZ(spi->read->clock));
++ break;
++ case OP_STYPE_ERASE:
++ clkrate = min((u_long)host->clkrate,
++ (u_long)CLK_FMC_TO_CRG_MHZ(spi->erase->clock));
++ break;
++ default:
++ break;
++ }
+
-+ ret = clk_set_rate(host->clk, clkrate);
-+ if (WARN_ON(ret)) {
-+ pr_err("clk_set_rate failed: %d\n", ret);
-+ }
++ ret = clk_set_rate(host->clk, clkrate);
++ if (WARN_ON(ret)) {
++ pr_err("clk_set_rate failed: %d\n", ret);
++ }
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_write(struct hifmc_host *host)
+{
-+ unsigned char pages_per_block_shift;
-+ unsigned int reg, block_num, block_num_h, page_num;
-+ struct hifmc_spi *spi = host->spi;
-+ struct nand_chip *chip = host->chip;
++ unsigned char pages_per_block_shift;
++ unsigned int reg, block_num, block_num_h, page_num;
++ struct hifmc_spi *spi = host->spi;
++ struct nand_chip *chip = host->chip;
+#ifdef HIFMC100_SPI_NAND_SUPPORT_REG_WRITE
-+ const char *op = "Reg";
++ const char *op = "Reg";
+#else
-+ const char *op = "Dma";
++ const char *op = "Dma";
+#endif
+
-+ if (WR_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(WR_DBG, "*-Start send %s page write command\n", op);
++ if (WR_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(WR_DBG, "*-Start send %s page write command\n", op);
+
-+ mutex_lock(host->lock);
-+ hifmc100_operation_config(host, OP_STYPE_WRITE);
++ mutex_lock(host->lock);
++ hifmc100_operation_config(host, OP_STYPE_WRITE);
+
-+ reg = spi->driver->wait_ready(spi);
-+ if (reg) {
-+ DB_MSG("Error: %s program wait ready failed! status: %#x\n",
-+ op, reg);
-+ goto end;
-+ }
++ reg = spi->driver->wait_ready(spi);
++ if (reg) {
++ DB_MSG("Error: %s program wait ready failed! status: %#x\n",
++ op, reg);
++ goto end;
++ }
+
-+ reg = spi->driver->write_enable(spi);
-+ if (reg) {
-+ DB_MSG("Error: %s program write enable failed! reg: %#x\n",
-+ op, reg);
-+ goto end;
-+ }
++ reg = spi->driver->write_enable(spi);
++ if (reg) {
++ DB_MSG("Error: %s program write enable failed! reg: %#x\n",
++ op, reg);
++ goto end;
++ }
+
-+ reg = FMC_INT_CLR_ALL;
-+ hifmc_writel(host, FMC_INT_CLR, reg);
-+ FMC_PR(WR_DBG, "|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
++ reg = FMC_INT_CLR_ALL;
++ hifmc_writel(host, FMC_INT_CLR, reg);
++ FMC_PR(WR_DBG, "|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_MEM_IF_TYPE(spi->write->iftype)
-+ | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(WR_DBG, "|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_MEM_IF_TYPE(spi->write->iftype)
++ | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(WR_DBG, "|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
-+ block_num = host->addr_value[1] >> pages_per_block_shift;
-+ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
-+ reg = FMC_ADDRH_SET(block_num_h);
-+ hifmc_writel(host, FMC_ADDRH, reg);
-+ FMC_PR(WR_DBG, "|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
++ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
++ block_num = host->addr_value[1] >> pages_per_block_shift;
++ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
++ reg = FMC_ADDRH_SET(block_num_h);
++ hifmc_writel(host, FMC_ADDRH, reg);
++ FMC_PR(WR_DBG, "|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
+
-+ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
-+ reg = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
-+ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT);
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(WR_DBG, "|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
++ reg = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
++ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT);
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(WR_DBG, "|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
-+ *host->epm = 0x0000;
++ *host->epm = 0x0000;
+
+#ifndef HIFMC100_SPI_NAND_SUPPORT_REG_WRITE
-+ reg = host->dma_buffer;
-+ hifmc_writel(host, FMC_DMA_SADDR_D0, reg);
-+ FMC_PR(WR_DBG, "|-Set DMA_SADDR_D[0x40]%#x\n", reg);
++ reg = host->dma_buffer;
++ hifmc_writel(host, FMC_DMA_SADDR_D0, reg);
++ FMC_PR(WR_DBG, "|-Set DMA_SADDR_D[0x40]%#x\n", reg);
+
+#ifdef CONFIG_64BIT
-+ reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
-+ hifmc_writel(host, FMC_DMA_SADDRH_D0, reg);
-+ FMC_PR(WR_DBG, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
++ reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
++ hifmc_writel(host, FMC_DMA_SADDRH_D0, reg);
++ FMC_PR(WR_DBG, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
+#endif
+
-+ reg = host->dma_oob;
-+ hifmc_writel(host, FMC_DMA_SADDR_OOB, reg);
-+ FMC_PR(WR_DBG, "|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, reg);
++ reg = host->dma_oob;
++ hifmc_writel(host, FMC_DMA_SADDR_OOB, reg);
++ FMC_PR(WR_DBG, "|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, reg);
+#ifdef CONFIG_64BIT
-+ reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
-+ hifmc_writel(host, FMC_DMA_SADDRH_OOB, reg);
-+ FMC_PR(WR_DBG, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
-+ reg);
++ reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
++ hifmc_writel(host, FMC_DMA_SADDRH_OOB, reg);
++ FMC_PR(WR_DBG, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
++ reg);
+#endif
+#endif
+
-+ reg = OP_CTRL_WR_OPCODE(spi->write->cmd)
++ reg = OP_CTRL_WR_OPCODE(spi->write->cmd)
+#ifdef HIFMC100_SPI_NAND_SUPPORT_REG_WRITE
-+ | OP_CTRL_DMA_OP(OP_TYPE_REG)
++ | OP_CTRL_DMA_OP(OP_TYPE_REG)
+#else
-+ | OP_CTRL_DMA_OP(OP_TYPE_DMA)
++ | OP_CTRL_DMA_OP(OP_TYPE_DMA)
+#endif
-+ | OP_CTRL_RW_OP(RW_OP_WRITE)
-+ | OP_CTRL_DMA_OP_READY;
-+ hifmc_writel(host, FMC_OP_CTRL, reg);
-+ FMC_PR(WR_DBG, "|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
++ | OP_CTRL_RW_OP(RW_OP_WRITE)
++ | OP_CTRL_DMA_OP_READY;
++ hifmc_writel(host, FMC_OP_CTRL, reg);
++ FMC_PR(WR_DBG, "|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
+
-+ FMC_DMA_WAIT_INT_FINISH(host);
++ FMC_DMA_WAIT_INT_FINISH(host);
+
+end:
-+ mutex_unlock(host->lock);
-+ FMC_PR(WR_DBG, "*-End %s page program!\n", op);
++ mutex_unlock(host->lock);
++ FMC_PR(WR_DBG, "*-End %s page program!\n", op);
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_status(struct hifmc_host *host)
+{
-+ unsigned char status, addr = STATUS_ADDR;
-+ struct hifmc_spi *spi = host->spi;
++ unsigned char status, addr = STATUS_ADDR;
++ struct hifmc_spi *spi = host->spi;
+
-+ if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
-+ addr = PROTECT_ADDR;
-+ }
++ if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
++ addr = PROTECT_ADDR;
++ }
+
-+ status = spi_nand_feature_op(spi, GET_OP, addr, 0);
-+ FMC_PR((ER_DBG || WR_DBG), "\t*-Get status[%#x]: %#x\n", addr, status);
++ status = spi_nand_feature_op(spi, GET_OP, addr, 0);
++ FMC_PR((ER_DBG || WR_DBG), "\t*-Get status[%#x]: %#x\n", addr, status);
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_read(struct hifmc_host *host)
+{
-+ unsigned char pages_per_block_shift, only_oob = 0;
-+ unsigned short wrap = 0;
-+ unsigned int reg, block_num, block_num_h, page_num, addr_of = 0;
-+ struct hifmc_spi *spi = host->spi;
-+ struct nand_chip *chip = host->chip;
++ unsigned char pages_per_block_shift, only_oob = 0;
++ unsigned short wrap = 0;
++ unsigned int reg, block_num, block_num_h, page_num, addr_of = 0;
++ struct hifmc_spi *spi = host->spi;
++ struct nand_chip *chip = host->chip;
+#ifdef HIFMC100_SPI_NAND_SUPPORT_REG_READ
-+ char *op = "Reg";
++ char *op = "Reg";
+#else
-+ char *op = "Dma";
++ char *op = "Dma";
+#endif
+
-+ if (RD_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(RD_DBG, "\t*-Start %s page read\n", op);
++ if (RD_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(RD_DBG, "\t*-Start %s page read\n", op);
+
-+ if ((host->addr_value[0] == host->cache_addr_value[0])
-+ && (host->addr_value[1] == host->cache_addr_value[1])) {
-+ FMC_PR(RD_DBG, "\t*-%s read cache hit, addr[%#x %#x]\n",
-+ op, host->addr_value[1], host->addr_value[0]);
-+ return;
-+ }
++ if ((host->addr_value[0] == host->cache_addr_value[0])
++ && (host->addr_value[1] == host->cache_addr_value[1])) {
++ FMC_PR(RD_DBG, "\t*-%s read cache hit, addr[%#x %#x]\n",
++ op, host->addr_value[1], host->addr_value[0]);
++ return;
++ }
+
-+ mutex_lock(host->lock);
-+ hifmc100_operation_config(host, OP_STYPE_READ);
++ mutex_lock(host->lock);
++ hifmc100_operation_config(host, OP_STYPE_READ);
+
-+ FMC_PR(RD_DBG, "\t|-Wait ready before %s page read\n", op);
-+ reg = spi->driver->wait_ready(spi);
-+ if (reg) {
-+ DB_MSG("Error: %s read wait ready fail! reg: %#x\n", op, reg);
-+ goto end;
-+ }
++ FMC_PR(RD_DBG, "\t|-Wait ready before %s page read\n", op);
++ reg = spi->driver->wait_ready(spi);
++ if (reg) {
++ DB_MSG("Error: %s read wait ready fail! reg: %#x\n", op, reg);
++ goto end;
++ }
+
-+ reg = FMC_INT_CLR_ALL;
-+ hifmc_writel(host, FMC_INT_CLR, reg);
-+ FMC_PR(RD_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
++ reg = FMC_INT_CLR_ALL;
++ hifmc_writel(host, FMC_INT_CLR, reg);
++ FMC_PR(RD_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
+
-+ if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
-+ only_oob = 1;
-+ host->cmd_op.op_cfg = OP_CTRL_RD_OP_SEL(RD_OP_READ_OOB);
-+ } else {
-+ host->cmd_op.op_cfg = OP_CTRL_RD_OP_SEL(RD_OP_READ_ALL_PAGE);
-+ }
++ if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
++ only_oob = 1;
++ host->cmd_op.op_cfg = OP_CTRL_RD_OP_SEL(RD_OP_READ_OOB);
++ } else {
++ host->cmd_op.op_cfg = OP_CTRL_RD_OP_SEL(RD_OP_READ_ALL_PAGE);
++ }
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_MEM_IF_TYPE(spi->read->iftype)
-+ | OP_CFG_DUMMY_NUM(spi->read->dummy)
-+ | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(RD_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_MEM_IF_TYPE(spi->read->iftype)
++ | OP_CFG_DUMMY_NUM(spi->read->dummy)
++ | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(RD_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
-+ block_num = host->addr_value[1] >> pages_per_block_shift;
-+ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
++ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
++ block_num = host->addr_value[1] >> pages_per_block_shift;
++ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
+
-+ reg = FMC_ADDRH_SET(block_num_h);
-+ hifmc_writel(host, FMC_ADDRH, reg);
-+ FMC_PR(RD_DBG, "\t|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
++ reg = FMC_ADDRH_SET(block_num_h);
++ hifmc_writel(host, FMC_ADDRH, reg);
++ FMC_PR(RD_DBG, "\t|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
+
-+ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
-+ if (only_oob)
-+ switch (host->ecctype) {
-+ case NAND_ECC_8BIT:
-+ addr_of = REG_CNT_ECC_8BIT_OFFSET;
-+ break;
-+ case NAND_ECC_16BIT:
-+ addr_of = REG_CNT_ECC_16BIT_OFFSET;
-+ break;
-+ case NAND_ECC_24BIT:
-+ addr_of = REG_CNT_ECC_24BIT_OFFSET;
-+ break;
-+ case NAND_ECC_0BIT:
-+ default:
-+ break;
-+ }
++ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
++ if (only_oob)
++ switch (host->ecctype) {
++ case NAND_ECC_8BIT:
++ addr_of = REG_CNT_ECC_8BIT_OFFSET;
++ break;
++ case NAND_ECC_16BIT:
++ addr_of = REG_CNT_ECC_16BIT_OFFSET;
++ break;
++ case NAND_ECC_24BIT:
++ addr_of = REG_CNT_ECC_24BIT_OFFSET;
++ break;
++ case NAND_ECC_0BIT:
++ default:
++ break;
++ }
+
-+ reg = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
-+ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT)
-+ | ((wrap & REG_CNT_WRAP_MASK) << REG_CNT_WRAP_SHIFT)
-+ | (addr_of & REG_CNT_ECC_OFFSET_MASK);
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(RD_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ reg = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
++ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT)
++ | ((wrap & REG_CNT_WRAP_MASK) << REG_CNT_WRAP_SHIFT)
++ | (addr_of & REG_CNT_ECC_OFFSET_MASK);
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(RD_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
+#ifndef HIFMC100_SPI_NAND_SUPPORT_REG_READ
-+ reg = host->dma_buffer;
-+ hifmc_writel(host, FMC_DMA_SADDR_D0, reg);
-+ FMC_PR(RD_DBG, "\t|-Set DMA_SADDR_D0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
++ reg = host->dma_buffer;
++ hifmc_writel(host, FMC_DMA_SADDR_D0, reg);
++ FMC_PR(RD_DBG, "\t|-Set DMA_SADDR_D0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
+
+#ifdef CONFIG_64BIT
-+ reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
-+ hifmc_writel(host, FMC_DMA_SADDRH_D0, reg);
-+ FMC_PR(RD_DBG, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
++ reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
++ hifmc_writel(host, FMC_DMA_SADDRH_D0, reg);
++ FMC_PR(RD_DBG, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
+#endif
+
-+ reg = host->dma_oob;
-+ hifmc_writel(host, FMC_DMA_SADDR_OOB, reg);
-+ FMC_PR(RD_DBG, "\t|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB,
-+ reg);
++ reg = host->dma_oob;
++ hifmc_writel(host, FMC_DMA_SADDR_OOB, reg);
++ FMC_PR(RD_DBG, "\t|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB,
++ reg);
+
+#ifdef CONFIG_64BIT
-+ reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
-+ hifmc_writel(host, FMC_DMA_SADDRH_OOB, reg);
-+ FMC_PR(RD_DBG, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
-+ reg);
++ reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
++ hifmc_writel(host, FMC_DMA_SADDRH_OOB, reg);
++ FMC_PR(RD_DBG, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
++ reg);
+#endif
+#endif
+
-+ reg = OP_CTRL_RD_OPCODE(spi->read->cmd) | host->cmd_op.op_cfg
++ reg = OP_CTRL_RD_OPCODE(spi->read->cmd) | host->cmd_op.op_cfg
+#ifdef HIFMC100_SPI_NAND_SUPPORT_REG_READ
-+ | OP_CTRL_DMA_OP(OP_TYPE_REG)
++ | OP_CTRL_DMA_OP(OP_TYPE_REG)
+#else
-+ | OP_CTRL_DMA_OP(OP_TYPE_DMA)
++ | OP_CTRL_DMA_OP(OP_TYPE_DMA)
+#endif
-+ | OP_CTRL_RW_OP(RW_OP_READ) | OP_CTRL_DMA_OP_READY;
-+ hifmc_writel(host, FMC_OP_CTRL, reg);
-+ FMC_PR(RD_DBG, "\t|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
++ | OP_CTRL_RW_OP(RW_OP_READ) | OP_CTRL_DMA_OP_READY;
++ hifmc_writel(host, FMC_OP_CTRL, reg);
++ FMC_PR(RD_DBG, "\t|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
+
-+ FMC_DMA_WAIT_INT_FINISH(host);
++ FMC_DMA_WAIT_INT_FINISH(host);
+
-+ host->cache_addr_value[0] = host->addr_value[0];
-+ host->cache_addr_value[1] = host->addr_value[1];
++ host->cache_addr_value[0] = host->addr_value[0];
++ host->cache_addr_value[1] = host->addr_value[1];
+
+end:
-+ mutex_unlock(host->lock);
-+ FMC_PR(RD_DBG, "\t*-End %s page read\n", op);
++ mutex_unlock(host->lock);
++ FMC_PR(RD_DBG, "\t*-End %s page read\n", op);
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_erase(struct hifmc_host *host)
+{
-+ unsigned int reg;
-+ struct hifmc_spi *spi = host->spi;
++ unsigned int reg;
++ struct hifmc_spi *spi = host->spi;
+
-+ if (ER_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(ER_DBG, "\t*-Start send cmd erase!\n");
++ if (ER_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(ER_DBG, "\t*-Start send cmd erase!\n");
+
-+ mutex_lock(host->lock);
-+ hifmc100_operation_config(host, OP_STYPE_ERASE);
++ mutex_lock(host->lock);
++ hifmc100_operation_config(host, OP_STYPE_ERASE);
+
-+ reg = spi->driver->wait_ready(spi);
-+ FMC_PR(ER_DBG, "\t|-Erase wait ready, reg: %#x\n", reg);
-+ if (reg) {
-+ DB_MSG("Error: Erase wait ready fail! status: %#x\n", reg);
-+ goto end;
-+ }
++ reg = spi->driver->wait_ready(spi);
++ FMC_PR(ER_DBG, "\t|-Erase wait ready, reg: %#x\n", reg);
++ if (reg) {
++ DB_MSG("Error: Erase wait ready fail! status: %#x\n", reg);
++ goto end;
++ }
+
-+ reg = spi->driver->write_enable(spi);
-+ if (reg) {
-+ DB_MSG("Error: Erase write enable failed! reg: %#x\n", reg);
-+ goto end;
-+ }
++ reg = spi->driver->write_enable(spi);
++ if (reg) {
++ DB_MSG("Error: Erase write enable failed! reg: %#x\n", reg);
++ goto end;
++ }
+
-+ reg = FMC_INT_CLR_ALL;
-+ hifmc_writel(host, FMC_INT_CLR, reg);
-+ FMC_PR(ER_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
++ reg = FMC_INT_CLR_ALL;
++ hifmc_writel(host, FMC_INT_CLR, reg);
++ FMC_PR(ER_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
+
-+ reg = spi->erase->cmd;
-+ hifmc_writel(host, FMC_CMD, FMC_CMD_CMD1(reg));
-+ FMC_PR(ER_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = spi->erase->cmd;
++ hifmc_writel(host, FMC_CMD, FMC_CMD_CMD1(reg));
++ FMC_PR(ER_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ reg = FMC_ADDRL_BLOCK_H_MASK(host->addr_value[1])
-+ | FMC_ADDRL_BLOCK_L_MASK(host->addr_value[0]);
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(ER_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ reg = FMC_ADDRL_BLOCK_H_MASK(host->addr_value[1])
++ | FMC_ADDRL_BLOCK_L_MASK(host->addr_value[0]);
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(ER_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_MEM_IF_TYPE(spi->erase->iftype)
-+ | OP_CFG_ADDR_NUM(STD_OP_ADDR_NUM)
-+ | OP_CFG_DUMMY_NUM(spi->erase->dummy)
-+ | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(ER_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_MEM_IF_TYPE(spi->erase->iftype)
++ | OP_CFG_ADDR_NUM(STD_OP_ADDR_NUM)
++ | OP_CFG_DUMMY_NUM(spi->erase->dummy)
++ | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(ER_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_OP_CMD1_EN
-+ | FMC_OP_ADDR_EN
-+ | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(ER_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, reg);
++ reg = FMC_OP_CMD1_EN
++ | FMC_OP_ADDR_EN
++ | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(ER_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
+end:
-+ mutex_unlock(host->lock);
-+ FMC_PR(ER_DBG, "\t*-End send cmd erase!\n");
++ mutex_unlock(host->lock);
++ FMC_PR(ER_DBG, "\t*-End send cmd erase!\n");
+}
+
+/*****************************************************************************/
+void hifmc100_ecc0_switch(struct hifmc_host *host, unsigned char op)
+{
-+ unsigned int config;
++ unsigned int config;
+#if EC_DBG
-+ unsigned int cmp_cfg;
++ unsigned int cmp_cfg;
+
-+ config = hifmc_readl(host, FMC_CFG);
-+ FMC_PR(EC_DBG, "\t *-Get CFG[%#x]%#x\n", FMC_CFG, config);
++ config = hifmc_readl(host, FMC_CFG);
++ FMC_PR(EC_DBG, "\t *-Get CFG[%#x]%#x\n", FMC_CFG, config);
+
-+ if (op) {
-+ cmp_cfg = host->fmc_cfg;
-+ } else {
-+ cmp_cfg = host->fmc_cfg_ecc0;
-+ }
++ if (op) {
++ cmp_cfg = host->fmc_cfg;
++ } else {
++ cmp_cfg = host->fmc_cfg_ecc0;
++ }
+
-+ if (cmp_cfg != config)
-+ DB_MSG("Warning: FMC config[%#x] is different.\n",
-+ cmp_cfg);
++ if (cmp_cfg != config)
++ DB_MSG("Warning: FMC config[%#x] is different.\n",
++ cmp_cfg);
+#endif
+
-+ if (op == ENABLE) {
-+ config = host->fmc_cfg_ecc0;
-+ } else if (op == DISABLE) {
-+ config = host->fmc_cfg;
-+ } else {
-+ DB_MSG("Error: Invalid opcode: %d\n", op);
-+ return;
-+ }
++ if (op == ENABLE) {
++ config = host->fmc_cfg_ecc0;
++ } else if (op == DISABLE) {
++ config = host->fmc_cfg;
++ } else {
++ DB_MSG("Error: Invalid opcode: %d\n", op);
++ return;
++ }
+
-+ hifmc_writel(host, FMC_CFG, config);
-+ FMC_PR(EC_DBG, "\t *-Set CFG[%#x]%#x\n", FMC_CFG, config);
++ hifmc_writel(host, FMC_CFG, config);
++ FMC_PR(EC_DBG, "\t *-Set CFG[%#x]%#x\n", FMC_CFG, config);
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_readid(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(BT_DBG, "\t|*-Start send cmd read ID\n");
++ FMC_PR(BT_DBG, "\t|*-Start send cmd read ID\n");
+
-+ hifmc100_ecc0_switch(host, ENABLE);
++ hifmc100_ecc0_switch(host, ENABLE);
+
-+ reg = FMC_CMD_CMD1(SPI_CMD_RDID);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD1(SPI_CMD_RDID);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ reg = READ_ID_ADDR;
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(BT_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ reg = READ_ID_ADDR;
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(BT_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_ADDR_NUM(READ_ID_ADDR_NUM)
-+ | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_ADDR_NUM(READ_ID_ADDR_NUM)
++ | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_DATA_NUM_CNT(MAX_SPI_NAND_ID_LEN);
-+ hifmc_writel(host, FMC_DATA_NUM, reg);
-+ FMC_PR(BT_DBG, "\t||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
++ reg = FMC_DATA_NUM_CNT(MAX_SPI_NAND_ID_LEN);
++ hifmc_writel(host, FMC_DATA_NUM, reg);
++ FMC_PR(BT_DBG, "\t||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
+
-+ reg = FMC_OP_CMD1_EN
-+ | FMC_OP_ADDR_EN
-+ | FMC_OP_READ_DATA_EN
-+ | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
++ reg = FMC_OP_CMD1_EN
++ | FMC_OP_ADDR_EN
++ | FMC_OP_READ_DATA_EN
++ | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ host->addr_cycle = 0x0;
++ host->addr_cycle = 0x0;
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ hifmc100_ecc0_switch(host, DISABLE);
++ hifmc100_ecc0_switch(host, DISABLE);
+
-+ FMC_PR(BT_DBG, "\t|*-End read flash ID\n");
++ FMC_PR(BT_DBG, "\t|*-End read flash ID\n");
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_reset(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(BT_DBG, "\t|*-Start send cmd reset\n");
++ FMC_PR(BT_DBG, "\t|*-Start send cmd reset\n");
+
-+ reg = FMC_CMD_CMD1(SPI_CMD_RESET);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD1(SPI_CMD_RESET);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
++ reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ FMC_PR(BT_DBG, "\t|*-End send cmd reset\n");
++ FMC_PR(BT_DBG, "\t|*-End send cmd reset\n");
+}
+
+/*****************************************************************************/
+static void hifmc100_host_init(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(BT_DBG, "\t||*-Start SPI Nand host init\n");
++ FMC_PR(BT_DBG, "\t||*-Start SPI Nand host init\n");
+
-+ reg = hifmc_readl(host, FMC_CFG);
-+ if ((reg & FMC_CFG_OP_MODE_MASK) == FMC_CFG_OP_MODE_BOOT) {
-+ reg |= FMC_CFG_OP_MODE(FMC_CFG_OP_MODE_NORMAL);
-+ hifmc_writel(host, FMC_CFG, reg);
-+ FMC_PR(BT_DBG, "\t|||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
-+ }
++ reg = hifmc_readl(host, FMC_CFG);
++ if ((reg & FMC_CFG_OP_MODE_MASK) == FMC_CFG_OP_MODE_BOOT) {
++ reg |= FMC_CFG_OP_MODE(FMC_CFG_OP_MODE_NORMAL);
++ hifmc_writel(host, FMC_CFG, reg);
++ FMC_PR(BT_DBG, "\t|||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
++ }
+
-+ host->fmc_cfg = reg;
-+ host->fmc_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
++ host->fmc_cfg = reg;
++ host->fmc_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
+
-+ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
-+ if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
-+ reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
-+ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
-+ }
++ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
++ if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
++ reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
++ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
++ }
+
-+ host->addr_cycle = 0;
-+ host->addr_value[0] = 0;
-+ host->addr_value[1] = 0;
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
++ host->addr_cycle = 0;
++ host->addr_value[0] = 0;
++ host->addr_value[1] = 0;
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
+
-+ host->send_cmd_write = hifmc100_send_cmd_write;
-+ host->send_cmd_status = hifmc100_send_cmd_status;
-+ host->send_cmd_read = hifmc100_send_cmd_read;
-+ host->send_cmd_erase = hifmc100_send_cmd_erase;
-+ host->send_cmd_readid = hifmc100_send_cmd_readid;
-+ host->send_cmd_reset = hifmc100_send_cmd_reset;
++ host->send_cmd_write = hifmc100_send_cmd_write;
++ host->send_cmd_status = hifmc100_send_cmd_status;
++ host->send_cmd_read = hifmc100_send_cmd_read;
++ host->send_cmd_erase = hifmc100_send_cmd_erase;
++ host->send_cmd_readid = hifmc100_send_cmd_readid;
++ host->send_cmd_reset = hifmc100_send_cmd_reset;
+#ifdef CONFIG_PM
-+ host->suspend = hifmc100_suspend;
-+ host->resume = hifmc100_resume;
++ host->suspend = hifmc100_suspend;
++ host->resume = hifmc100_resume;
+#endif
+
-+ reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
-+ | TIMING_CFG_TCSS(CS_SETUP_TIME)
-+ | TIMING_CFG_TSHSL(CS_DESELECT_TIME);
-+ hifmc_writel(host, FMC_SPI_TIMING_CFG, reg);
++ reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
++ | TIMING_CFG_TCSS(CS_SETUP_TIME)
++ | TIMING_CFG_TSHSL(CS_DESELECT_TIME);
++ hifmc_writel(host, FMC_SPI_TIMING_CFG, reg);
+
-+ reg = ALL_BURST_ENABLE;
-+ hifmc_writel(host, FMC_DMA_AHB_CTRL, reg);
++ reg = ALL_BURST_ENABLE;
++ hifmc_writel(host, FMC_DMA_AHB_CTRL, reg);
+
-+ FMC_PR(BT_DBG, "\t||*-End SPI Nand host init\n");
++ FMC_PR(BT_DBG, "\t||*-End SPI Nand host init\n");
+}
+
+/*****************************************************************************/
+static unsigned char hifmc100_read_byte(struct mtd_info *mtd)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
-+ unsigned char value, ret_val = 0;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
++ unsigned char value, ret_val = 0;
+
-+ if (host->cmd_op.l_cmd == NAND_CMD_READID) {
-+ value = hifmc_readb(host->iobase + host->offset);
-+ host->offset++;
-+ if (host->cmd_op.data_no == host->offset) {
-+ host->cmd_op.l_cmd = 0;
-+ }
-+ return value;
-+ }
++ if (host->cmd_op.l_cmd == NAND_CMD_READID) {
++ value = hifmc_readb(host->iobase + host->offset);
++ host->offset++;
++ if (host->cmd_op.data_no == host->offset) {
++ host->cmd_op.l_cmd = 0;
++ }
++ return value;
++ }
+
-+ if (host->cmd_op.cmd == NAND_CMD_STATUS) {
-+ value = hifmc_readl(host, FMC_STATUS);
-+ if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
-+ FMC_PR((ER_DBG || WR_DBG), "\t\tRead BP status:%#x\n",
-+ value);
-+ if (ANY_BP_ENABLE(value)) {
-+ ret_val |= NAND_STATUS_WP;
-+ }
++ if (host->cmd_op.cmd == NAND_CMD_STATUS) {
++ value = hifmc_readl(host, FMC_STATUS);
++ if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
++ FMC_PR((ER_DBG || WR_DBG), "\t\tRead BP status:%#x\n",
++ value);
++ if (ANY_BP_ENABLE(value)) {
++ ret_val |= NAND_STATUS_WP;
++ }
+
-+ host->cmd_op.l_cmd = NAND_CMD_STATUS;
-+ }
++ host->cmd_op.l_cmd = NAND_CMD_STATUS;
++ }
+
-+ if (!(value & STATUS_OIP_MASK)) {
-+ ret_val |= NAND_STATUS_READY;
-+ }
++ if (!(value & STATUS_OIP_MASK)) {
++ ret_val |= NAND_STATUS_READY;
++ }
+
-+ if (value & STATUS_E_FAIL_MASK) {
-+ FMC_PR(ER_DBG, "\t\tGet erase status: %#x\n", value);
-+ ret_val |= NAND_STATUS_FAIL;
-+ }
++ if (value & STATUS_E_FAIL_MASK) {
++ FMC_PR(ER_DBG, "\t\tGet erase status: %#x\n", value);
++ ret_val |= NAND_STATUS_FAIL;
++ }
+
-+ if (value & STATUS_P_FAIL_MASK) {
-+ FMC_PR(WR_DBG, "\t\tGet write status: %#x\n", value);
-+ ret_val |= NAND_STATUS_FAIL;
-+ }
++ if (value & STATUS_P_FAIL_MASK) {
++ FMC_PR(WR_DBG, "\t\tGet write status: %#x\n", value);
++ ret_val |= NAND_STATUS_FAIL;
++ }
+
-+ return ret_val;
-+ }
++ return ret_val;
++ }
+
-+ if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
-+ value = hifmc_readb(host->buffer + host->pagesize + host->offset);
-+ host->offset++;
-+ return value;
-+ }
++ if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
++ value = hifmc_readb(host->buffer + host->pagesize + host->offset);
++ host->offset++;
++ return value;
++ }
+
-+ host->offset++;
++ host->offset++;
+
-+ return hifmc_readb(host->buffer + host->column + host->offset - 1);
++ return hifmc_readb(host->buffer + host->column + host->offset - 1);
+}
+
+/*****************************************************************************/
+static unsigned short hifmc100_read_word(struct mtd_info *mtd)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ host->offset += 2;
-+ return hifmc_readw(host->buffer + host->column + host->offset - 2);
++ host->offset += 2;
++ return hifmc_readw(host->buffer + host->column + host->offset - 2);
+}
+
+/*****************************************************************************/
+static void hifmc100_write_buf(struct mtd_info *mtd,
-+ const u_char *buf, int len)
++ const u_char *buf, int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
+#ifdef HIFMC100_SPI_NAND_SUPPORT_REG_WRITE
-+ if (buf == chip->oob_poi) {
-+ memcpy((char *)host->iobase + host->pagesize, buf, len);
-+ } else {
-+ memcpy((char *)host->iobase, buf, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy((char *)host->iobase + host->pagesize, buf, len);
++ } else {
++ memcpy((char *)host->iobase, buf, len);
++ }
+#else
-+ if (buf == chip->oob_poi) {
-+ memcpy((char *)(host->buffer + host->pagesize), buf, len);
-+ } else {
-+ memcpy((char *)host->buffer, buf, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy((char *)(host->buffer + host->pagesize), buf, len);
++ } else {
++ memcpy((char *)host->buffer, buf, len);
++ }
+#endif
-+ return;
++ return;
+}
+
+/*****************************************************************************/
+static void hifmc100_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
+#ifdef HIFMC100_SPI_NAND_SUPPORT_REG_READ
-+ if (buf == chip->oob_poi) {
-+ memcpy(buf, (char *)host->iobase + host->pagesize, len);
-+ } else {
-+ memcpy(buf, (char *)host->iobase, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy(buf, (char *)host->iobase + host->pagesize, len);
++ } else {
++ memcpy(buf, (char *)host->iobase, len);
++ }
+#else
-+ if (buf == chip->oob_poi) {
-+ memcpy(buf, (char *)host->buffer + host->pagesize, len);
-+ } else {
-+ memcpy(buf, (char *)host->buffer, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy(buf, (char *)host->buffer + host->pagesize, len);
++ } else {
++ memcpy(buf, (char *)host->buffer, len);
++ }
+#endif
+
+#ifdef CONFIG_HISI_NAND_ECC_STATUS_REPORT
-+ if (buf != chip->oob_poi) {
-+ u_int reg, ecc_step = host->pagesize >> 10;
++ if (buf != chip->oob_poi) {
++ u_int reg, ecc_step = host->pagesize >> 10;
+
-+ reg = hifmc_readl(host, HIFMC100_ECC_ERR_NUM0_BUF0);
-+ while (ecc_step) {
-+ u_char err_num;
++ reg = hifmc_readl(host, HIFMC100_ECC_ERR_NUM0_BUF0);
++ while (ecc_step) {
++ u_char err_num;
+
-+ err_num = GET_ECC_ERR_NUM(--ecc_step, reg);
-+ if (err_num == 0xff) {
-+ mtd->ecc_stats.failed++;
-+ } else {
-+ mtd->ecc_stats.corrected += err_num;
-+ }
-+ }
-+ }
++ err_num = GET_ECC_ERR_NUM(--ecc_step, reg);
++ if (err_num == 0xff) {
++ mtd->ecc_stats.failed++;
++ } else {
++ mtd->ecc_stats.corrected += err_num;
++ }
++ }
++ }
+#endif
+
-+ return;
++ return;
+}
+
+/*****************************************************************************/
+static void hifmc100_select_chip(struct mtd_info *mtd, int chipselect)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ if (chipselect < 0) {
-+ mutex_unlock(&fmc_switch_mutex);
-+ return;
-+ }
++ if (chipselect < 0) {
++ mutex_unlock(&fmc_switch_mutex);
++ return;
++ }
+
-+ mutex_lock(&fmc_switch_mutex);
++ mutex_lock(&fmc_switch_mutex);
+
-+ if (chipselect > CONFIG_SPI_NAND_MAX_CHIP_NUM) {
-+ DB_BUG("Error: Invalid chipselect: %d\n", chipselect);
-+ }
++ if (chipselect > CONFIG_SPI_NAND_MAX_CHIP_NUM) {
++ DB_BUG("Error: Invalid chipselect: %d\n", chipselect);
++ }
+
-+ if (host->mtd != mtd) {
-+ host->mtd = mtd;
-+ host->cmd_op.cs = chipselect;
-+ }
++ if (host->mtd != mtd) {
++ host->mtd = mtd;
++ host->cmd_op.cs = chipselect;
++ }
+
-+ if (!(chip->options & NAND_BROKEN_XD)) {
-+ if ((chip->state == FL_ERASING) || (chip->state == FL_WRITING)) {
-+ host->cmd_op.l_cmd = NAND_CMD_GET_FEATURES;
-+ }
-+ }
++ if (!(chip->options & NAND_BROKEN_XD)) {
++ if ((chip->state == FL_ERASING) || (chip->state == FL_WRITING)) {
++ host->cmd_op.l_cmd = NAND_CMD_GET_FEATURES;
++ }
++ }
+}
+
+/*****************************************************************************/
+static void hifmc100_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned ctrl)
+{
-+ unsigned char cmd;
-+ int is_cache_invalid = 1;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
-+ unsigned int udat = (unsigned int)dat;
++ unsigned char cmd;
++ int is_cache_invalid = 1;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
++ unsigned int udat = (unsigned int)dat;
+
-+ if (ctrl & NAND_ALE) {
-+ unsigned int addr_value = 0;
-+ unsigned int addr_offset = 0;
++ if (ctrl & NAND_ALE) {
++ unsigned int addr_value = 0;
++ unsigned int addr_offset = 0;
+
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ host->addr_cycle = 0x0;
-+ host->addr_value[0] = 0x0;
-+ host->addr_value[1] = 0x0;
-+ }
-+ addr_offset = host->addr_cycle << 3;
++ if (ctrl & NAND_CTRL_CHANGE) {
++ host->addr_cycle = 0x0;
++ host->addr_value[0] = 0x0;
++ host->addr_value[1] = 0x0;
++ }
++ addr_offset = host->addr_cycle << 3;
+
-+ if (host->addr_cycle >= HIFMC100_ADDR_CYCLE_MASK) {
-+ addr_offset = (host->addr_cycle -
-+ HIFMC100_ADDR_CYCLE_MASK) << 3;
-+ addr_value = 1;
-+ }
-+ host->addr_value[addr_value] |=
-+ ((udat & 0xff) << addr_offset);
++ if (host->addr_cycle >= HIFMC100_ADDR_CYCLE_MASK) {
++ addr_offset = (host->addr_cycle -
++ HIFMC100_ADDR_CYCLE_MASK) << 3;
++ addr_value = 1;
++ }
++ host->addr_value[addr_value] |=
++ ((udat & 0xff) << addr_offset);
+
-+ host->addr_cycle++;
-+ }
++ host->addr_cycle++;
++ }
+
-+ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
-+ cmd = udat & 0xff;
-+ host->cmd_op.cmd = cmd;
-+ switch (cmd) {
-+ case NAND_CMD_PAGEPROG:
-+ host->offset = 0;
-+ host->send_cmd_write(host);
-+ break;
++ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
++ cmd = udat & 0xff;
++ host->cmd_op.cmd = cmd;
++ switch (cmd) {
++ case NAND_CMD_PAGEPROG:
++ host->offset = 0;
++ host->send_cmd_write(host);
++ break;
+
-+ case NAND_CMD_READSTART:
-+ is_cache_invalid = 0;
-+ if (host->addr_value[0] == host->pagesize) {
-+ host->cmd_op.l_cmd = NAND_CMD_READOOB;
-+ }
-+ host->send_cmd_read(host);
-+ break;
++ case NAND_CMD_READSTART:
++ is_cache_invalid = 0;
++ if (host->addr_value[0] == host->pagesize) {
++ host->cmd_op.l_cmd = NAND_CMD_READOOB;
++ }
++ host->send_cmd_read(host);
++ break;
+
-+ case NAND_CMD_ERASE2:
-+ host->send_cmd_erase(host);
-+ break;
++ case NAND_CMD_ERASE2:
++ host->send_cmd_erase(host);
++ break;
+
-+ case NAND_CMD_READID:
-+ memset((u_char *)(host->iobase), 0,
-+ MAX_SPI_NAND_ID_LEN);
-+ host->cmd_op.l_cmd = cmd;
-+ host->cmd_op.data_no = MAX_SPI_NAND_ID_LEN;
-+ host->send_cmd_readid(host);
-+ break;
++ case NAND_CMD_READID:
++ memset((u_char *)(host->iobase), 0,
++ MAX_SPI_NAND_ID_LEN);
++ host->cmd_op.l_cmd = cmd;
++ host->cmd_op.data_no = MAX_SPI_NAND_ID_LEN;
++ host->send_cmd_readid(host);
++ break;
+
-+ case NAND_CMD_STATUS:
-+ host->send_cmd_status(host);
-+ break;
++ case NAND_CMD_STATUS:
++ host->send_cmd_status(host);
++ break;
+
-+ case NAND_CMD_READ0:
-+ host->cmd_op.l_cmd = cmd;
-+ break;
++ case NAND_CMD_READ0:
++ host->cmd_op.l_cmd = cmd;
++ break;
+
-+ case NAND_CMD_RESET:
-+ host->send_cmd_reset(host);
-+ break;
++ case NAND_CMD_RESET:
++ host->send_cmd_reset(host);
++ break;
+
-+ case NAND_CMD_SEQIN:
-+ case NAND_CMD_ERASE1:
-+ default:
-+ break;
-+ }
-+ }
++ case NAND_CMD_SEQIN:
++ case NAND_CMD_ERASE1:
++ default:
++ break;
++ }
++ }
+
-+ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
-+ if (host->cmd_op.cmd == NAND_CMD_SEQIN
-+ || host->cmd_op.cmd == NAND_CMD_READ0
-+ || host->cmd_op.cmd == NAND_CMD_READID) {
-+ host->offset = 0x0;
-+ host->column = (host->addr_value[0] & 0xffff);
-+ }
-+ }
++ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
++ if (host->cmd_op.cmd == NAND_CMD_SEQIN
++ || host->cmd_op.cmd == NAND_CMD_READ0
++ || host->cmd_op.cmd == NAND_CMD_READID) {
++ host->offset = 0x0;
++ host->column = (host->addr_value[0] & 0xffff);
++ }
++ }
+
-+ if (is_cache_invalid) {
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
-+ }
++ if (is_cache_invalid) {
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
++ }
+}
+
+/*****************************************************************************/
+static int hifmc100_dev_ready(struct mtd_info *mtd)
+{
-+ unsigned int reg;
-+ unsigned long deadline = jiffies + FMC_MAX_READY_WAIT_JIFFIES;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ unsigned int reg;
++ unsigned long deadline = jiffies + FMC_MAX_READY_WAIT_JIFFIES;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ do {
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
++ do {
++ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
+
-+ reg = FMC_OP_READ_STATUS_EN | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
++ reg = FMC_OP_READ_STATUS_EN | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ reg = hifmc_readl(host, FMC_STATUS);
++ reg = hifmc_readl(host, FMC_STATUS);
+
-+ if (!(reg & STATUS_OIP_MASK)) {
-+ return NAND_STATUS_READY;
-+ }
++ if (!(reg & STATUS_OIP_MASK)) {
++ return NAND_STATUS_READY;
++ }
+
-+ cond_resched();
++ cond_resched();
+
-+ } while (!time_after_eq(jiffies, deadline));
++ } while (!time_after_eq(jiffies, deadline));
+
-+ if (!(chip->options & NAND_SCAN_SILENT_NODEV)) {
-+ pr_warn("Wait SPI nand ready timeout, status: %#x\n", reg);
-+ }
++ if (!(chip->options & NAND_SCAN_SILENT_NODEV)) {
++ pr_warn("Wait SPI nand ready timeout, status: %#x\n", reg);
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -286489,117 +354534,117 @@ index 0000000..25576f9
+ */
+/* Default OOB area layout */
+static int hifmc_ooblayout_ecc_default(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 32;
-+ oobregion->offset = 32;
++ oobregion->length = 32;
++ oobregion->offset = 32;
+
-+ return 0;
++ return 0;
+}
+
+static int hifmc_ooblayout_free_default(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 30;
-+ oobregion->offset = 2;
++ oobregion->length = 30;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+
+static struct mtd_ooblayout_ops hifmc_ooblayout_default_ops = {
-+ .ecc = hifmc_ooblayout_ecc_default,
-+ .free = hifmc_ooblayout_free_default,
++ .ecc = hifmc_ooblayout_ecc_default,
++ .free = hifmc_ooblayout_free_default,
+};
+
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
+static int hifmc_ooblayout_ecc_4k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 14;
-+ oobregion->offset = 14;
++ oobregion->length = 14;
++ oobregion->offset = 14;
+
-+ return 0;
++ return 0;
+}
+
+static int hifmc_ooblayout_free_4k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 14;
-+ oobregion->offset = 2;
++ oobregion->length = 14;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+
+static struct mtd_ooblayout_ops hifmc_ooblayout_4k16bit_ops = {
-+ .ecc = hifmc_ooblayout_ecc_4k16bit,
-+ .free = hifmc_ooblayout_free_4k16bit,
++ .ecc = hifmc_ooblayout_ecc_4k16bit,
++ .free = hifmc_ooblayout_free_4k16bit,
+};
+
+static int hifmc_ooblayout_ecc_2k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 6;
-+ oobregion->offset = 6;
++ oobregion->length = 6;
++ oobregion->offset = 6;
+
-+ return 0;
++ return 0;
+}
+
+static int hifmc_ooblayout_free_2k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 6;
-+ oobregion->offset = 2;
++ oobregion->length = 6;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+
+static struct mtd_ooblayout_ops hifmc_ooblayout_2k16bit_ops = {
-+ .ecc = hifmc_ooblayout_ecc_2k16bit,
-+ .free = hifmc_ooblayout_free_2k16bit,
++ .ecc = hifmc_ooblayout_ecc_2k16bit,
++ .free = hifmc_ooblayout_free_2k16bit,
+};
+#endif
+
+/*****************************************************************************/
+static struct nand_config_info hifmc_spi_nand_config_table[] = {
-+ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200, &hifmc_ooblayout_default_ops},
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
-+ {NAND_PAGE_4K, NAND_ECC_16BIT, 16, 128, &hifmc_ooblayout_4k16bit_ops},
++ {NAND_PAGE_4K, NAND_ECC_16BIT, 16, 128, &hifmc_ooblayout_4k16bit_ops},
+#endif
-+ {NAND_PAGE_4K, NAND_ECC_8BIT, 8, 128, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_4K, NAND_ECC_8BIT, 8, 128, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
+
-+ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128, &hifmc_ooblayout_default_ops},
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
-+ {NAND_PAGE_2K, NAND_ECC_16BIT, 16, 64, &hifmc_ooblayout_2k16bit_ops},
++ {NAND_PAGE_2K, NAND_ECC_16BIT, 16, 64, &hifmc_ooblayout_2k16bit_ops},
+#endif
-+ {NAND_PAGE_2K, NAND_ECC_8BIT, 8, 64, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_2K, NAND_ECC_8BIT, 8, 64, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
+
-+ {0, 0, 0, 0, NULL},
++ {0, 0, 0, 0, NULL},
+};
+
+/*
@@ -286608,271 +354653,269 @@ index 0000000..25576f9
+ * so the page size and ecc type is match adaptively without switch on the board
+ */
+static struct nand_config_info *hifmc100_get_config_type_info(
-+ struct mtd_info *mtd, struct nand_dev_t *nand_dev)
++ struct mtd_info *mtd, struct nand_dev_t *nand_dev)
+{
-+ struct nand_config_info *best = NULL;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct nand_config_info *info = hifmc_spi_nand_config_table;
++ struct nand_config_info *best = NULL;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct nand_config_info *info = hifmc_spi_nand_config_table;
+
-+ nand_dev->start_type = "Auto";
++ nand_dev->start_type = "Auto";
+
-+ for (; info->ooblayout_ops; info++) {
-+ if (match_page_type_to_size(info->pagetype) != mtd->writesize) {
-+ continue;
-+ }
++ for (; info->ooblayout_ops; info++) {
++ if (match_page_type_to_size(info->pagetype) != mtd->writesize) {
++ continue;
++ }
+
-+ if (mtd->oobsize < info->oobsize) {
-+ continue;
-+ }
++ if (mtd->oobsize < info->oobsize) {
++ continue;
++ }
+
-+ if (!best || (best->ecctype < info->ecctype)) {
-+ best = info;
-+ }
-+ }
++ if (!best || (best->ecctype < info->ecctype)) {
++ best = info;
++ }
++ }
+
-+ /* All SPI NAND are small-page, SLC */
-+ chip->bits_per_cell = 1;
++ /* All SPI NAND are small-page, SLC */
++ chip->bits_per_cell = 1;
+
-+ return best;
++ return best;
+}
+
+/*****************************************************************************/
+static void hifmc100_chip_init(struct nand_chip *chip)
+{
-+ chip->read_byte = hifmc100_read_byte;
-+ chip->read_word = hifmc100_read_word;
-+ chip->write_buf = hifmc100_write_buf;
-+ chip->read_buf = hifmc100_read_buf;
++ chip->read_byte = hifmc100_read_byte;
++ chip->read_word = hifmc100_read_word;
++ chip->write_buf = hifmc100_write_buf;
++ chip->read_buf = hifmc100_read_buf;
+
-+ chip->select_chip = hifmc100_select_chip;
++ chip->select_chip = hifmc100_select_chip;
+
-+ chip->cmd_ctrl = hifmc100_cmd_ctrl;
-+ chip->dev_ready = hifmc100_dev_ready;
++ chip->cmd_ctrl = hifmc100_cmd_ctrl;
++ chip->dev_ready = hifmc100_dev_ready;
+
-+ chip->chip_delay = FMC_CHIP_DELAY;
++ chip->chip_delay = FMC_CHIP_DELAY;
+
-+ chip->options = NAND_SKIP_BBTSCAN | NAND_BROKEN_XD
-+ | NAND_SCAN_SILENT_NODEV;
++ chip->options = NAND_SKIP_BBTSCAN | NAND_BROKEN_XD
++ | NAND_SCAN_SILENT_NODEV;
+
-+ chip->ecc.mode = NAND_ECC_NONE;
++ chip->ecc.mode = NAND_ECC_NONE;
+}
+
+/*****************************************************************************/
+static void hifmc100_set_oob_info(struct mtd_info *mtd,
-+ struct nand_config_info *info, struct nand_dev_t *nand_dev)
++ struct nand_config_info *info, struct nand_dev_t *nand_dev)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
-+ struct mtd_oob_region hifmc_oobregion = {0, 0};
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
++ struct mtd_oob_region hifmc_oobregion = {0, 0};
+
-+ if (info->ecctype != NAND_ECC_0BIT) {
-+ mtd->oobsize = info->oobsize;
-+ }
++ if (info->ecctype != NAND_ECC_0BIT) {
++ mtd->oobsize = info->oobsize;
++ }
+
-+ host->oobsize = mtd->oobsize;
-+ nand_dev->oobsize = host->oobsize;
++ host->oobsize = mtd->oobsize;
++ nand_dev->oobsize = host->oobsize;
+
-+ host->dma_oob = host->dma_buffer + host->pagesize;
-+ host->bbm = (u_char *)(host->buffer + host->pagesize
-+ + HIFMC_BAD_BLOCK_POS);
++ host->dma_oob = host->dma_buffer + host->pagesize;
++ host->bbm = (u_char *)(host->buffer + host->pagesize
++ + HIFMC_BAD_BLOCK_POS);
+
-+ info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
++ info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
+
-+ mtd_set_ooblayout(mtd, info->ooblayout_ops);
++ mtd_set_ooblayout(mtd, info->ooblayout_ops);
+
-+ /* EB bits locate in the bottom two of CTRL(30) */
-+ host->epm = (u_short *)(host->buffer + host->pagesize
-+ + hifmc_oobregion.offset + 28);
++ /* EB bits locate in the bottom two of CTRL(30) */
++ host->epm = (u_short *)(host->buffer + host->pagesize
++ + hifmc_oobregion.offset + 28);
+
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
-+ if (best->ecctype == NAND_ECC_16BIT) {
-+ if (host->pagesize == _2K) {
-+ /* EB bits locate in the bottom two of CTRL(4) */
-+ host->epm = (u_short *)(host->buffer + host->pagesize
-+ + hifmc_oobregion.offset + 4);
-+ } else if (host->pagesize == _4K) {
-+ /* EB bit locate in the bottom two of CTRL(14) */
-+ host->epm = (u_short *)(host->buffer + host->pagesize
-+ + hifmc_oobregion.offset + 12);
-+ }
-+ }
++ if (best->ecctype == NAND_ECC_16BIT) {
++ if (host->pagesize == _2K) {
++ /* EB bits locate in the bottom two of CTRL(4) */
++ host->epm = (u_short *)(host->buffer + host->pagesize
++ + hifmc_oobregion.offset + 4);
++ } else if (host->pagesize == _4K) {
++ /* EB bit locate in the bottom two of CTRL(14) */
++ host->epm = (u_short *)(host->buffer + host->pagesize
++ + hifmc_oobregion.offset + 12);
++ }
++ }
+#endif
+}
+
+/*****************************************************************************/
+static unsigned int hifmc100_get_ecc_reg(struct hifmc_host *host,
-+ struct nand_config_info *info, struct nand_dev_t *nand_dev)
++ struct nand_config_info *info, struct nand_dev_t *nand_dev)
+{
-+ host->ecctype = info->ecctype;
-+ nand_dev->ecctype = host->ecctype;
++ host->ecctype = info->ecctype;
++ nand_dev->ecctype = host->ecctype;
+
-+ return FMC_CFG_ECC_TYPE(match_ecc_type_to_reg(info->ecctype));
++ return FMC_CFG_ECC_TYPE(match_ecc_type_to_reg(info->ecctype));
+}
+
+/*****************************************************************************/
+static unsigned int hifmc100_get_page_reg(struct hifmc_host *host,
-+ struct nand_config_info *info)
++ struct nand_config_info *info)
+{
-+ host->pagesize = match_page_type_to_size(info->pagetype);
++ host->pagesize = match_page_type_to_size(info->pagetype);
+
-+ return FMC_CFG_PAGE_SIZE(match_page_type_to_reg(info->pagetype));
++ return FMC_CFG_PAGE_SIZE(match_page_type_to_reg(info->pagetype));
+}
+
+/*****************************************************************************/
+static unsigned int hifmc100_get_block_reg(struct hifmc_host *host,
-+ struct nand_config_info *info)
++ struct nand_config_info *info)
+{
-+ unsigned int block_reg = 0, page_per_block;
-+ struct mtd_info *mtd = host->mtd;
++ unsigned int block_reg = 0, page_per_block;
++ struct mtd_info *mtd = host->mtd;
+
-+ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
-+ page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
-+ switch (page_per_block) {
-+ case 64:
-+ block_reg = BLOCK_SIZE_64_PAGE;
-+ break;
-+ case 128:
-+ block_reg = BLOCK_SIZE_128_PAGE;
-+ break;
-+ case 256:
-+ block_reg = BLOCK_SIZE_256_PAGE;
-+ break;
-+ case 512:
-+ block_reg = BLOCK_SIZE_512_PAGE;
-+ break;
-+ default:
-+ DB_MSG("Can't support block %#x and page %#x size\n",
-+ mtd->erasesize, mtd->writesize);
-+ }
++ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
++ page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
++ switch (page_per_block) {
++ case 64:
++ block_reg = BLOCK_SIZE_64_PAGE;
++ break;
++ case 128:
++ block_reg = BLOCK_SIZE_128_PAGE;
++ break;
++ case 256:
++ block_reg = BLOCK_SIZE_256_PAGE;
++ break;
++ case 512:
++ block_reg = BLOCK_SIZE_512_PAGE;
++ break;
++ default:
++ DB_MSG("Can't support block %#x and page %#x size\n",
++ mtd->erasesize, mtd->writesize);
++ }
+
-+ return FMC_CFG_BLOCK_SIZE(block_reg);
++ return FMC_CFG_BLOCK_SIZE(block_reg);
+}
+
+/*****************************************************************************/
+static void hifmc100_set_fmc_cfg_reg(struct hifmc_host *host,
-+ struct nand_config_info *type_info, struct nand_dev_t *nand_dev)
++ struct nand_config_info *type_info, struct nand_dev_t *nand_dev)
+{
-+ unsigned int page_reg, ecc_reg, block_reg, reg_fmc_cfg;
++ unsigned int page_reg, ecc_reg, block_reg, reg_fmc_cfg;
+
-+ ecc_reg = hifmc100_get_ecc_reg(host, type_info, nand_dev);
-+ page_reg = hifmc100_get_page_reg(host, type_info);
-+ block_reg = hifmc100_get_block_reg(host, type_info);
++ ecc_reg = hifmc100_get_ecc_reg(host, type_info, nand_dev);
++ page_reg = hifmc100_get_page_reg(host, type_info);
++ block_reg = hifmc100_get_block_reg(host, type_info);
+
-+ reg_fmc_cfg = hifmc_readl(host, FMC_CFG);
-+ reg_fmc_cfg &= ~(PAGE_SIZE_MASK | ECC_TYPE_MASK | BLOCK_SIZE_MASK);
-+ reg_fmc_cfg |= ecc_reg | page_reg | block_reg;
-+ hifmc_writel(host, FMC_CFG, reg_fmc_cfg);
++ reg_fmc_cfg = hifmc_readl(host, FMC_CFG);
++ reg_fmc_cfg &= ~(PAGE_SIZE_MASK | ECC_TYPE_MASK | BLOCK_SIZE_MASK);
++ reg_fmc_cfg |= ecc_reg | page_reg | block_reg;
++ hifmc_writel(host, FMC_CFG, reg_fmc_cfg);
+
-+ /* Save value of FMC_CFG and FMC_CFG_ECC0 to turn on/off ECC */
-+ host->fmc_cfg = reg_fmc_cfg;
-+ host->fmc_cfg_ecc0 = (host->fmc_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
-+ FMC_PR(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
-+ FMC_CFG, host->fmc_cfg, host->fmc_cfg_ecc0);
++ /* Save value of FMC_CFG and FMC_CFG_ECC0 to turn on/off ECC */
++ host->fmc_cfg = reg_fmc_cfg;
++ host->fmc_cfg_ecc0 = (host->fmc_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
++ FMC_PR(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
++ FMC_CFG, host->fmc_cfg, host->fmc_cfg_ecc0);
+}
+
+/*****************************************************************************/
+static int hifmc100_set_config_info(struct mtd_info *mtd,
-+ struct nand_chip *chip, struct nand_dev_t *nand_dev)
++ struct nand_chip *chip, struct nand_dev_t *nand_dev)
+{
-+ struct hifmc_host *host = chip->priv;
-+ struct nand_config_info *type_info = NULL;
++ struct hifmc_host *host = chip->priv;
++ struct nand_config_info *type_info = NULL;
+
-+ FMC_PR(BT_DBG, "\t*-Start config Block Page OOB and Ecc\n");
++ FMC_PR(BT_DBG, "\t*-Start config Block Page OOB and Ecc\n");
+
-+ type_info = hifmc100_get_config_type_info(mtd, nand_dev);
-+ BUG_ON(!type_info);
++ type_info = hifmc100_get_config_type_info(mtd, nand_dev);
++ BUG_ON(!type_info);
+
-+ FMC_PR(BT_DBG, "\t|-%s Config, PageSize %s EccType %s OOBSize %d\n",
-+ nand_dev->start_type, nand_page_name(type_info->pagetype),
-+ nand_ecc_name(type_info->ecctype), type_info->oobsize);
++ FMC_PR(BT_DBG, "\t|-%s Config, PageSize %s EccType %s OOBSize %d\n",
++ nand_dev->start_type, nand_page_name(type_info->pagetype),
++ nand_ecc_name(type_info->ecctype), type_info->oobsize);
+
-+ /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
-+ hifmc100_set_fmc_cfg_reg(host, type_info, nand_dev);
++ /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
++ hifmc100_set_fmc_cfg_reg(host, type_info, nand_dev);
+
-+ hifmc100_set_oob_info(mtd, type_info, nand_dev);
++ hifmc100_set_oob_info(mtd, type_info, nand_dev);
+
-+ FMC_PR(BT_DBG, "\t*-End config Block Page Oob and Ecc\n");
++ FMC_PR(BT_DBG, "\t*-End config Block Page Oob and Ecc\n");
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+int hifmc100_spi_nand_init(struct nand_chip *chip)
+{
-+ struct hifmc_host *host = chip->priv;
++ struct hifmc_host *host = chip->priv;
+
-+ FMC_PR(BT_DBG, "\t|*-Start hifmc100 SPI Nand init\n");
++ FMC_PR(BT_DBG, "\t|*-Start hifmc100 SPI Nand init\n");
+
-+ /* Set system clock and enable controller */
-+ clk_prepare_enable(host->clk);
++ /* Set system clock and enable controller */
++ clk_prepare_enable(host->clk);
+
-+ /* Switch SPI type to SPI nand */
-+ hifmc100_switch_to_spi_nand(host);
++ /* Switch SPI type to SPI nand */
++ hifmc100_switch_to_spi_nand(host);
+
-+ /* hold on STR mode */
-+ hifmc100_set_str_mode(host);
++ /* hold on STR mode */
++ hifmc100_set_str_mode(host);
+
-+ /* Hifmc host init */
-+ hifmc100_host_init(host);
-+ host->chip = chip;
++ /* Hifmc host init */
++ hifmc100_host_init(host);
++ host->chip = chip;
+
-+ /* Hifmc nand_chip struct init */
-+ hifmc100_chip_init(chip);
++ /* Hifmc nand_chip struct init */
++ hifmc100_chip_init(chip);
+
-+ hifmc_spi_nand_ids_register();
-+ hinfc_param_adjust = hifmc100_set_config_info;
++ hifmc_spi_nand_ids_register();
++ hinfc_param_adjust = hifmc100_set_config_info;
+
-+ FMC_PR(BT_DBG, "\t|*-End hifmc100 SPI Nand init\n");
++ FMC_PR(BT_DBG, "\t|*-End hifmc100 SPI Nand init\n");
+
-+ return 0;
++ return 0;
+}
+#ifdef CONFIG_PM
+/*****************************************************************************/
+int hifmc100_suspend(struct platform_device *pltdev, pm_message_t state)
+{
-+ unsigned int ret;
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
-+ struct hifmc_spi *spi = host->spi;
++ unsigned int ret;
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ struct hifmc_spi *spi = host->spi;
+
-+ mutex_lock(host->lock);
-+ hifmc100_switch_to_spi_nand(host);
++ mutex_lock(host->lock);
++ hifmc100_switch_to_spi_nand(host);
+
-+ ret = spi->driver->wait_ready(spi);
-+ if (ret) {
-+ DB_MSG("Error: wait ready failed!");
-+ return 0;
-+ }
++ ret = spi->driver->wait_ready(spi);
++ if (ret)
++ DB_MSG("Error: wait ready failed!");
+
-+ clk_disable_unprepare(host->clk);
-+ mutex_unlock(host->lock);
++ clk_disable_unprepare(host->clk);
++ mutex_unlock(host->lock);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+int hifmc100_resume(struct platform_device *pltdev)
+{
-+ int cs;
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
-+ struct nand_chip *chip = host->chip;
++ int cs;
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ struct nand_chip *chip = host->chip;
+
-+ mutex_lock(host->lock);
-+ hifmc100_switch_to_spi_nand(host);
-+ clk_prepare_enable(host->clk);
++ mutex_lock(host->lock);
++ hifmc100_switch_to_spi_nand(host);
++ clk_prepare_enable(host->clk);
+
-+ for (cs = 0; cs < chip->numchips; cs++) {
-+ host->send_cmd_reset(host);
-+ }
++ for (cs = 0; cs < chip->numchips; cs++) {
++ host->send_cmd_reset(host);
++ }
+
-+ hifmc100_spi_nand_config(host);
++ hifmc100_spi_nand_config(host);
+
-+ mutex_unlock(host->lock);
-+ return 0;
++ mutex_unlock(host->lock);
++ return 0;
+}
+#endif
+
diff --git a/drivers/mtd/nand/hifmc100/hifmc100.h b/drivers/mtd/nand/hifmc100/hifmc100.h
new file mode 100644
-index 0000000..d0ae0a2
+index 0000000..4bab352
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100/hifmc100.h
@@ -0,0 +1,391 @@
@@ -287120,132 +355163,132 @@ index 0000000..d0ae0a2
+/*****************************************************************************/
+/* SPI general operation parameter */
+struct spi_op {
-+ unsigned char iftype;
-+ unsigned char cmd;
-+ unsigned char dummy;
-+ unsigned int size;
-+ unsigned int clock;
++ unsigned char iftype;
++ unsigned char cmd;
++ unsigned char dummy;
++ unsigned int size;
++ unsigned int clock;
+};
+
+struct spi_drv;
+
+/* SPI interface all operation */
+struct hifmc_spi {
-+ char *name;
-+ int chipselect;
-+ unsigned long long chipsize;
-+ unsigned int erasesize;
++ char *name;
++ int chipselect;
++ unsigned long long chipsize;
++ unsigned int erasesize;
+#define SPI_NOR_3BYTE_ADDR_LEN 3 /* address len 3Bytes */
+#define SPI_NOR_4BYTE_ADDR_LEN 4 /* address len 4Bytes for 32MB */
-+ unsigned int addrcycle;
++ unsigned int addrcycle;
+
-+ struct spi_op read[1];
-+ struct spi_op write[1];
-+ struct spi_op erase[MAX_SPI_OP];
++ struct spi_op read[1];
++ struct spi_op write[1];
++ struct spi_op erase[MAX_SPI_OP];
+
-+ void *host;
++ void *host;
+
-+ struct spi_drv *driver;
++ struct spi_drv *driver;
+};
+
+/* SPI interface special operation function hook */
+struct spi_drv {
-+ int (*wait_ready)(struct hifmc_spi *spi);
-+ int (*write_enable)(struct hifmc_spi *spi);
-+ int (*qe_enable)(struct hifmc_spi *spi);
-+ int (*bus_prepare)(struct hifmc_spi *spi, int op);
-+ int (*entry_4addr)(struct hifmc_spi *spi, int en);
++ int (*wait_ready)(struct hifmc_spi *spi);
++ int (*write_enable)(struct hifmc_spi *spi);
++ int (*qe_enable)(struct hifmc_spi *spi);
++ int (*bus_prepare)(struct hifmc_spi *spi, int op);
++ int (*entry_4addr)(struct hifmc_spi *spi, int en);
+};
+
+struct spi_nand_info {
-+ char *name;
-+ unsigned char id[MAX_SPI_NAND_ID_LEN];
-+ unsigned char id_len;
-+ unsigned long long chipsize;
-+ unsigned int erasesize;
-+ unsigned int pagesize;
-+ unsigned int oobsize;
++ char *name;
++ unsigned char id[MAX_SPI_NAND_ID_LEN];
++ unsigned char id_len;
++ unsigned long long chipsize;
++ unsigned int erasesize;
++ unsigned int pagesize;
++ unsigned int oobsize;
+#define BBP_LAST_PAGE 0x01
+#define BBP_FIRST_PAGE 0x02
-+ unsigned int badblock_pos;
-+ struct spi_op *read[MAX_SPI_OP];
-+ struct spi_op *write[MAX_SPI_OP];
-+ struct spi_op *erase[MAX_SPI_OP];
-+ struct spi_drv *driver;
++ unsigned int badblock_pos;
++ struct spi_op *read[MAX_SPI_OP];
++ struct spi_op *write[MAX_SPI_OP];
++ struct spi_op *erase[MAX_SPI_OP];
++ struct spi_drv *driver;
+};
+
+/*****************************************************************************/
+extern u_char spi_nand_feature_op(struct hifmc_spi *spi, u_char op, u_char addr,
-+ u_char val);
++ u_char val);
+
+/*****************************************************************************/
+struct hifmc_host {
-+ struct mtd_info *mtd;
-+ struct nand_chip *chip;
-+ struct hifmc_spi spi[CONFIG_SPI_NAND_MAX_CHIP_NUM];
-+ struct hifmc_cmd_op cmd_op;
++ struct mtd_info *mtd;
++ struct nand_chip *chip;
++ struct hifmc_spi spi[CONFIG_SPI_NAND_MAX_CHIP_NUM];
++ struct hifmc_cmd_op cmd_op;
+
-+ void __iomem *iobase;
-+ void __iomem *regbase;
-+ struct clk *clk;
-+ u32 clkrate;
++ void __iomem *iobase;
++ void __iomem *regbase;
++ struct clk *clk;
++ u32 clkrate;
+
-+ unsigned int fmc_cfg;
-+ unsigned int fmc_cfg_ecc0;
++ unsigned int fmc_cfg;
++ unsigned int fmc_cfg_ecc0;
+
-+ unsigned int offset;
++ unsigned int offset;
+
-+ struct device *dev;
-+ struct mutex *lock;
++ struct device *dev;
++ struct mutex *lock;
+
-+ /* This is maybe an un-aligment address, only for malloc or free */
-+ char *buforg;
-+ char *buffer;
++ /* This is maybe an un-aligment address, only for malloc or free */
++ char *buforg;
++ char *buffer;
+
+#ifdef CONFIG_64BIT
-+ unsigned long long dma_buffer;
-+ unsigned long long dma_oob;
++ unsigned long long dma_buffer;
++ unsigned long long dma_oob;
+#else
-+ unsigned int dma_buffer;
-+ unsigned int dma_oob;
++ unsigned int dma_buffer;
++ unsigned int dma_oob;
+#endif
+
-+ unsigned int addr_cycle;
-+ unsigned int addr_value[2];
-+ unsigned int cache_addr_value[2];
++ unsigned int addr_cycle;
++ unsigned int addr_value[2];
++ unsigned int cache_addr_value[2];
+
-+ unsigned int column;
-+ unsigned int block_page_mask;
++ unsigned int column;
++ unsigned int block_page_mask;
+
-+ unsigned int ecctype;
-+ unsigned int pagesize;
-+ unsigned int oobsize;
++ unsigned int ecctype;
++ unsigned int pagesize;
++ unsigned int oobsize;
+
-+ int add_partition;
++ int add_partition;
+
-+ int need_rr_data;
++ int need_rr_data;
+#define HIFMC100_READ_RETRY_DATA_LEN 128
-+ char rr_data[HIFMC100_READ_RETRY_DATA_LEN];
-+ struct read_retry_t *read_retry;
++ char rr_data[HIFMC100_READ_RETRY_DATA_LEN];
++ struct read_retry_t *read_retry;
+
-+ int version;
++ int version;
+
-+ /* BOOTROM read two bytes to detect the bad block flag */
++ /* BOOTROM read two bytes to detect the bad block flag */
+#define HIFMC_BAD_BLOCK_POS 0
-+ unsigned char *bbm; /* nand bad block mark */
-+ unsigned short *epm; /* nand empty page mark */
++ unsigned char *bbm; /* nand bad block mark */
++ unsigned short *epm; /* nand empty page mark */
+
-+ unsigned int uc_er;
++ unsigned int uc_er;
+
-+ void (*send_cmd_write)(struct hifmc_host *host);
-+ void (*send_cmd_status)(struct hifmc_host *host);
-+ void (*send_cmd_read)(struct hifmc_host *host);
-+ void (*send_cmd_erase)(struct hifmc_host *host);
-+ void (*send_cmd_readid)(struct hifmc_host *host);
-+ void (*send_cmd_reset)(struct hifmc_host *host);
++ void (*send_cmd_write)(struct hifmc_host *host);
++ void (*send_cmd_status)(struct hifmc_host *host);
++ void (*send_cmd_read)(struct hifmc_host *host);
++ void (*send_cmd_erase)(struct hifmc_host *host);
++ void (*send_cmd_readid)(struct hifmc_host *host);
++ void (*send_cmd_reset)(struct hifmc_host *host);
+#ifdef CONFIG_PM
-+ int (*suspend)(struct platform_device *pltdev, pm_message_t state);
-+ int (*resume)(struct platform_device *pltdev);
++ int (*suspend)(struct platform_device *pltdev, pm_message_t state);
++ int (*resume)(struct platform_device *pltdev);
+#endif
+};
+
@@ -287269,7 +355312,7 @@ index 0000000..d0ae0a2
+#endif /* End of __HIFMC100_H__ */
diff --git a/drivers/mtd/nand/hifmc100/hifmc100_os.c b/drivers/mtd/nand/hifmc100/hifmc100_os.c
new file mode 100644
-index 0000000..eaab37c
+index 0000000..f1029d2
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100/hifmc100_os.c
@@ -0,0 +1,239 @@
@@ -287312,199 +355355,199 @@ index 0000000..eaab37c
+/*****************************************************************************/
+static int hifmc100_spi_nand_pre_probe(struct nand_chip *chip)
+{
-+ uint8_t nand_maf_id;
-+ struct hifmc_host *host = chip->priv;
++ uint8_t nand_maf_id;
++ struct hifmc_host *host = chip->priv;
+
-+ /* Reset the chip first */
-+ host->send_cmd_reset(host);
-+ udelay(1000);
++ /* Reset the chip first */
++ host->send_cmd_reset(host);
++ udelay(1000);
+
-+ /* Check the ID */
-+ host->offset = 0;
-+ memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
-+ host->send_cmd_readid(host);
-+ nand_maf_id = hifmc_readb(chip->IO_ADDR_R);
++ /* Check the ID */
++ host->offset = 0;
++ memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
++ host->send_cmd_readid(host);
++ nand_maf_id = hifmc_readb(chip->IO_ADDR_R);
+
-+ if (nand_maf_id == 0x00 || nand_maf_id == 0xff) {
-+ printk("Cannot found a valid SPI Nand Device\n");
-+ return 1;
-+ }
++ if (nand_maf_id == 0x00 || nand_maf_id == 0xff) {
++ printk("Cannot found a valid SPI Nand Device\n");
++ return 1;
++ }
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+static int hifmc_nand_scan(struct mtd_info *mtd)
+{
-+ int result = 0;
-+ unsigned char cs, chip_num = CONFIG_SPI_NAND_MAX_CHIP_NUM;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ int result = 0;
++ unsigned char cs, chip_num = CONFIG_SPI_NAND_MAX_CHIP_NUM;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ for (cs = 0; chip_num && (cs < HIFMC_MAX_CHIP_NUM); cs++) {
-+ if (hifmc_cs_user[cs]) {
-+ FMC_PR(BT_DBG, "\t\t*-Current CS(%d) is occupied.\n",
-+ cs);
-+ continue;
-+ }
++ for (cs = 0; chip_num && (cs < HIFMC_MAX_CHIP_NUM); cs++) {
++ if (hifmc_cs_user[cs]) {
++ FMC_PR(BT_DBG, "\t\t*-Current CS(%d) is occupied.\n",
++ cs);
++ continue;
++ }
+
-+ host->cmd_op.cs = cs;
++ host->cmd_op.cs = cs;
+
-+ if (hifmc100_spi_nand_pre_probe(chip)) {
-+ return -ENODEV;
-+ }
++ if (hifmc100_spi_nand_pre_probe(chip)) {
++ return -ENODEV;
++ }
+
-+ FMC_PR(BT_DBG, "\t\t*-Scan SPI nand flash on CS: %d\n", cs);
-+ if (nand_scan(mtd, chip_num)) {
-+ continue;
-+ }
-+ chip_num--;
-+ }
++ FMC_PR(BT_DBG, "\t\t*-Scan SPI nand flash on CS: %d\n", cs);
++ if (nand_scan(mtd, chip_num)) {
++ continue;
++ }
++ chip_num--;
++ }
+
-+ if (chip_num == CONFIG_SPI_NAND_MAX_CHIP_NUM) {
-+ result = -ENXIO;
-+ } else {
-+ result = 0;
-+ }
++ if (chip_num == CONFIG_SPI_NAND_MAX_CHIP_NUM) {
++ result = -ENXIO;
++ } else {
++ result = 0;
++ }
+
-+ return result;
++ return result;
+}
+
+/*****************************************************************************/
+static int hisi_spi_nand_probe(struct platform_device *pltdev)
+{
-+ int len, result = 0;
-+ struct hifmc_host *host;
-+ struct nand_chip *chip;
-+ struct mtd_info *mtd;
-+ struct device *dev = &pltdev->dev;
-+ struct device_node *np = NULL;
-+ struct hisi_fmc *fmc = dev_get_drvdata(dev->parent);
++ int len, result = 0;
++ struct hifmc_host *host = NULL;
++ struct nand_chip *chip = NULL;
++ struct mtd_info *mtd = NULL;
++ struct device *dev = &pltdev->dev;
++ struct device_node *np = NULL;
++ struct hisi_fmc *fmc = dev_get_drvdata(dev->parent);
+
-+ FMC_PR(BT_DBG, "\t*-Start SPI Nand flash driver probe\n");
++ FMC_PR(BT_DBG, "\t*-Start SPI Nand flash driver probe\n");
+
-+ if (!fmc) {
-+ dev_err(dev, "get mfd fmc devices failed\n");
-+ return -ENXIO;
-+ }
++ if (!fmc) {
++ dev_err(dev, "get mfd fmc devices failed\n");
++ return -ENXIO;
++ }
+
-+ len = sizeof(struct hifmc_host) + sizeof(struct nand_chip)
-+ + sizeof(struct mtd_info);
-+ host = devm_kzalloc(dev, len, GFP_KERNEL);
-+ if (!host) {
-+ return -ENOMEM;
-+ }
-+ memset((char *)host, 0, len);
++ len = sizeof(struct hifmc_host) + sizeof(struct nand_chip)
++ + sizeof(struct mtd_info);
++ host = devm_kzalloc(dev, len, GFP_KERNEL);
++ if (!host) {
++ return -ENOMEM;
++ }
++ memset((char *)host, 0, len);
+
-+ platform_set_drvdata(pltdev, host);
-+ host->dev = &pltdev->dev;
++ platform_set_drvdata(pltdev, host);
++ host->dev = &pltdev->dev;
+
-+ host->chip = chip = (struct nand_chip *)&host[1];
-+ host->mtd = mtd = nand_to_mtd(chip);
++ host->chip = chip = (struct nand_chip *)&host[1];
++ host->mtd = mtd = nand_to_mtd(chip);
+
-+ host->regbase = fmc->regbase;
-+ host->iobase = fmc->iobase;
-+ host->clk = fmc->clk;
-+ host->lock = &fmc->lock;
-+ host->buffer = fmc->buffer;
-+ host->dma_buffer = fmc->dma_buffer;
++ host->regbase = fmc->regbase;
++ host->iobase = fmc->iobase;
++ host->clk = fmc->clk;
++ host->lock = &fmc->lock;
++ host->buffer = fmc->buffer;
++ host->dma_buffer = fmc->dma_buffer;
+
-+ memset((char *)host->iobase, 0xff, fmc->dma_len);
-+ chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
++ memset((char *)host->iobase, 0xff, fmc->dma_len);
++ chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
+
-+ chip->priv = host;
-+ result = hifmc100_spi_nand_init(chip);
-+ if (result) {
-+ FMC_PR(BT_DBG, "\t|-SPI Nand init failed, ret: %d\n", result);
-+ result = -ENODEV;
-+ goto fail;
-+ }
++ chip->priv = host;
++ result = hifmc100_spi_nand_init(chip);
++ if (result) {
++ FMC_PR(BT_DBG, "\t|-SPI Nand init failed, ret: %d\n", result);
++ result = -ENODEV;
++ goto fail;
++ }
+
-+ np = of_get_next_available_child(dev->of_node, NULL);
-+ mtd->name = np->name;
-+ mtd->type = MTD_NANDFLASH;
-+ mtd->priv = chip;
-+ mtd->owner = THIS_MODULE;
++ np = of_get_next_available_child(dev->of_node, NULL);
++ mtd->name = np->name;
++ mtd->type = MTD_NANDFLASH;
++ mtd->priv = chip;
++ mtd->owner = THIS_MODULE;
+
-+ result = of_property_read_u32(np, "spi-max-frequency", &host->clkrate);
-+ if (result) {
-+ goto fail;
-+ }
++ result = of_property_read_u32(np, "spi-max-frequency", &host->clkrate);
++ if (result) {
++ goto fail;
++ }
+
-+ result = hifmc_nand_scan(mtd);
-+ if (result) {
-+ FMC_PR(BT_DBG, "\t|-Scan SPI Nand failed.\n");
-+ goto fail;
-+ }
++ result = hifmc_nand_scan(mtd);
++ if (result) {
++ FMC_PR(BT_DBG, "\t|-Scan SPI Nand failed.\n");
++ goto fail;
++ }
+
-+ result = mtd_device_register(mtd, NULL, 0);
-+ if (!result) {
-+ FMC_PR(BT_DBG, "\t*-End driver probe !!\n");
-+ return 0;
-+ }
++ result = mtd_device_register(mtd, NULL, 0);
++ if (!result) {
++ FMC_PR(BT_DBG, "\t*-End driver probe !!\n");
++ return 0;
++ }
+
-+ result = -ENODEV;
++ result = -ENODEV;
+fail:
-+ clk_disable_unprepare(host->clk);
-+ nand_release(mtd);
++ clk_disable_unprepare(host->clk);
++ nand_release(mtd);
+
-+ DB_MSG("Error: driver probe, result: %d\n", result);
-+ return result;
++ DB_MSG("Error: driver probe, result: %d\n", result);
++ return result;
+}
+
+/*****************************************************************************/
+static int hisi_spi_nand_remove(struct platform_device *pltdev)
+{
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
+
-+ clk_disable_unprepare(host->clk);
-+ nand_release(host->mtd);
++ clk_disable_unprepare(host->clk);
++ nand_release(host->mtd);
+
-+ return 0;
++ return 0;
+}
+
+#ifdef CONFIG_PM
+/*****************************************************************************/
+static int hifmc100_os_suspend(struct platform_device *pltdev,
-+ pm_message_t state)
++ pm_message_t state)
+{
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
+
-+ if (host && host->suspend) {
-+ return (host->suspend)(pltdev, state);
-+ }
++ if (host && host->suspend) {
++ return (host->suspend)(pltdev, state);
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+static int hifmc100_os_resume(struct platform_device *pltdev)
+{
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
+
-+ if (host && host->resume) {
-+ return (host->resume)(pltdev);
-+ }
++ if (host && host->resume) {
++ return (host->resume)(pltdev);
++ }
+
-+ return 0;
++ return 0;
+}
+#endif /* End of CONFIG_PM */
+/*****************************************************************************/
+static const struct of_device_id hisi_spi_nand_dt_ids[] = {
-+ { .compatible = "hisilicon,hisi-spi-nand"},
-+ { /* sentinel */ }
++ { .compatible = "hisilicon,hisi-spi-nand"},
++ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, hisi_spi_nand_dt_ids);
+
+static struct platform_driver hisi_spi_nand_driver = {
-+ .driver = {
-+ .name = "hisi_spi_nand",
-+ .of_match_table = hisi_spi_nand_dt_ids,
-+ },
-+ .probe = hisi_spi_nand_probe,
-+ .remove = hisi_spi_nand_remove,
++ .driver = {
++ .name = "hisi_spi_nand",
++ .of_match_table = hisi_spi_nand_dt_ids,
++ },
++ .probe = hisi_spi_nand_probe,
++ .remove = hisi_spi_nand_remove,
+#ifdef CONFIG_PM
-+ .suspend = hifmc100_os_suspend,
-+ .resume = hifmc100_os_resume,
++ .suspend = hifmc100_os_suspend,
++ .resume = hifmc100_os_resume,
+#endif
+};
+module_platform_driver(hisi_spi_nand_driver);
@@ -287514,7 +355557,7 @@ index 0000000..eaab37c
+MODULE_DESCRIPTION("Hisilicon Flash Memory Controller V100 SPI Nand Driver");
diff --git a/drivers/mtd/nand/hifmc100/hifmc100_spi_general.c b/drivers/mtd/nand/hifmc100/hifmc100_spi_general.c
new file mode 100644
-index 0000000..0c7dad9
+index 0000000..1527b5c
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100/hifmc100_spi_general.c
@@ -0,0 +1,262 @@
@@ -287542,84 +355585,84 @@ index 0000000..0c7dad9
+ Send set/get features command to SPI Nand flash
+*/
+u_char spi_nand_feature_op(struct hifmc_spi *spi, u_char op, u_char addr,
-+ u_char val)
++ u_char val)
+{
-+ unsigned int reg;
-+ const char *str[] = {"Get", "Set"};
-+ struct hifmc_host *host = (struct hifmc_host *)spi->host;
++ unsigned int reg;
++ const char *str[] = {"Get", "Set"};
++ struct hifmc_host *host = (struct hifmc_host *)spi->host;
+
-+ if ((op == GET_OP) && (STATUS_ADDR == addr)) {
-+ if (SR_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(SR_DBG, "\t\t|*-Start Get Status\n");
++ if ((op == GET_OP) && (STATUS_ADDR == addr)) {
++ if (SR_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(SR_DBG, "\t\t|*-Start Get Status\n");
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(SR_DBG, "\t\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(SR_DBG, "\t\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_OP_READ_STATUS_EN | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(SR_DBG, "\t\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
++ reg = FMC_OP_READ_STATUS_EN | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(SR_DBG, "\t\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ val = hifmc_readl(host, FMC_STATUS);
-+ FMC_PR(SR_DBG, "\t\t|*-End Get Status, result: %#x\n", val);
++ val = hifmc_readl(host, FMC_STATUS);
++ FMC_PR(SR_DBG, "\t\t|*-End Get Status, result: %#x\n", val);
+
-+ return val;
-+ }
++ return val;
++ }
+
-+ FMC_PR(FT_DBG, "\t|||*-Start %s feature, addr[%#x]\n", str[op], addr);
++ FMC_PR(FT_DBG, "\t|||*-Start %s feature, addr[%#x]\n", str[op], addr);
+
-+ hifmc100_ecc0_switch(host, ENABLE);
++ hifmc100_ecc0_switch(host, ENABLE);
+
-+ reg = FMC_CMD_CMD1(op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(FT_DBG, "\t||||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD1(op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(FT_DBG, "\t||||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ hifmc_writel(host, FMC_ADDRL, addr);
-+ FMC_PR(FT_DBG, "\t||||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, addr);
++ hifmc_writel(host, FMC_ADDRL, addr);
++ FMC_PR(FT_DBG, "\t||||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, addr);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_ADDR_NUM(FEATURES_OP_ADDR_NUM)
-+ | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(FT_DBG, "\t||||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_ADDR_NUM(FEATURES_OP_ADDR_NUM)
++ | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(FT_DBG, "\t||||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_DATA_NUM_CNT(FEATURES_DATA_LEN);
-+ hifmc_writel(host, FMC_DATA_NUM, reg);
-+ FMC_PR(FT_DBG, "\t||||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
++ reg = FMC_DATA_NUM_CNT(FEATURES_DATA_LEN);
++ hifmc_writel(host, FMC_DATA_NUM, reg);
++ FMC_PR(FT_DBG, "\t||||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
+
-+ reg = FMC_OP_CMD1_EN
-+ | FMC_OP_ADDR_EN
-+ | FMC_OP_REG_OP_START;
++ reg = FMC_OP_CMD1_EN
++ | FMC_OP_ADDR_EN
++ | FMC_OP_REG_OP_START;
+
-+ if (op == SET_OP) {
-+ reg |= FMC_OP_WRITE_DATA_EN;
-+ hifmc_writeb(val, host->iobase);
-+ FMC_PR(FT_DBG, "\t||||-Write IO[%#lx]%#x\n", (long)host->iobase,
-+ *(u_char *)host->iobase);
-+ } else {
-+ reg |= FMC_OP_READ_DATA_EN;
-+ }
++ if (op == SET_OP) {
++ reg |= FMC_OP_WRITE_DATA_EN;
++ hifmc_writeb(val, host->iobase);
++ FMC_PR(FT_DBG, "\t||||-Write IO[%#lx]%#x\n", (long)host->iobase,
++ *(u_char *)host->iobase);
++ } else {
++ reg |= FMC_OP_READ_DATA_EN;
++ }
+
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(FT_DBG, "\t||||-Set OP[%#x]%#x\n", FMC_OP, reg);
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(FT_DBG, "\t||||-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ if (op == GET_OP) {
-+ val = hifmc_readb(host->iobase);
-+ FMC_PR(FT_DBG, "\t||||-Read IO[%#lx]%#x\n", (long)host->iobase,
-+ *(u_char *)host->iobase);
-+ }
++ if (op == GET_OP) {
++ val = hifmc_readb(host->iobase);
++ FMC_PR(FT_DBG, "\t||||-Read IO[%#lx]%#x\n", (long)host->iobase,
++ *(u_char *)host->iobase);
++ }
+
-+ hifmc100_ecc0_switch(host, DISABLE);
++ hifmc100_ecc0_switch(host, DISABLE);
+
-+ FMC_PR(FT_DBG, "\t|||*-End %s Feature[%#x]:%#x\n", str[op], addr, val);
++ FMC_PR(FT_DBG, "\t|||*-End %s Feature[%#x]:%#x\n", str[op], addr, val);
+
-+ return val;
++ return val;
+}
+
+/*****************************************************************************/
@@ -287628,31 +355671,31 @@ index 0000000..0c7dad9
+*/
+static int spi_general_wait_ready(struct hifmc_spi *spi)
+{
-+ unsigned char status;
-+ unsigned long deadline = jiffies + FMC_MAX_READY_WAIT_JIFFIES;
-+ struct hifmc_host *host = (struct hifmc_host *)spi->host;
++ unsigned char status;
++ unsigned long deadline = jiffies + FMC_MAX_READY_WAIT_JIFFIES;
++ struct hifmc_host *host = (struct hifmc_host *)spi->host;
+
-+ do {
-+ status = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
-+ if (!(status & STATUS_OIP_MASK)) {
-+ if ((host->cmd_op.l_cmd == NAND_CMD_ERASE2)
-+ && (status & STATUS_E_FAIL_MASK)) {
-+ return status;
-+ }
-+ if ((host->cmd_op.l_cmd == NAND_CMD_PAGEPROG)
-+ && (status & STATUS_P_FAIL_MASK)) {
-+ return status;
-+ }
-+ return 0;
-+ }
++ do {
++ status = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
++ if (!(status & STATUS_OIP_MASK)) {
++ if ((host->cmd_op.l_cmd == NAND_CMD_ERASE2)
++ && (status & STATUS_E_FAIL_MASK)) {
++ return status;
++ }
++ if ((host->cmd_op.l_cmd == NAND_CMD_PAGEPROG)
++ && (status & STATUS_P_FAIL_MASK)) {
++ return status;
++ }
++ return 0;
++ }
+
-+ cond_resched();
++ cond_resched();
+
-+ } while (!time_after_eq(jiffies, deadline));
++ } while (!time_after_eq(jiffies, deadline));
+
-+ DB_MSG("Error: SPI Nand wait ready timeout, status: %#x\n", status);
++ DB_MSG("Error: SPI Nand wait ready timeout, status: %#x\n", status);
+
-+ return 1;
++ return 1;
+}
+
+/*****************************************************************************/
@@ -287661,58 +355704,58 @@ index 0000000..0c7dad9
+*/
+static int spi_general_write_enable(struct hifmc_spi *spi)
+{
-+ unsigned int reg;
-+ struct hifmc_host *host = (struct hifmc_host *)spi->host;
++ unsigned int reg;
++ struct hifmc_host *host = (struct hifmc_host *)spi->host;
+
-+ if (WE_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(WE_DBG, "\t|*-Start Write Enable\n");
++ if (WE_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(WE_DBG, "\t|*-Start Write Enable\n");
+
-+ reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
-+ if (reg & STATUS_WEL_MASK) {
-+ FMC_PR(WE_DBG, "\t||-Write Enable was opened! reg: %#x\n",
-+ reg);
-+ return 0;
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
++ if (reg & STATUS_WEL_MASK) {
++ FMC_PR(WE_DBG, "\t||-Write Enable was opened! reg: %#x\n",
++ reg);
++ return 0;
++ }
+
-+ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
-+ FMC_PR(WE_DBG, "\t||-Get GLOBAL_CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
-+ if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
-+ reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
-+ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
-+ FMC_PR(WE_DBG, "\t||-Set GLOBAL_CFG[%#x]%#x\n",
-+ FMC_GLOBAL_CFG, reg);
-+ }
++ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
++ FMC_PR(WE_DBG, "\t||-Get GLOBAL_CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
++ if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
++ reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
++ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
++ FMC_PR(WE_DBG, "\t||-Set GLOBAL_CFG[%#x]%#x\n",
++ FMC_GLOBAL_CFG, reg);
++ }
+
-+ reg = FMC_CMD_CMD1(SPI_CMD_WREN);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(WE_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD1(SPI_CMD_WREN);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(WE_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(WE_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(WE_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(WE_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
++ reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(WE_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
+#if WE_DBG
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
-+ if (reg & STATUS_WEL_MASK) {
-+ FMC_PR(WE_DBG, "\t||-Write Enable success. reg: %#x\n", reg);
-+ } else {
-+ DB_MSG("Error: Write Enable failed! reg: %#x\n", reg);
-+ return reg;
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
++ if (reg & STATUS_WEL_MASK) {
++ FMC_PR(WE_DBG, "\t||-Write Enable success. reg: %#x\n", reg);
++ } else {
++ DB_MSG("Error: Write Enable failed! reg: %#x\n", reg);
++ return reg;
++ }
+#endif
+
-+ FMC_PR(WE_DBG, "\t|*-End Write Enable\n");
-+ return 0;
++ FMC_PR(WE_DBG, "\t|*-End Write Enable\n");
++ return 0;
+}
+
+/*****************************************************************************/
@@ -287721,19 +355764,19 @@ index 0000000..0c7dad9
+*/
+static int spi_is_quad(struct hifmc_spi *spi)
+{
-+ const char *if_str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
++ const char *if_str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
+
-+ FMC_PR(QE_DBG, "\t\t|||*-SPI read iftype: %s write iftype: %s\n",
-+ if_str[spi->read->iftype], if_str[spi->write->iftype]);
++ FMC_PR(QE_DBG, "\t\t|||*-SPI read iftype: %s write iftype: %s\n",
++ if_str[spi->read->iftype], if_str[spi->write->iftype]);
+
-+ if ((spi->read->iftype == IF_TYPE_QUAD)
-+ || (spi->read->iftype == IF_TYPE_QIO)
-+ || (spi->write->iftype == IF_TYPE_QUAD)
-+ || (spi->write->iftype == IF_TYPE_QIO)) {
-+ return 1;
-+ }
++ if ((spi->read->iftype == IF_TYPE_QUAD)
++ || (spi->read->iftype == IF_TYPE_QIO)
++ || (spi->write->iftype == IF_TYPE_QUAD)
++ || (spi->write->iftype == IF_TYPE_QIO)) {
++ return 1;
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -287742,50 +355785,50 @@ index 0000000..0c7dad9
+*/
+static int spi_general_qe_enable(struct hifmc_spi *spi)
+{
-+ unsigned int reg, op;
-+ const char *str[] = {"Disable", "Enable"};
++ unsigned int reg, op;
++ const char *str[] = {"Disable", "Enable"};
+
-+ FMC_PR(QE_DBG, "\t||*-Start SPI Nand flash QE\n");
++ FMC_PR(QE_DBG, "\t||*-Start SPI Nand flash QE\n");
+
-+ op = spi_is_quad(spi);
++ op = spi_is_quad(spi);
+
-+ FMC_PR(QE_DBG, "\t|||*-End Quad check, SPI Nand %s Quad.\n", str[op]);
++ FMC_PR(QE_DBG, "\t|||*-End Quad check, SPI Nand %s Quad.\n", str[op]);
+
-+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
-+ FMC_PR(QE_DBG, "\t|||-Get [%#x]feature: %#x\n", FEATURE_ADDR, reg);
-+ if ((reg & FEATURE_QE_ENABLE) == op) {
-+ FMC_PR(QE_DBG, "\t||*-SPI Nand quad was %sd!\n", str[op]);
-+ return op;
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
++ FMC_PR(QE_DBG, "\t|||-Get [%#x]feature: %#x\n", FEATURE_ADDR, reg);
++ if ((reg & FEATURE_QE_ENABLE) == op) {
++ FMC_PR(QE_DBG, "\t||*-SPI Nand quad was %sd!\n", str[op]);
++ return op;
++ }
+
-+ if (op == ENABLE) {
-+ reg |= FEATURE_QE_ENABLE;
-+ } else {
-+ reg &= ~FEATURE_QE_ENABLE;
-+ }
++ if (op == ENABLE) {
++ reg |= FEATURE_QE_ENABLE;
++ } else {
++ reg &= ~FEATURE_QE_ENABLE;
++ }
+
-+ spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
-+ FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad\n", str[op]);
++ spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
++ FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad\n", str[op]);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
-+ if ((reg & FEATURE_QE_ENABLE) == op) {
-+ FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad succeed!\n", str[op]);
-+ } else {
-+ DB_MSG("Error: %s Quad failed! reg: %#x\n", str[op], reg);
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
++ if ((reg & FEATURE_QE_ENABLE) == op) {
++ FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad succeed!\n", str[op]);
++ } else {
++ DB_MSG("Error: %s Quad failed! reg: %#x\n", str[op], reg);
++ }
+
-+ FMC_PR(QE_DBG, "\t||*-End SPI Nand %s Quad.\n", str[op]);
++ FMC_PR(QE_DBG, "\t||*-End SPI Nand %s Quad.\n", str[op]);
+
-+ return op;
++ return op;
+}
diff --git a/drivers/mtd/nand/hifmc100/hifmc_spi_nand_ids.c b/drivers/mtd/nand/hifmc100/hifmc_spi_nand_ids.c
new file mode 100644
-index 0000000..cd89d0e
+index 0000000..cc3ce11
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100/hifmc_spi_nand_ids.c
-@@ -0,0 +1,1915 @@
+@@ -0,0 +1,2082 @@
+/*
+ * The Flash Memory Controller v100 Device Driver for hisilicon
+ *
@@ -287828,32 +355871,41 @@ index 0000000..cd89d0e
+SET_READ_FAST(1, INFINITE, 104);
+SET_READ_FAST(1, INFINITE, 108);
+SET_READ_FAST(1, INFINITE, 120);
++SET_READ_FAST(1, INFINITE, 133);
+
+SET_READ_DUAL(1, INFINITE, 80);
+SET_READ_DUAL(1, INFINITE, 100);
+SET_READ_DUAL(1, INFINITE, 104);
+SET_READ_DUAL(1, INFINITE, 108);
+SET_READ_DUAL(1, INFINITE, 120);
++SET_READ_DUAL(1, INFINITE, 133);
+
++SET_READ_DUAL_ADDR(1, INFINITE, 40);
+SET_READ_DUAL_ADDR(1, INFINITE, 80);
++SET_READ_DUAL_ADDR(2, INFINITE, 80);
+SET_READ_DUAL_ADDR(1, INFINITE, 100);
+SET_READ_DUAL_ADDR(1, INFINITE, 104);
+SET_READ_DUAL_ADDR(1, INFINITE, 108);
+SET_READ_DUAL_ADDR(1, INFINITE, 120);
++SET_READ_DUAL_ADDR(2, INFINITE, 104);
+
+SET_READ_QUAD(1, INFINITE, 80);
+SET_READ_QUAD(1, INFINITE, 100);
+SET_READ_QUAD(1, INFINITE, 104);
+SET_READ_QUAD(1, INFINITE, 108);
+SET_READ_QUAD(1, INFINITE, 120);
++SET_READ_QUAD(1, INFINITE, 133);
+
++SET_READ_QUAD_ADDR(2, INFINITE, 40);
+SET_READ_QUAD_ADDR(1, INFINITE, 80);
+SET_READ_QUAD_ADDR(2, INFINITE, 80);
++SET_READ_QUAD_ADDR(4, INFINITE, 80);
+SET_READ_QUAD_ADDR(1, INFINITE, 100);
+SET_READ_QUAD_ADDR(1, INFINITE, 104);
+SET_READ_QUAD_ADDR(2, INFINITE, 104);
+SET_READ_QUAD_ADDR(1, INFINITE, 108);
+SET_READ_QUAD_ADDR(1, INFINITE, 120);
++SET_READ_QUAD_ADDR(4, INFINITE, 104);
+
+/*****************************************************************************/
+SET_WRITE_STD(0, 256, 24);
@@ -287861,12 +355913,14 @@ index 0000000..cd89d0e
+SET_WRITE_STD(0, 256, 80);
+SET_WRITE_STD(0, 256, 100);
+SET_WRITE_STD(0, 256, 104);
++SET_WRITE_STD(0, 256, 133);
+
+SET_WRITE_QUAD(0, 256, 80);
+SET_WRITE_QUAD(0, 256, 100);
+SET_WRITE_QUAD(0, 256, 104);
+SET_WRITE_QUAD(0, 256, 108);
+SET_WRITE_QUAD(0, 256, 120);
++SET_WRITE_QUAD(0, 256, 133);
+
+/*****************************************************************************/
+SET_ERASE_SECTOR_128K(0, _128K, 24);
@@ -287879,19 +355933,20 @@ index 0000000..cd89d0e
+SET_ERASE_SECTOR_256K(0, _256K, 80);
+SET_ERASE_SECTOR_256K(0, _256K, 100);
+SET_ERASE_SECTOR_256K(0, _256K, 104);
++SET_ERASE_SECTOR_256K(0, _256K, 133);
+
+/*****************************************************************************/
+#include "hifmc100_spi_general.c"
+static struct spi_drv spi_driver_general = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .qe_enable = spi_general_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .qe_enable = spi_general_qe_enable,
+};
+
+/* some spi nand flash default QUAD enable, needn't to set qe enable */
+static struct spi_drv spi_driver_no_qe = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
+};
+
+/*****************************************************************************/
@@ -287902,15 +355957,17 @@ index 0000000..cd89d0e
+ * 1.0 ESMT F50L512M41A 64MB Add 5 chip
+ * GD 5F1GQ4UAYIG 128MB
+ * GD 5F2GQ4UAYIG 256MB
++ * GD GD5F2GQ5UEYIG 256MB
+ * GD 5F4GQ4UAYIG 512MB
+ * GD 5F4GQ4UBYIG 512MB
+ * GD 5F1GQ4RB9IG 128MB
+ * GD 5F1GQ4UEYIHY 128MB
+ * 1.1 ESMT F50L1G41A 128MB Add 2 chip
+ * Winbond W25N01GV 128MB
-+ * Winbond W25N02JWZEIF 256MB
++ * Winbond W25N02JWZEIF 256MB
+ * 1.2 GD 5F1GQ4UBYIG 128MB Add 2 chip
+ * GD 5F2GQ4U9IGR/BYIG 256MB
++ * GD 1.8V 5F4GQ6RE9IG 512MB
+ * 1.3 ATO ATO25D1GA 128MB Add 1 chip
+ * 1.4 MXIC MX35LF1GE4AB 128MB Add 2 chip
+ * MXIC MX35LF2GE4AB 256MB (SOP-16Pin)
@@ -287938,81 +355995,420 @@ index 0000000..cd89d0e
+ * Micron 1.8V MT29F1G01ABB 128MB
+ * Micron 1.8V MT29F2G01ABB 256MB
+ * 2.7 Dosilicon DS35Q1GA-IB 128MB Add 2 chip
-+ * Dosilicon DS35Q2GA-IB 256MB
++ * Dosilicon DS35Q2GA-IB 256MB
+ * GD 5F1GQ4RB9IGR 128MB
+ * Micron MT29F4G01ADAG 512MB 3.3V Add 1 chip
+ * GD 1.8V 5F4GQ4RBYIG 512MB Add 1 chip
+ * Etron 1.8V EM78D044VCF-H 256MB
++ * Etron 3.3V EM73C044VCC-H 128MB
+ * XTX 3.3V XT26G01B 1Gbit 128MB
-+ * Micron MT29F4G01ABBFDW 512MB 1.8V
++ * Micron MT29F4G01ABBFDW 512MB 1.8V
++ * FM FM25S01-DND-A-G 128MB 3.3V
++ * FM FM25S01A 128MB 3.3V
+ ******************************************************************************/
+struct spi_nand_info hifmc_spi_nand_flash_table[] = {
-+ /* Micron MT29F1G01ABA 1GBit */
-+ {
-+ .name = "MT29F1G01ABA",
-+ .id = {0x2C, 0x14},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(2, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
++ /* Micron MT29F1G01ABA 1GBit */
++ {
++ .name = "MT29F1G01ABA",
++ .id = {0x2C, 0x14},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(2, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
+
-+ /* Micron MT29F1G01ABB 1GBit 1.8V */
-+ {
-+ .name = "MT29F1G01ABB",
-+ .id = {0x2C, 0x15},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(2, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
++ /* Micron MT29F1G01ABB 1GBit 1.8V */
++ {
++ .name = "MT29F1G01ABB",
++ .id = {0x2C, 0x15},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(2, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
+
-+ /* Micron MT29F2G01ABA 2GBit */
-+ {
-+ .name = "MT29F2G01ABA",
-+ .id = {0x2C, 0x24},
++ /* Micron MT29F2G01ABA 2GBit */
++ {
++ .name = "MT29F2G01ABA",
++ .id = {0x2C, 0x24},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(2, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 108),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* Micron MT29F2G01ABB 2GBit 1.8V */
++ {
++ .name = "MT29F2G01ABB",
++ .id = {0x2C, 0x25},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(2, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* Micron MT29F4G01ADAG 4GBit 3.3V */
++ {
++ .name = "MT29F4G01ADAG",
++ .id = {0x2C, 0x36},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(2, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 108),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* ESMT F50L512M41A 512Mbit */
++ {
++ .name = "F50L512M41A",
++ .id = {0xC8, 0x20},
++ .id_len = 2,
++ .chipsize = _64M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* ESMT F50L1G41A 1Gbit */
++ {
++ .name = "F50L1G41A",
++ .id = {0xC8, 0x21},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* GD 3.3v GD5F1GQ4UAYIG 1Gbit */
++ {
++ .name = "GD5F1GQ4UAYIG",
++ .id = {0xc8, 0xf1},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* GD 3.3v GD5F1GQ4UEYIHY 1Gbit */
++ {
++ .name = "GD5F1GQ4UEYIHY",
++ .id = {0xc8, 0xd9},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* GD 1.8v GD5F1GQ4RB9IG 1Gbit */
++ {
++ .name = "GD5F1GQ4RB9IG",
++ .id = {0xc8, 0xc1},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* GD 3.3v GD5F1GQ4UBYIG 1Gbit */
++ {
++ .name = "GD5F1GQ4UBYIG",
++ .id = {0xc8, 0xd1},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* GD 3.3v GD5F2GQ4UAYIG 2Gbit */
++ {
++ .name = "GD5F2GQ4UAYIG",
++ .id = {0xc8, 0xf2},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* GD 3.3v GD5F2GQ4U9IGR/BYIG 2Gbit */
++ {
++ .name = "GD5F2GQ4U9IGR/BYIG",
++ .id = {0xc8, 0xd2},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++ /* GD 3.3v GD5F2GQ5UEYIG 2Gbit */
++ {
++ .name = "GD5F2GQ5UEYIG",
++ .id = {0xc8, 0x52},
+ .id_len = 2,
+ .chipsize = _256M,
+ .erasesize = _128K,
@@ -288021,193 +356417,11 @@ index 0000000..cd89d0e
+ .badblock_pos = BBP_FIRST_PAGE,
+ .read = {
+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(2, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 108),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* Micron MT29F2G01ABB 2GBit 1.8V */
-+ {
-+ .name = "MT29F2G01ABB",
-+ .id = {0x2C, 0x25},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(2, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* Micron MT29F4G01ADAG 4GBit 3.3V */
-+ {
-+ .name = "MT29F4G01ADAG",
-+ .id = {0x2C, 0x36},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(2, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 108),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* ESMT F50L512M41A 512Mbit */
-+ {
-+ .name = "F50L512M41A",
-+ .id = {0xC8, 0x20},
-+ .id_len = 2,
-+ .chipsize = _64M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
+ &READ_FAST(1, INFINITE, 104),
+ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(2, INFINITE, 104),
+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* ESMT F50L1G41A 1Gbit */
-+ {
-+ .name = "F50L1G41A",
-+ .id = {0xC8, 0x21},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* GD 3.3v GD5F1GQ4UAYIG 1Gbit */
-+ {
-+ .name = "GD5F1GQ4UAYIG",
-+ .id = {0xc8, 0xf1},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* GD 3.3v GD5F1GQ4UEYIHY 1Gbit */
-+ {
-+ .name = "GD5F1GQ4UEYIHY",
-+ .id = {0xc8, 0xd9},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
++ &READ_QUAD_ADDR(4, INFINITE, 104),
+ 0
+ },
+ .write = {
@@ -288222,285 +356436,190 @@ index 0000000..cd89d0e
+ .driver = &spi_driver_general,
+ },
+
-+ /* GD 1.8v GD5F1GQ4RB9IG 1Gbit */
-+ {
-+ .name = "GD5F1GQ4RB9IG",
-+ .id = {0xc8, 0xc1},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
++ /* GD 3.3v GD5F4GQ4UAYIG 4Gbit */
++ {
++ .name = "GD5F4GQ4UAYIG",
++ .id = {0xc8, 0xf4},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
+
-+ /* GD 3.3v GD5F1GQ4UBYIG 1Gbit */
-+ {
-+ .name = "GD5F1GQ4UBYIG",
-+ .id = {0xc8, 0xd1},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
++ /* GD 3.3v GD5F4GQ4UBYIG 4Gbit */
++ {
++ .name = "GD5F4GQ4UBYIG",
++ .id = {0xc8, 0xd4},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
+
-+ /* GD 3.3v GD5F2GQ4UAYIG 2Gbit */
-+ {
-+ .name = "GD5F2GQ4UAYIG",
-+ .id = {0xc8, 0xf2},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
++ /* GD 1.8V GD5F1GQ4RB9IGR 1Gbit */
++ {
++ .name = "GD5F1GQ4RB9IGR",
++ .id = {0xc8, 0xc1},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
+
-+ /* GD 3.3v GD5F2GQ4U9IGR/BYIG 2Gbit */
-+ {
-+ .name = "GD5F2GQ4U9IGR/BYIG",
-+ .id = {0xc8, 0xd2},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
++ /* GD 1.8V GD5F2GQ4RB9IGR 2Gbit */
++ {
++ .name = "GD5F2GQ4RB9IGR",
++ .id = {0xc8, 0xc2},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++ /* GD 1.8V 5F4GQ6RE9IG 4Gbit */
++ {
++ .name = "GD5F4GQ6RE9IG",
++ .id = {0xc8, 0x45},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(2, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(4, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++ /* GD 1.8V GD5F4GQ4RAYIG 4Gbit */
++ {
++ .name = "GD5F4GQ4RAYIG",
++ .id = {0xc8, 0xe4},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
+
-+ /* GD 3.3v GD5F4GQ4UAYIG 4Gbit */
-+ {
-+ .name = "GD5F4GQ4UAYIG",
-+ .id = {0xc8, 0xf4},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* GD 3.3v GD5F4GQ4UBYIG 4Gbit */
-+ {
-+ .name = "GD5F4GQ4UBYIG",
-+ .id = {0xc8, 0xd4},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* GD 1.8V GD5F1GQ4RB9IGR 1Gbit */
-+ {
-+ .name = "GD5F1GQ4RB9IGR",
-+ .id = {0xc8, 0xc1},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* GD 1.8V GD5F2GQ4RB9IGR 2Gbit */
-+ {
-+ .name = "GD5F2GQ4RB9IGR",
-+ .id = {0xc8, 0xc2},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* GD 1.8V GD5F4GQ4RAYIG 4Gbit */
-+ {
-+ .name = "GD5F4GQ4RAYIG",
-+ .id = {0xc8, 0xe4},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
+ /* Winbond 1.8V W25N02JWZEIF 2Gbit */
+ {
+ .name = "W25N02JWZEIF",
@@ -288529,837 +356648,866 @@ index 0000000..cd89d0e
+ &ERASE_SECTOR_128K(0, _128K, 104),
+ 0
+ },
-+ .driver = &spi_driver_no_qe,
++ .driver = &spi_driver_general,
+ },
+
-+ /* GD 1.8V 5F4GQ4RBYIG 4Gbit */
-+ {
-+ .name = "5F4GQ4RBYIG",
-+ .id = {0xc8, 0xc4},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* Winbond W25N01GV 1Gbit 3.3V */
-+ {
-+ .name = "W25N01GV",
-+ .id = {0xef, 0xaa, 0x21},
-+ .id_len = 3,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(2, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* Winbond W25M02GV 2Gbit 3.3V*/
-+ {
-+ .name = "W25M02GV",
-+ .id = {0xef, 0xab, 0x21},
-+ .id_len = 3,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(2, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* Winbond W25N01GWZEIG 1Gbit 1.8V */
-+ {
-+ .name = "W25N01GWZEIG",
-+ .id = {0xef, 0xba, 0x21},
-+ .id_len = 3,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(2, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* ATO ATO25D1GA 1Gbit */
-+ {
-+ .name = "ATO25D1GA",
-+ .id = {0x9b, 0x12},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* MXIC MX35LF1GE4AB 1Gbit */
-+ {
-+ .name = "MX35LF1GE4AB",
-+ .id = {0xc2, 0x12},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* MXIC MX35UF1G14AC 1Gbit 1.8V */
-+ {
-+ .name = "MX35UF1G14AC",
-+ .id = {0xc2, 0x90},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* MXIC MX35LF2GE4AB 2Gbit SOP-16Pin */
-+ {
-+ .name = "MX35LF2GE4AB",
-+ .id = {0xc2, 0x22},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* MXIC MX35LF2G14AC 2GBit */
-+ {
-+ .name = "MX35LF2G14AC",
-+ .id = {0xc2, 0x20},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* MXIC MX35UF2G14AC 2Gbit 1.8V */
-+ {
-+ .name = "MX35UF2G14AC",
-+ .id = {0xc2, 0xa0},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* Paragon PN26G01A 1Gbit */
-+ {
-+ .name = "PN26G01A",
-+ .id = {0xa1, 0xe1},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(1, INFINITE, 108),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 108),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* Paragon PN26G02A 2Gbit */
-+ {
-+ .name = "PN26G02A",
-+ .id = {0xa1, 0xe2},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(1, INFINITE, 108),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 108),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* All-flash AFS1GQ4UAC 1Gbit */
-+ {
-+ .name = "AFS1GQ4UAC",
-+ .id = {0xc1, 0x51},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(1, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* All-flash AFS2GQ4UAD 2Gbit */
-+ {
-+ .name = "AFS2GQ4UAD",
-+ .id = {0xc1, 0x52},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(1, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 24),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* TOSHIBA TC58CVG0S3H 1Gbit */
-+ {
-+ .name = "TC58CVG0S3H",
-+ .id = {0x98, 0xc2},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* TOSHIBA TC58CYG0S3H 1.8V 1Gbit */
-+ {
-+ .name = "TC58CYG0S3H",
-+ .id = {0x98, 0xb2},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* TOSHIBA TC58CVG1S3H 2Gbit */
-+ {
-+ .name = "TC58CVG1S3H",
-+ .id = {0x98, 0xcb},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* TOSHIBA TC58CYG1S3H 1.8V 2Gbit */
-+ {
-+ .name = "TC58CYG1S3H",
-+ .id = {0x98, 0xbb},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 75),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 75),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* TOSHIBA TC58CVG2S0H 4Gbit */
-+ {
-+ .name = "TC58CVG2S0H",
-+ .id = {0x98, 0xcd},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* TOSHIBA TC58CYG2S0H 1.8V 4Gbit */
-+ {
-+ .name = "TC58CYG2S0H",
-+ .id = {0x98, 0xbd},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 75),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 75),
-+ 0
-+ },
-+ .driver = &spi_driver_no_qe,
-+ },
-+
-+ /* HeYangTek HYF1GQ4UAACAE 1Gbit */
-+ {
-+ .name = "HYF1GQ4UAACAE",
-+ .id = {0xc9, 0x51},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(1, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* HeYangTek HYF2GQ4UAACAE 2Gbit */
-+ {
-+ .name = "HYF2GQ4UAACAE",
-+ .id = {0xc9, 0x52},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(1, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* HeYangTek HYF4GQ4UAACBE 4Gbit */
-+ {
-+ .name = "HYF4GQ4UAACBE",
-+ .id = {0xc9, 0xd4},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(1, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* Dosilicon 3.3V DS35Q1GA-IB 1Gbit */
-+ {
-+ .name = "DS35Q1GA-IB",
-+ .id = {0xe5, 0x71},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* XTX 3.3V XT26G01B 1Gbit */
-+ {
-+ .name = "XT26G01B",
-+ .id = {0x0B, 0xF1},
-+ .id_len = 2,
-+ .chipsize = _128M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(1, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 80),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
-+ /* Etron 1.8V EM78F044VCA-H 8Gbit */
-+ {
-+ .name = "EM78F044VCA-H",
-+ .id = {0xD5, 0x8D},
-+ .id_len = 2,
-+ .chipsize = _512M*2,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 100),
-+ &READ_DUAL(1, INFINITE, 100),
-+ &READ_DUAL_ADDR(1, INFINITE, 100),
-+ &READ_QUAD(1, INFINITE, 100),
-+ &READ_QUAD_ADDR(1, INFINITE, 100),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 100),
-+ &WRITE_QUAD(0, 256, 100),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 100),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
++ /* GD 1.8V 5F4GQ4RBYIG 4Gbit */
++ {
++ .name = "5F4GQ4RBYIG",
++ .id = {0xc8, 0xc4},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
+ },
+
-+ /* Etron 1.8V EM78E044VCA-H 4Gbit */
-+ {
-+ .name = "EM78E044VCA-H",
-+ .id = {0xD5, 0x8C},
-+ .id_len = 2,
-+ .chipsize = _512M,
-+ .erasesize = _256K,
-+ .pagesize = _4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 100),
-+ &READ_DUAL(1, INFINITE, 100),
-+ &READ_DUAL_ADDR(1, INFINITE, 100),
-+ &READ_QUAD(1, INFINITE, 100),
-+ &READ_QUAD_ADDR(1, INFINITE, 100),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 100),
-+ &WRITE_QUAD(0, 256, 100),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, _256K, 100),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
++ /* Winbond W25N01GV 1Gbit 3.3V */
++ {
++ .name = "W25N01GV",
++ .id = {0xef, 0xaa, 0x21},
++ .id_len = 3,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(2, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
+ },
+
-+ /* Etron 1.8V EM78D044VCF-H 2Gbit */
-+ {
-+ .name = "EM78D044VCF-H",
-+ .id = {0xd5, 0x81},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
++ /* Winbond W25N01GWZEIG 1Gbit 1.8V */
++ {
++ .name = "W25N01GWZEIG",
++ .id = {0xef, 0xba, 0x21},
++ .id_len = 3,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(2, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* ATO ATO25D1GA 1Gbit */
++ {
++ .name = "ATO25D1GA",
++ .id = {0x9b, 0x12},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* MXIC MX35LF1GE4AB 1Gbit */
++ {
++ .name = "MX35LF1GE4AB",
++ .id = {0xc2, 0x12},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* MXIC MX35UF1G14AC 1Gbit 1.8V */
++ {
++ .name = "MX35UF1G14AC",
++ .id = {0xc2, 0x90},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* MXIC MX35LF2GE4AB 2Gbit SOP-16Pin */
++ {
++ .name = "MX35LF2GE4AB",
++ .id = {0xc2, 0x22},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* MXIC MX35LF2G14AC 2GBit */
++ {
++ .name = "MX35LF2G14AC",
++ .id = {0xc2, 0x20},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* MXIC MX35UF2G14AC 2Gbit 1.8V */
++ {
++ .name = "MX35UF2G14AC",
++ .id = {0xc2, 0xa0},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* Paragon PN26G01A 1Gbit */
++ {
++ .name = "PN26G01A",
++ .id = {0xa1, 0xe1},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(1, INFINITE, 108),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 108),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* Paragon PN26G02A 2Gbit */
++ {
++ .name = "PN26G02A",
++ .id = {0xa1, 0xe2},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(1, INFINITE, 108),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 108),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* All-flash AFS1GQ4UAC 1Gbit */
++ {
++ .name = "AFS1GQ4UAC",
++ .id = {0xc1, 0x51},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(1, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* All-flash AFS2GQ4UAD 2Gbit */
++ {
++ .name = "AFS2GQ4UAD",
++ .id = {0xc1, 0x52},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(1, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 24),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* TOSHIBA TC58CVG0S3H 1Gbit */
++ {
++ .name = "TC58CVG0S3H",
++ .id = {0x98, 0xc2},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* TOSHIBA TC58CYG0S3H 1.8V 1Gbit */
++ {
++ .name = "TC58CYG0S3H",
++ .id = {0x98, 0xb2},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* TOSHIBA TC58CVG1S3H 2Gbit */
++ {
++ .name = "TC58CVG1S3H",
++ .id = {0x98, 0xcb},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* TOSHIBA TC58CYG1S3H 1.8V 2Gbit */
++ {
++ .name = "TC58CYG1S3H",
++ .id = {0x98, 0xbb},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 75),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 75),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* TOSHIBA TC58CVG2S0H 4Gbit */
++ {
++ .name = "TC58CVG2S0H",
++ .id = {0x98, 0xcd},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 104),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* TOSHIBA TC58CYG2S0H 1.8V 4Gbit */
++ {
++ .name = "TC58CYG2S0H",
++ .id = {0x98, 0xbd},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 75),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 75),
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* KIOXIA TH58CYG3S0H 1.8V 8Gbit */
++ {
++ .name = "TH58CYG3S0H",
++ .id = {0x98, 0xd4, 0x51},
++ .id_len = 3,
++ .chipsize = _1G,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24), /* 24MHz */
++ &READ_FAST(1, INFINITE, 133), /* 133MHz */
++ &READ_DUAL(1, INFINITE, 133), /* 133MHz */
++ &READ_QUAD(1, INFINITE, 133), /* 133MHz */
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 133), /* 133MHz */
++ &WRITE_QUAD(0, 256, 133), /* 133MHz */
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 133), /* 133MHz */
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* HeYangTek HYF1GQ4UAACAE 1Gbit */
++ {
++ .name = "HYF1GQ4UAACAE",
++ .id = {0xc9, 0x51},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(1, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* HeYangTek HYF2GQ4UAACAE 2Gbit */
++ {
++ .name = "HYF2GQ4UAACAE",
++ .id = {0xc9, 0x52},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(1, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* HeYangTek HYF4GQ4UAACBE 4Gbit */
++ {
++ .name = "HYF4GQ4UAACBE",
++ .id = {0xc9, 0xd4},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(1, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 80),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* Dosilicon 3.3V DS35Q1GA-IB 1Gbit */
++ {
++ .name = "DS35Q1GA-IB",
++ .id = {0xe5, 0x71},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* XTX 3.3V XT26G01B 1Gbit */
++ {
++ .name = "XT26G01B",
++ .id = {0x0B, 0xF1},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(1, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 80),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* Etron 1.8V EM78F044VCA-H 8Gbit */
++ {
++ .name = "EM78F044VCA-H",
++ .id = {0xD5, 0x8D},
++ .id_len = 2,
++ .chipsize = _512M*2,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 100),
++ &READ_DUAL(1, INFINITE, 100),
++ &READ_DUAL_ADDR(1, INFINITE, 100),
++ &READ_QUAD(1, INFINITE, 100),
++ &READ_QUAD_ADDR(1, INFINITE, 100),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 100),
++ &WRITE_QUAD(0, 256, 100),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 100),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* Etron 1.8V EM78E044VCA-H 4Gbit */
++ {
++ .name = "EM78E044VCA-H",
++ .id = {0xD5, 0x8C},
++ .id_len = 2,
++ .chipsize = _512M,
++ .erasesize = _256K,
++ .pagesize = _4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 100),
++ &READ_DUAL(1, INFINITE, 100),
++ &READ_DUAL_ADDR(1, INFINITE, 100),
++ &READ_QUAD(1, INFINITE, 100),
++ &READ_QUAD_ADDR(1, INFINITE, 100),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 100),
++ &WRITE_QUAD(0, 256, 100),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, _256K, 100),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* Etron 1.8V EM78D044VCF-H 2Gbit */
++ {
++ .name = "EM78D044VCF-H",
++ .id = {0xd5, 0x81},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* Etron 3.3V EM73C044VCC-H 1Gbit */
++ {
++ .name = "EM73C044VCC-H",
++ .id = {0xd5, 0x22},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_general,
+ },
+
+ /* Micron MT29F4G01ABBFDWB 4GBit 1.8V */
@@ -289390,320 +357538,382 @@ index 0000000..cd89d0e
+ },
+ .driver = &spi_driver_no_qe,
+ },
-+
-+ /* Dosilicon 3.3V DS35Q2GA-IB 1Gb */
-+ {
-+ .name = "DS35Q2GA-IB",
-+ .id = {0xe5, 0x72},
-+ .id_len = 2,
-+ .chipsize = _256M,
-+ .erasesize = _128K,
-+ .pagesize = _2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, _128K, 104),
-+ 0
-+ },
-+ .driver = &spi_driver_general,
-+ },
-+
++
++ /* Dosilicon 3.3V DS35Q2GA-IB 1Gb */
++ {
++ .name = "DS35Q2GA-IB",
++ .id = {0xe5, 0x72},
++ .id_len = 2,
++ .chipsize = _256M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104),
++ 0
++ },
++ .driver = &spi_driver_general,
++ },
++
++ /* FM 3.3v FM25S01-DND-A-G 1Gbit */
++ {
++ .name = "FM25S01-DND-A-G",
++ .id = {0xa1, 0xa1},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24), /* 24MHz */
++ &READ_FAST(1, INFINITE, 104), /* 104MHz */
++ &READ_DUAL(1, INFINITE, 104), /* 104MHz */
++ &READ_DUAL_ADDR(1, INFINITE, 40), /* 40MHz */
++ &READ_QUAD(1, INFINITE, 104), /* 104MHz */
++ &READ_QUAD_ADDR(2, INFINITE, 40), /* 40MHz */
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104), /* 104MHz */
++ &WRITE_QUAD(0, 256, 104), /* 104MHz */
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
++ /* FM 3.3v FM25S01A 1Gbit */
++ {
++ .name = "FM25S01A",
++ .id = {0xa1, 0xe4},
++ .id_len = 2,
++ .chipsize = _128M,
++ .erasesize = _128K,
++ .pagesize = _2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24), /* 104MHz */
++ &READ_FAST(1, INFINITE, 104), /* 104MHz */
++ &READ_DUAL(1, INFINITE, 104), /* 104MHz */
++ &READ_DUAL_ADDR(1, INFINITE, 40), /* 70MHz */
++ &READ_QUAD(1, INFINITE, 104), /* 104MHz */
++ &READ_QUAD_ADDR(2, INFINITE, 40), /* 70MHz */
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104), /* 104MHz */
++ &WRITE_QUAD(0, 256, 104), /* 104MHz */
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
++ 0
++ },
++ .driver = &spi_driver_no_qe,
++ },
++
+ { .id_len = 0, },
+};
+
+/*****************************************************************************/
+static void hifmc100_spi_nand_search_rw(struct spi_nand_info *spiinfo,
-+ struct spi_op *spiop_rw, u_int iftype, u_int max_dummy, int rw_type)
++ struct spi_op *spiop_rw, u_int iftype, u_int max_dummy, int rw_type)
+{
-+ int ix = 0;
-+ struct spi_op **spiop, **fitspiop;
++ int ix = 0;
++ struct spi_op **spiop, **fitspiop;
+
-+ for (fitspiop = spiop = (rw_type ? spiinfo->write : spiinfo->read);
-+ (*spiop) && ix < MAX_SPI_OP; spiop++, ix++) {
-+ if (((*spiop)->iftype & iftype)
-+ && ((*spiop)->dummy <= max_dummy)
-+ && (*fitspiop)->iftype < (*spiop)->iftype) {
-+ fitspiop = spiop;
-+ }
-+ }
-+ memcpy(spiop_rw, (*fitspiop), sizeof(struct spi_op));
++ for (fitspiop = spiop = (rw_type ? spiinfo->write : spiinfo->read);
++ (*spiop) && ix < MAX_SPI_OP; spiop++, ix++) {
++ if (((*spiop)->iftype & iftype)
++ && ((*spiop)->dummy <= max_dummy)
++ && (*fitspiop)->iftype < (*spiop)->iftype) {
++ fitspiop = spiop;
++ }
++ }
++ memcpy(spiop_rw, (*fitspiop), sizeof(struct spi_op));
+}
+
+/*****************************************************************************/
+static void hifmc100_spi_nand_get_erase(struct spi_nand_info *spiinfo,
-+ struct spi_op *spiop_erase)
++ struct spi_op *spiop_erase)
+{
-+ int ix;
++ int ix;
+
-+ spiop_erase->size = 0;
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spiinfo->erase[ix] == NULL) {
-+ break;
-+ }
-+ if (spiinfo->erasesize == spiinfo->erase[ix]->size) {
-+ memcpy(&spiop_erase[ix], spiinfo->erase[ix],
-+ sizeof(struct spi_op));
-+ break;
-+ }
-+ }
++ spiop_erase->size = 0;
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spiinfo->erase[ix] == NULL) {
++ break;
++ }
++ if (spiinfo->erasesize == spiinfo->erase[ix]->size) {
++ memcpy(&spiop_erase[ix], spiinfo->erase[ix],
++ sizeof(struct spi_op));
++ break;
++ }
++ }
+}
+
+/*****************************************************************************/
+static void hifmc100_map_spi_op(struct hifmc_spi *spi)
+{
-+ unsigned char ix;
-+ const int iftype_read[] = {
-+ SPI_IF_READ_STD, IF_TYPE_STD,
-+ SPI_IF_READ_FAST, IF_TYPE_STD,
-+ SPI_IF_READ_DUAL, IF_TYPE_DUAL,
-+ SPI_IF_READ_DUAL_ADDR, IF_TYPE_DIO,
-+ SPI_IF_READ_QUAD, IF_TYPE_QUAD,
-+ SPI_IF_READ_QUAD_ADDR, IF_TYPE_QIO,
-+ 0, 0,
-+ };
-+ const int iftype_write[] = {
-+ SPI_IF_WRITE_STD, IF_TYPE_STD,
-+ SPI_IF_WRITE_QUAD, IF_TYPE_QUAD,
-+ 0, 0,
-+ };
-+ const char *if_str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
++ unsigned char ix;
++ const int iftype_read[] = {
++ SPI_IF_READ_STD, IF_TYPE_STD,
++ SPI_IF_READ_FAST, IF_TYPE_STD,
++ SPI_IF_READ_DUAL, IF_TYPE_DUAL,
++ SPI_IF_READ_DUAL_ADDR, IF_TYPE_DIO,
++ SPI_IF_READ_QUAD, IF_TYPE_QUAD,
++ SPI_IF_READ_QUAD_ADDR, IF_TYPE_QIO,
++ 0, 0,
++ };
++ const int iftype_write[] = {
++ SPI_IF_WRITE_STD, IF_TYPE_STD,
++ SPI_IF_WRITE_QUAD, IF_TYPE_QUAD,
++ 0, 0,
++ };
++ const char *if_str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
+
-+ FMC_PR(BT_DBG, "\t||*-Start Get SPI operation iftype\n");
++ FMC_PR(BT_DBG, "\t||*-Start Get SPI operation iftype\n");
+
-+ for (ix = 0; iftype_write[ix]; ix += 2) {
-+ if (spi->write->iftype == iftype_write[ix]) {
-+ spi->write->iftype = iftype_write[ix + 1];
-+ break;
-+ }
-+ }
-+ FMC_PR(BT_DBG, "\t|||-Get best write iftype: %s \n",
-+ if_str[spi->write->iftype]);
++ for (ix = 0; iftype_write[ix]; ix += 2) {
++ if (spi->write->iftype == iftype_write[ix]) {
++ spi->write->iftype = iftype_write[ix + 1];
++ break;
++ }
++ }
++ FMC_PR(BT_DBG, "\t|||-Get best write iftype: %s \n",
++ if_str[spi->write->iftype]);
+
-+ for (ix = 0; iftype_read[ix]; ix += 2) {
-+ if (spi->read->iftype == iftype_read[ix]) {
-+ spi->read->iftype = iftype_read[ix + 1];
-+ break;
-+ }
-+ }
-+ FMC_PR(BT_DBG, "\t|||-Get best read iftype: %s \n",
-+ if_str[spi->read->iftype]);
++ for (ix = 0; iftype_read[ix]; ix += 2) {
++ if (spi->read->iftype == iftype_read[ix]) {
++ spi->read->iftype = iftype_read[ix + 1];
++ break;
++ }
++ }
++ FMC_PR(BT_DBG, "\t|||-Get best read iftype: %s \n",
++ if_str[spi->read->iftype]);
+
-+ spi->erase->iftype = IF_TYPE_STD;
-+ FMC_PR(BT_DBG, "\t|||-Get best erase iftype: %s \n",
-+ if_str[spi->erase->iftype]);
++ spi->erase->iftype = IF_TYPE_STD;
++ FMC_PR(BT_DBG, "\t|||-Get best erase iftype: %s \n",
++ if_str[spi->erase->iftype]);
+
-+ FMC_PR(BT_DBG, "\t||*-End Get SPI operation iftype \n");
++ FMC_PR(BT_DBG, "\t||*-End Get SPI operation iftype \n");
+}
+
+/*****************************************************************************/
+static void hifmc100_spi_ids_probe(struct mtd_info *mtd,
-+ struct spi_nand_info *spi_dev)
++ struct spi_nand_info *spi_dev)
+{
-+ unsigned int reg;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
-+ struct hifmc_spi *spi = host->spi;
++ unsigned int reg;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
++ struct hifmc_spi *spi = host->spi;
+
-+ FMC_PR(BT_DBG, "\t|*-Start match SPI operation & chip init\n");
++ FMC_PR(BT_DBG, "\t|*-Start match SPI operation & chip init\n");
+
-+ spi->host = host;
-+ spi->name = spi_dev->name;
-+ spi->driver = spi_dev->driver;
++ spi->host = host;
++ spi->name = spi_dev->name;
++ spi->driver = spi_dev->driver;
+
-+ hifmc100_spi_nand_search_rw(spi_dev, spi->read,
-+ HIFMC_SPI_NAND_SUPPORT_READ,
-+ HIFMC_SPI_NAND_SUPPORT_MAX_DUMMY, RW_OP_READ);
-+ FMC_PR(BT_DBG, "\t||-Save spi->read op cmd:%#x\n", spi->read->cmd);
++ hifmc100_spi_nand_search_rw(spi_dev, spi->read,
++ HIFMC_SPI_NAND_SUPPORT_READ,
++ HIFMC_SPI_NAND_SUPPORT_MAX_DUMMY, RW_OP_READ);
++ FMC_PR(BT_DBG, "\t||-Save spi->read op cmd:%#x\n", spi->read->cmd);
+
-+ hifmc100_spi_nand_search_rw(spi_dev, spi->write,
-+ HIFMC_SPI_NAND_SUPPORT_WRITE,
-+ HIFMC_SPI_NAND_SUPPORT_MAX_DUMMY, RW_OP_WRITE);
-+ FMC_PR(BT_DBG, "\t||-Save spi->write op cmd:%#x\n", spi->write->cmd);
++ hifmc100_spi_nand_search_rw(spi_dev, spi->write,
++ HIFMC_SPI_NAND_SUPPORT_WRITE,
++ HIFMC_SPI_NAND_SUPPORT_MAX_DUMMY, RW_OP_WRITE);
++ FMC_PR(BT_DBG, "\t||-Save spi->write op cmd:%#x\n", spi->write->cmd);
+
-+ hifmc100_spi_nand_get_erase(spi_dev, spi->erase);
-+ FMC_PR(BT_DBG, "\t||-Save spi->erase op cmd:%#x\n", spi->erase->cmd);
++ hifmc100_spi_nand_get_erase(spi_dev, spi->erase);
++ FMC_PR(BT_DBG, "\t||-Save spi->erase op cmd:%#x\n", spi->erase->cmd);
+
-+ hifmc100_map_spi_op(spi);
++ hifmc100_map_spi_op(spi);
+
-+ if (spi->driver->qe_enable) {
-+ spi->driver->qe_enable(spi);
-+ }
++ if (spi->driver->qe_enable) {
++ spi->driver->qe_enable(spi);
++ }
+
-+ /* Disable write protection */
-+ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
-+ FMC_PR(BT_DBG, "\t||-Get protect status[%#x]: %#x\n", PROTECT_ADDR,
-+ reg);
-+ if (ANY_BP_ENABLE(reg)) {
-+ reg &= ~ALL_BP_MASK;
-+ spi_nand_feature_op(spi, SET_OP, PROTECT_ADDR, reg);
-+ FMC_PR(BT_DBG, "\t||-Set [%#x]FT %#x\n", PROTECT_ADDR, reg);
++ /* Disable write protection */
++ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
++ FMC_PR(BT_DBG, "\t||-Get protect status[%#x]: %#x\n", PROTECT_ADDR,
++ reg);
++ if (ANY_BP_ENABLE(reg)) {
++ reg &= ~ALL_BP_MASK;
++ spi_nand_feature_op(spi, SET_OP, PROTECT_ADDR, reg);
++ FMC_PR(BT_DBG, "\t||-Set [%#x]FT %#x\n", PROTECT_ADDR, reg);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
-+ FMC_PR(BT_DBG, "\t||-Check BP disable result: %#x\n", reg);
-+ if (ANY_BP_ENABLE(reg)) {
-+ DB_MSG("Error: Write protection disable failed!\n");
-+ }
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
++ FMC_PR(BT_DBG, "\t||-Check BP disable result: %#x\n", reg);
++ if (ANY_BP_ENABLE(reg)) {
++ DB_MSG("Error: Write protection disable failed!\n");
++ }
++ }
+
-+ /* Disable chip internal ECC */
-+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
-+ FMC_PR(BT_DBG, "\t||-Get feature status[%#x]: %#x\n", FEATURE_ADDR,
-+ reg);
-+ if (reg & FEATURE_ECC_ENABLE) {
-+ reg &= ~FEATURE_ECC_ENABLE;
-+ spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
-+ FMC_PR(BT_DBG, "\t||-Set [%#x]FT: %#x\n", FEATURE_ADDR, reg);
++ /* Disable chip internal ECC */
++ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
++ FMC_PR(BT_DBG, "\t||-Get feature status[%#x]: %#x\n", FEATURE_ADDR,
++ reg);
++ if (reg & FEATURE_ECC_ENABLE) {
++ reg &= ~FEATURE_ECC_ENABLE;
++ spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
++ FMC_PR(BT_DBG, "\t||-Set [%#x]FT: %#x\n", FEATURE_ADDR, reg);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
-+ FMC_PR(BT_DBG, "\t||-Check internal ECC disable result: %#x\n",
-+ reg);
-+ if (reg & FEATURE_ECC_ENABLE) {
-+ DB_MSG("Error: Chip internal ECC disable failed!\n");
-+ }
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
++ FMC_PR(BT_DBG, "\t||-Check internal ECC disable result: %#x\n",
++ reg);
++ if (reg & FEATURE_ECC_ENABLE) {
++ DB_MSG("Error: Chip internal ECC disable failed!\n");
++ }
++ }
+
-+ hifmc_cs_user[host->cmd_op.cs]++;
++ hifmc_cs_user[host->cmd_op.cs]++;
+
-+ FMC_PR(BT_DBG, "\t|*-End match SPI operation & chip init\n");
++ FMC_PR(BT_DBG, "\t|*-End match SPI operation & chip init\n");
+}
+
+static struct nand_flash_dev spi_nand_dev;
+/*****************************************************************************/
+static struct nand_flash_dev *spi_nand_get_flash_info(struct mtd_info *mtd,
-+ unsigned char *id)
++ unsigned char *id)
+{
-+ unsigned char ix, len = 0;
-+ char buffer[100];
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
-+ struct spi_nand_info *spi_dev = hifmc_spi_nand_flash_table;
-+ struct nand_flash_dev *type = &spi_nand_dev;
++ unsigned char ix, len = 0;
++ char buffer[100];
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
++ struct spi_nand_info *spi_dev = hifmc_spi_nand_flash_table;
++ struct nand_flash_dev *type = &spi_nand_dev;
+
-+ FMC_PR(BT_DBG, "\t*-Start find SPI Nand flash\n");
++ FMC_PR(BT_DBG, "\t*-Start find SPI Nand flash\n");
+
-+ len = sprintf(buffer, "SPI Nand(cs %d) ID: %#x %#x",
-+ host->cmd_op.cs, id[0], id[1]);
++ len = sprintf(buffer, "SPI Nand(cs %d) ID: %#x %#x",
++ host->cmd_op.cs, id[0], id[1]);
+
-+ for (; spi_dev->id_len; spi_dev++) {
-+ if (memcmp(id, spi_dev->id, spi_dev->id_len)) {
-+ continue;
-+ }
++ for (; spi_dev->id_len; spi_dev++) {
++ if (memcmp(id, spi_dev->id, spi_dev->id_len)) {
++ continue;
++ }
+
-+ for (ix = 2; ix < spi_dev->id_len; ix++) {
-+ len += sprintf(buffer + len, " %#x", id[ix]);
-+ }
-+ pr_info("%s\n", buffer);
++ for (ix = 2; ix < spi_dev->id_len; ix++) {
++ len += sprintf(buffer + len, " %#x", id[ix]);
++ }
++ pr_info("%s\n", buffer);
+
-+ FMC_PR(BT_DBG, "\t||-CS(%d) found SPI Nand: %s\n",
-+ host->cmd_op.cs, spi_dev->name);
++ FMC_PR(BT_DBG, "\t||-CS(%d) found SPI Nand: %s\n",
++ host->cmd_op.cs, spi_dev->name);
+
-+ type->name = spi_dev->name;
-+ memcpy(type->id, spi_dev->id, spi_dev->id_len);
-+ type->pagesize = spi_dev->pagesize;
-+ type->chipsize = spi_dev->chipsize >> 20;
-+ type->erasesize = spi_dev->erasesize;
-+ type->id_len = spi_dev->id_len;
-+ type->oobsize = spi_dev->oobsize;
-+ FMC_PR(BT_DBG, "\t|-Save struct nand_flash_dev info\n");
++ type->name = spi_dev->name;
++ memcpy(type->id, spi_dev->id, spi_dev->id_len);
++ type->pagesize = spi_dev->pagesize;
++ type->chipsize = spi_dev->chipsize >> 20;
++ type->erasesize = spi_dev->erasesize;
++ type->id_len = spi_dev->id_len;
++ type->oobsize = spi_dev->oobsize;
++ FMC_PR(BT_DBG, "\t|-Save struct nand_flash_dev info\n");
+
-+ mtd->oobsize = spi_dev->oobsize;
-+ mtd->erasesize = spi_dev->erasesize;
-+ mtd->writesize = spi_dev->pagesize;
-+ chip->chipsize = spi_dev->chipsize;
++ mtd->oobsize = spi_dev->oobsize;
++ mtd->erasesize = spi_dev->erasesize;
++ mtd->writesize = spi_dev->pagesize;
++ chip->chipsize = spi_dev->chipsize;
+
-+ hifmc100_spi_ids_probe(mtd, spi_dev);
++ hifmc100_spi_ids_probe(mtd, spi_dev);
+
-+ FMC_PR(BT_DBG, "\t*-Found SPI nand: %s\n", spi_dev->name);
++ FMC_PR(BT_DBG, "\t*-Found SPI nand: %s\n", spi_dev->name);
+
-+ return type;
-+ }
++ return type;
++ }
+
-+ FMC_PR(BT_DBG, "\t*-Not found SPI nand flash, %s\n", buffer);
++ FMC_PR(BT_DBG, "\t*-Not found SPI nand flash, %s\n", buffer);
+
-+ return NULL;
++ return NULL;
+}
+
+/*****************************************************************************/
+void hifmc_spi_nand_ids_register(void)
+{
-+ pr_info("SPI Nand ID Table Version %s\n", SPI_NAND_ID_TAB_VER);
-+ get_spi_nand_flash_type_hook = spi_nand_get_flash_info;
++ pr_info("SPI Nand ID Table Version %s\n", SPI_NAND_ID_TAB_VER);
++ get_spi_nand_flash_type_hook = spi_nand_get_flash_info;
+}
+
+#ifdef CONFIG_PM
+/*****************************************************************************/
+void hifmc100_spi_nand_config(struct hifmc_host *host)
+{
-+ unsigned int reg;
-+ struct hifmc_spi *spi = host->spi;
-+ static const char const *str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
++ unsigned int reg;
++ struct hifmc_spi *spi = host->spi;
++ static const char *str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
+
-+ /* judge whether support QUAD read/write or not, set it if yes */
-+ FMC_PR(PM_DBG, "\t|-SPI read iftype: %s write iftype: %s\n",
-+ str[spi->read->iftype], str[spi->write->iftype]);
++ /* judge whether support QUAD read/write or not, set it if yes */
++ FMC_PR(PM_DBG, "\t|-SPI read iftype: %s write iftype: %s\n",
++ str[spi->read->iftype], str[spi->write->iftype]);
+
-+ if (spi->driver->qe_enable) {
-+ spi->driver->qe_enable(spi);
-+ }
++ if (spi->driver->qe_enable) {
++ spi->driver->qe_enable(spi);
++ }
+
-+ /* Disable write protection */
-+ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
-+ FMC_PR(PM_DBG, "\t|-Get protect status[%#x]: %#x\n", PROTECT_ADDR,
-+ reg);
-+ if (ANY_BP_ENABLE(reg)) {
-+ reg &= ~ALL_BP_MASK;
-+ spi_nand_feature_op(spi, SET_OP, PROTECT_ADDR, reg);
-+ FMC_PR(PM_DBG, "\t|-Set [%#x]FT %#x\n", PROTECT_ADDR, reg);
++ /* Disable write protection */
++ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
++ FMC_PR(PM_DBG, "\t|-Get protect status[%#x]: %#x\n", PROTECT_ADDR,
++ reg);
++ if (ANY_BP_ENABLE(reg)) {
++ reg &= ~ALL_BP_MASK;
++ spi_nand_feature_op(spi, SET_OP, PROTECT_ADDR, reg);
++ FMC_PR(PM_DBG, "\t|-Set [%#x]FT %#x\n", PROTECT_ADDR, reg);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
-+ FMC_PR(PM_DBG, "\t|-Check BP disable result: %#x\n", reg);
-+ if (ANY_BP_ENABLE(reg)) {
-+ DB_MSG("Error: Write protection disable failed!\n");
-+ }
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, PROTECT_ADDR, 0);
++ FMC_PR(PM_DBG, "\t|-Check BP disable result: %#x\n", reg);
++ if (ANY_BP_ENABLE(reg)) {
++ DB_MSG("Error: Write protection disable failed!\n");
++ }
++ }
+
-+ /* Disable chip internal ECC */
-+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
-+ FMC_PR(PM_DBG, "\t|-Get feature status[%#x]: %#x\n", FEATURE_ADDR,
-+ reg);
-+ if (reg & FEATURE_ECC_ENABLE) {
-+ reg &= ~FEATURE_ECC_ENABLE;
-+ spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
-+ FMC_PR(PM_DBG, "\t|-Set [%#x]FT: %#x\n", FEATURE_ADDR, reg);
++ /* Disable chip internal ECC */
++ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
++ FMC_PR(PM_DBG, "\t|-Get feature status[%#x]: %#x\n", FEATURE_ADDR,
++ reg);
++ if (reg & FEATURE_ECC_ENABLE) {
++ reg &= ~FEATURE_ECC_ENABLE;
++ spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
++ FMC_PR(PM_DBG, "\t|-Set [%#x]FT: %#x\n", FEATURE_ADDR, reg);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
-+ FMC_PR(PM_DBG, "\t|-Check internal ECC disable result: %#x\n",
-+ reg);
-+ if (reg & FEATURE_ECC_ENABLE) {
-+ DB_MSG("Error: Chip internal ECC disable failed!\n");
-+ }
-+ }
++ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
++ FMC_PR(PM_DBG, "\t|-Check internal ECC disable result: %#x\n",
++ reg);
++ if (reg & FEATURE_ECC_ENABLE) {
++ DB_MSG("Error: Chip internal ECC disable failed!\n");
++ }
++ }
+}
+/*****************************************************************************/
+#endif /* CONFIG_PM */
diff --git a/drivers/mtd/nand/hifmc100_nand/Kconfig b/drivers/mtd/nand/hifmc100_nand/Kconfig
new file mode 100644
-index 0000000..7775208
+index 0000000..188c9a7
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100_nand/Kconfig
@@ -0,0 +1,50 @@
@@ -289738,21 +357948,21 @@ index 0000000..7775208
+config RW_H_WIDTH
+ int "the width of Read/Write HIGH Hold Time (0 to 15)"
+ range 0 15
-+ default 10 if ARCH_HI3559AV100
++ default 10 if (ARCH_HI3559AV100 || ARCH_HI3569V100)
+ help
+ the Read/Write HIGH Hold Time of nand flash
+
+config R_L_WIDTH
+ int "the Read pulse width (0 to 15)"
+ range 0 15
-+ default 10 if ARCH_HI3559AV100
++ default 10 if (ARCH_HI3559AV100 || ARCH_HI3569V100)
+ help
+ the Read/Write LOW Hold Time of nand flash
+
+config W_L_WIDTH
+ int "the Write pulse width (0 to 15)"
+ range 0 15
-+ default 10 if ARCH_HI3559AV100
++ default 10 if (ARCH_HI3559AV100 || ARCH_HI3569V100)
+ help
+ the Read/Write LOW Hold Time of nand flash
+
@@ -289791,7 +358001,7 @@ index 0000000..623363c
+obj-y += hifmc100_nand.o hifmc100_nand_os.o
diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.c b/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.c
new file mode 100644
-index 0000000..7623b93
+index 0000000..d32b9fd
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.c
@@ -0,0 +1,1164 @@
@@ -289830,617 +358040,617 @@ index 0000000..7623b93
+/*****************************************************************************/
+static void hifmc100_dma_transfer(struct hifmc_host *host, int todev)
+{
-+ unsigned int reg = (unsigned int)host->dma_buffer;
-+ char *op = todev ? "write" : "read";
++ unsigned int reg = (unsigned int)host->dma_buffer;
++ char *op = todev ? "write" : "read";
+
-+ FMC_PR(DMA_DB, "\t\t *-Start %s page dma transfer\n", op);
++ FMC_PR(DMA_DB, "\t\t *-Start %s page dma transfer\n", op);
+
-+ hifmc_writel(host, FMC_DMA_SADDR_D0, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set ADDR0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
++ hifmc_writel(host, FMC_DMA_SADDR_D0, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set ADDR0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
+
+#ifdef CONFIG_64BIT
-+ reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
-+ hifmc_writel(host, FMC_DMA_SADDRH_D0, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set ADDRH0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
++ reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
++ hifmc_writel(host, FMC_DMA_SADDRH_D0, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set ADDRH0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
+#endif
+
-+ reg += FMC_DMA_ADDR_OFFSET;
-+ hifmc_writel(host, FMC_DMA_SADDR_D1, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set ADDR1[%#x]%#x\n", FMC_DMA_SADDR_D1, reg);
++ reg += FMC_DMA_ADDR_OFFSET;
++ hifmc_writel(host, FMC_DMA_SADDR_D1, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set ADDR1[%#x]%#x\n", FMC_DMA_SADDR_D1, reg);
+
-+ reg += FMC_DMA_ADDR_OFFSET;
-+ hifmc_writel(host, FMC_DMA_SADDR_D2, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set ADDR2[%#x]%#x\n", FMC_DMA_SADDR_D2, reg);
++ reg += FMC_DMA_ADDR_OFFSET;
++ hifmc_writel(host, FMC_DMA_SADDR_D2, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set ADDR2[%#x]%#x\n", FMC_DMA_SADDR_D2, reg);
+
-+ reg += FMC_DMA_ADDR_OFFSET;
-+ hifmc_writel(host, FMC_DMA_SADDR_D3, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set ADDR3[%#x]%#x\n", FMC_DMA_SADDR_D3, reg);
++ reg += FMC_DMA_ADDR_OFFSET;
++ hifmc_writel(host, FMC_DMA_SADDR_D3, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set ADDR3[%#x]%#x\n", FMC_DMA_SADDR_D3, reg);
+
-+ reg = host->dma_oob;
-+ hifmc_writel(host, FMC_DMA_SADDR_OOB, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, reg);
++ reg = host->dma_oob;
++ hifmc_writel(host, FMC_DMA_SADDR_OOB, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, reg);
+
+#ifdef CONFIG_64BIT
-+ reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
-+ hifmc_writel(host, FMC_DMA_SADDRH_OOB, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set ADDRH0[%#x]%#x\n", FMC_DMA_SADDRH_OOB, reg);
++ reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
++ hifmc_writel(host, FMC_DMA_SADDRH_OOB, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set ADDRH0[%#x]%#x\n", FMC_DMA_SADDRH_OOB, reg);
+#endif
+
-+ if (host->ecctype == NAND_ECC_0BIT) {
-+ hifmc_writel(host, FMC_DMA_LEN, FMC_DMA_LEN_SET(host->oobsize));
-+ FMC_PR(DMA_DB, "\t\t |-Set LEN[%#x]%#x\n", FMC_DMA_LEN, reg);
-+ }
-+ reg = FMC_OP_READ_DATA_EN | FMC_OP_WRITE_DATA_EN;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
++ if (host->ecctype == NAND_ECC_0BIT) {
++ hifmc_writel(host, FMC_DMA_LEN, FMC_DMA_LEN_SET(host->oobsize));
++ FMC_PR(DMA_DB, "\t\t |-Set LEN[%#x]%#x\n", FMC_DMA_LEN, reg);
++ }
++ reg = FMC_OP_READ_DATA_EN | FMC_OP_WRITE_DATA_EN;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ reg = FMC_DMA_AHB_CTRL_DMA_PP_EN
-+ | FMC_DMA_AHB_CTRL_BURST16_EN
-+ | FMC_DMA_AHB_CTRL_BURST8_EN
-+ | FMC_DMA_AHB_CTRL_BURST4_EN;
-+ hifmc_writel(host, FMC_DMA_AHB_CTRL, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set AHBCTRL[%#x]%#x\n", FMC_DMA_AHB_CTRL, reg);
++ reg = FMC_DMA_AHB_CTRL_DMA_PP_EN
++ | FMC_DMA_AHB_CTRL_BURST16_EN
++ | FMC_DMA_AHB_CTRL_BURST8_EN
++ | FMC_DMA_AHB_CTRL_BURST4_EN;
++ hifmc_writel(host, FMC_DMA_AHB_CTRL, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set AHBCTRL[%#x]%#x\n", FMC_DMA_AHB_CTRL, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_ADDR_NUM(host->addr_cycle);
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_ADDR_NUM(host->addr_cycle);
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = OP_CTRL_DMA_OP_READY;
-+ if (todev) {
-+ reg |= OP_CTRL_RW_OP(todev);
-+ }
-+ hifmc_writel(host, FMC_OP_CTRL, reg);
-+ FMC_PR(DMA_DB, "\t\t |-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
++ reg = OP_CTRL_DMA_OP_READY;
++ if (todev) {
++ reg |= OP_CTRL_RW_OP(todev);
++ }
++ hifmc_writel(host, FMC_OP_CTRL, reg);
++ FMC_PR(DMA_DB, "\t\t |-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
+
-+ FMC_DMA_WAIT_CPU_FINISH(host);
++ FMC_DMA_WAIT_CPU_FINISH(host);
+
-+ FMC_PR(DMA_DB, "\t\t *-End %s page dma transfer\n", op);
++ FMC_PR(DMA_DB, "\t\t *-End %s page dma transfer\n", op);
+
-+ return;
++ return;
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_write(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(WR_DBG, "\t|*-Start send page programme cmd\n");
++ FMC_PR(WR_DBG, "\t|*-Start send page programme cmd\n");
+
-+ if (*host->bbm != 0xFF && *host->bbm != 0x00) {
-+ pr_info("WARNING: attempt to write an invalid bbm. " \
-+ "page: 0x%08x, mark: 0x%02x,\n",
-+ GET_PAGE_INDEX(host), *host->bbm);
-+ }
++ if (*host->bbm != 0xFF && *host->bbm != 0x00) {
++ pr_info("WARNING: attempt to write an invalid bbm. " \
++ "page: 0x%08x, mark: 0x%02x,\n",
++ GET_PAGE_INDEX(host), *host->bbm);
++ }
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ reg = host->addr_value[1];
-+ hifmc_writel(host, FMC_ADDRH, reg);
-+ FMC_PR(WR_DBG, "\t||-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
++ reg = host->addr_value[1];
++ hifmc_writel(host, FMC_ADDRH, reg);
++ FMC_PR(WR_DBG, "\t||-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
+
-+ reg = host->addr_value[0] & 0xffff0000;
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(WR_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ reg = host->addr_value[0] & 0xffff0000;
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(WR_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
-+ reg = FMC_CMD_CMD2(NAND_CMD_PAGEPROG) | FMC_CMD_CMD1(NAND_CMD_SEQIN);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(WR_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD2(NAND_CMD_PAGEPROG) | FMC_CMD_CMD1(NAND_CMD_SEQIN);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(WR_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ *host->epm = 0x0000;
++ *host->epm = 0x0000;
+
-+ hifmc100_dma_transfer(host, RW_OP_WRITE);
++ hifmc100_dma_transfer(host, RW_OP_WRITE);
+
-+ FMC_PR(WR_DBG, "\t|*-End send page read cmd\n");
++ FMC_PR(WR_DBG, "\t|*-End send page read cmd\n");
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_read(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(RD_DBG, "\t*-Start send page read cmd\n");
++ FMC_PR(RD_DBG, "\t*-Start send page read cmd\n");
+
-+ if ((host->addr_value[0] == host->cache_addr_value[0])
-+ && (host->addr_value[1] == host->cache_addr_value[1])) {
-+ FMC_PR(RD_DBG, "\t*-Cache hit! addr1[%#x], addr0[%#x]\n",
-+ host->addr_value[1], host->addr_value[0]);
-+ return;
-+ }
++ if ((host->addr_value[0] == host->cache_addr_value[0])
++ && (host->addr_value[1] == host->cache_addr_value[1])) {
++ FMC_PR(RD_DBG, "\t*-Cache hit! addr1[%#x], addr0[%#x]\n",
++ host->addr_value[1], host->addr_value[0]);
++ return;
++ }
+
-+ host->page_status = 0;
++ host->page_status = 0;
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ reg = FMC_INT_CLR_ALL;
-+ hifmc_writel(host, FMC_INT_CLR, reg);
-+ FMC_PR(RD_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
++ reg = FMC_INT_CLR_ALL;
++ hifmc_writel(host, FMC_INT_CLR, reg);
++ FMC_PR(RD_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
+
-+ reg = host->nand_cfg;
-+ hifmc_writel(host, FMC_CFG, reg);
-+ FMC_PR(RD_DBG, "\t|-Set CFG[%#x]%#x\n", FMC_CFG, reg);
++ reg = host->nand_cfg;
++ hifmc_writel(host, FMC_CFG, reg);
++ FMC_PR(RD_DBG, "\t|-Set CFG[%#x]%#x\n", FMC_CFG, reg);
+
-+ reg = host->addr_value[1];
-+ hifmc_writel(host, FMC_ADDRH, reg);
-+ FMC_PR(RD_DBG, "\t|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
++ reg = host->addr_value[1];
++ hifmc_writel(host, FMC_ADDRH, reg);
++ FMC_PR(RD_DBG, "\t|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
+
-+ reg = host->addr_value[0] & 0xffff0000;
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(RD_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ reg = host->addr_value[0] & 0xffff0000;
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(RD_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
-+ reg = FMC_CMD_CMD2(NAND_CMD_READSTART) | FMC_CMD_CMD1(NAND_CMD_READ0);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(RD_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD2(NAND_CMD_READSTART) | FMC_CMD_CMD1(NAND_CMD_READ0);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(RD_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ hifmc100_dma_transfer(host, RW_OP_READ);
++ hifmc100_dma_transfer(host, RW_OP_READ);
+
-+ if (hifmc_readl(host, FMC_INT) & FMC_INT_ERR_INVALID) {
-+ host->page_status |= HIFMC100_PS_UC_ECC;
-+ }
++ if (hifmc_readl(host, FMC_INT) & FMC_INT_ERR_INVALID) {
++ host->page_status |= HIFMC100_PS_UC_ECC;
++ }
+
-+ host->cache_addr_value[0] = host->addr_value[0];
-+ host->cache_addr_value[1] = host->addr_value[1];
++ host->cache_addr_value[0] = host->addr_value[0];
++ host->cache_addr_value[1] = host->addr_value[1];
+
-+ FMC_PR(RD_DBG, "\t*-End send page read cmd\n");
++ FMC_PR(RD_DBG, "\t*-End send page read cmd\n");
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_erase(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(ER_DBG, "\t *-Start send cmd erase\n");
++ FMC_PR(ER_DBG, "\t *-Start send cmd erase\n");
+
-+ /* Don't case the read retry config */
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ /* Don't case the read retry config */
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ reg = host->addr_value[0];
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(ER_DBG, "\t |-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ reg = host->addr_value[0];
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(ER_DBG, "\t |-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
-+ reg = FMC_CMD_CMD2(NAND_CMD_ERASE2) | FMC_CMD_CMD1(NAND_CMD_ERASE1);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(ER_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD2(NAND_CMD_ERASE2) | FMC_CMD_CMD1(NAND_CMD_ERASE1);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(ER_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_ADDR_NUM(host->addr_cycle);
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(ER_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_ADDR_NUM(host->addr_cycle);
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(ER_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ /* need to config WAIT_READY_EN */
-+ reg = FMC_OP_WAIT_READY_EN
-+ | FMC_OP_CMD1_EN
-+ | FMC_OP_CMD2_EN
-+ | FMC_OP_ADDR_EN
-+ | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(ER_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
++ /* need to config WAIT_READY_EN */
++ reg = FMC_OP_WAIT_READY_EN
++ | FMC_OP_CMD1_EN
++ | FMC_OP_CMD2_EN
++ | FMC_OP_ADDR_EN
++ | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(ER_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ FMC_PR(ER_DBG, "\t |*-End send cmd erase\n");
++ FMC_PR(ER_DBG, "\t |*-End send cmd erase\n");
+}
+
+/*****************************************************************************/
+static void hifmc100_ecc_randomizer(struct hifmc_host *host, int ecc_en,
-+ int randomizer_en)
++ int randomizer_en)
+{
-+ unsigned int old_reg, reg, change = 0;
-+ char *ecc_op = ecc_en ? "Quit" : "Enter";
-+ char *rand_op = randomizer_en ? "Enable" : "Disable";
++ unsigned int old_reg, reg, change = 0;
++ char *ecc_op = ecc_en ? "Quit" : "Enter";
++ char *rand_op = randomizer_en ? "Enable" : "Disable";
+
-+ if (IS_NAND_RANDOM(host)) {
-+ reg = old_reg = hifmc_readl(host, FMC_GLOBAL_CFG);
-+ if (randomizer_en) {
-+ reg |= FMC_GLOBAL_CFG_RANDOMIZER_EN;
-+ } else {
-+ reg &= ~FMC_GLOBAL_CFG_RANDOMIZER_EN;
-+ }
++ if (IS_NAND_RANDOM(host)) {
++ reg = old_reg = hifmc_readl(host, FMC_GLOBAL_CFG);
++ if (randomizer_en) {
++ reg |= FMC_GLOBAL_CFG_RANDOMIZER_EN;
++ } else {
++ reg &= ~FMC_GLOBAL_CFG_RANDOMIZER_EN;
++ }
+
-+ if (old_reg != reg) {
-+ FMC_PR(EC_DBG, "\t |*-Start %s randomizer\n", rand_op);
-+ FMC_PR(EC_DBG, "\t ||-Get global CFG[%#x]%#x\n",
-+ FMC_GLOBAL_CFG, old_reg);
-+ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
-+ FMC_PR(EC_DBG, "\t ||-Set global CFG[%#x]%#x\n",
-+ FMC_GLOBAL_CFG, reg);
-+ change++;
-+ }
-+ }
++ if (old_reg != reg) {
++ FMC_PR(EC_DBG, "\t |*-Start %s randomizer\n", rand_op);
++ FMC_PR(EC_DBG, "\t ||-Get global CFG[%#x]%#x\n",
++ FMC_GLOBAL_CFG, old_reg);
++ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
++ FMC_PR(EC_DBG, "\t ||-Set global CFG[%#x]%#x\n",
++ FMC_GLOBAL_CFG, reg);
++ change++;
++ }
++ }
+
-+ old_reg = hifmc_readl(host, FMC_CFG);
-+ reg = (ecc_en ? host->nand_cfg : host->nand_cfg_ecc0);
++ old_reg = hifmc_readl(host, FMC_CFG);
++ reg = (ecc_en ? host->nand_cfg : host->nand_cfg_ecc0);
+
-+ if (old_reg != reg) {
-+ FMC_PR(EC_DBG, "\t |%s-Start %s ECC0 mode\n", change ? "|" : "*",
-+ ecc_op);
-+ FMC_PR(EC_DBG, "\t ||-Get CFG[%#x]%#x\n", FMC_CFG, old_reg);
-+ hifmc_writel(host, FMC_CFG, reg);
-+ FMC_PR(EC_DBG, "\t ||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
-+ change++;
-+ }
++ if (old_reg != reg) {
++ FMC_PR(EC_DBG, "\t |%s-Start %s ECC0 mode\n", change ? "|" : "*",
++ ecc_op);
++ FMC_PR(EC_DBG, "\t ||-Get CFG[%#x]%#x\n", FMC_CFG, old_reg);
++ hifmc_writel(host, FMC_CFG, reg);
++ FMC_PR(EC_DBG, "\t ||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
++ change++;
++ }
+
-+ if (EC_DBG && change) {
-+ FMC_PR(EC_DBG, "\t |*-End randomizer and ECC0 mode config\n");
-+ }
++ if (EC_DBG && change) {
++ FMC_PR(EC_DBG, "\t |*-End randomizer and ECC0 mode config\n");
++ }
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_status(struct hifmc_host *host)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ regval = OP_CFG_FM_CS(host->cmd_op.cs);
-+ hifmc_writel(host, FMC_OP_CFG, regval);
++ regval = OP_CFG_FM_CS(host->cmd_op.cs);
++ hifmc_writel(host, FMC_OP_CFG, regval);
+
-+ regval = FMC_OP_READ_STATUS_EN | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, regval);
++ regval = FMC_OP_READ_STATUS_EN | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, regval);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_readid(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(BT_DBG, "\t *-Start read nand flash ID\n");
++ FMC_PR(BT_DBG, "\t *-Start read nand flash ID\n");
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ reg = FMC_DATA_NUM_CNT(host->cmd_op.data_no);
-+ hifmc_writel(host, FMC_DATA_NUM, reg);
-+ FMC_PR(BT_DBG, "\t |-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
++ reg = FMC_DATA_NUM_CNT(host->cmd_op.data_no);
++ hifmc_writel(host, FMC_DATA_NUM, reg);
++ FMC_PR(BT_DBG, "\t |-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
+
-+ reg = FMC_CMD_CMD1(NAND_CMD_READID);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(BT_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD1(NAND_CMD_READID);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(BT_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ reg = 0;
-+ hifmc_writel(host, FMC_ADDRL, reg);
-+ FMC_PR(BT_DBG, "\t |-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
++ reg = 0;
++ hifmc_writel(host, FMC_ADDRL, reg);
++ FMC_PR(BT_DBG, "\t |-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
-+ | OP_CFG_ADDR_NUM(READ_ID_ADDR_NUM);
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(BT_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs)
++ | OP_CFG_ADDR_NUM(READ_ID_ADDR_NUM);
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(BT_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_OP_CMD1_EN
-+ | FMC_OP_ADDR_EN
-+ | FMC_OP_READ_DATA_EN
-+ | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(BT_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
++ reg = FMC_OP_CMD1_EN
++ | FMC_OP_ADDR_EN
++ | FMC_OP_READ_DATA_EN
++ | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(BT_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ host->addr_cycle = 0x0;
++ host->addr_cycle = 0x0;
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ FMC_PR(BT_DBG, "\t *-End read nand flash ID\n");
++ FMC_PR(BT_DBG, "\t *-End read nand flash ID\n");
+}
+
+/*****************************************************************************/
+static void hifmc100_send_cmd_reset(struct hifmc_host *host)
+{
-+ unsigned int reg;
++ unsigned int reg;
+
-+ FMC_PR(BT_DBG, "\t *-Start reset nand flash\n");
++ FMC_PR(BT_DBG, "\t *-Start reset nand flash\n");
+
-+ reg = FMC_CMD_CMD1(NAND_CMD_RESET);
-+ hifmc_writel(host, FMC_CMD, reg);
-+ FMC_PR(BT_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
++ reg = FMC_CMD_CMD1(NAND_CMD_RESET);
++ hifmc_writel(host, FMC_CMD, reg);
++ FMC_PR(BT_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
+
-+ reg = OP_CFG_FM_CS(host->cmd_op.cs);
-+ hifmc_writel(host, FMC_OP_CFG, reg);
-+ FMC_PR(BT_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
++ reg = OP_CFG_FM_CS(host->cmd_op.cs);
++ hifmc_writel(host, FMC_OP_CFG, reg);
++ FMC_PR(BT_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
+
-+ reg = FMC_OP_CMD1_EN
-+ | FMC_OP_WAIT_READY_EN
-+ | FMC_OP_REG_OP_START;
-+ hifmc_writel(host, FMC_OP, reg);
-+ FMC_PR(BT_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
++ reg = FMC_OP_CMD1_EN
++ | FMC_OP_WAIT_READY_EN
++ | FMC_OP_REG_OP_START;
++ hifmc_writel(host, FMC_OP, reg);
++ FMC_PR(BT_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
+
-+ FMC_CMD_WAIT_CPU_FINISH(host);
++ FMC_CMD_WAIT_CPU_FINISH(host);
+
-+ FMC_PR(BT_DBG, "\t *-End reset nand flash\n");
++ FMC_PR(BT_DBG, "\t *-End reset nand flash\n");
+}
+
+/*****************************************************************************/
+static unsigned char hifmc100_read_byte(struct mtd_info *mtd)
+{
-+ unsigned char value = 0;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ unsigned char value = 0;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ if (host->cmd_op.l_cmd == NAND_CMD_READID) {
-+ value = hifmc_readb((void __iomem *)(chip->IO_ADDR_R + host->offset));
-+ host->offset++;
-+ if (host->cmd_op.data_no == host->offset) {
-+ host->cmd_op.l_cmd = 0;
-+ }
-+ return value;
-+ }
++ if (host->cmd_op.l_cmd == NAND_CMD_READID) {
++ value = hifmc_readb((void __iomem *)(chip->IO_ADDR_R + host->offset));
++ host->offset++;
++ if (host->cmd_op.data_no == host->offset) {
++ host->cmd_op.l_cmd = 0;
++ }
++ return value;
++ }
+
-+ if (host->cmd_op.cmd == NAND_CMD_STATUS) {
-+ value = hifmc_readl(host, FMC_STATUS);
-+ if (host->cmd_op.l_cmd == NAND_CMD_ERASE1) {
-+ FMC_PR(ER_DBG, "\t*-Erase WP status: %#x\n", value);
-+ }
-+ if (host->cmd_op.l_cmd == NAND_CMD_PAGEPROG) {
-+ FMC_PR(WR_DBG, "\t*-Write WP status: %#x\n", value);
-+ }
-+ return value;
-+ }
++ if (host->cmd_op.cmd == NAND_CMD_STATUS) {
++ value = hifmc_readl(host, FMC_STATUS);
++ if (host->cmd_op.l_cmd == NAND_CMD_ERASE1) {
++ FMC_PR(ER_DBG, "\t*-Erase WP status: %#x\n", value);
++ }
++ if (host->cmd_op.l_cmd == NAND_CMD_PAGEPROG) {
++ FMC_PR(WR_DBG, "\t*-Write WP status: %#x\n", value);
++ }
++ return value;
++ }
+
-+ if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
-+ value = hifmc_readb((void __iomem *)(host->buffer + host->pagesize
-+ + host->offset));
-+ host->offset++;
-+ return value;
-+ }
++ if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
++ value = hifmc_readb((void __iomem *)(host->buffer + host->pagesize
++ + host->offset));
++ host->offset++;
++ return value;
++ }
+
-+ host->offset++;
++ host->offset++;
+
-+ return hifmc_readb((void __iomem *)(host->buffer + host->column \
-+ + host->offset - 1));
++ return hifmc_readb((void __iomem *)(host->buffer + host->column \
++ + host->offset - 1));
+}
+
+/*****************************************************************************/
+static unsigned short hifmc100_read_word(struct mtd_info *mtd)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ host->offset += 2;
-+ return hifmc_readw(host->buffer + host->column + host->offset - 2);
++ host->offset += 2;
++ return hifmc_readw(host->buffer + host->column + host->offset - 2);
+}
+
+/*****************************************************************************/
+static void hifmc100_write_buf(struct mtd_info *mtd,
-+ const u_char *buf, int len)
++ const u_char *buf, int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
+#ifdef HIFMC100_NAND_SUPPORT_REG_WRITE
-+ if (buf == chip->oob_poi) {
-+ memcpy((char *)host->iobase + host->pagesize, buf, len);
-+ } else {
-+ memcpy((char *)host->iobase, buf, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy((char *)host->iobase + host->pagesize, buf, len);
++ } else {
++ memcpy((char *)host->iobase, buf, len);
++ }
+#else
-+ if (buf == chip->oob_poi) {
-+ memcpy((char *)host->buffer + host->pagesize, buf, len);
-+ } else {
-+ memcpy((char *)host->buffer, buf, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy((char *)host->buffer + host->pagesize, buf, len);
++ } else {
++ memcpy((char *)host->buffer, buf, len);
++ }
+#endif
-+ return;
++ return;
+}
+
+#ifdef CONFIG_HISI_NAND_ECC_STATUS_REPORT
+/*****************************************************************************/
+static void hifmc100_ecc_err_num_count(struct mtd_info *mtd,
-+ u_int ecc_st, u_int reg)
++ u_int ecc_st, u_int reg)
+{
-+ u_char err_num;
++ u_char err_num;
+
-+ if (ecc_st > 4) {
-+ ecc_st = 4;
-+ }
++ if (ecc_st > 4) {
++ ecc_st = 4;
++ }
+
-+ while (ecc_st) {
-+ err_num = GET_ECC_ERR_NUM(--ecc_st, reg);
-+ if (err_num == 0xff) {
-+ mtd->ecc_stats.failed++;
-+ } else {
-+ mtd->ecc_stats.corrected += err_num;
-+ }
-+ }
++ while (ecc_st) {
++ err_num = GET_ECC_ERR_NUM(--ecc_st, reg);
++ if (err_num == 0xff) {
++ mtd->ecc_stats.failed++;
++ } else {
++ mtd->ecc_stats.corrected += err_num;
++ }
++ }
+}
+#endif
+
+/*****************************************************************************/
+static void hifmc100_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
+#ifdef HIFMC100_NAND_SUPPORT_REG_READ
-+ if (buf == chip->oob_poi) {
-+ memcpy(buf, (char *)host->iobase + host->pagesize, len);
-+ } else {
-+ memcpy(buf, (char *)host->iobase, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy(buf, (char *)host->iobase + host->pagesize, len);
++ } else {
++ memcpy(buf, (char *)host->iobase, len);
++ }
+#else
-+ if (buf == chip->oob_poi) {
-+ memcpy(buf, (char *)host->buffer + host->pagesize, len);
-+ } else {
-+ memcpy(buf, (char *)host->buffer, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy(buf, (char *)host->buffer + host->pagesize, len);
++ } else {
++ memcpy(buf, (char *)host->buffer, len);
++ }
+#endif
+
+#ifdef CONFIG_HISI_NAND_ECC_STATUS_REPORT
-+ if (buf != chip->oob_poi) {
-+ u_int reg, ecc_step = host->pagesize >> 10;
++ if (buf != chip->oob_poi) {
++ u_int reg, ecc_step = host->pagesize >> 10;
+
-+ /* 2K or 4K or 8K(1) or 16K(1-1) pagesize */
-+ reg = hifmc_readl(host, HIFMC100_ECC_ERR_NUM0_BUF0);
-+ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
++ /* 2K or 4K or 8K(1) or 16K(1-1) pagesize */
++ reg = hifmc_readl(host, HIFMC100_ECC_ERR_NUM0_BUF0);
++ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
+
-+ if (ecc_step > 4) {
-+ /* 8K(2) or 16K(1-2) pagesize */
-+ reg = hifmc_readl(host, HIFMC100_ECC_ERR_NUM1_BUF0);
-+ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
-+ if (ecc_step > 8) {
-+ /* 16K(2-1) pagesize */
-+ reg = hifmc_readl(host,
-+ HIFMC100_ECC_ERR_NUM0_BUF1);
-+ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
-+ /* 16K(2-2) pagesize */
-+ reg = hifmc_readl(host,
-+ HIFMC100_ECC_ERR_NUM1_BUF1);
-+ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
-+ }
-+ }
-+ }
++ if (ecc_step > 4) {
++ /* 8K(2) or 16K(1-2) pagesize */
++ reg = hifmc_readl(host, HIFMC100_ECC_ERR_NUM1_BUF0);
++ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
++ if (ecc_step > 8) {
++ /* 16K(2-1) pagesize */
++ reg = hifmc_readl(host,
++ HIFMC100_ECC_ERR_NUM0_BUF1);
++ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
++ /* 16K(2-2) pagesize */
++ reg = hifmc_readl(host,
++ HIFMC100_ECC_ERR_NUM1_BUF1);
++ hifmc100_ecc_err_num_count(mtd, ecc_step, reg);
++ }
++ }
++ }
+#endif
+
-+ return;
++ return;
+}
+
+/*****************************************************************************/
+static void hifmc100_select_chip(struct mtd_info *mtd, int chipselect)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ if (chipselect < 0) {
-+ mutex_unlock(&fmc_switch_mutex);
-+ return;
-+ }
++ if (chipselect < 0) {
++ mutex_unlock(&fmc_switch_mutex);
++ return;
++ }
+
-+ mutex_lock(&fmc_switch_mutex);
++ mutex_lock(&fmc_switch_mutex);
+
-+ if (chipselect > CONFIG_HIFMC100_MAX_NAND_CHIP) {
-+ DB_BUG("Error: Invalid chip select: %d\n", chipselect);
-+ }
++ if (chipselect > CONFIG_HIFMC100_MAX_NAND_CHIP) {
++ DB_BUG("Error: Invalid chip select: %d\n", chipselect);
++ }
+
-+ host->cmd_op.cs = chipselect;
-+ if (host->mtd != mtd) {
-+ host->mtd = mtd;
-+ }
++ host->cmd_op.cs = chipselect;
++ if (host->mtd != mtd) {
++ host->mtd = mtd;
++ }
+
-+ switch (chip->state) {
-+ case FL_ERASING:
-+ host->cmd_op.l_cmd = NAND_CMD_ERASE1;
-+ if (ER_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(ER_DBG, "\t*-Erase chip: %d\n", chipselect);
-+ break;
-+ case FL_WRITING:
-+ host->cmd_op.l_cmd = NAND_CMD_PAGEPROG;
-+ if (WR_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(WR_DBG, "\t*-Write chip: %d\n", chipselect);
-+ break;
-+ case FL_READING:
-+ host->cmd_op.l_cmd = NAND_CMD_READ0;
-+ if (RD_DBG) {
-+ pr_info("\n");
-+ }
-+ FMC_PR(RD_DBG, "\t*-Read chip: %d\n", chipselect);
-+ break;
-+ default:
-+ break;
-+ }
++ switch (chip->state) {
++ case FL_ERASING:
++ host->cmd_op.l_cmd = NAND_CMD_ERASE1;
++ if (ER_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(ER_DBG, "\t*-Erase chip: %d\n", chipselect);
++ break;
++ case FL_WRITING:
++ host->cmd_op.l_cmd = NAND_CMD_PAGEPROG;
++ if (WR_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(WR_DBG, "\t*-Write chip: %d\n", chipselect);
++ break;
++ case FL_READING:
++ host->cmd_op.l_cmd = NAND_CMD_READ0;
++ if (RD_DBG) {
++ pr_info("\n");
++ }
++ FMC_PR(RD_DBG, "\t*-Read chip: %d\n", chipselect);
++ break;
++ default:
++ break;
++ }
+}
+
+/*****************************************************************************/
+static void hifmc100_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned ctrl)
+{
-+ unsigned char cmd;
-+ int is_cache_invalid = 1;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
++ unsigned char cmd;
++ int is_cache_invalid = 1;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
+
-+ if (ctrl & NAND_ALE) {
-+ unsigned int addr_value = 0;
-+ unsigned int addr_offset = 0;
++ if (ctrl & NAND_ALE) {
++ unsigned int addr_value = 0;
++ unsigned int addr_offset = 0;
+
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ host->addr_cycle = 0x0;
-+ host->addr_value[0] = 0x0;
-+ host->addr_value[1] = 0x0;
-+ }
-+ addr_offset = host->addr_cycle << 3;
++ if (ctrl & NAND_CTRL_CHANGE) {
++ host->addr_cycle = 0x0;
++ host->addr_value[0] = 0x0;
++ host->addr_value[1] = 0x0;
++ }
++ addr_offset = host->addr_cycle << 3;
+
-+ if (host->addr_cycle >= HIFMC100_ADDR_CYCLE_MASK) {
-+ addr_offset = (host->addr_cycle -
-+ HIFMC100_ADDR_CYCLE_MASK) << 3;
-+ addr_value = 1;
-+ }
++ if (host->addr_cycle >= HIFMC100_ADDR_CYCLE_MASK) {
++ addr_offset = (host->addr_cycle -
++ HIFMC100_ADDR_CYCLE_MASK) << 3;
++ addr_value = 1;
++ }
+
-+ host->addr_value[addr_value] |=
-+ ((dat & 0xff) << addr_offset);
++ host->addr_value[addr_value] |=
++ ((dat & 0xff) << addr_offset);
+
-+ host->addr_cycle++;
-+ }
++ host->addr_cycle++;
++ }
+
-+ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
-+ cmd = dat & 0xff;
-+ host->cmd_op.cmd = cmd;
-+ switch (cmd) {
-+ case NAND_CMD_PAGEPROG:
-+ host->offset = 0;
-+ host->send_cmd_pageprog(host);
-+ break;
++ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
++ cmd = dat & 0xff;
++ host->cmd_op.cmd = cmd;
++ switch (cmd) {
++ case NAND_CMD_PAGEPROG:
++ host->offset = 0;
++ host->send_cmd_pageprog(host);
++ break;
+
-+ case NAND_CMD_READSTART:
-+ is_cache_invalid = 0;
-+ if (host->addr_value[0] == host->pagesize) {
-+ host->cmd_op.l_cmd = NAND_CMD_READOOB;
-+ }
-+ host->send_cmd_readstart(host);
-+ break;
++ case NAND_CMD_READSTART:
++ is_cache_invalid = 0;
++ if (host->addr_value[0] == host->pagesize) {
++ host->cmd_op.l_cmd = NAND_CMD_READOOB;
++ }
++ host->send_cmd_readstart(host);
++ break;
+
-+ case NAND_CMD_ERASE2:
-+ host->cmd_op.l_cmd = cmd;
-+ host->send_cmd_erase(host);
-+ break;
++ case NAND_CMD_ERASE2:
++ host->cmd_op.l_cmd = cmd;
++ host->send_cmd_erase(host);
++ break;
+
-+ case NAND_CMD_READID:
-+ memset((u_char *)(chip->IO_ADDR_R), 0, MAX_NAND_ID_LEN);
-+ host->cmd_op.l_cmd = cmd;
-+ host->cmd_op.data_no = MAX_NAND_ID_LEN;
-+ host->send_cmd_readid(host);
-+ break;
++ case NAND_CMD_READID:
++ memset((u_char *)(chip->IO_ADDR_R), 0, MAX_NAND_ID_LEN);
++ host->cmd_op.l_cmd = cmd;
++ host->cmd_op.data_no = MAX_NAND_ID_LEN;
++ host->send_cmd_readid(host);
++ break;
+
-+ case NAND_CMD_STATUS:
-+ host->send_cmd_status(host);
-+ break;
++ case NAND_CMD_STATUS:
++ host->send_cmd_status(host);
++ break;
+
-+ case NAND_CMD_READ0:
-+ host->cmd_op.l_cmd = cmd;
-+ break;
++ case NAND_CMD_READ0:
++ host->cmd_op.l_cmd = cmd;
++ break;
+
-+ case NAND_CMD_RESET:
-+ host->send_cmd_reset(host);
-+ break;
++ case NAND_CMD_RESET:
++ host->send_cmd_reset(host);
++ break;
+
-+ case NAND_CMD_SEQIN:
-+ case NAND_CMD_ERASE1:
-+ default:
-+ break;
-+ }
-+ }
++ case NAND_CMD_SEQIN:
++ case NAND_CMD_ERASE1:
++ default:
++ break;
++ }
++ }
+
-+ /* pass pagesize and ecctype to kernel when startup. */
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ /* pass pagesize and ecctype to kernel when startup. */
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
-+ if (host->cmd_op.cmd == NAND_CMD_SEQIN
-+ || host->cmd_op.cmd == NAND_CMD_READ0
-+ || host->cmd_op.cmd == NAND_CMD_READID) {
-+ host->offset = 0x0;
-+ host->column = (host->addr_value[0] & 0xffff);
-+ }
-+ }
++ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
++ if (host->cmd_op.cmd == NAND_CMD_SEQIN
++ || host->cmd_op.cmd == NAND_CMD_READ0
++ || host->cmd_op.cmd == NAND_CMD_READID) {
++ host->offset = 0x0;
++ host->column = (host->addr_value[0] & 0xffff);
++ }
++ }
+
-+ if (is_cache_invalid) {
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
-+ }
++ if (is_cache_invalid) {
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
++ }
+}
+
+/*****************************************************************************/
+static int hifmc100_dev_ready(struct mtd_info *mtd)
+{
-+ return 0x1;
++ return 0x1;
+}
+
+/*****************************************************************************/
@@ -290448,125 +358658,125 @@ index 0000000..7623b93
+ * 'host->epm' only use the first oobfree[0] field, it looks very simple, But...
+ */
+static int hifmc_ooblayout_ecc_default(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 32;
-+ oobregion->offset = 32;
++ oobregion->length = 32;
++ oobregion->offset = 32;
+
-+ return 0;
++ return 0;
+}
+
+static int hifmc_ooblayout_free_default(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 30;
-+ oobregion->offset = 2;
++ oobregion->length = 30;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+
+static struct mtd_ooblayout_ops hifmc_ooblayout_default_ops = {
-+ .ecc = hifmc_ooblayout_ecc_default,
-+ .free = hifmc_ooblayout_free_default,
++ .ecc = hifmc_ooblayout_ecc_default,
++ .free = hifmc_ooblayout_free_default,
+};
+
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
+static int hifmc_ooblayout_ecc_4k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 14;
-+ oobregion->offset = 14;
++ oobregion->length = 14;
++ oobregion->offset = 14;
+
-+ return 0;
++ return 0;
+}
+
+static int hifmc_ooblayout_free_4k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 14;
-+ oobregion->offset = 2;
++ oobregion->length = 14;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+tatic struct mtd_ooblayout_ops hifmc_ooblayout_4k16bit_ops = {
-+ .ecc = hifmc_ooblayout_ecc_4k16bit,
-+ .free = hifmc_ooblayout_free_4k16bit,
++ .ecc = hifmc_ooblayout_ecc_4k16bit,
++ .free = hifmc_ooblayout_free_4k16bit,
+};
+
+static int hifmc_ooblayout_ecc_2k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 6;
-+ oobregion->offset = 6;
++ oobregion->length = 6;
++ oobregion->offset = 6;
+
-+ return 0;
++ return 0;
+}
+
+static int hifmc_ooblayout_free_2k16bit(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 6;
-+ oobregion->offset = 2;
++ oobregion->length = 6;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+
+static struct mtd_ooblayout_ops hifmc_ooblayout_2k16bit_ops = {
-+ .ecc = hifmc_ooblayout_ecc_2k16bit,
-+ .free = hifmc_ooblayout_free_2k16bit,
++ .ecc = hifmc_ooblayout_ecc_2k16bit,
++ .free = hifmc_ooblayout_free_2k16bit,
+};
+#endif
+/*****************************************************************************/
+/* ecc/pagesize get from NAND controller */
+static struct nand_config_info hifmc100_nand_hw_auto_config_table[] = {
-+ {NAND_PAGE_16K, NAND_ECC_64BIT, 64, 1824/*1824*/, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_16K, NAND_ECC_40BIT, 40, 1200/*1152*/, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_16K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_16K, NAND_ECC_64BIT, 64, 1824/*1824*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_16K, NAND_ECC_40BIT, 40, 1200/*1152*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_16K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
+
-+ {NAND_PAGE_8K, NAND_ECC_64BIT, 64, 928 /*928*/, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_8K, NAND_ECC_40BIT, 40, 600 /*592*/, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_8K, NAND_ECC_24BIT, 24, 368 /*368*/, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_8K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_8K, NAND_ECC_64BIT, 64, 928 /*928*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_8K, NAND_ECC_40BIT, 40, 600 /*592*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_8K, NAND_ECC_24BIT, 24, 368 /*368*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_8K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
+
-+ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200 /*200*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200 /*200*/, &hifmc_ooblayout_default_ops},
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
-+ {NAND_PAGE_4K, NAND_ECC_16BIT, 16, 128 /*128*/, &hifmc_ooblayout_4k16bit_ops},
++ {NAND_PAGE_4K, NAND_ECC_16BIT, 16, 128 /*128*/, &hifmc_ooblayout_4k16bit_ops},
+#endif
-+ {NAND_PAGE_4K, NAND_ECC_8BIT, 8, 128 /*88*/, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_4K, NAND_ECC_8BIT, 8, 128 /*88*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
+
-+ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128 /*116*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128 /*116*/, &hifmc_ooblayout_default_ops},
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
-+ {NAND_PAGE_2K, NAND_ECC_16BIT, 16, 64 /*64*/, &hifmc_ooblayout_2k16bit_ops},
++ {NAND_PAGE_2K, NAND_ECC_16BIT, 16, 64 /*64*/, &hifmc_ooblayout_2k16bit_ops},
+#endif
-+ {NAND_PAGE_2K, NAND_ECC_8BIT, 8, 64 /*60*/, &hifmc_ooblayout_default_ops},
-+ {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_2K, NAND_ECC_8BIT, 8, 64 /*60*/, &hifmc_ooblayout_default_ops},
++ {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
+
-+ {0, 0, 0, 0, NULL},
++ {0, 0, 0, 0, NULL},
+};
+
+/*****************************************************************************/
@@ -290576,392 +358786,392 @@ index 0000000..7623b93
+ */
+static int hifmc100_nand_support_randomizer(u_int pageisze, u_int ecctype)
+{
-+ switch (pageisze) {
-+ case _8K:
-+ return (ecctype >= NAND_ECC_24BIT && ecctype <= NAND_ECC_80BIT);
-+ case _16K:
-+ return (ecctype >= NAND_ECC_40BIT && ecctype <= NAND_ECC_80BIT);
-+ case _32K:
-+ return (ecctype >= NAND_ECC_40BIT && ecctype <= NAND_ECC_80BIT);
-+ default:
-+ return 0;
-+ }
++ switch (pageisze) {
++ case _8K:
++ return (ecctype >= NAND_ECC_24BIT && ecctype <= NAND_ECC_80BIT);
++ case _16K:
++ return (ecctype >= NAND_ECC_40BIT && ecctype <= NAND_ECC_80BIT);
++ case _32K:
++ return (ecctype >= NAND_ECC_40BIT && ecctype <= NAND_ECC_80BIT);
++ default:
++ return 0;
++ }
+}
+
+/*****************************************************************************/
+/* used the best correct arithmetic. */
+static struct nand_config_info *hifmc100_get_config_type_info(
-+ struct mtd_info *mtd, struct nand_dev_t *nand_dev)
++ struct mtd_info *mtd, struct nand_dev_t *nand_dev)
+{
-+ struct nand_config_info *best = NULL;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
-+ struct nand_config_info *info = hifmc100_nand_hw_auto_config_table;
++ struct nand_config_info *best = NULL;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
++ struct nand_config_info *info = hifmc100_nand_hw_auto_config_table;
+
-+ nand_dev->start_type = "Auto";
-+ nand_dev->flags |= (IS_NANDC_HW_AUTO(host) | IS_NANDC_CONFIG_DONE(host));
++ nand_dev->start_type = "Auto";
++ nand_dev->flags |= (IS_NANDC_HW_AUTO(host) | IS_NANDC_CONFIG_DONE(host));
+
-+ for (; info->ooblayout_ops; info++) {
-+ if (match_page_type_to_size(info->pagetype) != mtd->writesize) {
-+ continue;
-+ }
++ for (; info->ooblayout_ops; info++) {
++ if (match_page_type_to_size(info->pagetype) != mtd->writesize) {
++ continue;
++ }
+
-+ if (mtd->oobsize < info->oobsize) {
-+ continue;
-+ }
++ if (mtd->oobsize < info->oobsize) {
++ continue;
++ }
+
-+ if (!best || (best->ecctype < info->ecctype)) {
-+ best = info;
-+ }
-+ }
++ if (!best || (best->ecctype < info->ecctype)) {
++ best = info;
++ }
++ }
+
-+ return best;
++ return best;
+}
+
+/*****************************************************************************/
+static unsigned int hifmc100_get_ecc_reg(struct hifmc_host *host,
-+ struct nand_config_info *info, struct nand_dev_t *nand_dev)
++ struct nand_config_info *info, struct nand_dev_t *nand_dev)
+{
-+ host->ecctype = info->ecctype;
-+ FMC_PR(BT_DBG, "\t |-Save best EccType %d(%s)\n", host->ecctype,
-+ match_ecc_type_to_str(info->ecctype));
++ host->ecctype = info->ecctype;
++ FMC_PR(BT_DBG, "\t |-Save best EccType %d(%s)\n", host->ecctype,
++ match_ecc_type_to_str(info->ecctype));
+
-+ nand_dev->ecctype = host->ecctype;
++ nand_dev->ecctype = host->ecctype;
+
-+ return FMC_CFG_ECC_TYPE(match_ecc_type_to_reg(info->ecctype));
++ return FMC_CFG_ECC_TYPE(match_ecc_type_to_reg(info->ecctype));
+}
+
+/*****************************************************************************/
+static unsigned int hifmc100_get_page_reg(struct hifmc_host *host,
-+ struct nand_config_info *info)
++ struct nand_config_info *info)
+{
-+ host->pagesize = match_page_type_to_size(info->pagetype);
-+ FMC_PR(BT_DBG, "\t |-Save best PageSize %d(%s)\n", host->pagesize,
-+ match_page_type_to_str(info->pagetype));
++ host->pagesize = match_page_type_to_size(info->pagetype);
++ FMC_PR(BT_DBG, "\t |-Save best PageSize %d(%s)\n", host->pagesize,
++ match_page_type_to_str(info->pagetype));
+
-+ return FMC_CFG_PAGE_SIZE(match_page_type_to_reg(info->pagetype));
++ return FMC_CFG_PAGE_SIZE(match_page_type_to_reg(info->pagetype));
+}
+
+/*****************************************************************************/
+static unsigned int hifmc100_get_block_reg(struct hifmc_host *host,
-+ struct nand_config_info *info)
++ struct nand_config_info *info)
+{
-+ unsigned int block_reg = 0, page_per_block;
-+ struct mtd_info *mtd = host->mtd;
++ unsigned int block_reg = 0, page_per_block;
++ struct mtd_info *mtd = host->mtd;
+
-+ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
-+ page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
-+ switch (page_per_block) {
-+ case 64:
-+ block_reg = BLOCK_SIZE_64_PAGE;
-+ break;
-+ case 128:
-+ block_reg = BLOCK_SIZE_128_PAGE;
-+ break;
-+ case 256:
-+ block_reg = BLOCK_SIZE_256_PAGE;
-+ break;
-+ case 512:
-+ block_reg = BLOCK_SIZE_512_PAGE;
-+ break;
-+ default:
-+ DB_MSG("Can't support block %#x and page %#x size\n",
-+ mtd->erasesize, mtd->writesize);
-+ }
++ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
++ page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
++ switch (page_per_block) {
++ case 64:
++ block_reg = BLOCK_SIZE_64_PAGE;
++ break;
++ case 128:
++ block_reg = BLOCK_SIZE_128_PAGE;
++ break;
++ case 256:
++ block_reg = BLOCK_SIZE_256_PAGE;
++ break;
++ case 512:
++ block_reg = BLOCK_SIZE_512_PAGE;
++ break;
++ default:
++ DB_MSG("Can't support block %#x and page %#x size\n",
++ mtd->erasesize, mtd->writesize);
++ }
+
-+ return FMC_CFG_BLOCK_SIZE(block_reg);
++ return FMC_CFG_BLOCK_SIZE(block_reg);
+}
+
+/*****************************************************************************/
+static void hifmc100_set_fmc_cfg_reg(struct hifmc_host *host,
-+ struct nand_config_info *type_info, struct nand_dev_t *nand_dev)
++ struct nand_config_info *type_info, struct nand_dev_t *nand_dev)
+{
-+ unsigned int page_reg, ecc_reg, block_reg, reg_fmc_cfg;
++ unsigned int page_reg, ecc_reg, block_reg, reg_fmc_cfg;
+
-+ ecc_reg = hifmc100_get_ecc_reg(host, type_info, nand_dev);
-+ page_reg = hifmc100_get_page_reg(host, type_info);
-+ block_reg = hifmc100_get_block_reg(host, type_info);
++ ecc_reg = hifmc100_get_ecc_reg(host, type_info, nand_dev);
++ page_reg = hifmc100_get_page_reg(host, type_info);
++ block_reg = hifmc100_get_block_reg(host, type_info);
+
-+ if (hifmc100_nand_support_randomizer(host->pagesize, host->ecctype)) {
-+ host->flags |= IS_NAND_RANDOM(nand_dev);
-+ }
++ if (hifmc100_nand_support_randomizer(host->pagesize, host->ecctype)) {
++ host->flags |= IS_NAND_RANDOM(nand_dev);
++ }
+
-+ /*
-+ * Check if hardware enable randomizer PIN, But NAND does not need
-+ * randomizer. We will notice user.
-+ */
-+ if (IS_NAND_RANDOM(host) &&
-+ !hifmc100_nand_support_randomizer(host->pagesize, host->ecctype)) {
-+ DB_BUG(ERSTR_HARDWARE
-+ "This NAND flash does not support `randomizer`, "
-+ "Please don't configure hardware randomizer PIN.");
-+ }
-+ /* Save value of FMC_CFG and FMC_CFG_ECC0 to turn on/off ECC */
-+ reg_fmc_cfg = hifmc_readl(host, FMC_CFG);
-+ reg_fmc_cfg &= ~(PAGE_SIZE_MASK | ECC_TYPE_MASK | BLOCK_SIZE_MASK);
-+ reg_fmc_cfg |= ecc_reg | page_reg | block_reg;
-+ host->nand_cfg = reg_fmc_cfg;
-+ host->nand_cfg_ecc0 = (host->nand_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
-+ FMC_PR(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
-+ FMC_CFG, host->nand_cfg, host->nand_cfg_ecc0);
++ /*
++ * Check if hardware enable randomizer PIN, But NAND does not need
++ * randomizer. We will notice user.
++ */
++ if (IS_NAND_RANDOM(host) &&
++ !hifmc100_nand_support_randomizer(host->pagesize, host->ecctype)) {
++ DB_BUG(ERSTR_HARDWARE
++ "This NAND flash does not support `randomizer`, "
++ "Please don't configure hardware randomizer PIN.");
++ }
++ /* Save value of FMC_CFG and FMC_CFG_ECC0 to turn on/off ECC */
++ reg_fmc_cfg = hifmc_readl(host, FMC_CFG);
++ reg_fmc_cfg &= ~(PAGE_SIZE_MASK | ECC_TYPE_MASK | BLOCK_SIZE_MASK);
++ reg_fmc_cfg |= ecc_reg | page_reg | block_reg;
++ host->nand_cfg = reg_fmc_cfg;
++ host->nand_cfg_ecc0 = (host->nand_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
++ FMC_PR(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
++ FMC_CFG, host->nand_cfg, host->nand_cfg_ecc0);
+
-+ /* pass pagesize and ecctype to kernel when spiflash startup. */
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ /* pass pagesize and ecctype to kernel when spiflash startup. */
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ /*
-+ * If it want to support the 'read retry' feature, the 'randomizer'
-+ * feature must be support first.
-+ */
-+ host->read_retry = NULL;
++ /*
++ * If it want to support the 'read retry' feature, the 'randomizer'
++ * feature must be support first.
++ */
++ host->read_retry = NULL;
+
-+ if (host->read_retry && !IS_NAND_RANDOM(host)) {
-+ DB_BUG(ERSTR_HARDWARE
-+ "This Nand flash need to enable 'randomizer' feature. "
-+ "Please configure hardware randomizer PIN.");
-+ }
++ if (host->read_retry && !IS_NAND_RANDOM(host)) {
++ DB_BUG(ERSTR_HARDWARE
++ "This Nand flash need to enable 'randomizer' feature. "
++ "Please configure hardware randomizer PIN.");
++ }
+}
+
+/*****************************************************************************/
+static void hifmc100_set_oob_info(struct mtd_info *mtd,
-+ struct nand_config_info *info, struct nand_dev_t *nand_dev)
++ struct nand_config_info *info, struct nand_dev_t *nand_dev)
+{
-+ int buffer_len;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hifmc_host *host = chip->priv;
-+ struct mtd_oob_region hifmc_oobregion = {0, 0};
++ int buffer_len;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hifmc_host *host = chip->priv;
++ struct mtd_oob_region hifmc_oobregion = {0, 0};
+
-+ if (info->ecctype != NAND_ECC_0BIT) {
-+ mtd->oobsize = info->oobsize;
-+ }
-+ mtd->oobavail = HIFMC100_NAND_OOBSIZE_FOR_YAFFS;
++ if (info->ecctype != NAND_ECC_0BIT) {
++ mtd->oobsize = info->oobsize;
++ }
++ mtd->oobavail = HIFMC100_NAND_OOBSIZE_FOR_YAFFS;
+
-+ host->oobsize = mtd->oobsize;
++ host->oobsize = mtd->oobsize;
+
-+ buffer_len = host->pagesize + host->oobsize;
++ buffer_len = host->pagesize + host->oobsize;
+
-+ memset(host->buffer, 0xff, buffer_len);
-+ host->dma_oob = host->dma_buffer + host->pagesize;
++ memset(host->buffer, 0xff, buffer_len);
++ host->dma_oob = host->dma_buffer + host->pagesize;
+
-+ host->bbm = (unsigned char *)(host->buffer + host->pagesize
-+ + HIFMC100_BAD_BLOCK_POS);
++ host->bbm = (unsigned char *)(host->buffer + host->pagesize
++ + HIFMC100_BAD_BLOCK_POS);
+
-+ info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
++ info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
+
-+ mtd_set_ooblayout(mtd, info->ooblayout_ops);
++ mtd_set_ooblayout(mtd, info->ooblayout_ops);
+
-+ /* EB bits locate in the bottom two of CTRL(30) */
-+ host->epm = (u_short *)(host->buffer + host->pagesize
-+ + hifmc_oobregion.offset + 28);
++ /* EB bits locate in the bottom two of CTRL(30) */
++ host->epm = (u_short *)(host->buffer + host->pagesize
++ + hifmc_oobregion.offset + 28);
+
+#ifdef CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2
-+ if (best->ecctype == NAND_ECC_16BIT) {
-+ if (host->pagesize == _2K) {
-+ /* EB bits locate in the bottom two of CTRL(4) */
-+ host->epm = (u_short *)(host->buffer + host->pagesize
-+ + hifmc_oobregion.offset + 4);
-+ } else if (host->pagesize == _4K) {
-+ /* EB bit locate in the bottom two of CTRL(14) */
-+ host->epm = (u_short *)(host->buffer + host->pagesize
-+ + hifmc_oobregion.offset + 12);
-+ }
-+ }
++ if (best->ecctype == NAND_ECC_16BIT) {
++ if (host->pagesize == _2K) {
++ /* EB bits locate in the bottom two of CTRL(4) */
++ host->epm = (u_short *)(host->buffer + host->pagesize
++ + hifmc_oobregion.offset + 4);
++ } else if (host->pagesize == _4K) {
++ /* EB bit locate in the bottom two of CTRL(14) */
++ host->epm = (u_short *)(host->buffer + host->pagesize
++ + hifmc_oobregion.offset + 12);
++ }
++ }
+#endif
+}
+/*****************************************************************************/
+static int hifmc100_set_config_info(struct mtd_info *mtd,
-+ struct nand_chip *chip, struct nand_dev_t *dev)
++ struct nand_chip *chip, struct nand_dev_t *dev)
+{
-+ struct hifmc_host *host = chip->priv;
-+ struct nand_dev_t *nand_dev = dev;
-+ struct nand_config_info *type_info = NULL;
++ struct hifmc_host *host = chip->priv;
++ struct nand_dev_t *nand_dev = dev;
++ struct nand_config_info *type_info = NULL;
+
-+ FMC_PR(BT_DBG, "\t*-Start config Block Page OOB and Ecc\n");
++ FMC_PR(BT_DBG, "\t*-Start config Block Page OOB and Ecc\n");
+
-+ type_info = hifmc100_get_config_type_info(mtd, nand_dev);
-+ BUG_ON(!type_info);
++ type_info = hifmc100_get_config_type_info(mtd, nand_dev);
++ BUG_ON(!type_info);
+
-+ FMC_PR(BT_DBG, "\t|-%s Config, PageSize %s EccType %s OobSize %d\n",
-+ nand_dev->start_type, nand_page_name(type_info->pagetype),
-+ nand_ecc_name(type_info->ecctype), type_info->oobsize);
++ FMC_PR(BT_DBG, "\t|-%s Config, PageSize %s EccType %s OobSize %d\n",
++ nand_dev->start_type, nand_page_name(type_info->pagetype),
++ nand_ecc_name(type_info->ecctype), type_info->oobsize);
+
-+ /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
-+ hifmc100_set_fmc_cfg_reg(host, type_info, nand_dev);
++ /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
++ hifmc100_set_fmc_cfg_reg(host, type_info, nand_dev);
+
-+ hifmc100_set_oob_info(mtd, type_info, nand_dev);
++ hifmc100_set_oob_info(mtd, type_info, nand_dev);
+
-+ if (mtd->writesize > NAND_MAX_PAGESIZE
-+ || mtd->oobsize > NAND_MAX_OOBSIZE) {
-+ DB_BUG(ERSTR_DRIVER
-+ "Driver does not support this Nand Flash. Please " \
-+ "increase NAND_MAX_PAGESIZE and NAND_MAX_OOBSIZE.\n");
-+ }
++ if (mtd->writesize > NAND_MAX_PAGESIZE
++ || mtd->oobsize > NAND_MAX_OOBSIZE) {
++ DB_BUG(ERSTR_DRIVER
++ "Driver does not support this Nand Flash. Please " \
++ "increase NAND_MAX_PAGESIZE and NAND_MAX_OOBSIZE.\n");
++ }
+
-+ /* Some Nand Flash devices have subpage structure */
-+ if (mtd->writesize != host->pagesize) {
-+ unsigned int shift = 0;
-+ unsigned int writesize = mtd->writesize;
++ /* Some Nand Flash devices have subpage structure */
++ if (mtd->writesize != host->pagesize) {
++ unsigned int shift = 0;
++ unsigned int writesize = mtd->writesize;
+
-+ while (writesize > host->pagesize) {
-+ writesize >>= 1;
-+ shift++;
-+ }
-+ chip->chipsize = chip->chipsize >> shift;
-+ mtd->erasesize = mtd->erasesize >> shift;
-+ mtd->writesize = host->pagesize;
-+ pr_info("Nand divide into 1/%u\n", (1 << shift));
-+ }
++ while (writesize > host->pagesize) {
++ writesize >>= 1;
++ shift++;
++ }
++ chip->chipsize = chip->chipsize >> shift;
++ mtd->erasesize = mtd->erasesize >> shift;
++ mtd->writesize = host->pagesize;
++ pr_info("Nand divide into 1/%u\n", (1 << shift));
++ }
+
-+ FMC_PR(BT_DBG, "\t*-End config Block Page Oob and Ecc\n");
++ FMC_PR(BT_DBG, "\t*-End config Block Page Oob and Ecc\n");
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+static void hifmc100_chip_init(struct nand_chip *chip)
+{
-+ struct hifmc_host *host = chip->priv;
++ struct hifmc_host *host = chip->priv;
+
-+ memset((char *)chip->IO_ADDR_R, 0xff, host->dma_len);
++ memset((char *)chip->IO_ADDR_R, 0xff, host->dma_len);
+
-+ chip->read_byte = hifmc100_read_byte;
-+ chip->read_word = hifmc100_read_word;
-+ chip->write_buf = hifmc100_write_buf;
-+ chip->read_buf = hifmc100_read_buf;
++ chip->read_byte = hifmc100_read_byte;
++ chip->read_word = hifmc100_read_word;
++ chip->write_buf = hifmc100_write_buf;
++ chip->read_buf = hifmc100_read_buf;
+
-+ chip->select_chip = hifmc100_select_chip;
++ chip->select_chip = hifmc100_select_chip;
+
-+ chip->cmd_ctrl = hifmc100_cmd_ctrl;
-+ chip->dev_ready = hifmc100_dev_ready;
++ chip->cmd_ctrl = hifmc100_cmd_ctrl;
++ chip->dev_ready = hifmc100_dev_ready;
+
-+ chip->chip_delay = FMC_CHIP_DELAY;
++ chip->chip_delay = FMC_CHIP_DELAY;
+
-+ chip->options = NAND_NEED_READRDY | NAND_BROKEN_XD
-+ | NAND_SKIP_BBTSCAN;
++ chip->options = NAND_NEED_READRDY | NAND_BROKEN_XD
++ | NAND_SKIP_BBTSCAN;
+
-+ chip->ecc.mode = NAND_ECC_NONE;
++ chip->ecc.mode = NAND_ECC_NONE;
+}
+
+/*****************************************************************************/
+static int hifmc100_host_init(struct hifmc_host *host)
+{
-+ unsigned int reg, flash_type;
++ unsigned int reg, flash_type;
+
-+ FMC_PR(BT_DBG, "\t *-Start nand host init\n");
++ FMC_PR(BT_DBG, "\t *-Start nand host init\n");
+
-+ reg = hifmc_readl(host, FMC_CFG);
-+ FMC_PR(BT_DBG, "\t |-Read FMC CFG[%#x]%#x\n", FMC_CFG, reg);
-+ flash_type = GET_SPI_FLASH_TYPE(reg);
-+ if (flash_type != FLASH_TYPE_NAND) {
-+ DB_MSG("Error: Flash type isn't Nand flash. reg[%#x]\n", reg);
-+ reg |= FMC_CFG_FLASH_SEL(FLASH_TYPE_NAND);
-+ FMC_PR(BT_DBG, "\t |-Change flash type to Nand flash\n");
-+ }
++ reg = hifmc_readl(host, FMC_CFG);
++ FMC_PR(BT_DBG, "\t |-Read FMC CFG[%#x]%#x\n", FMC_CFG, reg);
++ flash_type = GET_SPI_FLASH_TYPE(reg);
++ if (flash_type != FLASH_TYPE_NAND) {
++ DB_MSG("Error: Flash type isn't Nand flash. reg[%#x]\n", reg);
++ reg |= FMC_CFG_FLASH_SEL(FLASH_TYPE_NAND);
++ FMC_PR(BT_DBG, "\t |-Change flash type to Nand flash\n");
++ }
+
-+ if ((reg & FMC_CFG_OP_MODE_MASK) == FMC_CFG_OP_MODE_BOOT) {
-+ reg |= FMC_CFG_OP_MODE(FMC_CFG_OP_MODE_NORMAL);
-+ FMC_PR(BT_DBG, "\t |-Controller enter normal mode\n");
-+ }
-+ hifmc_writel(host, FMC_CFG, reg);
-+ FMC_PR(BT_DBG, "\t |-Set CFG[%#x]%#x\n", FMC_CFG, reg);
++ if ((reg & FMC_CFG_OP_MODE_MASK) == FMC_CFG_OP_MODE_BOOT) {
++ reg |= FMC_CFG_OP_MODE(FMC_CFG_OP_MODE_NORMAL);
++ FMC_PR(BT_DBG, "\t |-Controller enter normal mode\n");
++ }
++ hifmc_writel(host, FMC_CFG, reg);
++ FMC_PR(BT_DBG, "\t |-Set CFG[%#x]%#x\n", FMC_CFG, reg);
+
-+ host->nand_cfg = reg;
-+ host->nand_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
++ host->nand_cfg = reg;
++ host->nand_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
+
-+ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
-+ FMC_PR(BT_DBG, "\t |-Read global CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
-+ if (reg & FMC_GLOBAL_CFG_RANDOMIZER_EN) {
-+ host->flags &= ~NAND_RANDOMIZER;
-+ FMC_PR(BT_DBG, "\t |-Default disable randomizer\n");
-+ reg &= ~FMC_GLOBAL_CFG_RANDOMIZER_EN;
-+ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
-+ FMC_PR(BT_DBG, "\t |-Set global CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
-+ }
++ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
++ FMC_PR(BT_DBG, "\t |-Read global CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
++ if (reg & FMC_GLOBAL_CFG_RANDOMIZER_EN) {
++ host->flags &= ~NAND_RANDOMIZER;
++ FMC_PR(BT_DBG, "\t |-Default disable randomizer\n");
++ reg &= ~FMC_GLOBAL_CFG_RANDOMIZER_EN;
++ hifmc_writel(host, FMC_GLOBAL_CFG, reg);
++ FMC_PR(BT_DBG, "\t |-Set global CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
++ }
+
+#ifdef CONFIG_HIFMC100_NAND_EDO_MODE
-+ /* enable EDO node */
-+ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
-+ hifmc_writel(host, FMC_GLOBAL_CFG, SET_NAND_EDO_MODE_EN(reg));
++ /* enable EDO node */
++ reg = hifmc_readl(host, FMC_GLOBAL_CFG);
++ hifmc_writel(host, FMC_GLOBAL_CFG, SET_NAND_EDO_MODE_EN(reg));
+#endif
+
-+ host->addr_cycle = 0;
-+ host->addr_value[0] = 0;
-+ host->addr_value[1] = 0;
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
++ host->addr_cycle = 0;
++ host->addr_value[0] = 0;
++ host->addr_value[1] = 0;
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
+
-+ host->send_cmd_pageprog = hifmc100_send_cmd_write;
-+ host->send_cmd_status = hifmc100_send_cmd_status;
-+ host->send_cmd_readstart = hifmc100_send_cmd_read;
-+ host->send_cmd_erase = hifmc100_send_cmd_erase;
-+ host->send_cmd_readid = hifmc100_send_cmd_readid;
-+ host->send_cmd_reset = hifmc100_send_cmd_reset;
++ host->send_cmd_pageprog = hifmc100_send_cmd_write;
++ host->send_cmd_status = hifmc100_send_cmd_status;
++ host->send_cmd_readstart = hifmc100_send_cmd_read;
++ host->send_cmd_erase = hifmc100_send_cmd_erase;
++ host->send_cmd_readid = hifmc100_send_cmd_readid;
++ host->send_cmd_reset = hifmc100_send_cmd_reset;
+
-+ /*
-+ * check if start from nand.
-+ * This register REG_SYSSTAT is set in start.S
-+ * When start in NAND (Auto), the ECC/PAGESIZE driver don't detect.
-+ */
-+ host->flags |= NANDC_HW_AUTO;
++ /*
++ * check if start from nand.
++ * This register REG_SYSSTAT is set in start.S
++ * When start in NAND (Auto), the ECC/PAGESIZE driver don't detect.
++ */
++ host->flags |= NANDC_HW_AUTO;
+
-+ if (GET_SYS_BOOT_MODE(reg) == BOOT_FROM_NAND) {
-+ host->flags |= NANDC_CONFIG_DONE;
-+ FMC_PR(BT_DBG, "\t |-Auto config pagesize and ecctype\n");
-+ }
++ if (GET_SYS_BOOT_MODE(reg) == BOOT_FROM_NAND) {
++ host->flags |= NANDC_CONFIG_DONE;
++ FMC_PR(BT_DBG, "\t |-Auto config pagesize and ecctype\n");
++ }
+
-+ host->enable_ecc_randomizer = hifmc100_ecc_randomizer;
++ host->enable_ecc_randomizer = hifmc100_ecc_randomizer;
+
-+ FMC_PR(BT_DBG, "\t *-End nand host init\n");
++ FMC_PR(BT_DBG, "\t *-End nand host init\n");
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+int hifmc100_nand_init(struct nand_chip *chip)
+{
-+ struct hifmc_host *host = chip->priv;
++ struct hifmc_host *host = chip->priv;
+
-+ /* enable and set system clock */
-+ clk_prepare_enable(host->clk);
++ /* enable and set system clock */
++ clk_prepare_enable(host->clk);
+
-+ /* fmc ip version check */
-+ host->version = hifmc_readl(host, FMC_VERSION);
-+ if (host->version != HIFMC_VER_100) {
-+ return -EFAULT;
-+ }
-+ pr_info("Found Flash Memory Controller v100 Nand Driver\n");
++ /* fmc ip version check */
++ host->version = hifmc_readl(host, FMC_VERSION);
++ if (host->version != HIFMC_VER_100) {
++ return -EFAULT;
++ }
++ pr_info("Found Flash Memory Controller v100 Nand Driver\n");
+
-+ /* hifmc host init */
-+ if (hifmc100_host_init(host)) {
-+ DB_MSG("Error: Nand host init failed!\n");
-+ return -EFAULT;
-+ }
-+ host->chip = chip;
++ /* hifmc host init */
++ if (hifmc100_host_init(host)) {
++ DB_MSG("Error: Nand host init failed!\n");
++ return -EFAULT;
++ }
++ host->chip = chip;
+
-+ hifmc_writel(host, FMC_PND_PWIDTH_CFG, PWIDTH_CFG_RW_HCNT(CONFIG_RW_H_WIDTH)
-+ | PWIDTH_CFG_R_LCNT(CONFIG_R_L_WIDTH)
-+ | PWIDTH_CFG_W_LCNT(CONFIG_W_L_WIDTH));
++ hifmc_writel(host, FMC_PND_PWIDTH_CFG, PWIDTH_CFG_RW_HCNT(CONFIG_RW_H_WIDTH)
++ | PWIDTH_CFG_R_LCNT(CONFIG_R_L_WIDTH)
++ | PWIDTH_CFG_W_LCNT(CONFIG_W_L_WIDTH));
+
-+ /* hifmc nand_chip struct init */
-+ hifmc100_chip_init(chip);
++ /* hifmc nand_chip struct init */
++ hifmc100_chip_init(chip);
+
-+ hifmc_spl_ids_register();
-+ hinfc_param_adjust = hifmc100_set_config_info;
++ hifmc_spl_ids_register();
++ hinfc_param_adjust = hifmc100_set_config_info;
+
-+ return 0;
++ return 0;
+}
+
+#ifdef CONFIG_PM
+/*****************************************************************************/
+void hifmc100_nand_config(struct hifmc_host *host)
+{
-+ /* enable system clock */
-+ clk_prepare_enable(host->clk);
-+ FMC_PR(PM_DBG, "\t |-enable system clock\n");
++ /* enable system clock */
++ clk_prepare_enable(host->clk);
++ FMC_PR(PM_DBG, "\t |-enable system clock\n");
+}
+#endif /* CONFIG_PM */
diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.h b/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.h
new file mode 100644
-index 0000000..01e714c
+index 0000000..150e29b
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.h
@@ -0,0 +1,165 @@
@@ -291038,80 +359248,80 @@ index 0000000..01e714c
+#define SET_NAND_EDO_MODE_EN(reg) ((reg) | NAND_EDO_MODE_MASK)
+/*****************************************************************************/
+struct hifmc_host {
-+ struct nand_chip *chip;
-+ struct mtd_info *mtd;
++ struct nand_chip *chip;
++ struct mtd_info *mtd;
+
-+ struct hifmc_cmd_op cmd_op;
-+ void __iomem *regbase;
-+ void __iomem *iobase;
++ struct hifmc_cmd_op cmd_op;
++ void __iomem *regbase;
++ void __iomem *iobase;
+
-+ /* Controller config option nand flash */
-+ unsigned int nand_cfg;
-+ unsigned int nand_cfg_ecc0;
++ /* Controller config option nand flash */
++ unsigned int nand_cfg;
++ unsigned int nand_cfg_ecc0;
+
-+ unsigned int offset;
++ unsigned int offset;
+
-+ struct device *dev;
++ struct device *dev;
+
-+ /* This is maybe an un-aligment address, only for malloc or free */
-+ char *buforg;
-+ char *buffer;
++ /* This is maybe an un-aligment address, only for malloc or free */
++ char *buforg;
++ char *buffer;
+
+#ifdef CONFIG_64BIT
-+ unsigned long long dma_buffer;
-+ unsigned long long dma_oob;
++ unsigned long long dma_buffer;
++ unsigned long long dma_oob;
+#else
-+ unsigned int dma_buffer;
-+ unsigned int dma_oob;
++ unsigned int dma_buffer;
++ unsigned int dma_oob;
+#endif
-+ unsigned int dma_len;
++ unsigned int dma_len;
+
-+ unsigned int addr_cycle;
-+ unsigned int addr_value[2];
-+ unsigned int cache_addr_value[2];
++ unsigned int addr_cycle;
++ unsigned int addr_value[2];
++ unsigned int cache_addr_value[2];
+
-+ unsigned int column;
-+ unsigned int block_page_mask;
++ unsigned int column;
++ unsigned int block_page_mask;
+
-+ unsigned int ecctype;
-+ unsigned int pagesize;
-+ unsigned int oobsize;
++ unsigned int ecctype;
++ unsigned int pagesize;
++ unsigned int oobsize;
+
-+ int need_rr_data;
++ int need_rr_data;
+#define HIFMC100_READ_RETRY_DATA_LEN 128
-+ char rr_data[HIFMC100_READ_RETRY_DATA_LEN];
-+ int version;
-+ int add_partition;
++ char rr_data[HIFMC100_READ_RETRY_DATA_LEN];
++ int version;
++ int add_partition;
+
-+ /* BOOTROM read two bytes to detect the bad block flag */
++ /* BOOTROM read two bytes to detect the bad block flag */
+#define HIFMC100_BAD_BLOCK_POS 0
-+ unsigned char *bbm; /* nand bad block mark */
-+ unsigned short *epm; /* nand empty page mark */
-+ unsigned int flags;
++ unsigned char *bbm; /* nand bad block mark */
++ unsigned short *epm; /* nand empty page mark */
++ unsigned int flags;
+
+#define HIFMC100_PS_UC_ECC 0x01 /* page has ecc error */
+#define HIFMC100_PS_BAD_BLOCK 0x02 /* bad block */
+#define HIFMC100_PS_EMPTY_PAGE 0x04 /* page is empty */
+#define HIFMC100_PS_EPM_ERROR 0x0100 /* empty page mark word has error. */
+#define HIFMC100_PS_BBM_ERROR 0x0200 /* bad block mark word has error. */
-+ unsigned int page_status;
++ unsigned int page_status;
+
-+ struct clk *clk;
++ struct clk *clk;
+
-+ void (*send_cmd_pageprog)(struct hifmc_host *host);
-+ void (*send_cmd_status)(struct hifmc_host *host);
-+ void (*send_cmd_readstart)(struct hifmc_host *host);
-+ void (*send_cmd_erase)(struct hifmc_host *host);
-+ void (*send_cmd_readid)(struct hifmc_host *host);
-+ void (*send_cmd_reset)(struct hifmc_host *host);
-+ void (*enable)(int enable);
++ void (*send_cmd_pageprog)(struct hifmc_host *host);
++ void (*send_cmd_status)(struct hifmc_host *host);
++ void (*send_cmd_readstart)(struct hifmc_host *host);
++ void (*send_cmd_erase)(struct hifmc_host *host);
++ void (*send_cmd_readid)(struct hifmc_host *host);
++ void (*send_cmd_reset)(struct hifmc_host *host);
++ void (*enable)(int enable);
+
-+ void (*enable_ecc_randomizer)(struct hifmc_host *host,
-+ int ecc_en, int randomizer_en);
++ void (*enable_ecc_randomizer)(struct hifmc_host *host,
++ int ecc_en, int randomizer_en);
+
-+ void (*detect_ecc)(struct hifmc_host *host);
++ void (*detect_ecc)(struct hifmc_host *host);
+
-+ struct read_retry_t *read_retry;
++ struct read_retry_t *read_retry;
+};
+
+/*****************************************************************************/
@@ -291132,7 +359342,7 @@ index 0000000..01e714c
+#endif /* End of __HIFMC100_NAND_H__ */
diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc100_nand_os.c b/drivers/mtd/nand/hifmc100_nand/hifmc100_nand_os.c
new file mode 100644
-index 0000000..3cca2e2
+index 0000000..b5a9b4b
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100_nand/hifmc100_nand_os.c
@@ -0,0 +1,183 @@
@@ -291165,153 +359375,153 @@ index 0000000..3cca2e2
+/*****************************************************************************/
+static inline int mtd_has_partitions(void)
+{
-+ return 1;
++ return 1;
+}
+
+/*****************************************************************************/
+static int hisi_nand_os_probe(struct platform_device *pltdev)
+{
-+ int len, result = 0;
-+ struct hifmc_host *host;
-+ struct nand_chip *chip;
-+ struct mtd_info *mtd;
-+ int nr_parts = 0;
-+ struct mtd_partition *parts = NULL;
-+ struct device *dev = &pltdev->dev;
-+ struct device_node *np = NULL;
-+ struct hisi_fmc *fmc = dev_get_drvdata(dev->parent);
++ int len, result = 0;
++ struct hifmc_host *host = NULL;
++ struct nand_chip *chip = NULL;
++ struct mtd_info *mtd = NULL;
++ int nr_parts = 0;
++ struct mtd_partition *parts = NULL;
++ struct device *dev = &pltdev->dev;
++ struct device_node *np = NULL;
++ struct hisi_fmc *fmc = dev_get_drvdata(dev->parent);
+
-+ if (!fmc) {
-+ dev_err(dev, "get mfd fmc devices failed\n");
-+ return -ENXIO;
-+ }
++ if (!fmc) {
++ dev_err(dev, "get mfd fmc devices failed\n");
++ return -ENXIO;
++ }
+
-+ len = sizeof(struct hifmc_host) + sizeof(struct nand_chip)
-+ + sizeof(struct mtd_info);
-+ host = devm_kzalloc(dev, len, GFP_KERNEL);
-+ if (!host) {
-+ return -ENOMEM;
-+ }
-+ memset((char *)host, 0, len);
-+ platform_set_drvdata(pltdev, host);
++ len = sizeof(struct hifmc_host) + sizeof(struct nand_chip)
++ + sizeof(struct mtd_info);
++ host = devm_kzalloc(dev, len, GFP_KERNEL);
++ if (!host) {
++ return -ENOMEM;
++ }
++ memset((char *)host, 0, len);
++ platform_set_drvdata(pltdev, host);
+
-+ host->dev = &pltdev->dev;
-+ host->chip = chip = (struct nand_chip *)&host[1];
-+ host->mtd = mtd = nand_to_mtd(chip);
-+ host->regbase = fmc->regbase;
-+ host->iobase = fmc->iobase;
-+ host->clk = fmc->clk;
-+ chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
-+ host->buffer = fmc->buffer;
-+ host->dma_buffer = fmc->dma_buffer;
-+ host->dma_len = fmc->dma_len;
++ host->dev = &pltdev->dev;
++ host->chip = chip = (struct nand_chip *)&host[1];
++ host->mtd = mtd = nand_to_mtd(chip);
++ host->regbase = fmc->regbase;
++ host->iobase = fmc->iobase;
++ host->clk = fmc->clk;
++ chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
++ host->buffer = fmc->buffer;
++ host->dma_buffer = fmc->dma_buffer;
++ host->dma_len = fmc->dma_len;
+
-+ /* hifmc Nand host init */
-+ chip->priv = host;
-+ result = hifmc100_nand_init(chip);
-+ if (result) {
-+ DB_MSG("Error: host init failed! result: %d\n", result);
-+ goto fail;
-+ }
++ /* hifmc Nand host init */
++ chip->priv = host;
++ result = hifmc100_nand_init(chip);
++ if (result) {
++ DB_MSG("Error: host init failed! result: %d\n", result);
++ goto fail;
++ }
+
-+ np = of_get_next_available_child(dev->of_node, NULL);
-+ mtd->name = np->name;
-+ mtd->type = MTD_NANDFLASH;
-+ mtd->priv = chip;
-+ mtd->flags = MTD_CAP_NANDFLASH;
-+ mtd->owner = THIS_MODULE;
++ np = of_get_next_available_child(dev->of_node, NULL);
++ mtd->name = np->name;
++ mtd->type = MTD_NANDFLASH;
++ mtd->priv = chip;
++ mtd->flags = MTD_CAP_NANDFLASH;
++ mtd->owner = THIS_MODULE;
+
-+ if (nand_scan(mtd, CONFIG_HIFMC100_MAX_NAND_CHIP)) {
-+ result = -ENXIO;
-+ goto fail;
-+ }
++ if (nand_scan(mtd, CONFIG_HIFMC100_MAX_NAND_CHIP)) {
++ result = -ENXIO;
++ goto fail;
++ }
+
-+ result = mtd_device_register(host->mtd, parts, nr_parts);
-+ if (result) {
-+ kfree(parts);
-+ parts = NULL;
-+ }
++ result = mtd_device_register(host->mtd, parts, nr_parts);
++ if (result) {
++ kfree(parts);
++ parts = NULL;
++ }
+
-+ return (result == 1) ? -ENODEV : 0;
++ return (result == 1) ? -ENODEV : 0;
+
+fail:
-+ clk_disable_unprepare(host->clk);
-+ nand_release(mtd);
-+ return result;
++ clk_disable_unprepare(host->clk);
++ nand_release(mtd);
++ return result;
+}
+
+/*****************************************************************************/
+static int hisi_nand_os_remove(struct platform_device *pltdev)
+{
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
+
-+ clk_disable_unprepare(host->clk);
-+ nand_release(host->mtd);
++ clk_disable_unprepare(host->clk);
++ nand_release(host->mtd);
+
-+ return 0;
++ return 0;
+}
+
+#ifdef CONFIG_PM
+/*****************************************************************************/
+static int hifmc100_nand_os_suspend(struct platform_device *pltdev,
-+ pm_message_t state)
++ pm_message_t state)
+{
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
-+ if (!host) {
-+ return 0;
-+ }
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ if (!host) {
++ return 0;
++ }
+
-+ while ((hifmc_readl(host, FMC_OP) & FMC_OP_REG_OP_START)) {
-+ _cond_resched();
-+ }
++ while ((hifmc_readl(host, FMC_OP) & FMC_OP_REG_OP_START)) {
++ _cond_resched();
++ }
+
-+ while ((hifmc_readl(host, FMC_OP_CTRL) & OP_CTRL_DMA_OP_READY)) {
-+ _cond_resched();
-+ }
++ while ((hifmc_readl(host, FMC_OP_CTRL) & OP_CTRL_DMA_OP_READY)) {
++ _cond_resched();
++ }
+
-+ clk_disable_unprepare(host->clk);
-+ FMC_PR(PM_DBG, "\t|-disable system clock\n");
-+ return 0;
++ clk_disable_unprepare(host->clk);
++ FMC_PR(PM_DBG, "\t|-disable system clock\n");
++ return 0;
+}
+
+/*****************************************************************************/
+static int hifmc100_nand_os_resume(struct platform_device *pltdev)
+{
-+ int cs;
-+ struct hifmc_host *host = platform_get_drvdata(pltdev);
-+ struct nand_chip *chip;
++ int cs;
++ struct hifmc_host *host = platform_get_drvdata(pltdev);
++ struct nand_chip *chip = NULL;
+
-+ if (!host) {
-+ return 0;
-+ }
-+ chip = host->chip;
++ if (!host) {
++ return 0;
++ }
++ chip = host->chip;
+
-+ for (cs = 0; cs < chip->numchips; cs++) {
-+ host->send_cmd_reset(host);
-+ }
++ for (cs = 0; cs < chip->numchips; cs++) {
++ host->send_cmd_reset(host);
++ }
+
-+ hifmc100_nand_config(host);
-+ return 0;
++ hifmc100_nand_config(host);
++ return 0;
+}
+#endif /* CONFIG_PM */
+
+/*****************************************************************************/
+static const struct of_device_id hisi_nand_dt_ids[] = {
-+ { .compatible = "hisilicon,hisi_nand" },
-+ { /* sentinel */ }
++ { .compatible = "hisilicon,hisi_nand" },
++ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, hisi_nand_dt_ids);
+
+static struct platform_driver hisi_nand_driver = {
-+ .driver = {
-+ .name = "hisi_nand",
-+ .of_match_table = hisi_nand_dt_ids,
-+ },
-+ .probe = hisi_nand_os_probe,
-+ .remove = hisi_nand_os_remove,
++ .driver = {
++ .name = "hisi_nand",
++ .of_match_table = hisi_nand_dt_ids,
++ },
++ .probe = hisi_nand_os_probe,
++ .remove = hisi_nand_os_remove,
+#ifdef CONFIG_PM
-+ .suspend = hifmc100_nand_os_suspend,
-+ .resume = hifmc100_nand_os_resume,
++ .suspend = hifmc100_nand_os_suspend,
++ .resume = hifmc100_nand_os_resume,
+#endif
+};
+module_platform_driver(hisi_nand_driver);
@@ -291401,7 +359611,7 @@ index 0000000..6414d12
+#endif /* End of __HIFMC100_NAND_OS_H__ */
diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc_nand_spl_ids.c b/drivers/mtd/nand/hifmc100_nand/hifmc_nand_spl_ids.c
new file mode 100644
-index 0000000..463eb69
+index 0000000..489e47b
--- /dev/null
+++ b/drivers/mtd/nand/hifmc100_nand/hifmc_nand_spl_ids.c
@@ -0,0 +1,980 @@
@@ -291437,22 +359647,22 @@ index 0000000..463eb69
+
+/*****************************************************************************/
+struct nand_flash_special_dev {
-+ unsigned char id[8];
-+ int length; /* length of id. */
-+ unsigned long long chipsize;
-+ struct nand_flash_dev *(*probe)(unsigned char *id);
-+ char *name;
++ unsigned char id[8];
++ int length; /* length of id. */
++ unsigned long long chipsize;
++ struct nand_flash_dev *(*probe)(unsigned char *id);
++ char *name;
+
-+ unsigned long pagesize;
-+ unsigned long erasesize;
-+ unsigned long oobsize;
-+ unsigned long options;
-+ unsigned int read_retry_type;
++ unsigned long pagesize;
++ unsigned long erasesize;
++ unsigned long oobsize;
++ unsigned long options;
++ unsigned int read_retry_type;
+
+#define BBP_LAST_PAGE 0x01
+#define BBP_FIRST_PAGE 0x02
-+ unsigned int badblock_pos;
-+ int flags;
++ unsigned int badblock_pos;
++ int flags;
+};
+
+/*****************************************************************************/
@@ -291461,41 +359671,41 @@ index 0000000..463eb69
+
+static struct nand_flash_dev *hynix_probe_v02(unsigned char *id)
+{
-+ struct nand_flash_dev *type = &g_nand_dev.flash_dev;
++ struct nand_flash_dev *type = &g_nand_dev.flash_dev;
+
-+ int pagesizes[] = {_2K, _4K, _8K, 0};
-+ int oobsizes[] = {128, 224, 448, 0, 0, 0, 0, 0};
-+ int blocksizes[] = {_128K, _256K, _512K, _768K, _1M, _2M, 0, 0};
++ int pagesizes[] = {_2K, _4K, _8K, 0};
++ int oobsizes[] = {128, 224, 448, 0, 0, 0, 0, 0};
++ int blocksizes[] = {_128K, _256K, _512K, _768K, _1M, _2M, 0, 0};
+
-+ int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
-+ int oobtype = (((id[3] >> 2) & 0x03) | ((id[3] >> 4) & 0x04));
++ int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
++ int oobtype = (((id[3] >> 2) & 0x03) | ((id[3] >> 4) & 0x04));
+
-+ type->options = 0;
-+ type->pagesize = pagesizes[(id[3] & 0x03)];
-+ type->erasesize = blocksizes[blocktype];
-+ type->oobsize = oobsizes[oobtype];
++ type->options = 0;
++ type->pagesize = pagesizes[(id[3] & 0x03)];
++ type->erasesize = blocksizes[blocktype];
++ type->oobsize = oobsizes[oobtype];
+
-+ return type;
++ return type;
+}
+
+/*****************************************************************************/
+static struct nand_flash_dev *samsung_probe_v02(unsigned char *id)
+{
-+ struct nand_flash_dev *type = &g_nand_dev.flash_dev;
++ struct nand_flash_dev *type = &g_nand_dev.flash_dev;
+
-+ int pagesizes[] = {_2K, _4K, _8K, 0};
-+ int oobsizes[] = {0, 128, 218, 400, 436, 0, 0, 0};
-+ int blocksizes[] = {_128K, _256K, _512K, _1M, 0, 0, 0, 0};
++ int pagesizes[] = {_2K, _4K, _8K, 0};
++ int oobsizes[] = {0, 128, 218, 400, 436, 0, 0, 0};
++ int blocksizes[] = {_128K, _256K, _512K, _1M, 0, 0, 0, 0};
+
-+ int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
-+ int oobtype = (((id[3] >> 4) & 0x04) | ((id[3] >> 2) & 0x03));
++ int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
++ int oobtype = (((id[3] >> 4) & 0x04) | ((id[3] >> 2) & 0x03));
+
-+ type->options = 0;
-+ type->pagesize = pagesizes[(id[3] & 0x03)];
-+ type->erasesize = blocksizes[blocktype];
-+ type->oobsize = oobsizes[oobtype];
++ type->options = 0;
++ type->pagesize = pagesizes[(id[3] & 0x03)];
++ type->erasesize = blocksizes[blocktype];
++ type->oobsize = oobsizes[oobtype];
+
-+ return type;
++ return type;
+}
+
+/*****************************************************************************/
@@ -291570,820 +359780,820 @@ index 0000000..463eb69
+ */
+static struct nand_flash_special_dev nand_flash_special_table[] = {
+
-+ /************************* 1.8V MXIC Macronix **************************/
-+ { /* SLC 4bit/512 1.8V */
-+ .name = "MX30UF2G18AC",
-+ .id = {0xC2, 0xAA, 0x90, 0x15, 0x06},
-+ .length = 5,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 64,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
++ /************************* 1.8V MXIC Macronix **************************/
++ { /* SLC 4bit/512 1.8V */
++ .name = "MX30UF2G18AC",
++ .id = {0xC2, 0xAA, 0x90, 0x15, 0x06},
++ .length = 5,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 64,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
+
-+ /****************************** Spansion *******************************/
++ /****************************** Spansion *******************************/
+
-+ { /* SLC S34ML02G200TFI000 */
-+ .name = "S34ML02G200TFI000",
-+ .id = {0x01, 0xDA, 0x90, 0x95, 0x46, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
++ { /* SLC S34ML02G200TFI000 */
++ .name = "S34ML02G200TFI000",
++ .id = {0x01, 0xDA, 0x90, 0x95, 0x46, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
+
-+ { /* SLC S34ML04G200TFI000 */
-+ .name = "S34ML04G200TFI000",
-+ .id = {0x01, 0xDC, 0x90, 0x95, 0x56, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _512M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
++ { /* SLC S34ML04G200TFI000 */
++ .name = "S34ML04G200TFI000",
++ .id = {0x01, 0xDC, 0x90, 0x95, 0x56, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _512M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
+
-+ { /* SLC S34MS02G200TFI00 1.8V */
-+ .name = "S34MS02G200TFI00",
-+ .id = {0x01, 0xAA, 0x90, 0x15, 0x46, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
++ { /* SLC S34MS02G200TFI00 1.8V */
++ .name = "S34MS02G200TFI00",
++ .id = {0x01, 0xAA, 0x90, 0x15, 0x46, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
+
-+ { /* SLC S34MS04G200TFI00 1.8V */
-+ .name = "S34MS04G200TFI00",
-+ .id = {0x01, 0xAC, 0x90, 0x15, 0x56, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _512M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
++ { /* SLC S34MS04G200TFI00 1.8V */
++ .name = "S34MS04G200TFI00",
++ .id = {0x01, 0xAC, 0x90, 0x15, 0x56, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _512M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
+
-+ /****************************** Micron *******************************/
++ /****************************** Micron *******************************/
+
-+ { /* MLC 40bit/1k */
-+ .name = "MT29F64G08CBABA",
-+ .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _8G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 744,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_MICRON,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = NAND_RANDOMIZER | NAND_CHIP_MICRON,
-+ },
-+ { /* MLC 40bit/1k */
-+ .name = "MT29F32G08CBADA",
-+ .id = {0x2C, 0x44, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 744,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_MICRON,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* SLC 4bit/512 */
-+ .name = "MT29F8G08ABxBA",
-+ .id = {0x2C, 0x38, 0x00, 0x26, 0x85, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _1G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _512K,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 12bit/512 */
-+ .name = "MT29F16G08CBABx",
-+ .id = {0x2C, 0x48, 0x04, 0x46, 0x85, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _2G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _1M,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1k */
-+ .name = "MT29F16G08CBACA",
-+ .id = {0x2C, 0x48, 0x04, 0x4A, 0xA5, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _2G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _1M,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1k */
-+ .name = "MT29F32G08CBACA",
-+ .id = {0x2C, 0x68, 0x04, 0x4A, 0xA9, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _1M,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1k */
-+ .name = "MT29F64G08CxxAA",
-+ .id = {0x2C, 0x88, 0x04, 0x4B, 0xA9, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _8G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 448,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* MLC 24bit/1k 2CE */
-+ .name = "MT29F256G08CJAAA",
-+ .id = {0x2C, 0xA8, 0x05, 0xCB, 0xA9, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _16G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 448,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* MLC 40bit/1k */
-+ .name = "MT29F256G08CMCBB",
-+ .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
-+ .length = 8,
-+ .chipsize = _8G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 744,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 8bit/512 */
-+ .name = "MT29F8G08ABACA",
-+ .id = {0x2C, 0xD3, 0x90, 0xA6, 0x64, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _1G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _256K,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 8bit/512 */
-+ .name = "MT29F4G08ABAEA",
-+ .id = {0x2C, 0xDC, 0x90, 0xA6, 0x54, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _512M,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _256K,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 8bit/512 */
-+ .name = "MT29F2G08ABAFA",
-+ .id = {0x2C, 0xDA, 0x90, 0x95, 0x04, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC MT29F2G08ABAEA */
-+ .name = "MT29F2G08ABAEA",
-+ .id = {0x2C, 0xDA, 0x90, 0x95, 0x06, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 64,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 8bit/512 */
-+ .name = "MT29F16G08ABACA",
-+ .id = {0x2C, 0x48, 0x00, 0x26, 0xA9, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _2G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _512K,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
++ { /* MLC 40bit/1k */
++ .name = "MT29F64G08CBABA",
++ .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _8G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 744,
++ .options = 0,
++ .read_retry_type = NAND_RR_MICRON,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = NAND_RANDOMIZER | NAND_CHIP_MICRON,
++ },
++ { /* MLC 40bit/1k */
++ .name = "MT29F32G08CBADA",
++ .id = {0x2C, 0x44, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 744,
++ .options = 0,
++ .read_retry_type = NAND_RR_MICRON,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* SLC 4bit/512 */
++ .name = "MT29F8G08ABxBA",
++ .id = {0x2C, 0x38, 0x00, 0x26, 0x85, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _1G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _512K,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 12bit/512 */
++ .name = "MT29F16G08CBABx",
++ .id = {0x2C, 0x48, 0x04, 0x46, 0x85, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _2G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _1M,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1k */
++ .name = "MT29F16G08CBACA",
++ .id = {0x2C, 0x48, 0x04, 0x4A, 0xA5, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _2G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _1M,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1k */
++ .name = "MT29F32G08CBACA",
++ .id = {0x2C, 0x68, 0x04, 0x4A, 0xA9, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _1M,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1k */
++ .name = "MT29F64G08CxxAA",
++ .id = {0x2C, 0x88, 0x04, 0x4B, 0xA9, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _8G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 448,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* MLC 24bit/1k 2CE */
++ .name = "MT29F256G08CJAAA",
++ .id = {0x2C, 0xA8, 0x05, 0xCB, 0xA9, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _16G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 448,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* MLC 40bit/1k */
++ .name = "MT29F256G08CMCBB",
++ .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
++ .length = 8,
++ .chipsize = _8G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 744,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 8bit/512 */
++ .name = "MT29F8G08ABACA",
++ .id = {0x2C, 0xD3, 0x90, 0xA6, 0x64, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _1G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _256K,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 8bit/512 */
++ .name = "MT29F4G08ABAEA",
++ .id = {0x2C, 0xDC, 0x90, 0xA6, 0x54, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _512M,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _256K,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 8bit/512 */
++ .name = "MT29F2G08ABAFA",
++ .id = {0x2C, 0xDA, 0x90, 0x95, 0x04, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC MT29F2G08ABAEA */
++ .name = "MT29F2G08ABAEA",
++ .id = {0x2C, 0xDA, 0x90, 0x95, 0x06, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 64,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 8bit/512 */
++ .name = "MT29F16G08ABACA",
++ .id = {0x2C, 0x48, 0x00, 0x26, 0xA9, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _2G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _512K,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
+
-+ /****************************** Toshaba *******************************/
++ /****************************** Toshaba *******************************/
+
-+ { /* MLC 24bit/1k 32nm */
-+ .name = "TC58NVG4D2FTA00",
-+ .id = {0x98, 0xD5, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _2G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _1M,
-+ .oobsize = 448,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1k 32nm 2CE*/
-+ .name = "TH58NVG6D2FTA20",
-+ .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _1M,
-+ .oobsize = 448,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 40bit/1k 24nm */
-+ .name = "TC58NVG5D2HTA00 24nm",
-+ .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x56, 0x08, 0x00},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _1M,
-+ .oobsize = 640,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_TOSHIBA_24nm,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* MLC 40bit/1k */
-+ .name = "TC58NVG6D2GTA00",
-+ .id = {0x98, 0xDE, 0x94, 0x82, 0x76, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _8G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 640,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 19nm */
-+ .name = "TC58NVG6DCJTA00 19nm",
-+ .id = {0x98, 0xDE, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
-+ .length = 8,
-+ .chipsize = _8G,
-+ .probe = NULL,
-+ .pagesize = _16K,
-+ .erasesize = _4M,
-+ .oobsize = 1280,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_TOSHIBA_24nm,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* MLC 19nm */
-+ .name = "TC58TEG5DCJTA00 19nm",
-+ .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _16K,
-+ .erasesize = _4M,
-+ .oobsize = 1280,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_TOSHIBA_24nm,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER | NAND_CHIP_TOSHIBA_TOGGLE_10,
-+ },
-+ { /* SLC 8bit/512 */
-+ .name = "TC58NVG0S3HTA00",
-+ .id = {0x98, 0xF1, 0x80, 0x15, 0x72, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _128M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ /*
-+ * Datasheet: read one column of any page in each block. If the
-+ * data of the column is 00 (Hex), define the block as a bad
-+ * block.
-+ */
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 8bit/512 */
-+ .name = "TC58NVG1S3HTA00",
-+ .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x16, 0x08, 0x00},
-+ .length = 7,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 4bit/512 */
-+ .name = "TC58NVG1S3ETA00",
-+ .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x14, 0x03, 0x00},
-+ .length = 7,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 64,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 4bit/512 */
-+ .name = "TC58NVG3S0FTA00",
-+ .id = {0x98, 0xD3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08},
-+ .length = 8,
-+ .chipsize = _1G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _256K,
-+ .oobsize = 232,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 24bit/1k */
-+ .name = "TC58NVG3S0HTA00",
-+ .id = {0x98, 0xD3, 0x91, 0x26, 0x76, 0x16, 0x08, 0x00},
-+ .length = 8,
-+ .chipsize = _1G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _256K,
-+ .oobsize = 256,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 24bit/1k */
-+ .name = "TC58NVG2S0HTA00",
-+ .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00},
-+ .length = 8,
-+ .chipsize = _512M,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _256K,
-+ .oobsize = 256,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 4bit/512 */
-+ .name = "TC58NVG2S0FTA00",
-+ .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08},
-+ .length = 8,
-+ .chipsize = _512M,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _256K,
-+ .oobsize = 224,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 4bit/512 */
-+ .name = "TH58NVG2S3HTA00",
-+ .id = {0x98, 0xDC, 0x91, 0x15, 0x76},
-+ .length = 5,
-+ .chipsize = _512M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* TLC 60bit/1k 19nm */
-+ .name = "TC58NVG5T2JTA00 19nm TLC",
-+ /* datasheet says 6 ids id data, but really has 8 ids. */
-+ .id = {0x98, 0xD7, 0x98, 0x92, 0x72, 0x57, 0x08, 0x10},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _4M,
-+ .oobsize = 1024,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_TOSHIBA_24nm,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* TLC 60bit/1k 19nm */
-+ .name = "TC58TEG5DCKTAx0 19nm MLC",
-+ /* datasheet says 6 ids id data, but really has 8 ids. */
-+ .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x50, 0x08, 0x04},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _16K,
-+ .erasesize = _4M,
-+ .oobsize = 1280,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_TOSHIBA_19nm,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ {
-+ .name = "Tx58TEGxDDKTAx0 19nm MLC",
-+ .id = {0x98, 0xDE, 0x94, 0x93, 0x76, 0x50},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _16K,
-+ .erasesize = _4M,
-+ .oobsize = 1280,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_TOSHIBA_19nm,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ /******************************* Samsung ******************************/
-+ { /* MLC 8bit/512B */
-+ .name = "K9LB(HC/PD/MD)G08U0(1)D",
-+ .id = {0xEC, 0xD7, 0xD5, 0x29, 0x38, 0x41, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = samsung_probe_v02,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1KB */
-+ .name = "K9GAG08U0E",
-+ .id = {0xEC, 0xD5, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _2G,
-+ .probe = samsung_probe_v02,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1KB */
-+ .name = "K9LBG08U0E",
-+ .id = {0xEC, 0xD7, 0xC5, 0x72, 0x54, 0x42, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = samsung_probe_v02,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1KB */
-+ .name = "K9G8G08U0C",
-+ .id = {0xEC, 0xD3, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _1G,
-+ .probe = samsung_probe_v02,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1k */
-+ .name = "K9GAG08U0F",
-+ .id = {0xEC, 0xD5, 0x94, 0x76, 0x54, 0x43, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _2G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _1M,
-+ .oobsize = 512,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC */
-+ .name = "K9LBG08U0M",
-+ .id = {0xEC, 0xD7, 0x55, 0xB6, 0x78, 0x00, 0x00, 0x00},
-+ .length = 5,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _512K,
-+ .oobsize = 128,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1k */
-+ .name = "K9GBG08U0A 20nm",
-+ .id = {0xEC, 0xD7, 0x94, 0x7A, 0x54, 0x43, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _1M,
-+ .oobsize = 640,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_SAMSUNG,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* MLC 40bit/1k */
-+ .name = "K9GBG08U0B",
-+ .id = {0xEC, 0xD7, 0x94, 0x7E, 0x64, 0x44, 0x00, 0x00},
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _1M,
-+ .oobsize = 1024,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_SAMSUNG,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
++ { /* MLC 24bit/1k 32nm */
++ .name = "TC58NVG4D2FTA00",
++ .id = {0x98, 0xD5, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _2G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _1M,
++ .oobsize = 448,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1k 32nm 2CE*/
++ .name = "TH58NVG6D2FTA20",
++ .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _1M,
++ .oobsize = 448,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 40bit/1k 24nm */
++ .name = "TC58NVG5D2HTA00 24nm",
++ .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x56, 0x08, 0x00},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _1M,
++ .oobsize = 640,
++ .options = 0,
++ .read_retry_type = NAND_RR_TOSHIBA_24nm,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* MLC 40bit/1k */
++ .name = "TC58NVG6D2GTA00",
++ .id = {0x98, 0xDE, 0x94, 0x82, 0x76, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _8G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 640,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 19nm */
++ .name = "TC58NVG6DCJTA00 19nm",
++ .id = {0x98, 0xDE, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
++ .length = 8,
++ .chipsize = _8G,
++ .probe = NULL,
++ .pagesize = _16K,
++ .erasesize = _4M,
++ .oobsize = 1280,
++ .options = 0,
++ .read_retry_type = NAND_RR_TOSHIBA_24nm,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* MLC 19nm */
++ .name = "TC58TEG5DCJTA00 19nm",
++ .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _16K,
++ .erasesize = _4M,
++ .oobsize = 1280,
++ .options = 0,
++ .read_retry_type = NAND_RR_TOSHIBA_24nm,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER | NAND_CHIP_TOSHIBA_TOGGLE_10,
++ },
++ { /* SLC 8bit/512 */
++ .name = "TC58NVG0S3HTA00",
++ .id = {0x98, 0xF1, 0x80, 0x15, 0x72, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _128M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ /*
++ * Datasheet: read one column of any page in each block. If the
++ * data of the column is 00 (Hex), define the block as a bad
++ * block.
++ */
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 8bit/512 */
++ .name = "TC58NVG1S3HTA00",
++ .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x16, 0x08, 0x00},
++ .length = 7,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 4bit/512 */
++ .name = "TC58NVG1S3ETA00",
++ .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x14, 0x03, 0x00},
++ .length = 7,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 64,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 4bit/512 */
++ .name = "TC58NVG3S0FTA00",
++ .id = {0x98, 0xD3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08},
++ .length = 8,
++ .chipsize = _1G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _256K,
++ .oobsize = 232,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 24bit/1k */
++ .name = "TC58NVG3S0HTA00",
++ .id = {0x98, 0xD3, 0x91, 0x26, 0x76, 0x16, 0x08, 0x00},
++ .length = 8,
++ .chipsize = _1G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _256K,
++ .oobsize = 256,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 24bit/1k */
++ .name = "TC58NVG2S0HTA00",
++ .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00},
++ .length = 8,
++ .chipsize = _512M,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _256K,
++ .oobsize = 256,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 4bit/512 */
++ .name = "TC58NVG2S0FTA00",
++ .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08},
++ .length = 8,
++ .chipsize = _512M,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _256K,
++ .oobsize = 224,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 4bit/512 */
++ .name = "TH58NVG2S3HTA00",
++ .id = {0x98, 0xDC, 0x91, 0x15, 0x76},
++ .length = 5,
++ .chipsize = _512M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .flags = 0,
++ },
++ { /* TLC 60bit/1k 19nm */
++ .name = "TC58NVG5T2JTA00 19nm TLC",
++ /* datasheet says 6 ids id data, but really has 8 ids. */
++ .id = {0x98, 0xD7, 0x98, 0x92, 0x72, 0x57, 0x08, 0x10},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _4M,
++ .oobsize = 1024,
++ .options = 0,
++ .read_retry_type = NAND_RR_TOSHIBA_24nm,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* TLC 60bit/1k 19nm */
++ .name = "TC58TEG5DCKTAx0 19nm MLC",
++ /* datasheet says 6 ids id data, but really has 8 ids. */
++ .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x50, 0x08, 0x04},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _16K,
++ .erasesize = _4M,
++ .oobsize = 1280,
++ .options = 0,
++ .read_retry_type = NAND_RR_TOSHIBA_19nm,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ {
++ .name = "Tx58TEGxDDKTAx0 19nm MLC",
++ .id = {0x98, 0xDE, 0x94, 0x93, 0x76, 0x50},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _16K,
++ .erasesize = _4M,
++ .oobsize = 1280,
++ .options = 0,
++ .read_retry_type = NAND_RR_TOSHIBA_19nm,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ /******************************* Samsung ******************************/
++ { /* MLC 8bit/512B */
++ .name = "K9LB(HC/PD/MD)G08U0(1)D",
++ .id = {0xEC, 0xD7, 0xD5, 0x29, 0x38, 0x41, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = samsung_probe_v02,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1KB */
++ .name = "K9GAG08U0E",
++ .id = {0xEC, 0xD5, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _2G,
++ .probe = samsung_probe_v02,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1KB */
++ .name = "K9LBG08U0E",
++ .id = {0xEC, 0xD7, 0xC5, 0x72, 0x54, 0x42, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = samsung_probe_v02,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1KB */
++ .name = "K9G8G08U0C",
++ .id = {0xEC, 0xD3, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _1G,
++ .probe = samsung_probe_v02,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1k */
++ .name = "K9GAG08U0F",
++ .id = {0xEC, 0xD5, 0x94, 0x76, 0x54, 0x43, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _2G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _1M,
++ .oobsize = 512,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC */
++ .name = "K9LBG08U0M",
++ .id = {0xEC, 0xD7, 0x55, 0xB6, 0x78, 0x00, 0x00, 0x00},
++ .length = 5,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _512K,
++ .oobsize = 128,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1k */
++ .name = "K9GBG08U0A 20nm",
++ .id = {0xEC, 0xD7, 0x94, 0x7A, 0x54, 0x43, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _1M,
++ .oobsize = 640,
++ .options = 0,
++ .read_retry_type = NAND_RR_SAMSUNG,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* MLC 40bit/1k */
++ .name = "K9GBG08U0B",
++ .id = {0xEC, 0xD7, 0x94, 0x7E, 0x64, 0x44, 0x00, 0x00},
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _1M,
++ .oobsize = 1024,
++ .options = 0,
++ .read_retry_type = NAND_RR_SAMSUNG,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
+
-+ /*********************************** Hynix ****************************/
-+ { /* MLC */
-+ .name = "H27UAG8T2A",
-+ .id = {0xAD, 0xD5, 0x94, 0x25, 0x44, 0x41, },
-+ .length = 6,
-+ .chipsize = _2G,
-+ .probe = hynix_probe_v02,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC */
-+ .name = "H27UAG8T2B",
-+ .id = {0xAD, 0xD5, 0x94, 0x9A, 0x74, 0x42, },
-+ .length = 6,
-+ .chipsize = _2G,
-+ .probe = hynix_probe_v02,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC */
-+ .name = "H27UBG8T2A",
-+ .id = {0xAD, 0xD7, 0x94, 0x9A, 0x74, 0x42, },
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = hynix_probe_v02,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 24bit/1K, 26nm TODO: Need read retry, chip is EOS */
-+ .name = "H27UBG8T2BTR 26nm",
-+ .id = {0xAD, 0xD7, 0x94, 0xDA, 0x74, 0xC3, },
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 640,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_HYNIX_BG_BDIE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* MLC 40bit/1k */
-+ .name = "H27UCG8T2A",
-+ .id = {0xAD, 0xDE, 0x94, 0xDA, 0x74, 0xC4, },
-+ .length = 6,
-+ .chipsize = _8G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 640,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_HYNIX_CG_ADIE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
-+ { /* MLC 40bit/1k */
-+ .name = "H27UBG8T2C",
-+ .id = {0xAD, 0xD7, 0x94, 0x91, 0x60, 0x44, },
-+ .length = 6,
-+ .chipsize = _4G,
-+ .probe = NULL,
-+ .pagesize = _8K,
-+ .erasesize = _2M,
-+ .oobsize = 640,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_HYNIX_BG_CDIE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = NAND_RANDOMIZER,
-+ },
++ /*********************************** Hynix ****************************/
++ { /* MLC */
++ .name = "H27UAG8T2A",
++ .id = {0xAD, 0xD5, 0x94, 0x25, 0x44, 0x41, },
++ .length = 6,
++ .chipsize = _2G,
++ .probe = hynix_probe_v02,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC */
++ .name = "H27UAG8T2B",
++ .id = {0xAD, 0xD5, 0x94, 0x9A, 0x74, 0x42, },
++ .length = 6,
++ .chipsize = _2G,
++ .probe = hynix_probe_v02,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC */
++ .name = "H27UBG8T2A",
++ .id = {0xAD, 0xD7, 0x94, 0x9A, 0x74, 0x42, },
++ .length = 6,
++ .chipsize = _4G,
++ .probe = hynix_probe_v02,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 24bit/1K, 26nm TODO: Need read retry, chip is EOS */
++ .name = "H27UBG8T2BTR 26nm",
++ .id = {0xAD, 0xD7, 0x94, 0xDA, 0x74, 0xC3, },
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 640,
++ .options = 0,
++ .read_retry_type = NAND_RR_HYNIX_BG_BDIE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* MLC 40bit/1k */
++ .name = "H27UCG8T2A",
++ .id = {0xAD, 0xDE, 0x94, 0xDA, 0x74, 0xC4, },
++ .length = 6,
++ .chipsize = _8G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 640,
++ .options = 0,
++ .read_retry_type = NAND_RR_HYNIX_CG_ADIE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
++ { /* MLC 40bit/1k */
++ .name = "H27UBG8T2C",
++ .id = {0xAD, 0xD7, 0x94, 0x91, 0x60, 0x44, },
++ .length = 6,
++ .chipsize = _4G,
++ .probe = NULL,
++ .pagesize = _8K,
++ .erasesize = _2M,
++ .oobsize = 640,
++ .options = 0,
++ .read_retry_type = NAND_RR_HYNIX_BG_CDIE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = NAND_RANDOMIZER,
++ },
+
-+ /********************** MISC ******************************************/
-+ { /* MLC 8bit/512 */
-+ .name = "P1UAGA30AT-GCA",
-+ .id = {0xC8, 0xD5, 0x14, 0x29, 0x34, 0x01, },
-+ .length = 6,
-+ .chipsize = _2G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _512K,
-+ .oobsize = 218,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* MLC 4bit/512 */
-+ /*
-+ * PowerFlash ASU8GA30IT-G30CA ID and MIRA PSU8GA30AT-GIA ID are
-+ * the same ID
-+ */
-+ .name = "PSU8GA30AT-GIA/ASU8GA30IT-G30CA",
-+ .id = {0xC8, 0xD3, 0x90, 0x19, 0x34, 0x01, },
-+ .length = 6,
-+ .chipsize = _1G,
-+ .probe = NULL,
-+ .pagesize = _4K,
-+ .erasesize = _256K,
-+ .oobsize = 218,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ { /* SLC 1bit/512 */
-+ .name = "PSU2GA30AT",
-+ .id = {0x7F, 0x7F, 0x7F, 0x7F, 0xC8, 0xDA, 0x00, 0x15, },
-+ .length = 8,
-+ .chipsize = _256M,
-+ .probe = NULL,
-+ .pagesize = _2K,
-+ .erasesize = _128K,
-+ .oobsize = 64,
-+ .options = 0,
-+ .read_retry_type = NAND_RR_NONE,
-+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
-+ .flags = 0,
-+ },
-+ {{0}, 0, 0, 0, 0, 0, 0, 0, 0},
++ /********************** MISC ******************************************/
++ { /* MLC 8bit/512 */
++ .name = "P1UAGA30AT-GCA",
++ .id = {0xC8, 0xD5, 0x14, 0x29, 0x34, 0x01, },
++ .length = 6,
++ .chipsize = _2G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _512K,
++ .oobsize = 218,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* MLC 4bit/512 */
++ /*
++ * PowerFlash ASU8GA30IT-G30CA ID and MIRA PSU8GA30AT-GIA ID are
++ * the same ID
++ */
++ .name = "PSU8GA30AT-GIA/ASU8GA30IT-G30CA",
++ .id = {0xC8, 0xD3, 0x90, 0x19, 0x34, 0x01, },
++ .length = 6,
++ .chipsize = _1G,
++ .probe = NULL,
++ .pagesize = _4K,
++ .erasesize = _256K,
++ .oobsize = 218,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ { /* SLC 1bit/512 */
++ .name = "PSU2GA30AT",
++ .id = {0x7F, 0x7F, 0x7F, 0x7F, 0xC8, 0xDA, 0x00, 0x15, },
++ .length = 8,
++ .chipsize = _256M,
++ .probe = NULL,
++ .pagesize = _2K,
++ .erasesize = _128K,
++ .oobsize = 64,
++ .options = 0,
++ .read_retry_type = NAND_RR_NONE,
++ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
++ .flags = 0,
++ },
++ {{0}, 0, 0, 0, 0, 0, 0, 0, 0},
+};
+
+struct nand_dev_t g_nand_dev;
+/*****************************************************************************/
+struct nand_flash_dev *hifmc_get_spl_flash_type(struct mtd_info *mtd,
-+ unsigned char *id)
++ unsigned char *id)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct nand_flash_special_dev *spl_dev = nand_flash_special_table;
-+ struct nand_flash_dev *type = &g_nand_dev.flash_dev;
-+ struct nand_dev_t *nand_dev = &g_nand_dev;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct nand_flash_special_dev *spl_dev = nand_flash_special_table;
++ struct nand_flash_dev *type = &g_nand_dev.flash_dev;
++ struct nand_dev_t *nand_dev = &g_nand_dev;
+
-+ FMC_PR(BT_DBG, "\t *-Start find special nand flash\n");
++ FMC_PR(BT_DBG, "\t *-Start find special nand flash\n");
+
-+ pr_info("Nand ID: %#X %#X %#X %#X %#X %#X %#X %#X\n", id[0], id[1],
-+ id[2], id[3], id[4], id[5], id[6], id[7]);
++ pr_info("Nand ID: %#X %#X %#X %#X %#X %#X %#X %#X\n", id[0], id[1],
++ id[2], id[3], id[4], id[5], id[6], id[7]);
+
-+ for (; spl_dev->length; spl_dev++) {
-+ if (memcmp(id, spl_dev->id, spl_dev->length)) {
-+ continue;
-+ }
++ for (; spl_dev->length; spl_dev++) {
++ if (memcmp(id, spl_dev->id, spl_dev->length)) {
++ continue;
++ }
+
-+ FMC_PR(BT_DBG, "\t |-Found special Nand flash: %s\n",
-+ spl_dev->name);
++ FMC_PR(BT_DBG, "\t |-Found special Nand flash: %s\n",
++ spl_dev->name);
+
-+ if (spl_dev->probe) {
-+ type = spl_dev->probe(id);
-+ } else {
-+ type->options = spl_dev->options;
-+ type->pagesize = spl_dev->pagesize;
-+ type->erasesize = spl_dev->erasesize;
-+ type->oobsize = spl_dev->oobsize;
-+ }
++ if (spl_dev->probe) {
++ type = spl_dev->probe(id);
++ } else {
++ type->options = spl_dev->options;
++ type->pagesize = spl_dev->pagesize;
++ type->erasesize = spl_dev->erasesize;
++ type->oobsize = spl_dev->oobsize;
++ }
+
-+ type->name = spl_dev->name;
-+ type->id_len = spl_dev->length;
-+ memcpy(type->id, id, type->id_len);
-+ type->chipsize = (unsigned int)(spl_dev->chipsize >> 20);
-+ FMC_PR(BT_DBG, "\t |-Save struct nand_flash_dev info\n");
++ type->name = spl_dev->name;
++ type->id_len = spl_dev->length;
++ memcpy(type->id, id, type->id_len);
++ type->chipsize = (unsigned int)(spl_dev->chipsize >> 20);
++ FMC_PR(BT_DBG, "\t |-Save struct nand_flash_dev info\n");
+
-+ memcpy(nand_dev->ids, id, MAX_NAND_ID_LEN);
-+ nand_dev->oobsize = type->oobsize;
-+ nand_dev->flags = spl_dev->flags;
-+ nand_dev->read_retry_type = spl_dev->read_retry_type;
-+ FMC_PR(BT_DBG, "\t |-Save struct nand_dev_t information\n");
++ memcpy(nand_dev->ids, id, MAX_NAND_ID_LEN);
++ nand_dev->oobsize = type->oobsize;
++ nand_dev->flags = spl_dev->flags;
++ nand_dev->read_retry_type = spl_dev->read_retry_type;
++ FMC_PR(BT_DBG, "\t |-Save struct nand_dev_t information\n");
+
-+ mtd->oobsize = spl_dev->oobsize;
-+ mtd->erasesize = spl_dev->erasesize;
-+ mtd->writesize = spl_dev->pagesize;
-+ chip->chipsize = spl_dev->chipsize;
-+ mtd->size = spl_dev->chipsize;
++ mtd->oobsize = spl_dev->oobsize;
++ mtd->erasesize = spl_dev->erasesize;
++ mtd->writesize = spl_dev->pagesize;
++ chip->chipsize = spl_dev->chipsize;
++ mtd->size = spl_dev->chipsize;
+
-+ return type;
-+ }
-+ nand_dev->read_retry_type = NAND_RR_NONE;
++ return type;
++ }
++ nand_dev->read_retry_type = NAND_RR_NONE;
+
-+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
-+ chip->read_byte(mtd);
-+ chip->read_byte(mtd);
++ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
++ chip->read_byte(mtd);
++ chip->read_byte(mtd);
+
-+ FMC_PR(BT_DBG, "\t *-Not found special nand flash\n");
++ FMC_PR(BT_DBG, "\t *-Not found special nand flash\n");
+
-+ return NULL;
++ return NULL;
+}
+
+/*****************************************************************************/
+void hifmc_spl_ids_register(void)
+{
-+ pr_info("Special NAND id table Version %s\n", DRV_VERSION);
-+ get_spi_nand_flash_type_hook = hifmc_get_spl_flash_type;
++ pr_info("Special NAND id table Version %s\n", DRV_VERSION);
++ get_spi_nand_flash_type_hook = hifmc_get_spl_flash_type;
+}
diff --git a/drivers/mtd/nand/hinfc610/Kconfig b/drivers/mtd/nand/hinfc610/Kconfig
new file mode 100644
@@ -292512,7 +360722,7 @@ index 0000000..9ef9acd
+obj-$(CONFIG_HINFC610_DBG_NAND_READ_RETRY) += hinfc610_dbg_read_retry.o
diff --git a/drivers/mtd/nand/hinfc610/hinfc610.c b/drivers/mtd/nand/hinfc610/hinfc610.c
new file mode 100644
-index 0000000..b71500b
+index 0000000..256184c
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610.c
@@ -0,0 +1,1248 @@
@@ -292547,750 +360757,750 @@ index 0000000..b71500b
+/*****************************************************************************/
+static unsigned int get_8bits(unsigned char byte)
+{
-+ int ix = 0;
-+ int num = 0;
++ int ix = 0;
++ int num = 0;
+
-+ if (byte == 0xFF) {
-+ return 8;
-+ }
-+ if (!byte) {
-+ return 0;
-+ }
++ if (byte == 0xFF) {
++ return 8;
++ }
++ if (!byte) {
++ return 0;
++ }
+
-+ while (ix++ < 8) {
-+ if ((byte & 1)) {
-+ num++;
-+ }
-+ byte = (byte >> 1);
-+ }
-+ return num;
++ while (ix++ < 8) {
++ if ((byte & 1)) {
++ num++;
++ }
++ byte = (byte >> 1);
++ }
++ return num;
+}
+/*****************************************************************************/
+
+static unsigned int get_16bits(unsigned short byte)
+{
-+ int ix = 0;
-+ int num = 0;
++ int ix = 0;
++ int num = 0;
+
-+ if (byte == 0xFFFF) {
-+ return 16;
-+ }
-+ if (!byte) {
-+ return 0;
-+ }
++ if (byte == 0xFFFF) {
++ return 16;
++ }
++ if (!byte) {
++ return 0;
++ }
+
-+ while (ix++ < 16) {
-+ if ((byte & 1)) {
-+ num++;
-+ }
-+ byte = (byte >> 1);
-+ }
-+ return num;
++ while (ix++ < 16) {
++ if ((byte & 1)) {
++ num++;
++ }
++ byte = (byte >> 1);
++ }
++ return num;
+}
+/*****************************************************************************/
+
+static void hinfc610_dma_transfer(struct hinfc_host *host, int todev)
+{
-+ unsigned long reg_val;
-+ unsigned int dma_addr = (unsigned int)host->dma_buffer;
++ unsigned long reg_val;
++ unsigned int dma_addr = (unsigned int)host->dma_buffer;
+
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA);
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA);
+
-+ dma_addr += HINFC610_DMA_ADDR_OFFSET;
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA1);
++ dma_addr += HINFC610_DMA_ADDR_OFFSET;
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA1);
+
-+ dma_addr += HINFC610_DMA_ADDR_OFFSET;
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA2);
++ dma_addr += HINFC610_DMA_ADDR_OFFSET;
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA2);
+
-+ dma_addr += HINFC610_DMA_ADDR_OFFSET;
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA3);
++ dma_addr += HINFC610_DMA_ADDR_OFFSET;
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA3);
+
-+ /* 32K PAGESIZE need below. */
-+ dma_addr += HINFC610_DMA_ADDR_OFFSET;
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA4);
++ /* 32K PAGESIZE need below. */
++ dma_addr += HINFC610_DMA_ADDR_OFFSET;
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA4);
+
-+ dma_addr += HINFC610_DMA_ADDR_OFFSET;
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA5);
++ dma_addr += HINFC610_DMA_ADDR_OFFSET;
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA5);
+
-+ dma_addr += HINFC610_DMA_ADDR_OFFSET;
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA6);
++ dma_addr += HINFC610_DMA_ADDR_OFFSET;
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA6);
+
-+ dma_addr += HINFC610_DMA_ADDR_OFFSET;
-+ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA7);
++ dma_addr += HINFC610_DMA_ADDR_OFFSET;
++ hinfc_write(host, dma_addr, HINFC610_DMA_ADDR_DATA7);
+
-+ hinfc_write(host, host->dma_oob, HINFC610_DMA_ADDR_OOB);
++ hinfc_write(host, host->dma_oob, HINFC610_DMA_ADDR_OOB);
+
-+ if (host->ecctype == NAND_ECC_NONE) {
-+ hinfc_write(host,
-+ ((host->oobsize & HINFC610_DMA_LEN_OOB_MASK)
-+ << HINFC610_DMA_LEN_OOB_SHIFT),
-+ HINFC610_DMA_LEN);
++ if (host->ecctype == NAND_ECC_NONE) {
++ hinfc_write(host,
++ ((host->oobsize & HINFC610_DMA_LEN_OOB_MASK)
++ << HINFC610_DMA_LEN_OOB_SHIFT),
++ HINFC610_DMA_LEN);
+
-+ hinfc_write(host,
-+ HINFC610_DMA_PARA_DATA_RW_EN
-+ | HINFC610_DMA_PARA_OOB_RW_EN,
-+ HINFC610_DMA_PARA);
-+ } else {
-+ hinfc_write(host,
-+ HINFC610_DMA_PARA_DATA_RW_EN
-+ | HINFC610_DMA_PARA_OOB_RW_EN
-+ | HINFC610_DMA_PARA_DATA_EDC_EN
-+ | HINFC610_DMA_PARA_OOB_EDC_EN,
-+ HINFC610_DMA_PARA);
-+ }
++ hinfc_write(host,
++ HINFC610_DMA_PARA_DATA_RW_EN
++ | HINFC610_DMA_PARA_OOB_RW_EN,
++ HINFC610_DMA_PARA);
++ } else {
++ hinfc_write(host,
++ HINFC610_DMA_PARA_DATA_RW_EN
++ | HINFC610_DMA_PARA_OOB_RW_EN
++ | HINFC610_DMA_PARA_DATA_EDC_EN
++ | HINFC610_DMA_PARA_OOB_EDC_EN,
++ HINFC610_DMA_PARA);
++ }
+
-+ reg_val = (HINFC610_DMA_CTRL_DMA_START
-+ | HINFC610_DMA_CTRL_BURST4_EN
-+ | HINFC610_DMA_CTRL_BURST8_EN
-+ | HINFC610_DMA_CTRL_BURST16_EN
-+ | ((host->addr_cycle == 4 ? 1 : 0)
-+ << HINFC610_DMA_CTRL_ADDR_NUM_SHIFT)
-+ | (((unsigned int)host->chipselect & HINFC610_DMA_CTRL_CS_MASK)
-+ << HINFC610_DMA_CTRL_CS_SHIFT));
++ reg_val = (HINFC610_DMA_CTRL_DMA_START
++ | HINFC610_DMA_CTRL_BURST4_EN
++ | HINFC610_DMA_CTRL_BURST8_EN
++ | HINFC610_DMA_CTRL_BURST16_EN
++ | ((host->addr_cycle == 4 ? 1 : 0)
++ << HINFC610_DMA_CTRL_ADDR_NUM_SHIFT)
++ | (((unsigned int)host->chipselect & HINFC610_DMA_CTRL_CS_MASK)
++ << HINFC610_DMA_CTRL_CS_SHIFT));
+
-+ if (todev) {
-+ reg_val |= HINFC610_DMA_CTRL_WE;
-+ }
++ if (todev) {
++ reg_val |= HINFC610_DMA_CTRL_WE;
++ }
+
-+ hinfc_write(host, reg_val, HINFC610_DMA_CTRL);
++ hinfc_write(host, reg_val, HINFC610_DMA_CTRL);
+
-+ do {
-+ unsigned int timeout = 0xF0000000;
++ do {
++ unsigned int timeout = 0xF0000000;
+
-+ while ((hinfc_read(host, HINFC610_DMA_CTRL))
-+ & HINFC610_DMA_CTRL_DMA_START && timeout) {
-+ _cond_resched();
-+ timeout--;
-+ }
-+ if (!timeout) {
-+ PR_BUG("Wait DMA finish timeout.\n");
-+ }
-+ } while (0);
++ while ((hinfc_read(host, HINFC610_DMA_CTRL))
++ & HINFC610_DMA_CTRL_DMA_START && timeout) {
++ _cond_resched();
++ timeout--;
++ }
++ if (!timeout) {
++ PR_BUG("Wait DMA finish timeout.\n");
++ }
++ } while (0);
+}
+/*****************************************************************************/
+
+static void hinfc610_sync_entry(struct hinfc_host *host)
+{
-+ struct nand_sync *sync = host->sync;
-+ struct nand_chip *chip = host->chip;
++ struct nand_sync *sync = host->sync;
++ struct nand_chip *chip = host->chip;
+
-+ if (!sync) {
-+ PR_BUG("this NAND not support sync feature.\n");
-+ return;
-+ }
++ if (!sync) {
++ PR_BUG("this NAND not support sync feature.\n");
++ return;
++ }
+
-+ if (HINFC610_IS_SYNC(host)) {
-+ PR_BUG("this NAND not support sync feature.\n");
-+ return;
-+ }
++ if (HINFC610_IS_SYNC(host)) {
++ PR_BUG("this NAND not support sync feature.\n");
++ return;
++ }
+
-+ if (sync->enable) {
-+ sync->enable(chip);
-+ }
++ if (sync->enable) {
++ sync->enable(chip);
++ }
+
-+ clk_prepare_enable(host->clk);
++ clk_prepare_enable(host->clk);
+
-+ switch (sync->type) {
-+ case NAND_TYPE_TOGGLE_10:
-+ host->NFC_CON |= HINFC610_CON_NF_MODE_TOGGLE;
-+ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_TOGGLE;
-+ break;
++ switch (sync->type) {
++ case NAND_TYPE_TOGGLE_10:
++ host->NFC_CON |= HINFC610_CON_NF_MODE_TOGGLE;
++ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_TOGGLE;
++ break;
+
-+ case NAND_TYPE_ONFI_23:
-+ host->NFC_CON |= HINFC610_CON_NF_MODE_ONFI_23;
-+ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_ONFI_23;
-+ break;
++ case NAND_TYPE_ONFI_23:
++ host->NFC_CON |= HINFC610_CON_NF_MODE_ONFI_23;
++ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_ONFI_23;
++ break;
+
-+ case NAND_TYPE_ONFI_30:
-+ host->NFC_CON |= HINFC610_CON_NF_MODE_ONFI_30;
-+ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_ONFI_30;
-+ break;
++ case NAND_TYPE_ONFI_30:
++ host->NFC_CON |= HINFC610_CON_NF_MODE_ONFI_30;
++ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_ONFI_30;
++ break;
+
-+ default:
-+ PR_BUG("Unsupport sync type 0x%08X.\n", sync->type);
-+ break;
-+ }
++ default:
++ PR_BUG("Unsupport sync type 0x%08X.\n", sync->type);
++ break;
++ }
+}
+/*****************************************************************************/
+
+static void hinfc610_sync_exit(struct hinfc_host *host)
+{
-+ struct nand_sync *sync = host->sync;
-+ struct nand_chip *chip = host->chip;
++ struct nand_sync *sync = host->sync;
++ struct nand_chip *chip = host->chip;
+
-+ if (!HINFC610_IS_SYNC(host)) {
-+ PR_BUG("Current already exit from sync feature.\n");
-+ return;
-+ }
++ if (!HINFC610_IS_SYNC(host)) {
++ PR_BUG("Current already exit from sync feature.\n");
++ return;
++ }
+
-+ if (sync->disable) {
-+ sync->disable(chip);
-+ }
++ if (sync->disable) {
++ sync->disable(chip);
++ }
+
-+ host->NFC_CON &= ~HINFC610_CON_NF_MODE_MASK;
-+ host->NFC_CON_ECC_NONE &= ~HINFC610_CON_NF_MODE_MASK;
++ host->NFC_CON &= ~HINFC610_CON_NF_MODE_MASK;
++ host->NFC_CON_ECC_NONE &= ~HINFC610_CON_NF_MODE_MASK;
+
-+ clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk);
+}
+/*****************************************************************************/
+
+void hinfc610_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
-+ int is_cache_invalid = 1;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hinfc_host *host = chip->priv;
++ int is_cache_invalid = 1;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hinfc_host *host = chip->priv;
+
-+ if (ctrl & NAND_ALE) {
-+ unsigned int addr_value = 0;
-+ unsigned int addr_offset = 0;
++ if (ctrl & NAND_ALE) {
++ unsigned int addr_value = 0;
++ unsigned int addr_offset = 0;
+
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ host->addr_cycle = 0x0;
-+ host->addr_value[0] = 0x0;
-+ host->addr_value[1] = 0x0;
-+ }
-+ addr_offset = host->addr_cycle << 3;
++ if (ctrl & NAND_CTRL_CHANGE) {
++ host->addr_cycle = 0x0;
++ host->addr_value[0] = 0x0;
++ host->addr_value[1] = 0x0;
++ }
++ addr_offset = host->addr_cycle << 3;
+
-+ if (host->addr_cycle >= HINFC610_ADDR_CYCLE_MASK) {
-+ addr_offset =
-+ (host->addr_cycle - HINFC610_ADDR_CYCLE_MASK) << 3;
-+ addr_value = 1;
-+ }
++ if (host->addr_cycle >= HINFC610_ADDR_CYCLE_MASK) {
++ addr_offset =
++ (host->addr_cycle - HINFC610_ADDR_CYCLE_MASK) << 3;
++ addr_value = 1;
++ }
+
-+ host->addr_value[addr_value] |=
-+ ((dat & 0xff) << addr_offset);
++ host->addr_value[addr_value] |=
++ ((dat & 0xff) << addr_offset);
+
-+ host->addr_cycle++;
-+ }
++ host->addr_cycle++;
++ }
+
-+ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
-+ host->command = dat & 0xff;
-+ switch (host->command) {
-+ case NAND_CMD_PAGEPROG:
-+ host->send_cmd_pageprog(host);
-+ hinfc610_dbg_write(host);
-+ break;
++ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
++ host->command = dat & 0xff;
++ switch (host->command) {
++ case NAND_CMD_PAGEPROG:
++ host->send_cmd_pageprog(host);
++ hinfc610_dbg_write(host);
++ break;
+
-+ case NAND_CMD_READSTART:
-+ is_cache_invalid = 0;
-+ host->send_cmd_readstart(host);
-+ hinfc610_dbg_read(host);
++ case NAND_CMD_READSTART:
++ is_cache_invalid = 0;
++ host->send_cmd_readstart(host);
++ hinfc610_dbg_read(host);
+
-+ break;
++ break;
+
-+ case NAND_CMD_ERASE2:
-+ host->send_cmd_erase(host);
-+ hinfc610_dbg_erase(host);
++ case NAND_CMD_ERASE2:
++ host->send_cmd_erase(host);
++ hinfc610_dbg_erase(host);
+
-+ break;
++ break;
+
-+ case NAND_CMD_READID:
-+ memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
-+ host->send_cmd_readid(host);
-+ break;
++ case NAND_CMD_READID:
++ memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
++ host->send_cmd_readid(host);
++ break;
+
-+ case NAND_CMD_STATUS:
-+ host->send_cmd_status(host);
-+ break;
++ case NAND_CMD_STATUS:
++ host->send_cmd_status(host);
++ break;
+
-+ case NAND_CMD_SEQIN:
-+ case NAND_CMD_ERASE1:
-+ case NAND_CMD_READ0:
-+ break;
-+ case NAND_CMD_RESET:
-+ host->send_cmd_reset(host, host->chipselect);
-+ break;
++ case NAND_CMD_SEQIN:
++ case NAND_CMD_ERASE1:
++ case NAND_CMD_READ0:
++ break;
++ case NAND_CMD_RESET:
++ host->send_cmd_reset(host, host->chipselect);
++ break;
+
-+ default:
-+ break;
-+ }
-+ }
++ default:
++ break;
++ }
++ }
+
-+ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
-+ if (host->command == NAND_CMD_SEQIN ||
-+ host->command == NAND_CMD_READ0 ||
-+ host->command == NAND_CMD_READID) {
-+ host->offset = 0x0;
-+ host->column = (host->addr_value[0] & 0xffff);
-+ }
-+ }
++ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
++ if (host->command == NAND_CMD_SEQIN ||
++ host->command == NAND_CMD_READ0 ||
++ host->command == NAND_CMD_READID) {
++ host->offset = 0x0;
++ host->column = (host->addr_value[0] & 0xffff);
++ }
++ }
+
-+ if (is_cache_invalid) {
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
-+ }
++ if (is_cache_invalid) {
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
++ }
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_pageprog(struct hinfc_host *host)
+{
-+ if (*host->bbm != 0xFF && *host->bbm != 0x00)
-+ pr_warn("Attempt to write an invalid bbm. page: 0x%08x, mark: 0x%02x, current process(pid): %s(%d).\n",
-+ GET_PAGE_INDEX(host), *host->bbm,
-+ current->comm, current->pid);
++ if (*host->bbm != 0xFF && *host->bbm != 0x00)
++ pr_warn("Attempt to write an invalid bbm. page: 0x%08x, mark: 0x%02x, current process(pid): %s(%d).\n",
++ GET_PAGE_INDEX(host), *host->bbm,
++ current->comm, current->pid);
+
-+ if (IS_NAND_SYNC_ASYNC(host)) {
-+ hinfc610_sync_entry(host);
-+ }
++ if (IS_NAND_SYNC_ASYNC(host)) {
++ hinfc610_sync_entry(host);
++ }
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ hinfc_write(host, host->addr_value[0] & 0xffff0000, HINFC610_ADDRL);
-+ hinfc_write(host, host->addr_value[1], HINFC610_ADDRH);
-+ hinfc_write(host,
-+ ((NAND_CMD_STATUS << 16) | (NAND_CMD_PAGEPROG << 8) |
-+ NAND_CMD_SEQIN),
-+ HINFC610_CMD);
++ hinfc_write(host, host->addr_value[0] & 0xffff0000, HINFC610_ADDRL);
++ hinfc_write(host, host->addr_value[1], HINFC610_ADDRH);
++ hinfc_write(host,
++ ((NAND_CMD_STATUS << 16) | (NAND_CMD_PAGEPROG << 8) |
++ NAND_CMD_SEQIN),
++ HINFC610_CMD);
+
-+ *host->epm = 0x0000;
++ *host->epm = 0x0000;
+
-+ hinfc610_dma_transfer(host, 1);
++ hinfc610_dma_transfer(host, 1);
+
-+ if (IS_NAND_SYNC_ASYNC(host)) {
-+ hinfc610_sync_exit(host);
-+ }
++ if (IS_NAND_SYNC_ASYNC(host)) {
++ hinfc610_sync_exit(host);
++ }
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_get_data_status(struct hinfc_host *host)
+{
-+ unsigned int page_status = 0;
++ unsigned int page_status = 0;
+
-+ if (IS_PS_UN_ECC(host)) {
-+ page_status = HINFC610_PS_UC_ECC;
-+ }
++ if (IS_PS_UN_ECC(host)) {
++ page_status = HINFC610_PS_UC_ECC;
++ }
+
-+ /* this is block start address */
-+ if (!((host->addr_value[0] >> 16) & host->block_page_mask)) {
++ /* this is block start address */
++ if (!((host->addr_value[0] >> 16) & host->block_page_mask)) {
+
-+ /* it is a bad block */
-+ if (*host->bbm == 0x00) {
-+ page_status |= HINFC610_PS_BAD_BLOCK;
-+ goto out;
-+ }
++ /* it is a bad block */
++ if (*host->bbm == 0x00) {
++ page_status |= HINFC610_PS_BAD_BLOCK;
++ goto out;
++ }
+
-+ if (*host->bbm != 0xFF) {
-+ page_status |= HINFC610_PS_BBM_ERROR;
++ if (*host->bbm != 0xFF) {
++ page_status |= HINFC610_PS_BBM_ERROR;
+
-+ /*
-+ * if there are more than 2 bits flipping, it is
-+ * maybe a bad block
-+ */
-+ if (!IS_PS_UN_ECC(host) || get_8bits(*host->bbm) < 6) {
-+ page_status |= HINFC610_PS_BAD_BLOCK;
-+ goto out;
-+ }
-+ }
-+ }
++ /*
++ * if there are more than 2 bits flipping, it is
++ * maybe a bad block
++ */
++ if (!IS_PS_UN_ECC(host) || get_8bits(*host->bbm) < 6) {
++ page_status |= HINFC610_PS_BAD_BLOCK;
++ goto out;
++ }
++ }
++ }
+
-+ if (*host->epm == 0x0000) {
-+ goto out;
-+ }
++ if (*host->epm == 0x0000) {
++ goto out;
++ }
+
-+ if (*host->epm == 0xFFFF) {
-+ page_status |= HINFC610_PS_EMPTY_PAGE;
-+ goto out;
-+ }
++ if (*host->epm == 0xFFFF) {
++ page_status |= HINFC610_PS_EMPTY_PAGE;
++ goto out;
++ }
+
-+ page_status |= HINFC610_PS_EPM_ERROR;
++ page_status |= HINFC610_PS_EPM_ERROR;
+
-+ if (IS_PS_UN_ECC(host) && get_16bits(*host->epm) > 12) {
-+ page_status |= HINFC610_PS_EMPTY_PAGE;
-+ goto out;
-+ }
++ if (IS_PS_UN_ECC(host) && get_16bits(*host->epm) > 12) {
++ page_status |= HINFC610_PS_EMPTY_PAGE;
++ goto out;
++ }
+
+out:
-+ return page_status;
++ return page_status;
+}
+/*****************************************************************************/
+
+static int hinfc610_do_read_retry(struct hinfc_host *host)
+{
-+ int ix;
++ int ix;
+
-+ for (ix = 1; IS_PS_UN_ECC(host) && ix < host->read_retry->count; ix++) {
++ for (ix = 1; IS_PS_UN_ECC(host) && ix < host->read_retry->count; ix++) {
+
-+ hinfc_write(host, HINFC610_INTCLR_UE | HINFC610_INTCLR_CE,
-+ HINFC610_INTCLR);
++ hinfc_write(host, HINFC610_INTCLR_UE | HINFC610_INTCLR_CE,
++ HINFC610_INTCLR);
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
-+ host->read_retry->set_rr_param(host, ix);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->read_retry->set_rr_param(host, ix);
+
-+ /* enable ecc and randomizer */
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ /* enable ecc and randomizer */
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ hinfc_write(host, HINFC610_INTCLR_UE | HINFC610_INTCLR_CE,
-+ HINFC610_INTCLR);
-+ hinfc_write(host, host->NFC_CON, HINFC610_CON);
-+ hinfc_write(host, host->addr_value[0] & 0xffff0000,
-+ HINFC610_ADDRL);
-+ hinfc_write(host, host->addr_value[1], HINFC610_ADDRH);
-+ hinfc_write(host,
-+ HINFC_CMD_SEQ(NAND_CMD_READ0, NAND_CMD_READSTART),
-+ HINFC610_CMD);
++ hinfc_write(host, HINFC610_INTCLR_UE | HINFC610_INTCLR_CE,
++ HINFC610_INTCLR);
++ hinfc_write(host, host->NFC_CON, HINFC610_CON);
++ hinfc_write(host, host->addr_value[0] & 0xffff0000,
++ HINFC610_ADDRL);
++ hinfc_write(host, host->addr_value[1], HINFC610_ADDRH);
++ hinfc_write(host,
++ HINFC_CMD_SEQ(NAND_CMD_READ0, NAND_CMD_READSTART),
++ HINFC610_CMD);
+
-+ hinfc610_dma_transfer(host, 0);
++ hinfc610_dma_transfer(host, 0);
+
-+ if (hinfc_read(host, HINFC610_INTS) & HINFC610_INTS_UE) {
-+ host->page_status |= HINFC610_PS_UC_ECC;
-+ } else {
-+ host->page_status &= ~HINFC610_PS_UC_ECC;
-+ }
-+ }
++ if (hinfc_read(host, HINFC610_INTS) & HINFC610_INTS_UE) {
++ host->page_status |= HINFC610_PS_UC_ECC;
++ } else {
++ host->page_status &= ~HINFC610_PS_UC_ECC;
++ }
++ }
+
-+ host->page_status = hinfc610_get_data_status(host);
++ host->page_status = hinfc610_get_data_status(host);
+
-+ hinfc610_dbg_read_retry(host, ix);
++ hinfc610_dbg_read_retry(host, ix);
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
-+ host->read_retry->reset_rr_param(host);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->read_retry->reset_rr_param(host);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_readstart(struct hinfc_host *host)
+{
-+ if ((host->addr_value[0] == host->cache_addr_value[0]) &&
-+ (host->addr_value[1] == host->cache_addr_value[1])) {
-+ return 0;
-+ }
++ if ((host->addr_value[0] == host->cache_addr_value[0]) &&
++ (host->addr_value[1] == host->cache_addr_value[1])) {
++ return 0;
++ }
+
-+ if (IS_NAND_SYNC_ASYNC(host)) {
-+ hinfc610_sync_entry(host);
-+ }
++ if (IS_NAND_SYNC_ASYNC(host)) {
++ hinfc610_sync_entry(host);
++ }
+
-+ host->page_status = 0;
++ host->page_status = 0;
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ hinfc_write(host, HINFC610_INTCLR_UE | HINFC610_INTCLR_CE,
-+ HINFC610_INTCLR);
-+ hinfc_write(host, host->NFC_CON, HINFC610_CON);
-+ hinfc_write(host, host->addr_value[0] & 0xffff0000, HINFC610_ADDRL);
-+ hinfc_write(host, host->addr_value[1], HINFC610_ADDRH);
-+ hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
-+ HINFC610_CMD);
++ hinfc_write(host, HINFC610_INTCLR_UE | HINFC610_INTCLR_CE,
++ HINFC610_INTCLR);
++ hinfc_write(host, host->NFC_CON, HINFC610_CON);
++ hinfc_write(host, host->addr_value[0] & 0xffff0000, HINFC610_ADDRL);
++ hinfc_write(host, host->addr_value[1], HINFC610_ADDRH);
++ hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
++ HINFC610_CMD);
+
-+ hinfc610_dma_transfer(host, 0);
++ hinfc610_dma_transfer(host, 0);
+
-+ if (hinfc_read(host, HINFC610_INTS) & HINFC610_INTS_UE) {
-+ host->page_status |= HINFC610_PS_UC_ECC;
-+ }
++ if (hinfc_read(host, HINFC610_INTS) & HINFC610_INTS_UE) {
++ host->page_status |= HINFC610_PS_UC_ECC;
++ }
+
-+ if (host->read_retry || IS_NAND_RANDOM(host)) {
-+ host->page_status |= hinfc610_get_data_status(host);
++ if (host->read_retry || IS_NAND_RANDOM(host)) {
++ host->page_status |= hinfc610_get_data_status(host);
+
-+ if (IS_PS_EMPTY_PAGE(host)) {
-+ /*
-+ * oob area used by yaffs2 only 32 bytes,
-+ * so we only fill 32 bytes.
-+ */
-+ if (IS_NAND_RANDOM(host))
-+ memset(host->buffer, 0xFF,
-+ host->pagesize + host->oobsize);
++ if (IS_PS_EMPTY_PAGE(host)) {
++ /*
++ * oob area used by yaffs2 only 32 bytes,
++ * so we only fill 32 bytes.
++ */
++ if (IS_NAND_RANDOM(host))
++ memset(host->buffer, 0xFF,
++ host->pagesize + host->oobsize);
+
-+ } else if (!IS_PS_BAD_BLOCK(host)) {
-+ /* if NAND chip support read retry */
-+ if (IS_PS_UN_ECC(host) && host->read_retry) {
-+ hinfc610_do_read_retry(host);
-+ }
++ } else if (!IS_PS_BAD_BLOCK(host)) {
++ /* if NAND chip support read retry */
++ if (IS_PS_UN_ECC(host) && host->read_retry) {
++ hinfc610_do_read_retry(host);
++ }
+
-+ } /* 'else' NAND have a bad block, do nothing. */
-+ }
++ } /* 'else' NAND have a bad block, do nothing. */
++ }
+
-+ if (IS_NAND_SYNC_ASYNC(host)) {
-+ hinfc610_sync_exit(host);
-+ }
++ if (IS_NAND_SYNC_ASYNC(host)) {
++ hinfc610_sync_exit(host);
++ }
+
-+ host->cache_addr_value[0] = host->addr_value[0];
-+ host->cache_addr_value[1] = host->addr_value[1];
++ host->cache_addr_value[0] = host->addr_value[0];
++ host->cache_addr_value[1] = host->addr_value[1];
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_erase(struct hinfc_host *host)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ /* Don't case the read retry config */
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ /* Don't case the read retry config */
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, host->addr_value[0], HINFC610_ADDRL);
-+ hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
-+ HINFC610_CMD);
++ hinfc_write(host, host->addr_value[0], HINFC610_ADDRL);
++ hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
++ HINFC610_CMD);
+
-+ regval = HINFC610_OP_WAIT_READY_EN
-+ | HINFC610_OP_CMD2_EN
-+ | HINFC610_OP_CMD1_EN
-+ | HINFC610_OP_ADDR_EN
-+ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
-+ << HINFC610_OP_NF_CS_SHIFT)
-+ | ((host->addr_cycle & HINFC610_OP_ADDR_CYCLE_MASK)
-+ << HINFC610_OP_ADDR_CYCLE_SHIFT);
++ regval = HINFC610_OP_WAIT_READY_EN
++ | HINFC610_OP_CMD2_EN
++ | HINFC610_OP_CMD1_EN
++ | HINFC610_OP_ADDR_EN
++ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
++ << HINFC610_OP_NF_CS_SHIFT)
++ | ((host->addr_cycle & HINFC610_OP_ADDR_CYCLE_MASK)
++ << HINFC610_OP_ADDR_CYCLE_SHIFT);
+
-+ hinfc_write(host, regval, HINFC610_OP);
++ hinfc_write(host, regval, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_sync_readid(struct hinfc_host *host)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, HINFC610_NANDINFO_LEN, HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
-+ hinfc_write(host, 0, HINFC610_ADDRL);
++ hinfc_write(host, HINFC610_NANDINFO_LEN, HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
++ hinfc_write(host, 0, HINFC610_ADDRL);
+
-+ /* no need to config HINFC610_OP_WAIT_READY_EN, here not config. */
-+ regval = HINFC610_OP_CMD1_EN
-+ | HINFC610_OP_ADDR_EN
-+ | HINFC610_OP_READ_DATA_EN
-+ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
-+ << HINFC610_OP_NF_CS_SHIFT)
-+ | (1 << HINFC610_OP_ADDR_CYCLE_SHIFT)
-+ | HINFC610_OP_READID_EN
-+ | HINFC610_OP_RW_REG_EN;
++ /* no need to config HINFC610_OP_WAIT_READY_EN, here not config. */
++ regval = HINFC610_OP_CMD1_EN
++ | HINFC610_OP_ADDR_EN
++ | HINFC610_OP_READ_DATA_EN
++ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
++ << HINFC610_OP_NF_CS_SHIFT)
++ | (1 << HINFC610_OP_ADDR_CYCLE_SHIFT)
++ | HINFC610_OP_READID_EN
++ | HINFC610_OP_RW_REG_EN;
+
-+ hinfc_write(host, regval, HINFC610_OP);
++ hinfc_write(host, regval, HINFC610_OP);
+
-+ host->addr_cycle = 0x0;
++ host->addr_cycle = 0x0;
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_async_readid(struct hinfc_host *host)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, HINFC610_NANDINFO_LEN, HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
-+ hinfc_write(host, 0, HINFC610_ADDRL);
++ hinfc_write(host, HINFC610_NANDINFO_LEN, HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
++ hinfc_write(host, 0, HINFC610_ADDRL);
+
-+ /* no need to config HINFC610_OP_WAIT_READY_EN, here not config. */
-+ regval = HINFC610_OP_CMD1_EN
-+ | HINFC610_OP_ADDR_EN
-+ | HINFC610_OP_READ_DATA_EN
-+ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
-+ << HINFC610_OP_NF_CS_SHIFT)
-+ | (1 << HINFC610_OP_ADDR_CYCLE_SHIFT);
++ /* no need to config HINFC610_OP_WAIT_READY_EN, here not config. */
++ regval = HINFC610_OP_CMD1_EN
++ | HINFC610_OP_ADDR_EN
++ | HINFC610_OP_READ_DATA_EN
++ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
++ << HINFC610_OP_NF_CS_SHIFT)
++ | (1 << HINFC610_OP_ADDR_CYCLE_SHIFT);
+
-+ hinfc_write(host, regval, HINFC610_OP);
++ hinfc_write(host, regval, HINFC610_OP);
+
-+ host->addr_cycle = 0x0;
++ host->addr_cycle = 0x0;
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_readid(struct hinfc_host *host)
+{
-+ if (HINFC610_IS_SYNC(host)) {
-+ return hinfc610_send_cmd_sync_readid(host);
-+ } else {
-+ return hinfc610_send_cmd_async_readid(host);
-+ }
++ if (HINFC610_IS_SYNC(host)) {
++ return hinfc610_send_cmd_sync_readid(host);
++ } else {
++ return hinfc610_send_cmd_async_readid(host);
++ }
+}
+/*****************************************************************************/
+
+static int hinfc610_enable_ecc_randomizer(struct hinfc_host *host, int ecc_en,
-+ int randomizer_en)
++ int randomizer_en)
+{
-+ unsigned int nfc_con;
++ unsigned int nfc_con;
+
-+ if (IS_NAND_RANDOM(host)) {
-+ if (randomizer_en) {
-+ host->NFC_CON |= HINFC610_CON_RANDOMIZER_EN;
-+ host->NFC_CON_ECC_NONE |= HINFC610_CON_RANDOMIZER_EN;
-+ } else {
-+ host->NFC_CON &= ~HINFC610_CON_RANDOMIZER_EN;
-+ host->NFC_CON_ECC_NONE &= ~HINFC610_CON_RANDOMIZER_EN;
-+ }
-+ }
++ if (IS_NAND_RANDOM(host)) {
++ if (randomizer_en) {
++ host->NFC_CON |= HINFC610_CON_RANDOMIZER_EN;
++ host->NFC_CON_ECC_NONE |= HINFC610_CON_RANDOMIZER_EN;
++ } else {
++ host->NFC_CON &= ~HINFC610_CON_RANDOMIZER_EN;
++ host->NFC_CON_ECC_NONE &= ~HINFC610_CON_RANDOMIZER_EN;
++ }
++ }
+
-+ nfc_con = (ecc_en ? host->NFC_CON : host->NFC_CON_ECC_NONE);
++ nfc_con = (ecc_en ? host->NFC_CON : host->NFC_CON_ECC_NONE);
+
-+ hinfc_write(host, nfc_con, HINFC610_CON);
++ hinfc_write(host, nfc_con, HINFC610_CON);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_status(struct hinfc_host *host)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, HINFC610_NANDINFO_LEN, HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_STATUS, HINFC610_CMD);
++ hinfc_write(host, HINFC610_NANDINFO_LEN, HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_STATUS, HINFC610_CMD);
+
-+ /* no need config HINFC610_OP_WAIT_READY_EN, here not config */
-+ regval = HINFC610_OP_CMD1_EN
-+ | HINFC610_OP_READ_DATA_EN
-+ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
-+ << HINFC610_OP_NF_CS_SHIFT);
++ /* no need config HINFC610_OP_WAIT_READY_EN, here not config */
++ regval = HINFC610_OP_CMD1_EN
++ | HINFC610_OP_READ_DATA_EN
++ | (((unsigned int)host->chipselect & HINFC610_OP_NF_CS_MASK)
++ << HINFC610_OP_NF_CS_SHIFT);
+
-+ hinfc_write(host, regval, HINFC610_OP);
++ hinfc_write(host, regval, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+static int hinfc610_send_cmd_async_reset(struct hinfc_host *host,
-+ int chipselect)
++ int chipselect)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ hinfc_write(host, NAND_CMD_RESET, HINFC610_CMD);
++ hinfc_write(host, NAND_CMD_RESET, HINFC610_CMD);
+
-+ /* need to config HINFC610_OP_WAIT_READY_EN */
-+ regval = HINFC610_OP_CMD1_EN
-+ | ((((unsigned int)chipselect & HINFC610_OP_NF_CS_MASK)
-+ << HINFC610_OP_NF_CS_SHIFT)
-+ | HINFC610_OP_WAIT_READY_EN);
++ /* need to config HINFC610_OP_WAIT_READY_EN */
++ regval = HINFC610_OP_CMD1_EN
++ | ((((unsigned int)chipselect & HINFC610_OP_NF_CS_MASK)
++ << HINFC610_OP_NF_CS_SHIFT)
++ | HINFC610_OP_WAIT_READY_EN);
+
-+ hinfc_write(host, regval, HINFC610_OP);
++ hinfc_write(host, regval, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_sync_reset(struct hinfc_host *host,
-+ int chipselect)
++ int chipselect)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ /*
-+ * Regarding the ONFI chip sync mode,
-+ * NAND_CMD_SYNC_RESET make chip remain sync mode.
-+ * But NAND_CMD_RESET will change chip mode to async mode.
-+ */
-+ hinfc_write(host, NAND_CMD_SYNC_RESET, HINFC610_CMD);
++ /*
++ * Regarding the ONFI chip sync mode,
++ * NAND_CMD_SYNC_RESET make chip remain sync mode.
++ * But NAND_CMD_RESET will change chip mode to async mode.
++ */
++ hinfc_write(host, NAND_CMD_SYNC_RESET, HINFC610_CMD);
+
-+ /* need to config HINFC610_OP_WAIT_READY_EN */
-+ regval = HINFC610_OP_CMD1_EN
-+ | (((unsigned int)chipselect & HINFC610_OP_NF_CS_MASK)
-+ << HINFC610_OP_NF_CS_SHIFT)
-+ | HINFC610_OP_WAIT_READY_EN;
++ /* need to config HINFC610_OP_WAIT_READY_EN */
++ regval = HINFC610_OP_CMD1_EN
++ | (((unsigned int)chipselect & HINFC610_OP_NF_CS_MASK)
++ << HINFC610_OP_NF_CS_SHIFT)
++ | HINFC610_OP_WAIT_READY_EN;
+
-+ hinfc_write(host, regval, HINFC610_OP);
++ hinfc_write(host, regval, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_send_cmd_reset(struct hinfc_host *host, int chipselect)
+{
-+ if (HINFC610_IS_SYNC(host)) {
-+ return hinfc610_send_cmd_sync_reset(host, chipselect);
-+ } else {
-+ return hinfc610_send_cmd_async_reset(host, chipselect);
-+ }
++ if (HINFC610_IS_SYNC(host)) {
++ return hinfc610_send_cmd_sync_reset(host, chipselect);
++ } else {
++ return hinfc610_send_cmd_async_reset(host, chipselect);
++ }
+}
+/*****************************************************************************/
+
+int hinfc610_dev_ready(struct mtd_info *mtd)
+{
-+ return 0x1;
++ return 0x1;
+}
+/*****************************************************************************/
+
+void hinfc610_select_chip(struct mtd_info *mtd, int chipselect)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hinfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hinfc_host *host = chip->priv;
+
-+ if (chipselect < 0) {
-+ return;
-+ }
++ if (chipselect < 0) {
++ return;
++ }
+
-+ if (chipselect > CONFIG_HINFC610_MAX_CHIP) {
-+ PR_BUG("invalid chipselect: %d\n", chipselect);
-+ }
++ if (chipselect > CONFIG_HINFC610_MAX_CHIP) {
++ PR_BUG("invalid chipselect: %d\n", chipselect);
++ }
+
-+ host->chipselect = chipselect;
++ host->chipselect = chipselect;
+}
+/*****************************************************************************/
+
+uint8_t hinfc610_read_byte(struct mtd_info *mtd)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hinfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hinfc_host *host = chip->priv;
+
-+ if (host->command == NAND_CMD_STATUS) {
-+ return readb(chip->IO_ADDR_R);
-+ }
++ if (host->command == NAND_CMD_STATUS) {
++ return readb(chip->IO_ADDR_R);
++ }
+
-+ host->offset++;
++ host->offset++;
+
-+ if (host->command == NAND_CMD_READID) {
-+ return readb(chip->IO_ADDR_R + host->offset - 1);
-+ }
++ if (host->command == NAND_CMD_READID) {
++ return readb(chip->IO_ADDR_R + host->offset - 1);
++ }
+
-+ return readb(host->buffer + host->column + host->offset - 1);
++ return readb(host->buffer + host->column + host->offset - 1);
+}
+/*****************************************************************************/
+
+u16 hinfc610_read_word(struct mtd_info *mtd)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hinfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hinfc_host *host = chip->priv;
+
-+ host->offset += 2;
-+ return readw(host->buffer + host->column + host->offset - 2);
++ host->offset += 2;
++ return readw(host->buffer + host->column + host->offset - 2);
+}
+/*****************************************************************************/
+
+void hinfc610_write_buf(struct mtd_info *mtd, const uint8_t *buf,
-+ int len)
++ int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hinfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hinfc_host *host = chip->priv;
+
-+ memcpy(host->buffer + host->column + host->offset, buf, len);
-+ host->offset += len;
++ memcpy(host->buffer + host->column + host->offset, buf, len);
++ host->offset += len;
+}
+#ifdef CONFIG_HISI_NAND_ECC_STATUS_REPORT
+/*****************************************************************************/
+static void hinfc610_ecc_err_num_count(struct mtd_info *mtd,
-+ uint8_t ecc_st, int reg)
++ uint8_t ecc_st, int reg)
+{
-+ u_char err_num;
++ u_char err_num;
+
-+ if (ecc_st > 4) {
-+ ecc_st = 4;
-+ }
++ if (ecc_st > 4) {
++ ecc_st = 4;
++ }
+
-+ while (ecc_st) {
-+ err_num = GET_ECC_ERR_NUM(--ecc_st, reg);
-+ if (err_num == 0xff) {
-+ mtd->ecc_stats.failed++;
-+ } else {
-+ mtd->ecc_stats.corrected += err_num;
-+ }
-+ }
++ while (ecc_st) {
++ err_num = GET_ECC_ERR_NUM(--ecc_st, reg);
++ if (err_num == 0xff) {
++ mtd->ecc_stats.failed++;
++ } else {
++ mtd->ecc_stats.corrected += err_num;
++ }
++ }
+}
+#endif
+
@@ -293298,34 +361508,34 @@ index 0000000..b71500b
+
+void hinfc610_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hinfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hinfc_host *host = chip->priv;
+#ifdef CONFIG_HISI_NAND_ECC_STATUS_REPORT
-+ int reg;
-+ uint8_t ecc_step = host->pagesize >> 10;
++ int reg;
++ uint8_t ecc_step = host->pagesize >> 10;
+#endif
+
-+ memcpy(buf, host->buffer + host->column + host->offset, len);
-+ host->offset += len;
++ memcpy(buf, host->buffer + host->column + host->offset, len);
++ host->offset += len;
+
+#ifdef CONFIG_HISI_NAND_ECC_STATUS_REPORT
-+ /* 2K or 4K or 8K(1) or 16K(1-1) pagesize */
-+ reg = hinfc_read(host, HINFC_ECC_ERR_NUM0_BUF0);
-+ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
++ /* 2K or 4K or 8K(1) or 16K(1-1) pagesize */
++ reg = hinfc_read(host, HINFC_ECC_ERR_NUM0_BUF0);
++ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
+
-+ if (ecc_step > 4) {
-+ /* 8K(2) or 16K(1-2) pagesize */
-+ reg = hinfc_read(host, HINFC_ECC_ERR_NUM1_BUF0);
-+ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
-+ if (ecc_step > 8) {
-+ /* 16K(2-1) pagesize */
-+ reg = hinfc_read(host, HINFC_ECC_ERR_NUM0_BUF1);
-+ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
-+ /* 16K(2-2) pagesize */
-+ reg = hinfc_read(host, HINFC_ECC_ERR_NUM1_BUF1);
-+ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
-+ }
-+ }
++ if (ecc_step > 4) {
++ /* 8K(2) or 16K(1-2) pagesize */
++ reg = hinfc_read(host, HINFC_ECC_ERR_NUM1_BUF0);
++ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
++ if (ecc_step > 8) {
++ /* 16K(2-1) pagesize */
++ reg = hinfc_read(host, HINFC_ECC_ERR_NUM0_BUF1);
++ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
++ /* 16K(2-2) pagesize */
++ reg = hinfc_read(host, HINFC_ECC_ERR_NUM1_BUF1);
++ hinfc610_ecc_err_num_count(mtd, ecc_step, reg);
++ }
++ }
+#endif
+}
+/*****************************************************************************/
@@ -293335,114 +361545,114 @@ index 0000000..b71500b
+
+/* Default OOB area layout */
+static int hinfc_ooblayout_ecc_64(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 32;
-+ oobregion->offset = 32;
++ oobregion->length = 32;
++ oobregion->offset = 32;
+
-+ return 0;
++ return 0;
+}
+
+static int hinfc_ooblayout_free_64(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 30;
-+ oobregion->offset = 2;
++ oobregion->length = 30;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+
+static struct mtd_ooblayout_ops hinfc_ooblayout_64_ops = {
-+ .ecc = hinfc_ooblayout_ecc_64,
-+ .free = hinfc_ooblayout_free_64,
++ .ecc = hinfc_ooblayout_ecc_64,
++ .free = hinfc_ooblayout_free_64,
+};
+
+/*****************************************************************************/
+
+static struct nand_config_info hinfc610_soft_auto_config_table[] = {
-+ {NAND_PAGE_16K, NAND_ECC_64BIT, 60, 1824/*1824*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_16K, NAND_ECC_40BIT, 40, 1200/*1152*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_16K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_16K, NAND_ECC_64BIT, 60, 1824/*1824*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_16K, NAND_ECC_40BIT, 40, 1200/*1152*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_16K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
+
-+ {NAND_PAGE_8K, NAND_ECC_64BIT, 60, 928 /*928*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_8K, NAND_ECC_40BIT, 40, 600 /*592*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_8K, NAND_ECC_24BIT, 24, 368 /*368*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_8K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_8K, NAND_ECC_64BIT, 60, 928 /*928*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_8K, NAND_ECC_40BIT, 40, 600 /*592*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_8K, NAND_ECC_24BIT, 24, 368 /*368*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_8K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
+
-+ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200 /*200*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_4K, NAND_ECC_4BIT_512, 8, 128 /*88*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_4K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200 /*200*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_4K, NAND_ECC_4BIT_512, 8, 128 /*88*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_4K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
+
-+ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128 /*116*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_2K, NAND_ECC_4BIT_512, 8, 64 /*60*/, &hinfc_ooblayout_64_ops},
-+ {NAND_PAGE_2K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128 /*116*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_2K, NAND_ECC_4BIT_512, 8, 64 /*60*/, &hinfc_ooblayout_64_ops},
++ {NAND_PAGE_2K, NAND_ECC_NONE, 0, 32, &hinfc_ooblayout_64_ops},
+
-+ {0, 0, 0, 0, NULL},
++ {0, 0, 0, 0, NULL},
+};
+/*****************************************************************************/
+/* used the best correct arithmetic. */
+struct nand_config_info *hinfc610_get_best_ecc(struct mtd_info *mtd)
+{
-+ struct nand_config_info *best = NULL;
-+ struct nand_config_info *config = hinfc610_soft_auto_config_table;
++ struct nand_config_info *best = NULL;
++ struct nand_config_info *config = hinfc610_soft_auto_config_table;
+
-+ for (; config->ooblayout_ops; config++) {
-+ if (nandpage_type2size(config->pagetype) != mtd->writesize) {
-+ continue;
-+ }
++ for (; config->ooblayout_ops; config++) {
++ if (nandpage_type2size(config->pagetype) != mtd->writesize) {
++ continue;
++ }
+
-+ if (mtd->oobsize < config->oobsize) {
-+ continue;
-+ }
++ if (mtd->oobsize < config->oobsize) {
++ continue;
++ }
+
-+ if (!best || (best->ecctype < config->ecctype)) {
-+ best = config;
-+ }
-+ }
++ if (!best || (best->ecctype < config->ecctype)) {
++ best = config;
++ }
++ }
+
-+ if (!best) {
-+ PR_BUG(ERSTR_DRIVER
-+ "Driver does not support the pagesize(%d) "
-+ "and oobsize(%d).\n",
-+ mtd->writesize, mtd->oobsize);
-+ }
-+ return best;
++ if (!best) {
++ PR_BUG(ERSTR_DRIVER
++ "Driver does not support the pagesize(%d) "
++ "and oobsize(%d).\n",
++ mtd->writesize, mtd->oobsize);
++ }
++ return best;
+}
+/*****************************************************************************/
+/* force the pagesize and ecctype */
+struct nand_config_info *hinfc610_force_ecc(struct mtd_info *mtd, int pagetype,
-+ int oobsize, char *cfgmsg,
-+ int allow_pagediv)
++ int oobsize, char *cfgmsg,
++ int allow_pagediv)
+{
-+ struct nand_config_info *fit = NULL;
-+ struct nand_config_info *config = hinfc610_soft_auto_config_table;
++ struct nand_config_info *fit = NULL;
++ struct nand_config_info *config = hinfc610_soft_auto_config_table;
+
-+ for (; config->ooblayout_ops; config++) {
-+ if (config->pagetype == pagetype
-+ && config->oobsize <= oobsize) {
-+ fit = config;
-+ break;
-+ }
-+ }
++ for (; config->ooblayout_ops; config++) {
++ if (config->pagetype == pagetype
++ && config->oobsize <= oobsize) {
++ fit = config;
++ break;
++ }
++ }
+
-+ if (!fit) {
-+ PR_BUG(ERSTR_DRIVER
-+ "Driver(%s mode) does not support this Nand Flash "
-+ "pagesize:%s, oobsize:%d\n",
-+ cfgmsg,
-+ nand_page_name(pagetype),
-+ oobsize);
-+ return NULL;
-+ }
-+ return fit;
++ if (!fit) {
++ PR_BUG(ERSTR_DRIVER
++ "Driver(%s mode) does not support this Nand Flash "
++ "pagesize:%s, oobsize:%d\n",
++ cfgmsg,
++ nand_page_name(pagetype),
++ oobsize);
++ return NULL;
++ }
++ return fit;
+}
+/*****************************************************************************/
+static unsigned int nand_otp_len;
@@ -293451,19 +361661,19 @@ index 0000000..b71500b
+/* Get NAND parameter table. */
+static int __init parse_nand_param(const struct tag *tag)
+{
-+ if (tag->hdr.size <= 2) {
-+ return 0;
-+ }
++ if (tag->hdr.size <= 2) {
++ return 0;
++ }
+
-+ nand_otp_len = ((tag->hdr.size << 2) - sizeof(struct tag_header));
++ nand_otp_len = ((tag->hdr.size << 2) - sizeof(struct tag_header));
+
-+ if (nand_otp_len > sizeof(nand_otp)) {
-+ pr_warn("%s(%d): Get Nand OTP from tag fail.\n",
-+ __func__, __LINE__);
-+ return 0;
-+ }
-+ memcpy(nand_otp, &tag->u, nand_otp_len);
-+ return 0;
++ if (nand_otp_len > sizeof(nand_otp)) {
++ pr_warn("%s(%d): Get Nand OTP from tag fail.\n",
++ __func__, __LINE__);
++ return 0;
++ }
++ memcpy(nand_otp, &tag->u, nand_otp_len);
++ return 0;
+}
+/* 0x48694E77 equal to fastoot ATAG_NAND_PARAM */
+__tagtable(0x48694E77, parse_nand_param);
@@ -293471,57 +361681,57 @@ index 0000000..b71500b
+/*****************************************************************************/
+int hinfc610_ecc_type2reg_intf(int type, struct hinfc_host *host)
+{
-+ if (host->version == HINFC_VER_620) {
-+ return hinfc620_ecc_type2reg(type);
-+ } else {
-+ return hinfc610_ecc_type2reg(type);
-+ }
++ if (host->version == HINFC_VER_620) {
++ return hinfc620_ecc_type2reg(type);
++ } else {
++ return hinfc610_ecc_type2reg(type);
++ }
+}
+/*****************************************************************************/
+int hinfc610_ecc_reg2type_intf(int reg, struct hinfc_host *host)
+{
-+ if (host->version == HINFC_VER_620) {
-+ return hinfc620_ecc_reg2type(reg);
-+ } else {
-+ return hinfc610_ecc_reg2type(reg);
-+ }
++ if (host->version == HINFC_VER_620) {
++ return hinfc620_ecc_reg2type(reg);
++ } else {
++ return hinfc610_ecc_reg2type(reg);
++ }
+}
+
+/*****************************************************************************/
+static int hinfc610_param_adjust(struct mtd_info *mtd, struct nand_chip *chip,
-+ struct nand_dev_t *nand_dev)
++ struct nand_dev_t *nand_dev)
+{
-+ int pagetype;
-+ int oobsize;
-+ int regval;
-+ char *start_type = "unknown";
-+ struct nand_config_info *best = NULL;
-+ struct hinfc_host *host = chip->priv;
-+ struct mtd_oob_region *hinfc_oobregion;
++ int pagetype;
++ int oobsize;
++ int regval;
++ char *start_type = "unknown";
++ struct nand_config_info *best = NULL;
++ struct hinfc_host *host = chip->priv;
++ struct mtd_oob_region *hinfc_oobregion;
+
-+ hinfc_oobregion = kmalloc(sizeof(struct mtd_oob_region), GFP_KERNEL);
-+ if (!hinfc_oobregion) {
-+ PR_BUG("failed to allocate hinfc_oobregion structure.\n");
-+ return -ENOMEM;
-+ }
++ hinfc_oobregion = kmalloc(sizeof(struct mtd_oob_region), GFP_KERNEL);
++ if (!hinfc_oobregion) {
++ PR_BUG("failed to allocate hinfc_oobregion structure.\n");
++ return -ENOMEM;
++ }
+
-+ if (IS_NANDC_HW_AUTO(host)) {
-+ start_type = "HW-Auto";
-+ } else {
-+ start_type = "HW-Reg";
-+ }
++ if (IS_NANDC_HW_AUTO(host)) {
++ start_type = "HW-Auto";
++ } else {
++ start_type = "HW-Reg";
++ }
+
-+ if ((mtd->writesize == SZ_8K)
-+ || (mtd->writesize == SZ_16K)
-+ || (mtd->writesize == SZ_32K)) {
-+ host->flags |= NAND_RANDOMIZER;
-+ }
++ if ((mtd->writesize == SZ_8K)
++ || (mtd->writesize == SZ_16K)
++ || (mtd->writesize == SZ_32K)) {
++ host->flags |= NAND_RANDOMIZER;
++ }
+
-+ pagetype = nandpage_size2type(mtd->writesize);
-+ oobsize = mtd->oobsize;
++ pagetype = nandpage_size2type(mtd->writesize);
++ oobsize = mtd->oobsize;
+
-+ best = hinfc610_force_ecc(mtd, pagetype, oobsize,
-+ start_type, 0);
++ best = hinfc610_force_ecc(mtd, pagetype, oobsize,
++ start_type, 0);
+
+#ifdef CONFIG_HINFC610_PAGESIZE_AUTO_ECC_NONE
+# ifdef CONFIG_HINFC610_AUTO_PAGESIZE_ECC
@@ -293533,240 +361743,240 @@ index 0000000..b71500b
+and CONFIG_HINFC610_HARDWARE_PAGESIZE_ECC at the same time
+# endif
+
-+ pagetype = nandpage_size2type(mtd->writesize);
-+ oobsize = 32;
-+ best = hinfc610_force_ecc(mtd, pagetype, oobsize,
-+ "force config", 0);
-+ start_type = "AutoForce";
++ pagetype = nandpage_size2type(mtd->writesize);
++ oobsize = 32;
++ best = hinfc610_force_ecc(mtd, pagetype, oobsize,
++ "force config", 0);
++ start_type = "AutoForce";
+
+#endif /* CONFIG_HINFC610_PAGESIZE_AUTO_ECC_NONE */
+
-+ if (!best) {
-+ kfree(hinfc_oobregion);
-+ PR_BUG(ERSTR_HARDWARE
-+ "Please configure Nand Flash pagesize and ecctype!\n");
-+ return -1;
-+ }
++ if (!best) {
++ kfree(hinfc_oobregion);
++ PR_BUG(ERSTR_HARDWARE
++ "Please configure Nand Flash pagesize and ecctype!\n");
++ return -1;
++ }
+
-+ /* only in case fastboot check randomizer failed.
-+ * Update fastboot or configure hardware randomizer pin
-+ * fix this problem.
-+ */
-+ if (IS_NAND_RANDOM(nand_dev) && !(IS_NAND_RANDOM(host))) {
-+ PR_BUG(ERSTR_HARDWARE
-+ "Hardware is not configure randomizer, "
-+ "but it is more suitable for this Nand Flash. "
-+ "1. Please configure hardware randomizer PIN."
-+ "2. Please updata fastboot.\n");
-+ }
++ /* only in case fastboot check randomizer failed.
++ * Update fastboot or configure hardware randomizer pin
++ * fix this problem.
++ */
++ if (IS_NAND_RANDOM(nand_dev) && !(IS_NAND_RANDOM(host))) {
++ PR_BUG(ERSTR_HARDWARE
++ "Hardware is not configure randomizer, "
++ "but it is more suitable for this Nand Flash. "
++ "1. Please configure hardware randomizer PIN."
++ "2. Please updata fastboot.\n");
++ }
+
-+ host->flags |= (IS_NAND_RANDOM(nand_dev) |
-+ IS_NAND_SYNC_ASYNC(nand_dev) |
-+ IS_NAND_ONLY_SYNC(nand_dev) |
-+ IS_NAND_ONFI(nand_dev));
++ host->flags |= (IS_NAND_RANDOM(nand_dev) |
++ IS_NAND_SYNC_ASYNC(nand_dev) |
++ IS_NAND_ONLY_SYNC(nand_dev) |
++ IS_NAND_ONFI(nand_dev));
+
-+ /* only for print nand info. */
-+ nand_dev->flags |= (IS_NANDC_HW_AUTO(host) |
-+ IS_NANDC_SYNC_BOOT(host));
++ /* only for print nand info. */
++ nand_dev->flags |= (IS_NANDC_HW_AUTO(host) |
++ IS_NANDC_SYNC_BOOT(host));
+
-+ /* only in case fastboot check sync boot pin failed.
-+ * Update fastboot or configure hardware sync boot pin fix this problem.
-+ */
-+ if (IS_NANDC_SYNC_BOOT(host)) {
-+ /* But NAND do not support sync mode, warning ! */
-+ if (!IS_NAND_ONLY_SYNC(nand_dev)) {
-+ PR_BUG(ERSTR_HARDWARE
-+ "Hardware SYNC BOOT PIN has configured sync mode, "
-+ "but the Nand Flash is async mode.\n"
-+ "1. DO NOT configure SYNC BOOT PIN. "
-+ "2. Update fastboot.\n");
++ /* only in case fastboot check sync boot pin failed.
++ * Update fastboot or configure hardware sync boot pin fix this problem.
++ */
++ if (IS_NANDC_SYNC_BOOT(host)) {
++ /* But NAND do not support sync mode, warning ! */
++ if (!IS_NAND_ONLY_SYNC(nand_dev)) {
++ PR_BUG(ERSTR_HARDWARE
++ "Hardware SYNC BOOT PIN has configured sync mode, "
++ "but the Nand Flash is async mode.\n"
++ "1. DO NOT configure SYNC BOOT PIN. "
++ "2. Update fastboot.\n");
+ }
-+ } else {
-+ if (IS_NAND_ONLY_SYNC(nand_dev)) {
-+ PR_BUG(ERSTR_HARDWARE
-+ "Hardware SYNC BOOT PIN has configured async mode, "
-+ "but the Nand Flash only support sync mode.\n"
-+ "1. Please configure SYNC BOOT PIN."
-+ "2. Update fastboot.\n");
++ } else {
++ if (IS_NAND_ONLY_SYNC(nand_dev)) {
++ PR_BUG(ERSTR_HARDWARE
++ "Hardware SYNC BOOT PIN has configured async mode, "
++ "but the Nand Flash only support sync mode.\n"
++ "1. Please configure SYNC BOOT PIN."
++ "2. Update fastboot.\n");
+ }
-+ }
++ }
+
-+ if (IS_NAND_SYNC_ASYNC(nand_dev)) {
-+ hinfc610_get_sync_info(host);
-+ }
++ if (IS_NAND_SYNC_ASYNC(nand_dev)) {
++ hinfc610_get_sync_info(host);
++ }
+
-+ if (best->ecctype != NAND_ECC_NONE) {
-+ mtd->oobsize = best->oobsize;
-+ }
++ if (best->ecctype != NAND_ECC_NONE) {
++ mtd->oobsize = best->oobsize;
++ }
+
-+ if (best->ooblayout_ops->free) {
-+ best->ooblayout_ops->free(mtd, 0, hinfc_oobregion);
-+ }
++ if (best->ooblayout_ops->free) {
++ best->ooblayout_ops->free(mtd, 0, hinfc_oobregion);
++ }
+
-+ host->ecctype = best->ecctype;
-+ host->pagesize = nandpage_type2size(best->pagetype);
-+ host->oobsize = mtd->oobsize;
-+ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
++ host->ecctype = best->ecctype;
++ host->pagesize = nandpage_type2size(best->pagetype);
++ host->oobsize = mtd->oobsize;
++ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
+
-+ host->buffer = dma_alloc_coherent(host->dev,
-+ (host->pagesize + host->oobsize),
-+ &host->dma_buffer, GFP_KERNEL);
-+ if (!host->buffer) {
-+ kfree(hinfc_oobregion);
-+ PR_BUG("Can't malloc memory for NAND driver.");
-+ return -EIO;
-+ }
-+ memset(host->buffer, 0xff, (host->pagesize + host->oobsize));
++ host->buffer = dma_alloc_coherent(host->dev,
++ (host->pagesize + host->oobsize),
++ &host->dma_buffer, GFP_KERNEL);
++ if (!host->buffer) {
++ kfree(hinfc_oobregion);
++ PR_BUG("Can't malloc memory for NAND driver.");
++ return -EIO;
++ }
++ memset(host->buffer, 0xff, (host->pagesize + host->oobsize));
+
-+ host->dma_oob = host->dma_buffer + host->pagesize;
-+ host->bbm = (unsigned char *)(host->buffer
-+ + host->pagesize + HINFC_BAD_BLOCK_POS);
++ host->dma_oob = host->dma_buffer + host->pagesize;
++ host->bbm = (unsigned char *)(host->buffer
++ + host->pagesize + HINFC_BAD_BLOCK_POS);
+
-+ host->epm = (unsigned short *)(host->buffer
-+ + host->pagesize + hinfc_oobregion->offset + 28);
++ host->epm = (unsigned short *)(host->buffer
++ + host->pagesize + hinfc_oobregion->offset + 28);
+
-+ regval = ~(HINFC610_CON_PAGESIZE_MASK << HINFC610_CON_PAGEISZE_SHIFT);
-+ host->NFC_CON &= regval;
-+ host->NFC_CON_ECC_NONE &= regval;
-+ regval = (hinfc610_page_type2reg(best->pagetype)
-+ & HINFC610_CON_PAGESIZE_MASK) << HINFC610_CON_PAGEISZE_SHIFT;
-+ host->NFC_CON |= regval;
-+ host->NFC_CON_ECC_NONE |= regval;
++ regval = ~(HINFC610_CON_PAGESIZE_MASK << HINFC610_CON_PAGEISZE_SHIFT);
++ host->NFC_CON &= regval;
++ host->NFC_CON_ECC_NONE &= regval;
++ regval = (hinfc610_page_type2reg(best->pagetype)
++ & HINFC610_CON_PAGESIZE_MASK) << HINFC610_CON_PAGEISZE_SHIFT;
++ host->NFC_CON |= regval;
++ host->NFC_CON_ECC_NONE |= regval;
+
-+ regval = ~(HINFC610_CON_ECCTYPE_MASK << HINFC610_CON_ECCTYPE_SHIFT);
-+ host->NFC_CON &= regval;
-+ host->NFC_CON_ECC_NONE &= regval;
-+ regval = (hinfc610_ecc_type2reg_intf(best->ecctype, host)
-+ & HINFC610_CON_ECCTYPE_MASK) << HINFC610_CON_ECCTYPE_SHIFT;
-+ host->NFC_CON |= regval;
++ regval = ~(HINFC610_CON_ECCTYPE_MASK << HINFC610_CON_ECCTYPE_SHIFT);
++ host->NFC_CON &= regval;
++ host->NFC_CON_ECC_NONE &= regval;
++ regval = (hinfc610_ecc_type2reg_intf(best->ecctype, host)
++ & HINFC610_CON_ECCTYPE_MASK) << HINFC610_CON_ECCTYPE_SHIFT;
++ host->NFC_CON |= regval;
+
-+ if (mtd->writesize > NAND_MAX_PAGESIZE ||
-+ mtd->oobsize > NAND_MAX_OOBSIZE) {
-+ PR_BUG(ERSTR_DRIVER
-+ "Driver does not support this Nand Flash. "
-+ "Please increase NAND_MAX_PAGESIZE and NAND_MAX_OOBSIZE.\n");
-+ }
++ if (mtd->writesize > NAND_MAX_PAGESIZE ||
++ mtd->oobsize > NAND_MAX_OOBSIZE) {
++ PR_BUG(ERSTR_DRIVER
++ "Driver does not support this Nand Flash. "
++ "Please increase NAND_MAX_PAGESIZE and NAND_MAX_OOBSIZE.\n");
++ }
+
-+ if (mtd->writesize != host->pagesize) {
-+ unsigned int shift = 0;
-+ unsigned int writesize = mtd->writesize;
++ if (mtd->writesize != host->pagesize) {
++ unsigned int shift = 0;
++ unsigned int writesize = mtd->writesize;
+
-+ while (writesize > host->pagesize) {
-+ writesize >>= 1;
-+ shift++;
-+ }
-+ chip->chipsize = chip->chipsize >> shift;
-+ mtd->erasesize = mtd->erasesize >> shift;
-+ mtd->writesize = host->pagesize;
-+ PR_MSG("Nand divide into 1/%u\n", (1 << shift));
-+ }
++ while (writesize > host->pagesize) {
++ writesize >>= 1;
++ shift++;
++ }
++ chip->chipsize = chip->chipsize >> shift;
++ mtd->erasesize = mtd->erasesize >> shift;
++ mtd->writesize = host->pagesize;
++ PR_MSG("Nand divide into 1/%u\n", (1 << shift));
++ }
+
-+ nand_dev->start_type = start_type;
-+ nand_dev->ecctype = host->ecctype;
-+ nand_dev->oobsize = mtd->oobsize;
++ nand_dev->start_type = start_type;
++ nand_dev->ecctype = host->ecctype;
++ nand_dev->oobsize = mtd->oobsize;
+
-+ host->read_retry = NULL;
-+ if (nand_dev->read_retry_type != NAND_RR_NONE) {
-+ host->read_retry
-+ = hinfc610_find_read_retry(nand_dev->read_retry_type);
-+ if (!host->read_retry) {
-+ PR_BUG(ERSTR_DRIVER
-+ "This Nand Flash need to enable the "
-+ "'read retry' feature. "
-+ "but the driver dose not offer the feature");
-+ }
++ host->read_retry = NULL;
++ if (nand_dev->read_retry_type != NAND_RR_NONE) {
++ host->read_retry
++ = hinfc610_find_read_retry(nand_dev->read_retry_type);
++ if (!host->read_retry) {
++ PR_BUG(ERSTR_DRIVER
++ "This Nand Flash need to enable the "
++ "'read retry' feature. "
++ "but the driver dose not offer the feature");
++ }
+
-+ if (nand_otp_len) {
-+ memcpy(host->rr_data, nand_otp, nand_otp_len);
-+ }
-+ }
++ if (nand_otp_len) {
++ memcpy(host->rr_data, nand_otp, nand_otp_len);
++ }
++ }
+
-+ /*
-+ * If it want to support the 'read retry' feature, the 'randomizer'
-+ * feature must be support first.
-+ */
-+ if (host->read_retry && !IS_NAND_RANDOM(host)) {
-+ PR_BUG(ERSTR_HARDWARE
-+ "This Nand flash need to enable 'randomizer' feature. "
-+ "Please configure hardware randomizer PIN.");
-+ }
++ /*
++ * If it want to support the 'read retry' feature, the 'randomizer'
++ * feature must be support first.
++ */
++ if (host->read_retry && !IS_NAND_RANDOM(host)) {
++ PR_BUG(ERSTR_HARDWARE
++ "This Nand flash need to enable 'randomizer' feature. "
++ "Please configure hardware randomizer PIN.");
++ }
+
+
-+ mtd_set_ooblayout(mtd, &hinfc_ooblayout_64_ops);
-+ hinfc610_dbg_init(host);
++ mtd_set_ooblayout(mtd, &hinfc_ooblayout_64_ops);
++ hinfc610_dbg_init(host);
+
-+ kfree(hinfc_oobregion);
++ kfree(hinfc_oobregion);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+int hinfc610_nand_init(struct hinfc_host *host, struct nand_chip *chip)
+{
-+ unsigned int regval;
++ unsigned int regval;
+
-+ host->version = hinfc_read(host, HINFC610_VERSION);
++ host->version = hinfc_read(host, HINFC610_VERSION);
+
-+ host->addr_cycle = 0;
-+ host->addr_value[0] = 0;
-+ host->addr_value[1] = 0;
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
-+ host->chipselect = 0;
++ host->addr_cycle = 0;
++ host->addr_value[0] = 0;
++ host->addr_value[1] = 0;
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
++ host->chipselect = 0;
+
-+ host->send_cmd_pageprog = hinfc610_send_cmd_pageprog;
-+ host->send_cmd_readstart = hinfc610_send_cmd_readstart;
-+ host->send_cmd_erase = hinfc610_send_cmd_erase;
-+ host->send_cmd_readid = hinfc610_send_cmd_readid;
-+ host->send_cmd_status = hinfc610_send_cmd_status;
-+ host->send_cmd_reset = hinfc610_send_cmd_reset;
++ host->send_cmd_pageprog = hinfc610_send_cmd_pageprog;
++ host->send_cmd_readstart = hinfc610_send_cmd_readstart;
++ host->send_cmd_erase = hinfc610_send_cmd_erase;
++ host->send_cmd_readid = hinfc610_send_cmd_readid;
++ host->send_cmd_status = hinfc610_send_cmd_status;
++ host->send_cmd_reset = hinfc610_send_cmd_reset;
+
-+ host->flags = 0;
++ host->flags = 0;
+
-+ regval = hinfc_read(host, HINFC610_CON);
++ regval = hinfc_read(host, HINFC610_CON);
+
-+ host->NFC_CON = (regval
-+ | HINFC610_CON_OP_MODE_NORMAL
-+ | HINFC610_CON_READY_BUSY_SEL);
++ host->NFC_CON = (regval
++ | HINFC610_CON_OP_MODE_NORMAL
++ | HINFC610_CON_READY_BUSY_SEL);
+
-+ host->NFC_CON_ECC_NONE = host->NFC_CON
-+ & (~(HINFC610_CON_ECCTYPE_MASK
-+ << HINFC610_CON_ECCTYPE_SHIFT))
-+ & (~HINFC610_CON_RANDOMIZER_EN);
++ host->NFC_CON_ECC_NONE = host->NFC_CON
++ & (~(HINFC610_CON_ECCTYPE_MASK
++ << HINFC610_CON_ECCTYPE_SHIFT))
++ & (~HINFC610_CON_RANDOMIZER_EN);
+
-+ hinfc_write(host,
-+ (SET_HINFC610_PWIDTH(CONFIG_HINFC610_W_LATCH,
-+ CONFIG_HINFC610_R_LATCH,
-+ CONFIG_HINFC610_RW_LATCH)),
-+ HINFC610_PWIDTH);
++ hinfc_write(host,
++ (SET_HINFC610_PWIDTH(CONFIG_HINFC610_W_LATCH,
++ CONFIG_HINFC610_R_LATCH,
++ CONFIG_HINFC610_RW_LATCH)),
++ HINFC610_PWIDTH);
+
-+ host->flags |= NANDC_HW_AUTO;
++ host->flags |= NANDC_HW_AUTO;
+
-+ /* check if chip is sync mode. */
-+ if (regval & HINFC610_BOOT_CFG_SYC_NAND_PAD) {
-+ host->flags |= NANDC_IS_SYNC_BOOT;
++ /* check if chip is sync mode. */
++ if (regval & HINFC610_BOOT_CFG_SYC_NAND_PAD) {
++ host->flags |= NANDC_IS_SYNC_BOOT;
+
-+ /*
-+ * NAND default is sync mode, and read id, reset in sync mode.
-+ */
-+ host->NFC_CON |= HINFC610_CON_NF_MODE_TOGGLE;
-+ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_TOGGLE;
++ /*
++ * NAND default is sync mode, and read id, reset in sync mode.
++ */
++ host->NFC_CON |= HINFC610_CON_NF_MODE_TOGGLE;
++ host->NFC_CON_ECC_NONE |= HINFC610_CON_NF_MODE_TOGGLE;
+
-+ /* set synchronous clock and timing. */
-+ clk_prepare_enable(host->clk);
-+ }
++ /* set synchronous clock and timing. */
++ clk_prepare_enable(host->clk);
++ }
+
-+ memset((char *)chip->IO_ADDR_R,
-+ 0xff, HINFC610_BUFFER_BASE_ADDRESS_LEN);
++ memset((char *)chip->IO_ADDR_R,
++ 0xff, HINFC610_BUFFER_BASE_ADDRESS_LEN);
+
-+ host->enable_ecc_randomizer = hinfc610_enable_ecc_randomizer;
-+ hinfc_param_adjust = hinfc610_param_adjust;
++ host->enable_ecc_randomizer = hinfc610_enable_ecc_randomizer;
++ hinfc_param_adjust = hinfc610_param_adjust;
+
-+ return 0;
++ return 0;
+}
diff --git a/drivers/mtd/nand/hinfc610/hinfc610.h b/drivers/mtd/nand/hinfc610/hinfc610.h
new file mode 100644
-index 0000000..4c073a1
+index 0000000..6a8f98b
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610.h
@@ -0,0 +1,512 @@
@@ -293977,72 +362187,72 @@ index 0000000..4c073a1
+/*****************************************************************************/
+
+struct hinfc_host {
-+ struct nand_chip *chip;
-+ struct mtd_info *mtd;
-+ void __iomem *iobase;
-+ struct device *dev;
++ struct nand_chip *chip;
++ struct mtd_info *mtd;
++ void __iomem *iobase;
++ struct device *dev;
+
-+ unsigned int offset;
-+ unsigned int command;
++ unsigned int offset;
++ unsigned int command;
+
-+ int chipselect;
++ int chipselect;
+
-+ unsigned int n24bit_ext_len;
-+ int ecctype;
++ unsigned int n24bit_ext_len;
++ int ecctype;
+
-+ /* Current system has already gone to sync mode */
++ /* Current system has already gone to sync mode */
+#define HINFC610_IS_SYNC(_host) ((_host)->NFC_CON & HINFC610_CON_NF_MODE_MASK)
-+ unsigned long NFC_CON;
-+ unsigned long NFC_CON_ECC_NONE;
++ unsigned long NFC_CON;
++ unsigned long NFC_CON_ECC_NONE;
+
-+ unsigned int addr_cycle;
-+ unsigned int addr_value[2];
-+ unsigned int cache_addr_value[2];
-+ unsigned int column;
-+ unsigned int block_page_mask;
++ unsigned int addr_cycle;
++ unsigned int addr_value[2];
++ unsigned int cache_addr_value[2];
++ unsigned int column;
++ unsigned int block_page_mask;
+
-+ unsigned int dma_oob;
-+ unsigned int dma_buffer;
-+ unsigned int pagesize;
-+ unsigned int oobsize;
-+ /* This is maybe an un-aligment address, only for malloc or free */
-+ char *buforg;
-+ char *buffer;
++ unsigned int dma_oob;
++ unsigned int dma_buffer;
++ unsigned int pagesize;
++ unsigned int oobsize;
++ /* This is maybe an un-aligment address, only for malloc or free */
++ char *buforg;
++ char *buffer;
+
-+ int need_rr_data;
++ int need_rr_data;
+#define HINFC_READ_RETRY_DATA_LEN 128
-+ char rr_data[HINFC_READ_RETRY_DATA_LEN];
-+ int version;
-+ int add_partition;
++ char rr_data[HINFC_READ_RETRY_DATA_LEN];
++ int version;
++ int add_partition;
+
-+ /* BOOTROM read two bytes to detect the bad block flag */
++ /* BOOTROM read two bytes to detect the bad block flag */
+#define HINFC_BAD_BLOCK_POS 0
-+ unsigned char *bbm; /* nand bad block mark */
-+ unsigned short *epm; /* nand empty page mark */
-+ unsigned int flags;
++ unsigned char *bbm; /* nand bad block mark */
++ unsigned short *epm; /* nand empty page mark */
++ unsigned int flags;
+
+#define HINFC610_PS_UC_ECC 0x01 /* page has ecc error */
+#define HINFC610_PS_BAD_BLOCK 0x02 /* bad block */
+#define HINFC610_PS_EMPTY_PAGE 0x04 /* page is empty */
+#define HINFC610_PS_EPM_ERROR 0x0100 /* empty page mark word has ecc error*/
+#define HINFC610_PS_BBM_ERROR 0x0200 /* bad block mark word has ecc error*/
-+ unsigned int page_status;
++ unsigned int page_status;
+
-+ struct clk *clk;
++ struct clk *clk;
+
-+ int (*send_cmd_pageprog)(struct hinfc_host *host);
-+ int (*send_cmd_status)(struct hinfc_host *host);
-+ int (*send_cmd_readstart)(struct hinfc_host *host);
-+ int (*send_cmd_erase)(struct hinfc_host *host);
-+ int (*send_cmd_readid)(struct hinfc_host *host);
-+ int (*send_cmd_reset)(struct hinfc_host *host, int chipselect);
-+ int (*enable)(struct hinfc_host *host, int enable);
++ int (*send_cmd_pageprog)(struct hinfc_host *host);
++ int (*send_cmd_status)(struct hinfc_host *host);
++ int (*send_cmd_readstart)(struct hinfc_host *host);
++ int (*send_cmd_erase)(struct hinfc_host *host);
++ int (*send_cmd_readid)(struct hinfc_host *host);
++ int (*send_cmd_reset)(struct hinfc_host *host, int chipselect);
++ int (*enable)(struct hinfc_host *host, int enable);
+
-+ int (*enable_ecc_randomizer)(struct hinfc_host *host,
-+ int ecc_en, int randomizer_en);
++ int (*enable_ecc_randomizer)(struct hinfc_host *host,
++ int ecc_en, int randomizer_en);
+
-+ struct read_retry_t *read_retry;
-+ struct nand_sync *sync;
++ struct read_retry_t *read_retry;
++ struct nand_sync *sync;
+};
+
+#define HINFC610_UC_ECC 0x01
@@ -294263,12 +362473,12 @@ index 0000000..4c073a1
+#else
+int register_mtd_partdev(struct mtd_info *mtd)
+{
-+ return 0;
++ return 0;
+};
+
+int unregister_mtd_partdev(struct mtd_info *mtd)
+{
-+ return 0;
++ return 0;
+};
+#endif
+
@@ -294284,7 +362494,7 @@ index 0000000..4c073a1
+#endif /* HINFCV610H */
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg.c b/drivers/mtd/nand/hinfc610/hinfc610_dbg.c
new file mode 100644
-index 0000000..9126f21
+index 0000000..1fb7b63
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg.c
@@ -0,0 +1,312 @@
@@ -294320,21 +362530,21 @@ index 0000000..9126f21
+#include "hinfc610_dbg.h"
+
+struct hinfc610_dbg_inf_t *hinfc610_dbg_inf[] = {
-+ &hinfc610_dbg_inf_ecc_notice,
-+ &hinfc610_dbg_inf_read_retry_notice,
++ &hinfc610_dbg_inf_ecc_notice,
++ &hinfc610_dbg_inf_read_retry_notice,
+#ifdef CONFIG_HINFC610_DBG_NAND_DUMP
-+ &hinfc610_dbg_inf_dump,
++ &hinfc610_dbg_inf_dump,
+#endif
+#ifdef CONFIG_HINFC610_DBG_NAND_ERASE_COUNT
-+ &hinfc610_dbg_inf_erase_count,
++ &hinfc610_dbg_inf_erase_count,
+#endif
+#ifdef CONFIG_HINFC610_DBG_NAND_ECC_COUNT
-+ &hinfc610_dbg_inf_ecc_count,
++ &hinfc610_dbg_inf_ecc_count,
+#endif
+#ifdef CONFIG_HINFC610_DBG_NAND_READ_RETRY
-+ &hinfc610_dbg_inf_read_retry,
++ &hinfc610_dbg_inf_read_retry,
+#endif
-+ NULL,
++ NULL,
+};
+
+static struct dentry *dbgfs_root;
@@ -294342,267 +362552,267 @@ index 0000000..9126f21
+
+/*****************************************************************************/
+static ssize_t dbgfs_debug_read(struct file *filp, char __user *buffer,
-+ size_t count, loff_t *ppos)
++ size_t count, loff_t *ppos)
+{
-+ char *msg, *p;
-+ struct hinfc610_dbg_inf_t **inf;
++ char *msg, *p;
++ struct hinfc610_dbg_inf_t **inf;
+
-+ if (*ppos != 0) {
-+ return 0;
-+ }
++ if (*ppos != 0) {
++ return 0;
++ }
+
-+ msg = (char *)__get_free_page(GFP_TEMPORARY);
-+ if (!msg) {
-+ return -ENOMEM;
-+ }
++ msg = (char *)__get_free_page(GFP_TEMPORARY);
++ if (!msg) {
++ return -ENOMEM;
++ }
+
-+ p = msg;
-+ if (count > PAGE_SIZE) {
-+ count = PAGE_SIZE;
-+ }
++ p = msg;
++ if (count > PAGE_SIZE) {
++ count = PAGE_SIZE;
++ }
+
-+ for (inf = hinfc610_dbg_inf; *inf; inf++) {
-+ if ((p - msg) + MAX_OPTION_SIZE + 2 > count) {
-+ PR_ERR("Not enough memory.\n");
-+ break;
-+ }
-+ p += snprintf(p, (MAX_OPTION_SIZE + 2), "%c%s,",
-+ ((*inf)->enable ? '+' : '-'),
-+ (*inf)->name);
-+ }
++ for (inf = hinfc610_dbg_inf; *inf; inf++) {
++ if ((p - msg) + MAX_OPTION_SIZE + 2 > count) {
++ PR_ERR("Not enough memory.\n");
++ break;
++ }
++ p += snprintf(p, (MAX_OPTION_SIZE + 2), "%c%s,",
++ ((*inf)->enable ? '+' : '-'),
++ (*inf)->name);
++ }
+
-+ p += sprintf(p, "\n");
-+ count = (p - msg);
-+ if (copy_to_user(buffer, msg, count)) {
-+ free_page((unsigned long) msg);
-+ return -EFAULT;
-+ }
++ p += sprintf(p, "\n");
++ count = (p - msg);
++ if (copy_to_user(buffer, msg, count)) {
++ free_page((unsigned long) msg);
++ return -EFAULT;
++ }
+
-+ free_page((unsigned long) msg);
++ free_page((unsigned long) msg);
+
-+ *ppos += count;
-+ return count;
++ *ppos += count;
++ return count;
+}
+/*****************************************************************************/
+
+static void dbgfs_debug_do_cmd(struct hinfc610_dbg_inf_t **dbg_inf,
-+ const char *cmd, unsigned int length, int enable)
++ const char *cmd, unsigned int length, int enable)
+{
-+ int ret = 0;
-+ struct hinfc610_dbg_inf_t **inf;
++ int ret = 0;
++ struct hinfc610_dbg_inf_t **inf;
+
-+ if (length >= sizeof((*inf)->name)) {
-+ return;
-+ }
++ if (length >= sizeof((*inf)->name)) {
++ return;
++ }
+
-+ for (inf = dbg_inf; *inf; inf++) {
-+ if (!(*inf)->name[length] &&
-+ !memcmp((*inf)->name, cmd, length)) {
-+ break;
-+ }
-+ }
++ for (inf = dbg_inf; *inf; inf++) {
++ if (!(*inf)->name[length] &&
++ !memcmp((*inf)->name, cmd, length)) {
++ break;
++ }
++ }
+
-+ if (!(*inf) || (*inf)->enable == enable) {
-+ return;
-+ }
++ if (!(*inf) || (*inf)->enable == enable) {
++ return;
++ }
+
-+ if (enable) {
-+ if ((*inf)->init) {
-+ ret = (*inf)->init(dbgfs_root, dbgfs_host);
-+ }
-+ } else {
-+ if ((*inf)->uninit) {
-+ ret = (*inf)->uninit();
-+ }
-+ }
++ if (enable) {
++ if ((*inf)->init) {
++ ret = (*inf)->init(dbgfs_root, dbgfs_host);
++ }
++ } else {
++ if ((*inf)->uninit) {
++ ret = (*inf)->uninit();
++ }
++ }
+
-+ if (!ret) {
-+ (*inf)->enable = enable;
-+ }
++ if (!ret) {
++ (*inf)->enable = enable;
++ }
+}
+/*****************************************************************************/
+
+static void dbgfs_debug_ops(const char *options,
-+ struct hinfc610_dbg_inf_t **dbg_inf)
++ struct hinfc610_dbg_inf_t **dbg_inf)
+{
-+ int enable;
-+ const char *pos, *cmd;
++ int enable;
++ const char *pos, *cmd;
+
-+ pos = options;
++ pos = options;
+
-+ while (*pos) {
++ while (*pos) {
+
-+ while (*pos && *pos != '+' && *pos != '-') {
-+ pos++;
-+ }
++ while (*pos && *pos != '+' && *pos != '-') {
++ pos++;
++ }
+
-+ switch (*pos++) {
-+ case '+':
-+ enable = 1;
-+ break;
-+ case '-':
-+ enable = 0;
-+ break;
-+ default:
-+ return;
-+ }
++ switch (*pos++) {
++ case '+':
++ enable = 1;
++ break;
++ case '-':
++ enable = 0;
++ break;
++ default:
++ return;
++ }
+
-+ cmd = pos;
-+ while (*pos == '_' || isalpha(*pos)) {
-+ pos++;
-+ }
++ cmd = pos;
++ while (*pos == '_' || isalpha(*pos)) {
++ pos++;
++ }
+
-+ if (*cmd && pos > cmd) {
-+ dbgfs_debug_do_cmd(dbg_inf, cmd, (pos - cmd), enable);
-+ }
++ if (*cmd && pos > cmd) {
++ dbgfs_debug_do_cmd(dbg_inf, cmd, (pos - cmd), enable);
++ }
+
-+ while (isspace(*pos) || *pos == ',' || *pos == ';') {
-+ pos++;
-+ }
-+ }
++ while (isspace(*pos) || *pos == ',' || *pos == ';') {
++ pos++;
++ }
++ }
+}
+/*****************************************************************************/
+/*
+ * echo "+dump, +read_retry, +ecc_count, +erase_count" > debug
+ */
+static ssize_t dbgfs_debug_write(struct file *filp, const char __user *buffer,
-+ size_t count, loff_t *ppos)
++ size_t count, loff_t *ppos)
+{
-+ char *options;
-+ size_t num = count;
++ char *options;
++ size_t num = count;
+
-+ if (count > PAGE_SIZE) {
-+ num = (PAGE_SIZE - 1);
-+ }
++ if (count > PAGE_SIZE) {
++ num = (PAGE_SIZE - 1);
++ }
+
-+ options = (char *)__get_free_page(GFP_TEMPORARY);
-+ if (!options) {
-+ return -ENOMEM;
-+ }
++ options = (char *)__get_free_page(GFP_TEMPORARY);
++ if (!options) {
++ return -ENOMEM;
++ }
+
-+ if (copy_from_user(options, buffer, num)) {
-+ free_page((unsigned long) options);
-+ return -EFAULT;
-+ }
++ if (copy_from_user(options, buffer, num)) {
++ free_page((unsigned long) options);
++ return -EFAULT;
++ }
+
-+ options[num] = 0;
++ options[num] = 0;
+
-+ dbgfs_debug_ops(options, hinfc610_dbg_inf);
++ dbgfs_debug_ops(options, hinfc610_dbg_inf);
+
-+ free_page((unsigned long) options);
++ free_page((unsigned long) options);
+
-+ *ppos += count;
-+ return count;
++ *ppos += count;
++ return count;
+}
+/*****************************************************************************/
+
+static const struct file_operations dbgfs_debug_fops = {
-+ .owner = THIS_MODULE,
-+ .read = dbgfs_debug_read,
-+ .write = dbgfs_debug_write,
++ .owner = THIS_MODULE,
++ .read = dbgfs_debug_read,
++ .write = dbgfs_debug_write,
+};
+/*****************************************************************************/
+
+int hinfc610_dbgfs_debug_init(struct hinfc_host *host)
+{
-+ struct dentry *dentry;
++ struct dentry *dentry;
+
-+ if (dbgfs_root) {
-+ return 0;
-+ }
++ if (dbgfs_root) {
++ return 0;
++ }
+
-+ dbgfs_root = debugfs_create_dir("nand", NULL);
-+ if (!dbgfs_root) {
-+ PR_ERR("Can't create 'nand' dir.\n");
-+ return -ENOENT;
-+ }
++ dbgfs_root = debugfs_create_dir("nand", NULL);
++ if (!dbgfs_root) {
++ PR_ERR("Can't create 'nand' dir.\n");
++ return -ENOENT;
++ }
+
-+ dentry = debugfs_create_file("debug", S_IFREG | S_IRUSR | S_IWUSR,
-+ dbgfs_root, NULL, &dbgfs_debug_fops);
-+ if (!dentry) {
-+ PR_ERR("Can't create 'debug' file.\n");
-+ goto fail;
-+ }
++ dentry = debugfs_create_file("debug", S_IFREG | S_IRUSR | S_IWUSR,
++ dbgfs_root, NULL, &dbgfs_debug_fops);
++ if (!dentry) {
++ PR_ERR("Can't create 'debug' file.\n");
++ goto fail;
++ }
+
-+ dbgfs_host = host;
++ dbgfs_host = host;
+
-+ if (nand_dbgfs_options) {
-+ dbgfs_debug_ops(nand_dbgfs_options, hinfc610_dbg_inf);
-+ }
++ if (nand_dbgfs_options) {
++ dbgfs_debug_ops(nand_dbgfs_options, hinfc610_dbg_inf);
++ }
+
-+ return 0;
++ return 0;
+
+fail:
-+ debugfs_remove_recursive(dbgfs_root);
-+ dbgfs_root = NULL;
++ debugfs_remove_recursive(dbgfs_root);
++ dbgfs_root = NULL;
+
-+ return -ENOENT;
++ return -ENOENT;
+}
+/*****************************************************************************/
+
+static int dbgfs_read_retry_notice_init(struct dentry *root,
-+ struct hinfc_host *host)
++ struct hinfc_host *host)
+{
-+ if (!host->read_retry) {
-+ pr_warn("read_retry_notice: The NAND not support this interface.\n");
-+ return -1;
-+ }
++ if (!host->read_retry) {
++ pr_warn("read_retry_notice: The NAND not support this interface.\n");
++ return -1;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static void hinfc610_dbg_read_retry_notice(struct hinfc_host *host, int index)
+{
-+ pr_warn("Page 0x%08x do read retry (%d/%d) %s.\n",
-+ GET_PAGE_INDEX(host), index, host->read_retry->count,
-+ (IS_PS_UN_ECC(host) ? "Fail" : "Success"));
++ pr_warn("Page 0x%08x do read retry (%d/%d) %s.\n",
++ GET_PAGE_INDEX(host), index, host->read_retry->count,
++ (IS_PS_UN_ECC(host) ? "Fail" : "Success"));
+}
+
+struct hinfc610_dbg_inf_t hinfc610_dbg_inf_read_retry_notice = {
-+ "read_retry_notice", 0,
-+ dbgfs_read_retry_notice_init,
-+ NULL,
-+ NULL,
-+ NULL,
-+ NULL,
-+ hinfc610_dbg_read_retry_notice,
++ "read_retry_notice", 0,
++ dbgfs_read_retry_notice_init,
++ NULL,
++ NULL,
++ NULL,
++ NULL,
++ hinfc610_dbg_read_retry_notice,
+};
+/*****************************************************************************/
+
+static void hinfc610_dbg_ecc_notice_read(struct hinfc_host *host)
+{
-+ unsigned int pageindex = GET_PAGE_INDEX(host);
++ unsigned int pageindex = GET_PAGE_INDEX(host);
+
-+ if (IS_PS_BAD_BLOCK(host) || IS_PS_EMPTY_PAGE(host)) {
-+ if (IS_PS_BBM_ERR(host)) {
-+ pr_warn("page 0x%08x bbm is corruption, bbm: 0x%x.\n",
-+ pageindex, *host->bbm);
-+ }
-+ if (IS_PS_EPM_ERR(host)) {
-+ pr_warn("page 0x%08x epm is corruption, epm: 0x%x.\n",
-+ pageindex, *host->epm);
-+ }
-+ return;
-+ }
++ if (IS_PS_BAD_BLOCK(host) || IS_PS_EMPTY_PAGE(host)) {
++ if (IS_PS_BBM_ERR(host)) {
++ pr_warn("page 0x%08x bbm is corruption, bbm: 0x%x.\n",
++ pageindex, *host->bbm);
++ }
++ if (IS_PS_EPM_ERR(host)) {
++ pr_warn("page 0x%08x epm is corruption, epm: 0x%x.\n",
++ pageindex, *host->epm);
++ }
++ return;
++ }
+
-+ if (IS_PS_UN_ECC(host)) {
-+ pr_warn("page 0x%08x has uncorrect ecc.\n", pageindex);
-+ }
++ if (IS_PS_UN_ECC(host)) {
++ pr_warn("page 0x%08x has uncorrect ecc.\n", pageindex);
++ }
+}
+
+struct hinfc610_dbg_inf_t hinfc610_dbg_inf_ecc_notice = {
-+ "ecc_notice", 0,
-+ NULL,
-+ NULL,
-+ hinfc610_dbg_ecc_notice_read,
-+ NULL,
-+ NULL,
-+ NULL,
++ "ecc_notice", 0,
++ NULL,
++ NULL,
++ hinfc610_dbg_ecc_notice_read,
++ NULL,
++ NULL,
++ NULL,
+};
+/*****************************************************************************/
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg.h b/drivers/mtd/nand/hinfc610/hinfc610_dbg.h
new file mode 100644
-index 0000000..e217b15
+index 0000000..2d71801
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg.h
@@ -0,0 +1,63 @@
@@ -294632,16 +362842,16 @@ index 0000000..e217b15
+#define MAX_OPTION_SIZE 20
+
+struct hinfc610_dbg_inf_t {
-+ const char name[MAX_OPTION_SIZE];
-+ int enable;
-+ int (*init)(struct dentry *root, struct hinfc_host *host);
-+ int (*uninit)(void);
++ const char name[MAX_OPTION_SIZE];
++ int enable;
++ int (*init)(struct dentry *root, struct hinfc_host *host);
++ int (*uninit)(void);
+
-+ void (*read)(struct hinfc_host *host);
-+ void (*write)(struct hinfc_host *host);
-+ void (*erase)(struct hinfc_host *host);
++ void (*read)(struct hinfc_host *host);
++ void (*write)(struct hinfc_host *host);
++ void (*erase)(struct hinfc_host *host);
+
-+ void (*read_retry)(struct hinfc_host *host, int index);
++ void (*read_retry)(struct hinfc_host *host, int index);
+};
+
+#define CMD_WORD_OFFSET "offset="
@@ -294651,14 +362861,14 @@ index 0000000..e217b15
+#define CMD_WORD_OFF "off"
+
+struct hinfc610_ecc_inf_t {
-+ int pagesize;
-+ int ecctype;
-+ int section;
-+ void (*ecc_inf)(struct hinfc_host *host, unsigned char ecc[]);
++ int pagesize;
++ int ecctype;
++ int section;
++ void (*ecc_inf)(struct hinfc_host *host, unsigned char ecc[]);
+};
+
+struct hinfc610_ecc_inf_t *hinfc610_get_ecc_inf(struct hinfc_host *host,
-+ int pagesize, int ecctype);
++ int pagesize, int ecctype);
+
+extern struct hinfc610_dbg_inf_t hinfc610_dbg_inf_dump;
+extern struct hinfc610_dbg_inf_t hinfc610_dbg_inf_erase_count;
@@ -294671,7 +362881,7 @@ index 0000000..e217b15
+#endif /* HINFC610_DBGH */
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg_dump.c b/drivers/mtd/nand/hinfc610/hinfc610_dbg_dump.c
new file mode 100644
-index 0000000..395cfdd
+index 0000000..db1de0c
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg_dump.c
@@ -0,0 +1,483 @@
@@ -294715,36 +362925,36 @@ index 0000000..395cfdd
+#endif /* CONFIG_HINFC610_DBG_NAND_LOG_LENGTH */
+
+struct hinfc610_dbg_dump_item_t {
-+ unsigned short hour;
-+ unsigned short min;
-+ unsigned short sec;
-+ unsigned short msec;
++ unsigned short hour;
++ unsigned short min;
++ unsigned short sec;
++ unsigned short msec;
+
-+ unsigned int cycle;
++ unsigned int cycle;
+
-+ unsigned long page;
-+ unsigned long offset;
-+ unsigned long length;
++ unsigned long page;
++ unsigned long offset;
++ unsigned long length;
+
-+ char page_status[4];
-+ char op;
++ char page_status[4];
++ char op;
+
-+ unsigned char data[CONFIG_HINFC610_DBG_NAND_LOG_LENGTH];
++ unsigned char data[CONFIG_HINFC610_DBG_NAND_LOG_LENGTH];
+};
+
+struct hinfc610_dbg_dump_t {
+
-+ struct dentry *dentry;
-+ unsigned int index; /* current logs index */
-+ int count; /* number of logs */
++ struct dentry *dentry;
++ unsigned int index; /* current logs index */
++ int count; /* number of logs */
+
-+ unsigned long offset;
-+ unsigned long length;
++ unsigned long offset;
++ unsigned long length;
+
-+ struct hinfc610_dbg_dump_item_t
-+ logs[CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS];
++ struct hinfc610_dbg_dump_item_t
++ logs[CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS];
+
-+ unsigned int read_index;
++ unsigned int read_index;
+};
+
+static DEFINE_MUTEX(dbg_dump_mutex);
@@ -294753,27 +362963,27 @@ index 0000000..395cfdd
+/*****************************************************************************/
+
+static void do_gettime(unsigned short *hour, unsigned short *min,
-+ unsigned short *sec, unsigned short *msec)
++ unsigned short *sec, unsigned short *msec)
+{
-+ long val;
-+ struct timeval tv;
++ long val;
++ struct timeval tv;
+
-+ do_gettimeofday(&tv);
-+ val = tv.tv_sec % 86400; /* the second form 0 hour */
++ do_gettimeofday(&tv);
++ val = tv.tv_sec % 86400; /* the second form 0 hour */
+
-+ if (hour) {
-+ *hour = val / 3600;
-+ }
-+ val %= 3600;
-+ if (min) {
-+ *min = val / 60;
-+ }
-+ if (sec) {
-+ *sec = val % 60;
-+ }
-+ if (msec) {
-+ *msec = tv.tv_usec / 1000;
-+ }
++ if (hour) {
++ *hour = val / 3600;
++ }
++ val %= 3600;
++ if (min) {
++ *min = val / 60;
++ }
++ if (sec) {
++ *sec = val % 60;
++ }
++ if (msec) {
++ *msec = tv.tv_usec / 1000;
++ }
+}
+/*****************************************************************************/
+/*
@@ -294786,381 +362996,381 @@ index 0000000..395cfdd
+*
+*/
+static ssize_t dbgfs_dump_read(struct file *filp, char __user *buffer,
-+ size_t count, loff_t *ppos)
++ size_t count, loff_t *ppos)
+{
-+ int len = 0;
-+ char buf[128] = {0};
-+ unsigned int read_index;
-+ char __user *pusrbuf = buffer;
-+ struct hinfc610_dbg_dump_item_t *logs;
++ int len = 0;
++ char buf[128] = {0};
++ unsigned int read_index;
++ char __user *pusrbuf = buffer;
++ struct hinfc610_dbg_dump_item_t *logs;
+
-+ if (*ppos == 0) {
++ if (*ppos == 0) {
+
-+ if (dbg_dump->count
-+ < CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
-+ dbg_dump->read_index = 0;
-+ } else
-+ dbg_dump->read_index
-+ = (dbg_dump->index + 1);
++ if (dbg_dump->count
++ < CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
++ dbg_dump->read_index = 0;
++ } else
++ dbg_dump->read_index
++ = (dbg_dump->index + 1);
+
-+ len = snprintf(buf, sizeof(buf),
-+ "Print parameter: \"offset=%ld length=%ld\"\n",
-+ dbg_dump->offset, dbg_dump->length);
++ len = snprintf(buf, sizeof(buf),
++ "Print parameter: \"offset=%lu length=%lu\"\n",
++ dbg_dump->offset, dbg_dump->length);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
+
-+ pusrbuf += len;
++ pusrbuf += len;
+
-+ len += snprintf(buf, sizeof(buf),
-+ " UTC Clock op cylce page-offset data\n");
++ len += snprintf(buf, sizeof(buf),
++ " UTC Clock op cylce page-offset data\n");
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
+
-+ pusrbuf += len;
++ pusrbuf += len;
+
-+ } else if (dbg_dump->read_index == dbg_dump->index) {
-+ return 0;
-+ }
++ } else if (dbg_dump->read_index == dbg_dump->index) {
++ return 0;
++ }
+
-+ for (read_index = dbg_dump->read_index;
-+ (read_index != dbg_dump->index);
-+ ++read_index) {
++ for (read_index = dbg_dump->read_index;
++ (read_index != dbg_dump->index);
++ ++read_index) {
+
-+ if (read_index >= CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
-+ read_index = 0;
-+ }
++ if (read_index >= CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
++ read_index = 0;
++ }
+
-+ logs = &dbg_dump->logs[read_index];
++ logs = &dbg_dump->logs[read_index];
+
-+ if ((count - (pusrbuf - buffer)) < (50 + logs->length * 3)) {
-+ break;
-+ }
++ if ((count - (pusrbuf - buffer)) < (50 + logs->length * 3)) {
++ break;
++ }
+
-+ len = snprintf(buf, sizeof(buf),
-+ "%02d:%02d:%02d.%04d %c %-2u 0x%08lX-%04lX",
-+ logs->hour, logs->min, logs->sec, logs->msec,
-+ logs->op, logs->cycle,
-+ logs->page, logs->offset);
++ len = snprintf(buf, sizeof(buf),
++ "%02d:%02d:%02d.%04d %c %-2u 0x%08lX-%04lX",
++ logs->hour, logs->min, logs->sec, logs->msec,
++ logs->op, logs->cycle,
++ logs->page, logs->offset);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
+
-+ pusrbuf += len;
++ pusrbuf += len;
+
-+ if (logs->op == 'E') {
++ if (logs->op == 'E') {
+
-+ len = snprintf(buf, sizeof(buf), " ---");
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
++ len = snprintf(buf, sizeof(buf), " ---");
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
+
-+ } else {
++ } else {
+
-+ int ix;
++ int ix;
+
-+ len = snprintf(buf, sizeof(buf), "%s",
-+ logs->page_status);
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
++ len = snprintf(buf, sizeof(buf), "%s",
++ logs->page_status);
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
+
-+ for (ix = 0; ix < logs->length; ix++) {
-+ if ((ix % 16) == 15) {
-+ len = snprintf(buf, sizeof(buf),
-+ "%02X-",
-+ logs->data[ix]);
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
-+ } else {
-+ len = snprintf(buf, sizeof(buf),
-+ "%02X ",
-+ logs->data[ix]);
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
-+ }
-+ }
-+ }
-+ len = snprintf(buf, sizeof(buf), "\n");
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
-+ }
++ for (ix = 0; ix < logs->length; ix++) {
++ if ((ix % 16) == 15) {
++ len = snprintf(buf, sizeof(buf),
++ "%02X-",
++ logs->data[ix]);
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
++ } else {
++ len = snprintf(buf, sizeof(buf),
++ "%02X ",
++ logs->data[ix]);
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
++ }
++ }
++ }
++ len = snprintf(buf, sizeof(buf), "\n");
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
++ }
+
-+ dbg_dump->read_index = read_index;
++ dbg_dump->read_index = read_index;
+
-+ *ppos += (pusrbuf - buffer);
-+ return pusrbuf - buffer;
++ *ppos += (pusrbuf - buffer);
++ return pusrbuf - buffer;
+}
+/*****************************************************************************/
+
+static ssize_t dbgfs_dump_write(struct file *filp, const char __user *buffer,
-+ size_t count, loff_t *ppos)
++ size_t count, loff_t *ppos)
+{
-+ char *p;
-+ int ret;
-+ unsigned long value = 0;
-+ char buf[128] = {0};
-+ unsigned long pos = 0;
++ char *p;
++ int ret;
++ unsigned long value = 0;
++ char buf[128] = {0};
++ unsigned long pos = 0;
+
-+ if (count > sizeof(buf)) {
-+ count = sizeof(buf);
-+ }
++ if (count > sizeof(buf)) {
++ count = sizeof(buf);
++ }
+
-+ if (copy_from_user(buf, buffer, count)) {
-+ return -EFAULT;
-+ }
++ if (copy_from_user(buf, buffer, count)) {
++ return -EFAULT;
++ }
+
-+ while (pos < count) {
++ while (pos < count) {
+
-+ while (pos < count
-+ && (buf[pos] == ' ' ||
-+ buf[pos] == ',' || buf[pos] == ';')) {
-+ pos++;
-+ }
++ while (pos < count
++ && (buf[pos] == ' ' ||
++ buf[pos] == ',' || buf[pos] == ';')) {
++ pos++;
++ }
+
-+ if (pos >= count) {
-+ break;
-+ }
++ if (pos >= count) {
++ break;
++ }
+
-+ switch (buf[pos]) {
-+ case 'o':
-+ if (!memcmp(&buf[pos], CMD_WORD_OFFSET,
-+ sizeof(CMD_WORD_OFFSET) - 1)) {
++ switch (buf[pos]) {
++ case 'o':
++ if (!memcmp(&buf[pos], CMD_WORD_OFFSET,
++ sizeof(CMD_WORD_OFFSET) - 1)) {
+
-+ pos += sizeof(CMD_WORD_OFFSET) - 1;
-+ p = (char *)(buf + pos);
-+ ret = kstrtoul(p, 10, &value);
-+ if (ret < 0) {
-+ value = 0;
-+ }
-+ dbg_dump->offset = value;
-+ }
-+ break;
++ pos += sizeof(CMD_WORD_OFFSET) - 1;
++ p = (char *)(buf + pos);
++ ret = kstrtoul(p, 10, &value);
++ if (ret < 0) {
++ value = 0;
++ }
++ dbg_dump->offset = value;
++ }
++ break;
+
-+ case 'l':
-+ if (!memcmp(&buf[pos], CMD_WORD_LENGTH,
-+ sizeof(CMD_WORD_LENGTH) - 1)) {
++ case 'l':
++ if (!memcmp(&buf[pos], CMD_WORD_LENGTH,
++ sizeof(CMD_WORD_LENGTH) - 1)) {
+
-+ pos += sizeof(CMD_WORD_LENGTH) - 1;
-+ p = (char *)(buf + pos);
-+ ret = kstrtoul(p, 10, &value);
-+ if (ret < 0) {
-+ value = 0;
-+ }
-+ dbg_dump->length = value;
-+ }
-+ break;
-+ }
++ pos += sizeof(CMD_WORD_LENGTH) - 1;
++ p = (char *)(buf + pos);
++ ret = kstrtoul(p, 10, &value);
++ if (ret < 0) {
++ value = 0;
++ }
++ dbg_dump->length = value;
++ }
++ break;
++ }
+
-+ while (pos < count &&
-+ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
-+ pos++;
-+ }
-+ }
++ while (pos < count &&
++ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
++ pos++;
++ }
++ }
+
-+ *ppos += count;
-+ return count;
++ *ppos += count;
++ return count;
+}
+/*****************************************************************************/
+
+static const struct file_operations dbgfs_dump_fops = {
-+ .owner = THIS_MODULE,
-+ .read = dbgfs_dump_read,
-+ .write = dbgfs_dump_write,
++ .owner = THIS_MODULE,
++ .read = dbgfs_dump_read,
++ .write = dbgfs_dump_write,
+};
+/*****************************************************************************/
+
+static int dbgfs_dump_init(struct dentry *root, struct hinfc_host *host)
+{
-+ struct hinfc610_dbg_dump_t *dump;
++ struct hinfc610_dbg_dump_t *dump;
+
-+ if (dbg_dump) {
-+ return 0;
-+ }
++ if (dbg_dump) {
++ return 0;
++ }
+
-+ dump = vmalloc(sizeof(struct hinfc610_dbg_dump_t));
-+ if (!dump) {
-+ PR_ERR("Can't allocate memory.\n");
-+ return -ENOMEM;
-+ }
-+ memset(dump, 0, sizeof(struct hinfc610_dbg_dump_t));
++ dump = vmalloc(sizeof(struct hinfc610_dbg_dump_t));
++ if (!dump) {
++ PR_ERR("Can't allocate memory.\n");
++ return -ENOMEM;
++ }
++ memset(dump, 0, sizeof(struct hinfc610_dbg_dump_t));
+
-+ dump->dentry = debugfs_create_file("dump",
-+ S_IFREG | S_IRUSR | S_IWUSR,
-+ root, NULL, &dbgfs_dump_fops);
-+ if (!dump->dentry) {
-+ PR_ERR("Can't create 'dump' file.\n");
-+ vfree(dump);
-+ return -ENOENT;
-+ }
++ dump->dentry = debugfs_create_file("dump",
++ S_IFREG | S_IRUSR | S_IWUSR,
++ root, NULL, &dbgfs_dump_fops);
++ if (!dump->dentry) {
++ PR_ERR("Can't create 'dump' file.\n");
++ vfree(dump);
++ return -ENOENT;
++ }
+
-+ dump->length = 8;
++ dump->length = 8;
+
-+ dbg_dump = dump;
++ dbg_dump = dump;
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int dbgfs_dump_uninit(void)
+{
-+ if (!dbg_dump) {
-+ return 0;
-+ }
++ if (!dbg_dump) {
++ return 0;
++ }
+
-+ mutex_lock(&dbg_dump_mutex);
++ mutex_lock(&dbg_dump_mutex);
+
-+ debugfs_remove(dbg_dump->dentry);
++ debugfs_remove(dbg_dump->dentry);
+
-+ vfree(dbg_dump);
-+ dbg_dump = NULL;
++ vfree(dbg_dump);
++ dbg_dump = NULL;
+
-+ mutex_unlock(&dbg_dump_mutex);
++ mutex_unlock(&dbg_dump_mutex);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static void dbg_dump_rw(struct hinfc_host *host, char op)
+{
-+ unsigned long buflen;
-+ struct hinfc610_dbg_dump_item_t *logs;
++ unsigned long buflen;
++ struct hinfc610_dbg_dump_item_t *logs;
+
-+ mutex_lock(&dbg_dump_mutex);
++ mutex_lock(&dbg_dump_mutex);
+
-+ if (!dbg_dump) {
-+ goto exit;
-+ }
++ if (!dbg_dump) {
++ goto exit;
++ }
+
-+ buflen = (host->pagesize + host->oobsize);
-+ logs = &dbg_dump->logs[dbg_dump->index];
++ buflen = (host->pagesize + host->oobsize);
++ logs = &dbg_dump->logs[dbg_dump->index];
+
-+ dbg_dump->count++;
++ dbg_dump->count++;
+
-+ do_gettime(&logs->hour, &logs->min, &logs->sec, &logs->msec);
++ do_gettime(&logs->hour, &logs->min, &logs->sec, &logs->msec);
+
-+ memcpy(logs->page_status, "\x20\x20\x20\x00", 4);
++ memcpy(logs->page_status, "\x20\x20\x20\x00", 4);
+
-+ if (host->page_status) {
-+ if (IS_PS_BAD_BLOCK(host)) {
-+ logs->page_status[0] = 'B';
-+ } else if (IS_PS_EMPTY_PAGE(host)) {
-+ logs->page_status[0] = 'E';
-+ }
++ if (host->page_status) {
++ if (IS_PS_BAD_BLOCK(host)) {
++ logs->page_status[0] = 'B';
++ } else if (IS_PS_EMPTY_PAGE(host)) {
++ logs->page_status[0] = 'E';
++ }
+
-+ if (IS_PS_UN_ECC(host)) {
-+ logs->page_status[1] = '*';
-+ }
++ if (IS_PS_UN_ECC(host)) {
++ logs->page_status[1] = '*';
++ }
+
-+ if (IS_PS_EPM_ERR(host) || IS_PS_BBM_ERR(host)) {
-+ logs->page_status[2] = '?';
-+ }
-+ }
++ if (IS_PS_EPM_ERR(host) || IS_PS_BBM_ERR(host)) {
++ logs->page_status[2] = '?';
++ }
++ }
+
-+ logs->op = op;
-+ logs->cycle = host->addr_cycle;
-+ logs->length = dbg_dump->length;
-+ logs->offset = (host->addr_value[0] & 0xFFFF);
-+ logs->page = GET_PAGE_INDEX(host);
++ logs->op = op;
++ logs->cycle = host->addr_cycle;
++ logs->length = dbg_dump->length;
++ logs->offset = (host->addr_value[0] & 0xFFFF);
++ logs->page = GET_PAGE_INDEX(host);
+
-+ if (!logs->offset) {
-+ logs->offset = dbg_dump->offset;
-+ }
++ if (!logs->offset) {
++ logs->offset = dbg_dump->offset;
++ }
+
-+ if (logs->offset >= buflen) {
-+ logs->offset = 0;
-+ }
++ if (logs->offset >= buflen) {
++ logs->offset = 0;
++ }
+
-+ if (logs->length > (buflen - logs->offset)) {
-+ logs->length = (buflen - logs->offset);
-+ }
++ if (logs->length > (buflen - logs->offset)) {
++ logs->length = (buflen - logs->offset);
++ }
+
-+ if (logs->length > CONFIG_HINFC610_DBG_NAND_LOG_LENGTH) {
-+ logs->length = CONFIG_HINFC610_DBG_NAND_LOG_LENGTH;
-+ }
++ if (logs->length > CONFIG_HINFC610_DBG_NAND_LOG_LENGTH) {
++ logs->length = CONFIG_HINFC610_DBG_NAND_LOG_LENGTH;
++ }
+
-+ memcpy(logs->data, (host->buffer + logs->offset), logs->length);
++ memcpy(logs->data, (host->buffer + logs->offset), logs->length);
+
-+ if (++dbg_dump->index >= CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
-+ dbg_dump->index = 0;
-+ }
++ if (++dbg_dump->index >= CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
++ dbg_dump->index = 0;
++ }
+
+exit:
-+ mutex_unlock(&dbg_dump_mutex);
++ mutex_unlock(&dbg_dump_mutex);
+}
+/*****************************************************************************/
+
+static void dbg_dump_read(struct hinfc_host *host)
+{
-+ dbg_dump_rw(host, 'R');
++ dbg_dump_rw(host, 'R');
+}
+/*****************************************************************************/
+
+static void dbg_dump_write(struct hinfc_host *host)
+{
-+ dbg_dump_rw(host, 'W');
++ dbg_dump_rw(host, 'W');
+}
+/*****************************************************************************/
+
+static void dbg_dump_erase(struct hinfc_host *host)
+{
-+ struct hinfc610_dbg_dump_item_t *logs;
++ struct hinfc610_dbg_dump_item_t *logs;
+
-+ mutex_lock(&dbg_dump_mutex);
++ mutex_lock(&dbg_dump_mutex);
+
-+ if (!dbg_dump) {
-+ goto exit;
-+ }
++ if (!dbg_dump) {
++ goto exit;
++ }
+
-+ dbg_dump->count++;
-+ logs = &dbg_dump->logs[dbg_dump->index];
++ dbg_dump->count++;
++ logs = &dbg_dump->logs[dbg_dump->index];
+
-+ do_gettime(&logs->hour, &logs->min, &logs->sec, &logs->msec);
++ do_gettime(&logs->hour, &logs->min, &logs->sec, &logs->msec);
+
-+ memcpy(logs->page_status, "\x20\x20\x20\x00", 4);
++ memcpy(logs->page_status, "\x20\x20\x20\x00", 4);
+
-+ logs->op = 'E';
-+ logs->cycle = host->addr_cycle;
-+ logs->length = dbg_dump->length;
++ logs->op = 'E';
++ logs->cycle = host->addr_cycle;
++ logs->length = dbg_dump->length;
+
-+ logs->offset = 0;
-+ logs->page = host->addr_value[0];
-+ logs->length = 0;
++ logs->offset = 0;
++ logs->page = host->addr_value[0];
++ logs->length = 0;
+
-+ if (++dbg_dump->index >= CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
-+ dbg_dump->index = 0;
-+ }
++ if (++dbg_dump->index >= CONFIG_HINFC610_DBG_NAND_NUM_OF_LOGS) {
++ dbg_dump->index = 0;
++ }
+
+exit:
-+ mutex_unlock(&dbg_dump_mutex);
++ mutex_unlock(&dbg_dump_mutex);
+}
+/*****************************************************************************/
+
+struct hinfc610_dbg_inf_t hinfc610_dbg_inf_dump = {
-+ "dump", 0,
-+ dbgfs_dump_init,
-+ dbgfs_dump_uninit,
-+ dbg_dump_read,
-+ dbg_dump_write,
-+ dbg_dump_erase,
-+ NULL,
++ "dump", 0,
++ dbgfs_dump_init,
++ dbgfs_dump_uninit,
++ dbg_dump_read,
++ dbg_dump_write,
++ dbg_dump_erase,
++ NULL,
+};
+/*****************************************************************************/
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg_ecc_count.c b/drivers/mtd/nand/hinfc610/hinfc610_dbg_ecc_count.c
new file mode 100644
-index 0000000..c51a705
+index 0000000..715bed4
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg_ecc_count.c
@@ -0,0 +1,433 @@
@@ -295200,30 +363410,30 @@ index 0000000..c51a705
+#endif /* CONFIG_HINFC610_DBG_ECC_COUNT_NUM */
+
+struct hinfc610_dbg_ecc_count_item_t {
-+ unsigned int page;
-+ unsigned int page_status; /* the same as host->page_status */
-+ unsigned short hour;
-+ unsigned short min;
-+ unsigned short sec;
-+ unsigned short msec;
++ unsigned int page;
++ unsigned int page_status; /* the same as host->page_status */
++ unsigned short hour;
++ unsigned short min;
++ unsigned short sec;
++ unsigned short msec;
+
-+ unsigned char ecc[4];
++ unsigned char ecc[4];
+};
+
+struct hinfc610_dbg_ecc_count_t {
+
-+ struct dentry *dentry;
-+ unsigned int index; /* current logs index */
-+ int count; /* number of logs */
++ struct dentry *dentry;
++ unsigned int index; /* current logs index */
++ int count; /* number of logs */
+
-+ struct hinfc610_ecc_inf_t *ecc_inf;
-+ unsigned int offset;
-+ unsigned int length;
-+ unsigned int pagecount;
++ struct hinfc610_ecc_inf_t *ecc_inf;
++ unsigned int offset;
++ unsigned int length;
++ unsigned int pagecount;
+
-+ unsigned char *item;
++ unsigned char *item;
+
-+ unsigned int read_index;
++ unsigned int read_index;
+};
+
+#define GET_ITEM(_ecc_count, _index) \
@@ -295236,143 +363446,143 @@ index 0000000..c51a705
+/*****************************************************************************/
+
+static void do_gettime(unsigned short *hour, unsigned short *min,
-+ unsigned short *sec, unsigned short *msec)
++ unsigned short *sec, unsigned short *msec)
+{
-+ long val;
-+ struct timeval tv;
++ long val;
++ struct timeval tv;
+
-+ do_gettimeofday(&tv);
-+ val = tv.tv_sec % 86400; /* the second form 0 hour */
++ do_gettimeofday(&tv);
++ val = tv.tv_sec % 86400; /* the second form 0 hour */
+
-+ if (hour) {
-+ *hour = val / 3600;
-+ }
-+ val %= 3600;
-+ if (min) {
-+ *min = val / 60;
-+ }
-+ if (sec) {
-+ *sec = val % 60;
-+ }
-+ if (msec) {
-+ *msec = tv.tv_usec / 1000;
-+ }
++ if (hour) {
++ *hour = val / 3600;
++ }
++ val %= 3600;
++ if (min) {
++ *min = val / 60;
++ }
++ if (sec) {
++ *sec = val % 60;
++ }
++ if (msec) {
++ *msec = tv.tv_usec / 1000;
++ }
+}
+/*****************************************************************************/
+
+static ssize_t dbgfs_ecc_count_read(struct file *filp, char __user *buffer,
-+ size_t count, loff_t *ppos)
++ size_t count, loff_t *ppos)
+{
-+ int len = 0;
-+ char buf[128] = {0};
-+ unsigned int read_index;
-+ char __user *pusrbuf = buffer;
-+ struct hinfc610_dbg_ecc_count_item_t *item;
++ int len = 0;
++ char buf[128] = {0};
++ unsigned int read_index;
++ char __user *pusrbuf = buffer;
++ struct hinfc610_dbg_ecc_count_item_t *item;
+
-+ if (*ppos == 0) {
++ if (*ppos == 0) {
+
-+ if (dbg_ecc_count->count
-+ < CONFIG_HINFC610_DBG_ECC_COUNT_NUM) {
-+ dbg_ecc_count->read_index = 0;
-+ } else
-+ dbg_ecc_count->read_index
-+ = (dbg_ecc_count->index + 1);
++ if (dbg_ecc_count->count
++ < CONFIG_HINFC610_DBG_ECC_COUNT_NUM) {
++ dbg_ecc_count->read_index = 0;
++ } else
++ dbg_ecc_count->read_index
++ = (dbg_ecc_count->index + 1);
+
-+ len = snprintf(buf, sizeof(buf),
-+ "Print parameter: \"offset=%d length=%d\"\n",
-+ dbg_ecc_count->offset,
-+ dbg_ecc_count->length);
++ len = snprintf(buf, sizeof(buf),
++ "Print parameter: \"offset=%u length=%u\"\n",
++ dbg_ecc_count->offset,
++ dbg_ecc_count->length);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
+
-+ pusrbuf += len;
++ pusrbuf += len;
+
-+ len = snprintf(buf, sizeof(buf),
-+ " UTC Clock page ecc data\n");
++ len = snprintf(buf, sizeof(buf),
++ " UTC Clock page ecc data\n");
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
+
-+ pusrbuf += len;
++ pusrbuf += len;
+
-+ } else if (dbg_ecc_count->read_index == dbg_ecc_count->index) {
-+ return 0;
-+ }
++ } else if (dbg_ecc_count->read_index == dbg_ecc_count->index) {
++ return 0;
++ }
+
-+ for (read_index = dbg_ecc_count->read_index;
-+ (read_index != dbg_ecc_count->index); ++read_index) {
++ for (read_index = dbg_ecc_count->read_index;
++ (read_index != dbg_ecc_count->index); ++read_index) {
+
-+ if (read_index >= CONFIG_HINFC610_DBG_ECC_COUNT_NUM) {
-+ read_index = 0;
-+ }
++ if (read_index >= CONFIG_HINFC610_DBG_ECC_COUNT_NUM) {
++ read_index = 0;
++ }
+
-+ item = GET_ITEM(dbg_ecc_count, read_index);
++ item = GET_ITEM(dbg_ecc_count, read_index);
+
-+ if ((count - (pusrbuf - buffer)) < 80) {
-+ break;
-+ }
++ if ((count - (pusrbuf - buffer)) < 80) {
++ break;
++ }
+
-+ len = snprintf(buf, sizeof(buf),
-+ "%02d:%02d:%02d.%04d 0x%08X ",
-+ item->hour, item->min, item->sec, item->msec,
-+ item->page);
++ len = snprintf(buf, sizeof(buf),
++ "%02d:%02d:%02d.%04d 0x%08X ",
++ item->hour, item->min, item->sec, item->msec,
++ item->page);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
+
-+ pusrbuf += len;
++ pusrbuf += len;
+
-+ if (IS_PS_BAD_BLOCK(item) || IS_PS_EMPTY_PAGE(item) ||
-+ IS_PS_UN_ECC(item)) {
-+ char *ptr = buf;
++ if (IS_PS_BAD_BLOCK(item) || IS_PS_EMPTY_PAGE(item) ||
++ IS_PS_UN_ECC(item)) {
++ char *ptr = buf;
+
-+ if (IS_PS_BAD_BLOCK(item)) {
-+ ptr += snprintf(ptr, 16, "bb ");
-+ } else if (IS_PS_EMPTY_PAGE(item)) {
-+ ptr += snprintf(ptr, 16, "ep ");
-+ }
++ if (IS_PS_BAD_BLOCK(item)) {
++ ptr += snprintf(ptr, 16, "bb ");
++ } else if (IS_PS_EMPTY_PAGE(item)) {
++ ptr += snprintf(ptr, 16, "ep ");
++ }
+
-+ if (IS_PS_UN_ECC(item)) {
-+ ptr += snprintf(ptr, 16, "ecc ");
-+ }
++ if (IS_PS_UN_ECC(item)) {
++ ptr += snprintf(ptr, 16, "ecc ");
++ }
+
-+ if (IS_PS_EPM_ERR(item) || IS_PS_BBM_ERR(item)) {
-+ ptr += snprintf(ptr, 16, "? ");
-+ }
++ if (IS_PS_EPM_ERR(item) || IS_PS_BBM_ERR(item)) {
++ ptr += snprintf(ptr, 16, "? ");
++ }
+
-+ ptr += snprintf(ptr, 16, "\n");
-+ len = (ptr - buf);
++ ptr += snprintf(ptr, 16, "\n");
++ len = (ptr - buf);
+
-+ } else {
-+ int ix;
-+ char *ptr = buf;
++ } else {
++ int ix;
++ char *ptr = buf;
+
-+ for (ix = 0; ix < dbg_ecc_count->ecc_inf->section; ix++) {
-+ ptr += snprintf(ptr, 16, "%d/", item->ecc[ix]);
-+ }
++ for (ix = 0; ix < dbg_ecc_count->ecc_inf->section; ix++) {
++ ptr += snprintf(ptr, 16, "%d/", item->ecc[ix]);
++ }
+
-+ if (IS_PS_EPM_ERR(item)) {
-+ ptr += snprintf(ptr, 16, " ?");
-+ }
++ if (IS_PS_EPM_ERR(item)) {
++ ptr += snprintf(ptr, 16, " ?");
++ }
+
-+ ptr += snprintf(ptr, 16, "\n");
-+ len = (ptr - buf);
-+ }
++ ptr += snprintf(ptr, 16, "\n");
++ len = (ptr - buf);
++ }
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
++ }
+
-+ dbg_ecc_count->read_index = read_index;
++ dbg_ecc_count->read_index = read_index;
+
-+ *ppos += (pusrbuf - buffer);
-+ return pusrbuf - buffer;
++ *ppos += (pusrbuf - buffer);
++ return pusrbuf - buffer;
+}
+/******************************************************************************/
+/*
@@ -295380,226 +363590,226 @@ index 0000000..c51a705
+ *
+ */
+static ssize_t dbgfs_ecc_count_write(struct file *filp,
-+ const char __user *buffer, size_t count,
-+ loff_t *ppos)
++ const char __user *buffer, size_t count,
++ loff_t *ppos)
+{
-+ char *str;
-+ char buf[128] = {0};
-+ int ret;
-+ unsigned long value = 0;
-+ unsigned long pos = 0;
++ char *str;
++ char buf[128] = {0};
++ int ret;
++ unsigned long value = 0;
++ unsigned long pos = 0;
+
-+ if (count > sizeof(buf)) {
-+ count = sizeof(buf);
-+ }
++ if (count > sizeof(buf)) {
++ count = sizeof(buf);
++ }
+
-+ if (copy_from_user(buf, buffer, count)) {
-+ return -EFAULT;
-+ }
++ if (copy_from_user(buf, buffer, count)) {
++ return -EFAULT;
++ }
+
-+ while (pos < count) {
-+ while (pos < count &&
-+ (buf[pos] == ' ' || buf[pos] == ',' || buf[pos] == ';')) {
-+ pos++;
-+ }
++ while (pos < count) {
++ while (pos < count &&
++ (buf[pos] == ' ' || buf[pos] == ',' || buf[pos] == ';')) {
++ pos++;
++ }
+
-+ if (pos >= count) {
-+ break;
-+ }
++ if (pos >= count) {
++ break;
++ }
+
-+ switch (buf[pos]) {
++ switch (buf[pos]) {
+
-+ case 'o':
++ case 'o':
+
-+ if (memcmp(&buf[pos], CMD_WORD_OFFSET,
-+ sizeof(CMD_WORD_OFFSET) - 1)) {
-+ break;
-+ }
++ if (memcmp(&buf[pos], CMD_WORD_OFFSET,
++ sizeof(CMD_WORD_OFFSET) - 1)) {
++ break;
++ }
+
-+ pos += sizeof(CMD_WORD_OFFSET) - 1;
-+ str = (char *)(buf + pos);
-+ ret = kstrtoul(str, 10, &value);
++ pos += sizeof(CMD_WORD_OFFSET) - 1;
++ str = (char *)(buf + pos);
++ ret = kstrtoul(str, 10, &value);
+
-+ if (ret < 0) {
-+ value = 0;
-+ }
-+ if (value >= dbg_ecc_count->pagecount) {
-+ value = 0;
-+ }
++ if (ret < 0) {
++ value = 0;
++ }
++ if (value >= dbg_ecc_count->pagecount) {
++ value = 0;
++ }
+
-+ dbg_ecc_count->offset = (value & ~7);
++ dbg_ecc_count->offset = (value & ~7);
+
-+ break;
++ break;
+
-+ case 'l':
-+ if (memcmp(&buf[pos], CMD_WORD_LENGTH,
-+ sizeof(CMD_WORD_LENGTH) - 1)) {
-+ break;
-+ }
++ case 'l':
++ if (memcmp(&buf[pos], CMD_WORD_LENGTH,
++ sizeof(CMD_WORD_LENGTH) - 1)) {
++ break;
++ }
+
-+ pos += sizeof(CMD_WORD_LENGTH) - 1;
-+ str = (char *)(buf + pos);
-+ ret = kstrtoul(str, 10, &value);
++ pos += sizeof(CMD_WORD_LENGTH) - 1;
++ str = (char *)(buf + pos);
++ ret = kstrtoul(str, 10, &value);
+
-+ if (ret < 0) {
-+ value = dbg_ecc_count->pagecount;
-+ }
++ if (ret < 0) {
++ value = dbg_ecc_count->pagecount;
++ }
+
-+ value = ((value + 7) & ~7);
++ value = ((value + 7) & ~7);
+
-+ if (dbg_ecc_count->offset + value >
-+ dbg_ecc_count->pagecount) {
-+ value = dbg_ecc_count->pagecount
-+ - dbg_ecc_count->offset;
-+ }
-+ dbg_ecc_count->length = value;
++ if (dbg_ecc_count->offset + value >
++ dbg_ecc_count->pagecount) {
++ value = dbg_ecc_count->pagecount
++ - dbg_ecc_count->offset;
++ }
++ dbg_ecc_count->length = value;
+
-+ break;
-+ }
++ break;
++ }
+
-+ while (pos < count &&
-+ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
-+ pos++;
-+ }
-+ }
++ while (pos < count &&
++ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
++ pos++;
++ }
++ }
+
-+ return count;
++ return count;
+}
+/******************************************************************************/
+
+static const struct file_operations dbgfs_ecc_count_fops = {
-+ .owner = THIS_MODULE,
-+ .read = dbgfs_ecc_count_read,
-+ .write = dbgfs_ecc_count_write,
++ .owner = THIS_MODULE,
++ .read = dbgfs_ecc_count_read,
++ .write = dbgfs_ecc_count_write,
+};
+/*****************************************************************************/
+
+static int dbgfs_ecc_count_init(struct dentry *root, struct hinfc_host *host)
+{
-+ unsigned int size;
-+ unsigned int pagesize;
-+ unsigned int chipsize;
-+ struct hinfc610_ecc_inf_t *ecc_inf;
-+ struct hinfc610_dbg_ecc_count_t *ecc_count;
++ unsigned int size;
++ unsigned int pagesize;
++ unsigned int chipsize;
++ struct hinfc610_ecc_inf_t *ecc_inf;
++ struct hinfc610_dbg_ecc_count_t *ecc_count;
+
-+ if (dbg_ecc_count) {
-+ return 0;
-+ }
++ if (dbg_ecc_count) {
++ return 0;
++ }
+
-+ ecc_inf = hinfc610_get_ecc_inf(host, host->pagesize, host->ecctype);
-+ if (!ecc_inf) {
-+ pr_warn("ecc_count: The NAND not support this interface.\n");
-+ return -1;
-+ }
++ ecc_inf = hinfc610_get_ecc_inf(host, host->pagesize, host->ecctype);
++ if (!ecc_inf) {
++ pr_warn("ecc_count: The NAND not support this interface.\n");
++ return -1;
++ }
+
-+ size = sizeof(struct hinfc610_dbg_ecc_count_t);
-+ size += CONFIG_HINFC610_DBG_ECC_COUNT_NUM *
-+ (sizeof(struct hinfc610_dbg_ecc_count_item_t)
-+ + ecc_inf->section);
++ size = sizeof(struct hinfc610_dbg_ecc_count_t);
++ size += CONFIG_HINFC610_DBG_ECC_COUNT_NUM *
++ (sizeof(struct hinfc610_dbg_ecc_count_item_t)
++ + ecc_inf->section);
+
-+ ecc_count = vmalloc(size);
-+ if (!ecc_count) {
-+ PR_ERR("Can't allocate memory.\n");
-+ return -ENOMEM;
-+ }
-+ memset(ecc_count, 0, size);
++ ecc_count = vmalloc(size);
++ if (!ecc_count) {
++ PR_ERR("Can't allocate memory.\n");
++ return -ENOMEM;
++ }
++ memset(ecc_count, 0, size);
+
-+ ecc_count->item = (char *)ecc_count +
-+ sizeof(struct hinfc610_dbg_ecc_count_t);
-+ ecc_count->ecc_inf = ecc_inf;
++ ecc_count->item = (char *)ecc_count +
++ sizeof(struct hinfc610_dbg_ecc_count_t);
++ ecc_count->ecc_inf = ecc_inf;
+
-+ pagesize = (host->pagesize >> 10);
-+ chipsize = (unsigned int)(host->chip->chipsize >> 10);
-+ ecc_count->pagecount = (chipsize / pagesize);
-+ ecc_count->length = ecc_count->pagecount;
++ pagesize = (host->pagesize >> 10);
++ chipsize = (unsigned int)(host->chip->chipsize >> 10);
++ ecc_count->pagecount = (chipsize / pagesize);
++ ecc_count->length = ecc_count->pagecount;
+
-+ ecc_count->dentry = debugfs_create_file("ecc_count",
-+ S_IFREG | S_IRUSR | S_IWUSR,
-+ root, NULL, &dbgfs_ecc_count_fops);
-+ if (!ecc_count->dentry) {
-+ PR_ERR("Can't create 'ecc_count' file.\n");
-+ vfree(ecc_count);
-+ return -ENOENT;
-+ }
++ ecc_count->dentry = debugfs_create_file("ecc_count",
++ S_IFREG | S_IRUSR | S_IWUSR,
++ root, NULL, &dbgfs_ecc_count_fops);
++ if (!ecc_count->dentry) {
++ PR_ERR("Can't create 'ecc_count' file.\n");
++ vfree(ecc_count);
++ return -ENOENT;
++ }
+
-+ dbg_ecc_count = ecc_count;
++ dbg_ecc_count = ecc_count;
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int dbgfs_ecc_count_uninit(void)
+{
-+ if (!dbg_ecc_count) {
-+ return 0;
-+ }
++ if (!dbg_ecc_count) {
++ return 0;
++ }
+
-+ mutex_lock(&dbg_ecc_count_mutex);
++ mutex_lock(&dbg_ecc_count_mutex);
+
-+ debugfs_remove(dbg_ecc_count->dentry);
++ debugfs_remove(dbg_ecc_count->dentry);
+
-+ vfree(dbg_ecc_count);
-+ dbg_ecc_count = NULL;
++ vfree(dbg_ecc_count);
++ dbg_ecc_count = NULL;
+
-+ mutex_unlock(&dbg_ecc_count_mutex);
++ mutex_unlock(&dbg_ecc_count_mutex);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static void dbg_ecc_count_read(struct hinfc_host *host)
+{
-+ unsigned int page;
-+ struct hinfc610_dbg_ecc_count_item_t *item;
++ unsigned int page;
++ struct hinfc610_dbg_ecc_count_item_t *item;
+
-+ mutex_lock(&dbg_ecc_count_mutex);
++ mutex_lock(&dbg_ecc_count_mutex);
+
-+ if (!dbg_ecc_count) {
-+ goto exit;
-+ }
++ if (!dbg_ecc_count) {
++ goto exit;
++ }
+
-+ page = GET_PAGE_INDEX(host);
++ page = GET_PAGE_INDEX(host);
+
-+ if (page < dbg_ecc_count->offset ||
-+ page > (dbg_ecc_count->offset + dbg_ecc_count->length)) {
-+ goto exit;
-+ }
++ if (page < dbg_ecc_count->offset ||
++ page > (dbg_ecc_count->offset + dbg_ecc_count->length)) {
++ goto exit;
++ }
+
-+ item = GET_ITEM(dbg_ecc_count, dbg_ecc_count->index);
++ item = GET_ITEM(dbg_ecc_count, dbg_ecc_count->index);
+
-+ dbg_ecc_count->count++;
++ dbg_ecc_count->count++;
+
-+ do_gettime(&item->hour, &item->min, &item->sec, &item->msec);
++ do_gettime(&item->hour, &item->min, &item->sec, &item->msec);
+
-+ item->page = page;
-+ item->page_status = host->page_status;
++ item->page = page;
++ item->page_status = host->page_status;
+
-+ if (!IS_PS_UN_ECC(host)) {
-+ dbg_ecc_count->ecc_inf->ecc_inf(host, item->ecc);
-+ }
++ if (!IS_PS_UN_ECC(host)) {
++ dbg_ecc_count->ecc_inf->ecc_inf(host, item->ecc);
++ }
+
-+ if (++dbg_ecc_count->index >= CONFIG_HINFC610_DBG_ECC_COUNT_NUM) {
-+ dbg_ecc_count->index = 0;
-+ }
++ if (++dbg_ecc_count->index >= CONFIG_HINFC610_DBG_ECC_COUNT_NUM) {
++ dbg_ecc_count->index = 0;
++ }
+
+exit:
-+ mutex_unlock(&dbg_ecc_count_mutex);
++ mutex_unlock(&dbg_ecc_count_mutex);
+}
+/*****************************************************************************/
+
+struct hinfc610_dbg_inf_t hinfc610_dbg_inf_ecc_count = {
-+ "ecc_count", 0,
-+ dbgfs_ecc_count_init,
-+ dbgfs_ecc_count_uninit,
-+ dbg_ecc_count_read,
-+ NULL,
-+ NULL,
-+ NULL,
++ "ecc_count", 0,
++ dbgfs_ecc_count_init,
++ dbgfs_ecc_count_uninit,
++ dbg_ecc_count_read,
++ NULL,
++ NULL,
++ NULL,
+};
+/*****************************************************************************/
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg_ecc_dump.c b/drivers/mtd/nand/hinfc610/hinfc610_dbg_ecc_dump.c
new file mode 100644
-index 0000000..bec153b
+index 0000000..aeaf56a
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg_ecc_dump.c
@@ -0,0 +1,146 @@
@@ -295635,123 +363845,123 @@ index 0000000..bec153b
+
+/*****************************************************************************/
+static inline void hinfc610_detect_ecc(unsigned char ecc[], int begin,
-+ int end, unsigned int reg)
++ int end, unsigned int reg)
+{
-+ while (begin < end) {
-+ ecc[begin] = (reg & 0xff);
-+ reg = (reg >> 8);
-+ begin++;
-+ }
++ while (begin < end) {
++ ecc[begin] = (reg & 0xff);
++ reg = (reg >> 8);
++ begin++;
++ }
+}
+/*****************************************************************************/
+
+static void hinfc610_ecc_32k(struct hinfc_host *host, unsigned char ecc[])
+{
-+ int ix, jx, kx;
++ int ix, jx, kx;
+
-+ for (ix = 0, jx = 0; ix < 4; ix ++, jx += 4) {
-+ hinfc610_detect_ecc(ecc, jx, jx + 4,
-+ hinfc_read(host, 0xA0 + jx));
-+ }
-+ kx = jx;
-+ for (ix = 0, jx = 0; ix < 4; ix ++, jx += 4) {
-+ hinfc610_detect_ecc(ecc, kx, kx + 4,
-+ hinfc_read(host, 0xDC + jx));
-+ }
++ for (ix = 0, jx = 0; ix < 4; ix ++, jx += 4) {
++ hinfc610_detect_ecc(ecc, jx, jx + 4,
++ hinfc_read(host, 0xA0 + jx));
++ }
++ kx = jx;
++ for (ix = 0, jx = 0; ix < 4; ix ++, jx += 4) {
++ hinfc610_detect_ecc(ecc, kx, kx + 4,
++ hinfc_read(host, 0xDC + jx));
++ }
+}
+/*****************************************************************************/
+
+static void hinfc610_ecc_16k(struct hinfc_host *host, unsigned char ecc[])
+{
-+ int ix, jx;
++ int ix, jx;
+
-+ for (ix = 0, jx = 0; ix < 4; ix ++, jx += 4) {
-+ hinfc610_detect_ecc(ecc, jx, jx + 4,
-+ hinfc_read(host, 0xA0 + jx));
-+ }
++ for (ix = 0, jx = 0; ix < 4; ix ++, jx += 4) {
++ hinfc610_detect_ecc(ecc, jx, jx + 4,
++ hinfc_read(host, 0xA0 + jx));
++ }
+}
+/*****************************************************************************/
+
+static void hinfc610_ecc_8k(struct hinfc_host *host, unsigned char ecc[])
+{
-+ int ix, jx;
++ int ix, jx;
+
-+ for (ix = 0, jx = 0; ix < 2; ix ++, jx += 4)
-+ hinfc610_detect_ecc(ecc, jx, jx + 4,
-+ hinfc_read(host, 0xA0 + jx));
++ for (ix = 0, jx = 0; ix < 2; ix ++, jx += 4)
++ hinfc610_detect_ecc(ecc, jx, jx + 4,
++ hinfc_read(host, 0xA0 + jx));
+}
+/*****************************************************************************/
+
+static void hinfc610_ecc_4k(struct hinfc_host *host, unsigned char ecc[])
+{
-+ hinfc610_detect_ecc(ecc, 0, 4, hinfc_read(host, 0xA0));
++ hinfc610_detect_ecc(ecc, 0, 4, hinfc_read(host, 0xA0));
+}
+/*****************************************************************************/
+
+static void hinfc610_ecc_2k(struct hinfc_host *host, unsigned char ecc[])
+{
-+ hinfc610_detect_ecc(ecc, 0, 2, hinfc_read(host, 0xA0));
++ hinfc610_detect_ecc(ecc, 0, 2, hinfc_read(host, 0xA0));
+}
+/*****************************************************************************/
+
+static struct hinfc610_ecc_inf_t hinfc610_ecc_inf[] = {
+
-+ {32768, NAND_ECC_80BIT, 32, hinfc610_ecc_32k},
-+ {32768, NAND_ECC_72BIT, 32, hinfc610_ecc_32k},
-+ {32768, NAND_ECC_60BIT, 32, hinfc610_ecc_32k},
-+ {32768, NAND_ECC_48BIT, 32, hinfc610_ecc_32k},
-+ {32768, NAND_ECC_41BIT, 32, hinfc610_ecc_32k},
++ {32768, NAND_ECC_80BIT, 32, hinfc610_ecc_32k},
++ {32768, NAND_ECC_72BIT, 32, hinfc610_ecc_32k},
++ {32768, NAND_ECC_60BIT, 32, hinfc610_ecc_32k},
++ {32768, NAND_ECC_48BIT, 32, hinfc610_ecc_32k},
++ {32768, NAND_ECC_41BIT, 32, hinfc610_ecc_32k},
+
-+ {16384, NAND_ECC_80BIT, 16, hinfc610_ecc_16k},
-+ {16384, NAND_ECC_72BIT, 16, hinfc610_ecc_16k},
-+ {16384, NAND_ECC_60BIT, 16, hinfc610_ecc_16k},
-+ {16384, NAND_ECC_48BIT, 16, hinfc610_ecc_16k},
-+ {16384, NAND_ECC_41BIT, 16, hinfc610_ecc_16k},
++ {16384, NAND_ECC_80BIT, 16, hinfc610_ecc_16k},
++ {16384, NAND_ECC_72BIT, 16, hinfc610_ecc_16k},
++ {16384, NAND_ECC_60BIT, 16, hinfc610_ecc_16k},
++ {16384, NAND_ECC_48BIT, 16, hinfc610_ecc_16k},
++ {16384, NAND_ECC_41BIT, 16, hinfc610_ecc_16k},
+
-+ {8192, NAND_ECC_80BIT, 8, hinfc610_ecc_8k},
-+ {8192, NAND_ECC_72BIT, 8, hinfc610_ecc_8k},
-+ {8192, NAND_ECC_60BIT, 8, hinfc610_ecc_8k},
-+ {8192, NAND_ECC_48BIT, 8, hinfc610_ecc_8k},
-+ {8192, NAND_ECC_41BIT, 8, hinfc610_ecc_8k},
-+ {8192, NAND_ECC_32BIT, 8, hinfc610_ecc_8k},
-+ {8192, NAND_ECC_27BIT, 8, hinfc610_ecc_8k},
-+ {8192, NAND_ECC_24BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_80BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_72BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_60BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_48BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_41BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_32BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_27BIT, 8, hinfc610_ecc_8k},
++ {8192, NAND_ECC_24BIT, 8, hinfc610_ecc_8k},
+
+
+
-+ {4096, NAND_ECC_32BIT, 4, hinfc610_ecc_4k},
-+ {4096, NAND_ECC_27BIT, 4, hinfc610_ecc_4k},
-+ {4096, NAND_ECC_24BIT, 4, hinfc610_ecc_4k},
-+ {4096, NAND_ECC_18BIT, 4, hinfc610_ecc_4k},
-+ {4096, NAND_ECC_13BIT, 4, hinfc610_ecc_4k},
-+ {4096, NAND_ECC_8BIT, 4, hinfc610_ecc_4k},
++ {4096, NAND_ECC_32BIT, 4, hinfc610_ecc_4k},
++ {4096, NAND_ECC_27BIT, 4, hinfc610_ecc_4k},
++ {4096, NAND_ECC_24BIT, 4, hinfc610_ecc_4k},
++ {4096, NAND_ECC_18BIT, 4, hinfc610_ecc_4k},
++ {4096, NAND_ECC_13BIT, 4, hinfc610_ecc_4k},
++ {4096, NAND_ECC_8BIT, 4, hinfc610_ecc_4k},
+
-+ {2048, NAND_ECC_32BIT, 2, hinfc610_ecc_2k},
-+ {2048, NAND_ECC_27BIT, 2, hinfc610_ecc_2k},
-+ {2048, NAND_ECC_24BIT, 2, hinfc610_ecc_2k},
-+ {2048, NAND_ECC_18BIT, 2, hinfc610_ecc_2k},
-+ {2048, NAND_ECC_13BIT, 2, hinfc610_ecc_2k},
-+ {2048, NAND_ECC_8BIT, 2, hinfc610_ecc_2k},
-+ {0, 0, 0},
++ {2048, NAND_ECC_32BIT, 2, hinfc610_ecc_2k},
++ {2048, NAND_ECC_27BIT, 2, hinfc610_ecc_2k},
++ {2048, NAND_ECC_24BIT, 2, hinfc610_ecc_2k},
++ {2048, NAND_ECC_18BIT, 2, hinfc610_ecc_2k},
++ {2048, NAND_ECC_13BIT, 2, hinfc610_ecc_2k},
++ {2048, NAND_ECC_8BIT, 2, hinfc610_ecc_2k},
++ {0, 0, 0},
+};
+/*****************************************************************************/
+
+struct hinfc610_ecc_inf_t *hinfc610_get_ecc_inf(struct hinfc_host *host,
-+ int pagesize, int ecctype)
++ int pagesize, int ecctype)
+{
-+ struct hinfc610_ecc_inf_t *inf;
++ struct hinfc610_ecc_inf_t *inf;
+
-+ for (inf = hinfc610_ecc_inf; inf->pagesize; inf++) {
-+ if (inf->pagesize == pagesize && inf->ecctype == ecctype) {
-+ return inf;
-+ }
-+ }
++ for (inf = hinfc610_ecc_inf; inf->pagesize; inf++) {
++ if (inf->pagesize == pagesize && inf->ecctype == ecctype) {
++ return inf;
++ }
++ }
+
-+ return NULL;
++ return NULL;
+}
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg_erase_count.c b/drivers/mtd/nand/hinfc610/hinfc610_dbg_erase_count.c
new file mode 100644
-index 0000000..26c51b0
+index 0000000..5b31945
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg_erase_count.c
@@ -0,0 +1,334 @@
@@ -295788,16 +363998,16 @@ index 0000000..26c51b0
+
+struct hinfc610_dbg_erase_count_t {
+
-+ unsigned int index; /* display pos */
-+ unsigned int offset; /* display offset */
-+ unsigned int length; /* display length */
++ unsigned int index; /* display pos */
++ unsigned int offset; /* display offset */
++ unsigned int length; /* display length */
+
-+ struct dentry *dentry;
++ struct dentry *dentry;
+
-+ unsigned int blocknum;
-+ unsigned int page_per_block;
++ unsigned int blocknum;
++ unsigned int page_per_block;
+
-+ unsigned int pe[1];
++ unsigned int pe[1];
+};
+
+static DEFINE_MUTEX(dbg_erase_count_mutex);
@@ -295806,62 +364016,62 @@ index 0000000..26c51b0
+/*****************************************************************************/
+
+static int dbgfs_erase_count_read(struct file *filp, char __user *buffer,
-+ size_t count, loff_t *ppos)
++ size_t count, loff_t *ppos)
+{
-+ int len = 0;
-+ int value = 0;
-+ unsigned int *pe;
-+ unsigned int index;
-+ char buf[128] = {0};
-+ char __user *pusrbuf = buffer;
++ int len = 0;
++ int value = 0;
++ unsigned int *pe;
++ unsigned int index;
++ char buf[128] = {0};
++ char __user *pusrbuf = buffer;
+
-+ if (*ppos == 0) {
-+ dbg_erase_count->index = dbg_erase_count->offset;
++ if (*ppos == 0) {
++ dbg_erase_count->index = dbg_erase_count->offset;
+
-+ len = snprintf(buf, sizeof(buf),
-+ "Print parameter: \"offset=%d length=%d\"\n",
-+ dbg_erase_count->offset,
-+ dbg_erase_count->length);
++ len = snprintf(buf, sizeof(buf),
++ "Print parameter: \"offset=%u length=%u\"\n",
++ dbg_erase_count->offset,
++ dbg_erase_count->length);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
+
-+ len = snprintf(buf, sizeof(buf),
-+ "Block Index ---------------- "
-+ "Erase count from system startup ----------------\n");
++ len = snprintf(buf, sizeof(buf),
++ "Block Index ---------------- "
++ "Erase count from system startup ----------------\n");
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
++ }
+
-+ for (index = dbg_erase_count->index;
-+ index < (dbg_erase_count->offset + dbg_erase_count->length) &&
-+ ((pusrbuf - buffer) < (count - 100));
-+ index += 8) {
++ for (index = dbg_erase_count->index;
++ index < (dbg_erase_count->offset + dbg_erase_count->length) &&
++ ((pusrbuf - buffer) < (count - 100));
++ index += 8) {
+
-+ pe = &dbg_erase_count->pe[index];
++ pe = &dbg_erase_count->pe[index];
+
-+ len = snprintf(buf, sizeof(buf),
-+ "%4d: %8u %8u %8u %8u %8u %8u %8u %8u\n",
-+ index,
-+ pe[0], pe[1], pe[2], pe[3],
-+ pe[4], pe[5], pe[6], pe[7]);
++ len = snprintf(buf, sizeof(buf),
++ "%4u: %8u %8u %8u %8u %8u %8u %8u %8u\n",
++ index,
++ pe[0], pe[1], pe[2], pe[3],
++ pe[4], pe[5], pe[6], pe[7]);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
++ }
+
-+ dbg_erase_count->index = index;
++ dbg_erase_count->index = index;
+
-+ *ppos += (pusrbuf - buffer);
-+ value = pusrbuf - buffer;
-+ return value;
++ *ppos += (pusrbuf - buffer);
++ value = pusrbuf - buffer;
++ return value;
+}
+/*****************************************************************************/
+/*
@@ -295886,212 +364096,212 @@ index 0000000..26c51b0
+
+ */
+static int dbgfs_erase_count_write(struct file *filp,
-+ const char __user *buffer,
-+ size_t count, loff_t *ppos)
++ const char __user *buffer,
++ size_t count, loff_t *ppos)
+{
-+ char *str;
-+ char buf[128] = {0};
-+ int ret;
-+ unsigned long value = 0;
-+ unsigned long pos = 0;
++ char *str;
++ char buf[128] = {0};
++ int ret;
++ unsigned long value = 0;
++ unsigned long pos = 0;
+
-+ if (count > sizeof(buf)) {
-+ count = sizeof(buf);
-+ }
++ if (count > sizeof(buf)) {
++ count = sizeof(buf);
++ }
+
-+ if (copy_from_user(buf, buffer, count)) {
-+ return -EFAULT;
-+ }
++ if (copy_from_user(buf, buffer, count)) {
++ return -EFAULT;
++ }
+
-+ while (pos < count) {
-+ while (pos < count &&
-+ (buf[pos] == ' ' || buf[pos] == ',' || buf[pos] == ';')) {
-+ pos++;
-+ }
++ while (pos < count) {
++ while (pos < count &&
++ (buf[pos] == ' ' || buf[pos] == ',' || buf[pos] == ';')) {
++ pos++;
++ }
+
-+ if (pos >= count) {
-+ break;
-+ }
++ if (pos >= count) {
++ break;
++ }
+
-+ switch (buf[pos]) {
++ switch (buf[pos]) {
+
-+ case 'o':
++ case 'o':
+
-+ if (memcmp(&buf[pos], CMD_WORD_OFFSET,
-+ sizeof(CMD_WORD_OFFSET) - 1)) {
-+ break;
-+ }
++ if (memcmp(&buf[pos], CMD_WORD_OFFSET,
++ sizeof(CMD_WORD_OFFSET) - 1)) {
++ break;
++ }
+
-+ pos += sizeof(CMD_WORD_OFFSET) - 1;
-+ str = (char *)(buf + pos);
-+ ret = kstrtoul(str, 10, &value);
-+ if (ret < 0) {
-+ value = 0;
-+ }
-+ if (value >= dbg_erase_count->blocknum) {
-+ value = 0;
-+ }
++ pos += sizeof(CMD_WORD_OFFSET) - 1;
++ str = (char *)(buf + pos);
++ ret = kstrtoul(str, 10, &value);
++ if (ret < 0) {
++ value = 0;
++ }
++ if (value >= dbg_erase_count->blocknum) {
++ value = 0;
++ }
+
-+ dbg_erase_count->offset = (value & ~7);
++ dbg_erase_count->offset = (value & ~7);
+
-+ break;
++ break;
+
-+ case 'l':
-+ if (memcmp(&buf[pos], CMD_WORD_LENGTH,
-+ sizeof(CMD_WORD_LENGTH) - 1)) {
-+ break;
-+ }
++ case 'l':
++ if (memcmp(&buf[pos], CMD_WORD_LENGTH,
++ sizeof(CMD_WORD_LENGTH) - 1)) {
++ break;
++ }
+
-+ pos += sizeof(CMD_WORD_LENGTH) - 1;
-+ str = (char *)(buf + pos);
-+ ret = kstrtoul(str, 10, &value);
-+ if (ret < 0) {
-+ value = dbg_erase_count->blocknum;
-+ }
++ pos += sizeof(CMD_WORD_LENGTH) - 1;
++ str = (char *)(buf + pos);
++ ret = kstrtoul(str, 10, &value);
++ if (ret < 0) {
++ value = dbg_erase_count->blocknum;
++ }
+
-+ value = ((value + 7) & ~7);
++ value = ((value + 7) & ~7);
+
-+ if (dbg_erase_count->offset + value
-+ > dbg_erase_count->blocknum)
-+ value = dbg_erase_count->blocknum
-+ - dbg_erase_count->offset;
++ if (dbg_erase_count->offset + value
++ > dbg_erase_count->blocknum)
++ value = dbg_erase_count->blocknum
++ - dbg_erase_count->offset;
+
-+ dbg_erase_count->length = value;
++ dbg_erase_count->length = value;
+
-+ break;
++ break;
+
-+ case 'c':
-+ if (memcmp(&buf[pos], CMD_WORD_CLEAN,
-+ sizeof(CMD_WORD_CLEAN) - 1)) {
-+ break;
-+ }
++ case 'c':
++ if (memcmp(&buf[pos], CMD_WORD_CLEAN,
++ sizeof(CMD_WORD_CLEAN) - 1)) {
++ break;
++ }
+
-+ memset(dbg_erase_count->pe, 0,
-+ dbg_erase_count->blocknum *
-+ sizeof(struct hinfc610_dbg_erase_count_t));
++ memset(dbg_erase_count->pe, 0,
++ dbg_erase_count->blocknum *
++ sizeof(struct hinfc610_dbg_erase_count_t));
+
-+ return count;
-+ }
++ return count;
++ }
+
-+ while (pos < count &&
-+ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
-+ pos++;
-+ }
-+ }
++ while (pos < count &&
++ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
++ pos++;
++ }
++ }
+
-+ return count;
++ return count;
+}
+/*****************************************************************************/
+
+static const struct file_operations dbgfs_erase_count_fops = {
-+ .owner = THIS_MODULE,
-+ .read = dbgfs_erase_count_read,
-+ .write = dbgfs_erase_count_write,
++ .owner = THIS_MODULE,
++ .read = dbgfs_erase_count_read,
++ .write = dbgfs_erase_count_write,
+};
+/*****************************************************************************/
+
+static int dbgfs_erase_count_init(struct dentry *root, struct hinfc_host *host)
+{
-+ unsigned int size;
-+ unsigned int blocknum;
-+ unsigned int pagesize;
-+ unsigned int blocksize;
-+ unsigned int chipsize;
-+ struct hinfc610_dbg_erase_count_t *erase_count;
++ unsigned int size;
++ unsigned int blocknum;
++ unsigned int pagesize;
++ unsigned int blocksize;
++ unsigned int chipsize;
++ struct hinfc610_dbg_erase_count_t *erase_count;
+
-+ if (dbg_erase_count) {
-+ return 0;
-+ }
++ if (dbg_erase_count) {
++ return 0;
++ }
+
-+ pagesize = (host->pagesize >> 10);
-+ blocksize = (host->mtd->erasesize >> 10);
-+ chipsize = (unsigned int)(host->chip->chipsize >> 10);
++ pagesize = (host->pagesize >> 10);
++ blocksize = (host->mtd->erasesize >> 10);
++ chipsize = (unsigned int)(host->chip->chipsize >> 10);
+
-+ blocknum = chipsize / blocksize;
-+ size = sizeof(int) * blocknum
-+ + sizeof(struct hinfc610_dbg_erase_count_t);
++ blocknum = chipsize / blocksize;
++ size = sizeof(int) * blocknum
++ + sizeof(struct hinfc610_dbg_erase_count_t);
+
-+ erase_count = vmalloc(size);
-+ if (!erase_count) {
-+ PR_ERR("Can't allocate memory.\n");
-+ return -ENOMEM;
-+ }
-+ memset(erase_count, 0, size);
++ erase_count = vmalloc(size);
++ if (!erase_count) {
++ PR_ERR("Can't allocate memory.\n");
++ return -ENOMEM;
++ }
++ memset(erase_count, 0, size);
+
-+ erase_count->blocknum = blocknum;
-+ erase_count->page_per_block = blocksize / pagesize;
-+ erase_count->length = blocknum;
++ erase_count->blocknum = blocknum;
++ erase_count->page_per_block = blocksize / pagesize;
++ erase_count->length = blocknum;
+
-+ erase_count->dentry = debugfs_create_file("erase_count",
-+ S_IFREG | S_IRUSR | S_IWUSR,
-+ root, NULL, &dbgfs_erase_count_fops);
-+ if (!erase_count->dentry) {
-+ PR_ERR("Can't create 'erase_count' file.\n");
-+ vfree(erase_count);
-+ return -ENOENT;
-+ }
++ erase_count->dentry = debugfs_create_file("erase_count",
++ S_IFREG | S_IRUSR | S_IWUSR,
++ root, NULL, &dbgfs_erase_count_fops);
++ if (!erase_count->dentry) {
++ PR_ERR("Can't create 'erase_count' file.\n");
++ vfree(erase_count);
++ return -ENOENT;
++ }
+
-+ dbg_erase_count = erase_count;
++ dbg_erase_count = erase_count;
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int dbgfs_erase_count_uninit(void)
+{
-+ if (!dbg_erase_count) {
-+ return 0;
-+ }
++ if (!dbg_erase_count) {
++ return 0;
++ }
+
-+ mutex_lock(&dbg_erase_count_mutex);
++ mutex_lock(&dbg_erase_count_mutex);
+
-+ debugfs_remove(dbg_erase_count->dentry);
++ debugfs_remove(dbg_erase_count->dentry);
+
-+ vfree(dbg_erase_count);
-+ dbg_erase_count = NULL;
++ vfree(dbg_erase_count);
++ dbg_erase_count = NULL;
+
-+ mutex_unlock(&dbg_erase_count_mutex);
++ mutex_unlock(&dbg_erase_count_mutex);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static void dbg_erase_count_erase(struct hinfc_host *host)
+{
-+ unsigned int block_index;
++ unsigned int block_index;
+
-+ mutex_lock(&dbg_erase_count_mutex);
++ mutex_lock(&dbg_erase_count_mutex);
+
-+ if (!dbg_erase_count) {
-+ goto exit;
-+ }
++ if (!dbg_erase_count) {
++ goto exit;
++ }
+
-+ block_index = (host->addr_value[0] / dbg_erase_count->page_per_block);
++ block_index = (host->addr_value[0] / dbg_erase_count->page_per_block);
+
-+ if (block_index > dbg_erase_count->blocknum) {
-+ PR_ERR("Block out of range.\n");
-+ return;
-+ }
++ if (block_index > dbg_erase_count->blocknum) {
++ PR_ERR("Block out of range.\n");
++ return;
++ }
+
-+ dbg_erase_count->pe[block_index]++;
++ dbg_erase_count->pe[block_index]++;
+
+exit:
-+ mutex_unlock(&dbg_erase_count_mutex);
++ mutex_unlock(&dbg_erase_count_mutex);
+}
+/*****************************************************************************/
+
+struct hinfc610_dbg_inf_t hinfc610_dbg_inf_erase_count = {
-+ "erase_count", 0,
-+ dbgfs_erase_count_init,
-+ dbgfs_erase_count_uninit,
-+ NULL,
-+ NULL,
-+ dbg_erase_count_erase,
-+ NULL,
++ "erase_count", 0,
++ dbgfs_erase_count_init,
++ dbgfs_erase_count_uninit,
++ NULL,
++ NULL,
++ dbg_erase_count_erase,
++ NULL,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg_inf.c b/drivers/mtd/nand/hinfc610/hinfc610_dbg_inf.c
new file mode 100644
-index 0000000..b089e0a
+index 0000000..48eee92
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg_inf.c
@@ -0,0 +1,85 @@
@@ -296128,57 +364338,57 @@ index 0000000..b089e0a
+void hinfc610_dbg_write(struct hinfc_host *host)
+{
+#ifdef CONFIG_HINFC610_DBG_NAND_DEBUG
-+ struct hinfc610_dbg_inf_t **inf;
++ struct hinfc610_dbg_inf_t **inf;
+
-+ for (inf = hinfc610_dbg_inf; *inf; inf++)
-+ if ((*inf)->enable && (*inf)->write) {
-+ (*inf)->write(host);
-+ }
++ for (inf = hinfc610_dbg_inf; *inf; inf++)
++ if ((*inf)->enable && (*inf)->write) {
++ (*inf)->write(host);
++ }
+#endif
+}
+
+void hinfc610_dbg_erase(struct hinfc_host *host)
+{
+#ifdef CONFIG_HINFC610_DBG_NAND_DEBUG
-+ struct hinfc610_dbg_inf_t **inf;
++ struct hinfc610_dbg_inf_t **inf;
+
-+ for (inf = hinfc610_dbg_inf; *inf; inf++)
-+ if ((*inf)->enable && (*inf)->erase) {
-+ (*inf)->erase(host);
-+ }
++ for (inf = hinfc610_dbg_inf; *inf; inf++)
++ if ((*inf)->enable && (*inf)->erase) {
++ (*inf)->erase(host);
++ }
+#endif
+}
+
+void hinfc610_dbg_read(struct hinfc_host *host)
+{
+#ifdef CONFIG_HINFC610_DBG_NAND_DEBUG
-+ struct hinfc610_dbg_inf_t **inf;
++ struct hinfc610_dbg_inf_t **inf;
+
-+ for (inf = hinfc610_dbg_inf; *inf; inf++)
-+ if ((*inf)->enable && (*inf)->read) {
-+ (*inf)->read(host);
-+ }
++ for (inf = hinfc610_dbg_inf; *inf; inf++)
++ if ((*inf)->enable && (*inf)->read) {
++ (*inf)->read(host);
++ }
+#endif
+}
+
+void hinfc610_dbg_read_retry(struct hinfc_host *host, int index)
+{
+#ifdef CONFIG_HINFC610_DBG_NAND_DEBUG
-+ struct hinfc610_dbg_inf_t **inf;
++ struct hinfc610_dbg_inf_t **inf;
+
-+ for (inf = hinfc610_dbg_inf; *inf; inf++)
-+ if ((*inf)->enable && (*inf)->read_retry) {
-+ (*inf)->read_retry(host, index);
-+ }
++ for (inf = hinfc610_dbg_inf; *inf; inf++)
++ if ((*inf)->enable && (*inf)->read_retry) {
++ (*inf)->read_retry(host, index);
++ }
+#endif
+}
+
+int hinfc610_dbg_init(struct hinfc_host *host)
+{
+#ifdef CONFIG_HINFC610_DBG_NAND_DEBUG
-+ return hinfc610_dbgfs_debug_init(host);
++ return hinfc610_dbgfs_debug_init(host);
+#endif
-+ return 0;
++ return 0;
+}
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg_inf.h b/drivers/mtd/nand/hinfc610/hinfc610_dbg_inf.h
new file mode 100644
@@ -296222,7 +364432,7 @@ index 0000000..10ac797
+#endif /* HINFC610_DBG_INFH */
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_dbg_read_retry.c b/drivers/mtd/nand/hinfc610/hinfc610_dbg_read_retry.c
new file mode 100644
-index 0000000..61834f6
+index 0000000..2e1a7bd
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_dbg_read_retry.c
@@ -0,0 +1,415 @@
@@ -296262,34 +364472,34 @@ index 0000000..61834f6
+#endif /* CONFIG_HINFC610_DBG_READ_RETRY_NUM */
+
+struct hinfc610_dbg_read_retry_item_t {
-+ unsigned int page;
++ unsigned int page;
+
-+ unsigned short hour;
-+ unsigned short min;
-+ unsigned short sec;
-+ unsigned short msec;
++ unsigned short hour;
++ unsigned short min;
++ unsigned short sec;
++ unsigned short msec;
+
-+ unsigned short retry; /* success retry */
-+ unsigned short ecc_err;
++ unsigned short retry; /* success retry */
++ unsigned short ecc_err;
+};
+
+struct hinfc610_dbg_read_retry_t {
+
-+ struct dentry *dentry;
-+ unsigned int index; /* current logs index */
-+ int count; /* number of logs */
++ struct dentry *dentry;
++ unsigned int index; /* current logs index */
++ int count; /* number of logs */
+
-+ unsigned int offset;
-+ unsigned int length;
-+ unsigned int pagecount;
++ unsigned int offset;
++ unsigned int length;
++ unsigned int pagecount;
+
-+ unsigned int read_index;
++ unsigned int read_index;
+
-+ unsigned int max_retry; /* the max read retry times */
-+ unsigned int retry[16];
++ unsigned int max_retry; /* the max read retry times */
++ unsigned int retry[16];
+
-+ struct hinfc610_dbg_read_retry_item_t
-+ item[CONFIG_HINFC610_DBG_READ_RETRY_NUM];
++ struct hinfc610_dbg_read_retry_item_t
++ item[CONFIG_HINFC610_DBG_READ_RETRY_NUM];
+};
+
+static DEFINE_MUTEX(dbg_read_retry_mutex);
@@ -296297,130 +364507,130 @@ index 0000000..61834f6
+/*****************************************************************************/
+
+static void do_gettime(unsigned short *hour, unsigned short *min,
-+ unsigned short *sec, unsigned short *msec)
++ unsigned short *sec, unsigned short *msec)
+{
-+ long val;
-+ struct timeval tv;
++ long val;
++ struct timeval tv;
+
-+ do_gettimeofday(&tv);
-+ val = tv.tv_sec % 86400; /* the second form 0 hour */
++ do_gettimeofday(&tv);
++ val = tv.tv_sec % 86400; /* the second form 0 hour */
+
-+ if (hour) {
-+ *hour = val / 3600;
-+ }
-+ val %= 3600;
-+ if (min) {
-+ *min = val / 60;
-+ }
-+ if (sec) {
-+ *sec = val % 60;
-+ }
-+ if (msec) {
-+ *msec = tv.tv_usec / 1000;
-+ }
++ if (hour) {
++ *hour = val / 3600;
++ }
++ val %= 3600;
++ if (min) {
++ *min = val / 60;
++ }
++ if (sec) {
++ *sec = val % 60;
++ }
++ if (msec) {
++ *msec = tv.tv_usec / 1000;
++ }
+}
+/*****************************************************************************/
+
+static ssize_t dbgfs_read_retry_read(struct file *filp, char __user *buffer,
-+ size_t count, loff_t *ppos)
++ size_t count, loff_t *ppos)
+{
-+ int ix;
-+ char *ptr;
-+ int len = 0;
-+ char buf[128] = {0};
-+ unsigned int read_index;
-+ char __user *pusrbuf = buffer;
-+ struct hinfc610_dbg_read_retry_item_t *item;
++ int ix;
++ char *ptr;
++ int len = 0;
++ char buf[128] = {0};
++ unsigned int read_index;
++ char __user *pusrbuf = buffer;
++ struct hinfc610_dbg_read_retry_item_t *item;
+
-+ if (*ppos == 0) {
++ if (*ppos == 0) {
+
-+ if (dbg_read_retry->count
-+ < CONFIG_HINFC610_DBG_READ_RETRY_NUM) {
-+ dbg_read_retry->read_index = 0;
-+ } else {
-+ dbg_read_retry->read_index
-+ = (dbg_read_retry->index + 1);
-+ }
-+ len = snprintf(buf, sizeof(buf),
-+ "Print parameter: \"offset=%d length=%d\"\n",
-+ dbg_read_retry->offset,
-+ dbg_read_retry->length);
++ if (dbg_read_retry->count
++ < CONFIG_HINFC610_DBG_READ_RETRY_NUM) {
++ dbg_read_retry->read_index = 0;
++ } else {
++ dbg_read_retry->read_index
++ = (dbg_read_retry->index + 1);
++ }
++ len = snprintf(buf, sizeof(buf),
++ "Print parameter: \"offset=%u length=%u\"\n",
++ dbg_read_retry->offset,
++ dbg_read_retry->length);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
+
-+ len = snprintf(buf, sizeof(buf),
-+ " UTC Clock page read retry (max: %d)\n",
-+ dbg_read_retry->max_retry);
++ len = snprintf(buf, sizeof(buf),
++ " UTC Clock page read retry (max: %u)\n",
++ dbg_read_retry->max_retry);
+
-+ ptr = buf;
-+ ptr += sprintf(ptr, "Read retry: ");
-+ for (ix = 1; ix <= dbg_read_retry->max_retry; ix++) {
-+ ptr += sprintf(ptr, "%d, ", dbg_read_retry->retry[ix]);
-+ }
-+ ptr += sprintf(ptr, "\n");
++ ptr = buf;
++ ptr += sprintf(ptr, "Read retry: ");
++ for (ix = 1; ix <= dbg_read_retry->max_retry; ix++) {
++ ptr += sprintf(ptr, "%u, ", dbg_read_retry->retry[ix]);
++ }
++ ptr += sprintf(ptr, "\n");
+
-+ len = (ptr - buf);
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
++ len = (ptr - buf);
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
+
+
-+ len = snprintf(buf, sizeof(buf),
-+ " UTC Clock page read retry (max: %d)\n",
-+ dbg_read_retry->max_retry);
++ len = snprintf(buf, sizeof(buf),
++ " UTC Clock page read retry (max: %u)\n",
++ dbg_read_retry->max_retry);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
+
-+ } else if (dbg_read_retry->read_index == dbg_read_retry->index) {
-+ return 0;
-+ }
++ } else if (dbg_read_retry->read_index == dbg_read_retry->index) {
++ return 0;
++ }
+
-+ for (read_index = dbg_read_retry->read_index;
-+ (read_index != dbg_read_retry->index); ++read_index) {
++ for (read_index = dbg_read_retry->read_index;
++ (read_index != dbg_read_retry->index); ++read_index) {
+
-+ if (read_index >= CONFIG_HINFC610_DBG_READ_RETRY_NUM) {
-+ read_index = 0;
-+ }
++ if (read_index >= CONFIG_HINFC610_DBG_READ_RETRY_NUM) {
++ read_index = 0;
++ }
+
-+ item = &dbg_read_retry->item[read_index];
++ item = &dbg_read_retry->item[read_index];
+
-+ if ((count - (pusrbuf - buffer)) < 80) {
-+ break;
-+ }
++ if ((count - (pusrbuf - buffer)) < 80) {
++ break;
++ }
+
-+ len = snprintf(buf, sizeof(buf),
-+ "%02d:%02d:%02d.%04d 0x%08X ",
-+ item->hour, item->min, item->sec, item->msec,
-+ item->page);
++ len = snprintf(buf, sizeof(buf),
++ "%02d:%02d:%02d.%04d 0x%08X ",
++ item->hour, item->min, item->sec, item->msec,
++ item->page);
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
+
-+ if (!item->ecc_err) {
-+ len = sprintf(buf, "%d\n", item->retry);
-+ } else {
-+ len = sprintf(buf, "fail\n");
-+ }
++ if (!item->ecc_err) {
++ len = sprintf(buf, "%d\n", item->retry);
++ } else {
++ len = sprintf(buf, "fail\n");
++ }
+
-+ if (copy_to_user(pusrbuf, buf, len)) {
-+ return -EFAULT;
-+ }
-+ pusrbuf += len;
-+ }
++ if (copy_to_user(pusrbuf, buf, len)) {
++ return -EFAULT;
++ }
++ pusrbuf += len;
++ }
+
-+ dbg_read_retry->read_index = read_index;
++ dbg_read_retry->read_index = read_index;
+
-+ *ppos += (pusrbuf - buffer);
-+ return pusrbuf - buffer;
++ *ppos += (pusrbuf - buffer);
++ return pusrbuf - buffer;
+}
+/******************************************************************************/
+/*
@@ -296428,222 +364638,222 @@ index 0000000..61834f6
+ *
+ */
+static ssize_t dbgfs_read_retry_write(struct file *filp,
-+ const char __user *buffer, size_t count,
-+ loff_t *ppos)
++ const char __user *buffer, size_t count,
++ loff_t *ppos)
+{
-+ char *str;
-+ char buf[128] = {0};
-+ int ret;
-+ unsigned long value = 0;
-+ unsigned long pos = 0;
++ char *str;
++ char buf[128] = {0};
++ int ret;
++ unsigned long value = 0;
++ unsigned long pos = 0;
+
-+ if (count > sizeof(buf)) {
-+ count = sizeof(buf);
-+ }
++ if (count > sizeof(buf)) {
++ count = sizeof(buf);
++ }
+
-+ if (copy_from_user(buf, buffer, count)) {
-+ return -EFAULT;
-+ }
++ if (copy_from_user(buf, buffer, count)) {
++ return -EFAULT;
++ }
+
-+ while (pos < count) {
-+ while (pos < count &&
-+ (buf[pos] == ' ' || buf[pos] == ',' || buf[pos] == ';')) {
-+ pos++;
-+ }
++ while (pos < count) {
++ while (pos < count &&
++ (buf[pos] == ' ' || buf[pos] == ',' || buf[pos] == ';')) {
++ pos++;
++ }
+
-+ if (pos >= count) {
-+ break;
-+ }
++ if (pos >= count) {
++ break;
++ }
+
-+ switch (buf[pos]) {
++ switch (buf[pos]) {
+
-+ case 'o':
++ case 'o':
+
-+ if (memcmp(&buf[pos], CMD_WORD_OFFSET,
-+ sizeof(CMD_WORD_OFFSET) - 1)) {
-+ break;
-+ }
++ if (memcmp(&buf[pos], CMD_WORD_OFFSET,
++ sizeof(CMD_WORD_OFFSET) - 1)) {
++ break;
++ }
+
-+ pos += sizeof(CMD_WORD_OFFSET) - 1;
-+ str = (char *)(buf + pos);
-+ ret = kstrtoul(str, 10, &value);
++ pos += sizeof(CMD_WORD_OFFSET) - 1;
++ str = (char *)(buf + pos);
++ ret = kstrtoul(str, 10, &value);
+
-+ if (ret < 0) {
-+ value = 0;
-+ }
-+ if (value >= dbg_read_retry->pagecount) {
-+ value = 0;
-+ }
++ if (ret < 0) {
++ value = 0;
++ }
++ if (value >= dbg_read_retry->pagecount) {
++ value = 0;
++ }
+
-+ dbg_read_retry->offset = (value & ~7);
++ dbg_read_retry->offset = (value & ~7);
+
-+ break;
++ break;
+
-+ case 'l':
-+ if (memcmp(&buf[pos], CMD_WORD_LENGTH,
-+ sizeof(CMD_WORD_LENGTH) - 1)) {
-+ break;
-+ }
++ case 'l':
++ if (memcmp(&buf[pos], CMD_WORD_LENGTH,
++ sizeof(CMD_WORD_LENGTH) - 1)) {
++ break;
++ }
+
-+ pos += sizeof(CMD_WORD_LENGTH) - 1;
-+ str = (char *)(buf + pos);
-+ ret = kstrtoul(str, 10, &value);
++ pos += sizeof(CMD_WORD_LENGTH) - 1;
++ str = (char *)(buf + pos);
++ ret = kstrtoul(str, 10, &value);
+
-+ if (ret < 0) {
-+ value = dbg_read_retry->pagecount;
-+ }
++ if (ret < 0) {
++ value = dbg_read_retry->pagecount;
++ }
+
-+ value = ((value + 7) & ~7);
++ value = ((value + 7) & ~7);
+
-+ if (dbg_read_retry->offset + value >
-+ dbg_read_retry->pagecount)
-+ value = dbg_read_retry->pagecount
-+ - dbg_read_retry->offset;
++ if (dbg_read_retry->offset + value >
++ dbg_read_retry->pagecount)
++ value = dbg_read_retry->pagecount
++ - dbg_read_retry->offset;
+
-+ dbg_read_retry->length = value;
++ dbg_read_retry->length = value;
+
-+ break;
-+ }
++ break;
++ }
+
-+ while (pos < count &&
-+ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
-+ pos++;
-+ }
-+ }
++ while (pos < count &&
++ (buf[pos] != ' ' && buf[pos] != ',' && buf[pos] != ';')) {
++ pos++;
++ }
++ }
+
-+ return count;
++ return count;
+}
+/******************************************************************************/
+
+static const struct file_operations dbgfs_read_retry_fops = {
-+ .owner = THIS_MODULE,
-+ .read = dbgfs_read_retry_read,
-+ .write = dbgfs_read_retry_write,
++ .owner = THIS_MODULE,
++ .read = dbgfs_read_retry_read,
++ .write = dbgfs_read_retry_write,
+};
+/*****************************************************************************/
+
+static int dbgfs_read_retry_init(struct dentry *root, struct hinfc_host *host)
+{
-+ unsigned int pagesize;
-+ unsigned int chipsize;
-+ struct hinfc610_dbg_read_retry_t *read_retry;
++ unsigned int pagesize;
++ unsigned int chipsize;
++ struct hinfc610_dbg_read_retry_t *read_retry;
+
-+ if (dbg_read_retry) {
-+ return 0;
-+ }
++ if (dbg_read_retry) {
++ return 0;
++ }
+
-+ if (!host->read_retry) {
-+ pr_warn("read_retry: The NAND not support this interface.\n");
-+ return -1;
-+ }
++ if (!host->read_retry) {
++ pr_warn("read_retry: The NAND not support this interface.\n");
++ return -1;
++ }
+
-+ read_retry = vmalloc(sizeof(struct hinfc610_dbg_read_retry_t));
-+ if (!read_retry) {
-+ PR_ERR("Can't allocate memory.\n");
-+ return -ENOMEM;
-+ }
-+ memset(read_retry, 0, sizeof(struct hinfc610_dbg_read_retry_t));
++ read_retry = vmalloc(sizeof(struct hinfc610_dbg_read_retry_t));
++ if (!read_retry) {
++ PR_ERR("Can't allocate memory.\n");
++ return -ENOMEM;
++ }
++ memset(read_retry, 0, sizeof(struct hinfc610_dbg_read_retry_t));
+
-+ pagesize = (host->pagesize >> 10);
-+ chipsize = (unsigned int)(host->chip->chipsize >> 10);
-+ read_retry->pagecount = (chipsize / pagesize);
-+ read_retry->length = read_retry->pagecount;
-+ read_retry->max_retry = host->read_retry->count;
++ pagesize = (host->pagesize >> 10);
++ chipsize = (unsigned int)(host->chip->chipsize >> 10);
++ read_retry->pagecount = (chipsize / pagesize);
++ read_retry->length = read_retry->pagecount;
++ read_retry->max_retry = host->read_retry->count;
+
-+ if (read_retry->max_retry > 16) {
-+ vfree(read_retry);
-+ PR_ERR("Bug, max_retry too small.\n");
-+ return -EFAULT;
-+ }
++ if (read_retry->max_retry > 16) {
++ vfree(read_retry);
++ PR_ERR("Bug, max_retry too small.\n");
++ return -EFAULT;
++ }
+
-+ read_retry->dentry = debugfs_create_file("read_retry",
-+ S_IFREG | S_IRUSR | S_IWUSR,
-+ root, NULL, &dbgfs_read_retry_fops);
-+ if (!read_retry->dentry) {
-+ PR_ERR("Can't create 'read_retry' file.\n");
-+ vfree(read_retry);
-+ return -ENOENT;
-+ }
++ read_retry->dentry = debugfs_create_file("read_retry",
++ S_IFREG | S_IRUSR | S_IWUSR,
++ root, NULL, &dbgfs_read_retry_fops);
++ if (!read_retry->dentry) {
++ PR_ERR("Can't create 'read_retry' file.\n");
++ vfree(read_retry);
++ return -ENOENT;
++ }
+
-+ dbg_read_retry = read_retry;
++ dbg_read_retry = read_retry;
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int dbgfs_read_retry_uninit(void)
+{
-+ if (!dbg_read_retry) {
-+ return 0;
-+ }
++ if (!dbg_read_retry) {
++ return 0;
++ }
+
-+ mutex_lock(&dbg_read_retry_mutex);
++ mutex_lock(&dbg_read_retry_mutex);
+
-+ debugfs_remove(dbg_read_retry->dentry);
++ debugfs_remove(dbg_read_retry->dentry);
+
-+ vfree(dbg_read_retry);
-+ dbg_read_retry = NULL;
++ vfree(dbg_read_retry);
++ dbg_read_retry = NULL;
+
-+ mutex_unlock(&dbg_read_retry_mutex);
++ mutex_unlock(&dbg_read_retry_mutex);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static void hinfc610_dbg_read_retry_rr(struct hinfc_host *host, int index)
+{
-+ unsigned int page;
-+ struct hinfc610_dbg_read_retry_item_t *item;
++ unsigned int page;
++ struct hinfc610_dbg_read_retry_item_t *item;
+
-+ mutex_lock(&dbg_read_retry_mutex);
++ mutex_lock(&dbg_read_retry_mutex);
+
-+ if (!dbg_read_retry) {
-+ goto exit;
-+ }
++ if (!dbg_read_retry) {
++ goto exit;
++ }
+
-+ page = GET_PAGE_INDEX(host);
++ page = GET_PAGE_INDEX(host);
+
-+ if (page < dbg_read_retry->offset ||
-+ page > (dbg_read_retry->offset + dbg_read_retry->length)) {
-+ goto exit;
-+ }
++ if (page < dbg_read_retry->offset ||
++ page > (dbg_read_retry->offset + dbg_read_retry->length)) {
++ goto exit;
++ }
+
-+ item = &dbg_read_retry->item[dbg_read_retry->index];
++ item = &dbg_read_retry->item[dbg_read_retry->index];
+
-+ dbg_read_retry->count++;
++ dbg_read_retry->count++;
+
-+ do_gettime(&item->hour, &item->min, &item->sec, &item->msec);
++ do_gettime(&item->hour, &item->min, &item->sec, &item->msec);
+
-+ item->page = page;
-+ item->retry = index;
++ item->page = page;
++ item->retry = index;
+
-+ item->ecc_err = IS_PS_UN_ECC(host) ? 1 : 0;
-+ if (!item->ecc_err) {
-+ dbg_read_retry->retry[index]++;
-+ }
++ item->ecc_err = IS_PS_UN_ECC(host) ? 1 : 0;
++ if (!item->ecc_err) {
++ dbg_read_retry->retry[index]++;
++ }
+
-+ if (++dbg_read_retry->index >= CONFIG_HINFC610_DBG_READ_RETRY_NUM) {
-+ dbg_read_retry->index = 0;
-+ }
++ if (++dbg_read_retry->index >= CONFIG_HINFC610_DBG_READ_RETRY_NUM) {
++ dbg_read_retry->index = 0;
++ }
+
+exit:
-+ mutex_unlock(&dbg_read_retry_mutex);
++ mutex_unlock(&dbg_read_retry_mutex);
+}
+/*****************************************************************************/
+
+struct hinfc610_dbg_inf_t hinfc610_dbg_inf_read_retry = {
-+ "read_retry", 0,
-+ dbgfs_read_retry_init,
-+ dbgfs_read_retry_uninit,
-+ NULL,
-+ NULL,
-+ NULL,
-+ hinfc610_dbg_read_retry_rr,
++ "read_retry", 0,
++ dbgfs_read_retry_init,
++ dbgfs_read_retry_uninit,
++ NULL,
++ NULL,
++ NULL,
++ hinfc610_dbg_read_retry_rr,
+};
+/*****************************************************************************/
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_gen.c b/drivers/mtd/nand/hinfc610/hinfc610_gen.c
new file mode 100644
-index 0000000..9e3ed8b
+index 0000000..2b43cf9
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_gen.c
@@ -0,0 +1,85 @@
@@ -296671,70 +364881,70 @@ index 0000000..9e3ed8b
+/*****************************************************************************/
+
+static struct match_reg_type page_type2reg[] = {
-+ {
-+ hinfc610_pagesize_2K, NAND_PAGE_2K,
-+ }, {
-+ hinfc610_pagesize_4K, NAND_PAGE_4K,
-+ }, {
-+ hinfc610_pagesize_8K, NAND_PAGE_8K,
-+ }, {
-+ hinfc610_pagesize_16K, NAND_PAGE_16K,
-+ }, {
-+ hinfc610_pagesize_32K, NAND_PAGE_32K,
-+ }
++ {
++ hinfc610_pagesize_2K, NAND_PAGE_2K,
++ }, {
++ hinfc610_pagesize_4K, NAND_PAGE_4K,
++ }, {
++ hinfc610_pagesize_8K, NAND_PAGE_8K,
++ }, {
++ hinfc610_pagesize_16K, NAND_PAGE_16K,
++ }, {
++ hinfc610_pagesize_32K, NAND_PAGE_32K,
++ }
+};
+
+enum hinfc610_page_reg hinfc610_page_type2reg(int type)
+{
-+ return type2reg(page_type2reg, ARRAY_SIZE(page_type2reg), type, 0);
++ return type2reg(page_type2reg, ARRAY_SIZE(page_type2reg), type, 0);
+}
+
+int hinfc610_page_reg2type(enum hinfc610_page_reg reg)
+{
-+ return reg2type(page_type2reg, ARRAY_SIZE(page_type2reg), reg, 0);
++ return reg2type(page_type2reg, ARRAY_SIZE(page_type2reg), reg, 0);
+}
+/*****************************************************************************/
+
+static struct match_reg_type ecc_type2reg[] = {
-+ {
-+ hinfc610_ecc_none, NAND_ECC_NONE,
-+ }, {
-+ hinfc610_ecc_8bit, NAND_ECC_8BIT,
-+ }, {
-+ hinfc610_ecc_13bit, NAND_ECC_13BIT,
-+ }, {
-+ hinfc610_ecc_18bit, NAND_ECC_18BIT,
-+ }, {
-+ hinfc610_ecc_24bit, NAND_ECC_24BIT,
-+ }, {
-+ hinfc610_ecc_27bit, NAND_ECC_27BIT,
-+ }, {
-+ hinfc610_ecc_32bit, NAND_ECC_32BIT,
-+ }, {
-+ hinfc610_ecc_41bit, NAND_ECC_41BIT,
-+ }, {
-+ hinfc610_ecc_48bit, NAND_ECC_48BIT,
-+ }, {
-+ hinfc610_ecc_60bit, NAND_ECC_60BIT,
-+ }, {
-+ hinfc610_ecc_72bit, NAND_ECC_72BIT,
-+ }, {
-+ hinfc610_ecc_80bit, NAND_ECC_80BIT,
-+ }
++ {
++ hinfc610_ecc_none, NAND_ECC_NONE,
++ }, {
++ hinfc610_ecc_8bit, NAND_ECC_8BIT,
++ }, {
++ hinfc610_ecc_13bit, NAND_ECC_13BIT,
++ }, {
++ hinfc610_ecc_18bit, NAND_ECC_18BIT,
++ }, {
++ hinfc610_ecc_24bit, NAND_ECC_24BIT,
++ }, {
++ hinfc610_ecc_27bit, NAND_ECC_27BIT,
++ }, {
++ hinfc610_ecc_32bit, NAND_ECC_32BIT,
++ }, {
++ hinfc610_ecc_41bit, NAND_ECC_41BIT,
++ }, {
++ hinfc610_ecc_48bit, NAND_ECC_48BIT,
++ }, {
++ hinfc610_ecc_60bit, NAND_ECC_60BIT,
++ }, {
++ hinfc610_ecc_72bit, NAND_ECC_72BIT,
++ }, {
++ hinfc610_ecc_80bit, NAND_ECC_80BIT,
++ }
+};
+
+enum hinfc610_ecc_reg hinfc610_ecc_type2reg(int type)
+{
-+ return type2reg(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), type, 0);
++ return type2reg(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), type, 0);
+}
+
+int hinfc610_ecc_reg2type(enum hinfc610_ecc_reg reg)
+{
-+ return reg2type(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), reg, 0);
++ return reg2type(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), reg, 0);
+}
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_gen.h b/drivers/mtd/nand/hinfc610/hinfc610_gen.h
new file mode 100644
-index 0000000..3b85128
+index 0000000..c41ff6f
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_gen.h
@@ -0,0 +1,57 @@
@@ -296763,26 +364973,26 @@ index 0000000..3b85128
+#include "../hinfc_gen.h"
+
+enum hinfc610_ecc_reg {
-+ hinfc610_ecc_none = 0x00,
-+ hinfc610_ecc_8bit = 0x01,
-+ hinfc610_ecc_13bit = 0x02,
-+ hinfc610_ecc_18bit = 0x03,
-+ hinfc610_ecc_24bit = 0x04,
-+ hinfc610_ecc_27bit = 0x05,
-+ hinfc610_ecc_32bit = 0x06,
-+ hinfc610_ecc_41bit = 0x07,
-+ hinfc610_ecc_48bit = 0x08,
-+ hinfc610_ecc_60bit = 0x09,
-+ hinfc610_ecc_72bit = 0x0a,
-+ hinfc610_ecc_80bit = 0x0b,
++ hinfc610_ecc_none = 0x00,
++ hinfc610_ecc_8bit = 0x01,
++ hinfc610_ecc_13bit = 0x02,
++ hinfc610_ecc_18bit = 0x03,
++ hinfc610_ecc_24bit = 0x04,
++ hinfc610_ecc_27bit = 0x05,
++ hinfc610_ecc_32bit = 0x06,
++ hinfc610_ecc_41bit = 0x07,
++ hinfc610_ecc_48bit = 0x08,
++ hinfc610_ecc_60bit = 0x09,
++ hinfc610_ecc_72bit = 0x0a,
++ hinfc610_ecc_80bit = 0x0b,
+};
+
+enum hinfc610_page_reg {
-+ hinfc610_pagesize_2K = 0x01,
-+ hinfc610_pagesize_4K = 0x02,
-+ hinfc610_pagesize_8K = 0x03,
-+ hinfc610_pagesize_16K = 0x04,
-+ hinfc610_pagesize_32K = 0x05,
++ hinfc610_pagesize_2K = 0x01,
++ hinfc610_pagesize_4K = 0x02,
++ hinfc610_pagesize_8K = 0x03,
++ hinfc610_pagesize_16K = 0x04,
++ hinfc610_pagesize_32K = 0x05,
+};
+
+enum hinfc610_page_reg hinfc610_page_type2reg(int type);
@@ -296797,7 +365007,7 @@ index 0000000..3b85128
+#endif /* HINFC610_GENH */
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_os.c b/drivers/mtd/nand/hinfc610/hinfc610_os.c
new file mode 100644
-index 0000000..3cc6a83
+index 0000000..dda8928
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_os.c
@@ -0,0 +1,249 @@
@@ -296827,222 +365037,222 @@ index 0000000..3cc6a83
+
+static int hinfc610_nand_pre_probe(struct nand_chip *chip)
+{
-+ uint8_t nand_maf_id;
-+ struct hinfc_host *host = chip->priv;
++ uint8_t nand_maf_id;
++ struct hinfc_host *host = chip->priv;
+
-+ /* Reset the chip first */
-+ host->send_cmd_reset(host, 0);
++ /* Reset the chip first */
++ host->send_cmd_reset(host, 0);
+
-+ /* Check the ID */
-+ host->offset = 0;
-+ memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
-+ host->send_cmd_readid(host);
-+ nand_maf_id = readb(chip->IO_ADDR_R);
++ /* Check the ID */
++ host->offset = 0;
++ memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
++ host->send_cmd_readid(host);
++ nand_maf_id = readb(chip->IO_ADDR_R);
+
-+ if (nand_maf_id == 0x00 || nand_maf_id == 0xff) {
-+ PR_BUG("\nCannot found a valid Nand Device\n");
-+ return 1;
-+ }
++ if (nand_maf_id == 0x00 || nand_maf_id == 0xff) {
++ PR_BUG("\nCannot found a valid Nand Device\n");
++ return 1;
++ }
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_os_probe(struct platform_device *pltdev)
+{
-+ int size;
-+ int result = 0;
-+ struct hinfc_host *host;
-+ struct nand_chip *chip;
-+ struct mtd_info *mtd;
-+ struct resource *rs_reg, *rs_io = NULL;
-+ struct device *dev = &pltdev->dev;
-+ struct device_node *np = NULL;
++ int size;
++ int result = 0;
++ struct hinfc_host *host;
++ struct nand_chip *chip;
++ struct mtd_info *mtd;
++ struct resource *rs_reg, *rs_io = NULL;
++ struct device *dev = &pltdev->dev;
++ struct device_node *np = NULL;
+
-+ size = sizeof(struct hinfc_host) + sizeof(struct nand_chip)
-+ + sizeof(struct mtd_info);
-+ host = kmalloc(size, GFP_KERNEL);
-+ if (!host) {
-+ PR_BUG("failed to allocate device structure.\n");
-+ return -ENOMEM;
-+ }
-+ memset((char *)host, 0, size);
-+ platform_set_drvdata(pltdev, host);
++ size = sizeof(struct hinfc_host) + sizeof(struct nand_chip)
++ + sizeof(struct mtd_info);
++ host = kmalloc(size, GFP_KERNEL);
++ if (!host) {
++ PR_BUG("failed to allocate device structure.\n");
++ return -ENOMEM;
++ }
++ memset((char *)host, 0, size);
++ platform_set_drvdata(pltdev, host);
+
-+ host->dev = dev;
-+ host->chip = chip = (struct nand_chip *)&host[1];
-+ host->mtd = mtd = (struct mtd_info *)&chip[1];
++ host->dev = dev;
++ host->chip = chip = (struct nand_chip *)&host[1];
++ host->mtd = mtd = (struct mtd_info *)&chip[1];
+
-+ host->clk = devm_clk_get(dev, NULL);
-+ if (IS_ERR(host->clk)) {
-+ return PTR_ERR(host->clk);
-+ }
-+ /* enable and set system clock */
-+ clk_prepare_enable(host->clk);
++ host->clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(host->clk)) {
++ return PTR_ERR(host->clk);
++ }
++ /* enable and set system clock */
++ clk_prepare_enable(host->clk);
+
-+ rs_reg = platform_get_resource_byname(pltdev, IORESOURCE_MEM,
-+ "control");
-+ host->iobase = devm_ioremap_resource(dev, rs_reg);
-+ if (IS_ERR(host->iobase)) {
-+ PR_BUG("Error: Can't get resource for reg address.\n");
-+ result = -EIO;
-+ goto fail;
-+ }
++ rs_reg = platform_get_resource_byname(pltdev, IORESOURCE_MEM,
++ "control");
++ host->iobase = devm_ioremap_resource(dev, rs_reg);
++ if (IS_ERR(host->iobase)) {
++ PR_BUG("Error: Can't get resource for reg address.\n");
++ result = -EIO;
++ goto fail;
++ }
+
-+ np = of_get_next_available_child(dev->of_node, NULL);
++ np = of_get_next_available_child(dev->of_node, NULL);
+
-+ mtd->type = MTD_NANDFLASH;
-+ mtd = nand_to_mtd(chip);
-+ mtd->flags = MTD_CAP_NANDFLASH;
-+ mtd->owner = THIS_MODULE;
-+ mtd->name = np->name;
++ mtd->type = MTD_NANDFLASH;
++ mtd = nand_to_mtd(chip);
++ mtd->flags = MTD_CAP_NANDFLASH;
++ mtd->owner = THIS_MODULE;
++ mtd->name = np->name;
+
-+ rs_io = platform_get_resource_byname(pltdev, IORESOURCE_MEM,
-+ "memory");
-+ chip->IO_ADDR_R = chip->IO_ADDR_W = devm_ioremap_resource(dev, rs_io);
-+ if (IS_ERR(chip->IO_ADDR_R)) {
-+ PR_BUG("Error: Can't get resource for buffer address.\n");
-+ result = -EIO;
-+ goto fail;
-+ }
++ rs_io = platform_get_resource_byname(pltdev, IORESOURCE_MEM,
++ "memory");
++ chip->IO_ADDR_R = chip->IO_ADDR_W = devm_ioremap_resource(dev, rs_io);
++ if (IS_ERR(chip->IO_ADDR_R)) {
++ PR_BUG("Error: Can't get resource for buffer address.\n");
++ result = -EIO;
++ goto fail;
++ }
+
-+ host->buffer = dma_alloc_coherent(host->dev,
-+ (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE),
-+ &host->dma_buffer, GFP_KERNEL);
-+ if (!host->buffer) {
-+ PR_BUG("Can't malloc memory for NAND driver.");
-+ result = -EIO;
-+ goto fail;
-+ }
++ host->buffer = dma_alloc_coherent(host->dev,
++ (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE),
++ &host->dma_buffer, GFP_KERNEL);
++ if (!host->buffer) {
++ PR_BUG("Can't malloc memory for NAND driver.");
++ result = -EIO;
++ goto fail;
++ }
+
-+ chip->priv = host;
-+ host->chip = chip;
-+ chip->cmd_ctrl = hinfc610_cmd_ctrl;
-+ chip->dev_ready = hinfc610_dev_ready;
-+ chip->select_chip = hinfc610_select_chip;
-+ chip->read_byte = hinfc610_read_byte;
-+ chip->read_word = hinfc610_read_word;
-+ chip->write_buf = hinfc610_write_buf;
-+ chip->read_buf = hinfc610_read_buf;
++ chip->priv = host;
++ host->chip = chip;
++ chip->cmd_ctrl = hinfc610_cmd_ctrl;
++ chip->dev_ready = hinfc610_dev_ready;
++ chip->select_chip = hinfc610_select_chip;
++ chip->read_byte = hinfc610_read_byte;
++ chip->read_word = hinfc610_read_word;
++ chip->write_buf = hinfc610_write_buf;
++ chip->read_buf = hinfc610_read_buf;
+
-+ chip->chip_delay = HINFC610_CHIP_DELAY;
-+ chip->options = NAND_NEED_READRDY
-+ | NAND_BROKEN_XD
-+ | NAND_SKIP_BBTSCAN;
-+ chip->ecc.mode = NAND_ECC_NONE;
++ chip->chip_delay = HINFC610_CHIP_DELAY;
++ chip->options = NAND_NEED_READRDY
++ | NAND_BROKEN_XD
++ | NAND_SKIP_BBTSCAN;
++ chip->ecc.mode = NAND_ECC_NONE;
+
-+ if (hinfc610_nand_init(host, chip)) {
-+ PR_BUG("failed to allocate device buffer.\n");
-+ result = -EIO;
-+ goto fail;
-+ }
++ if (hinfc610_nand_init(host, chip)) {
++ PR_BUG("failed to allocate device buffer.\n");
++ result = -EIO;
++ goto fail;
++ }
+
-+ if (hinfc610_nand_pre_probe(chip)) {
-+ result = -EXDEV;
-+ goto fail;
-+ }
++ if (hinfc610_nand_pre_probe(chip)) {
++ result = -EXDEV;
++ goto fail;
++ }
+
-+ if (nand_scan(mtd, CONFIG_HINFC610_MAX_CHIP)) {
-+ result = -ENXIO;
-+ goto fail;
-+ }
++ if (nand_scan(mtd, CONFIG_HINFC610_MAX_CHIP)) {
++ result = -ENXIO;
++ goto fail;
++ }
+
-+ result = mtd_device_register(mtd, NULL, 0);
-+ if (result) {
-+ goto fail;
-+ }
++ result = mtd_device_register(mtd, NULL, 0);
++ if (result) {
++ goto fail;
++ }
+
-+ return result;
++ return result;
+
+fail:
-+ if (host->buffer) {
-+ dma_free_coherent(host->dev,
-+ (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE),
-+ host->buffer,
-+ host->dma_buffer);
-+ host->buffer = NULL;
-+ }
-+ nand_release(host->mtd);
-+ kfree(host);
-+ platform_set_drvdata(pltdev, NULL);
++ if (host->buffer) {
++ dma_free_coherent(host->dev,
++ (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE),
++ host->buffer,
++ host->dma_buffer);
++ host->buffer = NULL;
++ }
++ nand_release(host->mtd);
++ kfree(host);
++ platform_set_drvdata(pltdev, NULL);
+
-+ return result;
++ return result;
+}
+/*****************************************************************************/
+
+static int hinfc610_os_remove(struct platform_device *pltdev)
+{
-+ struct hinfc_host *host = platform_get_drvdata(pltdev);
++ struct hinfc_host *host = platform_get_drvdata(pltdev);
+
-+ clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk);
+
-+ nand_release(host->mtd);
++ nand_release(host->mtd);
+
-+ dma_free_coherent(host->dev,
-+ (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE),
-+ host->buffer,
-+ host->dma_buffer);
-+ kfree(host);
-+ platform_set_drvdata(pltdev, NULL);
++ dma_free_coherent(host->dev,
++ (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE),
++ host->buffer,
++ host->dma_buffer);
++ kfree(host);
++ platform_set_drvdata(pltdev, NULL);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+#ifdef CONFIG_PM
+static int hinfc610_os_suspend(struct platform_device *pltdev,
-+ pm_message_t state)
++ pm_message_t state)
+{
-+ struct hinfc_host *host = platform_get_drvdata(pltdev);
++ struct hinfc_host *host = platform_get_drvdata(pltdev);
+
-+ while ((hinfc_read(host, HINFC610_STATUS) & 0x1) == 0x0)
-+ ;
++ while ((hinfc_read(host, HINFC610_STATUS) & 0x1) == 0x0)
++ ;
+
-+ while ((hinfc_read(host, HINFC610_DMA_CTRL))
-+ & HINFC610_DMA_CTRL_DMA_START) {
-+ _cond_resched();
-+ }
++ while ((hinfc_read(host, HINFC610_DMA_CTRL))
++ & HINFC610_DMA_CTRL_DMA_START) {
++ _cond_resched();
++ }
+
-+ clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_os_resume(struct platform_device *pltdev)
+{
-+ int cs;
-+ struct hinfc_host *host = platform_get_drvdata(pltdev);
-+ struct nand_chip *chip = host->chip;
++ int cs;
++ struct hinfc_host *host = platform_get_drvdata(pltdev);
++ struct nand_chip *chip = host->chip;
+
-+ clk_prepare_enable(host->clk);
-+ for (cs = 0; cs < chip->numchips; cs++) {
-+ host->send_cmd_reset(host, cs);
-+ }
-+ hinfc_write(host,
-+ SET_HINFC610_PWIDTH(CONFIG_HINFC610_W_LATCH,
-+ CONFIG_HINFC610_R_LATCH, CONFIG_HINFC610_RW_LATCH),
-+ HINFC610_PWIDTH);
++ clk_prepare_enable(host->clk);
++ for (cs = 0; cs < chip->numchips; cs++) {
++ host->send_cmd_reset(host, cs);
++ }
++ hinfc_write(host,
++ SET_HINFC610_PWIDTH(CONFIG_HINFC610_W_LATCH,
++ CONFIG_HINFC610_R_LATCH, CONFIG_HINFC610_RW_LATCH),
++ HINFC610_PWIDTH);
+
-+ return 0;
++ return 0;
+}
+#endif /* CONFIG_PM */
+/*****************************************************************************/
+static const struct of_device_id hisi_nand_dt_ids[] = {
-+ { .compatible = "hisilicon,hisi-parallel-nand" },
-+ { /* sentinel */ }
++ { .compatible = "hisilicon,hisi-parallel-nand" },
++ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, hisi_nand_dt_ids);
+
+static struct platform_driver hisi_nand_driver = {
-+ .driver = {
-+ .name = "hisi-nand",
-+ .of_match_table = hisi_nand_dt_ids,
-+ },
-+ .probe = hinfc610_os_probe,
-+ .remove = hinfc610_os_remove,
++ .driver = {
++ .name = "hisi-nand",
++ .of_match_table = hisi_nand_dt_ids,
++ },
++ .probe = hinfc610_os_probe,
++ .remove = hinfc610_os_remove,
+#ifdef CONFIG_PM
-+ .suspend = hinfc610_os_suspend,
-+ .resume = hinfc610_os_resume,
++ .suspend = hinfc610_os_suspend,
++ .resume = hinfc610_os_resume,
+#endif
+};
+module_platform_driver(hisi_nand_driver);
@@ -297137,7 +365347,7 @@ index 0000000..72ed056
+#endif /* HINFC610_OSH */
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry.c b/drivers/mtd/nand/hinfc610/hinfc610_read_retry.c
new file mode 100644
-index 0000000..1052abb
+index 0000000..f11b623
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_read_retry.c
@@ -0,0 +1,44 @@
@@ -297164,26 +365374,26 @@ index 0000000..1052abb
+#include "hinfc610_read_retry.h"
+
+static struct read_retry_t *read_retry_table[] = {
-+ &hinfc610_hynix_bg_bdie_read_retry,
-+ &hinfc610_hynix_bg_cdie_read_retry,
-+ &hinfc610_hynix_cg_adie_read_retry,
-+ &hinfc610_micron_read_retry,
-+ &hinfc610_toshiba_24nm_read_retry,
-+ &hinfc610_samsung_read_retry,
-+ NULL,
++ &hinfc610_hynix_bg_bdie_read_retry,
++ &hinfc610_hynix_bg_cdie_read_retry,
++ &hinfc610_hynix_cg_adie_read_retry,
++ &hinfc610_micron_read_retry,
++ &hinfc610_toshiba_24nm_read_retry,
++ &hinfc610_samsung_read_retry,
++ NULL,
+};
+
+struct read_retry_t *hinfc610_find_read_retry(int type)
+{
-+ struct read_retry_t **rr;
++ struct read_retry_t **rr;
+
-+ for (rr = read_retry_table; rr; rr++) {
-+ if ((*rr)->type == type) {
-+ return *rr;
-+ }
-+ }
++ for (rr = read_retry_table; rr; rr++) {
++ if ((*rr)->type == type) {
++ return *rr;
++ }
++ }
+
-+ return NULL;
++ return NULL;
+}
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry.h b/drivers/mtd/nand/hinfc610/hinfc610_read_retry.h
new file mode 100644
@@ -297218,7 +365428,7 @@ index 0000000..cfd8880
+
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_bg_bdie.c b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_bg_bdie.c
new file mode 100644
-index 0000000..46f9124
+index 0000000..ea5c5dd
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_bg_bdie.c
@@ -0,0 +1,138 @@
@@ -297252,117 +365462,117 @@ index 0000000..46f9124
+
+static int hinfc610_hynix_bg_bdie_set_rr_reg(struct hinfc_host *host, int index)
+{
-+ int ix;
-+ char HYNIX_BG_BDIE_RR_REG[4] = {0xA7, 0xAD, 0xAE, 0xAF};
-+ char value_offset[7][4] = {
-+ {0x00, 0x00, 0x00, 0x00},
-+ {0x00, 0x06, 0x0A, 0x06},
-+ {0x7F, -0x03, -0x07, -0x08},
-+ {0x7F, -0x06, -0x0D, -0x0F},
-+ {0x7F, -0x09, -0x14, -0x17},
-+ {0x7F, 0x7F, -0x1A, -0x1E},
-+ {0x7F, 0x7F, -0x20, -0x25}
-+ };
-+ char *value = &value_offset[index][0];
++ int ix;
++ char HYNIX_BG_BDIE_RR_REG[4] = {0xA7, 0xAD, 0xAE, 0xAF};
++ char value_offset[7][4] = {
++ {0x00, 0x00, 0x00, 0x00},
++ {0x00, 0x06, 0x0A, 0x06},
++ {0x7F, -0x03, -0x07, -0x08},
++ {0x7F, -0x06, -0x0D, -0x0F},
++ {0x7F, -0x09, -0x14, -0x17},
++ {0x7F, 0x7F, -0x1A, -0x1E},
++ {0x7F, 0x7F, -0x20, -0x25}
++ };
++ char *value = &value_offset[index][0];
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
+
-+ if (!hynix_bg_bdie_rr_org_exist) {
++ if (!hynix_bg_bdie_rr_org_exist) {
+
-+ for (ix = 0; ix < 4; ix++) {
++ for (ix = 0; ix < 4; ix++) {
+
-+ memset(host->chip->IO_ADDR_R, 0xff, 32);
++ memset(host->chip->IO_ADDR_R, 0xff, 32);
+
-+ hinfc_write(host, 0x37, HINFC610_CMD);
-+ hinfc_write(host, HYNIX_BG_BDIE_RR_REG[ix],
-+ HINFC610_ADDRL);
-+ /*
-+ * according to hynix doc, no need to config
-+ * HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA,
-+ HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 0x37, HINFC610_CMD);
++ hinfc_write(host, HYNIX_BG_BDIE_RR_REG[ix],
++ HINFC610_ADDRL);
++ /*
++ * according to hynix doc, no need to config
++ * HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA,
++ HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ hynix_bg_bdie_rr_org[ix]
-+ = (char)(readl(host->chip->IO_ADDR_R) & 0xff);
-+ }
-+ hynix_bg_bdie_rr_org_exist = 1;
-+ }
++ hynix_bg_bdie_rr_org[ix]
++ = (char)(readl(host->chip->IO_ADDR_R) & 0xff);
++ }
++ hynix_bg_bdie_rr_org_exist = 1;
++ }
+
-+ for (ix = 0; ix < 4; ix++) {
-+ if (value[ix] == 0x7F) {
-+ value[ix] = 0x00;
-+ } else {
-+ value[ix] += hynix_bg_bdie_rr_org[ix];
-+ }
-+ }
++ for (ix = 0; ix < 4; ix++) {
++ if (value[ix] == 0x7F) {
++ value[ix] = 0x00;
++ } else {
++ value[ix] += hynix_bg_bdie_rr_org[ix];
++ }
++ }
+
-+ writel(value[0], host->chip->IO_ADDR_W);
-+ hinfc_write(host, HYNIX_BG_BDIE_RR_REG[0], HINFC610_ADDRL);
-+ hinfc_write(host, 0x36, HINFC610_CMD);
-+ /*
-+ * according to hynix doc, no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(value[0], host->chip->IO_ADDR_W);
++ hinfc_write(host, HYNIX_BG_BDIE_RR_REG[0], HINFC610_ADDRL);
++ hinfc_write(host, 0x36, HINFC610_CMD);
++ /*
++ * according to hynix doc, no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ for (ix = 1; ix < 4; ix++) {
-+ writel(value[ix], host->chip->IO_ADDR_W);
-+ hinfc_write(host, HYNIX_BG_BDIE_RR_REG[ix], HINFC610_ADDRL);
-+ /*
-+ * according to hynix doc, no need to config
-+ * HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
-+ }
++ for (ix = 1; ix < 4; ix++) {
++ writel(value[ix], host->chip->IO_ADDR_W);
++ hinfc_write(host, HYNIX_BG_BDIE_RR_REG[ix], HINFC610_ADDRL);
++ /*
++ * according to hynix doc, no need to config
++ * HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
++ }
+
-+ hinfc_write(host, 0x16, HINFC610_CMD);
-+ /*
-+ * according to hynix doc, only 1 cmd: 0x16.
-+ * And no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host, HINFC610_WRITE_1CMD_0ADD_NODATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 0x16, HINFC610_CMD);
++ /*
++ * according to hynix doc, only 1 cmd: 0x16.
++ * And no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host, HINFC610_WRITE_1CMD_0ADD_NODATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_hynix_bg_bdie_set_rr_param(struct hinfc_host *host,
-+ int param)
++ int param)
+{
-+ if (!param) {
-+ return 0;
-+ }
-+ return hinfc610_hynix_bg_bdie_set_rr_reg(host, param);
++ if (!param) {
++ return 0;
++ }
++ return hinfc610_hynix_bg_bdie_set_rr_reg(host, param);
+}
+/*****************************************************************************/
+
+static int hinfc610_hynix_bg_bdie_reset_rr_param(struct hinfc_host *host)
+{
-+ return hinfc610_hynix_bg_bdie_set_rr_param(host, 0);
++ return hinfc610_hynix_bg_bdie_set_rr_param(host, 0);
+}
+/*****************************************************************************/
+
+struct read_retry_t hinfc610_hynix_bg_bdie_read_retry = {
-+ .type = NAND_RR_HYNIX_BG_BDIE,
-+ .count = 7,
-+ .set_rr_param = hinfc610_hynix_bg_bdie_set_rr_param,
-+ .get_rr_param = NULL,
-+ .reset_rr_param = hinfc610_hynix_bg_bdie_reset_rr_param,
++ .type = NAND_RR_HYNIX_BG_BDIE,
++ .count = 7,
++ .set_rr_param = hinfc610_hynix_bg_bdie_set_rr_param,
++ .get_rr_param = NULL,
++ .reset_rr_param = hinfc610_hynix_bg_bdie_reset_rr_param,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_bg_cdie.c b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_bg_cdie.c
new file mode 100644
-index 0000000..a83422c
+index 0000000..482b166
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_bg_cdie.c
@@ -0,0 +1,229 @@
@@ -297391,213 +365601,213 @@ index 0000000..a83422c
+
+static char *hinfc610_hynix_bg_cdie_otp_check(char *otp)
+{
-+ int index = 0;
-+ int ix, jx;
-+ char *ptr = NULL;
-+ int min, cur;
-+ char *otp_origin, *otp_inverse;
++ int index = 0;
++ int ix, jx;
++ char *ptr = NULL;
++ int min, cur;
++ char *otp_origin, *otp_inverse;
+
-+ min = 64;
-+ for (ix = 0; ix < 8; ix++, otp += 128) {
++ min = 64;
++ for (ix = 0; ix < 8; ix++, otp += 128) {
+
-+ otp_origin = otp;
-+ otp_inverse = otp + 64;
-+ cur = 0;
++ otp_origin = otp;
++ otp_inverse = otp + 64;
++ cur = 0;
+
-+ for (jx = 0; jx < 64; jx++, otp_origin++, otp_inverse++) {
-+ if (((*otp_origin) ^ (*otp_inverse)) == 0xFF) {
-+ continue;
-+ }
-+ cur++;
-+ }
++ for (jx = 0; jx < 64; jx++, otp_origin++, otp_inverse++) {
++ if (((*otp_origin) ^ (*otp_inverse)) == 0xFF) {
++ continue;
++ }
++ cur++;
++ }
+
-+ if (cur < min) {
-+ min = cur;
-+ index = ix;
-+ ptr = otp;
-+ if (!cur) {
-+ break;
-+ }
-+ }
-+ }
++ if (cur < min) {
++ min = cur;
++ index = ix;
++ ptr = otp;
++ if (!cur) {
++ break;
++ }
++ }
++ }
+
-+ pr_info("RR select parameter %d from %d, error %d\n",
-+ index, ix, min);
-+ return ptr;
++ pr_info("RR select parameter %d from %d, error %d\n",
++ index, ix, min);
++ return ptr;
+}
+/*****************************************************************************/
+
+static int hinfc610_hynix_bg_cdie_get_rr_param(struct hinfc_host *host)
+{
-+ char *otp;
++ char *otp;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
-+ /* step1: reset the chip */
-+ host->send_cmd_reset(host, host->chipselect);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ /* step1: reset the chip */
++ host->send_cmd_reset(host, host->chipselect);
+
-+ /* step2: cmd: 0x36, address: 0xAE, data: 0x00 */
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
-+ writel(0x00, host->chip->IO_ADDR_R); /* data: 0x00 */
-+ hinfc_write(host, 0xAE, HINFC610_ADDRL);/* address: 0xAE */
-+ hinfc_write(host, 0x36, HINFC610_CMD); /* cmd: 0x36 */
-+ /* according to hynix doc, no need to config
-+ * HINFC610_OP_WAIT_READY_EN */
-+ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step2: cmd: 0x36, address: 0xAE, data: 0x00 */
++ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
++ writel(0x00, host->chip->IO_ADDR_R); /* data: 0x00 */
++ hinfc_write(host, 0xAE, HINFC610_ADDRL);/* address: 0xAE */
++ hinfc_write(host, 0x36, HINFC610_CMD); /* cmd: 0x36 */
++ /* according to hynix doc, no need to config
++ * HINFC610_OP_WAIT_READY_EN */
++ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* step3: address: 0xB0, data: 0x4D */
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
-+ writel(0x4D, host->chip->IO_ADDR_R); /* data: 0x4d */
-+ hinfc_write(host, 0xB0, HINFC610_ADDRL);/* address: 0xB0 */
-+ /* only address and data, without cmd */
-+ /* according to hynix doc, no need to config
-+ * HINFC610_OP_WAIT_READY_EN */
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step3: address: 0xB0, data: 0x4D */
++ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
++ writel(0x4D, host->chip->IO_ADDR_R); /* data: 0x4d */
++ hinfc_write(host, 0xB0, HINFC610_ADDRL);/* address: 0xB0 */
++ /* only address and data, without cmd */
++ /* according to hynix doc, no need to config
++ * HINFC610_OP_WAIT_READY_EN */
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* step4: cmd: 0x16, 0x17, 0x04, 0x19 */
-+ hinfc_write(host, 0x17 << 8 | 0x16, HINFC610_CMD);
-+ /* according to hynix doc, no need to config
-+ * HINFC610_OP_WAIT_READY_EN */
-+ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step4: cmd: 0x16, 0x17, 0x04, 0x19 */
++ hinfc_write(host, 0x17 << 8 | 0x16, HINFC610_CMD);
++ /* according to hynix doc, no need to config
++ * HINFC610_OP_WAIT_READY_EN */
++ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ hinfc_write(host, 0x19 << 8 | 0x04, HINFC610_CMD);
-+ /* according to hynix doc, no need to config
-+ * HINFC610_OP_WAIT_READY_EN */
-+ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 0x19 << 8 | 0x04, HINFC610_CMD);
++ /* according to hynix doc, no need to config
++ * HINFC610_OP_WAIT_READY_EN */
++ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* step5: cmd: 0x00 0x30, address: 0x02 00 00 00 */
-+ hinfc_write(host, 0x2000000, HINFC610_ADDRL);
-+ hinfc_write(host, 0x00, HINFC610_ADDRH);
-+ hinfc_write(host, 0x30 << 8 | 0x00, HINFC610_CMD);
-+ hinfc_write(host, 0x800, HINFC610_DATA_NUM);
-+ /* according to hynix doc, need to config
-+ * HINFC610_OP_WAIT_READY_EN */
-+ hinfc_write(host, HINFC610_READ_2CMD_5ADD, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step5: cmd: 0x00 0x30, address: 0x02 00 00 00 */
++ hinfc_write(host, 0x2000000, HINFC610_ADDRL);
++ hinfc_write(host, 0x00, HINFC610_ADDRH);
++ hinfc_write(host, 0x30 << 8 | 0x00, HINFC610_CMD);
++ hinfc_write(host, 0x800, HINFC610_DATA_NUM);
++ /* according to hynix doc, need to config
++ * HINFC610_OP_WAIT_READY_EN */
++ hinfc_write(host, HINFC610_READ_2CMD_5ADD, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /*step6 save otp read retry table to mem*/
-+ otp = hinfc610_hynix_bg_cdie_otp_check(host->chip->IO_ADDR_R + 2);
-+ if (!otp) {
-+ pr_err("Read Retry select parameter failed, this Nand Chip maybe invalidation.\n");
-+ return -1;
-+ }
-+ memcpy(host->rr_data, otp, 64);
-+ host->need_rr_data = 1;
++ /*step6 save otp read retry table to mem*/
++ otp = hinfc610_hynix_bg_cdie_otp_check(host->chip->IO_ADDR_R + 2);
++ if (!otp) {
++ pr_err("Read Retry select parameter failed, this Nand Chip maybe invalidation.\n");
++ return -1;
++ }
++ memcpy(host->rr_data, otp, 64);
++ host->need_rr_data = 1;
+
-+ /* step7: reset the chip */
-+ host->send_cmd_reset(host, host->chipselect);
++ /* step7: reset the chip */
++ host->send_cmd_reset(host, host->chipselect);
+
-+ /* step8: cmd: 0x38 */
-+ hinfc_write(host, 0x38, HINFC610_CMD);
-+ /* according to hynix doc, need to config HINFC610_OP_WAIT_READY_EN */
-+ hinfc_write(host, HINFC610_WRITE_1CMD_0ADD_NODATA_WAIT_READY,
-+ HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step8: cmd: 0x38 */
++ hinfc_write(host, 0x38, HINFC610_CMD);
++ /* according to hynix doc, need to config HINFC610_OP_WAIT_READY_EN */
++ hinfc_write(host, HINFC610_WRITE_1CMD_0ADD_NODATA_WAIT_READY,
++ HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
-+ /* get hynix otp table finish */
-+ return 0;
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ /* get hynix otp table finish */
++ return 0;
+}
+/*****************************************************************************/
+static char hinfc610_hynix_bg_cdie_rr_reg[8] = {
-+ 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7
++ 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7
+};
+
+static int hinfc610_hynix_bg_cdie_set_rr_reg(struct hinfc_host *host,
-+ char *val)
++ char *val)
+{
-+ int i;
++ int i;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
+
-+ for (i = 0; i <= 8; i++) {
-+ switch (i) {
-+ case 0:
-+ writel(val[i], host->chip->IO_ADDR_R);
-+ hinfc_write(host,
-+ hinfc610_hynix_bg_cdie_rr_reg[i],
-+ HINFC610_ADDRL);
-+ hinfc_write(host,
-+ 0x36, HINFC610_CMD);
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host,
-+ HINFC610_WRITE_1CMD_1ADD_DATA,
-+ HINFC610_OP);
-+ break;
-+ case 8:
-+ hinfc_write(host,
-+ 0x16, HINFC610_CMD);
-+ /*
-+ * according to hynix doc, only 1 cmd: 0x16.
-+ * And no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host,
-+ HINFC610_WRITE_1CMD_0ADD_NODATA,
-+ HINFC610_OP);
-+ break;
-+ default:
-+ writel(val[i], host->chip->IO_ADDR_R);
-+ hinfc_write(host,
-+ hinfc610_hynix_bg_cdie_rr_reg[i],
-+ HINFC610_ADDRL);
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host,
-+ HINFC610_WRITE_0CMD_1ADD_DATA,
-+ HINFC610_OP);
-+ break;
-+ }
-+ WAIT_CONTROLLER_FINISH();
-+ }
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
-+ return 0;
++ for (i = 0; i <= 8; i++) {
++ switch (i) {
++ case 0:
++ writel(val[i], host->chip->IO_ADDR_R);
++ hinfc_write(host,
++ hinfc610_hynix_bg_cdie_rr_reg[i],
++ HINFC610_ADDRL);
++ hinfc_write(host,
++ 0x36, HINFC610_CMD);
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host,
++ HINFC610_WRITE_1CMD_1ADD_DATA,
++ HINFC610_OP);
++ break;
++ case 8:
++ hinfc_write(host,
++ 0x16, HINFC610_CMD);
++ /*
++ * according to hynix doc, only 1 cmd: 0x16.
++ * And no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host,
++ HINFC610_WRITE_1CMD_0ADD_NODATA,
++ HINFC610_OP);
++ break;
++ default:
++ writel(val[i], host->chip->IO_ADDR_R);
++ hinfc_write(host,
++ hinfc610_hynix_bg_cdie_rr_reg[i],
++ HINFC610_ADDRL);
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host,
++ HINFC610_WRITE_0CMD_1ADD_DATA,
++ HINFC610_OP);
++ break;
++ }
++ WAIT_CONTROLLER_FINISH();
++ }
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ return 0;
+}
+
+/*****************************************************************************/
+
+static int hinfc610_hynix_bg_cdie_set_rr_param(struct hinfc_host *host,
-+ int param)
++ int param)
+{
-+ unsigned char *rr;
++ unsigned char *rr;
+
-+ if (!(host->rr_data[0] | host->rr_data[1]
-+ | host->rr_data[2] | host->rr_data[3]) || !param) {
-+ return -1;
-+ }
++ if (!(host->rr_data[0] | host->rr_data[1]
++ | host->rr_data[2] | host->rr_data[3]) || !param) {
++ return -1;
++ }
+
-+ rr = (unsigned char *)&host->rr_data[((param & 0x07) << 3)];
++ rr = (unsigned char *)&host->rr_data[((param & 0x07) << 3)];
+
-+ /* set the read retry regs to adjust reading level */
-+ return hinfc610_hynix_bg_cdie_set_rr_reg(host, (char *)rr);
++ /* set the read retry regs to adjust reading level */
++ return hinfc610_hynix_bg_cdie_set_rr_reg(host, (char *)rr);
+}
+/*****************************************************************************/
+
+static int hinfc610_hynix_bg_cdie_reset_rr_param(struct hinfc_host *host)
+{
-+ return hinfc610_hynix_bg_cdie_set_rr_param(host, 0);
++ return hinfc610_hynix_bg_cdie_set_rr_param(host, 0);
+}
+/*****************************************************************************/
+
+struct read_retry_t hinfc610_hynix_bg_cdie_read_retry = {
-+ .type = NAND_RR_HYNIX_BG_CDIE,
-+ .count = 8,
-+ .set_rr_param = hinfc610_hynix_bg_cdie_set_rr_param,
-+ .get_rr_param = hinfc610_hynix_bg_cdie_get_rr_param,
-+ .reset_rr_param = hinfc610_hynix_bg_cdie_reset_rr_param,
++ .type = NAND_RR_HYNIX_BG_CDIE,
++ .count = 8,
++ .set_rr_param = hinfc610_hynix_bg_cdie_set_rr_param,
++ .get_rr_param = hinfc610_hynix_bg_cdie_get_rr_param,
++ .reset_rr_param = hinfc610_hynix_bg_cdie_reset_rr_param,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_cg_adie.c b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_cg_adie.c
new file mode 100644
-index 0000000..8039876
+index 0000000..b4c8e1d
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_hynix_cg_adie.c
@@ -0,0 +1,238 @@
@@ -297625,223 +365835,223 @@ index 0000000..8039876
+/*****************************************************************************/
+static char *hinfc610_hynix_cg_adie_otp_check(char *otp)
+{
-+ int index = 0;
-+ int ix, jx;
-+ char *ptr = NULL;
-+ int min, cur;
-+ char *otp_origin, *otp_inverse;
++ int index = 0;
++ int ix, jx;
++ char *ptr = NULL;
++ int min, cur;
++ char *otp_origin, *otp_inverse;
+
-+ min = 64;
-+ for (ix = 0; ix < 8; ix++, otp += 128) {
++ min = 64;
++ for (ix = 0; ix < 8; ix++, otp += 128) {
+
-+ otp_origin = otp;
-+ otp_inverse = otp + 64;
-+ cur = 0;
++ otp_origin = otp;
++ otp_inverse = otp + 64;
++ cur = 0;
+
-+ for (jx = 0; jx < 64; jx++, otp_origin++, otp_inverse++) {
-+ if (((*otp_origin) ^ (*otp_inverse)) == 0xFF) {
-+ continue;
-+ }
-+ cur++;
-+ }
++ for (jx = 0; jx < 64; jx++, otp_origin++, otp_inverse++) {
++ if (((*otp_origin) ^ (*otp_inverse)) == 0xFF) {
++ continue;
++ }
++ cur++;
++ }
+
-+ if (cur < min) {
-+ min = cur;
-+ index = ix;
-+ ptr = otp;
-+ if (!cur) {
-+ break;
-+ }
-+ }
-+ }
++ if (cur < min) {
++ min = cur;
++ index = ix;
++ ptr = otp;
++ if (!cur) {
++ break;
++ }
++ }
++ }
+
-+ pr_info("RR select parameter %d from %d, error %d\n",
-+ index, ix, min);
-+ return ptr;
++ pr_info("RR select parameter %d from %d, error %d\n",
++ index, ix, min);
++ return ptr;
+}
+/*****************************************************************************/
+
+static int hinfc610_hynix_cg_adie_get_rr_param(struct hinfc_host *host)
+{
-+ char *otp;
++ char *otp;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
-+ /* step1: reset the chip */
-+ host->send_cmd_reset(host, host->chipselect);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ /* step1: reset the chip */
++ host->send_cmd_reset(host, host->chipselect);
+
-+ /* step2: cmd: 0x36, address: 0xFF, data: 0x40 */
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
-+ writel(0x40, host->chip->IO_ADDR_R); /* data: 0x00 */
-+ hinfc_write(host, 0xFF, HINFC610_ADDRL);/* address: 0xAE */
-+ hinfc_write(host, 0x36, HINFC610_CMD); /* cmd: 0x36 */
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step2: cmd: 0x36, address: 0xFF, data: 0x40 */
++ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
++ writel(0x40, host->chip->IO_ADDR_R); /* data: 0x00 */
++ hinfc_write(host, 0xFF, HINFC610_ADDRL);/* address: 0xAE */
++ hinfc_write(host, 0x36, HINFC610_CMD); /* cmd: 0x36 */
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* step3: address: 0xCC, data: 0x4D */
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
-+ writel(0x4D, host->chip->IO_ADDR_R); /* data: 0x4d */
-+ hinfc_write(host, 0xCC, HINFC610_ADDRL);/* address: 0xB0 */
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ * only address and data, without cmd
-+ */
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step3: address: 0xCC, data: 0x4D */
++ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
++ writel(0x4D, host->chip->IO_ADDR_R); /* data: 0x4d */
++ hinfc_write(host, 0xCC, HINFC610_ADDRL);/* address: 0xB0 */
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ * only address and data, without cmd
++ */
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* step4: cmd: 0x16, 0x17, 0x04, 0x19 */
-+ hinfc_write(host, 0x17 << 8 | 0x16, HINFC610_CMD);
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step4: cmd: 0x16, 0x17, 0x04, 0x19 */
++ hinfc_write(host, 0x17 << 8 | 0x16, HINFC610_CMD);
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ hinfc_write(host, 0x19 << 8 | 0x04, HINFC610_CMD);
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 0x19 << 8 | 0x04, HINFC610_CMD);
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host, HINFC610_WRITE_2CMD_0ADD_NODATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* step5: cmd: 0x00 0x30, address: 0x02 00 00 00 */
-+ hinfc_write(host, 0x2000000, HINFC610_ADDRL);
-+ hinfc_write(host, 0x00, HINFC610_ADDRH);
-+ hinfc_write(host, 0x30 << 8 | 0x00, HINFC610_CMD);
-+ hinfc_write(host, 0x800, HINFC610_DATA_NUM);
-+ /*
-+ * need to config HINFC610_OP_WAIT_READY_EN, here config this bit.
-+ */
-+ hinfc_write(host, HINFC610_READ_2CMD_5ADD, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step5: cmd: 0x00 0x30, address: 0x02 00 00 00 */
++ hinfc_write(host, 0x2000000, HINFC610_ADDRL);
++ hinfc_write(host, 0x00, HINFC610_ADDRH);
++ hinfc_write(host, 0x30 << 8 | 0x00, HINFC610_CMD);
++ hinfc_write(host, 0x800, HINFC610_DATA_NUM);
++ /*
++ * need to config HINFC610_OP_WAIT_READY_EN, here config this bit.
++ */
++ hinfc_write(host, HINFC610_READ_2CMD_5ADD, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /*step6 save otp read retry table to mem*/
-+ otp = hinfc610_hynix_cg_adie_otp_check(host->chip->IO_ADDR_R + 2);
-+ if (!otp) {
-+ pr_err("Read Retry select parameter failed, this Nand Chip maybe invalidation.\n");
-+ return -1;
-+ }
-+ memcpy(host->rr_data, otp, 64);
-+ host->need_rr_data = 1;
++ /*step6 save otp read retry table to mem*/
++ otp = hinfc610_hynix_cg_adie_otp_check(host->chip->IO_ADDR_R + 2);
++ if (!otp) {
++ pr_err("Read Retry select parameter failed, this Nand Chip maybe invalidation.\n");
++ return -1;
++ }
++ memcpy(host->rr_data, otp, 64);
++ host->need_rr_data = 1;
+
-+ /* step7: reset the chip */
-+ host->send_cmd_reset(host, host->chipselect);
++ /* step7: reset the chip */
++ host->send_cmd_reset(host, host->chipselect);
+
-+ /* step8: cmd: 0x38 */
-+ hinfc_write(host, 0x38, HINFC610_CMD);
-+ /*
-+ * need to config HINFC610_OP_WAIT_READY_EN, here config this bit.
-+ */
-+ hinfc_write(host, HINFC610_WRITE_1CMD_0ADD_NODATA_WAIT_READY,
-+ HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* step8: cmd: 0x38 */
++ hinfc_write(host, 0x38, HINFC610_CMD);
++ /*
++ * need to config HINFC610_OP_WAIT_READY_EN, here config this bit.
++ */
++ hinfc_write(host, HINFC610_WRITE_1CMD_0ADD_NODATA_WAIT_READY,
++ HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
-+ /* get hynix otp table finish */
-+ return 0;
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ /* get hynix otp table finish */
++ return 0;
+}
+/*****************************************************************************/
+static char hinfc610_hynix_cg_adie__rr_reg[8] = {
-+ 0xCC, 0xBF, 0xAA, 0xAB, 0xCD, 0xAD, 0xAE, 0xAF
++ 0xCC, 0xBF, 0xAA, 0xAB, 0xCD, 0xAD, 0xAE, 0xAF
+};
+
+static int hinfc610_hynix_cg_adie_set_rr_reg(struct hinfc_host *host, char *val)
+{
-+ int i;
++ int i;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ hinfc_write(host, 1, HINFC610_DATA_NUM);/* data length 1 */
+
-+ for (i = 0; i <= 8; i++) {
-+ switch (i) {
-+ case 0:
-+ writel(val[i], host->chip->IO_ADDR_R);
-+ hinfc_write(host,
-+ hinfc610_hynix_cg_adie__rr_reg[i],
-+ HINFC610_ADDRL);
-+ hinfc_write(host,
-+ 0x36, HINFC610_CMD);
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host,
-+ HINFC610_WRITE_1CMD_1ADD_DATA,
-+ HINFC610_OP);
-+ break;
-+ case 8:
-+ hinfc_write(host,
-+ 0x16, HINFC610_CMD);
-+ /*
-+ * only have 1 cmd: 0x16
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host,
-+ HINFC610_WRITE_1CMD_0ADD_NODATA,
-+ HINFC610_OP);
-+ break;
-+ default:
-+ writel(val[i], host->chip->IO_ADDR_R);
-+ hinfc_write(host,
-+ hinfc610_hynix_cg_adie__rr_reg[i],
-+ HINFC610_ADDRL);
-+ /*
-+ * no need to config HINFC610_OP_WAIT_READY_EN,
-+ * here not config this bit.
-+ */
-+ hinfc_write(host,
-+ HINFC610_WRITE_0CMD_1ADD_DATA,
-+ HINFC610_OP);
-+ break;
-+ }
-+ WAIT_CONTROLLER_FINISH();
-+ }
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
-+ return 0;
++ for (i = 0; i <= 8; i++) {
++ switch (i) {
++ case 0:
++ writel(val[i], host->chip->IO_ADDR_R);
++ hinfc_write(host,
++ hinfc610_hynix_cg_adie__rr_reg[i],
++ HINFC610_ADDRL);
++ hinfc_write(host,
++ 0x36, HINFC610_CMD);
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host,
++ HINFC610_WRITE_1CMD_1ADD_DATA,
++ HINFC610_OP);
++ break;
++ case 8:
++ hinfc_write(host,
++ 0x16, HINFC610_CMD);
++ /*
++ * only have 1 cmd: 0x16
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host,
++ HINFC610_WRITE_1CMD_0ADD_NODATA,
++ HINFC610_OP);
++ break;
++ default:
++ writel(val[i], host->chip->IO_ADDR_R);
++ hinfc_write(host,
++ hinfc610_hynix_cg_adie__rr_reg[i],
++ HINFC610_ADDRL);
++ /*
++ * no need to config HINFC610_OP_WAIT_READY_EN,
++ * here not config this bit.
++ */
++ hinfc_write(host,
++ HINFC610_WRITE_0CMD_1ADD_DATA,
++ HINFC610_OP);
++ break;
++ }
++ WAIT_CONTROLLER_FINISH();
++ }
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ return 0;
+}
+
+/*****************************************************************************/
+
+static int hinfc610_hynix_cg_adie_set_rr_param(struct hinfc_host *host,
-+ int param)
++ int param)
+{
-+ unsigned char *rr;
++ unsigned char *rr;
+
-+ if (!(host->rr_data[0] | host->rr_data[1]
-+ | host->rr_data[2] | host->rr_data[3]) || !param) {
-+ return -1;
-+ }
++ if (!(host->rr_data[0] | host->rr_data[1]
++ | host->rr_data[2] | host->rr_data[3]) || !param) {
++ return -1;
++ }
+
-+ rr = (unsigned char *)&host->rr_data[((param & 0x07) << 3)];
++ rr = (unsigned char *)&host->rr_data[((param & 0x07) << 3)];
+
-+ /* set the read retry regs to adjust reading level */
-+ return hinfc610_hynix_cg_adie_set_rr_reg(host, (char *)rr);
++ /* set the read retry regs to adjust reading level */
++ return hinfc610_hynix_cg_adie_set_rr_reg(host, (char *)rr);
+}
+/*****************************************************************************/
+
+static int hinfc610_hynix_cg_adie_reset_rr_param(struct hinfc_host *host)
+{
-+ return hinfc610_hynix_cg_adie_set_rr_param(host, 0);
++ return hinfc610_hynix_cg_adie_set_rr_param(host, 0);
+}
+/*****************************************************************************/
+
+struct read_retry_t hinfc610_hynix_cg_adie_read_retry = {
-+ .type = NAND_RR_HYNIX_CG_ADIE,
-+ .count = 8,
-+ .set_rr_param = hinfc610_hynix_cg_adie_set_rr_param,
-+ .get_rr_param = hinfc610_hynix_cg_adie_get_rr_param,
-+ .reset_rr_param = hinfc610_hynix_cg_adie_reset_rr_param,
++ .type = NAND_RR_HYNIX_CG_ADIE,
++ .count = 8,
++ .set_rr_param = hinfc610_hynix_cg_adie_set_rr_param,
++ .get_rr_param = hinfc610_hynix_cg_adie_get_rr_param,
++ .reset_rr_param = hinfc610_hynix_cg_adie_reset_rr_param,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry_micron.c b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_micron.c
new file mode 100644
-index 0000000..30b485b
+index 0000000..1aea02f
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_micron.c
@@ -0,0 +1,74 @@
@@ -297872,29 +366082,29 @@ index 0000000..30b485b
+
+static int hinfc610_micron_set_rr_reg(struct hinfc_host *host, int rr)
+{
-+ int regval;
++ int regval;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
+
-+ writel(rr, host->chip->IO_ADDR_W);
-+ hinfc_write(host, MICRON_RR_ADDR, HINFC610_ADDRL);
-+ /* set read retry */
-+ hinfc_write(host, 0xEF, HINFC610_CMD);
++ writel(rr, host->chip->IO_ADDR_W);
++ hinfc_write(host, MICRON_RR_ADDR, HINFC610_ADDRL);
++ /* set read retry */
++ hinfc_write(host, 0xEF, HINFC610_CMD);
+
-+ /* need to config WAIT_READY_EN, here config WAIT_READY_EN bit. */
-+ regval = (HINFC610_IS_SYNC(host) ?
-+ HINFC610_WRITE_1CMD_1ADD_DATA_SYNC_WAIT_READY :
-+ HINFC610_WRITE_1CMD_1ADD_DATA_WAIT_READY);
++ /* need to config WAIT_READY_EN, here config WAIT_READY_EN bit. */
++ regval = (HINFC610_IS_SYNC(host) ?
++ HINFC610_WRITE_1CMD_1ADD_DATA_SYNC_WAIT_READY :
++ HINFC610_WRITE_1CMD_1ADD_DATA_WAIT_READY);
+
-+ hinfc_write(host, regval, HINFC610_OP);
++ hinfc_write(host, regval, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+#undef MICRON_RR_ADDR
@@ -297902,26 +366112,26 @@ index 0000000..30b485b
+
+static int hinfc610_micron_set_rr_param(struct hinfc_host *host, int rr_option)
+{
-+ return hinfc610_micron_set_rr_reg(host, rr_option);
++ return hinfc610_micron_set_rr_reg(host, rr_option);
+}
+/*****************************************************************************/
+
+static int hinfc610_micron_reset_rr_param(struct hinfc_host *host)
+{
-+ return hinfc610_micron_set_rr_reg(host, 0);
++ return hinfc610_micron_set_rr_reg(host, 0);
+}
+/*****************************************************************************/
+
+struct read_retry_t hinfc610_micron_read_retry = {
-+ .type = NAND_RR_MICRON,
-+ .count = 8,
-+ .set_rr_param = hinfc610_micron_set_rr_param,
-+ .get_rr_param = NULL,
-+ .reset_rr_param = hinfc610_micron_reset_rr_param,
++ .type = NAND_RR_MICRON,
++ .count = 8,
++ .set_rr_param = hinfc610_micron_set_rr_param,
++ .get_rr_param = NULL,
++ .reset_rr_param = hinfc610_micron_reset_rr_param,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry_samsung.c b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_samsung.c
new file mode 100644
-index 0000000..122acb2
+index 0000000..a893b28
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_samsung.c
@@ -0,0 +1,110 @@
@@ -297951,65 +366161,65 @@ index 0000000..122acb2
+static int hinfc610_samsung_set_rr_reg(struct hinfc_host *host, int param)
+{
+#define SAMSUNG_RR_CMD 0xA1
-+ int opval;
++ int opval;
+
-+ unsigned char samsung_rr_params[15][4] = {
-+ {0x00, 0x00, 0x00, 0x00},
-+ {0x05, 0x0A, 0x00, 0x00},
-+ {0x28, 0x00, 0xEC, 0xD8},
-+ {0xED, 0xF5, 0xED, 0xE6},
-+ {0x0A, 0x0F, 0x05, 0x00},
-+ {0x0F, 0x0A, 0xFB, 0xEC},
-+ {0xE8, 0xEF, 0xE8, 0xDC},
-+ {0xF1, 0xFB, 0xFE, 0xF0},
-+ {0x0A, 0x00, 0xFB, 0xEC},
-+ {0xD0, 0xE2, 0xD0, 0xC2},
-+ {0x14, 0x0F, 0xFB, 0xEC},
-+ {0xE8, 0xFB, 0xE8, 0xDC},
-+ {0x1E, 0x14, 0xFB, 0xEC},
-+ {0xFB, 0xFF, 0xFB, 0xF8},
-+ {0x07, 0x0C, 0x02, 0x00}
-+ };
++ unsigned char samsung_rr_params[15][4] = {
++ {0x00, 0x00, 0x00, 0x00},
++ {0x05, 0x0A, 0x00, 0x00},
++ {0x28, 0x00, 0xEC, 0xD8},
++ {0xED, 0xF5, 0xED, 0xE6},
++ {0x0A, 0x0F, 0x05, 0x00},
++ {0x0F, 0x0A, 0xFB, 0xEC},
++ {0xE8, 0xEF, 0xE8, 0xDC},
++ {0xF1, 0xFB, 0xFE, 0xF0},
++ {0x0A, 0x00, 0xFB, 0xEC},
++ {0xD0, 0xE2, 0xD0, 0xC2},
++ {0x14, 0x0F, 0xFB, 0xEC},
++ {0xE8, 0xFB, 0xE8, 0xDC},
++ {0x1E, 0x14, 0xFB, 0xEC},
++ {0xFB, 0xFF, 0xFB, 0xF8},
++ {0x07, 0x0C, 0x02, 0x00}
++ };
+
-+ if (param >= 15) {
-+ param = (param % 15);
-+ }
++ if (param >= 15) {
++ param = (param % 15);
++ }
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ /* no need to config WAIT_READY_EN, here not config WAIT_READY_EN bit */
-+ opval = (HINFC610_IS_SYNC(host) ? HINFC610_WRITE_1CMD_2ADD_DATA_SYNC
-+ : HINFC610_WRITE_1CMD_2ADD_DATA);
++ /* no need to config WAIT_READY_EN, here not config WAIT_READY_EN bit */
++ opval = (HINFC610_IS_SYNC(host) ? HINFC610_WRITE_1CMD_2ADD_DATA_SYNC
++ : HINFC610_WRITE_1CMD_2ADD_DATA);
+
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
+
-+ writel(samsung_rr_params[param][0], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0xA700, HINFC610_ADDRL);
-+ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(samsung_rr_params[param][0], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0xA700, HINFC610_ADDRL);
++ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(samsung_rr_params[param][1], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0xA400, HINFC610_ADDRL);
-+ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(samsung_rr_params[param][1], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0xA400, HINFC610_ADDRL);
++ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(samsung_rr_params[param][2], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0xA500, HINFC610_ADDRL);
-+ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(samsung_rr_params[param][2], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0xA500, HINFC610_ADDRL);
++ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(samsung_rr_params[param][3], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0xA600, HINFC610_ADDRL);
-+ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(samsung_rr_params[param][3], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0xA600, HINFC610_ADDRL);
++ hinfc_write(host, SAMSUNG_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+
+#undef SAMSUNG_RR_CMD
+}
@@ -298017,27 +366227,27 @@ index 0000000..122acb2
+
+static int hinfc610_samsung_set_rr_param(struct hinfc_host *host, int param)
+{
-+ return hinfc610_samsung_set_rr_reg(host, param);
++ return hinfc610_samsung_set_rr_reg(host, param);
+}
+/*****************************************************************************/
+
+static int hinfc610_samsung_reset_rr_param(struct hinfc_host *host)
+{
-+ return hinfc610_samsung_set_rr_reg(host, 0);
++ return hinfc610_samsung_set_rr_reg(host, 0);
+}
+/*****************************************************************************/
+
+struct read_retry_t hinfc610_samsung_read_retry = {
-+ .type = NAND_RR_SAMSUNG,
-+ .count = 15,
-+ .set_rr_param = hinfc610_samsung_set_rr_param,
-+ .get_rr_param = NULL,
-+ .reset_rr_param = hinfc610_samsung_reset_rr_param,
++ .type = NAND_RR_SAMSUNG,
++ .count = 15,
++ .set_rr_param = hinfc610_samsung_set_rr_param,
++ .get_rr_param = NULL,
++ .reset_rr_param = hinfc610_samsung_reset_rr_param,
+};
+
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_read_retry_toshiba.c b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_toshiba.c
new file mode 100644
-index 0000000..fab187b
+index 0000000..39267b7
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_read_retry_toshiba.c
@@ -0,0 +1,114 @@
@@ -298067,97 +366277,97 @@ index 0000000..fab187b
+static int hinfc610_toshiba_24nm_set_rr_reg(struct hinfc_host *host, int param)
+{
+#define TOSHIBA_RR_CMD 0x55
-+ int opval;
-+ static char toshiba_rr_param[] = {0x00, 0x04, 0x7c, 0x78, 0x74, 0x08};
++ int opval;
++ static char toshiba_rr_param[] = {0x00, 0x04, 0x7c, 0x78, 0x74, 0x08};
+
-+ if (!param) {
-+ host->send_cmd_reset(host, host->chipselect);
-+ return 0;
-+ }
++ if (!param) {
++ host->send_cmd_reset(host, host->chipselect);
++ return 0;
++ }
+
-+ if (param >= 6) {
-+ param = (param % 6);
-+ }
++ if (param >= 6) {
++ param = (param % 6);
++ }
+
-+ /*
-+ * no need to config WAIT_READY_EN, here not config WAIT_READY_EN
-+ */
-+ opval = (HINFC610_IS_SYNC(host) ? HINFC610_WRITE_1CMD_1ADD_DATA_SYNC
-+ : HINFC610_WRITE_1CMD_1ADD_DATA);
++ /*
++ * no need to config WAIT_READY_EN, here not config WAIT_READY_EN
++ */
++ opval = (HINFC610_IS_SYNC(host) ? HINFC610_WRITE_1CMD_1ADD_DATA_SYNC
++ : HINFC610_WRITE_1CMD_1ADD_DATA);
+
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
+
-+ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0x4, HINFC610_ADDRL);
-+ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0x4, HINFC610_ADDRL);
++ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0x5, HINFC610_ADDRL);
-+ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0x5, HINFC610_ADDRL);
++ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0x6, HINFC610_ADDRL);
-+ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0x6, HINFC610_ADDRL);
++ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
-+ hinfc_write(host, 0x7, HINFC610_ADDRL);
-+ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_rr_param[param], host->chip->IO_ADDR_R);
++ hinfc_write(host, 0x7, HINFC610_ADDRL);
++ hinfc_write(host, TOSHIBA_RR_CMD, HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ return 0;
++ return 0;
+
+#undef TOSHIBA_RR_CMD
+}
+/*****************************************************************************/
+
+static int hinfc610_toshiba_24nm_set_rr_param(struct hinfc_host *host,
-+ int param)
++ int param)
+{
-+ int opval;
++ int opval;
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ opval = (HINFC610_IS_SYNC(host) ? HINFC610_WRITE_2CMD_0ADD_NODATA_SYNC
-+ : HINFC610_WRITE_2CMD_0ADD_NODATA);
++ opval = (HINFC610_IS_SYNC(host) ? HINFC610_WRITE_2CMD_0ADD_NODATA_SYNC
++ : HINFC610_WRITE_2CMD_0ADD_NODATA);
+
-+ hinfc_write(host, HINFC_CMD_SEQ(0x5C, 0xC5), HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, HINFC_CMD_SEQ(0x5C, 0xC5), HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ hinfc610_toshiba_24nm_set_rr_reg(host, param);
++ hinfc610_toshiba_24nm_set_rr_reg(host, param);
+
-+ hinfc_write(host, HINFC_CMD_SEQ(0x26, 0x5D), HINFC610_CMD);
-+ hinfc_write(host, opval, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, HINFC_CMD_SEQ(0x26, 0x5D), HINFC610_CMD);
++ hinfc_write(host, opval, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_toshiba_24nm_reset_rr_param(struct hinfc_host *host)
+{
-+ return hinfc610_toshiba_24nm_set_rr_reg(host, 0);
++ return hinfc610_toshiba_24nm_set_rr_reg(host, 0);
+}
+/*****************************************************************************/
+struct read_retry_t hinfc610_toshiba_24nm_read_retry = {
-+ .type = NAND_RR_TOSHIBA_24nm,
-+ .count = 6,
-+ .set_rr_param = hinfc610_toshiba_24nm_set_rr_param,
-+ .get_rr_param = NULL,
-+ .reset_rr_param = hinfc610_toshiba_24nm_reset_rr_param,
++ .type = NAND_RR_TOSHIBA_24nm,
++ .count = 6,
++ .set_rr_param = hinfc610_toshiba_24nm_set_rr_param,
++ .get_rr_param = NULL,
++ .reset_rr_param = hinfc610_toshiba_24nm_reset_rr_param,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_sync.c b/drivers/mtd/nand/hinfc610/hinfc610_sync.c
new file mode 100644
-index 0000000..bf17e22
+index 0000000..0ab896d
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_sync.c
@@ -0,0 +1,198 @@
@@ -298185,178 +366395,178 @@ index 0000000..bf17e22
+#include "hinfc610_sync.h"
+
+static struct nand_sync *nand_sync_table[] = {
-+ &hinfc610_sync_onfi_23,
-+ &hinfc610_sync_onfi_30,
-+ &hinfc610_sync_toggle_10,
-+ NULL,
++ &hinfc610_sync_onfi_23,
++ &hinfc610_sync_onfi_30,
++ &hinfc610_sync_toggle_10,
++ NULL,
+};
+
+static struct nand_sync *hinfc610_find_sync_type(int type)
+{
-+ struct nand_sync **sync;
++ struct nand_sync **sync;
+
-+ for (sync = nand_sync_table; sync; sync++) {
-+ if ((*sync)->type == type) {
-+ return *sync;
-+ }
-+ }
++ for (sync = nand_sync_table; sync; sync++) {
++ if ((*sync)->type == type) {
++ return *sync;
++ }
++ }
+
-+ return NULL;
++ return NULL;
+}
+/*****************************************************************************/
+
+static int hinfc610_onfi_support_sync(struct hinfc_host *host)
+{
-+ char buf[6] = {0};
++ char buf[6] = {0};
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
-+ hinfc_write(host, 0x20, HINFC610_ADDRL);
-+ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
++ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
++ hinfc_write(host, 0x20, HINFC610_ADDRL);
++ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
-+ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
++ WAIT_CONTROLLER_FINISH();
++ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
+
-+ if (memcmp(buf, "ONFI", 4)) {
-+ return 0;
-+ }
++ if (memcmp(buf, "ONFI", 4)) {
++ return 0;
++ }
+
-+ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
-+ hinfc_write(host, 0x40, HINFC610_ADDRL);
-+ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
++ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
++ hinfc_write(host, 0x40, HINFC610_ADDRL);
++ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
-+ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
++ WAIT_CONTROLLER_FINISH();
++ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
+
-+ if (memcmp(buf, "JEDEC", 5)) {
-+ return 0;
-+ }
++ if (memcmp(buf, "JEDEC", 5)) {
++ return 0;
++ }
+
-+ return (buf[5] == 0x05);
++ return (buf[5] == 0x05);
+}
+/*****************************************************************************/
+
+static int hinfc610_get_onfi_info(struct hinfc_host *host, int *type)
+{
-+ char buf[6] = {0};
++ char buf[6] = {0};
+
-+ *type = 0;
++ *type = 0;
+
-+ if (!hinfc610_onfi_support_sync(host)) {
-+ return 0;
-+ }
++ if (!hinfc610_onfi_support_sync(host)) {
++ return 0;
++ }
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_PARAM, HINFC610_CMD);
-+ hinfc_write(host, 0x00, HINFC610_ADDRL);
-+ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
++ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_PARAM, HINFC610_CMD);
++ hinfc_write(host, 0x00, HINFC610_ADDRL);
++ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
-+ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
++ WAIT_CONTROLLER_FINISH();
++ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
+
-+ if (memcmp(buf, "ONFI", 4)) {
-+ return 0;
-+ }
++ if (memcmp(buf, "ONFI", 4)) {
++ return 0;
++ }
+
-+ if (buf[4] & (1 << 6)) {
-+ *type = NAND_TYPE_ONFI_30;
-+ } else if (buf[4] & (1 << 5) ||
-+ buf[4] & (1 << 4) ||
-+ buf[4] & (1 << 3) ||
-+ buf[4] & (1 << 2)) {
-+ *type = NAND_TYPE_ONFI_23;
-+ }
++ if (buf[4] & (1 << 6)) {
++ *type = NAND_TYPE_ONFI_30;
++ } else if (buf[4] & (1 << 5) ||
++ buf[4] & (1 << 4) ||
++ buf[4] & (1 << 3) ||
++ buf[4] & (1 << 2)) {
++ *type = NAND_TYPE_ONFI_23;
++ }
+
-+ return 1;
++ return 1;
+}
+/*****************************************************************************/
+
+static int hinfc610_toggle_support_sync(struct hinfc_host *host)
+{
-+ char buf[6] = {0};
++ char buf[6] = {0};
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
-+ hinfc_write(host, 0x40, HINFC610_ADDRL);
-+ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
++ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_READID, HINFC610_CMD);
++ hinfc_write(host, 0x40, HINFC610_ADDRL);
++ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
++ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
+
-+ if (memcmp(buf, "JEDEC", 5)) {
-+ return 0;
-+ }
++ if (memcmp(buf, "JEDEC", 5)) {
++ return 0;
++ }
+
-+ return 1;
++ return 1;
+}
+/*****************************************************************************/
+
+static int hinfc610_get_toggle_info(struct hinfc_host *host, int *type)
+{
-+ char buf[8] = {0};
++ char buf[8] = {0};
+
-+ *type = 0;
++ *type = 0;
+
-+ if (!hinfc610_toggle_support_sync(host)) {
-+ return 0;
-+ }
++ if (!hinfc610_toggle_support_sync(host)) {
++ return 0;
++ }
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
-+ hinfc_write(host, NAND_CMD_PARAM, HINFC610_CMD);
-+ hinfc_write(host, 0x40, HINFC610_ADDRL);
-+ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
++ hinfc_write(host, sizeof(buf), HINFC610_DATA_NUM);
++ hinfc_write(host, NAND_CMD_PARAM, HINFC610_CMD);
++ hinfc_write(host, 0x40, HINFC610_ADDRL);
++ hinfc_write(host, HINFC610_READ_1CMD_1ADD_DATA, HINFC610_OP);
+
-+ WAIT_CONTROLLER_FINISH();
++ WAIT_CONTROLLER_FINISH();
+
-+ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
++ memcpy(buf, host->chip->IO_ADDR_R, sizeof(buf));
+
-+ if (memcmp(buf, "JESD", 4)) {
-+ return 0;
-+ }
++ if (memcmp(buf, "JESD", 4)) {
++ return 0;
++ }
+
-+ if (buf[4] & (1 << 1)) {
-+ /* supports revision 1.0 */
-+ *type = NAND_TYPE_TOGGLE_10;
-+ } else {
-+ pr_warn("sync NAND has unknown toggle revision.\n");
-+ }
++ if (buf[4] & (1 << 1)) {
++ /* supports revision 1.0 */
++ *type = NAND_TYPE_TOGGLE_10;
++ } else {
++ pr_warn("sync NAND has unknown toggle revision.\n");
++ }
+
-+ return 1;
++ return 1;
+}
+/*****************************************************************************/
+
+int hinfc610_get_sync_info(struct hinfc_host *host)
+{
-+ int type = 0;
++ int type = 0;
+
-+ if (IS_NAND_ONFI(host)) {
-+ hinfc610_get_onfi_info(host, &type);
-+ } else {
-+ hinfc610_get_toggle_info(host, &type);
-+ }
++ if (IS_NAND_ONFI(host)) {
++ hinfc610_get_onfi_info(host, &type);
++ } else {
++ hinfc610_get_toggle_info(host, &type);
++ }
+
-+ if (!type) {
-+ host->flags &= ~NAND_MODE_SYNC_ASYNC;
-+ return 0;
-+ }
++ if (!type) {
++ host->flags &= ~NAND_MODE_SYNC_ASYNC;
++ return 0;
++ }
+
-+ host->sync = hinfc610_find_sync_type(type);
-+ if (!host->sync) {
-+ PR_BUG(ERSTR_DRIVER
-+ "This Nand Flash need to enable the 'synchronous' feature. "
-+ "but the driver dose not offer the feature");
-+ }
-+ return 0;
++ host->sync = hinfc610_find_sync_type(type);
++ if (!host->sync) {
++ PR_BUG(ERSTR_DRIVER
++ "This Nand Flash need to enable the 'synchronous' feature. "
++ "but the driver dose not offer the feature");
++ }
++ return 0;
+}
+/*****************************************************************************/
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_sync.h b/drivers/mtd/nand/hinfc610/hinfc610_sync.h
@@ -298392,7 +366602,7 @@ index 0000000..906fd10
+
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_sync_onfi_23.c b/drivers/mtd/nand/hinfc610/hinfc610_sync_onfi_23.c
new file mode 100644
-index 0000000..49b0723
+index 0000000..3684e30
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_sync_onfi_23.c
@@ -0,0 +1,107 @@
@@ -298422,90 +366632,90 @@ index 0000000..49b0723
+
+static int hinfc610_onfi_enable_sync(struct nand_chip *chip)
+{
-+ struct hinfc_host *host = chip->priv;
-+ unsigned char micron_sync_param[4] = {
-+ 0x14, /* set sync mode timing */ 0x00, 0x00, 0x00,
-+ };
++ struct hinfc_host *host = chip->priv;
++ unsigned char micron_sync_param[4] = {
++ 0x14, /* set sync mode timing */ 0x00, 0x00, 0x00,
++ };
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
-+ hinfc_write(host, 0xEF, HINFC610_CMD);
-+ hinfc_write(host, 0x01, HINFC610_ADDRL);
-+ writel(micron_sync_param[0], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ hinfc_write(host, 0xEF, HINFC610_CMD);
++ hinfc_write(host, 0x01, HINFC610_ADDRL);
++ writel(micron_sync_param[0], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(micron_sync_param[1], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(micron_sync_param[1], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(micron_sync_param[2], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(micron_sync_param[2], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* need to config WAIT_READY_EN, here config this bit. */
-+ writel(micron_sync_param[3], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_WAIT_READY,
-+ HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* need to config WAIT_READY_EN, here config this bit. */
++ writel(micron_sync_param[3], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_WAIT_READY,
++ HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+
+static int hinfc610_onfi_disable_sync(struct nand_chip *chip)
+{
-+ struct hinfc_host *host = chip->priv;
-+ unsigned char micron_sync_param[4] = {
-+ 0x00, 0x00, 0x00, 0x00,
-+ };
++ struct hinfc_host *host = chip->priv;
++ unsigned char micron_sync_param[4] = {
++ 0x00, 0x00, 0x00, 0x00,
++ };
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
-+ hinfc_write(host, 0xEF, HINFC610_CMD);
-+ hinfc_write(host, 0x01, HINFC610_ADDRL);
-+ writel(micron_sync_param[0], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA_SYNC, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ hinfc_write(host, 0xEF, HINFC610_CMD);
++ hinfc_write(host, 0x01, HINFC610_ADDRL);
++ writel(micron_sync_param[0], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA_SYNC, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(micron_sync_param[1], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(micron_sync_param[1], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(micron_sync_param[2], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(micron_sync_param[2], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(micron_sync_param[3], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC_WAIT_READY,
-+ HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(micron_sync_param[3], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC_WAIT_READY,
++ HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+struct nand_sync hinfc610_sync_onfi_23 = {
-+ .type = NAND_TYPE_ONFI_23,
-+ .enable = hinfc610_onfi_enable_sync,
-+ .disable = hinfc610_onfi_disable_sync,
++ .type = NAND_TYPE_ONFI_23,
++ .enable = hinfc610_onfi_enable_sync,
++ .disable = hinfc610_onfi_disable_sync,
+};
+
+struct nand_sync hinfc610_sync_onfi_30 = {
-+ .type = NAND_TYPE_ONFI_30,
-+ .enable = hinfc610_onfi_enable_sync,
-+ .disable = hinfc610_onfi_disable_sync,
++ .type = NAND_TYPE_ONFI_30,
++ .enable = hinfc610_onfi_enable_sync,
++ .disable = hinfc610_onfi_disable_sync,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc610_sync_toggle.c b/drivers/mtd/nand/hinfc610/hinfc610_sync_toggle.c
new file mode 100644
-index 0000000..c79b630
+index 0000000..cbf3bf2
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc610_sync_toggle.c
@@ -0,0 +1,101 @@
@@ -298535,84 +366745,84 @@ index 0000000..c79b630
+
+static int hinfc610_toggle_enable_sync(struct nand_chip *chip)
+{
-+ struct hinfc_host *host = chip->priv;
-+ unsigned char toshiba_sync_param[4] = {
-+ 0x00, 0x00, 0x00, 0x00,
-+ };
++ struct hinfc_host *host = chip->priv;
++ unsigned char toshiba_sync_param[4] = {
++ 0x00, 0x00, 0x00, 0x00,
++ };
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
-+ hinfc_write(host, 0xEF, HINFC610_CMD);
-+ hinfc_write(host, 0x80, HINFC610_ADDRL);
-+ writel(toshiba_sync_param[0], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ hinfc_write(host, 0xEF, HINFC610_CMD);
++ hinfc_write(host, 0x80, HINFC610_ADDRL);
++ writel(toshiba_sync_param[0], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(toshiba_sync_param[1], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_sync_param[1], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(toshiba_sync_param[2], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_sync_param[2], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* need to config WAIT_READY_EN. */
-+ writel(toshiba_sync_param[3], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_WAIT_READY,
-+ HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* need to config WAIT_READY_EN. */
++ writel(toshiba_sync_param[3], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_WAIT_READY,
++ HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+static int hinfc610_toggle_disable_sync(struct nand_chip *chip)
+{
-+ struct hinfc_host *host = chip->priv;
-+ unsigned char toshiba_sync_param[4] = {
-+ 0x01, 0x00, 0x00, 0x00,
-+ };
++ struct hinfc_host *host = chip->priv;
++ unsigned char toshiba_sync_param[4] = {
++ 0x01, 0x00, 0x00, 0x00,
++ };
+
-+ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
++ host->enable_ecc_randomizer(host, DISABLE, DISABLE);
+
-+ hinfc_write(host, 1, HINFC610_DATA_NUM);
-+ hinfc_write(host, 0xEF, HINFC610_CMD);
-+ hinfc_write(host, 0x80, HINFC610_ADDRL);
-+ writel(toshiba_sync_param[0], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA_SYNC, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ hinfc_write(host, 1, HINFC610_DATA_NUM);
++ hinfc_write(host, 0xEF, HINFC610_CMD);
++ hinfc_write(host, 0x80, HINFC610_ADDRL);
++ writel(toshiba_sync_param[0], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_1CMD_1ADD_DATA_SYNC, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(toshiba_sync_param[1], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_sync_param[1], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ writel(toshiba_sync_param[2], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ writel(toshiba_sync_param[2], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC, HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ /* need to config WAIT_READY_EN */
-+ writel(toshiba_sync_param[3], host->chip->IO_ADDR_R);
-+ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC_WAIT_READY,
-+ HINFC610_OP);
-+ WAIT_CONTROLLER_FINISH();
++ /* need to config WAIT_READY_EN */
++ writel(toshiba_sync_param[3], host->chip->IO_ADDR_R);
++ hinfc_write(host, HINFC610_WRITE_0CMD_1ADD_DATA_SYNC_WAIT_READY,
++ HINFC610_OP);
++ WAIT_CONTROLLER_FINISH();
+
-+ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
++ host->enable_ecc_randomizer(host, ENABLE, ENABLE);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+
+struct nand_sync hinfc610_sync_toggle_10 = {
-+ .type = NAND_TYPE_TOGGLE_10,
-+ .enable = hinfc610_toggle_enable_sync,
-+ .disable = hinfc610_toggle_disable_sync,
++ .type = NAND_TYPE_TOGGLE_10,
++ .enable = hinfc610_toggle_enable_sync,
++ .disable = hinfc610_toggle_disable_sync,
+};
diff --git a/drivers/mtd/nand/hinfc610/hinfc620_gen.c b/drivers/mtd/nand/hinfc610/hinfc620_gen.c
new file mode 100644
-index 0000000..4e82f56
+index 0000000..a1e68f8
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc620_gen.c
@@ -0,0 +1,78 @@
@@ -298640,63 +366850,63 @@ index 0000000..4e82f56
+/*****************************************************************************/
+
+static struct match_reg_type page_type2reg[] = {
-+ {
-+ hinfc620_pagesize_2K, NAND_PAGE_2K,
-+ }, {
-+ hinfc620_pagesize_4K, NAND_PAGE_4K,
-+ }, {
-+ hinfc620_pagesize_8K, NAND_PAGE_8K,
-+ }, {
-+ hinfc620_pagesize_16K, NAND_PAGE_16K,
-+ }, {
-+ hinfc620_pagesize_32K, NAND_PAGE_32K,
-+ }
++ {
++ hinfc620_pagesize_2K, NAND_PAGE_2K,
++ }, {
++ hinfc620_pagesize_4K, NAND_PAGE_4K,
++ }, {
++ hinfc620_pagesize_8K, NAND_PAGE_8K,
++ }, {
++ hinfc620_pagesize_16K, NAND_PAGE_16K,
++ }, {
++ hinfc620_pagesize_32K, NAND_PAGE_32K,
++ }
+};
+
+enum hinfc620_page_reg hinfc620_page_type2reg(int type)
+{
-+ return type2reg(page_type2reg, ARRAY_SIZE(page_type2reg), type, 0);
++ return type2reg(page_type2reg, ARRAY_SIZE(page_type2reg), type, 0);
+}
+
+int hinfc620_page_reg2type(enum hinfc620_page_reg reg)
+{
-+ return reg2type(page_type2reg, ARRAY_SIZE(page_type2reg), reg, 0);
++ return reg2type(page_type2reg, ARRAY_SIZE(page_type2reg), reg, 0);
+}
+/*****************************************************************************/
+
+static struct match_reg_type ecc_type2reg[] = {
-+ {
-+ hinfc620_ecc_none, NAND_ECC_NONE,
-+ }, {
-+ hinfc620_ecc_8bit, NAND_ECC_4BIT_512,
-+ }, {
-+ hinfc620_ecc_16bit, NAND_ECC_8BIT_512,
-+ }, {
-+ hinfc620_ecc_24bit, NAND_ECC_24BIT,
-+ }, {
-+ hinfc620_ecc_40bit, NAND_ECC_40BIT,
-+ }, {
-+ hinfc620_ecc_64bit, NAND_ECC_64BIT,
-+ }, {
-+ hinfc620_ecc_28bit, NAND_ECC_28BIT,
-+ }, {
-+ hinfc620_ecc_42bit, NAND_ECC_42BIT,
-+ }
++ {
++ hinfc620_ecc_none, NAND_ECC_NONE,
++ }, {
++ hinfc620_ecc_8bit, NAND_ECC_4BIT_512,
++ }, {
++ hinfc620_ecc_16bit, NAND_ECC_8BIT_512,
++ }, {
++ hinfc620_ecc_24bit, NAND_ECC_24BIT,
++ }, {
++ hinfc620_ecc_40bit, NAND_ECC_40BIT,
++ }, {
++ hinfc620_ecc_64bit, NAND_ECC_64BIT,
++ }, {
++ hinfc620_ecc_28bit, NAND_ECC_28BIT,
++ }, {
++ hinfc620_ecc_42bit, NAND_ECC_42BIT,
++ }
+};
+
+enum hinfc620_ecc_reg hinfc620_ecc_type2reg(int type)
+{
-+ return type2reg(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), type, 0);
++ return type2reg(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), type, 0);
+}
+
+int hinfc620_ecc_reg2type(enum hinfc620_ecc_reg reg)
+{
-+ return reg2type(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), reg, 0);
++ return reg2type(ecc_type2reg, ARRAY_SIZE(ecc_type2reg), reg, 0);
+}
+
diff --git a/drivers/mtd/nand/hinfc610/hinfc620_gen.h b/drivers/mtd/nand/hinfc610/hinfc620_gen.h
new file mode 100644
-index 0000000..1cf23b9
+index 0000000..88fb1e4
--- /dev/null
+++ b/drivers/mtd/nand/hinfc610/hinfc620_gen.h
@@ -0,0 +1,53 @@
@@ -298725,22 +366935,22 @@ index 0000000..1cf23b9
+#include "../hinfc_gen.h"
+
+enum hinfc620_ecc_reg {
-+ hinfc620_ecc_none = 0x00,
-+ hinfc620_ecc_8bit = 0x02,
-+ hinfc620_ecc_16bit = 0x03,
-+ hinfc620_ecc_24bit = 0x04,
-+ hinfc620_ecc_40bit = 0x05,
-+ hinfc620_ecc_64bit = 0x06,
-+ hinfc620_ecc_28bit = 0x07,
-+ hinfc620_ecc_42bit = 0x08,
++ hinfc620_ecc_none = 0x00,
++ hinfc620_ecc_8bit = 0x02,
++ hinfc620_ecc_16bit = 0x03,
++ hinfc620_ecc_24bit = 0x04,
++ hinfc620_ecc_40bit = 0x05,
++ hinfc620_ecc_64bit = 0x06,
++ hinfc620_ecc_28bit = 0x07,
++ hinfc620_ecc_42bit = 0x08,
+};
+
+enum hinfc620_page_reg {
-+ hinfc620_pagesize_2K = 0x01,
-+ hinfc620_pagesize_4K = 0x02,
-+ hinfc620_pagesize_8K = 0x03,
-+ hinfc620_pagesize_16K = 0x04,
-+ hinfc620_pagesize_32K = 0x05,
++ hinfc620_pagesize_2K = 0x01,
++ hinfc620_pagesize_4K = 0x02,
++ hinfc620_pagesize_8K = 0x03,
++ hinfc620_pagesize_16K = 0x04,
++ hinfc620_pagesize_32K = 0x05,
+};
+
+enum hinfc620_page_reg hinfc620_page_type2reg(int type);
@@ -298755,10 +366965,10 @@ index 0000000..1cf23b9
+#endif /* HINFC620_GENH */
diff --git a/drivers/mtd/nand/hinfc_gen.c b/drivers/mtd/nand/hinfc_gen.c
new file mode 100644
-index 0000000..d899ff4
+index 0000000..63273d7
--- /dev/null
+++ b/drivers/mtd/nand/hinfc_gen.c
-@@ -0,0 +1,244 @@
+@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
@@ -298776,7 +366986,7 @@ index 0000000..d899ff4
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
-+
++
+#include <linux/mfd/hisi_fmc.h>
+#include "match_table.h"
+#include "hinfc_gen.h"
@@ -298813,15 +367023,16 @@ index 0000000..d899ff4
+const char *nand_ecc_name(int type)
+{
+ return (char *)match_type_to_data(match_ecc, ARRAY_SIZE(match_ecc),
-+ type, "unknown");
++ type, "unknown");
+}
+
+char *get_ecctype_str(enum ecc_type ecctype)
+{
+ static char *ecctype_string[] = {
+ "None", "1bit/512Byte", "4bits/512Byte", "8bits/512Byte",
-+ "24bits/1K", "40bits/1K", "unknown", "unknown"};
-+ return ecctype_string[(ecctype & 0x07)];
++ "24bits/1K", "40bits/1K", "unknown", "unknown"
++ };
++ return ecctype_string[((unsigned int)ecctype & 0x07)];
+}
+
+/*****************************************************************************/
@@ -298843,8 +367054,9 @@ index 0000000..d899ff4
+{
+ static char *pagesize_str[] = {
+ "512", "2K", "4K", "8K", "16K", "unknown",
-+ "unknown", "unknown"};
-+ return pagesize_str[(pagetype & 0x07)];
++ "unknown", "unknown"
++ };
++ return pagesize_str[((unsigned int)pagetype & 0x07)];
+}
+
+/*****************************************************************************/
@@ -298860,8 +367072,9 @@ index 0000000..d899ff4
+unsigned int get_pagesize(enum page_type pagetype)
+{
+ unsigned int pagesize[] = {
-+ _512B, _2K, _4K, _8K, _16K, 0, 0, 0};
-+ return pagesize[(pagetype & 0x07)];
++ _512B, _2K, _4K, _8K, _16K, 0, 0, 0
++ };
++ return pagesize[((unsigned int)pagetype & 0x07)];
+}
+
+int nandpage_size2type(int size)
@@ -298940,19 +367153,19 @@ index 0000000..d899ff4
+unsigned char match_page_reg_to_type(unsigned char reg)
+{
+ return match_reg_to_type(page_table, ARRAY_SIZE(page_table), reg,
-+ NAND_PAGE_2K);
++ NAND_PAGE_2K);
+}
+
+unsigned char match_page_type_to_reg(unsigned char type)
+{
+ return match_type_to_reg(page_table, ARRAY_SIZE(page_table), type,
-+ PAGE_SIZE_2KB);
++ PAGE_SIZE_2KB);
+}
+
+const char *match_page_type_to_str(unsigned char type)
+{
+ return match_type_to_data(page_table, ARRAY_SIZE(page_table), type,
-+ "unknown");
++ "unknown");
+}
+
+/*****************************************************************************/
@@ -298969,19 +367182,19 @@ index 0000000..d899ff4
+unsigned char match_ecc_reg_to_type(unsigned char reg)
+{
+ return match_reg_to_type(ecc_table, ARRAY_SIZE(ecc_table), reg,
-+ NAND_ECC_8BIT);
++ NAND_ECC_8BIT);
+}
+
+unsigned char match_ecc_type_to_reg(unsigned char type)
+{
+ return match_type_to_reg(ecc_table, ARRAY_SIZE(ecc_table), type,
-+ ECC_TYPE_8BIT);
++ ECC_TYPE_8BIT);
+}
+
+const char *match_ecc_type_to_str(unsigned char type)
+{
+ return match_type_to_data(ecc_table, ARRAY_SIZE(ecc_table), type,
-+ "unknown");
++ "unknown");
+}
+
+/*****************************************************************************/
@@ -298995,17 +367208,17 @@ index 0000000..d899ff4
+unsigned char match_page_size_to_type(unsigned int size)
+{
+ return match_reg_to_type(page_type_size_table,
-+ ARRAY_SIZE(page_type_size_table), size, NAND_PAGE_2K);
++ ARRAY_SIZE(page_type_size_table), size, NAND_PAGE_2K);
+}
+
+unsigned int match_page_type_to_size(unsigned char type)
+{
+ return match_type_to_reg(page_type_size_table,
-+ ARRAY_SIZE(page_type_size_table), type, _2K);
++ ARRAY_SIZE(page_type_size_table), type, _2K);
+}
diff --git a/drivers/mtd/nand/hinfc_gen.h b/drivers/mtd/nand/hinfc_gen.h
new file mode 100644
-index 0000000..3d08c70
+index 0000000..2e8e77d
--- /dev/null
+++ b/drivers/mtd/nand/hinfc_gen.h
@@ -0,0 +1,294 @@
@@ -299175,22 +367388,22 @@ index 0000000..3d08c70
+ /* (Controller) is sync, default is async */
+#define NANDC_IS_SYNC_BOOT 0x04
+
-+/* (NAND) need randomizer */
++ /* (NAND) need randomizer */
+#define NAND_RANDOMIZER 0x10
-+/* (NAND) is ONFI interface, combine with sync/async symble */
++ /* (NAND) is ONFI interface, combine with sync/async symble */
+#define NAND_IS_ONFI 0x20
-+/* (NAND) support async and sync, such micron onfi, toshiba toggle 1.0 */
++ /* (NAND) support async and sync, such micron onfi, toshiba toggle 1.0 */
+#define NAND_MODE_SYNC_ASYNC 0x40
-+/* (NAND) support only sync, such samsung sync. */
++ /* (NAND) support only sync, such samsung sync. */
+#define NAND_MODE_ONLY_SYNC 0x80
+
+#define NAND_CHIP_MICRON (NAND_MODE_SYNC_ASYNC | NAND_IS_ONFI)
-+/* This NAND is async, or sync/async, default is async mode,
-+ * toggle1.0 interface */
++ /* This NAND is async, or sync/async, default is async mode,
++ * toggle1.0 interface */
+#define NAND_CHIP_TOSHIBA_TOGGLE_10 (NAND_MODE_SYNC_ASYNC)
-+/* This NAND is only sync mode, toggle2.0 interface */
++ /* This NAND is only sync mode, toggle2.0 interface */
+#define NAND_CHIP_TOSHIBA_TOGGLE_20 (NAND_MODE_ONLY_SYNC)
-+/* This NAND is only sync mode */
++ /* This NAND is only sync mode */
+#define NAND_CHIP_SAMSUNG (NAND_MODE_ONLY_SYNC)
+
+ unsigned int flags;
@@ -299241,23 +367454,23 @@ index 0000000..3d08c70
+
+/*****************************************************************************/
+extern int (*hinfc_param_adjust)(struct mtd_info *mtd, struct nand_chip *chip,
-+ struct nand_dev_t *nand_dev);
++ struct nand_dev_t *nand_dev);
+
+extern struct nand_flash_dev *(*nand_get_flash_type_func)(struct mtd_info *mtd,
-+ struct nand_chip *chip, struct nand_dev_t *spinand_dev_t);
++ struct nand_chip *chip, struct nand_dev_t *spinand_dev_t);
+
+extern struct nand_flash_dev *(*get_spi_nand_flash_type_hook)
-+ (struct mtd_info *mtd, unsigned char *id);
++(struct mtd_info *mtd, unsigned char *id);
+
+extern int (*hinfc_param_adjust)(struct mtd_info *,
-+ struct nand_chip *, struct nand_dev_t *);
++ struct nand_chip *, struct nand_dev_t *);
+
+/*****************************************************************************/
+struct nand_flash_dev *hinfc_get_flash_type(struct mtd_info *mtd,
-+ struct nand_chip *chip, u8 *id_data, int *busw);
++ struct nand_chip *chip, u8 *id_data, int *busw);
+
+extern struct nand_flash_dev *(*get_spi_nand_flash_type_hook)
-+ (struct mtd_info *mtd, unsigned char *id);
++(struct mtd_info *mtd, unsigned char *id);
+
+void hinfc_nand_param_adjust(struct mtd_info *mtd, struct nand_chip *chip);
+
@@ -299305,10 +367518,10 @@ index 0000000..3d08c70
+#endif /* End of __HINFC_GEN_H__ */
diff --git a/drivers/mtd/nand/hinfc_spl_ids.c b/drivers/mtd/nand/hinfc_spl_ids.c
new file mode 100644
-index 0000000..ccc15de
+index 0000000..5163569
--- /dev/null
+++ b/drivers/mtd/nand/hinfc_spl_ids.c
-@@ -0,0 +1,979 @@
+@@ -0,0 +1,980 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
@@ -299365,7 +367578,8 @@ index 0000000..ccc15de
+ int pagesizes[] = {SZ_2K, SZ_4K, SZ_8K, 0};
+ int oobsizes[] = {128, 224, 448, 0, 0, 0, 0, 0};
+ int blocksizes[] = {SZ_128K, SZ_256K, SZ_512K,
-+ (SZ_256K + SZ_512K), SZ_1M, SZ_2M, 0, 0};
++ (SZ_256K + SZ_512K), SZ_1M, SZ_2M, 0, 0
++ };
+
+ int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
+ int oobtype = (((id[3] >> 2) & 0x03) | ((id[3] >> 4) & 0x04));
@@ -299468,7 +367682,7 @@ index 0000000..ccc15de
+
+static struct nand_flash_special_dev nand_flash_special_dev[] = {
+
-+/****************************** Spansion *******************************/
++ /****************************** Spansion *******************************/
+
+ { /* SLC S34ML02G200TFI000 */
+ .name = "S34ML02G200TFI000",
@@ -299500,7 +367714,7 @@ index 0000000..ccc15de
+ .flags = 0,
+ },
+
-+/****************************** Micron *******************************/
++ /****************************** Micron *******************************/
+ { /* MLC 40bit/1k */
+ .name = "MT29F64G08CBABA",
+ .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
@@ -299698,7 +367912,7 @@ index 0000000..ccc15de
+ .flags = 0,
+ },
+
-+/****************************** Toshaba *******************************/
++ /****************************** Toshaba *******************************/
+
+ { /* MLC 24bit/1k 32nm */
+ .name = "TC58NVG4D2FTA00",
@@ -299944,7 +368158,7 @@ index 0000000..ccc15de
+ .badblock_pos = BBP_FIRST_PAGE | BBP_LAST_PAGE,
+ .flags = NAND_RANDOMIZER,
+ },
-+/******************************* Samsung ******************************/
++ /******************************* Samsung ******************************/
+ { /* MLC 8bit/512B */
+ .name = "K9LB(HC/PD/MD)G08U0(1)D",
+ .id = {0xEC, 0xD7, 0xD5, 0x29, 0x38, 0x41, 0x00, 0x00},
@@ -300042,7 +368256,7 @@ index 0000000..ccc15de
+ .flags = NAND_RANDOMIZER,
+ },
+
-+/*********************************** Hynix ****************************/
++ /*********************************** Hynix ****************************/
+ { /* MLC */
+ .name = "H27UAG8T2A",
+ .id = {0xAD, 0xD5, 0x94, 0x25, 0x44, 0x41, },
@@ -300116,7 +368330,7 @@ index 0000000..ccc15de
+ .flags = NAND_RANDOMIZER,
+ },
+
-+/********************** MISC ******************************************/
++ /********************** MISC ******************************************/
+ { /* MLC 8bit/512 */
+ .name = "P1UAGA30AT-GCA",
+ .id = {0xC8, 0xD5, 0x14, 0x29, 0x34, 0x01, },
@@ -300170,23 +368384,23 @@ index 0000000..ccc15de
+ (sizeof(nand_flash_special_dev)/sizeof(struct nand_flash_special_dev))
+
+int (*hinfc_param_adjust)(struct mtd_info *, struct nand_chip *,
-+ struct nand_dev_t *) = NULL;
++ struct nand_dev_t *) = NULL;
+
+static struct nand_dev_t __nand_dev;
+/*****************************************************************************/
+
+static struct nand_flash_dev *hinfc_nand_probe(struct mtd_info *mtd,
-+ struct nand_chip *chip,
-+ struct nand_dev_t *nand_dev)
++ struct nand_chip *chip,
++ struct nand_dev_t *nand_dev)
+{
-+ struct nand_flash_special_dev *spl_dev;
++ struct nand_flash_special_dev *spl_dev = NULL;
+ unsigned char *byte = nand_dev->ids;
+ struct nand_flash_dev *type = &nand_dev->flash_dev;
+
+ hinfc_pr_msg("Nand ID: 0x%02X 0x%02X 0x%02X 0x%02X",
-+ byte[0], byte[1], byte[2], byte[3]);
++ byte[0], byte[1], byte[2], byte[3]);
+ hinfc_pr_msg(" 0x%02X 0x%02X 0x%02X 0x%02X\n",
-+ byte[4], byte[5], byte[6], byte[7]);
++ byte[4], byte[5], byte[6], byte[7]);
+
+ for (spl_dev = nand_flash_special_dev; spl_dev->length; spl_dev++) {
+ if (memcmp(byte, spl_dev->id, spl_dev->length))
@@ -300218,10 +368432,10 @@ index 0000000..ccc15de
+/*****************************************************************************/
+
+struct nand_flash_dev *hinfc_get_flash_type(struct mtd_info *mtd,
-+ struct nand_chip *chip,
-+ u8 *id_data, int *busw)
++ struct nand_chip *chip,
++ u8 *id_data, int *busw)
+{
-+ struct nand_flash_dev *type;
++ struct nand_flash_dev *type = NULL;
+ struct nand_dev_t *nand_dev = &__nand_dev;
+
+ memset(nand_dev, 0, sizeof(struct nand_dev_t));
@@ -300364,7 +368578,7 @@ index 0000000..4ed5f59
+
diff --git a/drivers/mtd/nand/hisnfc100/hisnfc100.c b/drivers/mtd/nand/hisnfc100/hisnfc100.c
new file mode 100644
-index 0000000..c68d3c5
+index 0000000..40764a5
--- /dev/null
+++ b/drivers/mtd/nand/hisnfc100/hisnfc100.c
@@ -0,0 +1,1049 @@
@@ -300401,678 +368615,678 @@ index 0000000..c68d3c5
+/*****************************************************************************/
+static void hisnfc100_send_cmd_pageprog(struct hisnfc_host *host)
+{
-+ unsigned char pages_per_block_shift;
-+ unsigned val, block_num, block_num_h, page_num;
-+ struct hisnfc_op *spi = host->spi;
-+ struct nand_chip *chip = host->chip;
++ unsigned char pages_per_block_shift;
++ unsigned val, block_num, block_num_h, page_num;
++ struct hisnfc_op *spi = host->spi;
++ struct nand_chip *chip = host->chip;
+#ifdef HISNFC100_SUPPORT_REG_WRITE
-+ const char *op_type = "reg";
++ const char *op_type = "reg";
+#else
-+ const char *op_type = "dma";
++ const char *op_type = "dma";
+#endif
+
-+ if (DEBUG_WRITE) {
-+ pr_info("* Enter %s page program!\n", op_type);
-+ }
++ if (DEBUG_WRITE) {
++ pr_info("* Enter %s page program!\n", op_type);
++ }
+
-+ val = spi->driver->wait_ready(spi);
-+ if (val) {
-+ pr_info("%s: %s page program wait ready fail! status[%#x]\n",
-+ __func__, op_type, val);
-+ return;
-+ }
++ val = spi->driver->wait_ready(spi);
++ if (val) {
++ pr_info("%s: %s page program wait ready fail! status[%#x]\n",
++ __func__, op_type, val);
++ return;
++ }
+
-+ if (spi->driver->write_enable(spi)) {
-+ pr_info("%s %s page program write enable failed!\n", __func__,
-+ op_type);
-+ return;
-+ }
++ if (spi->driver->write_enable(spi)) {
++ pr_info("%s %s page program write enable failed!\n", __func__,
++ op_type);
++ return;
++ }
+
-+ host->set_system_clock(spi->write, ENABLE);
++ host->set_system_clock(spi->write, ENABLE);
+
-+ val = HISNFC100_INT_CLR_ALL;
-+ hisfc_write(host, HISNFC100_INT_CLR, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG INT_CLR[0x14]%#x\n", val);
-+ }
++ val = HISNFC100_INT_CLR_ALL;
++ hisfc_write(host, HISNFC100_INT_CLR, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG INT_CLR[0x14]%#x\n", val);
++ }
+
-+ val = HISNFC100_OP_CFG_MEM_IF_TYPE(spi->write->iftype);
-+ hisfc_write(host, HISNFC100_OP_CFG, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG OP_CFG[0x28]%#x\n", val);
-+ }
++ val = HISNFC100_OP_CFG_MEM_IF_TYPE(spi->write->iftype);
++ hisfc_write(host, HISNFC100_OP_CFG, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG OP_CFG[0x28]%#x\n", val);
++ }
+
-+ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
-+ block_num = host->addr_value[1] >> pages_per_block_shift;
-+ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
-+ val = HISNFC100_ADDRH_SET(block_num_h);
-+ hisfc_write(host, HISNFC100_ADDRH, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG ADDRH[0x2c]%#x\n", val);
-+ }
++ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
++ block_num = host->addr_value[1] >> pages_per_block_shift;
++ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
++ val = HISNFC100_ADDRH_SET(block_num_h);
++ hisfc_write(host, HISNFC100_ADDRH, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG ADDRH[0x2c]%#x\n", val);
++ }
+
-+ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
-+ val = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
-+ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT);
-+ hisfc_write(host, HISNFC100_ADDRL, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG ADDRL[0x30]%#x\n", val);
-+ }
++ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
++ val = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
++ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT);
++ hisfc_write(host, HISNFC100_ADDRL, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG ADDRL[0x30]%#x\n", val);
++ }
+
+#ifndef HISNFC100_SUPPORT_REG_WRITE
-+ val = HISNFC100_DMA_CTRL_ALL_ENABLE;
-+ hisfc_write(host, HISNFC100_DMA_CTRL, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG DMA_CTRL[0x3c]%#x\n", val);
-+ }
++ val = HISNFC100_DMA_CTRL_ALL_ENABLE;
++ hisfc_write(host, HISNFC100_DMA_CTRL, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG DMA_CTRL[0x3c]%#x\n", val);
++ }
+
-+ val = host->dma_buffer;
-+ hisfc_write(host, HISNFC100_DMA_SADDR_D, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG DMA_SADDR_D[0x40]%#x\n", val);
-+ }
++ val = host->dma_buffer;
++ hisfc_write(host, HISNFC100_DMA_SADDR_D, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG DMA_SADDR_D[0x40]%#x\n", val);
++ }
+
-+ val = host->dma_oob;
-+ hisfc_write(host, HISNFC100_DMA_SADDR_OOB, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG DMA_SADDR_OOB[%#x]%#x\n",
-+ HISNFC100_DMA_SADDR_OOB, val);
-+ }
++ val = host->dma_oob;
++ hisfc_write(host, HISNFC100_DMA_SADDR_OOB, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG DMA_SADDR_OOB[%#x]%#x\n",
++ HISNFC100_DMA_SADDR_OOB, val);
++ }
+#endif
+
-+ val = HISNFC100_OP_CTRL_WR_OPCODE(spi->write->cmd)
-+ | HISNFC100_OP_CTRL_CS_OP(host->cmd_option.chipselect)
++ val = HISNFC100_OP_CTRL_WR_OPCODE(spi->write->cmd)
++ | HISNFC100_OP_CTRL_CS_OP(host->cmd_option.chipselect)
+#ifdef HISNFC100_SUPPORT_REG_WRITE
-+ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_REG)
++ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_REG)
+#else
-+ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_DMA)
++ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_DMA)
+#endif
-+ | HISNFC100_OP_CTRL_RW_OP(RW_OP_WRITE)
-+ | HISNFC100_OP_CTRL_OP_READY;
-+ hisfc_write(host, HISNFC100_OP_CTRL, val);
-+ if (DEBUG_WRITE) {
-+ pr_info(" Set REG OP_CTRL[0x34]%#x\n", val);
-+ }
++ | HISNFC100_OP_CTRL_RW_OP(RW_OP_WRITE)
++ | HISNFC100_OP_CTRL_OP_READY;
++ hisfc_write(host, HISNFC100_OP_CTRL, val);
++ if (DEBUG_WRITE) {
++ pr_info(" Set REG OP_CTRL[0x34]%#x\n", val);
++ }
+
-+ HISNFC100_DMA_WAIT_INT_FINISH(host);
++ HISNFC100_DMA_WAIT_INT_FINISH(host);
+
-+ if (DEBUG_WRITE) {
-+ val = spi->driver->wait_ready(spi);
-+ if (val & STATUS_P_FAIL_MASK) {
-+ pr_info("hisnfc100: %s page program failed!" \
-+ " status[%#x]\n", op_type, val);
-+ }
-+ }
++ if (DEBUG_WRITE) {
++ val = spi->driver->wait_ready(spi);
++ if (val & STATUS_P_FAIL_MASK) {
++ pr_info("hisnfc100: %s page program failed!" \
++ " status[%#x]\n", op_type, val);
++ }
++ }
+
-+ if (DEBUG_WRITE) {
-+ pr_info("* End %s page program!\n", op_type);
-+ }
++ if (DEBUG_WRITE) {
++ pr_info("* End %s page program!\n", op_type);
++ }
+}
+
+/*****************************************************************************/
+static void hisnfc100_send_cmd_readstart(struct hisnfc_host *host)
+{
-+ unsigned char pages_per_block_shift, only_oob = 0;
-+ unsigned short wrap = 0;
-+ unsigned val, block_num, block_num_h, page_num, addr_of = 0;
-+ struct hisnfc_op *spi = host->spi;
-+ struct nand_chip *chip = host->chip;
++ unsigned char pages_per_block_shift, only_oob = 0;
++ unsigned short wrap = 0;
++ unsigned val, block_num, block_num_h, page_num, addr_of = 0;
++ struct hisnfc_op *spi = host->spi;
++ struct nand_chip *chip = host->chip;
+#ifdef HISNFC100_SUPPORT_REG_READ
-+ char *op_type = "reg";
++ char *op_type = "reg";
+#else
-+ char *op_type = "dma";
++ char *op_type = "dma";
+#endif
+
-+ if (DEBUG_READ) {
-+ pr_info("* Enter %s page read start!\n", op_type);
-+ }
++ if (DEBUG_READ) {
++ pr_info("* Enter %s page read start!\n", op_type);
++ }
+
-+ if ((host->addr_value[0] == host->cache_addr_value[0])
-+ && (host->addr_value[1] == host->cache_addr_value[1])) {
-+ if (DEBUG_READ) {
-+ pr_info("* %s page read cache hit! addr1[%#x], " \
-+ "addr0[%#x]\n", op_type, host->addr_value[1],
-+ host->addr_value[0]);
-+ }
-+ return;
-+ }
++ if ((host->addr_value[0] == host->cache_addr_value[0])
++ && (host->addr_value[1] == host->cache_addr_value[1])) {
++ if (DEBUG_READ) {
++ pr_info("* %s page read cache hit! addr1[%#x], " \
++ "addr0[%#x]\n", op_type, host->addr_value[1],
++ host->addr_value[0]);
++ }
++ return;
++ }
+
-+ val = spi->driver->wait_ready(spi);
-+ if (val) {
-+ pr_info("%s: %s read wait ready fail! status[%#x]\n", __func__,
-+ op_type, val);
-+ return;
-+ }
++ val = spi->driver->wait_ready(spi);
++ if (val) {
++ pr_info("%s: %s read wait ready fail! status[%#x]\n", __func__,
++ op_type, val);
++ return;
++ }
+
-+ host->set_system_clock(spi->read, ENABLE);
++ host->set_system_clock(spi->read, ENABLE);
+
-+ val = HISNFC100_INT_CLR_ALL;
-+ hisfc_write(host, HISNFC100_INT_CLR, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG INT_CLR[0x14]%#x\n", val);
-+ }
++ val = HISNFC100_INT_CLR_ALL;
++ hisfc_write(host, HISNFC100_INT_CLR, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG INT_CLR[0x14]%#x\n", val);
++ }
+
-+ if (host->cmd_option.last_cmd == NAND_CMD_READOOB) {
-+ only_oob = 1;
-+ host->cmd_option.op_config =
-+ HISNFC100_OP_CFG_RD_OP_SEL(RD_OP_READ_OOB);
-+ } else {
-+ host->cmd_option.op_config =
-+ HISNFC100_OP_CFG_RD_OP_SEL(RD_OP_READ_PAGE);
-+ }
++ if (host->cmd_option.last_cmd == NAND_CMD_READOOB) {
++ only_oob = 1;
++ host->cmd_option.op_config =
++ HISNFC100_OP_CFG_RD_OP_SEL(RD_OP_READ_OOB);
++ } else {
++ host->cmd_option.op_config =
++ HISNFC100_OP_CFG_RD_OP_SEL(RD_OP_READ_PAGE);
++ }
+
-+ val = host->cmd_option.op_config
-+ | HISNFC100_OP_CFG_MEM_IF_TYPE(spi->read->iftype)
-+ | HISNFC100_OP_CFG_DUMMY_ADDR_NUM(spi->read->dummy);
-+ hisfc_write(host, HISNFC100_OP_CFG, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG OP_CFG[0x28]%#x\n", val);
-+ }
++ val = host->cmd_option.op_config
++ | HISNFC100_OP_CFG_MEM_IF_TYPE(spi->read->iftype)
++ | HISNFC100_OP_CFG_DUMMY_ADDR_NUM(spi->read->dummy);
++ hisfc_write(host, HISNFC100_OP_CFG, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG OP_CFG[0x28]%#x\n", val);
++ }
+
-+ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
-+ block_num = host->addr_value[1] >> pages_per_block_shift;
-+ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
++ pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
++ block_num = host->addr_value[1] >> pages_per_block_shift;
++ block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
+
-+ val = HISNFC100_ADDRH_SET(block_num_h);
-+ hisfc_write(host, HISNFC100_ADDRH, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG ADDRH[0x2c]%#x\n", val);
-+ }
++ val = HISNFC100_ADDRH_SET(block_num_h);
++ hisfc_write(host, HISNFC100_ADDRH, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG ADDRH[0x2c]%#x\n", val);
++ }
+
-+ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
-+ if (only_oob)
-+ switch (host->ecctype) {
-+ case NAND_ECC_8BIT:
-+ addr_of = REG_CNT_ECC_8BIT_OFFSET;
-+ break;
-+ case NAND_ECC_16BIT:
-+ addr_of = REG_CNT_ECC_16BIT_OFFSET;
-+ break;
-+ case NAND_ECC_24BIT:
-+ addr_of = REG_CNT_ECC_24BIT_OFFSET;
-+ break;
-+ case NAND_ECC_0BIT:
-+ default:
-+ break;
-+ }
++ page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
++ if (only_oob)
++ switch (host->ecctype) {
++ case NAND_ECC_8BIT:
++ addr_of = REG_CNT_ECC_8BIT_OFFSET;
++ break;
++ case NAND_ECC_16BIT:
++ addr_of = REG_CNT_ECC_16BIT_OFFSET;
++ break;
++ case NAND_ECC_24BIT:
++ addr_of = REG_CNT_ECC_24BIT_OFFSET;
++ break;
++ case NAND_ECC_0BIT:
++ default:
++ break;
++ }
+
-+ val = (((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
-+ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT)
-+ | ((wrap & REG_CNT_WRAP_MASK) << REG_CNT_WRAP_SHIFT)
-+ | (addr_of & REG_CNT_ECC_OFFSET_MASK));
-+ hisfc_write(host, HISNFC100_ADDRL, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG ADDRL[0x30]%#x\n", val);
-+ }
++ val = (((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT)
++ | ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT)
++ | ((wrap & REG_CNT_WRAP_MASK) << REG_CNT_WRAP_SHIFT)
++ | (addr_of & REG_CNT_ECC_OFFSET_MASK));
++ hisfc_write(host, HISNFC100_ADDRL, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG ADDRL[0x30]%#x\n", val);
++ }
+
+#ifndef HISNFC100_SUPPORT_REG_READ
-+ val = HISNFC100_DMA_CTRL_ALL_ENABLE;
-+ hisfc_write(host, HISNFC100_DMA_CTRL, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG DMA_CTRL[0x3c]%#x\n", val);
-+ }
++ val = HISNFC100_DMA_CTRL_ALL_ENABLE;
++ hisfc_write(host, HISNFC100_DMA_CTRL, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG DMA_CTRL[0x3c]%#x\n", val);
++ }
+
-+ val = host->dma_buffer;
-+ hisfc_write(host, HISNFC100_DMA_SADDR_D, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG DMA_SADDR_D[0x40]%#x\n", val);
-+ }
++ val = host->dma_buffer;
++ hisfc_write(host, HISNFC100_DMA_SADDR_D, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG DMA_SADDR_D[0x40]%#x\n", val);
++ }
+
-+ val = host->dma_oob;
-+ hisfc_write(host, HISNFC100_DMA_SADDR_OOB, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG DMA_SADDR_OOB[%#x]%#x\n",
-+ HISNFC100_DMA_SADDR_OOB, val);
-+ }
++ val = host->dma_oob;
++ hisfc_write(host, HISNFC100_DMA_SADDR_OOB, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG DMA_SADDR_OOB[%#x]%#x\n",
++ HISNFC100_DMA_SADDR_OOB, val);
++ }
+#endif
+
-+ val = HISNFC100_OP_CTRL_RD_OPCODE(spi->read->cmd)
-+ | HISNFC100_OP_CTRL_CS_OP(host->cmd_option.chipselect)
++ val = HISNFC100_OP_CTRL_RD_OPCODE(spi->read->cmd)
++ | HISNFC100_OP_CTRL_CS_OP(host->cmd_option.chipselect)
+#ifdef HISNFC100_SUPPORT_REG_READ
-+ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_REG)
++ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_REG)
+#else
-+ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_DMA)
++ | HISNFC100_OP_CTRL_OP_TYPE(OP_TYPE_DMA)
+#endif
-+ | HISNFC100_OP_CTRL_RW_OP(RW_OP_READ)
-+ | HISNFC100_OP_CTRL_OP_READY;
-+ hisfc_write(host, HISNFC100_OP_CTRL, val);
-+ if (DEBUG_READ) {
-+ pr_info(" Set REG OP_CTRL[0x34]%#x\n", val);
-+ }
++ | HISNFC100_OP_CTRL_RW_OP(RW_OP_READ)
++ | HISNFC100_OP_CTRL_OP_READY;
++ hisfc_write(host, HISNFC100_OP_CTRL, val);
++ if (DEBUG_READ) {
++ pr_info(" Set REG OP_CTRL[0x34]%#x\n", val);
++ }
+
-+ HISNFC100_DMA_WAIT_INT_FINISH(host);
++ HISNFC100_DMA_WAIT_INT_FINISH(host);
+
-+ host->cache_addr_value[0] = host->addr_value[0];
-+ host->cache_addr_value[1] = host->addr_value[1];
++ host->cache_addr_value[0] = host->addr_value[0];
++ host->cache_addr_value[1] = host->addr_value[1];
+
-+ if (DEBUG_READ) {
-+ pr_info("* End %s page read start!\n", op_type);
-+ }
++ if (DEBUG_READ) {
++ pr_info("* End %s page read start!\n", op_type);
++ }
+}
+
+/*****************************************************************************/
+static void hisnfc100_send_cmd_erase(struct hisnfc_host *host)
+{
-+ unsigned val;
-+ struct hisnfc_op *spi = host->spi;
++ unsigned val;
++ struct hisnfc_op *spi = host->spi;
+
-+ if (DEBUG_ERASE) {
-+ pr_info("* Enter send cmd erase!\n");
-+ }
++ if (DEBUG_ERASE) {
++ pr_info("* Enter send cmd erase!\n");
++ }
+
-+ val = spi->driver->wait_ready(spi);
-+ if (val) {
-+ pr_info("hisnfc: erase wait ready fail! status[%#x]\n", val);
-+ return;
-+ }
++ val = spi->driver->wait_ready(spi);
++ if (val) {
++ pr_info("hisnfc: erase wait ready fail! status[%#x]\n", val);
++ return;
++ }
+
-+ if (spi->driver->write_enable(spi)) {
-+ pr_info("%s erase write enable failed!\n", __func__);
-+ return;
-+ }
++ if (spi->driver->write_enable(spi)) {
++ pr_info("%s erase write enable failed!\n", __func__);
++ return;
++ }
+
-+ if (DEBUG_ERASE) {
-+ spi_feature_op(host, GET_OP, STATUS_ADDR, &val);
-+ pr_info(" Get feature addr[0xC0], val[%#x]\n", val);
-+ }
++ if (DEBUG_ERASE) {
++ spi_feature_op(host, GET_OP, STATUS_ADDR, &val);
++ pr_info(" Get feature addr[0xC0], val[%#x]\n", val);
++ }
+
-+ host->set_system_clock(spi->erase, ENABLE);
++ host->set_system_clock(spi->erase, ENABLE);
+
-+ val = HISNFC100_INT_CLR_ALL;
-+ hisfc_write(host, HISNFC100_INT_CLR, val);
-+ if (DEBUG_ERASE) {
-+ pr_info(" Set REG INT_CLR[0x14]%#x\n", val);
-+ }
++ val = HISNFC100_INT_CLR_ALL;
++ hisfc_write(host, HISNFC100_INT_CLR, val);
++ if (DEBUG_ERASE) {
++ pr_info(" Set REG INT_CLR[0x14]%#x\n", val);
++ }
+
-+ val = spi->erase->cmd;
-+ hisfc_write(host, HISNFC100_OPCODE, val);
-+ if (DEBUG_ERASE) {
-+ pr_info(" Set REG OPCODE[0x18]%#x\n", val);
-+ }
++ val = spi->erase->cmd;
++ hisfc_write(host, HISNFC100_OPCODE, val);
++ if (DEBUG_ERASE) {
++ pr_info(" Set REG OPCODE[0x18]%#x\n", val);
++ }
+
-+ val = HISNFC100_OP_ADDRH_BLOCK_MASK(host->addr_value[1])
-+ | HISNFC100_OP_ADDRL_BLOCK_MASK(host->addr_value[0]);
-+ hisfc_write(host, HISNFC100_OP_ADDR, val);
-+ if (DEBUG_ERASE) {
-+ pr_info(" Set REG OP_ADDR[0x18]%#x\n", val);
-+ }
++ val = HISNFC100_OP_ADDRH_BLOCK_MASK(host->addr_value[1])
++ | HISNFC100_OP_ADDRL_BLOCK_MASK(host->addr_value[0]);
++ hisfc_write(host, HISNFC100_OP_ADDR, val);
++ if (DEBUG_ERASE) {
++ pr_info(" Set REG OP_ADDR[0x18]%#x\n", val);
++ }
+
-+ val = HISNFC100_OP_CFG_DIR_TRANS_ENABLE;
-+ hisfc_write(host, HISNFC100_OP_CFG, val);
-+ if (DEBUG_ERASE) {
-+ pr_info(" Set REG OP_CFG[0x28]%#x\n", val);
-+ }
++ val = HISNFC100_OP_CFG_DIR_TRANS_ENABLE;
++ hisfc_write(host, HISNFC100_OP_CFG, val);
++ if (DEBUG_ERASE) {
++ pr_info(" Set REG OP_CFG[0x28]%#x\n", val);
++ }
+
-+ val = HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
-+ | HISNFC100_OP_ADDR_NUM(STD_OP_ADDR_NUM)
-+ | HISNFC100_OP_OPCODE_EN(ENABLE)
-+ | HISNFC100_OP_ADDR_EN(ENABLE)
-+ | HISNFC100_OP_START;
-+ hisfc_write(host, HISNFC100_OP, val);
-+ if (DEBUG_ERASE) {
-+ pr_info(" Set REG OP[0x20]%#x\n", val);
-+ }
++ val = HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
++ | HISNFC100_OP_ADDR_NUM(STD_OP_ADDR_NUM)
++ | HISNFC100_OP_OPCODE_EN(ENABLE)
++ | HISNFC100_OP_ADDR_EN(ENABLE)
++ | HISNFC100_OP_START;
++ hisfc_write(host, HISNFC100_OP, val);
++ if (DEBUG_ERASE) {
++ pr_info(" Set REG OP[0x20]%#x\n", val);
++ }
+
-+ HISNFC100_CMD_WAIT_CPU_FINISH(host);
++ HISNFC100_CMD_WAIT_CPU_FINISH(host);
+
-+ if (DEBUG_ERASE) {
-+ val = spi->driver->wait_ready(spi);
-+ if (val & STATUS_E_FAIL_MASK) {
-+ pr_info("hisnfc100: erase failed! status[%#x]\n", val);
-+ }
-+ }
++ if (DEBUG_ERASE) {
++ val = spi->driver->wait_ready(spi);
++ if (val & STATUS_E_FAIL_MASK) {
++ pr_info("hisnfc100: erase failed! status[%#x]\n", val);
++ }
++ }
+
-+ if (DEBUG_ERASE) {
-+ pr_info("* End send cmd erase!\n");
-+ }
++ if (DEBUG_ERASE) {
++ pr_info("* End send cmd erase!\n");
++ }
+}
+
+/*****************************************************************************/
+static void hisnfc100_send_cmd_status(struct hisnfc_host *host)
+{
-+ unsigned regval, addr = 0;
++ unsigned regval, addr = 0;
+
-+ if ((host->cmd_option.last_cmd == NAND_CMD_ERASE1)
-+ || (host->cmd_option.last_cmd == NAND_CMD_PAGEPROG)) {
-+ addr = PROTECTION_ADDR;
-+ } else {
-+ addr = STATUS_ADDR;
-+ }
++ if ((host->cmd_option.last_cmd == NAND_CMD_ERASE1)
++ || (host->cmd_option.last_cmd == NAND_CMD_PAGEPROG)) {
++ addr = PROTECTION_ADDR;
++ } else {
++ addr = STATUS_ADDR;
++ }
+
-+ spi_feature_op(host, GET_OP, addr, ®val);
++ spi_feature_op(host, GET_OP, addr, ®val);
+
-+ if (DEBUG_ERASE || DEBUG_WRITE) {
-+ pr_info("hisnfc100: %s get %#x status[%#x]\n",
-+ ((host->cmd_option.last_cmd == NAND_CMD_ERASE1)
-+ ? "erase" : "write"), addr, regval);
-+ }
++ if (DEBUG_ERASE || DEBUG_WRITE) {
++ pr_info("hisnfc100: %s get %#x status[%#x]\n",
++ ((host->cmd_option.last_cmd == NAND_CMD_ERASE1)
++ ? "erase" : "write"), addr, regval);
++ }
+}
+
+/*****************************************************************************/
+static void hisnfc100_send_cmd_readid(struct hisnfc_host *host)
+{
-+ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
-+ hisfc_write(host, HISNFC100_OPCODE, SPI_CMD_RDID);
-+ hisfc_write(host, HISNFC100_OP_ADDR, READ_ID_ADDR);
-+ hisfc_write(host, HISNFC100_DATA_NUM,
-+ HISNFC100_DATA_NUM_CNT(MAX_ID_LEN));
-+ hisfc_write(host, HISNFC100_OP_CFG, HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
++ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
++ hisfc_write(host, HISNFC100_OPCODE, SPI_CMD_RDID);
++ hisfc_write(host, HISNFC100_OP_ADDR, READ_ID_ADDR);
++ hisfc_write(host, HISNFC100_DATA_NUM,
++ HISNFC100_DATA_NUM_CNT(MAX_ID_LEN));
++ hisfc_write(host, HISNFC100_OP_CFG, HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
+
-+ hisfc_write(host, HISNFC100_OP,
-+ HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
-+ | HISNFC100_OP_ADDR_NUM(READ_ID_ADDR_NUM)
-+ | HISNFC100_OP_OPCODE_EN(ENABLE)
-+ | HISNFC100_OP_ADDR_EN(ENABLE)
-+ | HISNFC100_OP_DATE_READ_EN(ENABLE)
-+ | HISNFC100_OP_START);
++ hisfc_write(host, HISNFC100_OP,
++ HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
++ | HISNFC100_OP_ADDR_NUM(READ_ID_ADDR_NUM)
++ | HISNFC100_OP_OPCODE_EN(ENABLE)
++ | HISNFC100_OP_ADDR_EN(ENABLE)
++ | HISNFC100_OP_DATE_READ_EN(ENABLE)
++ | HISNFC100_OP_START);
+
-+ HISNFC100_CMD_WAIT_CPU_FINISH(host);
++ HISNFC100_CMD_WAIT_CPU_FINISH(host);
+}
+
+/*****************************************************************************/
+static void hisnfc100_send_cmd_reset(struct hisnfc_host *host)
+{
-+ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
-+ hisfc_write(host, HISNFC100_OPCODE, SPI_CMD_RESET);
-+ hisfc_write(host, HISNFC100_OP_CFG, HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
-+ hisfc_write(host, HISNFC100_OP,
-+ HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
-+ | HISNFC100_OP_OPCODE_EN(ENABLE)
-+ | HISNFC100_OP_START);
++ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
++ hisfc_write(host, HISNFC100_OPCODE, SPI_CMD_RESET);
++ hisfc_write(host, HISNFC100_OP_CFG, HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
++ hisfc_write(host, HISNFC100_OP,
++ HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
++ | HISNFC100_OP_OPCODE_EN(ENABLE)
++ | HISNFC100_OP_START);
+
-+ HISNFC100_CMD_WAIT_CPU_FINISH(host);
++ HISNFC100_CMD_WAIT_CPU_FINISH(host);
+}
+
+/*****************************************************************************/
+static uint8_t hisnfc100_read_byte(struct mtd_info *mtd)
+{
-+ unsigned char value = 0, ret_val = 0;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
++ unsigned char value = 0, ret_val = 0;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
+
-+ if (host->cmd_option.last_cmd == NAND_CMD_READID) {
-+ value = readb(chip->IO_ADDR_R + host->offset);
-+ host->offset++;
-+ if (host->cmd_option.date_num == host->offset) {
-+ host->cmd_option.last_cmd = 0;
-+ }
-+ return value;
-+ }
++ if (host->cmd_option.last_cmd == NAND_CMD_READID) {
++ value = readb(chip->IO_ADDR_R + host->offset);
++ host->offset++;
++ if (host->cmd_option.date_num == host->offset) {
++ host->cmd_option.last_cmd = 0;
++ }
++ return value;
++ }
+
-+ if ((host->cmd_option.last_cmd == NAND_CMD_ERASE1)
-+ || (host->cmd_option.last_cmd == NAND_CMD_PAGEPROG)) {
-+ value = hisfc_read(host, HISNFC100_STATUS);
-+ if (ANY_BP_ENABLE(value)) {
-+ value &= ~NAND_STATUS_WP;
-+ } else {
-+ value |= NAND_STATUS_WP;
-+ }
++ if ((host->cmd_option.last_cmd == NAND_CMD_ERASE1)
++ || (host->cmd_option.last_cmd == NAND_CMD_PAGEPROG)) {
++ value = hisfc_read(host, HISNFC100_STATUS);
++ if (ANY_BP_ENABLE(value)) {
++ value &= ~NAND_STATUS_WP;
++ } else {
++ value |= NAND_STATUS_WP;
++ }
+
-+ host->cmd_option.last_cmd = 0;
++ host->cmd_option.last_cmd = 0;
+
-+ return value;
-+ }
++ return value;
++ }
+
-+ if (host->cmd_option.last_cmd == NAND_CMD_ERASE2) {
-+ value = hisfc_read(host, HISNFC100_STATUS);
-+ if (!(value & STATUS_OIP_MASK)) {
-+ ret_val |= NAND_STATUS_READY;
-+ }
++ if (host->cmd_option.last_cmd == NAND_CMD_ERASE2) {
++ value = hisfc_read(host, HISNFC100_STATUS);
++ if (!(value & STATUS_OIP_MASK)) {
++ ret_val |= NAND_STATUS_READY;
++ }
+
-+ if (value & STATUS_E_FAIL_MASK) {
-+ ret_val |= NAND_STATUS_FAIL;
-+ }
++ if (value & STATUS_E_FAIL_MASK) {
++ ret_val |= NAND_STATUS_FAIL;
++ }
+
-+ return ret_val;
-+ }
++ return ret_val;
++ }
+
-+ if (host->cmd_option.command == NAND_CMD_STATUS) {
-+ value = hisfc_read(host, HISNFC100_STATUS);
++ if (host->cmd_option.command == NAND_CMD_STATUS) {
++ value = hisfc_read(host, HISNFC100_STATUS);
+
-+ if (!(value & STATUS_OIP_MASK)) {
-+ ret_val |= NAND_STATUS_READY;
-+ }
++ if (!(value & STATUS_OIP_MASK)) {
++ ret_val |= NAND_STATUS_READY;
++ }
+
-+ if (value & STATUS_P_FAIL_MASK) {
-+ ret_val |= NAND_STATUS_FAIL;
-+ }
++ if (value & STATUS_P_FAIL_MASK) {
++ ret_val |= NAND_STATUS_FAIL;
++ }
+
-+ return ret_val;
-+ }
++ return ret_val;
++ }
+
-+ if (host->cmd_option.last_cmd == NAND_CMD_READOOB) {
-+ value = readb(host->buffer + host->pagesize + host->offset);
-+ host->offset++;
-+ return value;
-+ }
++ if (host->cmd_option.last_cmd == NAND_CMD_READOOB) {
++ value = readb(host->buffer + host->pagesize + host->offset);
++ host->offset++;
++ return value;
++ }
+
-+ host->offset++;
++ host->offset++;
+
-+ return readb(host->buffer + host->column + host->offset - 1);
++ return readb(host->buffer + host->column + host->offset - 1);
+}
+
+/*****************************************************************************/
+static u16 hisnfc100_read_word(struct mtd_info *mtd)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
+
-+ host->offset += 2;
-+ return readw(host->buffer + host->column + host->offset - 2);
++ host->offset += 2;
++ return readw(host->buffer + host->column + host->offset - 2);
+}
+
+/*****************************************************************************/
+static void hisnfc100_write_buf(struct mtd_info *mtd,
-+ const uint8_t *buf, int len)
++ const uint8_t *buf, int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
+
+#ifdef HISNFC100_SUPPORT_REG_WRITE
-+ if (buf == chip->oob_poi) {
-+ memcpy((char *)host->iobase + host->pagesize, buf, len);
-+ } else {
-+ memcpy((char *)host->iobase, buf, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy((char *)host->iobase + host->pagesize, buf, len);
++ } else {
++ memcpy((char *)host->iobase, buf, len);
++ }
+#else
-+ if (buf == chip->oob_poi) {
-+ memcpy((char *)(host->buffer + host->pagesize), buf, len);
-+ } else {
-+ memcpy((char *)host->buffer, buf, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy((char *)(host->buffer + host->pagesize), buf, len);
++ } else {
++ memcpy((char *)host->buffer, buf, len);
++ }
+#endif
-+ return;
++ return;
+}
+
+/*****************************************************************************/
+static void hisnfc100_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
+
+#ifdef HISNFC100_SUPPORT_REG_READ
-+ if (buf == chip->oob_poi) {
-+ memcpy(buf, (char *)host->iobase + host->pagesize, len);
-+ } else {
-+ memcpy(buf, (char *)host->iobase, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy(buf, (char *)host->iobase + host->pagesize, len);
++ } else {
++ memcpy(buf, (char *)host->iobase, len);
++ }
+#else
-+ if (buf == chip->oob_poi) {
-+ memcpy(buf, (char *)(host->buffer + host->pagesize), len);
-+ } else {
-+ memcpy(buf, (char *)host->buffer, len);
-+ }
++ if (buf == chip->oob_poi) {
++ memcpy(buf, (char *)(host->buffer + host->pagesize), len);
++ } else {
++ memcpy(buf, (char *)host->buffer, len);
++ }
+#endif
+
+#ifdef CONFIG_HISI_NAND_ECC_STATUS_REPORT
-+ if (buf != chip->oob_poi) {
-+ u_int reg, ecc_step = host->pagesize >> 10;
++ if (buf != chip->oob_poi) {
++ u_int reg, ecc_step = host->pagesize >> 10;
+
-+ reg = hisfc_read(host, HISNFC100_ECC_ERR_NUM);
-+ while (ecc_step) {
-+ u_char err_num;
++ reg = hisfc_read(host, HISNFC100_ECC_ERR_NUM);
++ while (ecc_step) {
++ u_char err_num;
+
-+ err_num = GET_ECC_ERR_NUM(--ecc_step, reg);
-+ if (err_num == 0xff) {
-+ mtd->ecc_stats.failed++;
-+ } else {
-+ mtd->ecc_stats.corrected += err_num;
-+ }
-+ }
-+ }
++ err_num = GET_ECC_ERR_NUM(--ecc_step, reg);
++ if (err_num == 0xff) {
++ mtd->ecc_stats.failed++;
++ } else {
++ mtd->ecc_stats.corrected += err_num;
++ }
++ }
++ }
+#endif
+
-+ return;
++ return;
+}
+
+/*****************************************************************************/
+static void hisnfc100_select_chip(struct mtd_info *mtd, int chipselect)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
+
-+ if (chipselect < 0) {
-+ return;
-+ }
++ if (chipselect < 0) {
++ return;
++ }
+
-+ if (chipselect > CONFIG_HISNFC100_MAX_CHIP) {
-+ DBG_BUG("invalid chipselect: %d\n", chipselect);
-+ }
++ if (chipselect > CONFIG_HISNFC100_MAX_CHIP) {
++ DBG_BUG("invalid chipselect: %d\n", chipselect);
++ }
+
-+ host->cmd_option.chipselect = chipselect + 1;
++ host->cmd_option.chipselect = chipselect + 1;
+
-+ switch (chip->state) {
-+ case FL_ERASING:
-+ host->cmd_option.last_cmd = NAND_CMD_ERASE1;
-+ break;
++ switch (chip->state) {
++ case FL_ERASING:
++ host->cmd_option.last_cmd = NAND_CMD_ERASE1;
++ break;
+
-+ case FL_WRITING:
-+ host->cmd_option.last_cmd = NAND_CMD_PAGEPROG;
-+ break;
++ case FL_WRITING:
++ host->cmd_option.last_cmd = NAND_CMD_PAGEPROG;
++ break;
+
-+ default:
-+ break;
-+ }
++ default:
++ break;
++ }
+}
+
+/*****************************************************************************/
+static void hisnfc100_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned ctrl)
+{
-+ unsigned char cmd;
-+ int is_cache_invalid = 1;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
++ unsigned char cmd;
++ int is_cache_invalid = 1;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
+
-+ if (ctrl & NAND_ALE) {
-+ unsigned int addr_value = 0;
-+ unsigned int addr_offset = 0;
++ if (ctrl & NAND_ALE) {
++ unsigned int addr_value = 0;
++ unsigned int addr_offset = 0;
+
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ host->addr_cycle = 0x0;
-+ host->addr_value[0] = 0x0;
-+ host->addr_value[1] = 0x0;
-+ }
-+ addr_offset = host->addr_cycle << 3;
++ if (ctrl & NAND_CTRL_CHANGE) {
++ host->addr_cycle = 0x0;
++ host->addr_value[0] = 0x0;
++ host->addr_value[1] = 0x0;
++ }
++ addr_offset = host->addr_cycle << 3;
+
-+ if (host->addr_cycle >= HISNFC100_ADDR_CYCLE_MASK) {
-+ addr_offset = (host->addr_cycle -
-+ HISNFC100_ADDR_CYCLE_MASK) << 3;
-+ addr_value = 1;
-+ }
++ if (host->addr_cycle >= HISNFC100_ADDR_CYCLE_MASK) {
++ addr_offset = (host->addr_cycle -
++ HISNFC100_ADDR_CYCLE_MASK) << 3;
++ addr_value = 1;
++ }
+
-+ host->addr_value[addr_value] |=
-+ ((dat & 0xff) << addr_offset);
++ host->addr_value[addr_value] |=
++ ((dat & 0xff) << addr_offset);
+
-+ host->addr_cycle++;
-+ }
++ host->addr_cycle++;
++ }
+
-+ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
-+ cmd = dat & 0xff;
-+ host->cmd_option.command = cmd;
-+ switch (cmd) {
-+ case NAND_CMD_PAGEPROG:
-+ host->offset = 0;
-+ host->send_cmd_pageprog(host);
-+ break;
++ if ((ctrl & NAND_CLE) && (ctrl & NAND_CTRL_CHANGE)) {
++ cmd = dat & 0xff;
++ host->cmd_option.command = cmd;
++ switch (cmd) {
++ case NAND_CMD_PAGEPROG:
++ host->offset = 0;
++ host->send_cmd_pageprog(host);
++ break;
+
-+ case NAND_CMD_READSTART:
-+ is_cache_invalid = 0;
-+ if (host->addr_value[0] == host->pagesize) {
-+ host->cmd_option.last_cmd = NAND_CMD_READOOB;
-+ }
-+ host->send_cmd_readstart(host);
-+ break;
++ case NAND_CMD_READSTART:
++ is_cache_invalid = 0;
++ if (host->addr_value[0] == host->pagesize) {
++ host->cmd_option.last_cmd = NAND_CMD_READOOB;
++ }
++ host->send_cmd_readstart(host);
++ break;
+
-+ case NAND_CMD_ERASE2:
-+ host->cmd_option.last_cmd = cmd;
-+ host->send_cmd_erase(host);
-+ break;
++ case NAND_CMD_ERASE2:
++ host->cmd_option.last_cmd = cmd;
++ host->send_cmd_erase(host);
++ break;
+
-+ case NAND_CMD_READID:
-+ memset((unsigned char *)(chip->IO_ADDR_R), 0,
-+ MAX_ID_LEN);
-+ host->cmd_option.last_cmd = cmd;
-+ host->cmd_option.date_num = MAX_ID_LEN;
-+ host->send_cmd_readid(host);
-+ break;
++ case NAND_CMD_READID:
++ memset((unsigned char *)(chip->IO_ADDR_R), 0,
++ MAX_ID_LEN);
++ host->cmd_option.last_cmd = cmd;
++ host->cmd_option.date_num = MAX_ID_LEN;
++ host->send_cmd_readid(host);
++ break;
+
-+ case NAND_CMD_STATUS:
-+ host->send_cmd_status(host);
-+ break;
++ case NAND_CMD_STATUS:
++ host->send_cmd_status(host);
++ break;
+
-+ case NAND_CMD_SEQIN:
-+ break;
++ case NAND_CMD_SEQIN:
++ break;
+
-+ case NAND_CMD_ERASE1:
-+ break;
++ case NAND_CMD_ERASE1:
++ break;
+
-+ case NAND_CMD_READ0:
-+ host->cmd_option.last_cmd = cmd;
-+ break;
++ case NAND_CMD_READ0:
++ host->cmd_option.last_cmd = cmd;
++ break;
+
-+ case NAND_CMD_RESET:
-+ host->send_cmd_reset(host);
-+ break;
++ case NAND_CMD_RESET:
++ host->send_cmd_reset(host);
++ break;
+
-+ default:
-+ break;
-+ }
-+ }
++ default:
++ break;
++ }
++ }
+
-+ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
-+ if (host->cmd_option.command == NAND_CMD_SEQIN
-+ || host->cmd_option.command == NAND_CMD_READ0
-+ || host->cmd_option.command == NAND_CMD_READID) {
-+ host->offset = 0x0;
-+ host->column = (host->addr_value[0] & 0xffff);
-+ }
-+ }
++ if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
++ if (host->cmd_option.command == NAND_CMD_SEQIN
++ || host->cmd_option.command == NAND_CMD_READ0
++ || host->cmd_option.command == NAND_CMD_READID) {
++ host->offset = 0x0;
++ host->column = (host->addr_value[0] & 0xffff);
++ }
++ }
+
-+ if (is_cache_invalid) {
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
-+ }
++ if (is_cache_invalid) {
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
++ }
+}
+
+/*****************************************************************************/
+static int hisnfc100_dev_ready(struct mtd_info *mtd)
+{
-+ unsigned regval;
-+ unsigned deadline = 0;
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
++ unsigned regval;
++ unsigned deadline = 0;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
+
-+ do {
-+ spi_feature_op(host, GET_OP, STATUS_ADDR, ®val);
-+ if (!(regval & STATUS_OIP_MASK)) {
-+ return 1;
-+ }
-+ udelay(1);
-+ } while (deadline++ < (40 << 20));
++ do {
++ spi_feature_op(host, GET_OP, STATUS_ADDR, ®val);
++ if (!(regval & STATUS_OIP_MASK)) {
++ return 1;
++ }
++ udelay(1);
++ } while (deadline++ < (40 << 20));
+
-+ pr_info("Wait spi nand flash ready timeout.\n");
++ pr_info("Wait spi nand flash ready timeout.\n");
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -301081,142 +369295,142 @@ index 0000000..c68d3c5
+ */
+/* Default OOB area layout */
+static int hisnfc_ooblayout_ecc_64(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 32;
-+ oobregion->offset = 32;
++ oobregion->length = 32;
++ oobregion->offset = 32;
+
-+ return 0;
++ return 0;
+}
+
+static int hisnfc_ooblayout_free_64(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
++ struct mtd_oob_region *oobregion)
+{
-+ if (section) {
-+ return -ERANGE;
-+ }
++ if (section) {
++ return -ERANGE;
++ }
+
-+ oobregion->length = 30;
-+ oobregion->offset = 2;
++ oobregion->length = 30;
++ oobregion->offset = 2;
+
-+ return 0;
++ return 0;
+}
+
+static struct mtd_ooblayout_ops hisnfc_ooblayout_64_ops = {
-+ .ecc = hisnfc_ooblayout_ecc_64,
-+ .free = hisnfc_ooblayout_free_64,
++ .ecc = hisnfc_ooblayout_ecc_64,
++ .free = hisnfc_ooblayout_free_64,
+};
+
+/*****************************************************************************/
+static struct nand_config_info hisnfc_spi_nand_config_table[] = {
-+ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200, &hisnfc_ooblayout_64_ops},
-+ {NAND_PAGE_4K, NAND_ECC_16BIT, 16, 144, &hisnfc_ooblayout_64_ops},
-+ {NAND_PAGE_4K, NAND_ECC_8BIT, 8, 128/*88*/, &hisnfc_ooblayout_64_ops},
-+ {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_4K, NAND_ECC_24BIT, 24, 200, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_4K, NAND_ECC_16BIT, 16, 144, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_4K, NAND_ECC_8BIT, 8, 128/*88*/, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hisnfc_ooblayout_64_ops},
+
-+ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128/*116*/, &hisnfc_ooblayout_64_ops},
-+ {NAND_PAGE_2K, NAND_ECC_16BIT, 16, 88, &hisnfc_ooblayout_64_ops},
-+ {NAND_PAGE_2K, NAND_ECC_8BIT, 8, 64/*60*/, &hisnfc_ooblayout_64_ops},
-+ {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_2K, NAND_ECC_24BIT, 24, 128/*116*/, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_2K, NAND_ECC_16BIT, 16, 88, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_2K, NAND_ECC_8BIT, 8, 64/*60*/, &hisnfc_ooblayout_64_ops},
++ {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hisnfc_ooblayout_64_ops},
+
-+ {0, 0, 0, 0, NULL},
++ {0, 0, 0, 0, NULL},
+};
+
+/*****************************************************************************/
+/* used the best correct arithmetic. */
+struct nand_config_info *hisnfc100_get_best_ecc(struct mtd_info *mtd)
+{
-+ struct nand_config_info *best = NULL;
-+ struct nand_config_info *info = hisnfc_spi_nand_config_table;
++ struct nand_config_info *best = NULL;
++ struct nand_config_info *info = hisnfc_spi_nand_config_table;
+
-+ for (; info->ooblayout_ops; info++) {
-+ if (nandpage_type2size(info->pagetype) != mtd->writesize) {
-+ continue;
-+ }
++ for (; info->ooblayout_ops; info++) {
++ if (nandpage_type2size(info->pagetype) != mtd->writesize) {
++ continue;
++ }
+
-+ if (mtd->oobsize < info->oobsize) {
-+ continue;
-+ }
++ if (mtd->oobsize < info->oobsize) {
++ continue;
++ }
+
-+ if (!best || (best->ecctype < info->ecctype)) {
-+ best = info;
-+ }
-+ }
++ if (!best || (best->ecctype < info->ecctype)) {
++ best = info;
++ }
++ }
+
-+ if (!best)
-+ DBG_BUG(ERSTR_DRIVER "Driver does not support the pagesize" \
-+ "(%d) and oobsize(%d).\n", mtd->writesize, mtd->oobsize);
++ if (!best)
++ DBG_BUG(ERSTR_DRIVER "Driver does not support the pagesize" \
++ "(%d) and oobsize(%d).\n", mtd->writesize, mtd->oobsize);
+
-+ return best;
++ return best;
+}
+
+/*****************************************************************************/
+/* force the pagesize and ecctype */
+struct nand_config_info *hisnfc100_force_ecc(struct mtd_info *mtd, int pagetype,
-+ int ecctype, char *cfgmsg, int allow_pagediv)
++ int ecctype, char *cfgmsg, int allow_pagediv)
+{
-+ int pagesize;
-+ struct nand_config_info *fit = NULL;
-+ struct nand_config_info *info = hisnfc_spi_nand_config_table;
++ int pagesize;
++ struct nand_config_info *fit = NULL;
++ struct nand_config_info *info = hisnfc_spi_nand_config_table;
+
-+ for (; info->ooblayout_ops; info++) {
-+ if (info->pagetype == pagetype && info->ecctype == ecctype) {
-+ fit = info;
-+ break;
-+ }
-+ }
++ for (; info->ooblayout_ops; info++) {
++ if (info->pagetype == pagetype && info->ecctype == ecctype) {
++ fit = info;
++ break;
++ }
++ }
+
-+ if (!fit) {
-+ DBG_BUG(ERSTR_DRIVER "Driver(%s mode) does not support this" \
-+ " Nand Flash pagesize:%s, ecctype:%s\n", cfgmsg,
-+ nand_page_name(pagetype), nand_ecc_name(ecctype));
-+ return NULL;
-+ }
++ if (!fit) {
++ DBG_BUG(ERSTR_DRIVER "Driver(%s mode) does not support this" \
++ " Nand Flash pagesize:%s, ecctype:%s\n", cfgmsg,
++ nand_page_name(pagetype), nand_ecc_name(ecctype));
++ return NULL;
++ }
+
-+ pagesize = nandpage_type2size(pagetype);
-+ if ((pagesize != mtd->writesize)
-+ && (pagesize > mtd->writesize || !allow_pagediv)) {
-+ DBG_BUG(ERSTR_HARDWARE "Hardware (%s mode) configure pagesize" \
-+ " %d, but the Nand Flash pageszie is %d\n", cfgmsg,
-+ pagesize, mtd->writesize);
-+ return NULL;
-+ }
++ pagesize = nandpage_type2size(pagetype);
++ if ((pagesize != mtd->writesize)
++ && (pagesize > mtd->writesize || !allow_pagediv)) {
++ DBG_BUG(ERSTR_HARDWARE "Hardware (%s mode) configure pagesize" \
++ " %d, but the Nand Flash pageszie is %d\n", cfgmsg,
++ pagesize, mtd->writesize);
++ return NULL;
++ }
+
-+ if (fit->oobsize > mtd->oobsize) {
-+ DBG_BUG(ERSTR_HARDWARE "(%s mode) The Nand Flash offer space" \
-+ " area is %d bytes, but the controller request %d" \
-+ "bytes in ecc %s. Please make sure the hardware ECC " \
-+ "configuration is correct.", cfgmsg, mtd->oobsize,
-+ fit->oobsize, nand_ecc_name(ecctype));
-+ return NULL;
-+ }
++ if (fit->oobsize > mtd->oobsize) {
++ DBG_BUG(ERSTR_HARDWARE "(%s mode) The Nand Flash offer space" \
++ " area is %d bytes, but the controller request %d" \
++ "bytes in ecc %s. Please make sure the hardware ECC " \
++ "configuration is correct.", cfgmsg, mtd->oobsize,
++ fit->oobsize, nand_ecc_name(ecctype));
++ return NULL;
++ }
+
-+ return fit;
++ return fit;
+}
+
+/*****************************************************************************/
+int hisnfc100_ecc_probe(struct mtd_info *mtd, struct nand_chip *chip,
-+ struct nand_dev_t *nand_dev)
++ struct nand_dev_t *nand_dev)
+{
-+ char *start_type = "unknown";
-+ struct nand_config_info *best = NULL;
-+ struct hisnfc_host *host = chip->priv;
-+ struct mtd_oob_region *hisnfc_oobregion;
-+ unsigned reg_pagetype, reg_ecctype, pagetype, ecctype;
++ char *start_type = "unknown";
++ struct nand_config_info *best = NULL;
++ struct hisnfc_host *host = chip->priv;
++ struct mtd_oob_region *hisnfc_oobregion;
++ unsigned reg_pagetype, reg_ecctype, pagetype, ecctype;
+
-+ hisnfc_oobregion = kmalloc(sizeof(struct mtd_oob_region), GFP_KERNEL);
-+ if (!hisnfc_oobregion) {
-+ PR_BUG("failed to allocate hinfc_oobregion structure.\n");
-+ return -ENOMEM;
-+ }
++ hisnfc_oobregion = kmalloc(sizeof(struct mtd_oob_region), GFP_KERNEL);
++ if (!hisnfc_oobregion) {
++ PR_BUG("failed to allocate hinfc_oobregion structure.\n");
++ return -ENOMEM;
++ }
+
+#ifdef CONFIG_HISNFC100_AUTO_PAGESIZE_ECC
-+ best = hisnfc100_get_best_ecc(mtd);
-+ start_type = "Auto";
++ best = hisnfc100_get_best_ecc(mtd);
++ start_type = "Auto";
+#endif /* CONFIG_HISNFC100_AUTO_PAGESIZE_ECC */
+
+#ifdef CONFIG_HISNFC100_HARDWARE_PAGESIZE_ECC
@@ -301225,36 +369439,36 @@ index 0000000..c68d3c5
+and CONFIG_HISNFC100_HARDWARE_PAGESIZE_ECC at the same time
+# endif
+
-+ reg_pagetype = (host->NFC_CFG & PAGE_SIZE_MASK) >> PAGE_SIZE_SHIFT;
-+ switch (reg_pagetype) {
-+ case 0:
-+ pagetype = NAND_PAGE_2K;
-+ break;
-+ case 1:
-+ pagetype = NAND_PAGE_4K;
-+ break;
-+ default:
-+ pagetype = NAND_PAGE_2K;
-+ }
++ reg_pagetype = (host->NFC_CFG & PAGE_SIZE_MASK) >> PAGE_SIZE_SHIFT;
++ switch (reg_pagetype) {
++ case 0:
++ pagetype = NAND_PAGE_2K;
++ break;
++ case 1:
++ pagetype = NAND_PAGE_4K;
++ break;
++ default:
++ pagetype = NAND_PAGE_2K;
++ }
+
-+ reg_ecctype = (host->NFC_CFG & ECC_TYPE_MASK) >> ECC_TYPE_SHIFT;
-+ switch (reg_ecctype) {
-+ case 0x01:
-+ ecctype = NAND_ECC_8BIT;
-+ break;
-+ case 0x02:
-+ ecctype = NAND_ECC_16BIT;
-+ break;
-+ case 0x03:
-+ ecctype = NAND_ECC_24BIT;
-+ break;
-+ case 0:
-+ default:
-+ ecctype = NAND_ECC_8BIT;
-+ }
-+ best = hisnfc100_force_ecc(mtd, pagetype, ecctype,
-+ "hardware config", 0);
-+ start_type = "Hardware";
++ reg_ecctype = (host->NFC_CFG & ECC_TYPE_MASK) >> ECC_TYPE_SHIFT;
++ switch (reg_ecctype) {
++ case 0x01:
++ ecctype = NAND_ECC_8BIT;
++ break;
++ case 0x02:
++ ecctype = NAND_ECC_16BIT;
++ break;
++ case 0x03:
++ ecctype = NAND_ECC_24BIT;
++ break;
++ case 0:
++ default:
++ ecctype = NAND_ECC_8BIT;
++ }
++ best = hisnfc100_force_ecc(mtd, pagetype, ecctype,
++ "hardware config", 0);
++ start_type = "Hardware";
+
+#endif /* CONFIG_HISNFC100_HARDWARE_PAGESIZE_ECC */
+
@@ -301268,158 +369482,158 @@ index 0000000..c68d3c5
+and CONFIG_HISNFC100_HARDWARE_PAGESIZE_ECC at the same time
+# endif
+
-+ {
-+ int pagetype;
++ {
++ int pagetype;
+
-+ switch (mtd->writesize)
-+ {
-+ case _2K:
-+ pagetype = NAND_PAGE_2K;
-+ break;
-+ case _4K:
-+ pagetype = NAND_PAGE_4K;
-+ break;
-+ default:
-+ pagetype = NAND_PAGE_2K;
-+ break;
-+ }
-+ best = hisnfc100_force_ecc(mtd, pagetype, NAND_ECC_0BIT,
-+ "force config", 0);
-+ start_type = "AutoForce";
-+ }
++ switch (mtd->writesize)
++ {
++ case _2K:
++ pagetype = NAND_PAGE_2K;
++ break;
++ case _4K:
++ pagetype = NAND_PAGE_4K;
++ break;
++ default:
++ pagetype = NAND_PAGE_2K;
++ break;
++ }
++ best = hisnfc100_force_ecc(mtd, pagetype, NAND_ECC_0BIT,
++ "force config", 0);
++ start_type = "AutoForce";
++ }
+#endif /* CONFIG_HISNFC100_PAGESIZE_AUTO_ECC_NONE */
+
-+ if (!best)
-+ DBG_BUG(ERSTR_HARDWARE
-+ "Please configure SPI Nand Flash pagesize and ecctype!\n");
++ if (!best)
++ DBG_BUG(ERSTR_HARDWARE
++ "Please configure SPI Nand Flash pagesize and ecctype!\n");
+
-+ if (best->ecctype != NAND_ECC_0BIT) {
-+ mtd->oobsize = best->oobsize;
-+ }
++ if (best->ecctype != NAND_ECC_0BIT) {
++ mtd->oobsize = best->oobsize;
++ }
+
-+ host->ecctype = best->ecctype;
-+ host->pagesize = nandpage_type2size(best->pagetype);
-+ host->oobsize = mtd->oobsize;
-+ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
++ host->ecctype = best->ecctype;
++ host->pagesize = nandpage_type2size(best->pagetype);
++ host->oobsize = mtd->oobsize;
++ host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
+
-+ host->dma_oob = host->dma_buffer + host->pagesize;
++ host->dma_oob = host->dma_buffer + host->pagesize;
+
-+ host->bbm = (unsigned char *)(host->buffer + host->pagesize
-+ + HINFC_BAD_BLOCK_POS);
++ host->bbm = (unsigned char *)(host->buffer + host->pagesize
++ + HINFC_BAD_BLOCK_POS);
+
-+ if (best->ooblayout_ops->free) {
-+ best->ooblayout_ops->free(mtd, 0, hisnfc_oobregion);
-+ }
++ if (best->ooblayout_ops->free) {
++ best->ooblayout_ops->free(mtd, 0, hisnfc_oobregion);
++ }
+
-+ host->epm = (unsigned short *)(host->buffer + host->pagesize
-+ + hisnfc_oobregion->offset + 28);
++ host->epm = (unsigned short *)(host->buffer + host->pagesize
++ + hisnfc_oobregion->offset + 28);
+
-+ mtd_set_ooblayout(mtd, &hisnfc_ooblayout_64_ops);
++ mtd_set_ooblayout(mtd, &hisnfc_ooblayout_64_ops);
+
-+ host->NFC_CFG |= (HISNFC100_CFG_ECC_TYPE(best->ecctype)
-+ | HISNFC100_CFG_PAGE_SIZE(best->pagetype)
-+ | HISNFC100_CFG_OP_MODE(OP_MODE_NORMAL));
++ host->NFC_CFG |= (HISNFC100_CFG_ECC_TYPE(best->ecctype)
++ | HISNFC100_CFG_PAGE_SIZE(best->pagetype)
++ | HISNFC100_CFG_OP_MODE(OP_MODE_NORMAL));
+
-+ if (mtd->writesize > SPI_NAND_MAX_PAGESIZE
-+ || mtd->oobsize > SPI_NAND_MAX_OOBSIZE) {
-+ DBG_BUG(ERSTR_DRIVER "Driver does not support this Nand " \
-+ "Flash. Please increase SPI_NAND_MAX_PAGESIZE and " \
-+ "SPI_NAND_MAX_OOBSIZE.\n");
-+ }
++ if (mtd->writesize > SPI_NAND_MAX_PAGESIZE
++ || mtd->oobsize > SPI_NAND_MAX_OOBSIZE) {
++ DBG_BUG(ERSTR_DRIVER "Driver does not support this Nand " \
++ "Flash. Please increase SPI_NAND_MAX_PAGESIZE and " \
++ "SPI_NAND_MAX_OOBSIZE.\n");
++ }
+
-+ if (mtd->writesize != host->pagesize) {
-+ unsigned int shift = 0;
-+ unsigned int writesize = mtd->writesize;
-+ while (writesize > host->pagesize) {
-+ writesize >>= 1;
-+ shift++;
-+ }
-+ chip->chipsize = chip->chipsize >> shift;
-+ mtd->erasesize = mtd->erasesize >> shift;
-+ mtd->writesize = host->pagesize;
-+ pr_info("Nand divide into 1/%u\n", (1 << shift));
-+ }
++ if (mtd->writesize != host->pagesize) {
++ unsigned int shift = 0;
++ unsigned int writesize = mtd->writesize;
++ while (writesize > host->pagesize) {
++ writesize >>= 1;
++ shift++;
++ }
++ chip->chipsize = chip->chipsize >> shift;
++ mtd->erasesize = mtd->erasesize >> shift;
++ mtd->writesize = host->pagesize;
++ pr_info("Nand divide into 1/%u\n", (1 << shift));
++ }
+
-+ nand_dev->start_type = start_type;
-+ nand_dev->ecctype = host->ecctype;
-+ nand_dev->oobsize = host->oobsize;
++ nand_dev->start_type = start_type;
++ nand_dev->ecctype = host->ecctype;
++ nand_dev->oobsize = host->oobsize;
+
-+ /* All SPI NAND are small-page, SLC */
-+ chip->bits_per_cell = 1;
++ /* All SPI NAND are small-page, SLC */
++ chip->bits_per_cell = 1;
+
-+ kfree(hisnfc_oobregion);
++ kfree(hisnfc_oobregion);
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+void hisnfc100_nand_init(struct nand_chip *chip)
+{
-+ chip->read_byte = hisnfc100_read_byte;
-+ chip->read_word = hisnfc100_read_word;
-+ chip->write_buf = hisnfc100_write_buf;
-+ chip->read_buf = hisnfc100_read_buf;
++ chip->read_byte = hisnfc100_read_byte;
++ chip->read_word = hisnfc100_read_word;
++ chip->write_buf = hisnfc100_write_buf;
++ chip->read_buf = hisnfc100_read_buf;
+
-+ chip->select_chip = hisnfc100_select_chip;
++ chip->select_chip = hisnfc100_select_chip;
+
-+ chip->cmd_ctrl = hisnfc100_cmd_ctrl;
-+ chip->dev_ready = hisnfc100_dev_ready;
++ chip->cmd_ctrl = hisnfc100_cmd_ctrl;
++ chip->dev_ready = hisnfc100_dev_ready;
+
-+ chip->chip_delay = HISNFC100_CHIP_DELAY;
++ chip->chip_delay = HISNFC100_CHIP_DELAY;
+
-+ chip->options = NAND_SKIP_BBTSCAN;
++ chip->options = NAND_SKIP_BBTSCAN;
+
-+ chip->ecc.mode = NAND_ECC_NONE;
++ chip->ecc.mode = NAND_ECC_NONE;
+}
+
+/*****************************************************************************/
+int hisnfc100_host_init(struct hisnfc_host *host)
+{
-+ unsigned regval;
++ unsigned regval;
+
-+ regval = hisfc_read(host, HISNFC100_CFG);
-+ if (((regval & DEVICE_TYPE_MASK) >> DEVICE_TYPE_SHIFT)
-+ != DEVICE_TYPE_NAND_FLASH) {
-+ pr_info("%s: Device type(SPI nor flash) error.\n", __func__);
-+ return -ENXIO;
-+ }
++ regval = hisfc_read(host, HISNFC100_CFG);
++ if (((regval & DEVICE_TYPE_MASK) >> DEVICE_TYPE_SHIFT)
++ != DEVICE_TYPE_NAND_FLASH) {
++ pr_info("%s: Device type(SPI nor flash) error.\n", __func__);
++ return -ENXIO;
++ }
+
-+ if ((regval & OP_MODE_MASK) == OP_MODE_BOOT) {
-+ regval |= HISNFC100_CFG_OP_MODE(OP_MODE_NORMAL);
-+ }
++ if ((regval & OP_MODE_MASK) == OP_MODE_BOOT) {
++ regval |= HISNFC100_CFG_OP_MODE(OP_MODE_NORMAL);
++ }
+
-+ if (!(regval & HISNFC100_CFG_DEVICE_INTERNAL_ECC_ENABLE)) {
-+ regval &= ~HISNFC100_CFG_DEVICE_INTERNAL_ECC_ENABLE;
-+ }
++ if (!(regval & HISNFC100_CFG_DEVICE_INTERNAL_ECC_ENABLE)) {
++ regval &= ~HISNFC100_CFG_DEVICE_INTERNAL_ECC_ENABLE;
++ }
+
-+ hisfc_write(host, HISNFC100_CFG, regval);
++ hisfc_write(host, HISNFC100_CFG, regval);
+
-+ host->NFC_CFG = regval;
++ host->NFC_CFG = regval;
+
-+ host->addr_cycle = 0;
-+ host->addr_value[0] = 0;
-+ host->addr_value[1] = 0;
-+ host->cache_addr_value[0] = ~0;
-+ host->cache_addr_value[1] = ~0;
++ host->addr_cycle = 0;
++ host->addr_value[0] = 0;
++ host->addr_value[1] = 0;
++ host->cache_addr_value[0] = ~0;
++ host->cache_addr_value[1] = ~0;
+
-+ host->send_cmd_pageprog = hisnfc100_send_cmd_pageprog;
-+ host->send_cmd_status = hisnfc100_send_cmd_status;
-+ host->send_cmd_readstart = hisnfc100_send_cmd_readstart;
-+ host->send_cmd_erase = hisnfc100_send_cmd_erase;
-+ host->send_cmd_readid = hisnfc100_send_cmd_readid;
-+ host->send_cmd_reset = hisnfc100_send_cmd_reset;
-+ host->set_system_clock = hisnfc100_set_system_clock;
++ host->send_cmd_pageprog = hisnfc100_send_cmd_pageprog;
++ host->send_cmd_status = hisnfc100_send_cmd_status;
++ host->send_cmd_readstart = hisnfc100_send_cmd_readstart;
++ host->send_cmd_erase = hisnfc100_send_cmd_erase;
++ host->send_cmd_readid = hisnfc100_send_cmd_readid;
++ host->send_cmd_reset = hisnfc100_send_cmd_reset;
++ host->set_system_clock = hisnfc100_set_system_clock;
+
-+ hisfc_write(host, HISNFC100_TIMING_CFG,
-+ HISNFC100_TIMING_CFG_TCSH(CS_HOLD_TIME)
-+ | HISNFC100_TIMING_CFG_TCSS(CS_SETUP_TIME)
-+ | HISNFC100_TIMING_CFG_TSHSL(CS_DESELECT_TIME));
-+ return 0;
++ hisfc_write(host, HISNFC100_TIMING_CFG,
++ HISNFC100_TIMING_CFG_TCSH(CS_HOLD_TIME)
++ | HISNFC100_TIMING_CFG_TCSS(CS_SETUP_TIME)
++ | HISNFC100_TIMING_CFG_TSHSL(CS_DESELECT_TIME));
++ return 0;
+}
+
diff --git a/drivers/mtd/nand/hisnfc100/hisnfc100.h b/drivers/mtd/nand/hisnfc100/hisnfc100.h
new file mode 100644
-index 0000000..db59d51
+index 0000000..4caa92b
--- /dev/null
+++ b/drivers/mtd/nand/hisnfc100/hisnfc100.h
@@ -0,0 +1,378 @@
@@ -301674,68 +369888,68 @@ index 0000000..db59d51
+
+/*****************************************************************************/
+struct hisfc_cmd_option {
-+ unsigned char chipselect;
-+ unsigned char command;
-+ unsigned char last_cmd;
-+ unsigned char address_h;
-+ unsigned int address_l;
-+ unsigned int date_num;
-+ unsigned short option;
-+ unsigned short op_config;
++ unsigned char chipselect;
++ unsigned char command;
++ unsigned char last_cmd;
++ unsigned char address_h;
++ unsigned int address_l;
++ unsigned int date_num;
++ unsigned short option;
++ unsigned short op_config;
+};
+
+struct hisnfc_host;
+
+struct hisnfc_host {
-+ struct nand_chip *chip;
-+ struct mtd_info *mtd;
-+ struct hisnfc_op spi[CONFIG_HISNFC100_MAX_CHIP];
-+ struct hisfc_cmd_option cmd_option;
++ struct nand_chip *chip;
++ struct mtd_info *mtd;
++ struct hisnfc_op spi[CONFIG_HISNFC100_MAX_CHIP];
++ struct hisfc_cmd_option cmd_option;
+
-+ void __iomem *iobase;
-+ void __iomem *regbase;
++ void __iomem *iobase;
++ void __iomem *regbase;
+
-+ unsigned int NFC_CFG;
++ unsigned int NFC_CFG;
+
-+ unsigned int offset;
++ unsigned int offset;
+
-+ struct device *dev;
-+ struct clk *clk;
++ struct device *dev;
++ struct clk *clk;
+
-+ unsigned int addr_cycle;
-+ unsigned int addr_value[2];
-+ unsigned int cache_addr_value[2];
-+ unsigned int column;
-+ unsigned int block_page_mask;
++ unsigned int addr_cycle;
++ unsigned int addr_value[2];
++ unsigned int cache_addr_value[2];
++ unsigned int column;
++ unsigned int block_page_mask;
+
-+ unsigned int dma_buffer;
-+ unsigned int dma_oob;
++ unsigned int dma_buffer;
++ unsigned int dma_oob;
+
-+ unsigned int ecctype;
-+ unsigned int pagesize;
-+ unsigned int oobsize;
++ unsigned int ecctype;
++ unsigned int pagesize;
++ unsigned int oobsize;
+
-+ /* This is maybe an un-aligment address, only for malloc or free */
-+ char *buforg;
-+ char *buffer;
++ /* This is maybe an un-aligment address, only for malloc or free */
++ char *buforg;
++ char *buffer;
+
-+ int add_partition;
++ int add_partition;
+
-+ /* BOOTROM read two bytes to detect the bad block flag */
++ /* BOOTROM read two bytes to detect the bad block flag */
+#define HINFC_BAD_BLOCK_POS 0
-+ unsigned char *bbm; /* nand bad block mark */
-+ unsigned short *epm; /* nand empty page mark */
++ unsigned char *bbm; /* nand bad block mark */
++ unsigned short *epm; /* nand empty page mark */
+
-+ unsigned int uc_er;
++ unsigned int uc_er;
+
-+ void (*set_system_clock)(struct spi_op_info *op, int clk_en);
++ void (*set_system_clock)(struct spi_op_info *op, int clk_en);
+
-+ void (*send_cmd_pageprog)(struct hisnfc_host *host);
-+ void (*send_cmd_status)(struct hisnfc_host *host);
-+ void (*send_cmd_readstart)(struct hisnfc_host *host);
-+ void (*send_cmd_erase)(struct hisnfc_host *host);
-+ void (*send_cmd_readid)(struct hisnfc_host *host);
-+ void (*send_cmd_reset)(struct hisnfc_host *host);
++ void (*send_cmd_pageprog)(struct hisnfc_host *host);
++ void (*send_cmd_status)(struct hisnfc_host *host);
++ void (*send_cmd_readstart)(struct hisnfc_host *host);
++ void (*send_cmd_erase)(struct hisnfc_host *host);
++ void (*send_cmd_readid)(struct hisnfc_host *host);
++ void (*send_cmd_reset)(struct hisnfc_host *host);
+};
+
+/*****************************************************************************/
@@ -301775,7 +369989,7 @@ index 0000000..db59d51
+ } while ((!(regval & HISNFC100_INT_OP_DONE) && timeout)); \
+ if (!timeout) { \
+ DBG_BUG("hisnfc100 wait dma int finish timeout!\n"); \
-+ } \
++ } \
+}while (0)
+
+/*****************************************************************************/
@@ -301796,14 +370010,14 @@ index 0000000..db59d51
+void hisnfc100_nand_init(struct nand_chip *chip);
+
+int hisnfc100_ecc_probe(struct mtd_info *mtd, struct nand_chip *chip,
-+ struct nand_dev_t *nand_dev);
++ struct nand_dev_t *nand_dev);
+
+/******************************************************************************/
+#endif /* HISNFC100H */
+
diff --git a/drivers/mtd/nand/hisnfc100/hisnfc100_hi3516a.c b/drivers/mtd/nand/hisnfc100/hisnfc100_hi3516a.c
new file mode 100644
-index 0000000..5a3457b
+index 0000000..854614f
--- /dev/null
+++ b/drivers/mtd/nand/hisnfc100/hisnfc100_hi3516a.c
@@ -0,0 +1,93 @@
@@ -301851,61 +370065,61 @@ index 0000000..5a3457b
+/*****************************************************************************/
+void hisnfc100_set_system_clock(struct spi_op_info *op, int clk_en)
+{
-+ unsigned int base = IO_ADDRESS(CRG_REG_BASE);
-+ unsigned int regval, old_val;
++ unsigned int base = IO_ADDRESS(CRG_REG_BASE);
++ unsigned int regval, old_val;
+
-+ old_val = regval = readl((void *)(base + HISNFC100_CRG48));
++ old_val = regval = readl((void *)(base + HISNFC100_CRG48));
+
-+ regval &= ~SPI_NAND_CLK_SEL_MASK;
++ regval &= ~SPI_NAND_CLK_SEL_MASK;
+
-+ if (op && op->clock) {
-+ regval |= op->clock & SPI_NAND_CLK_SEL_MASK;
-+ } else {
-+ regval |= SPI_NAND_CLK_SEL_24M;
-+ }
++ if (op && op->clock) {
++ regval |= op->clock & SPI_NAND_CLK_SEL_MASK;
++ } else {
++ regval |= SPI_NAND_CLK_SEL_24M;
++ }
+
-+ if (clk_en) {
-+ regval |= HISNFC100_CRG48_SPI_NAND_CLK_EN;
-+ } else {
-+ regval &= ~HISNFC100_CRG48_SPI_NAND_CLK_EN;
-+ }
++ if (clk_en) {
++ regval |= HISNFC100_CRG48_SPI_NAND_CLK_EN;
++ } else {
++ regval &= ~HISNFC100_CRG48_SPI_NAND_CLK_EN;
++ }
+
-+ if (regval != old_val) {
-+ writel(regval, (void *)(base + HISNFC100_CRG48));
-+ }
++ if (regval != old_val) {
++ writel(regval, (void *)(base + HISNFC100_CRG48));
++ }
+}
+
+/*****************************************************************************/
+void hisnfc100_get_best_clock(unsigned int *clock)
+{
-+ int ix;
-+ int clk_reg;
++ int ix;
++ int clk_reg;
+#define CLK_2X(_clk) (((_clk) + 1) >> 1)
-+ unsigned int sysclk[] = {
-+ CLK_2X(24), SPI_NAND_CLK_SEL_24M,
-+ CLK_2X(75), SPI_NAND_CLK_SEL_75M,
-+ CLK_2X(125), SPI_NAND_CLK_SEL_125M,
-+ 0, 0,
-+ };
++ unsigned int sysclk[] = {
++ CLK_2X(24), SPI_NAND_CLK_SEL_24M,
++ CLK_2X(75), SPI_NAND_CLK_SEL_75M,
++ CLK_2X(125), SPI_NAND_CLK_SEL_125M,
++ 0, 0,
++ };
+#undef CLK_2X
+
-+ clk_reg = SPI_NAND_CLK_SEL_24M;
-+ for (ix = 0; sysclk[ix]; ix += 2) {
-+ if (*clock < sysclk[ix]) {
-+ break;
-+ }
-+ clk_reg = sysclk[ix + 1];
-+ }
++ clk_reg = SPI_NAND_CLK_SEL_24M;
++ for (ix = 0; sysclk[ix]; ix += 2) {
++ if (*clock < sysclk[ix]) {
++ break;
++ }
++ clk_reg = sysclk[ix + 1];
++ }
+
-+ *clock = clk_reg;
++ *clock = clk_reg;
+}
+
diff --git a/drivers/mtd/nand/hisnfc100/hisnfc100_os.c b/drivers/mtd/nand/hisnfc100/hisnfc100_os.c
new file mode 100644
-index 0000000..e1e4046
+index 0000000..312e9be
--- /dev/null
+++ b/drivers/mtd/nand/hisnfc100/hisnfc100_os.c
-@@ -0,0 +1,182 @@
+@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
@@ -301932,154 +370146,155 @@ index 0000000..e1e4046
+/*****************************************************************************/
+static int hisnfc100_os_probe(struct platform_device *pltdev)
+{
-+ int size, result = 0;
-+ struct hisnfc_host *host;
-+ struct nand_chip *chip;
-+ struct mtd_info *mtd;
-+ struct resource *res1, *res2 = NULL;
-+ struct device *dev = &pltdev->dev;
-+ struct device_node *np = NULL;
++ int size, result = 0;
++ struct hisnfc_host *host = NULL;
++ struct nand_chip *chip = NULL;
++ struct mtd_info *mtd = NULL;
++ struct resource *res1 = NULL;
++ struct resource *res2 = NULL;
++ struct device *dev = &pltdev->dev;
++ struct device_node *np = NULL;
+
-+ size = sizeof(struct hisnfc_host) + sizeof(struct nand_chip)
-+ + sizeof(struct mtd_info);
-+ host = kmalloc(size, GFP_KERNEL);
-+ if (!host) {
-+ PR_BUG("failed to allocate device structure.\n");
-+ return -ENOMEM;
-+ }
-+ memset((char *)host, 0, size);
-+ platform_set_drvdata(pltdev, host);
++ size = sizeof(struct hisnfc_host) + sizeof(struct nand_chip)
++ + sizeof(struct mtd_info);
++ host = kmalloc(size, GFP_KERNEL);
++ if (!host) {
++ PR_BUG("failed to allocate device structure.\n");
++ return -ENOMEM;
++ }
++ memset((char *)host, 0, size);
++ platform_set_drvdata(pltdev, host);
+
-+ host->dev = dev;
-+ host->chip = chip = (struct nand_chip *)&host[1];
-+ host->mtd = mtd = nand_to_mtd(chip);;
++ host->dev = dev;
++ host->chip = chip = (struct nand_chip *)&host[1];
++ host->mtd = mtd = nand_to_mtd(chip);;
+
-+ host->clk = devm_clk_get(dev, NULL);
-+ if (IS_ERR(host->clk)) {
-+ return PTR_ERR(host->clk);
-+ }
-+ /* enable and set system clock */
-+ clk_prepare_enable(host->clk);
++ host->clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(host->clk)) {
++ return PTR_ERR(host->clk);
++ }
++ /* enable and set system clock */
++ clk_prepare_enable(host->clk);
+
-+ res1 = platform_get_resource_byname(pltdev, IORESOURCE_MEM, "control");
-+ host->regbase = devm_ioremap_resource(dev, res1);
-+ if (IS_ERR(host->iobase)) {
-+ PR_BUG("Error: Can't get resource for reg address.\n");
-+ result = -EIO;
-+ goto fail;
-+ }
++ res1 = platform_get_resource_byname(pltdev, IORESOURCE_MEM, "control");
++ host->regbase = devm_ioremap_resource(dev, res1);
++ if (IS_ERR(host->iobase)) {
++ PR_BUG("Error: Can't get resource for reg address.\n");
++ result = -EIO;
++ goto fail;
++ }
+
-+ res2 = platform_get_resource_byname(pltdev, IORESOURCE_MEM, "memory");
-+ host->iobase = devm_ioremap_resource(dev, res2);
-+ if (IS_ERR(host->iobase)) {
-+ PR_BUG("Error: Can't get resource for buffer address.\n");
-+ result = -EIO;
-+ goto fail;
-+ }
++ res2 = platform_get_resource_byname(pltdev, IORESOURCE_MEM, "memory");
++ host->iobase = devm_ioremap_resource(dev, res2);
++ if (IS_ERR(host->iobase)) {
++ PR_BUG("Error: Can't get resource for buffer address.\n");
++ result = -EIO;
++ goto fail;
++ }
+
-+ memset((char *)host->iobase, 0xff, HISNFC100_BUFFER_BASE_ADDRESS_LEN);
-+ chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
++ memset((char *)host->iobase, 0xff, HISNFC100_BUFFER_BASE_ADDRESS_LEN);
++ chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
+
-+ host->buffer = dma_alloc_coherent(host->dev, HISNFC100_BUFFER_LEN,
-+ &host->dma_buffer, GFP_KERNEL);
-+ if (!host->buffer) {
-+ PR_BUG("Can't malloc memory for SPI Nand driver.");
-+ result = -ENOMEM;
-+ goto fail;
-+ }
-+ memset(host->buffer, 0xff, HISNFC100_BUFFER_LEN);
++ host->buffer = dma_alloc_coherent(host->dev, HISNFC100_BUFFER_LEN,
++ &host->dma_buffer, GFP_KERNEL);
++ if (!host->buffer) {
++ PR_BUG("Can't malloc memory for SPI Nand driver.");
++ result = -ENOMEM;
++ goto fail;
++ }
++ memset(host->buffer, 0xff, HISNFC100_BUFFER_LEN);
+
-+ np = of_get_next_available_child(dev->of_node, NULL);
-+ mtd->priv = chip;
-+ mtd->owner = THIS_MODULE;
-+ mtd->type = MTD_NANDFLASH;
-+ mtd->name = np->name;
++ np = of_get_next_available_child(dev->of_node, NULL);
++ mtd->priv = chip;
++ mtd->owner = THIS_MODULE;
++ mtd->type = MTD_NANDFLASH;
++ mtd->name = np->name;
+
-+ result = hisnfc100_host_init(host);
-+ if (result) {
-+ return result;
-+ }
++ result = hisnfc100_host_init(host);
++ if (result) {
++ return result;
++ }
+
-+ chip->priv = host;
-+ hisnfc100_nand_init(chip);
++ chip->priv = host;
++ hisnfc100_nand_init(chip);
+
-+ spi_nand_ids_register();
-+ hinfc_param_adjust = hisnfc100_ecc_probe;
++ spi_nand_ids_register();
++ hinfc_param_adjust = hisnfc100_ecc_probe;
+
-+ if (nand_scan(mtd, CONFIG_HISNFC100_MAX_CHIP)) {
-+ result = -ENXIO;
-+ goto fail;
-+ }
++ if (nand_scan(mtd, CONFIG_HISNFC100_MAX_CHIP)) {
++ result = -ENXIO;
++ goto fail;
++ }
+
-+ result = mtd_device_register(mtd, NULL, 0);
-+ if (result) {
-+ goto fail;
-+ }
++ result = mtd_device_register(mtd, NULL, 0);
++ if (result) {
++ goto fail;
++ }
+
-+ return result;
++ return result;
+
+fail:
-+ if (host->buffer) {
-+ dma_free_coherent(host->dev, HISNFC100_BUFFER_LEN,
-+ host->buffer, host->dma_buffer);
-+ host->buffer = NULL;
-+ }
-+ nand_release(host->mtd);
-+ kfree(host);
-+ platform_set_drvdata(pltdev, NULL);
++ if (host->buffer) {
++ dma_free_coherent(host->dev, HISNFC100_BUFFER_LEN,
++ host->buffer, host->dma_buffer);
++ host->buffer = NULL;
++ }
++ nand_release(host->mtd);
++ kfree(host);
++ platform_set_drvdata(pltdev, NULL);
+
-+ return result;
++ return result;
+}
+/*****************************************************************************/
+
+static int hisnfc100_os_remove(struct platform_device *pltdev)
+{
-+ struct hisnfc_host *host = platform_get_drvdata(pltdev);
++ struct hisnfc_host *host = platform_get_drvdata(pltdev);
+
-+ clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk);
+
-+ nand_release(host->mtd);
-+ dma_free_coherent(host->dev,
-+ (SPI_NAND_MAX_PAGESIZE + SPI_NAND_MAX_OOBSIZE),
-+ host->buffer, host->dma_buffer);
-+ kfree(host);
-+ platform_set_drvdata(pltdev, NULL);
++ nand_release(host->mtd);
++ dma_free_coherent(host->dev,
++ (SPI_NAND_MAX_PAGESIZE + SPI_NAND_MAX_OOBSIZE),
++ host->buffer, host->dma_buffer);
++ kfree(host);
++ platform_set_drvdata(pltdev, NULL);
+
-+ return 0;
++ return 0;
+}
+/*****************************************************************************/
+#ifdef CONFIG_PM
+/*****************************************************************************/
+static int hisnfc100_os_suspend(struct platform_device *pltdev,
-+ pm_message_t state)
++ pm_message_t state)
+{
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
+static int hisnfc100_os_resume(struct platform_device *pltdev)
+{
-+ return 0;
++ return 0;
+}
+#endif /* CONFIG_PM */
+
+/*****************************************************************************/
+static const struct of_device_id hisi_spi_nand_dt_ids[] = {
-+ { .compatible = "hisilicon,hisi-spi-nand" },
-+ { /* sentinel */ }
++ { .compatible = "hisilicon,hisi-spi-nand" },
++ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, hisi_spi_nand_dt_ids);
+
+static struct platform_driver hisi_nand_driver = {
-+ .driver = {
-+ .name = "hisi-nand",
-+ .of_match_table = hisi_spi_nand_dt_ids,
-+ },
-+ .probe = hisnfc100_os_probe,
-+ .remove = hisnfc100_os_remove,
++ .driver = {
++ .name = "hisi-nand",
++ .of_match_table = hisi_spi_nand_dt_ids,
++ },
++ .probe = hisnfc100_os_probe,
++ .remove = hisnfc100_os_remove,
+#ifdef CONFIG_PM
-+ .suspend = hisnfc100_os_suspend,
-+ .resume = hisnfc100_os_resume,
++ .suspend = hisnfc100_os_suspend,
++ .resume = hisnfc100_os_resume,
+#endif
+};
+module_platform_driver(hisi_nand_driver);
@@ -302170,7 +370385,7 @@ index 0000000..5d2b9c7
+
diff --git a/drivers/mtd/nand/hisnfc100/hisnfc100_spi_general.c b/drivers/mtd/nand/hisnfc100/hisnfc100_spi_general.c
new file mode 100644
-index 0000000..c3dee32
+index 0000000..bb1bf74
--- /dev/null
+++ b/drivers/mtd/nand/hisnfc100/hisnfc100_spi_general.c
@@ -0,0 +1,213 @@
@@ -302203,46 +370418,46 @@ index 0000000..c3dee32
+*/
+void spi_feature_op(struct hisnfc_host *host, int op, int addr, unsigned *val)
+{
-+ unsigned regval = 0;
-+ struct nand_chip *chip = host->chip;
++ unsigned regval = 0;
++ struct nand_chip *chip = host->chip;
+
-+ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
++ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
+
-+ hisfc_write(host, HISNFC100_OPCODE,
-+ (op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES));
-+ hisfc_write(host, HISNFC100_OP_ADDR, addr);
++ hisfc_write(host, HISNFC100_OPCODE,
++ (op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES));
++ hisfc_write(host, HISNFC100_OP_ADDR, addr);
+
-+ hisfc_write(host, HISNFC100_OP_CFG, HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
++ hisfc_write(host, HISNFC100_OP_CFG, HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
+
-+ regval = (HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
-+ | HISNFC100_OP_ADDR_NUM(FEATURES_OP_ADDR_NUM)
-+ | HISNFC100_OP_OPCODE_EN(ENABLE)
-+ | HISNFC100_OP_ADDR_EN(ENABLE)
-+ | HISNFC100_OP_START);
++ regval = (HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
++ | HISNFC100_OP_ADDR_NUM(FEATURES_OP_ADDR_NUM)
++ | HISNFC100_OP_OPCODE_EN(ENABLE)
++ | HISNFC100_OP_ADDR_EN(ENABLE)
++ | HISNFC100_OP_START);
+
-+ if (op == SET_OP) {
-+ hisfc_write(host, HISNFC100_DATA_NUM, FEATURES_DATE_NUM);
-+ regval |= HISNFC100_OP_DATE_WRITE_EN(ENABLE);
-+ writeb(*val, chip->IO_ADDR_W);
-+ if (DEBUG_SPI_NAND_DRV) {
-+ pr_info("hisnfc: set feature [%#x]==>[%#x]\n", addr,
-+ *val);
-+ }
-+ } else {
-+ regval |= HISNFC100_OP_STATUS_READ_EN(ENABLE);
-+ }
++ if (op == SET_OP) {
++ hisfc_write(host, HISNFC100_DATA_NUM, FEATURES_DATE_NUM);
++ regval |= HISNFC100_OP_DATE_WRITE_EN(ENABLE);
++ writeb(*val, chip->IO_ADDR_W);
++ if (DEBUG_SPI_NAND_DRV) {
++ pr_info("hisnfc: set feature [%#x]==>[%#x]\n", addr,
++ *val);
++ }
++ } else {
++ regval |= HISNFC100_OP_STATUS_READ_EN(ENABLE);
++ }
+
-+ hisfc_write(host, HISNFC100_OP, regval);
++ hisfc_write(host, HISNFC100_OP, regval);
+
-+ HISNFC100_CMD_WAIT_CPU_FINISH(host);
++ HISNFC100_CMD_WAIT_CPU_FINISH(host);
+
-+ if (op == GET_OP) {
-+ *val = hisfc_read(host, HISNFC100_STATUS);
-+ if (DEBUG_SPI_NAND_DRV && (addr != STATUS_ADDR)) {
-+ pr_info("hisnfc: get feature [%#x]<==[%#x]\n", addr,
-+ *val);
-+ }
-+ }
++ if (op == GET_OP) {
++ *val = hisfc_read(host, HISNFC100_STATUS);
++ if (DEBUG_SPI_NAND_DRV && (addr != STATUS_ADDR)) {
++ pr_info("hisnfc: get feature [%#x]<==[%#x]\n", addr,
++ *val);
++ }
++ }
+}
+
+/*****************************************************************************/
@@ -302251,29 +370466,29 @@ index 0000000..c3dee32
+*/
+static int spi_general_wait_ready(struct hisnfc_op *spi)
+{
-+ unsigned regval = 0;
-+ unsigned deadline = 0;
-+ struct hisnfc_host *host = (struct hisnfc_host *)spi->host;
++ unsigned regval = 0;
++ unsigned deadline = 0;
++ struct hisnfc_host *host = (struct hisnfc_host *)spi->host;
+
-+ do {
-+ spi_feature_op(host, GET_OP, STATUS_ADDR, ®val);
-+ if (!(regval & STATUS_OIP_MASK)) {
-+ if ((host->cmd_option.last_cmd == NAND_CMD_ERASE2)
-+ && (regval & STATUS_E_FAIL_MASK)) {
-+ return regval;
-+ }
-+ if ((host->cmd_option.last_cmd == NAND_CMD_PAGEPROG)
-+ && (regval & STATUS_P_FAIL_MASK)) {
-+ return regval;
-+ }
-+ return 0;
-+ }
-+ udelay(1);
-+ } while (deadline++ < (40 << 20));
++ do {
++ spi_feature_op(host, GET_OP, STATUS_ADDR, ®val);
++ if (!(regval & STATUS_OIP_MASK)) {
++ if ((host->cmd_option.last_cmd == NAND_CMD_ERASE2)
++ && (regval & STATUS_E_FAIL_MASK)) {
++ return regval;
++ }
++ if ((host->cmd_option.last_cmd == NAND_CMD_PAGEPROG)
++ && (regval & STATUS_P_FAIL_MASK)) {
++ return regval;
++ }
++ return 0;
++ }
++ udelay(1);
++ } while (deadline++ < (40 << 20));
+
-+ pr_info("hisnfc: wait ready timeout.\n");
++ pr_info("hisnfc: wait ready timeout.\n");
+
-+ return 1;
++ return 1;
+}
+
+/*****************************************************************************/
@@ -302282,36 +370497,36 @@ index 0000000..c3dee32
+*/
+static int spi_general_write_enable(struct hisnfc_op *spi)
+{
-+ unsigned val;
-+ struct hisnfc_host *host = (struct hisnfc_host *)spi->host;
++ unsigned val;
++ struct hisnfc_host *host = (struct hisnfc_host *)spi->host;
+
-+ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
++ hisfc_write(host, HISNFC100_INT_CLR, HISNFC100_INT_CLR_OP_DONE);
+
-+ val = hisfc_read(host, HISNFC100_GLOBAL_CFG);
-+ if (val & HISNFC100_GLOBAL_CFG_WP_ENABLE) {
-+ val &= ~HISNFC100_GLOBAL_CFG_WP_ENABLE;
-+ hisfc_write(host, HISNFC100_GLOBAL_CFG, val);
-+ }
++ val = hisfc_read(host, HISNFC100_GLOBAL_CFG);
++ if (val & HISNFC100_GLOBAL_CFG_WP_ENABLE) {
++ val &= ~HISNFC100_GLOBAL_CFG_WP_ENABLE;
++ hisfc_write(host, HISNFC100_GLOBAL_CFG, val);
++ }
+
-+ hisfc_write(host, HISNFC100_OPCODE, SPI_CMD_WREN);
++ hisfc_write(host, HISNFC100_OPCODE, SPI_CMD_WREN);
+
-+ hisfc_write(host, HISNFC100_OP_CFG,
-+ HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
++ hisfc_write(host, HISNFC100_OP_CFG,
++ HISNFC100_OP_CFG_DIR_TRANS_ENABLE);
+
-+ hisfc_write(host, HISNFC100_OP,
-+ HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
-+ | HISNFC100_OP_OPCODE_EN(ENABLE)
-+ | HISNFC100_OP_START);
++ hisfc_write(host, HISNFC100_OP,
++ HISNFC100_OP_SEL_CS(host->cmd_option.chipselect)
++ | HISNFC100_OP_OPCODE_EN(ENABLE)
++ | HISNFC100_OP_START);
+
-+ HISNFC100_CMD_WAIT_CPU_FINISH(host);
++ HISNFC100_CMD_WAIT_CPU_FINISH(host);
+
-+ spi_feature_op(host, GET_OP, STATUS_ADDR, &val);
-+ if (!(val & STATUS_WEL_MASK)) {
-+ pr_info("hisnfc: write enable failed! val[%#x]\n", val);
-+ return 1;
-+ }
++ spi_feature_op(host, GET_OP, STATUS_ADDR, &val);
++ if (!(val & STATUS_WEL_MASK)) {
++ pr_info("hisnfc: write enable failed! val[%#x]\n", val);
++ return 1;
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -302320,18 +370535,18 @@ index 0000000..c3dee32
+*/
+static int spi_is_quad(struct hisnfc_op *spi)
+{
-+ if (DEBUG_SPI_NAND_DRV) {
-+ pr_info("hisnfc: SPI write iftype:%d\n", spi->write->iftype);
-+ pr_info("hisnfc: SPI read iftype:%d\n", spi->read->iftype);
-+ }
++ if (DEBUG_SPI_NAND_DRV) {
++ pr_info("hisnfc: SPI write iftype:%d\n", spi->write->iftype);
++ pr_info("hisnfc: SPI read iftype:%d\n", spi->read->iftype);
++ }
+
-+ if (HISNFC100_IFCYCLE_QUAD == spi->write->iftype
-+ || HISNFC100_IFCYCLE_QUAD == spi->read->iftype
-+ || HISNFC100_IFCYCLE_QUAD_ADDR == spi->read->iftype) {
-+ return 1;
-+ }
++ if (HISNFC100_IFCYCLE_QUAD == spi->write->iftype
++ || HISNFC100_IFCYCLE_QUAD == spi->read->iftype
++ || HISNFC100_IFCYCLE_QUAD_ADDR == spi->read->iftype) {
++ return 1;
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -302340,56 +370555,56 @@ index 0000000..c3dee32
+*/
+static int spi_general_qe_enable(struct hisnfc_op *spi)
+{
-+ unsigned val, op;
-+ const char *str[] = {"Disable", "Enable"};
-+ struct hisnfc_host *host = (struct hisnfc_host *)spi->host;
++ unsigned val, op;
++ const char *str[] = {"Disable", "Enable"};
++ struct hisnfc_host *host = (struct hisnfc_host *)spi->host;
+
-+ if (DEBUG_SPI_NAND_DRV) {
-+ pr_info("* SPI Quad-Enable start.\n");
-+ }
++ if (DEBUG_SPI_NAND_DRV) {
++ pr_info("* SPI Quad-Enable start.\n");
++ }
+
-+ if (spi_is_quad(spi)) {
-+ op = ENABLE;
-+ } else {
-+ op = DISABLE;
-+ }
++ if (spi_is_quad(spi)) {
++ op = ENABLE;
++ } else {
++ op = DISABLE;
++ }
+
-+ if (DEBUG_SPI_NAND_DRV) {
-+ pr_info(" Read Quad status.\n");
-+ }
-+ spi_feature_op(host, GET_OP, FEATURE_ADDR, &val);
-+ if ((val & FEATURE_QE_ENABLE) == op) {
-+ if (DEBUG_SPI_NAND_DRV) {
-+ pr_info("* Quad is %s!\n", str[op]);
-+ }
-+ return 0;
-+ }
++ if (DEBUG_SPI_NAND_DRV) {
++ pr_info(" Read Quad status.\n");
++ }
++ spi_feature_op(host, GET_OP, FEATURE_ADDR, &val);
++ if ((val & FEATURE_QE_ENABLE) == op) {
++ if (DEBUG_SPI_NAND_DRV) {
++ pr_info("* Quad is %s!\n", str[op]);
++ }
++ return 0;
++ }
+
-+ if (op == ENABLE) {
-+ val |= FEATURE_QE_ENABLE;
-+ } else {
-+ val &= ~FEATURE_QE_ENABLE;
-+ }
-+ if (DEBUG_SPI_NAND_DRV) {
-+ pr_info(" %s Quad\n", str[op]);
-+ }
-+ spi_feature_op(host, SET_OP, FEATURE_ADDR, &val);
++ if (op == ENABLE) {
++ val |= FEATURE_QE_ENABLE;
++ } else {
++ val &= ~FEATURE_QE_ENABLE;
++ }
++ if (DEBUG_SPI_NAND_DRV) {
++ pr_info(" %s Quad\n", str[op]);
++ }
++ spi_feature_op(host, SET_OP, FEATURE_ADDR, &val);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ spi_feature_op(host, GET_OP, FEATURE_ADDR, &val);
-+ if ((val & FEATURE_QE_ENABLE) != op) {
-+ pr_info("hisnfc: %s Quad failed! val[%#x]\n", str[op], val);
-+ return 1;
-+ } else if (DEBUG_SPI_NAND_DRV) {
-+ pr_info("* %s Quad succeed!\n", str[op]);
-+ }
++ spi_feature_op(host, GET_OP, FEATURE_ADDR, &val);
++ if ((val & FEATURE_QE_ENABLE) != op) {
++ pr_info("hisnfc: %s Quad failed! val[%#x]\n", str[op], val);
++ return 1;
++ } else if (DEBUG_SPI_NAND_DRV) {
++ pr_info("* %s Quad succeed!\n", str[op]);
++ }
+
-+ return 0;
++ return 0;
+}
diff --git a/drivers/mtd/nand/hisnfc100/hisnfc100_spi_ids.c b/drivers/mtd/nand/hisnfc100/hisnfc100_spi_ids.c
new file mode 100644
-index 0000000..e17b47d
+index 0000000..3ede9e4
--- /dev/null
+++ b/drivers/mtd/nand/hisnfc100/hisnfc100_spi_ids.c
@@ -0,0 +1,1138 @@
@@ -302546,17 +370761,17 @@ index 0000000..e17b47d
+
+/*****************************************************************************/
+static struct spi_nand_driver spi_nand_driver_general = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .qe_enable = spi_general_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .qe_enable = spi_general_qe_enable,
+};
+
+/*
+ * Some spi nand don't need set QE bit enable.
+ */
+static struct spi_nand_driver spi_nand_driver_no_qe = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
+};
+
+/*****************************************************************************/
@@ -302592,948 +370807,948 @@ index 0000000..e17b47d
+* 2.2 Micron MT29F2G01ABA 256MB Add 1 chip
+******************************************************************************/
+struct hisnfc_chip_info hisnfc_spi_nand_flash_table[] = {
-+ /* Micron MT29F1G01ABA 1GBit */
-+ {
-+ .name = "MT29F1G01ABA",
-+ .id = {0x2C, 0x14},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(2, INFINITE, 80),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 80),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* Micron MT29F1G01ABA 1GBit */
++ {
++ .name = "MT29F1G01ABA",
++ .id = {0x2C, 0x14},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(2, INFINITE, 80),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 80),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* Micron MT29F2G01ABA 2GBit */
-+ {
-+ .name = "MT29F2G01ABA",
-+ .id = {0x2C, 0x24},
-+ .id_len = 2,
-+ .chipsize = SZ_256M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(2, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 108),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 80),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* Micron MT29F2G01ABA 2GBit */
++ {
++ .name = "MT29F2G01ABA",
++ .id = {0x2C, 0x24},
++ .id_len = 2,
++ .chipsize = SZ_256M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(2, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 108),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 80),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* ESMT F50L512M41A 512Mbit */
-+ {
-+ .name = "F50L512M41A",
-+ .id = {0xC8, 0x20},
-+ .id_len = 2,
-+ .chipsize = SZ_64M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* ESMT F50L512M41A 512Mbit */
++ {
++ .name = "F50L512M41A",
++ .id = {0xC8, 0x20},
++ .id_len = 2,
++ .chipsize = SZ_64M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* ESMT F50L1G41A 1Gbit */
-+ {
-+ .name = "F50L1G41A",
-+ .id = {0xC8, 0x21},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* ESMT F50L1G41A 1Gbit */
++ {
++ .name = "F50L1G41A",
++ .id = {0xC8, 0x21},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* GD 5F1GQ4UAYIG 1Gbit */
-+ {
-+ .name = "5F1GQ4UAYIG",
-+ .id = {0xc8, 0xf1},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* GD 5F1GQ4UAYIG 1Gbit */
++ {
++ .name = "5F1GQ4UAYIG",
++ .id = {0xc8, 0xf1},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* GD 5F1GQ4UBYIG 1Gbit */
-+ {
-+ .name = "5F1GQ4UBYIG",
-+ .id = {0xc8, 0xd1},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* GD 5F1GQ4UBYIG 1Gbit */
++ {
++ .name = "5F1GQ4UBYIG",
++ .id = {0xc8, 0xd1},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* GD 5F2GQ4UAYIG 2Gbit */
-+ {
-+ .name = "5F2GQ4UAYIG",
-+ .id = {0xc8, 0xf2},
-+ .id_len = 2,
-+ .chipsize = SZ_256M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* GD 5F2GQ4UAYIG 2Gbit */
++ {
++ .name = "5F2GQ4UAYIG",
++ .id = {0xc8, 0xf2},
++ .id_len = 2,
++ .chipsize = SZ_256M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* GD 5F2GQ4UBYIG 2Gbit */
-+ {
-+ .name = "5F2GQ4UBYIG",
-+ .id = {0xc8, 0xd2},
-+ .id_len = 2,
-+ .chipsize = SZ_256M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* GD 5F2GQ4UBYIG 2Gbit */
++ {
++ .name = "5F2GQ4UBYIG",
++ .id = {0xc8, 0xd2},
++ .id_len = 2,
++ .chipsize = SZ_256M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* GD 5F4GQ4UAYIG 4Gbit */
-+ {
-+ .name = "5F4GQ4UAYIG",
-+ .id = {0xc8, 0xf4},
-+ .id_len = 2,
-+ .chipsize = SZ_512M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* GD 5F4GQ4UAYIG 4Gbit */
++ {
++ .name = "5F4GQ4UAYIG",
++ .id = {0xc8, 0xf4},
++ .id_len = 2,
++ .chipsize = SZ_512M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* GD 5F4GQ4UBYIG 4Gbit */
-+ {
-+ .name = "5F4GQ4UBYIG",
-+ .id = {0xc8, 0xd4},
-+ .id_len = 2,
-+ .chipsize = SZ_512M,
-+ .erasesize = SZ_256K,
-+ .pagesize = SZ_4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 120),
-+ &READ_DUAL(1, INFINITE, 120),
-+ &READ_DUAL_ADDR(1, INFINITE, 120),
-+ &READ_QUAD(1, INFINITE, 120),
-+ &READ_QUAD_ADDR(1, INFINITE, 120),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 120),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, SZ_256K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* GD 5F4GQ4UBYIG 4Gbit */
++ {
++ .name = "5F4GQ4UBYIG",
++ .id = {0xc8, 0xd4},
++ .id_len = 2,
++ .chipsize = SZ_512M,
++ .erasesize = SZ_256K,
++ .pagesize = SZ_4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 120),
++ &READ_DUAL(1, INFINITE, 120),
++ &READ_DUAL_ADDR(1, INFINITE, 120),
++ &READ_QUAD(1, INFINITE, 120),
++ &READ_QUAD_ADDR(1, INFINITE, 120),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 120),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, SZ_256K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* Winbond W25N01GV 1Gbit */
-+ {
-+ .name = "W25N01GV",
-+ .id = {0xef, 0xaa, 0x21},
-+ .id_len = 3,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(2, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* Winbond W25N01GV 1Gbit */
++ {
++ .name = "W25N01GV",
++ .id = {0xef, 0xaa, 0x21},
++ .id_len = 3,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(2, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* ATO ATO25D1GA 1Gbit */
-+ {
-+ .name = "ATO25D1GA",
-+ .id = {0x9b, 0x12},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* ATO ATO25D1GA 1Gbit */
++ {
++ .name = "ATO25D1GA",
++ .id = {0x9b, 0x12},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* Micron MT29F1G01 */
-+ {
-+ .name = "MT29F1G01",
-+ .id = {0x2c, 0x12},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 50),
-+ &READ_DUAL(1, INFINITE, 50),
-+ &READ_QUAD(1, INFINITE, 50),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* Micron MT29F1G01 */
++ {
++ .name = "MT29F1G01",
++ .id = {0x2c, 0x12},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 50),
++ &READ_DUAL(1, INFINITE, 50),
++ &READ_QUAD(1, INFINITE, 50),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* Micron MT29F2G01 */
-+ {
-+ .name = "MT29F2G01",
-+ .id = {0x2c, 0x22},
-+ .id_len = 2,
-+ .chipsize = SZ_256M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 50),
-+ &READ_DUAL(1, INFINITE, 50),
-+ &READ_QUAD(1, INFINITE, 50),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* Micron MT29F2G01 */
++ {
++ .name = "MT29F2G01",
++ .id = {0x2c, 0x22},
++ .id_len = 2,
++ .chipsize = SZ_256M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 50),
++ &READ_DUAL(1, INFINITE, 50),
++ &READ_QUAD(1, INFINITE, 50),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* Micron MT29F4G01 */
-+ {
-+ .name = "MT29F4G01",
-+ .id = {0x2c, 0x32},
-+ .id_len = 2,
-+ .chipsize = SZ_512M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 50),
-+ &READ_DUAL(1, INFINITE, 50),
-+ &READ_QUAD(1, INFINITE, 50),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* Micron MT29F4G01 */
++ {
++ .name = "MT29F4G01",
++ .id = {0x2c, 0x32},
++ .id_len = 2,
++ .chipsize = SZ_512M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 50),
++ &READ_DUAL(1, INFINITE, 50),
++ &READ_QUAD(1, INFINITE, 50),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* MXIC MX35LF1GE4AB 1Gbit */
-+ {
-+ .name = "MX35LF1GE4AB",
-+ .id = {0xc2, 0x12},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* MXIC MX35LF1GE4AB 1Gbit */
++ {
++ .name = "MX35LF1GE4AB",
++ .id = {0xc2, 0x12},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* Paragon PN26G01A 1Gbit */
-+ {
-+ .name = "PN26G01A",
-+ .id = {0xa1, 0xe1},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(1, INFINITE, 108),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 108),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* Paragon PN26G01A 1Gbit */
++ {
++ .name = "PN26G01A",
++ .id = {0xa1, 0xe1},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(1, INFINITE, 108),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 108),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* Paragon PN26G02A 2Gbit */
-+ {
-+ .name = "PN26G02A",
-+ .id = {0xa1, 0xe2},
-+ .id_len = 2,
-+ .chipsize = SZ_256M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(1, INFINITE, 108),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 108),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* Paragon PN26G02A 2Gbit */
++ {
++ .name = "PN26G02A",
++ .id = {0xa1, 0xe2},
++ .id_len = 2,
++ .chipsize = SZ_256M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(1, INFINITE, 108),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 108),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* All-flash AFS1GQ4UAC 1Gbit */
-+ {
-+ .name = "AFS1GQ4UAC",
-+ .id = {0xc1, 0x51},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* All-flash AFS1GQ4UAC 1Gbit */
++ {
++ .name = "AFS1GQ4UAC",
++ .id = {0xc1, 0x51},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* All-flash AFS2GQ4UAD 2Gbit */
-+ {
-+ .name = "AFS2GQ4UAD",
-+ .id = {0xc1, 0x52},
-+ .id_len = 2,
-+ .chipsize = SZ_256M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 24),
-+ &WRITE_QUAD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 24),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* All-flash AFS2GQ4UAD 2Gbit */
++ {
++ .name = "AFS2GQ4UAD",
++ .id = {0xc1, 0x52},
++ .id_len = 2,
++ .chipsize = SZ_256M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 24),
++ &WRITE_QUAD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 24),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* TOSHIBA TC58CVG0S3H 1Gbit */
-+ {
-+ .name = "TC58CVG0S3H",
-+ .id = {0x98, 0xc2},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 64,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 104),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* TOSHIBA TC58CVG0S3H 1Gbit */
++ {
++ .name = "TC58CVG0S3H",
++ .id = {0x98, 0xc2},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 64,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 104),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* TOSHIBA TC58CVG2S0H 4Gbit */
-+ {
-+ .name = "TC58CVG2S0H",
-+ .id = {0x98, 0xcd},
-+ .id_len = 2,
-+ .chipsize = SZ_512M,
-+ .erasesize = SZ_256K,
-+ .pagesize = SZ_4K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, SZ_256K, 104),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_no_qe,
-+ },
++ /* TOSHIBA TC58CVG2S0H 4Gbit */
++ {
++ .name = "TC58CVG2S0H",
++ .id = {0x98, 0xcd},
++ .id_len = 2,
++ .chipsize = SZ_512M,
++ .erasesize = SZ_256K,
++ .pagesize = SZ_4K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, SZ_256K, 104),
++ 0
++ },
++ .driver = &spi_nand_driver_no_qe,
++ },
+
-+ /* HeYangTek HYF1GQ4UAACAE 1Gbit */
-+ {
-+ .name = "HYF1GQ4UAACAE",
-+ .id = {0xc9, 0x51},
-+ .id_len = 2,
-+ .chipsize = SZ_128M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 50),
-+ &READ_DUAL(1, INFINITE, 50),
-+ &READ_DUAL_ADDR(1, INFINITE, 60),
-+ &READ_QUAD(1, INFINITE, 50),
-+ &READ_QUAD_ADDR(1, INFINITE, 60),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 80),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* HeYangTek HYF1GQ4UAACAE 1Gbit */
++ {
++ .name = "HYF1GQ4UAACAE",
++ .id = {0xc9, 0x51},
++ .id_len = 2,
++ .chipsize = SZ_128M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 50),
++ &READ_DUAL(1, INFINITE, 50),
++ &READ_DUAL_ADDR(1, INFINITE, 60),
++ &READ_QUAD(1, INFINITE, 50),
++ &READ_QUAD_ADDR(1, INFINITE, 60),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 80),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* HeYangTek HYF2GQ4UAACAE 2Gbit */
-+ {
-+ .name = "HYF2GQ4UAACAE",
-+ .id = {0xc9, 0x52},
-+ .id_len = 2,
-+ .chipsize = SZ_256M,
-+ .erasesize = SZ_128K,
-+ .pagesize = SZ_2K,
-+ .oobsize = 128,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 50),
-+ &READ_DUAL(1, INFINITE, 50),
-+ &READ_DUAL_ADDR(1, INFINITE, 60),
-+ &READ_QUAD(1, INFINITE, 50),
-+ &READ_QUAD_ADDR(1, INFINITE, 60),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_128K(0, SZ_128K, 80),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* HeYangTek HYF2GQ4UAACAE 2Gbit */
++ {
++ .name = "HYF2GQ4UAACAE",
++ .id = {0xc9, 0x52},
++ .id_len = 2,
++ .chipsize = SZ_256M,
++ .erasesize = SZ_128K,
++ .pagesize = SZ_2K,
++ .oobsize = 128,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 50),
++ &READ_DUAL(1, INFINITE, 50),
++ &READ_DUAL_ADDR(1, INFINITE, 60),
++ &READ_QUAD(1, INFINITE, 50),
++ &READ_QUAD_ADDR(1, INFINITE, 60),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_128K(0, SZ_128K, 80),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ /* HeYangTek HYF4GQ4UAACBE 4Gbit */
-+ {
-+ .name = "HYF4GQ4UAACBE",
-+ .id = {0xc9, 0xd4},
-+ .id_len = 2,
-+ .chipsize = SZ_512M,
-+ .erasesize = SZ_256K,
-+ .pagesize = SZ_4K,
-+ .oobsize = 256,
-+ .badblock_pos = BBP_FIRST_PAGE,
-+ .read = {
-+ &READ_STD(1, INFINITE, 24),
-+ &READ_FAST(1, INFINITE, 50),
-+ &READ_DUAL(1, INFINITE, 50),
-+ &READ_DUAL_ADDR(1, INFINITE, 60),
-+ &READ_QUAD(1, INFINITE, 50),
-+ &READ_QUAD_ADDR(1, INFINITE, 60),
-+ 0
-+ },
-+ .write = {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ .erase = {
-+ &ERASE_SECTOR_256K(0, SZ_256K, 80),
-+ 0
-+ },
-+ .driver = &spi_nand_driver_general,
-+ },
++ /* HeYangTek HYF4GQ4UAACBE 4Gbit */
++ {
++ .name = "HYF4GQ4UAACBE",
++ .id = {0xc9, 0xd4},
++ .id_len = 2,
++ .chipsize = SZ_512M,
++ .erasesize = SZ_256K,
++ .pagesize = SZ_4K,
++ .oobsize = 256,
++ .badblock_pos = BBP_FIRST_PAGE,
++ .read = {
++ &READ_STD(1, INFINITE, 24),
++ &READ_FAST(1, INFINITE, 50),
++ &READ_DUAL(1, INFINITE, 50),
++ &READ_DUAL_ADDR(1, INFINITE, 60),
++ &READ_QUAD(1, INFINITE, 50),
++ &READ_QUAD_ADDR(1, INFINITE, 60),
++ 0
++ },
++ .write = {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ .erase = {
++ &ERASE_SECTOR_256K(0, SZ_256K, 80),
++ 0
++ },
++ .driver = &spi_nand_driver_general,
++ },
+
-+ { .id_len = 0, },
++ { .id_len = 0, },
+};
+
+/*****************************************************************************/
+static void hisnfc100_spi_search_rw(struct hisnfc_chip_info *spiinfo,
-+ struct spi_op_info *spiop_rw, unsigned iftype,
-+ unsigned max_dummy, int rw_type)
++ struct spi_op_info *spiop_rw, unsigned iftype,
++ unsigned max_dummy, int rw_type)
+{
-+ int ix = 0;
-+ struct spi_op_info **spiop, **fitspiop;
++ int ix = 0;
++ struct spi_op_info **spiop, **fitspiop;
+
-+ for (fitspiop = spiop = (rw_type ? spiinfo->write : spiinfo->read);
-+ (*spiop) && ix < MAX_SPI_NAND_OP; spiop++, ix++)
-+ if (((*spiop)->iftype & iftype)
-+ && ((*spiop)->dummy <= max_dummy)
-+ && (*fitspiop)->iftype < (*spiop)->iftype) {
-+ fitspiop = spiop;
-+ }
++ for (fitspiop = spiop = (rw_type ? spiinfo->write : spiinfo->read);
++ (*spiop) && ix < MAX_SPI_NAND_OP; spiop++, ix++)
++ if (((*spiop)->iftype & iftype)
++ && ((*spiop)->dummy <= max_dummy)
++ && (*fitspiop)->iftype < (*spiop)->iftype) {
++ fitspiop = spiop;
++ }
+
-+ memcpy(spiop_rw, (*fitspiop), sizeof(struct spi_op_info));
++ memcpy(spiop_rw, (*fitspiop), sizeof(struct spi_op_info));
+}
+
+/*****************************************************************************/
+static void hisnfc100_spi_get_erase(struct hisnfc_chip_info *spiinfo,
-+ struct spi_op_info *spiop_erase)
++ struct spi_op_info *spiop_erase)
+{
-+ int ix;
++ int ix;
+
-+ spiop_erase->size = 0;
-+ for (ix = 0; ix < MAX_SPI_NAND_OP; ix++) {
-+ if (spiinfo->erase[ix] == NULL) {
-+ break;
-+ }
-+ if (spiinfo->erasesize == spiinfo->erase[ix]->size) {
-+ memcpy(&spiop_erase[ix], spiinfo->erase[ix],
-+ sizeof(struct spi_op_info));
-+ break;
-+ }
-+ }
++ spiop_erase->size = 0;
++ for (ix = 0; ix < MAX_SPI_NAND_OP; ix++) {
++ if (spiinfo->erase[ix] == NULL) {
++ break;
++ }
++ if (spiinfo->erasesize == spiinfo->erase[ix]->size) {
++ memcpy(&spiop_erase[ix], spiinfo->erase[ix],
++ sizeof(struct spi_op_info));
++ break;
++ }
++ }
+}
+
+/*****************************************************************************/
+static void hisnfc100_map_iftype_and_clock(struct hisnfc_op *spi)
+{
-+ int ix;
-+ const int iftype_read[] = {
-+ SPI_IF_READ_STD, HISNFC100_IFCYCLE_STD,
-+ SPI_IF_READ_FAST, HISNFC100_IFCYCLE_STD,
-+ SPI_IF_READ_DUAL, HISNFC100_IFCYCLE_DUAL,
-+ SPI_IF_READ_DUAL_ADDR, HISNFC100_IFCYCLE_DUAL_ADDR,
-+ SPI_IF_READ_QUAD, HISNFC100_IFCYCLE_QUAD,
-+ SPI_IF_READ_QUAD_ADDR, HISNFC100_IFCYCLE_QUAD_ADDR,
-+ 0, 0,
-+ };
-+ const int iftype_write[] = {
-+ SPI_IF_WRITE_STD, HISNFC100_IFCYCLE_STD,
-+ SPI_IF_WRITE_QUAD, HISNFC100_IFCYCLE_QUAD,
-+ 0, 0,
-+ };
++ int ix;
++ const int iftype_read[] = {
++ SPI_IF_READ_STD, HISNFC100_IFCYCLE_STD,
++ SPI_IF_READ_FAST, HISNFC100_IFCYCLE_STD,
++ SPI_IF_READ_DUAL, HISNFC100_IFCYCLE_DUAL,
++ SPI_IF_READ_DUAL_ADDR, HISNFC100_IFCYCLE_DUAL_ADDR,
++ SPI_IF_READ_QUAD, HISNFC100_IFCYCLE_QUAD,
++ SPI_IF_READ_QUAD_ADDR, HISNFC100_IFCYCLE_QUAD_ADDR,
++ 0, 0,
++ };
++ const int iftype_write[] = {
++ SPI_IF_WRITE_STD, HISNFC100_IFCYCLE_STD,
++ SPI_IF_WRITE_QUAD, HISNFC100_IFCYCLE_QUAD,
++ 0, 0,
++ };
+
-+ for (ix = 0; iftype_write[ix]; ix += 2) {
-+ if (spi->write->iftype == iftype_write[ix]) {
-+ spi->write->iftype = iftype_write[ix + 1];
-+ break;
-+ }
-+ }
-+ hisnfc100_get_best_clock(&spi->write->clock);
++ for (ix = 0; iftype_write[ix]; ix += 2) {
++ if (spi->write->iftype == iftype_write[ix]) {
++ spi->write->iftype = iftype_write[ix + 1];
++ break;
++ }
++ }
++ hisnfc100_get_best_clock(&spi->write->clock);
+
-+ for (ix = 0; iftype_read[ix]; ix += 2) {
-+ if (spi->read->iftype == iftype_read[ix]) {
-+ spi->read->iftype = iftype_read[ix + 1];
-+ break;
-+ }
-+ }
-+ hisnfc100_get_best_clock(&spi->read->clock);
++ for (ix = 0; iftype_read[ix]; ix += 2) {
++ if (spi->read->iftype == iftype_read[ix]) {
++ spi->read->iftype = iftype_read[ix + 1];
++ break;
++ }
++ }
++ hisnfc100_get_best_clock(&spi->read->clock);
+
-+ hisnfc100_get_best_clock(&spi->erase->clock);
-+ spi->erase->iftype = HISNFC100_IFCYCLE_STD;
++ hisnfc100_get_best_clock(&spi->erase->clock);
++ spi->erase->iftype = HISNFC100_IFCYCLE_STD;
+}
+
+/*****************************************************************************/
+static void hisnfc100_spi_probe(struct hisnfc_host *host,
-+ struct hisnfc_chip_info *spi_dev)
++ struct hisnfc_chip_info *spi_dev)
+{
-+ unsigned regval;
-+ struct hisnfc_op *spi = host->spi;
++ unsigned regval;
++ struct hisnfc_op *spi = host->spi;
+
-+ spi->host = host;
-+ spi->driver = spi_dev->driver;
++ spi->host = host;
++ spi->driver = spi_dev->driver;
+
-+ hisnfc100_spi_search_rw(spi_dev, spi->read, HISNFC100_SUPPORT_READ,
-+ HISNFC100_SUPPORT_MAX_DUMMY, SPI_NAND_READ);
++ hisnfc100_spi_search_rw(spi_dev, spi->read, HISNFC100_SUPPORT_READ,
++ HISNFC100_SUPPORT_MAX_DUMMY, SPI_NAND_READ);
+
-+ hisnfc100_spi_search_rw(spi_dev, spi->write, HISNFC100_SUPPORT_WRITE,
-+ HISNFC100_SUPPORT_MAX_DUMMY, SPI_NAND_WRITE);
++ hisnfc100_spi_search_rw(spi_dev, spi->write, HISNFC100_SUPPORT_WRITE,
++ HISNFC100_SUPPORT_MAX_DUMMY, SPI_NAND_WRITE);
+
-+ hisnfc100_spi_get_erase(spi_dev, spi->erase);
-+ hisnfc100_map_iftype_and_clock(spi);
++ hisnfc100_spi_get_erase(spi_dev, spi->erase);
++ hisnfc100_map_iftype_and_clock(spi);
+
-+ if (spi->driver->qe_enable) {
-+ if (spi->driver->qe_enable(spi)) {
-+ pr_err("%s set feature QE failed!\n", __func__);
-+ }
-+ }
++ if (spi->driver->qe_enable) {
++ if (spi->driver->qe_enable(spi)) {
++ pr_err("%s set feature QE failed!\n", __func__);
++ }
++ }
+
-+ spi_feature_op(host, GET_OP, PROTECTION_ADDR, ®val);
-+ if (ANY_BP_ENABLE(regval)) {
-+ regval &= ~ALL_BP_MASK;
-+ spi_feature_op(host, SET_OP, PROTECTION_ADDR, ®val);
++ spi_feature_op(host, GET_OP, PROTECTION_ADDR, ®val);
++ if (ANY_BP_ENABLE(regval)) {
++ regval &= ~ALL_BP_MASK;
++ spi_feature_op(host, SET_OP, PROTECTION_ADDR, ®val);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ spi_feature_op(host, GET_OP, PROTECTION_ADDR, ®val);
-+ if (ANY_BP_ENABLE(regval)) {
-+ pr_err("%s write protection disable fail! val[%#x]\n",
-+ __func__, regval);
-+ }
-+ }
++ spi_feature_op(host, GET_OP, PROTECTION_ADDR, ®val);
++ if (ANY_BP_ENABLE(regval)) {
++ pr_err("%s write protection disable fail! val[%#x]\n",
++ __func__, regval);
++ }
++ }
+
-+ spi_feature_op(host, GET_OP, FEATURE_ADDR, ®val);
-+ if (regval & FEATURE_ECC_ENABLE) {
-+ regval &= ~FEATURE_ECC_ENABLE;
-+ spi_feature_op(host, SET_OP, FEATURE_ADDR, ®val);
++ spi_feature_op(host, GET_OP, FEATURE_ADDR, ®val);
++ if (regval & FEATURE_ECC_ENABLE) {
++ regval &= ~FEATURE_ECC_ENABLE;
++ spi_feature_op(host, SET_OP, FEATURE_ADDR, ®val);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ spi_feature_op(host, GET_OP, FEATURE_ADDR, ®val);
-+ if (regval & FEATURE_ECC_ENABLE) {
-+ pr_err("%s Internal ECC disable fail! val[%#x]\n",
-+ __func__, regval);
-+ }
-+ }
++ spi_feature_op(host, GET_OP, FEATURE_ADDR, ®val);
++ if (regval & FEATURE_ECC_ENABLE) {
++ pr_err("%s Internal ECC disable fail! val[%#x]\n",
++ __func__, regval);
++ }
++ }
+}
+
+static struct nand_flash_dev spi_nand_dev;
+/*****************************************************************************/
+static struct nand_flash_dev *spi_nand_get_flash_info(struct mtd_info *mtd,
-+ unsigned char *id)
++ unsigned char *id)
+{
-+ struct nand_chip *chip = mtd_to_nand(mtd);
-+ struct hisnfc_host *host = chip->priv;
-+ struct hisnfc_chip_info *spi_dev = hisnfc_spi_nand_flash_table;
-+ unsigned char ix = 0, len = 0, buffer[100];
-+ struct nand_flash_dev *flash_type = &spi_nand_dev;
++ struct nand_chip *chip = mtd_to_nand(mtd);
++ struct hisnfc_host *host = chip->priv;
++ struct hisnfc_chip_info *spi_dev = hisnfc_spi_nand_flash_table;
++ unsigned char ix = 0, len = 0, buffer[100];
++ struct nand_flash_dev *flash_type = &spi_nand_dev;
+
-+ len = sprintf(buffer, "SPI Nand(cs %d) ID: %#x %#x",
-+ host->cmd_option.chipselect, id[0], id[1]);
++ len = sprintf(buffer, "SPI Nand(cs %d) ID: %#x %#x",
++ host->cmd_option.chipselect, id[0], id[1]);
+
-+ for (; spi_dev->id_len; spi_dev++) {
-+ if (memcmp(id, spi_dev->id, spi_dev->id_len)) {
-+ continue;
-+ }
++ for (; spi_dev->id_len; spi_dev++) {
++ if (memcmp(id, spi_dev->id, spi_dev->id_len)) {
++ continue;
++ }
+
-+ for (ix = 2; ix < spi_dev->id_len; ix++) {
-+ len += sprintf(buffer + len, " %#x", id[ix]);
-+ }
-+ pr_info("%s\n", buffer);
++ for (ix = 2; ix < spi_dev->id_len; ix++) {
++ len += sprintf(buffer + len, " %#x", id[ix]);
++ }
++ pr_info("%s\n", buffer);
+
-+ flash_type->name = spi_dev->name;
-+ memcpy(flash_type->id, spi_dev->id, spi_dev->id_len);
-+ flash_type->pagesize = spi_dev->pagesize;
-+ flash_type->chipsize = spi_dev->chipsize >> 20;
-+ flash_type->erasesize = spi_dev->erasesize;
-+ flash_type->oobsize = spi_dev->oobsize;
++ flash_type->name = spi_dev->name;
++ memcpy(flash_type->id, spi_dev->id, spi_dev->id_len);
++ flash_type->pagesize = spi_dev->pagesize;
++ flash_type->chipsize = spi_dev->chipsize >> 20;
++ flash_type->erasesize = spi_dev->erasesize;
++ flash_type->oobsize = spi_dev->oobsize;
+
-+ mtd->size = spi_dev->chipsize;
-+ mtd->oobsize = spi_dev->oobsize;
-+ mtd->erasesize = spi_dev->erasesize;
-+ mtd->writesize = spi_dev->pagesize;
-+ chip->chipsize = spi_dev->chipsize;
++ mtd->size = spi_dev->chipsize;
++ mtd->oobsize = spi_dev->oobsize;
++ mtd->erasesize = spi_dev->erasesize;
++ mtd->writesize = spi_dev->pagesize;
++ chip->chipsize = spi_dev->chipsize;
+
-+ if (host->mtd != mtd) {
-+ host->mtd = mtd;
-+ }
-+ hisnfc100_spi_probe(host, spi_dev);
++ if (host->mtd != mtd) {
++ host->mtd = mtd;
++ }
++ hisnfc100_spi_probe(host, spi_dev);
+
-+ return flash_type;
-+ }
++ return flash_type;
++ }
+
-+ return NULL;
++ return NULL;
+}
+
+/*****************************************************************************/
+void spi_nand_ids_register(void)
+{
-+ pr_info("SPI Nand ID Table Version %s\n", SPI_NAND_ID_TAB_VER);
-+ get_spi_nand_flash_type_hook = spi_nand_get_flash_info;
++ pr_info("SPI Nand ID Table Version %s\n", SPI_NAND_ID_TAB_VER);
++ get_spi_nand_flash_type_hook = spi_nand_get_flash_info;
+}
+
diff --git a/drivers/mtd/nand/hisnfc100/hisnfc100_spi_ids.h b/drivers/mtd/nand/hisnfc100/hisnfc100_spi_ids.h
new file mode 100644
-index 0000000..208778e
+index 0000000..33dceb7
--- /dev/null
+++ b/drivers/mtd/nand/hisnfc100/hisnfc100_spi_ids.h
@@ -0,0 +1,148 @@
@@ -303634,42 +371849,42 @@ index 0000000..208778e
+/*****************************************************************************/
+/* SPI operation information */
+struct spi_op_info {
-+ unsigned char iftype;
-+ unsigned char cmd;
-+ unsigned char dummy;
-+ unsigned int size;
-+ unsigned int clock;
++ unsigned char iftype;
++ unsigned char cmd;
++ unsigned char dummy;
++ unsigned int size;
++ unsigned int clock;
+};
+
+struct spi_nand_driver;
+
+struct hisnfc_op {
-+ void *host;
-+ struct spi_nand_driver *driver;
-+ struct spi_op_info read[1];
-+ struct spi_op_info write[1];
-+ struct spi_op_info erase[MAX_SPI_NAND_OP];
++ void *host;
++ struct spi_nand_driver *driver;
++ struct spi_op_info read[1];
++ struct spi_op_info write[1];
++ struct spi_op_info erase[MAX_SPI_NAND_OP];
+};
+
+struct spi_nand_driver {
-+ int (*wait_ready)(struct hisnfc_op *spi);
-+ int (*write_enable)(struct hisnfc_op *spi);
-+ int (*qe_enable)(struct hisnfc_op *spi);
++ int (*wait_ready)(struct hisnfc_op *spi);
++ int (*write_enable)(struct hisnfc_op *spi);
++ int (*qe_enable)(struct hisnfc_op *spi);
+};
+
+struct hisnfc_chip_info {
-+ char *name;
-+ unsigned char id[MAX_ID_LEN];
-+ unsigned char id_len;
-+ unsigned long long chipsize;
-+ unsigned int erasesize;
-+ unsigned int pagesize;
-+ unsigned int oobsize;
-+ unsigned int badblock_pos;
-+ struct spi_op_info *read[MAX_SPI_NAND_OP];
-+ struct spi_op_info *write[MAX_SPI_NAND_OP];
-+ struct spi_op_info *erase[MAX_SPI_NAND_OP];
-+ struct spi_nand_driver *driver;
++ char *name;
++ unsigned char id[MAX_ID_LEN];
++ unsigned char id_len;
++ unsigned long long chipsize;
++ unsigned int erasesize;
++ unsigned int pagesize;
++ unsigned int oobsize;
++ unsigned int badblock_pos;
++ struct spi_op_info *read[MAX_SPI_NAND_OP];
++ struct spi_op_info *write[MAX_SPI_NAND_OP];
++ struct spi_op_info *erase[MAX_SPI_NAND_OP];
++ struct spi_nand_driver *driver;
+};
+
+/*****************************************************************************/
@@ -303687,7 +371902,7 @@ index 0000000..208778e
+
diff --git a/drivers/mtd/nand/match_table.c b/drivers/mtd/nand/match_table.c
new file mode 100644
-index 0000000..b07358a
+index 0000000..58932bf
--- /dev/null
+++ b/drivers/mtd/nand/match_table.c
@@ -0,0 +1,104 @@
@@ -303706,98 +371921,98 @@ index 0000000..b07358a
+/*****************************************************************************/
+int reg2type(struct match_reg_type *table, int length, int reg, int def)
+{
-+ while (length-- > 0) {
-+ if (table->reg == reg) {
-+ return table->type;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (length-- > 0) {
++ if (table->reg == reg) {
++ return table->type;
++ }
++ table++;
++ }
++ return def;
+}
+
+int type2reg(struct match_reg_type *table, int length, int type, int def)
+{
-+ while (length-- > 0) {
-+ if (table->type == type) {
-+ return table->reg;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (length-- > 0) {
++ if (table->type == type) {
++ return table->reg;
++ }
++ table++;
++ }
++ return def;
+}
+
+int str2type(struct match_type_str *table, int length, const char *str,
-+ int size, int def)
++ int size, int def)
+{
-+ while (length-- > 0) {
-+ if (!strncmp(table->str, str, size)) {
-+ return table->type;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (length-- > 0) {
++ if (!strncmp(table->str, str, size)) {
++ return table->type;
++ }
++ table++;
++ }
++ return def;
+}
+
+const char *type2str(struct match_type_str *table, int length, int type,
-+ const char *def)
++ const char *def)
+{
-+ while (length-- > 0) {
-+ if (table->type == type) {
-+ return table->str;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (length-- > 0) {
++ if (table->type == type) {
++ return table->str;
++ }
++ table++;
++ }
++ return def;
+}
+
+int match_reg_to_type(struct match_t *table, int nr_table, int reg, int def)
+{
-+ while (nr_table-- > 0) {
-+ if (table->reg == reg) {
-+ return table->type;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (nr_table-- > 0) {
++ if (table->reg == reg) {
++ return table->type;
++ }
++ table++;
++ }
++ return def;
+}
+
+int match_type_to_reg(struct match_t *table, int nr_table, int type, int def)
+{
-+ while (nr_table-- > 0) {
-+ if (table->type == type) {
-+ return table->reg;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (nr_table-- > 0) {
++ if (table->type == type) {
++ return table->reg;
++ }
++ table++;
++ }
++ return def;
+}
+
+int match_data_to_type(struct match_t *table, int nr_table,const char *data,
-+ int size, int def)
++ int size, int def)
+{
-+ while (nr_table-- > 0) {
-+ if (!memcmp(table->data, data, size)) {
-+ return table->type;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (nr_table-- > 0) {
++ if (!memcmp(table->data, data, size)) {
++ return table->type;
++ }
++ table++;
++ }
++ return def;
+}
+
+void *match_type_to_data(struct match_t *table, int nr_table, int type,
-+ const void *def)
++ const void *def)
+{
-+ while (nr_table-- > 0) {
-+ if (table->type == type) {
-+ return table->data;
-+ }
-+ table++;
-+ }
-+ return def;
++ while (nr_table-- > 0) {
++ if (table->type == type) {
++ return table->data;
++ }
++ table++;
++ }
++ return (void *)def;
+}
diff --git a/drivers/mtd/nand/match_table.h b/drivers/mtd/nand/match_table.h
new file mode 100644
-index 0000000..28e645b
+index 0000000..388564a
--- /dev/null
+++ b/drivers/mtd/nand/match_table.h
@@ -0,0 +1,56 @@
@@ -303813,19 +372028,19 @@ index 0000000..28e645b
+
+/*****************************************************************************/
+struct match_reg_type {
-+ int reg;
-+ int type;
++ int reg;
++ int type;
+};
+
+struct match_type_str {
-+ int type;
-+ const char *str;
++ int type;
++ const char *str;
+};
+
+struct match_t {
-+ int type;
-+ int reg;
-+ void *data;
++ int type;
++ int reg;
++ void *data;
+};
+
+/*****************************************************************************/
@@ -303839,20 +372054,20 @@ index 0000000..28e645b
+int type2reg(struct match_reg_type *table, int length, int type, int def);
+
+int str2type(struct match_type_str *table, int length, const char *str,
-+ int size, int def);
++ int size, int def);
+
+const char *type2str(struct match_type_str *table, int length, int type,
-+ const char *def);
++ const char *def);
+
+int match_reg_to_type(struct match_t *table, int nr_table, int reg, int def);
+
+int match_type_to_reg(struct match_t *table, int nr_table, int type, int def);
+
+int match_data_to_type(struct match_t *table, int nr_table,const char *data,
-+ int size, int def);
++ int size, int def);
+
+void *match_type_to_data(struct match_t *table, int nr_table, int type,
-+ const void *def);
++ const void *def);
+
+/*****************************************************************************/
+
@@ -304143,7 +372358,7 @@ index 0000000..bc5f400
+
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350.c b/drivers/mtd/spi-nor/hisfc350/hisfc350.c
new file mode 100644
-index 0000000..20d6532
+index 0000000..9147718
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350.c
@@ -0,0 +1,1617 @@
@@ -304226,1249 +372441,1249 @@ index 0000000..20d6532
+
+static char *ultohstr(unsigned long long size)
+{
-+ int ix;
-+ static char buffer[20];
-+ char *fmt[] = {"%u", "%uK", "%uM", "%uG", "%uT", "%uT"};
++ int ix;
++ static char buffer[20];
++ char *fmt[] = {"%u", "%uK", "%uM", "%uG", "%uT", "%uT"};
+
-+ for (ix = 0; (ix < 5) && !(size & 0x3FF) && size; ix++) {
-+ size = (size >> 10);
-+ }
++ for (ix = 0; (ix < 5) && !(size & 0x3FF) && size; ix++) {
++ size = (size >> 10);
++ }
+
-+ sprintf(buffer, fmt[ix], size);
-+ return buffer;
++ sprintf(buffer, fmt[ix], size);
++ return buffer;
+}
+
+#ifdef CONFIG_HISFC350_SHOW_CYCLE_TIMING
+static char *hisfc350_get_ifcycle_str(int ifcycle)
+{
-+ static char *ifcycle_str[] = {
-+ "single",
-+ "dual",
-+ "dual-addr",
-+ "dual-cmd",
-+ "reserve",
-+ "quad",
-+ "quad-addr",
-+ "quad-cmd",
-+ };
++ static char *ifcycle_str[] = {
++ "single",
++ "dual",
++ "dual-addr",
++ "dual-cmd",
++ "reserve",
++ "quad",
++ "quad-addr",
++ "quad-cmd",
++ };
+
-+ return ifcycle_str[(ifcycle & 0x07)];
++ return ifcycle_str[(ifcycle & 0x07)];
+}
+#endif
+
+static void hisfc350_set_host_addr_mode(struct hisfc_host *host, int enable)
+{
-+ unsigned int regval;
-+ regval = hisfc_read(host, HISFC350_GLOBAL_CONFIG);
-+ if (enable) {
-+ regval |= HISFC350_GLOBAL_CONFIG_ADDR_MODE_4B;
-+ } else {
-+ regval &= ~HISFC350_GLOBAL_CONFIG_ADDR_MODE_4B;
-+ }
++ unsigned int regval;
++ regval = hisfc_read(host, HISFC350_GLOBAL_CONFIG);
++ if (enable) {
++ regval |= HISFC350_GLOBAL_CONFIG_ADDR_MODE_4B;
++ } else {
++ regval &= ~HISFC350_GLOBAL_CONFIG_ADDR_MODE_4B;
++ }
+
-+ hisfc_write(host, HISFC350_GLOBAL_CONFIG, regval);
++ hisfc_write(host, HISFC350_GLOBAL_CONFIG, regval);
+}
+
+static void hisfc350_spi_nor_shutdown(struct platform_device *pdev)
+{
-+ if (start_up_mode == THREE_BYTE_ADDR_BOOT) {
-+ int ix;
++ if (start_up_mode == THREE_BYTE_ADDR_BOOT) {
++ int ix;
+
-+ struct hisfc_host *host = platform_get_drvdata(pdev);
-+ struct hisfc_spi *spi = host->spi;
++ struct hisfc_host *host = platform_get_drvdata(pdev);
++ struct hisfc_spi *spi = host->spi;
+
-+ for (ix = 0; ix < host->num_chip; ix++, spi++) {
-+ if (spi->addrcycle == SPI_4BYTE_ADDR_LEN) {
-+ spi->driver->wait_ready(spi);
-+ spi->driver->entry_4addr(spi, 0);
-+ }
-+ }
-+ }
++ for (ix = 0; ix < host->num_chip; ix++, spi++) {
++ if (spi->addrcycle == SPI_4BYTE_ADDR_LEN) {
++ spi->driver->wait_ready(spi);
++ spi->driver->entry_4addr(spi, 0);
++ }
++ }
++ }
+}
+static void hisfc350_map_iftype_and_clock(struct hisfc_spi *spi)
+{
-+ int ix;
-+ const int iftype_read[] = {
-+ SPI_IF_READ_STD, HISFC350_IFCYCLE_STD,
-+ SPI_IF_READ_FAST, HISFC350_IFCYCLE_STD,
-+ SPI_IF_READ_DUAL, HISFC350_IFCYCLE_DUAL,
-+ SPI_IF_READ_DUAL_ADDR, HISFC350_IFCYCLE_DUAL_ADDR,
-+ SPI_IF_READ_QUAD, HISFC350_IFCYCLE_QUAD,
-+ SPI_IF_READ_QUAD_ADDR, HISFC350_IFCYCLE_QUAD_ADDR,
-+ 0, 0,
-+ };
-+ const int iftype_write[] = {
-+ SPI_IF_WRITE_STD, HISFC350_IFCYCLE_STD,
-+ SPI_IF_WRITE_DUAL, HISFC350_IFCYCLE_DUAL,
-+ SPI_IF_WRITE_DUAL_ADDR, HISFC350_IFCYCLE_DUAL_ADDR,
-+ SPI_IF_WRITE_QUAD, HISFC350_IFCYCLE_QUAD,
-+ SPI_IF_WRITE_QUAD_ADDR, HISFC350_IFCYCLE_QUAD_ADDR,
-+ 0, 0,
-+ };
++ int ix;
++ const int iftype_read[] = {
++ SPI_IF_READ_STD, HISFC350_IFCYCLE_STD,
++ SPI_IF_READ_FAST, HISFC350_IFCYCLE_STD,
++ SPI_IF_READ_DUAL, HISFC350_IFCYCLE_DUAL,
++ SPI_IF_READ_DUAL_ADDR, HISFC350_IFCYCLE_DUAL_ADDR,
++ SPI_IF_READ_QUAD, HISFC350_IFCYCLE_QUAD,
++ SPI_IF_READ_QUAD_ADDR, HISFC350_IFCYCLE_QUAD_ADDR,
++ 0, 0,
++ };
++ const int iftype_write[] = {
++ SPI_IF_WRITE_STD, HISFC350_IFCYCLE_STD,
++ SPI_IF_WRITE_DUAL, HISFC350_IFCYCLE_DUAL,
++ SPI_IF_WRITE_DUAL_ADDR, HISFC350_IFCYCLE_DUAL_ADDR,
++ SPI_IF_WRITE_QUAD, HISFC350_IFCYCLE_QUAD,
++ SPI_IF_WRITE_QUAD_ADDR, HISFC350_IFCYCLE_QUAD_ADDR,
++ 0, 0,
++ };
+
-+ for (ix = 0; iftype_write[ix]; ix += 2) {
-+ if (spi->write->iftype == iftype_write[ix]) {
-+ spi->write->iftype = iftype_write[ix + 1];
-+ break;
-+ }
-+ }
-+ hisfc350_get_best_clock(&spi->write->clock);
++ for (ix = 0; iftype_write[ix]; ix += 2) {
++ if (spi->write->iftype == iftype_write[ix]) {
++ spi->write->iftype = iftype_write[ix + 1];
++ break;
++ }
++ }
++ hisfc350_get_best_clock(&spi->write->clock);
+
-+ for (ix = 0; iftype_read[ix]; ix += 2) {
-+ if (spi->read->iftype == iftype_read[ix]) {
-+ spi->read->iftype = iftype_read[ix + 1];
-+ break;
-+ }
-+ }
-+ hisfc350_get_best_clock(&spi->read->clock);
++ for (ix = 0; iftype_read[ix]; ix += 2) {
++ if (spi->read->iftype == iftype_read[ix]) {
++ spi->read->iftype = iftype_read[ix + 1];
++ break;
++ }
++ }
++ hisfc350_get_best_clock(&spi->read->clock);
+
-+ hisfc350_get_best_clock(&spi->erase->clock);
-+ spi->erase->iftype = HISFC350_IFCYCLE_STD;
++ hisfc350_get_best_clock(&spi->erase->clock);
++ spi->erase->iftype = HISFC350_IFCYCLE_STD;
+}
+
+static void hisfc350_dma_transfer(struct hisfc_host *host,
-+ loff_t spi_start_addr, unsigned char *dma_buffer,
-+ unsigned char is_read, size_t size, unsigned char chipselect)
++ loff_t spi_start_addr, unsigned char *dma_buffer,
++ unsigned char is_read, size_t size, unsigned char chipselect)
+{
-+ hisfc_write(host, HISFC350_BUS_DMA_MEM_SADDR, dma_buffer);
++ hisfc_write(host, HISFC350_BUS_DMA_MEM_SADDR, dma_buffer);
+
-+ hisfc_write(host, HISFC350_BUS_DMA_FLASH_SADDR,
-+ (u32)spi_start_addr);
++ hisfc_write(host, HISFC350_BUS_DMA_FLASH_SADDR,
++ (u32)spi_start_addr);
+
-+ hisfc_write(host, HISFC350_BUS_DMA_LEN,
-+ HISFC350_BUS_DMA_LEN_DATA_CNT(size));
++ hisfc_write(host, HISFC350_BUS_DMA_LEN,
++ HISFC350_BUS_DMA_LEN_DATA_CNT(size));
+
-+ hisfc_write(host, HISFC350_BUS_DMA_AHB_CTRL,
-+ HISFC350_BUS_DMA_AHB_CTRL_INCR4_EN
-+ | HISFC350_BUS_DMA_AHB_CTRL_INCR8_EN
-+ | HISFC350_BUS_DMA_AHB_CTRL_INCR16_EN);
++ hisfc_write(host, HISFC350_BUS_DMA_AHB_CTRL,
++ HISFC350_BUS_DMA_AHB_CTRL_INCR4_EN
++ | HISFC350_BUS_DMA_AHB_CTRL_INCR8_EN
++ | HISFC350_BUS_DMA_AHB_CTRL_INCR16_EN);
+
-+ hisfc_write(host, HISFC350_BUS_DMA_CTRL,
-+ HISFC350_BUS_DMA_CTRL_RW(is_read)
-+ | HISFC350_BUS_DMA_CTRL_CS(chipselect)
-+ | HISFC350_BUS_DMA_CTRL_START);
++ hisfc_write(host, HISFC350_BUS_DMA_CTRL,
++ HISFC350_BUS_DMA_CTRL_RW(is_read)
++ | HISFC350_BUS_DMA_CTRL_CS(chipselect)
++ | HISFC350_BUS_DMA_CTRL_START);
+
+#ifndef CONFIG_HISFC350_ENABLE_INTR_DMA
-+ HISFC350_DMA_WAIT_CPU_FINISH(host);
++ HISFC350_DMA_WAIT_CPU_FINISH(host);
+#endif
+}
+
+#ifdef HISFCV350_SUPPORT_REG_READ
+static char *hisfc350_reg_read_buf(struct hisfc_host *host,
-+ struct hisfc_spi *spi, loff_t spi_start_addr,
-+ unsigned int size, unsigned char *buffer)
++ struct hisfc_spi *spi, loff_t spi_start_addr,
++ unsigned int size, unsigned char *buffer)
+{
-+ int index = 0;
++ int index = 0;
+
-+ if (size > HISFC350_REG_BUF_SIZE) {
-+ DBG_BUG("reg read out of reg range.\n");
-+ }
++ if (size > HISFC350_REG_BUF_SIZE) {
++ DBG_BUG("reg read out of reg range.\n");
++ }
+
-+ hisfc_write(host, HISFC350_CMD_INS, spi->read->cmd);
-+ hisfc_write(host, HISFC350_CMD_ADDR,
-+ ((u32)spi_start_addr & HISFC350_CMD_ADDR_MASK));
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->read->iftype)
-+ | HISFC350_CMD_CONFIG_DATA_CNT(size)
-+ | HISFC350_CMD_CONFIG_RW_READ
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->read->dummy)
-+ | HISFC350_CMD_CONFIG_ADDR_EN
-+ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_INS, spi->read->cmd);
++ hisfc_write(host, HISFC350_CMD_ADDR,
++ ((u32)spi_start_addr & HISFC350_CMD_ADDR_MASK));
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->read->iftype)
++ | HISFC350_CMD_CONFIG_DATA_CNT(size)
++ | HISFC350_CMD_CONFIG_RW_READ
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->read->dummy)
++ | HISFC350_CMD_CONFIG_ADDR_EN
++ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ while (index < size) {
-+ *(unsigned int *)(host->reg_buffer + index) = hisfc_read(host,
-+ HISFC350_CMD_DATABUF0 + index);
-+ index += 4;
-+ }
++ while (index < size) {
++ *(unsigned int *)(host->reg_buffer + index) = hisfc_read(host,
++ HISFC350_CMD_DATABUF0 + index);
++ index += 4;
++ }
+
-+ memcpy(buffer, host->reg_buffer, size);
++ memcpy(buffer, host->reg_buffer, size);
+
-+ return buffer;
++ return buffer;
+}
+
+static int hisfc350_reg_read(struct mtd_info *mtd, loff_t from, size_t len,
-+ size_t *retlen, u_char *buf)
++ size_t *retlen, u_char *buf)
+{
-+ int num;
-+ int result = -EIO;
-+ unsigned char *ptr = buf;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ int num;
++ int result = -EIO;
++ unsigned char *ptr = buf;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((from + len) > mtd->size) {
-+ DBG_MSG("read area out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((from + len) > mtd->size) {
++ DBG_MSG("read area out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("read length is 0.\n");
-+ return 0;
-+ }
-+ mutex_lock(&host->lock);
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("read length is 0.\n");
++ return 0;
++ }
++ mutex_lock(&host->lock);
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ host->set_system_clock(host, spi->read, TRUE);
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ host->set_system_clock(host, spi->read, TRUE);
+
-+ while (len > 0) {
-+ while (from >= spi->chipsize) {
-+ from -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("read memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ host->set_system_clock(host, spi->read, TRUE);
-+ }
++ while (len > 0) {
++ while (from >= spi->chipsize) {
++ from -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("read memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ host->set_system_clock(host, spi->read, TRUE);
++ }
+
-+ num = ((from + len) >= spi->chipsize)
-+ ? (spi->chipsize - from) : len;
++ num = ((from + len) >= spi->chipsize)
++ ? (spi->chipsize - from) : len;
+
-+ while (num >= HISFC350_REG_BUF_SIZE) {
-+ hisfc350_reg_read_buf(host, spi,
-+ from, HISFC350_REG_BUF_SIZE, ptr);
-+ ptr += HISFC350_REG_BUF_SIZE;
-+ from += HISFC350_REG_BUF_SIZE;
-+ len -= HISFC350_REG_BUF_SIZE;
-+ num -= HISFC350_REG_BUF_SIZE;
-+ }
++ while (num >= HISFC350_REG_BUF_SIZE) {
++ hisfc350_reg_read_buf(host, spi,
++ from, HISFC350_REG_BUF_SIZE, ptr);
++ ptr += HISFC350_REG_BUF_SIZE;
++ from += HISFC350_REG_BUF_SIZE;
++ len -= HISFC350_REG_BUF_SIZE;
++ num -= HISFC350_REG_BUF_SIZE;
++ }
+
-+ if (num) {
-+ hisfc350_reg_read_buf(host, spi,
-+ from, num, ptr);
-+ from += num;
-+ ptr += num;
-+ len -= num;
-+ }
-+ }
-+ result = 0;
-+ *retlen = (size_t)(ptr - buf);
++ if (num) {
++ hisfc350_reg_read_buf(host, spi,
++ from, num, ptr);
++ from += num;
++ ptr += num;
++ len -= num;
++ }
++ }
++ result = 0;
++ *retlen = (size_t)(ptr - buf);
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#endif /* HISFCV350_SUPPORT_REG_READ */
+
+#ifdef CONFIG_HISFC350_ENABLE_INTR_DMA
+static int hisfc350_dma_intr_read(struct mtd_info *mtd, loff_t from, size_t len,
-+ size_t *retlen, u_char *buf)
++ size_t *retlen, u_char *buf)
+{
-+ int result = -EIO;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ int result = -EIO;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((from + len) > mtd->size) {
-+ DBG_MSG("read area out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((from + len) > mtd->size) {
++ DBG_MSG("read area out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("read length is 0.\n");
-+ return 0;
-+ }
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("read length is 0.\n");
++ return 0;
++ }
+
-+ mutex_lock(&host->lock);
++ mutex_lock(&host->lock);
+
-+ sfc_offset = (unsigned char *)buf;
-+ sfc_ft = from;
-+ sfc_length = len;
-+ sfc_rw = READ;
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, READ);
++ sfc_offset = (unsigned char *)buf;
++ sfc_ft = from;
++ sfc_length = len;
++ sfc_rw = READ;
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, READ);
+
-+ if (sfc_ft & HISFC350_DMA_ALIGN_MASK) {
-+ sfc_num = HISFC350_DMA_ALIGN_SIZE -
-+ (sfc_ft & HISFC350_DMA_ALIGN_MASK);
-+ if (sfc_num > sfc_length) {
-+ sfc_num = sfc_length;
-+ }
-+ while (sfc_ft >= spi->chipsize) {
-+ sfc_ft -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, sfc_rw);
-+ }
-+ } else {
-+ while (sfc_ft >= spi->chipsize) {
-+ sfc_ft -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("read memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, sfc_rw);
-+ }
-+ if ((sfc_ft + sfc_length) >= spi->chipsize) {
-+ sfc_num = spi->chipsize - sfc_ft;
-+ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
-+ sfc_num = HISFC350_DMA_MAX_SIZE;
-+ }
-+ } else {
-+ sfc_num = sfc_length;
-+ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
-+ sfc_num = HISFC350_DMA_MAX_SIZE;
-+ }
-+ }
-+ }
++ if (sfc_ft & HISFC350_DMA_ALIGN_MASK) {
++ sfc_num = HISFC350_DMA_ALIGN_SIZE -
++ (sfc_ft & HISFC350_DMA_ALIGN_MASK);
++ if (sfc_num > sfc_length) {
++ sfc_num = sfc_length;
++ }
++ while (sfc_ft >= spi->chipsize) {
++ sfc_ft -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, sfc_rw);
++ }
++ } else {
++ while (sfc_ft >= spi->chipsize) {
++ sfc_ft -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("read memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, sfc_rw);
++ }
++ if ((sfc_ft + sfc_length) >= spi->chipsize) {
++ sfc_num = spi->chipsize - sfc_ft;
++ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
++ sfc_num = HISFC350_DMA_MAX_SIZE;
++ }
++ } else {
++ sfc_num = sfc_length;
++ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
++ sfc_num = HISFC350_DMA_MAX_SIZE;
++ }
++ }
++ }
+
-+ hisfc350_dma_transfer(host, sfc_ft,
-+ (unsigned char *)host->dma_buffer, sfc_rw,
-+ sfc_num, spi->chipselect);
-+ wait_event(host->intr_wait, host->wait_fg == SFC_WAIT_FLAG_R);
-+ host->wait_fg = 0;
-+ result = 0;
-+ *retlen = (size_t)(sfc_offset - buf);
++ hisfc350_dma_transfer(host, sfc_ft,
++ (unsigned char *)host->dma_buffer, sfc_rw,
++ sfc_num, spi->chipselect);
++ wait_event(host->intr_wait, host->wait_fg == SFC_WAIT_FLAG_R);
++ host->wait_fg = 0;
++ result = 0;
++ *retlen = (size_t)(sfc_offset - buf);
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#else
+static int hisfc350_dma_read(struct mtd_info *mtd, loff_t from, size_t len,
-+ size_t *retlen, u_char *buf)
++ size_t *retlen, u_char *buf)
+{
-+ int num;
-+ int result = -EIO;
-+ unsigned char *ptr = buf;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ int num;
++ int result = -EIO;
++ unsigned char *ptr = buf;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((from + len) > mtd->size) {
-+ DBG_MSG("read area out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((from + len) > mtd->size) {
++ DBG_MSG("read area out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("read length is 0.\n");
-+ return 0;
-+ }
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("read length is 0.\n");
++ return 0;
++ }
+
-+ mutex_lock(&host->lock);
++ mutex_lock(&host->lock);
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, READ);
-+ host->set_system_clock(host, spi->read, TRUE);
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, READ);
++ host->set_system_clock(host, spi->read, TRUE);
+
-+ if (from & HISFC350_DMA_ALIGN_MASK) {
-+ num = HISFC350_DMA_ALIGN_SIZE -
-+ (from & HISFC350_DMA_ALIGN_MASK);
-+ if (num > len) {
-+ num = len;
-+ }
-+ while (from >= spi->chipsize) {
-+ from -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, READ);
-+ host->set_system_clock(host, spi->read, TRUE);
-+ }
-+ hisfc350_dma_transfer(host, from,
-+ (unsigned char *)host->dma_buffer, READ,
-+ num, spi->chipselect);
-+ memcpy(ptr, host->buffer, num);
-+ from += num;
-+ ptr += num;
-+ len -= num;
-+ }
++ if (from & HISFC350_DMA_ALIGN_MASK) {
++ num = HISFC350_DMA_ALIGN_SIZE -
++ (from & HISFC350_DMA_ALIGN_MASK);
++ if (num > len) {
++ num = len;
++ }
++ while (from >= spi->chipsize) {
++ from -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, READ);
++ host->set_system_clock(host, spi->read, TRUE);
++ }
++ hisfc350_dma_transfer(host, from,
++ (unsigned char *)host->dma_buffer, READ,
++ num, spi->chipselect);
++ memcpy(ptr, host->buffer, num);
++ from += num;
++ ptr += num;
++ len -= num;
++ }
+
-+ while (len > 0) {
-+ while (from >= spi->chipsize) {
-+ from -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("read memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, READ);
-+ host->set_system_clock(host, spi->read, TRUE);
-+ }
++ while (len > 0) {
++ while (from >= spi->chipsize) {
++ from -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("read memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, READ);
++ host->set_system_clock(host, spi->read, TRUE);
++ }
+
-+ num = ((from + len) >= spi->chipsize)
-+ ? (spi->chipsize - from) : len;
-+ while (num >= HISFC350_DMA_MAX_SIZE) {
-+ hisfc350_dma_transfer(host, from,
-+ (unsigned char *)host->dma_buffer, READ,
-+ HISFC350_DMA_MAX_SIZE, spi->chipselect);
-+ memcpy(ptr, host->buffer, HISFC350_DMA_MAX_SIZE);
-+ ptr += HISFC350_DMA_MAX_SIZE;
-+ from += HISFC350_DMA_MAX_SIZE;
-+ len -= HISFC350_DMA_MAX_SIZE;
-+ num -= HISFC350_DMA_MAX_SIZE;
-+ }
++ num = ((from + len) >= spi->chipsize)
++ ? (spi->chipsize - from) : len;
++ while (num >= HISFC350_DMA_MAX_SIZE) {
++ hisfc350_dma_transfer(host, from,
++ (unsigned char *)host->dma_buffer, READ,
++ HISFC350_DMA_MAX_SIZE, spi->chipselect);
++ memcpy(ptr, host->buffer, HISFC350_DMA_MAX_SIZE);
++ ptr += HISFC350_DMA_MAX_SIZE;
++ from += HISFC350_DMA_MAX_SIZE;
++ len -= HISFC350_DMA_MAX_SIZE;
++ num -= HISFC350_DMA_MAX_SIZE;
++ }
+
-+ if (num) {
-+ hisfc350_dma_transfer(host, from,
-+ (unsigned char *)host->dma_buffer, READ,
-+ num, spi->chipselect);
-+ memcpy(ptr, host->buffer, num);
-+ from += num;
-+ ptr += num;
-+ len -= num;
-+ }
-+ }
-+ result = 0;
-+ *retlen = (size_t)(ptr - buf);
++ if (num) {
++ hisfc350_dma_transfer(host, from,
++ (unsigned char *)host->dma_buffer, READ,
++ num, spi->chipselect);
++ memcpy(ptr, host->buffer, num);
++ from += num;
++ ptr += num;
++ len -= num;
++ }
++ }
++ result = 0;
++ *retlen = (size_t)(ptr - buf);
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#endif
+
+static unsigned char *hisfc350_read_ids(struct hisfc_host *host,
-+ int chipselect, unsigned char *buffer)
++ int chipselect, unsigned char *buffer)
+{
-+ int regindex = 0;
-+ int numread = 8;
-+ unsigned int *ptr = (unsigned int *)buffer;
++ int regindex = 0;
++ int numread = 8;
++ unsigned int *ptr = (unsigned int *)buffer;
+
-+ if (numread > HISFC350_REG_BUF_SIZE) {
-+ numread = HISFC350_REG_BUF_SIZE;
-+ }
++ if (numread > HISFC350_REG_BUF_SIZE) {
++ numread = HISFC350_REG_BUF_SIZE;
++ }
+
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_RDID);
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(chipselect)
-+ | HISFC350_CMD_CONFIG_RW_READ
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_DATA_CNT(numread)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_RDID);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(chipselect)
++ | HISFC350_CMD_CONFIG_RW_READ
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_DATA_CNT(numread)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ while (numread) {
-+ *ptr = hisfc_read(host,
-+ HISFC350_CMD_DATABUF0 + regindex);
-+ ptr += 1;
-+ regindex += 4;
-+ numread -= 4;
-+ }
++ while (numread) {
++ *ptr = hisfc_read(host,
++ HISFC350_CMD_DATABUF0 + regindex);
++ ptr += 1;
++ regindex += 4;
++ numread -= 4;
++ }
+
-+ return buffer;
++ return buffer;
+}
+
+static int hisfc350_reg_erase_one_block(struct hisfc_host *host,
-+ struct hisfc_spi *spi, unsigned int offset)
++ struct hisfc_spi *spi, unsigned int offset)
+{
-+ if (spi->driver->wait_ready(spi)) {
-+ return 1;
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ return 1;
++ }
+
-+ spi->driver->write_enable(spi);
-+ host->set_system_clock(host, spi->erase, TRUE);
++ spi->driver->write_enable(spi);
++ host->set_system_clock(host, spi->erase, TRUE);
+
-+ hisfc_write(host, HISFC350_CMD_INS, spi->erase->cmd);
++ hisfc_write(host, HISFC350_CMD_INS, spi->erase->cmd);
+
-+ hisfc_write(host, HISFC350_CMD_ADDR,
-+ (offset & HISFC350_CMD_ADDR_MASK));
++ hisfc_write(host, HISFC350_CMD_ADDR,
++ (offset & HISFC350_CMD_ADDR_MASK));
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->erase->iftype)
-+ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->erase->dummy)
-+ | HISFC350_CMD_CONFIG_ADDR_EN
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->erase->iftype)
++ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->erase->dummy)
++ | HISFC350_CMD_CONFIG_ADDR_EN
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ return 0;
++ return 0;
+}
+
+#ifdef CONFIG_HISFC350_ENABLE_INTR_DMA
+static int hisfc350_dma_intr_write(struct mtd_info *mtd, loff_t to, size_t len,
-+ size_t *retlen, const u_char *buf)
++ size_t *retlen, const u_char *buf)
+{
-+ int result = -EIO;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ int result = -EIO;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((to + len) > mtd->size) {
-+ DBG_MSG("write data out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((to + len) > mtd->size) {
++ DBG_MSG("write data out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("write length is 0.\n");
-+ return 0;
-+ }
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("write length is 0.\n");
++ return 0;
++ }
+
+#ifdef CONFIG_CMD_SPI_BLOCK_PROTECTION
-+ if ((host->cmp == BP_CMP_TOP) && ((to + len) > host->start_addr)) {
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n",
-+ host->start_addr, (to + len));
-+ return -EINVAL;
-+ }
++ if ((host->cmp == BP_CMP_TOP) && ((to + len) > host->start_addr)) {
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n",
++ host->start_addr, (to + len));
++ return -EINVAL;
++ }
+
-+ if ((host->cmp == BP_CMP_BOTTOM) && (to <= host->end_addr)) {
-+ unsigned end = ((to + len) > host->end_addr) \
-+ ? host->end_addr : (to + len);
++ if ((host->cmp == BP_CMP_BOTTOM) && (to <= host->end_addr)) {
++ unsigned end = ((to + len) > host->end_addr) \
++ ? host->end_addr : (to + len);
+
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n", to, end);
-+ return -EINVAL;
-+ }
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n", to, end);
++ return -EINVAL;
++ }
+#endif /* CONFIG_CMD_SPI_BLOCK_PROTECTION */
+
-+ mutex_lock(&host->lock);
++ mutex_lock(&host->lock);
+
-+ sfc_offset = (unsigned char *)buf;
-+ sfc_ft = to;
-+ sfc_length = len;
-+ sfc_rw = WRITE;
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
++ sfc_offset = (unsigned char *)buf;
++ sfc_ft = to;
++ sfc_length = len;
++ sfc_rw = WRITE;
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
+
-+ spi->driver->write_enable(spi);
-+ spi->driver->bus_prepare(spi, sfc_rw);
++ spi->driver->write_enable(spi);
++ spi->driver->bus_prepare(spi, sfc_rw);
+
-+ if (sfc_ft & HISFC350_DMA_ALIGN_MASK) {
-+ sfc_num = HISFC350_DMA_ALIGN_SIZE
-+ - (sfc_ft & HISFC350_DMA_ALIGN_MASK);
-+ if (sfc_num > sfc_length) {
-+ sfc_num = sfc_length;
-+ }
-+ while (sfc_ft >= spi->chipsize) {
-+ sfc_ft -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->write_enable(spi);
-+ spi->driver->bus_prepare(spi, sfc_rw);
-+ }
-+ } else {
-+ while (sfc_ft >= spi->chipsize) {
-+ sfc_ft -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("read memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->write_enable(spi);
-+ spi->driver->bus_prepare(spi, sfc_rw);
-+ }
-+ if ((sfc_ft + sfc_length) >= spi->chipsize) {
-+ sfc_num = spi->chipsize - sfc_ft;
-+ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
-+ sfc_num = HISFC350_DMA_MAX_SIZE;
-+ }
-+ } else {
-+ sfc_num = sfc_length;
-+ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
-+ sfc_num = HISFC350_DMA_MAX_SIZE;
-+ }
-+ }
-+ }
++ if (sfc_ft & HISFC350_DMA_ALIGN_MASK) {
++ sfc_num = HISFC350_DMA_ALIGN_SIZE
++ - (sfc_ft & HISFC350_DMA_ALIGN_MASK);
++ if (sfc_num > sfc_length) {
++ sfc_num = sfc_length;
++ }
++ while (sfc_ft >= spi->chipsize) {
++ sfc_ft -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->write_enable(spi);
++ spi->driver->bus_prepare(spi, sfc_rw);
++ }
++ } else {
++ while (sfc_ft >= spi->chipsize) {
++ sfc_ft -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("read memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->write_enable(spi);
++ spi->driver->bus_prepare(spi, sfc_rw);
++ }
++ if ((sfc_ft + sfc_length) >= spi->chipsize) {
++ sfc_num = spi->chipsize - sfc_ft;
++ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
++ sfc_num = HISFC350_DMA_MAX_SIZE;
++ }
++ } else {
++ sfc_num = sfc_length;
++ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
++ sfc_num = HISFC350_DMA_MAX_SIZE;
++ }
++ }
++ }
+
-+ memcpy(host->buffer, sfc_offset, sfc_num);
-+ hisfc350_dma_transfer(host, sfc_ft,
-+ (unsigned char *)host->dma_buffer, sfc_rw,
-+ sfc_num, spi->chipselect);
-+ wait_event(host->intr_wait, host->wait_fg == SFC_WAIT_FLAG_W);
-+ host->wait_fg = 0;
-+ *retlen = (size_t)(sfc_offset - buf);
-+ result = 0;
++ memcpy(host->buffer, sfc_offset, sfc_num);
++ hisfc350_dma_transfer(host, sfc_ft,
++ (unsigned char *)host->dma_buffer, sfc_rw,
++ sfc_num, spi->chipselect);
++ wait_event(host->intr_wait, host->wait_fg == SFC_WAIT_FLAG_W);
++ host->wait_fg = 0;
++ *retlen = (size_t)(sfc_offset - buf);
++ result = 0;
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#else
+static int hisfc350_dma_write(struct mtd_info *mtd, loff_t to, size_t len,
-+ size_t *retlen, const u_char *buf)
++ size_t *retlen, const u_char *buf)
+{
-+ int num;
-+ int result = -EIO;
++ int num;
++ int result = -EIO;
+
-+ unsigned char *ptr = (unsigned char *)buf;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ unsigned char *ptr = (unsigned char *)buf;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((to + len) > mtd->size) {
-+ DBG_MSG("write data out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((to + len) > mtd->size) {
++ DBG_MSG("write data out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("write length is 0.\n");
-+ return 0;
-+ }
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("write length is 0.\n");
++ return 0;
++ }
+
+#ifdef CONFIG_CMD_SPI_BLOCK_PROTECTION
-+ if (host->level) {
-+ if ((host->cmp == BP_CMP_TOP)
-+ && ((to + len) > host->start_addr)) {
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n",
-+ host->start_addr, (unsigned)(to + len));
-+ return -EINVAL;
-+ }
++ if (host->level) {
++ if ((host->cmp == BP_CMP_TOP)
++ && ((to + len) > host->start_addr)) {
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n",
++ host->start_addr, (unsigned)(to + len));
++ return -EINVAL;
++ }
+
-+ if ((host->cmp == BP_CMP_BOTTOM) && (to < host->end_addr)) {
-+ unsigned end = ((to + len) > host->end_addr) \
-+ ? host->end_addr : (to + len);
++ if ((host->cmp == BP_CMP_BOTTOM) && (to < host->end_addr)) {
++ unsigned end = ((to + len) > host->end_addr) \
++ ? host->end_addr : (to + len);
+
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n",
-+ (unsigned)to, end);
-+ return -EINVAL;
-+ }
-+ }
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n",
++ (unsigned)to, end);
++ return -EINVAL;
++ }
++ }
+#endif /* CONFIG_CMD_SPI_BLOCK_PROTECTION */
+
-+ mutex_lock(&host->lock);
++ mutex_lock(&host->lock);
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
+
-+ spi->driver->write_enable(spi);
-+ spi->driver->bus_prepare(spi, WRITE);
-+ host->set_system_clock(host, spi->write, TRUE);
++ spi->driver->write_enable(spi);
++ spi->driver->bus_prepare(spi, WRITE);
++ host->set_system_clock(host, spi->write, TRUE);
+
-+ if (to & HISFC350_DMA_ALIGN_MASK) {
-+ num = HISFC350_DMA_ALIGN_SIZE - (to & HISFC350_DMA_ALIGN_MASK);
-+ if (num > len) {
-+ num = len;
-+ }
-+ while (to >= spi->chipsize) {
-+ to -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->write_enable(spi);
-+ spi->driver->bus_prepare(spi, WRITE);
-+ host->set_system_clock(host, spi->write, TRUE);
-+ }
-+ memcpy(host->buffer, ptr, num);
-+ hisfc350_dma_transfer(host, to,
-+ (unsigned char *)host->dma_buffer, WRITE,
-+ num, spi->chipselect);
++ if (to & HISFC350_DMA_ALIGN_MASK) {
++ num = HISFC350_DMA_ALIGN_SIZE - (to & HISFC350_DMA_ALIGN_MASK);
++ if (num > len) {
++ num = len;
++ }
++ while (to >= spi->chipsize) {
++ to -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->write_enable(spi);
++ spi->driver->bus_prepare(spi, WRITE);
++ host->set_system_clock(host, spi->write, TRUE);
++ }
++ memcpy(host->buffer, ptr, num);
++ hisfc350_dma_transfer(host, to,
++ (unsigned char *)host->dma_buffer, WRITE,
++ num, spi->chipselect);
+
-+ to += num;
-+ ptr += num;
-+ len -= num;
-+ }
++ to += num;
++ ptr += num;
++ len -= num;
++ }
+
-+ while (len > 0) {
-+ num = ((len >= HISFC350_DMA_MAX_SIZE)
-+ ? HISFC350_DMA_MAX_SIZE : len);
-+ while (to >= spi->chipsize) {
-+ to -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write memory out of range.\n");
-+ }
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->write_enable(spi);
-+ spi->driver->bus_prepare(spi, WRITE);
-+ host->set_system_clock(host, spi->write, TRUE);
-+ }
++ while (len > 0) {
++ num = ((len >= HISFC350_DMA_MAX_SIZE)
++ ? HISFC350_DMA_MAX_SIZE : len);
++ while (to >= spi->chipsize) {
++ to -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write memory out of range.\n");
++ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->write_enable(spi);
++ spi->driver->bus_prepare(spi, WRITE);
++ host->set_system_clock(host, spi->write, TRUE);
++ }
+
-+ memcpy(host->buffer, ptr, num);
-+ hisfc350_dma_transfer(host, to,
-+ (unsigned char *)host->dma_buffer, WRITE,
-+ num, spi->chipselect);
++ memcpy(host->buffer, ptr, num);
++ hisfc350_dma_transfer(host, to,
++ (unsigned char *)host->dma_buffer, WRITE,
++ num, spi->chipselect);
+
-+ to += num;
-+ ptr += num;
-+ len -= num;
-+ }
-+ *retlen = (size_t)(ptr - buf);
-+ result = 0;
++ to += num;
++ ptr += num;
++ len -= num;
++ }
++ *retlen = (size_t)(ptr - buf);
++ result = 0;
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#endif
+
+#ifdef HISFCV350_SUPPORT_REG_WRITE
+static int hisfc350_reg_write_buf(struct hisfc_host *host,
-+ struct hisfc_spi *spi, unsigned int spi_start_addr,
-+ unsigned int size, unsigned char *buffer)
++ struct hisfc_spi *spi, unsigned int spi_start_addr,
++ unsigned int size, unsigned char *buffer)
+{
-+ int index = 0;
++ int index = 0;
+
-+ if (size > HISFC350_REG_BUF_SIZE) {
-+ DBG_BUG("reg read out of reg range.\n");
-+ }
++ if (size > HISFC350_REG_BUF_SIZE) {
++ DBG_BUG("reg read out of reg range.\n");
++ }
+
-+ if (spi->driver->wait_ready(spi)) {
-+ return 1;
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ return 1;
++ }
+
-+ memcpy(host->reg_buffer, buffer, size);
++ memcpy(host->reg_buffer, buffer, size);
+
-+ while (index < size) {
-+ hisfc_write(host, HISFC350_CMD_DATABUF0 + index,
-+ *(unsigned int *)(host->reg_buffer + index));
-+ index += 4;
-+ }
++ while (index < size) {
++ hisfc_write(host, HISFC350_CMD_DATABUF0 + index,
++ *(unsigned int *)(host->reg_buffer + index));
++ index += 4;
++ }
+
-+ spi->driver->write_enable(spi);
++ spi->driver->write_enable(spi);
+
-+ hisfc_write(host, HISFC350_CMD_INS, spi->write->cmd);
-+ hisfc_write(host, HISFC350_CMD_ADDR,
-+ ((u32)spi_start_addr & HISFC350_CMD_ADDR_MASK));
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->write->iftype)
-+ | HISFC350_CMD_CONFIG_DATA_CNT(size)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->write->dummy)
-+ | HISFC350_CMD_CONFIG_ADDR_EN
-+ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_INS, spi->write->cmd);
++ hisfc_write(host, HISFC350_CMD_ADDR,
++ ((u32)spi_start_addr & HISFC350_CMD_ADDR_MASK));
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->write->iftype)
++ | HISFC350_CMD_CONFIG_DATA_CNT(size)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->write->dummy)
++ | HISFC350_CMD_CONFIG_ADDR_EN
++ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ return 0;
++ return 0;
+}
+
+static int hisfc350_reg_write(struct mtd_info *mtd, loff_t to, size_t len,
-+ size_t *retlen, const u_char *buf)
++ size_t *retlen, const u_char *buf)
+{
-+ int num;
-+ int result = -EIO;
-+ unsigned char *ptr = (unsigned char *)buf;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ int num;
++ int result = -EIO;
++ unsigned char *ptr = (unsigned char *)buf;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((to + len) > mtd->size) {
-+ DBG_MSG("write data out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((to + len) > mtd->size) {
++ DBG_MSG("write data out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("write length is 0.\n");
-+ return 0;
-+ }
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("write length is 0.\n");
++ return 0;
++ }
+
+#ifdef CONFIG_CMD_SPI_BLOCK_PROTECTION
-+ if (host->level) {
-+ if ((host->cmp == BP_CMP_TOP)
-+ && ((to + len) > host->start_addr)) {
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n",
-+ host->start_addr, (to + len));
-+ return -EINVAL;
-+ }
++ if (host->level) {
++ if ((host->cmp == BP_CMP_TOP)
++ && ((to + len) > host->start_addr)) {
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n",
++ host->start_addr, (to + len));
++ return -EINVAL;
++ }
+
-+ if ((host->cmp == BP_CMP_BOTTOM) && (to < host->end_addr)) {
-+ unsigned end = ((to + len) > host->end_addr) \
-+ ? host->end_addr : (to + len);
++ if ((host->cmp == BP_CMP_BOTTOM) && (to < host->end_addr)) {
++ unsigned end = ((to + len) > host->end_addr) \
++ ? host->end_addr : (to + len);
+
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n", to, end);
-+ return -EINVAL;
-+ }
-+ }
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n", to, end);
++ return -EINVAL;
++ }
++ }
+#endif /* CONFIG_CMD_SPI_BLOCK_PROTECTION */
+
-+ mutex_lock(&host->lock);
++ mutex_lock(&host->lock);
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
+
-+ host->set_system_clock(host, spi->write, TRUE);
++ host->set_system_clock(host, spi->write, TRUE);
+
-+ if (to & HISFC350_REG_BUF_MASK) {
-+ num = HISFC350_REG_BUF_SIZE - (to & HISFC350_REG_BUF_MASK);
-+ if (num > (int)len) {
-+ num = (int)len;
-+ }
++ if (to & HISFC350_REG_BUF_MASK) {
++ num = HISFC350_REG_BUF_SIZE - (to & HISFC350_REG_BUF_MASK);
++ if (num > (int)len) {
++ num = (int)len;
++ }
+
-+ while (to >= spi->chipsize) {
-+ to -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write memory out of range.\n");
-+ }
++ while (to >= spi->chipsize) {
++ to -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write memory out of range.\n");
++ }
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
+
-+ host->set_system_clock(host, spi->write, TRUE);
-+ }
-+ if (hisfc350_reg_write_buf(host, spi, to, num, ptr)) {
-+ goto fail;
-+ }
-+ to += num;
-+ ptr += num;
-+ len -= num;
-+ }
++ host->set_system_clock(host, spi->write, TRUE);
++ }
++ if (hisfc350_reg_write_buf(host, spi, to, num, ptr)) {
++ goto fail;
++ }
++ to += num;
++ ptr += num;
++ len -= num;
++ }
+
-+ while (len > 0) {
-+ num = ((len >= HISFC350_REG_BUF_SIZE) ?
-+ HISFC350_REG_BUF_SIZE : len);
-+ while (to >= spi->chipsize) {
-+ to -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write memory out of range.\n");
-+ }
++ while (len > 0) {
++ num = ((len >= HISFC350_REG_BUF_SIZE) ?
++ HISFC350_REG_BUF_SIZE : len);
++ while (to >= spi->chipsize) {
++ to -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write memory out of range.\n");
++ }
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
+
-+ host->set_system_clock(host, spi->write, TRUE);
-+ }
-+ if (hisfc350_reg_write_buf(host, spi, to, num, ptr)) {
-+ goto fail;
-+ }
-+ to += num;
-+ ptr += num;
-+ len -= num;
-+ }
-+ *retlen = (size_t)(ptr - buf);
-+ result = 0;
++ host->set_system_clock(host, spi->write, TRUE);
++ }
++ if (hisfc350_reg_write_buf(host, spi, to, num, ptr)) {
++ goto fail;
++ }
++ to += num;
++ ptr += num;
++ len -= num;
++ }
++ *retlen = (size_t)(ptr - buf);
++ result = 0;
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#endif /* HISFCV350_SUPPORT_REG_WRITE */
+
+static int hisfc350_reg_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ unsigned long long offset = instr->addr;
-+ unsigned long long length = instr->len;
++ unsigned long long offset = instr->addr;
++ unsigned long long length = instr->len;
+
-+ if (offset + length > mtd->size) {
-+ DBG_MSG("erase area out of range of mtd.\n");
-+ return -EINVAL;
-+ }
++ if (offset + length > mtd->size) {
++ DBG_MSG("erase area out of range of mtd.\n");
++ return -EINVAL;
++ }
+
-+ if ((unsigned int)offset & (mtd->erasesize - 1)) {
-+ DBG_MSG("erase start address is not alignment.\n");
-+ return -EINVAL;
-+ }
++ if ((unsigned int)offset & (mtd->erasesize - 1)) {
++ DBG_MSG("erase start address is not alignment.\n");
++ return -EINVAL;
++ }
+
-+ if ((unsigned int)length & (mtd->erasesize - 1)) {
-+ DBG_MSG("erase length is not alignment.\n");
-+ return -EINVAL;
-+ }
++ if ((unsigned int)length & (mtd->erasesize - 1)) {
++ DBG_MSG("erase length is not alignment.\n");
++ return -EINVAL;
++ }
+
+#ifdef CONFIG_CMD_SPI_BLOCK_PROTECTION
-+ if (host->level) {
-+ if ((host->cmp == BP_CMP_TOP)
-+ && ((offset + length) > host->start_addr)) {
-+ DBG_MSG("erase area offset[%#x => %#x] is locked," \
-+ " please unlock these blocks on u-boot.\n",
-+ host->start_addr, (unsigned)(offset + length));
-+ return -EINVAL;
-+ }
++ if (host->level) {
++ if ((host->cmp == BP_CMP_TOP)
++ && ((offset + length) > host->start_addr)) {
++ DBG_MSG("erase area offset[%#x => %#x] is locked," \
++ " please unlock these blocks on u-boot.\n",
++ host->start_addr, (unsigned)(offset + length));
++ return -EINVAL;
++ }
+
-+ if ((host->cmp == BP_CMP_BOTTOM) && (offset < host->end_addr)) {
-+ unsigned end = ((offset + length) > host->end_addr) \
-+ ? host->end_addr : (offset + length);
++ if ((host->cmp == BP_CMP_BOTTOM) && (offset < host->end_addr)) {
++ unsigned end = ((offset + length) > host->end_addr) \
++ ? host->end_addr : (offset + length);
+
-+ DBG_MSG("erase area offset[%#x => %#x] is locked," \
-+ " please unlock these blocks on u-boot.\n",
-+ (unsigned)offset, end);
-+ return -EINVAL;
-+ }
-+ }
++ DBG_MSG("erase area offset[%#x => %#x] is locked," \
++ " please unlock these blocks on u-boot.\n",
++ (unsigned)offset, end);
++ return -EINVAL;
++ }
++ }
+#endif /* CONFIG_CMD_SPI_BLOCK_PROTECTION */
+
-+ mutex_lock(&host->lock);
-+ while (length) {
-+ if (spi->chipsize <= offset) {
-+ offset -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("erase memory out of range.\n");
-+ }
-+ }
++ mutex_lock(&host->lock);
++ while (length) {
++ if (spi->chipsize <= offset) {
++ offset -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("erase memory out of range.\n");
++ }
++ }
+
-+ if (hisfc350_reg_erase_one_block(host, spi, offset)) {
-+ instr->state = MTD_ERASE_FAILED;
-+ mutex_unlock(&host->lock);
-+ return -EIO;
-+ }
++ if (hisfc350_reg_erase_one_block(host, spi, offset)) {
++ instr->state = MTD_ERASE_FAILED;
++ mutex_unlock(&host->lock);
++ return -EIO;
++ }
+
-+ offset += spi->erase->size;
-+ length -= spi->erase->size;
-+ }
++ offset += spi->erase->size;
++ length -= spi->erase->size;
++ }
+
-+ instr->state = MTD_ERASE_DONE;
-+ mutex_unlock(&host->lock);
-+ mtd_erase_callback(instr);
-+ return 0;
++ instr->state = MTD_ERASE_DONE;
++ mutex_unlock(&host->lock);
++ mtd_erase_callback(instr);
++ return 0;
+}
+
+#ifdef HISFCV350_SUPPORT_BUS_READ
+static int hisfc350_bus_read(struct mtd_info *mtd, loff_t from, size_t len,
-+ size_t *retlen, u_char *buf)
++ size_t *retlen, u_char *buf)
+{
-+ int num;
-+ int result = -EIO;
-+ unsigned char *ptr = buf;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ int num;
++ int result = -EIO;
++ unsigned char *ptr = buf;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((from + len) > mtd->size) {
-+ DBG_MSG("read area out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((from + len) > mtd->size) {
++ DBG_MSG("read area out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("read length is 0.\n");
-+ return 0;
-+ }
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("read length is 0.\n");
++ return 0;
++ }
+
-+ mutex_lock(&host->lock);
++ mutex_lock(&host->lock);
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, READ);
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, READ);
+
-+ while (len > 0) {
-+ while (from >= spi->chipsize) {
-+ from -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("read memory out of range.\n");
-+ }
++ while (len > 0) {
++ while (from >= spi->chipsize) {
++ from -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("read memory out of range.\n");
++ }
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, READ);
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, READ);
++ }
+
-+ num = ((from + len) >= spi->chipsize)
-+ ? (spi->chipsize - from) : len;
++ num = ((from + len) >= spi->chipsize)
++ ? (spi->chipsize - from) : len;
+
-+ if (num) {
-+ memcpy(ptr, (char *)spi->iobase + from, num);
-+ from += num;
-+ ptr += num;
-+ len -= num;
-+ }
-+ }
-+ *retlen = (size_t)(ptr - buf);
-+ result = 0;
++ if (num) {
++ memcpy(ptr, (char *)spi->iobase + from, num);
++ from += num;
++ ptr += num;
++ len -= num;
++ }
++ }
++ *retlen = (size_t)(ptr - buf);
++ result = 0;
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#endif /* HISFCV350_SUPPORT_BUS_READ */
+
+#ifdef HISFCV350_SUPPORT_BUS_WRITE
+static int hisfc350_bus_write(struct mtd_info *mtd, loff_t to, size_t len,
-+ size_t *retlen, u_char *buf)
++ size_t *retlen, u_char *buf)
+{
-+ int num;
-+ int result = -EIO;
-+ unsigned char *ptr = buf;
-+ struct hisfc_host *host = MTD_TO_HOST(mtd);
-+ struct hisfc_spi *spi = host->spi;
++ int num;
++ int result = -EIO;
++ unsigned char *ptr = buf;
++ struct hisfc_host *host = MTD_TO_HOST(mtd);
++ struct hisfc_spi *spi = host->spi;
+
-+ if ((to + len) > mtd->size) {
-+ DBG_MSG("write data out of range.\n");
-+ return -EINVAL;
-+ }
++ if ((to + len) > mtd->size) {
++ DBG_MSG("write data out of range.\n");
++ return -EINVAL;
++ }
+
-+ *retlen = 0;
-+ if (!len) {
-+ DBG_MSG("write length is 0.\n");
-+ return 0;
-+ }
++ *retlen = 0;
++ if (!len) {
++ DBG_MSG("write length is 0.\n");
++ return 0;
++ }
+
+#ifdef CONFIG_CMD_SPI_BLOCK_PROTECTION
-+ if (host->level) {
-+ if ((host->cmp == BP_CMP_TOP)
-+ && ((to + len) > host->start_addr)) {
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n",
-+ host->start_addr, (to + len));
-+ return -EINVAL;
-+ }
++ if (host->level) {
++ if ((host->cmp == BP_CMP_TOP)
++ && ((to + len) > host->start_addr)) {
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n",
++ host->start_addr, (to + len));
++ return -EINVAL;
++ }
+
-+ if ((host->cmp == BP_CMP_BOTTOM) && (to < host->end_addr)) {
-+ unsigned end = ((to + len) > host->end_addr) \
-+ ? host->end_addr : (to + len);
++ if ((host->cmp == BP_CMP_BOTTOM) && (to < host->end_addr)) {
++ unsigned end = ((to + len) > host->end_addr) \
++ ? host->end_addr : (to + len);
+
-+ DBG_MSG("write area to[%#x => %#x] is locked, please " \
-+ "unlock these blocks on u-boot.\n", to, end);
-+ return -EINVAL;
-+ }
-+ }
++ DBG_MSG("write area to[%#x => %#x] is locked, please " \
++ "unlock these blocks on u-boot.\n", to, end);
++ return -EINVAL;
++ }
++ }
+#endif /* CONFIG_CMD_SPI_BLOCK_PROTECTION */
+
-+ mutex_lock(&host->lock);
++ mutex_lock(&host->lock);
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
+
-+ spi->driver->bus_prepare(spi, WRITE);
++ spi->driver->bus_prepare(spi, WRITE);
+
-+ while (len > 0) {
-+ while (to >= spi->chipsize) {
-+ to -= spi->chipsize;
-+ spi++;
-+ if (!spi->name) {
-+ DBG_BUG("write spi space out of range.\n");
-+ }
++ while (len > 0) {
++ while (to >= spi->chipsize) {
++ to -= spi->chipsize;
++ spi++;
++ if (!spi->name) {
++ DBG_BUG("write spi space out of range.\n");
++ }
+
-+ if (spi->driver->wait_ready(spi)) {
-+ goto fail;
-+ }
-+ spi->driver->bus_prepare(spi, WRITE);
-+ }
++ if (spi->driver->wait_ready(spi)) {
++ goto fail;
++ }
++ spi->driver->bus_prepare(spi, WRITE);
++ }
+
-+ num = ((to + len) >= spi->chipsize)
-+ ? (spi->chipsize - to) : len;
++ num = ((to + len) >= spi->chipsize)
++ ? (spi->chipsize - to) : len;
+
-+ if (num) {
-+ memcpy((char *)spi->iobase + to, ptr, num);
-+ ptr += num;
-+ to += num;
-+ len -= num;
-+ }
-+ }
++ if (num) {
++ memcpy((char *)spi->iobase + to, ptr, num);
++ ptr += num;
++ to += num;
++ len -= num;
++ }
++ }
+
-+ *retlen = (size_t)(ptr - buf);
-+ result = 0;
++ *retlen = (size_t)(ptr - buf);
++ result = 0;
+fail:
-+ mutex_unlock(&host->lock);
-+ return result;
++ mutex_unlock(&host->lock);
++ return result;
+}
+#endif
+
+static int hisfc350_map_chipsize(unsigned long long chipsize)
+{
-+ int shift = 0;
-+ chipsize >>= (19 - 3); /* 19: 512K; 3: Bytes -> bit */
++ int shift = 0;
++ chipsize >>= (19 - 3); /* 19: 512K; 3: Bytes -> bit */
+
-+ while (chipsize) {
-+ chipsize >>= 1;
-+ shift++;
-+ }
-+ return shift;
++ while (chipsize) {
++ chipsize >>= 1;
++ shift++;
++ }
++ return shift;
+}
+
+#ifdef CONFIG_HISFC350_ENABLE_INTR_DMA
+static irqreturn_t hisfc_irq(int irq, void *dev_id)
+{
-+ struct hisfc_host *host = dev_id;
-+ struct hisfc_spi *spi = host->spi;
-+ u32 state = 0;
-+ unsigned int tmp_reg = 0;
++ struct hisfc_host *host = dev_id;
++ struct hisfc_spi *spi = host->spi;
++ u32 state = 0;
++ unsigned int tmp_reg = 0;
+
-+ state = hisfc_read(host, SFC_RINTSTS);
-+ /* clear interrupt */
-+ tmp_reg = hisfc_read(host, SFC_INTCLR);
-+ tmp_reg |= ALL_INT_CLR;
-+ hisfc_write(host, SFC_INTCLR, tmp_reg);
++ state = hisfc_read(host, SFC_RINTSTS);
++ /* clear interrupt */
++ tmp_reg = hisfc_read(host, SFC_INTCLR);
++ tmp_reg |= ALL_INT_CLR;
++ hisfc_write(host, SFC_INTCLR, tmp_reg);
+
-+ if (sfc_rw == READ) {
-+ memcpy(sfc_offset, host->buffer, sfc_num);
-+ }
++ if (sfc_rw == READ) {
++ memcpy(sfc_offset, host->buffer, sfc_num);
++ }
+
-+ sfc_ft += sfc_num;
-+ sfc_offset += sfc_num;
-+ sfc_length -= sfc_num;
++ sfc_ft += sfc_num;
++ sfc_offset += sfc_num;
++ sfc_length -= sfc_num;
+
-+ if (state & SFC_DMA_INT_STATUS) {
-+ if (sfc_length > 0) {
-+ while (sfc_ft >= spi->chipsize) {
-+ sfc_ft -= spi->chipsize;
-+ spi++;
-+ if (sfc_rw == WRITE) {
-+ spi->driver->write_enable(spi);
-+ }
-+ spi->driver->bus_prepare(spi, sfc_rw);
-+ }
-+ if ((sfc_ft + sfc_length) >= spi->chipsize) {
-+ sfc_num = spi->chipsize - sfc_ft;
-+ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
-+ sfc_num = HISFC350_DMA_MAX_SIZE;
-+ }
-+ } else {
-+ sfc_num = sfc_length;
-+ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
-+ sfc_num = HISFC350_DMA_MAX_SIZE;
-+ }
-+ }
-+ if (sfc_rw == WRITE) {
-+ memcpy(host->buffer, sfc_offset, sfc_num);
-+ }
-+ hisfc350_dma_transfer(host, sfc_ft,
-+ (unsigned char *)host->dma_buffer, sfc_rw,
-+ sfc_num, spi->chipselect);
-+ } else {
-+ if (sfc_rw == READ) {
-+ host->wait_fg = SFC_WAIT_FLAG_R;
-+ } else if (sfc_rw == WRITE) {
-+ host->wait_fg = SFC_WAIT_FLAG_W;
-+ }
-+ wake_up(&host->intr_wait);
-+ }
-+ }
-+ return IRQ_HANDLED;
++ if (state & SFC_DMA_INT_STATUS) {
++ if (sfc_length > 0) {
++ while (sfc_ft >= spi->chipsize) {
++ sfc_ft -= spi->chipsize;
++ spi++;
++ if (sfc_rw == WRITE) {
++ spi->driver->write_enable(spi);
++ }
++ spi->driver->bus_prepare(spi, sfc_rw);
++ }
++ if ((sfc_ft + sfc_length) >= spi->chipsize) {
++ sfc_num = spi->chipsize - sfc_ft;
++ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
++ sfc_num = HISFC350_DMA_MAX_SIZE;
++ }
++ } else {
++ sfc_num = sfc_length;
++ if (sfc_num >= HISFC350_DMA_MAX_SIZE) {
++ sfc_num = HISFC350_DMA_MAX_SIZE;
++ }
++ }
++ if (sfc_rw == WRITE) {
++ memcpy(host->buffer, sfc_offset, sfc_num);
++ }
++ hisfc350_dma_transfer(host, sfc_ft,
++ (unsigned char *)host->dma_buffer, sfc_rw,
++ sfc_num, spi->chipselect);
++ } else {
++ if (sfc_rw == READ) {
++ host->wait_fg = SFC_WAIT_FLAG_R;
++ } else if (sfc_rw == WRITE) {
++ host->wait_fg = SFC_WAIT_FLAG_W;
++ }
++ wake_up(&host->intr_wait);
++ }
++ }
++ return IRQ_HANDLED;
+}
+#endif
+
+static int hisfc350_spi_probe(struct hisfc_host *host)
+{
-+ unsigned int regval = 0;
-+ unsigned int total = 0;
-+ unsigned char ids[8];
-+ struct spi_info *spiinfo;
-+ struct hisfc_spi *spi = host->spi;
-+ int chipselect = (CONFIG_HISFC350_CHIP_NUM - 1);
++ unsigned int regval = 0;
++ unsigned int total = 0;
++ unsigned char ids[8];
++ struct spi_info *spiinfo = NULL;
++ struct hisfc_spi *spi = host->spi;
++ int chipselect = (CONFIG_HISFC350_CHIP_NUM - 1);
+
-+ host->num_chip = 0;
++ host->num_chip = 0;
+
-+ for (; chipselect >= 0; chipselect--) {
++ for (; chipselect >= 0; chipselect--) {
+
-+ hisfc350_read_ids(host, chipselect, ids);
++ hisfc350_read_ids(host, chipselect, ids);
+
-+ /* can't find spi flash device. */
-+ if (!(ids[0] | ids[1] | ids[2])
-+ || ((ids[0] & ids[1] & ids[2]) == 0xFF)) {
-+ continue;
-+ }
++ /* can't find spi flash device. */
++ if (!(ids[0] | ids[1] | ids[2])
++ || ((ids[0] & ids[1] & ids[2]) == 0xFF)) {
++ continue;
++ }
+
-+ printk(KERN_INFO "Spi(cs%d) ID: 0x%02X 0x%02X 0x%02X"
-+ " 0x%02X 0x%02X 0x%02X\n",
-+ chipselect,
-+ ids[0], ids[1], ids[2], ids[3], ids[4], ids[5]);
++ printk(KERN_INFO "Spi(cs%d) ID: 0x%02X 0x%02X 0x%02X"
++ " 0x%02X 0x%02X 0x%02X\n",
++ chipselect,
++ ids[0], ids[1], ids[2], ids[3], ids[4], ids[5]);
+
-+ spiinfo = spi_serach_ids(ids);
++ spiinfo = spi_serach_ids(ids);
+
-+ if (spiinfo) {
-+ spi->name = spiinfo->name;
-+ spi->chipselect = chipselect;
-+ spi->chipsize = spiinfo->chipsize;
-+ spi->erasesize = spiinfo->erasesize;
-+ spi->addrcycle = spiinfo->addrcycle;
-+ spi->driver = spiinfo->driver;
-+ spi->host = host;
++ if (spiinfo) {
++ spi->name = spiinfo->name;
++ spi->chipselect = chipselect;
++ spi->chipsize = spiinfo->chipsize;
++ spi->erasesize = spiinfo->erasesize;
++ spi->addrcycle = spiinfo->addrcycle;
++ spi->driver = spiinfo->driver;
++ spi->host = host;
+
-+ spi_search_rw(spiinfo, spi->read,
-+ HISFC350_SUPPORT_READ,
-+ HISFC350_SUPPORT_MAX_DUMMY, READ);
-+ hisfc350_map_iftype_and_clock(spi);
++ spi_search_rw(spiinfo, spi->read,
++ HISFC350_SUPPORT_READ,
++ HISFC350_SUPPORT_MAX_DUMMY, READ);
++ hisfc350_map_iftype_and_clock(spi);
+
-+ spi->driver->qe_enable(spi);
++ spi->driver->qe_enable(spi);
+
-+ spi_search_rw(spiinfo, spi->read,
-+ HISFC350_SUPPORT_READ,
-+ HISFC350_SUPPORT_MAX_DUMMY, READ);
++ spi_search_rw(spiinfo, spi->read,
++ HISFC350_SUPPORT_READ,
++ HISFC350_SUPPORT_MAX_DUMMY, READ);
+
-+ spi_search_rw(spiinfo, spi->write,
-+ HISFC350_SUPPORT_WRITE,
-+ HISFC350_SUPPORT_MAX_DUMMY, WRITE);
++ spi_search_rw(spiinfo, spi->write,
++ HISFC350_SUPPORT_WRITE,
++ HISFC350_SUPPORT_MAX_DUMMY, WRITE);
+
-+ spi_get_erase(spiinfo, spi->erase);
-+ hisfc350_map_iftype_and_clock(spi);
++ spi_get_erase(spiinfo, spi->erase);
++ hisfc350_map_iftype_and_clock(spi);
+
-+ regval = hisfc_read(host, HISFC350_BUS_FLASH_SIZE);
-+ regval &= ~(HISFC350_BUS_FLASH_SIZE_CS0_MASK
-+ << (chipselect << 3));
-+ regval |= (hisfc350_map_chipsize(spi->chipsize)
-+ << (chipselect << 3));
-+ hisfc_write(host, HISFC350_BUS_FLASH_SIZE, regval);
++ regval = hisfc_read(host, HISFC350_BUS_FLASH_SIZE);
++ regval &= ~(HISFC350_BUS_FLASH_SIZE_CS0_MASK
++ << (chipselect << 3));
++ regval |= (hisfc350_map_chipsize(spi->chipsize)
++ << (chipselect << 3));
++ hisfc_write(host, HISFC350_BUS_FLASH_SIZE, regval);
+
-+ hisfc_write(host,
-+ (HISFC350_BUS_BASE_ADDR_CS0
-+ + (chipselect << 2)),
-+ (host->iobase + total));
++ hisfc_write(host,
++ (HISFC350_BUS_BASE_ADDR_CS0
++ + (chipselect << 2)),
++ (host->iobase + total));
+
-+ spi->iobase = (char *)host->iobase + total;
++ spi->iobase = (char *)host->iobase + total;
+
-+ /* auto check sfc_addr_mode 3 bytes or 4 bytes */
-+ start_up_mode = GET_SFC_ADDR_MODE;
++ /* auto check sfc_addr_mode 3 bytes or 4 bytes */
++ start_up_mode = GET_SFC_ADDR_MODE;
+
-+ if (start_up_mode == THREE_BYTE_ADDR_BOOT) {
-+ printk(KERN_INFO "SPI nor flash boot mode is" \
-+ " 3 Bytes\n");
-+ spi->driver->entry_4addr(spi, TRUE);
-+ } else
-+ printk(KERN_INFO "SPI nor flash boot mode is" \
-+ " 4 Bytes\n");
++ if (start_up_mode == THREE_BYTE_ADDR_BOOT) {
++ printk(KERN_INFO "SPI nor flash boot mode is" \
++ " 3 Bytes\n");
++ spi->driver->entry_4addr(spi, TRUE);
++ } else
++ printk(KERN_INFO "SPI nor flash boot mode is" \
++ " 4 Bytes\n");
+
-+ printk(KERN_INFO "Spi(cs%d): ", spi->chipselect);
-+ printk(KERN_INFO "Block:%sB", ultohstr(spi->erasesize));
-+ printk(KERN_INFO "Chip:%sB ", ultohstr(spi->chipsize));
-+ printk(KERN_INFO "Name:\"%s\"\n", spi->name);
++ printk(KERN_INFO "Spi(cs%d): ", spi->chipselect);
++ printk(KERN_INFO "Block:%sB", ultohstr(spi->erasesize));
++ printk(KERN_INFO "Chip:%sB ", ultohstr(spi->chipsize));
++ printk(KERN_INFO "Name:\"%s\"\n", spi->name);
+
+#ifdef CONFIG_HISFC350_SHOW_CYCLE_TIMING
+
-+ printk(KERN_INFO "Spi(cs%d): ", spi->chipselect);
-+ if (spi->addrcycle == SPI_4BYTE_ADDR_LEN) {
-+ printk(KERN_INFO "4 addrcycle ");
-+ }
-+ printk(KERN_INFO "read:%s,%02X,%s ",
-+ hisfc350_get_ifcycle_str(spi->read->iftype),
-+ spi->read->cmd,
-+ hisfc350_get_clock_str(spi->read->clock));
-+ printk(KERN_INFO "write:%s,%02X,%s ",
-+ hisfc350_get_ifcycle_str(spi->write->iftype),
-+ spi->write->cmd,
-+ hisfc350_get_clock_str(spi->write->clock));
-+ printk(KERN_INFO "erase:%s,%02X,%s\n",
-+ hisfc350_get_ifcycle_str(spi->erase[0].iftype),
-+ spi->erase[0].cmd,
-+ hisfc350_get_clock_str(spi->erase[0].clock));
++ printk(KERN_INFO "Spi(cs%d): ", spi->chipselect);
++ if (spi->addrcycle == SPI_4BYTE_ADDR_LEN) {
++ printk(KERN_INFO "4 addrcycle ");
++ }
++ printk(KERN_INFO "read:%s,%02X,%s ",
++ hisfc350_get_ifcycle_str(spi->read->iftype),
++ spi->read->cmd,
++ hisfc350_get_clock_str(spi->read->clock));
++ printk(KERN_INFO "write:%s,%02X,%s ",
++ hisfc350_get_ifcycle_str(spi->write->iftype),
++ spi->write->cmd,
++ hisfc350_get_clock_str(spi->write->clock));
++ printk(KERN_INFO "erase:%s,%02X,%s\n",
++ hisfc350_get_ifcycle_str(spi->erase[0].iftype),
++ spi->erase[0].cmd,
++ hisfc350_get_clock_str(spi->erase[0].clock));
+
+#endif /* CONFIG_HISFC350_SHOW_CYCLE_TIMING */
-+ host->num_chip++;
-+ total += spi->chipsize;
-+ spi++;
-+ } else
-+ printk(KERN_ERR"Spi(cs%d): find unrecognized spi flash.\n",
++ host->num_chip++;
++ total += spi->chipsize;
++ spi++;
++ } else
++ printk(KERN_ERR"Spi(cs%d): find unrecognized spi flash.\n",
+ chipselect);
+ }
+
@@ -305548,10 +373763,10 @@ index 0000000..20d6532
+static int hisfc350_spi_nor_probe(struct platform_device *pdev)
+{
+ int result = -EIO;
-+ struct hisfc_host *host;
++ struct hisfc_host *host = NULL;
+ struct mtd_info *mtd = NULL;
+ struct device *dev = &pdev->dev;
-+ struct resource *res;
++ struct resource *res = NULL;
+#ifdef CONFIG_HISFC350_ENABLE_INTR_DMA
+ int irq;
+ unsigned int tmp_reg = 0;
@@ -305766,7 +373981,7 @@ index 0000000..20d6532
+MODULE_DESCRIPTION("Hisfc350 Device Driver, Version 1.00");
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350.h b/drivers/mtd/spi-nor/hisfc350/hisfc350.h
new file mode 100644
-index 0000000..6b4d983
+index 0000000..1858c2e
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350.h
@@ -0,0 +1,327 @@
@@ -305967,18 +374182,18 @@ index 0000000..6b4d983
+#define BP_CMP_BOTTOM 1
+
+enum block_protection_level {
-+ BP_LEVEL_0 = 0,
-+ BP_LEVEL_1 = 1,
-+ BP_LEVEL_2 = 2,
-+ BP_LEVEL_3 = 3,
-+ BP_LEVEL_4 = 4,
-+ BP_LEVEL_5 = 5,
-+ BP_LEVEL_6 = 6,
-+ BP_LEVEL_7 = 7,
-+ BP_LEVEL_8 = 8,
-+ BP_LEVEL_9 = 9,
-+ BP_LEVEL_10 = 10,
-+ BP_LEVEL_END,
++ BP_LEVEL_0 = 0,
++ BP_LEVEL_1 = 1,
++ BP_LEVEL_2 = 2,
++ BP_LEVEL_3 = 3,
++ BP_LEVEL_4 = 4,
++ BP_LEVEL_5 = 5,
++ BP_LEVEL_6 = 6,
++ BP_LEVEL_7 = 7,
++ BP_LEVEL_8 = 8,
++ BP_LEVEL_9 = 9,
++ BP_LEVEL_10 = 10,
++ BP_LEVEL_END,
+};
+
+#define BP_LEVEL_MAX (BP_LEVEL_END - 1)
@@ -305988,58 +374203,58 @@ index 0000000..6b4d983
+struct hisfc_spi;
+
+struct spi_driver {
-+ int (*wait_ready)(struct hisfc_spi *spi);
-+ int (*write_enable)(struct hisfc_spi *spi);
-+ int (*entry_4addr)(struct hisfc_spi *spi, int enable);
-+ int (*bus_prepare)(struct hisfc_spi *spi, int op);
-+ int (*qe_enable)(struct hisfc_spi *spi);
++ int (*wait_ready)(struct hisfc_spi *spi);
++ int (*write_enable)(struct hisfc_spi *spi);
++ int (*entry_4addr)(struct hisfc_spi *spi, int enable);
++ int (*bus_prepare)(struct hisfc_spi *spi, int op);
++ int (*qe_enable)(struct hisfc_spi *spi);
+};
+
+struct hisfc_spi {
-+ char *name;
-+ int chipselect;
-+ unsigned long long chipsize;
-+ unsigned int erasesize;
-+ void __iomem *iobase;
++ char *name;
++ int chipselect;
++ unsigned long long chipsize;
++ unsigned int erasesize;
++ void __iomem *iobase;
+
-+ unsigned int addrcycle;
-+ struct spi_operation read[1];
-+ struct spi_operation write[1];
-+ struct spi_operation erase[MAX_SPI_OP];
-+ void *host;
-+ struct spi_driver *driver;
++ unsigned int addrcycle;
++ struct spi_operation read[1];
++ struct spi_operation write[1];
++ struct spi_operation erase[MAX_SPI_OP];
++ void *host;
++ struct spi_driver *driver;
+};
+
+struct hisfc_host {
-+ struct mtd_info mtd[1];
-+ void __iomem *iobase;
-+ void __iomem *regbase;
-+ struct device *dev;
-+ struct mutex lock;
-+ void __iomem *sysreg;
-+ struct clk *clk;
++ struct mtd_info mtd[1];
++ void __iomem *iobase;
++ void __iomem *regbase;
++ struct device *dev;
++ struct mutex lock;
++ void __iomem *sysreg;
++ struct clk *clk;
+#ifdef CONFIG_HISFC350_ENABLE_INTR_DMA
-+ wait_queue_head_t intr_wait;
-+ unsigned int wait_fg;
++ wait_queue_head_t intr_wait;
++ unsigned int wait_fg;
+#endif
-+ void (*set_system_clock)(struct hisfc_host *host,
-+ struct spi_operation *op, int clk_en);
++ void (*set_system_clock)(struct hisfc_host *host,
++ struct spi_operation *op, int clk_en);
+
-+ void (*set_host_addr_mode)(struct hisfc_host *host, int enable);
-+ char *buffer;
-+ unsigned int dma_buffer;
-+ int add_partition;
-+ int num_chip;
-+ struct hisfc_spi spi[CONFIG_HISFC350_CHIP_NUM + 1];
-+ char reg_buffer[HISFC350_REG_BUF_SIZE];
++ void (*set_host_addr_mode)(struct hisfc_host *host, int enable);
++ char *buffer;
++ unsigned int dma_buffer;
++ int add_partition;
++ int num_chip;
++ struct hisfc_spi spi[CONFIG_HISFC350_CHIP_NUM + 1];
++ char reg_buffer[HISFC350_REG_BUF_SIZE];
+
-+ int (*suspend)(struct platform_device *pltdev, pm_message_t state);
-+ int (*resume)(struct platform_device *pltdev);
++ int (*suspend)(struct platform_device *pltdev, pm_message_t state);
++ int (*resume)(struct platform_device *pltdev);
+#ifdef CONFIG_CMD_SPI_BLOCK_PROTECTION
-+ unsigned int start_addr;
-+ unsigned int end_addr;
-+ unsigned char cmp;
-+ unsigned char level;
++ unsigned int start_addr;
++ unsigned int end_addr;
++ unsigned char cmp;
++ unsigned char level;
+#endif
+};
+
@@ -306099,7 +374314,7 @@ index 0000000..6b4d983
+#endif /* HISFC350H */
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_hi3516a.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_hi3516a.c
new file mode 100644
-index 0000000..48aab21
+index 0000000..8b50741
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_hi3516a.c
@@ -0,0 +1,105 @@
@@ -306145,72 +374360,72 @@ index 0000000..48aab21
+ start_up_mode; })
+/*****************************************************************************/
+void hisfc350_set_system_clock(struct hisfc_host *host,
-+ struct spi_operation *op, int clk_en)
++ struct spi_operation *op, int clk_en)
+{
-+ unsigned int regval = readl(host->sysreg + HISFC350_CRG48);
++ unsigned int regval = readl(host->sysreg + HISFC350_CRG48);
+
-+ regval = regval & (~SFC_CLSEL_MASK);
++ regval = regval & (~SFC_CLSEL_MASK);
+
-+ if (op && op->clock) {
-+ regval &= ~SFC_CLSEL_MASK;
-+ regval |= op->clock & SFC_CLSEL_MASK;
-+ } else {
-+ regval &= ~SFC_CLSEL_MASK;
-+ regval |= HISFC350_CRG48_CLK_24M; /* Default Clock */
-+ }
++ if (op && op->clock) {
++ regval &= ~SFC_CLSEL_MASK;
++ regval |= op->clock & SFC_CLSEL_MASK;
++ } else {
++ regval &= ~SFC_CLSEL_MASK;
++ regval |= HISFC350_CRG48_CLK_24M; /* Default Clock */
++ }
+
-+ if (clk_en) {
-+ regval |= HISFC350_CRG48_CLKEN;
-+ }
++ if (clk_en) {
++ regval |= HISFC350_CRG48_CLKEN;
++ }
+
-+ if (regval != readl(host->sysreg + HISFC350_CRG48)) {
-+ writel(regval, (host->sysreg + HISFC350_CRG48));
-+ }
++ if (regval != readl(host->sysreg + HISFC350_CRG48)) {
++ writel(regval, (host->sysreg + HISFC350_CRG48));
++ }
+}
+
+/*****************************************************************************/
+void hisfc350_get_best_clock(unsigned int *clock)
+{
-+ int ix;
-+ int clk_reg;
++ int ix;
++ int clk_reg;
+
+#define CLK_2X(_clk) (((_clk) + 1) >> 1)
-+ unsigned int sysclk[] = {
-+ CLK_2X(24), HISFC350_CRG48_CLK_24M,
-+ CLK_2X(75), HISFC350_CRG48_CLK_75M,
-+ CLK_2X(125), HISFC350_CRG48_CLK_125M,
-+ 0, 0,
-+ };
++ unsigned int sysclk[] = {
++ CLK_2X(24), HISFC350_CRG48_CLK_24M,
++ CLK_2X(75), HISFC350_CRG48_CLK_75M,
++ CLK_2X(125), HISFC350_CRG48_CLK_125M,
++ 0, 0,
++ };
+#undef CLK_2X
+
-+ clk_reg = HISFC350_CRG48_CLK_24M;
-+ for (ix = 0; sysclk[ix]; ix += 2) {
-+ if (*clock < sysclk[ix]) {
-+ break;
-+ }
-+ clk_reg = sysclk[ix + 1];
-+ }
++ clk_reg = HISFC350_CRG48_CLK_24M;
++ for (ix = 0; sysclk[ix]; ix += 2) {
++ if (*clock < sysclk[ix]) {
++ break;
++ }
++ clk_reg = sysclk[ix + 1];
++ }
+
-+ *clock = clk_reg;
++ *clock = clk_reg;
+}
+
+/*****************************************************************************/
+#ifdef CONFIG_HISFC350_SHOW_CYCLE_TIMING
+char *hisfc350_get_clock_str(unsigned int clk_reg)
+{
-+ static char buffer[40];
++ static char buffer[40];
+
-+ /* calculate reference PERI_CLKDIV1[31:28] */
-+ clk_reg = 216 / ((clk_reg >> SFC_PERI_CLKDIV1_SHIFT)
-+ & SFC_PERI_CLKDIV1_MASK);
-+ sprintf(buffer, "%dM", clk_reg);
++ /* calculate reference PERI_CLKDIV1[31:28] */
++ clk_reg = 216 / ((clk_reg >> SFC_PERI_CLKDIV1_SHIFT)
++ & SFC_PERI_CLKDIV1_MASK);
++ sprintf(buffer, "%uM", clk_reg);
+
-+ return buffer;
++ return buffer;
+}
+#endif /* CONFIG_HISFC350_SHOW_CYCLE_TIMING */
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_en25q64.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_en25q64.c
new file mode 100644
-index 0000000..ad2e59d
+index 0000000..0db4bc8
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_en25q64.c
@@ -0,0 +1,29 @@
@@ -306241,11 +374456,11 @@ index 0000000..ad2e59d
+
+static int spi_en25q64_qe_enable(struct hisfc_spi *spi)
+{
-+ return 0;
++ return 0;
+}
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_gd25qxxx.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_gd25qxxx.c
new file mode 100644
-index 0000000..fffe555
+index 0000000..f9b678e
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_gd25qxxx.c
@@ -0,0 +1,111 @@
@@ -306284,85 +374499,85 @@ index 0000000..fffe555
+
+static int spi_gd25qxxx_qe_enable(struct hisfc_spi *spi)
+{
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
-+ unsigned int regval = 0;
-+ unsigned int qe_op1 = 0;
-+ unsigned int qe_op2 = 0;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ unsigned int regval = 0;
++ unsigned int qe_op1 = 0;
++ unsigned int qe_op2 = 0;
+
-+ if (hisfc350_is_quad(spi)) {
-+ qe_op1 = SPI_CMD_SR_QE;
-+ qe_op2 = GD_SPI_CMD_SR_QE;
-+ } else {
-+ qe_op1 = SPI_CMD_SR_XQE;
-+ qe_op2 = GD_SPI_CMD_SR_DISQE;
-+ }
++ if (hisfc350_is_quad(spi)) {
++ qe_op1 = SPI_CMD_SR_QE;
++ qe_op2 = GD_SPI_CMD_SR_QE;
++ } else {
++ qe_op1 = SPI_CMD_SR_XQE;
++ qe_op2 = GD_SPI_CMD_SR_DISQE;
++ }
+
-+ spi->driver->write_enable(spi);
++ spi->driver->write_enable(spi);
+
-+ /* First, we enable QE(4bit r&w) for 16pin gd flash */
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR1);
-+ hisfc_write(host, HISFC350_CMD_DATABUF0, qe_op1);
++ /* First, we enable QE(4bit r&w) for 16pin gd flash */
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR1);
++ hisfc_write(host, HISFC350_CMD_DATABUF0, qe_op1);
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->
-+ write->iftype)
-+ | HISFC350_CMD_CONFIG_DATA_CNT(2)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->
-+ write->dummy)
-+ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->
++ write->iftype)
++ | HISFC350_CMD_CONFIG_DATA_CNT(2)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->
++ write->dummy)
++ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ /* Second, we enable QE for 8 pin gd flash. This will not affect
-+ 16pin gd spi, if the QE bit has been set 1.
-+ */
-+ spi->driver->write_enable(spi);
++ /* Second, we enable QE for 8 pin gd flash. This will not affect
++ 16pin gd spi, if the QE bit has been set 1.
++ */
++ spi->driver->write_enable(spi);
+
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR2);
-+ hisfc_write(host, HISFC350_CMD_DATABUF0, qe_op2);
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR2);
++ hisfc_write(host, HISFC350_CMD_DATABUF0, qe_op2);
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->
-+ write->iftype)
-+ | HISFC350_CMD_CONFIG_DATA_CNT(1)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->
-+ write->dummy)
-+ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->
++ write->iftype)
++ | HISFC350_CMD_CONFIG_DATA_CNT(1)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_DUMMY_CNT(spi->
++ write->dummy)
++ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ if (DEBUG_SPI) {
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_RDSR2);
++ if (DEBUG_SPI) {
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_RDSR2);
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_DATA_CNT(1)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_RW_READ
-+ | HISFC350_CMD_CONFIG_START);
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
-+ regval = hisfc_read(host, HISFC350_CMD_DATABUF0);
-+ printk(KERN_INFO "QEbit = 0x2? : 0x%x\n", regval);
-+ if ((regval & GD_SPI_CMD_SR_QE)) {
-+ printk(KERN_INFO "QE bit enable success\n");
-+ } else {
-+ printk(KERN_INFO "QE bit enable failed\n");
-+ }
-+ }
-+ return 0;
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_DATA_CNT(1)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_RW_READ
++ | HISFC350_CMD_CONFIG_START);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ regval = hisfc_read(host, HISFC350_CMD_DATABUF0);
++ printk(KERN_INFO "QEbit = 0x2? : 0x%x\n", regval);
++ if ((regval & GD_SPI_CMD_SR_QE)) {
++ printk(KERN_INFO "QE bit enable success\n");
++ } else {
++ printk(KERN_INFO "QE bit enable failed\n");
++ }
++ }
++ return 0;
+}
+
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_general.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_general.c
new file mode 100644
-index 0000000..f762528
+index 0000000..a5b070e
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_general.c
@@ -0,0 +1,284 @@
@@ -306399,79 +374614,79 @@ index 0000000..f762528
+/*****************************************************************************/
+u_char spi_general_get_flash_register(struct hisfc_spi *spi, u_char cmd)
+{
-+ unsigned char status;
-+ unsigned int regval;
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ unsigned char status;
++ unsigned int regval;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ if (DEBUG_GET_SR) {
-+ printk(KERN_INFO "* Start get flash Register %#x.\n", cmd);
-+ }
++ if (DEBUG_GET_SR) {
++ printk(KERN_INFO "* Start get flash Register %#x.\n", cmd);
++ }
+
-+ hisfc_write(host, HISFC350_CMD_INS, cmd);
-+ if (DEBUG_GET_SR) {
-+ printk(KERN_INFO " Set INS[%#x]%#x\n", HISFC350_CMD_INS, cmd);
-+ }
++ hisfc_write(host, HISFC350_CMD_INS, cmd);
++ if (DEBUG_GET_SR) {
++ printk(KERN_INFO " Set INS[%#x]%#x\n", HISFC350_CMD_INS, cmd);
++ }
+
-+ regval = HISFC350_CMD_CONFIG_DATA_CNT(SPI_NOR_SR_LEN)
-+ | HISFC350_CMD_CONFIG_RW_READ
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START;
++ regval = HISFC350_CMD_CONFIG_DATA_CNT(SPI_NOR_SR_LEN)
++ | HISFC350_CMD_CONFIG_RW_READ
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START;
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG, regval);
-+ if (DEBUG_GET_SR) {
-+ printk(KERN_INFO " Set CONFIG[%#x]%#x\n", HISFC350_CMD_CONFIG,
-+ regval);
-+ }
++ hisfc_write(host, HISFC350_CMD_CONFIG, regval);
++ if (DEBUG_GET_SR) {
++ printk(KERN_INFO " Set CONFIG[%#x]%#x\n", HISFC350_CMD_CONFIG,
++ regval);
++ }
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ status = hisfc_read(host, HISFC350_CMD_DATABUF0);
-+ if (DEBUG_GET_SR) {
-+ printk(KERN_INFO "* Get flash Register %#x, val[%#x]\n", cmd,
-+ status);
-+ }
++ status = hisfc_read(host, HISFC350_CMD_DATABUF0);
++ if (DEBUG_GET_SR) {
++ printk(KERN_INFO "* Get flash Register %#x, val[%#x]\n", cmd,
++ status);
++ }
+
-+ return status;
++ return status;
+}
+
+/*****************************************************************************/
+static int spi_general_wait_ready(struct hisfc_spi *spi)
+{
-+ unsigned long status;
-+ unsigned long deadline = jiffies + HISFC350_MAX_READY_WAIT_JIFFIES;
++ unsigned long status;
++ unsigned long deadline = jiffies + HISFC350_MAX_READY_WAIT_JIFFIES;
+
-+ do {
-+ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
-+ if (!(status & SPI_CMD_SR_WIP)) {
-+ return 0;
-+ }
++ do {
++ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
++ if (!(status & SPI_CMD_SR_WIP)) {
++ return 0;
++ }
+
-+ cond_resched();
++ cond_resched();
+
-+ } while (!time_after_eq(jiffies, deadline));
++ } while (!time_after_eq(jiffies, deadline));
+
-+ printk(KERN_ERR "Wait spi flash ready timeout.\n");
++ printk(KERN_ERR "Wait spi flash ready timeout.\n");
+
-+ return 1;
++ return 1;
+}
+
+/*****************************************************************************/
+static int spi_general_write_enable(struct hisfc_spi *spi)
+{
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WREN);
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WREN);
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -306480,29 +374695,29 @@ index 0000000..f762528
+*/
+static int spi_general_entry_4addr(struct hisfc_spi *spi, int enable)
+{
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
-+ return 0;
-+ }
++ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
++ return 0;
++ }
+
-+ if (enable) {
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EN4B);
-+ } else {
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EX4B);
-+ }
++ if (enable) {
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EN4B);
++ } else {
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EX4B);
++ }
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ host->set_host_addr_mode(host, enable);
++ host->set_host_addr_mode(host, enable);
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -306511,34 +374726,34 @@ index 0000000..f762528
+*/
+static int spi_general_bus_prepare(struct hisfc_spi *spi, int op)
+{
-+ unsigned int regval = 0;
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ unsigned int regval = 0;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
+#ifdef HISFCV350_SUPPORT_BUS_WRITE
-+ regval |= HISFC350_BUS_CONFIG1_WRITE_EN;
++ regval |= HISFC350_BUS_CONFIG1_WRITE_EN;
+#endif
-+ regval |= HISFC350_BUS_CONFIG1_WRITE_INS(spi->write->cmd);
-+ regval |= HISFC350_BUS_CONFIG1_WRITE_DUMMY_CNT(spi->write->dummy);
-+ regval |= HISFC350_BUS_CONFIG1_WRITE_IF_TYPE(spi->write->iftype);
++ regval |= HISFC350_BUS_CONFIG1_WRITE_INS(spi->write->cmd);
++ regval |= HISFC350_BUS_CONFIG1_WRITE_DUMMY_CNT(spi->write->dummy);
++ regval |= HISFC350_BUS_CONFIG1_WRITE_IF_TYPE(spi->write->iftype);
+
+#ifdef HISFCV350_SUPPORT_BUS_READ
-+ regval |= HISFC350_BUS_CONFIG1_READ_EN;
++ regval |= HISFC350_BUS_CONFIG1_READ_EN;
+#endif
-+ regval |= HISFC350_BUS_CONFIG1_READ_PREF_CNT(0);
-+ regval |= HISFC350_BUS_CONFIG1_READ_INS(spi->read->cmd);
-+ regval |= HISFC350_BUS_CONFIG1_READ_DUMMY_CNT(spi->read->dummy);
-+ regval |= HISFC350_BUS_CONFIG1_READ_IF_TYPE(spi->read->iftype);
++ regval |= HISFC350_BUS_CONFIG1_READ_PREF_CNT(0);
++ regval |= HISFC350_BUS_CONFIG1_READ_INS(spi->read->cmd);
++ regval |= HISFC350_BUS_CONFIG1_READ_DUMMY_CNT(spi->read->dummy);
++ regval |= HISFC350_BUS_CONFIG1_READ_IF_TYPE(spi->read->iftype);
+
-+ hisfc_write(host, HISFC350_BUS_CONFIG1, regval);
-+ hisfc_write(host, HISFC350_BUS_CONFIG2,
-+ HISFC350_BUS_CONFIG2_WIP_LOCATE(0));
-+ if (op == READ) {
-+ host->set_system_clock(host, spi->read, TRUE);
-+ } else if (op == WRITE) {
-+ host->set_system_clock(host, spi->write, TRUE);
-+ }
++ hisfc_write(host, HISFC350_BUS_CONFIG1, regval);
++ hisfc_write(host, HISFC350_BUS_CONFIG2,
++ HISFC350_BUS_CONFIG2_WIP_LOCATE(0));
++ if (op == READ) {
++ host->set_system_clock(host, spi->read, TRUE);
++ } else if (op == WRITE) {
++ host->set_system_clock(host, spi->write, TRUE);
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -306547,17 +374762,17 @@ index 0000000..f762528
+*/
+static int hisfc350_is_quad(struct hisfc_spi *spi)
+{
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO "SPI read if[%d] write if[%d]\n",
-+ spi->read->iftype, spi->write->iftype);
-+ }
-+ if (spi->write->iftype == 5 || spi->write->iftype == 6
-+ || spi->write->iftype == 7 || spi->read->iftype == 5
-+ || spi->read->iftype == 6 || spi->read->iftype == 7) {
-+ return 1;
-+ }
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO "SPI read if[%d] write if[%d]\n",
++ spi->read->iftype, spi->write->iftype);
++ }
++ if (spi->write->iftype == 5 || spi->write->iftype == 6
++ || spi->write->iftype == 7 || spi->read->iftype == 5
++ || spi->read->iftype == 6 || spi->read->iftype == 7) {
++ return 1;
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*****************************************************************************/
@@ -306566,80 +374781,80 @@ index 0000000..f762528
+*/
+static int spi_general_qe_enable(struct hisfc_spi *spi)
+{
-+ unsigned char status, config, op;
-+ unsigned int reg;
-+ const char *str[] = {"Disable", "Enable"};
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ unsigned char status, config, op;
++ unsigned int reg;
++ const char *str[] = {"Disable", "Enable"};
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ op = hisfc350_is_quad(spi);
++ op = hisfc350_is_quad(spi);
+
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO "* Start SPI Nor %s Quad.\n", str[op]);
-+ }
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO "* Start SPI Nor %s Quad.\n", str[op]);
++ }
+
-+ config = spi_general_get_flash_register(spi, SPI_CMD_RDCR);
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO " Read config %#x, val[%#x]\n", SPI_CMD_RDCR,
-+ config);
-+ }
-+ if (((config & SPI_NOR_CR_QE_MASK) >> SPI_NOR_CR_QE_SHIFT) == op) {
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO "* Quad was %sd!\n", str[op]);
-+ }
-+ return op;
-+ }
++ config = spi_general_get_flash_register(spi, SPI_CMD_RDCR);
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO " Read config %#x, val[%#x]\n", SPI_CMD_RDCR,
++ config);
++ }
++ if (((config & SPI_NOR_CR_QE_MASK) >> SPI_NOR_CR_QE_SHIFT) == op) {
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO "* Quad was %sd!\n", str[op]);
++ }
++ return op;
++ }
+
-+ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
-+ reg = (config << SPI_NOR_CR_SHIFT) | status;
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO " Read CR/SR[%#x]\n", reg);
-+ }
++ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
++ reg = (config << SPI_NOR_CR_SHIFT) | status;
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO " Read CR/SR[%#x]\n", reg);
++ }
+
-+ spi->driver->write_enable(spi);
++ spi->driver->write_enable(spi);
+
-+ if (op) {
-+ reg |= (SPI_NOR_CR_QE_MASK << SPI_NOR_CR_SHIFT);
-+ } else {
-+ reg &= ~(SPI_NOR_CR_QE_MASK << SPI_NOR_CR_SHIFT);
-+ }
-+ hisfc_write(host, HISFC350_CMD_DATABUF0, reg);
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO " Set DATA[%#x]%#x\n", HISFC350_CMD_DATABUF0,
-+ reg);
-+ }
++ if (op) {
++ reg |= (SPI_NOR_CR_QE_MASK << SPI_NOR_CR_SHIFT);
++ } else {
++ reg &= ~(SPI_NOR_CR_QE_MASK << SPI_NOR_CR_SHIFT);
++ }
++ hisfc_write(host, HISFC350_CMD_DATABUF0, reg);
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO " Set DATA[%#x]%#x\n", HISFC350_CMD_DATABUF0,
++ reg);
++ }
+
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR);
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO " Set INS[%#x]%#x\n", HISFC350_CMD_INS,
-+ SPI_CMD_WRSR);
-+ }
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR);
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO " Set INS[%#x]%#x\n", HISFC350_CMD_INS,
++ SPI_CMD_WRSR);
++ }
+
-+ reg = HISFC350_CMD_CONFIG_DATA_CNT(SPI_NOR_SR_LEN + SPI_NOR_CR_LEN)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START;
-+ hisfc_write(host, HISFC350_CMD_CONFIG, reg);
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO " Set CONFIG[%#x]%#x\n", HISFC350_CMD_CONFIG,
-+ reg);
-+ }
++ reg = HISFC350_CMD_CONFIG_DATA_CNT(SPI_NOR_SR_LEN + SPI_NOR_CR_LEN)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START;
++ hisfc_write(host, HISFC350_CMD_CONFIG, reg);
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO " Set CONFIG[%#x]%#x\n", HISFC350_CMD_CONFIG,
++ reg);
++ }
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ if (DEBUG_SPI_QE) {
-+ spi->driver->wait_ready(spi);
++ if (DEBUG_SPI_QE) {
++ spi->driver->wait_ready(spi);
+
-+ config = spi_general_get_flash_register(spi, SPI_CMD_RDCR);
-+ if (((config & SPI_NOR_CR_QE_MASK) >> SPI_NOR_CR_QE_SHIFT)
-+ == op) {
-+ printk(KERN_INFO "* SPI Quad %s succeed. [%#x]\n",
-+ str[op], config);
-+ } else {
-+ DBG_MSG("%s Quad failed! [%#x]\n", str[op], config);
-+ }
-+ }
++ config = spi_general_get_flash_register(spi, SPI_CMD_RDCR);
++ if (((config & SPI_NOR_CR_QE_MASK) >> SPI_NOR_CR_QE_SHIFT)
++ == op) {
++ printk(KERN_INFO "* SPI Quad %s succeed. [%#x]\n",
++ str[op], config);
++ } else {
++ DBG_MSG("%s Quad failed! [%#x]\n", str[op], config);
++ }
++ }
+
-+ return op;
++ return op;
+}
+
+/*****************************************************************************/
@@ -306648,11 +374863,11 @@ index 0000000..f762528
+*/
+static int spi_do_not_qe_enable(struct hisfc_spi *spi)
+{
-+ return 0;
++ return 0;
+}
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_ids.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_ids.c
new file mode 100644
-index 0000000..f7ceb67
+index 0000000..37b44cc
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_ids.c
@@ -0,0 +1,2210 @@
@@ -306908,1967 +375123,1967 @@ index 0000000..f7ceb67
+/*****************************************************************************/
+#include "hisfc350_spi_general.c"
+static struct spi_driver spi_driver_general = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_general_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_general_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_general_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_general_qe_enable,
+};
+
+static struct spi_driver spi_driver_no_qe = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_general_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_do_not_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_general_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_do_not_qe_enable,
+};
+
+#include "hisfc350_spi_s25fl256s.c"
+static struct spi_driver spi_driver_s25fl256s = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_s25fl256s_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_general_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_s25fl256s_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_general_qe_enable,
+};
+
+#include "hisfc350_spi_w25q256fv.c"
+static struct spi_driver spi_driver_w25q256fv = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_w25q256fv_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_general_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_w25q256fv_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_general_qe_enable,
+};
+
+#include "hisfc350_spi_mx25l25635e.c"
+static struct spi_driver spi_driver_mx25l25635e = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_general_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_mx25l25635e_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_general_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_mx25l25635e_qe_enable,
+};
+
+static struct spi_driver spi_driver_f25l64q = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_general_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_mx25l25635e_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_general_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_mx25l25635e_qe_enable,
+};
+
+#include "hisfc350_spi_gd25qxxx.c"
+static struct spi_driver spi_driver_gd25qxxx = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_general_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_gd25qxxx_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_general_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_gd25qxxx_qe_enable,
+};
+
+#include "hisfc350_spi_micron.c"
+static struct spi_driver spi_driver_micron = {
-+ .wait_ready = spi_general_wait_ready,
-+ .write_enable = spi_general_write_enable,
-+ .entry_4addr = spi_micron_entry_4addr,
-+ .bus_prepare = spi_general_bus_prepare,
-+ .qe_enable = spi_do_not_qe_enable,
++ .wait_ready = spi_general_wait_ready,
++ .write_enable = spi_general_write_enable,
++ .entry_4addr = spi_micron_entry_4addr,
++ .bus_prepare = spi_general_bus_prepare,
++ .qe_enable = spi_do_not_qe_enable,
+};
+
+/*****************************************************************************/
+struct spi_info spi_info_table[] = {
-+ /* name id id_len chipsize(Bytes) erasesize */
-+ {
-+ "at25fs010", {0x1f, 0x66, 0x01}, 3, _128K, _32K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_32K(0, _32K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ /* name id id_len chipsize(Bytes) erasesize */
++ {
++ "at25fs010", {0x1f, 0x66, 0x01}, 3, _128K, _32K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_32K(0, _32K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "at25fs040", {0x1f, 0x66, 0x04}, 3, _512K, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "at25fs040", {0x1f, 0x66, 0x04}, 3, _512K, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "at25df041a", {0x1f, 0x44, 0x01}, 3, _512K, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "at25df041a", {0x1f, 0x44, 0x01}, 3, _512K, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "at25df641", {0x1f, 0x48, 0x00}, 3, _8M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "at25df641", {0x1f, 0x48, 0x00}, 3, _8M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "at26f004", {0x1f, 0x04, 0x00}, 3, _512K, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "at26f004", {0x1f, 0x04, 0x00}, 3, _512K, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "at26df081a", {0x1f, 0x45, 0x01}, 3, _1M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "at26df081a", {0x1f, 0x45, 0x01}, 3, _1M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "at26df161a", {0x1f, 0x46, 0x01}, 3, _2M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "at26df161a", {0x1f, 0x46, 0x01}, 3, _2M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "at26df321", {0x1f, 0x47, 0x01}, 3, _4M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "at26df321", {0x1f, 0x47, 0x01}, 3, _4M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ /* Macronix/MXIC */
-+ {
-+ "mx25l4005a", {0xc2, 0x20, 0x13}, 3, _512K, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ /* Macronix/MXIC */
++ {
++ "mx25l4005a", {0xc2, 0x20, 0x13}, 3, _512K, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "MX25L8006E", {0xc2, 0x20, 0x14}, 3, _1M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 86),
-+ &READ_DUAL(1, INFINITE, 80),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 86),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 86),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "MX25L8006E", {0xc2, 0x20, 0x14}, 3, _1M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 86),
++ &READ_DUAL(1, INFINITE, 80),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 86),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 86),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "MX25L1606E", {0xc2, 0x20, 0x15}, 3, _2M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 86),
-+ &READ_DUAL(1, INFINITE, 80),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 86),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 86),
-+ 0
-+ },
-+ &spi_driver_no_qe,
-+ },
++ {
++ "MX25L1606E", {0xc2, 0x20, 0x15}, 3, _2M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 86),
++ &READ_DUAL(1, INFINITE, 80),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 86),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 86),
++ 0
++ },
++ &spi_driver_no_qe,
++ },
+
-+ {
-+ "mx25l3205d", {0xc2, 0x20, 0x16}, 3, _4M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "mx25l3205d", {0xc2, 0x20, 0x16}, 3, _4M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ /* MX25L6406E and MX25L6436F have the same ID, but different I/O wire */
-+ {
-+ "MX25L6406E", {0xc2, 0x20, 0x17}, 3, _8M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 86),
-+ &READ_DUAL(1, INFINITE, 80),
-+ /*
-+ #ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 133),
-+ &READ_QUAD_ADDR(3, INFINITE, 133),
-+ #endif
-+ */
-+ 0
-+ },
++ /* MX25L6406E and MX25L6436F have the same ID, but different I/O wire */
++ {
++ "MX25L6406E", {0xc2, 0x20, 0x17}, 3, _8M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 86),
++ &READ_DUAL(1, INFINITE, 80),
++ /*
++ #ifndef CONFIG_CLOSE_SPI_8PIN_4IO
++ &READ_QUAD(1, INFINITE, 133),
++ &READ_QUAD_ADDR(3, INFINITE, 133),
++ #endif
++ */
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 86),
-+ /*
-+ #ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD_ADDR(0, 256, 133),
-+ #endif
-+ */
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 86),
++ /*
++ #ifndef CONFIG_CLOSE_SPI_8PIN_4IO
++ &WRITE_QUAD_ADDR(0, 256, 133),
++ #endif
++ */
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 86),
-+ 0
-+ },
-+ &spi_driver_mx25l25635e,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 86),
++ 0
++ },
++ &spi_driver_mx25l25635e,
++ },
+
-+ /* MX25R6435F Wide Voltage Range 1.65~3.6V */
-+ {
-+ "MX25R6435F", {0xc2, 0x28, 0x17}, 3, _8M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
++ /* MX25R6435F Wide Voltage Range 1.65~3.6V */
++ {
++ "MX25R6435F", {0xc2, 0x28, 0x17}, 3, _8M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(3, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(3, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 33),
++ {
++ &WRITE_STD(0, 256, 33),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD_ADDR(0, 256, 33),
++ &WRITE_QUAD_ADDR(0, 256, 33),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 33),
-+ 0
-+ },
-+ &spi_driver_mx25l25635e,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 33),
++ 0
++ },
++ &spi_driver_mx25l25635e,
++ },
+
-+ {
-+ "MX25L128XX", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 104),
++ {
++ "MX25L128XX", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 104),
-+ &READ_QUAD_ADDR(3, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ &READ_QUAD_ADDR(3, INFINITE, 104),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD_ADDR(0, 256, 104),
++ &WRITE_QUAD_ADDR(0, 256, 104),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_mx25l25635e,
-+ },
-+ /*
-+ The follow chips have the same chipid, but command have some difference
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_mx25l25635e,
++ },
++ /*
++ The follow chips have the same chipid, but command have some difference
+
-+ {"MX25L12836E", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
-+ {&READ_STD(0, INFINITE, 50), &READ_FAST(1, INFINITE, 108), 0},
-+ {&WRITE_STD(0, 256, 108), 0},
-+ {&ERASE_SECTOR_64K(0, _64K, 108), 0}},
++ {"MX25L12836E", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
++ {&READ_STD(0, INFINITE, 50), &READ_FAST(1, INFINITE, 108), 0},
++ {&WRITE_STD(0, 256, 108), 0},
++ {&ERASE_SECTOR_64K(0, _64K, 108), 0}},
+
-+ {"MX25L12845E", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
-+ {&READ_STD(0, INFINITE, 50), &READ_FAST(1, INFINITE, 108), 0},
-+ {&WRITE_STD(0, 256, 108), 0},
-+ {&ERASE_SECTOR_64K(0, _64K, 108), 0}},
++ {"MX25L12845E", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
++ {&READ_STD(0, INFINITE, 50), &READ_FAST(1, INFINITE, 108), 0},
++ {&WRITE_STD(0, 256, 108), 0},
++ {&ERASE_SECTOR_64K(0, _64K, 108), 0}},
+
-+ {"MX25L12835F", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
-+ {&READ_STD(0, INFINITE, 50), &READ_FAST(1, INFINITE, 108), 0},
-+ {&WRITE_STD(0, 256, 108), 0},
-+ {&ERASE_SECTOR_64K(0, _64K, 108), 0}},
-+ */
++ {"MX25L12835F", {0xc2, 0x20, 0x18}, 3, _16M, _64K, 3,
++ {&READ_STD(0, INFINITE, 50), &READ_FAST(1, INFINITE, 108), 0},
++ {&WRITE_STD(0, 256, 108), 0},
++ {&ERASE_SECTOR_64K(0, _64K, 108), 0}},
++ */
+
-+ {
-+ "MX25L(256/257)XX",
-+ {0xc2, 0x20, 0x19}, 3, _32M, _64K, 4,
-+ {
-+ &READ_STD(0, INFINITE, 40/*50*/),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(2, INFINITE, 104),
-+ &READ_DUAL_ADDR(1, INFINITE, 84),
++ {
++ "MX25L(256/257)XX",
++ {0xc2, 0x20, 0x19}, 3, _32M, _64K, 4,
++ {
++ &READ_STD(0, INFINITE, 40/*50*/),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(2, INFINITE, 104),
++ &READ_DUAL_ADDR(1, INFINITE, 84),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD_ADDR(3, INFINITE, 75),
++ &READ_QUAD_ADDR(3, INFINITE, 75),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 75),
++ {
++ &WRITE_STD(0, 256, 75),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD_ADDR(0, 256, 104),
++ &WRITE_QUAD_ADDR(0, 256, 104),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80),
-+ 0
-+ },
-+ &spi_driver_mx25l25635e,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80),
++ 0
++ },
++ &spi_driver_mx25l25635e,
++ },
+
-+ {
-+ "mx25l1655d", {0xc2, 0x26, 0x15}, 3, _2M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "mx25l1655d", {0xc2, 0x26, 0x15}, 3, _2M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "mx25l12855e", {0xc2, 0x26, 0x18}, 3, _16M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "mx25l12855e", {0xc2, 0x26, 0x18}, 3, _16M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "s25sl004a", {0x01, 0x02, 0x12}, 3, (_64K * 8), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "s25sl004a", {0x01, 0x02, 0x12}, 3, (_64K * 8), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "s25sl008a", {0x01, 0x02, 0x13}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "s25sl008a", {0x01, 0x02, 0x13}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "s25sl016a", {0x01, 0x02, 0x14}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "s25sl016a", {0x01, 0x02, 0x14}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "S25FL064P", {0x01, 0x02, 0x16, 0x4d}, 4, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 40),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 80),
++ {
++ "S25FL064P", {0x01, 0x02, 0x16, 0x4d}, 4, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 40),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "s25sl064a", {0x01, 0x02, 0x16}, 3, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "s25sl064a", {0x01, 0x02, 0x16}, 3, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ /* Spansion */
++ /* Spansion */
+
-+ {
-+ "S25FL032P", {0x01, 0x02, 0x15, 0x4d}, 4, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 40),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(0, INFINITE, 80),
++ {
++ "S25FL032P", {0x01, 0x02, 0x15, 0x4d}, 4, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 40),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(0, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(2, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(2, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "S25FL032A", {0x01, 0x02, 0x15}, 3, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 50),
-+ 0
-+ },
++ {
++ "S25FL032A", {0x01, 0x02, 0x15}, 3, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 50),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 50),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 50),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 50),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 50),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "S25FL128P-0",
-+ {0x01, 0x20, 0x18, 0x03, 0x00}, 5, (_256K * 64), _256K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 40),
-+ &READ_FAST(1, INFINITE, 104),
-+ 0
-+ },
++ {
++ "S25FL128P-0",
++ {0x01, 0x20, 0x18, 0x03, 0x00}, 5, (_256K * 64), _256K, 3,
++ {
++ &READ_STD(0, INFINITE, 40),
++ &READ_FAST(1, INFINITE, 104),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_256K(0, _256K, 104),
-+ 0
-+ },
-+ &spi_driver_no_qe,
-+ },
++ {
++ &ERASE_SECTOR_256K(0, _256K, 104),
++ 0
++ },
++ &spi_driver_no_qe,
++ },
+
-+ {
-+ "S25FL128P-1",
-+ {0x01, 0x20, 0x18, 0x03, 0x01}, 5, (_64K * 256), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 40),
-+ &READ_FAST(1, INFINITE, 104),
-+ 0
-+ },
++ {
++ "S25FL128P-1",
++ {0x01, 0x20, 0x18, 0x03, 0x01}, 5, (_64K * 256), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 40),
++ &READ_FAST(1, INFINITE, 104),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104), 0
-+ },
++ {
++ &WRITE_STD(0, 256, 104), 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_no_qe,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_no_qe,
++ },
+
-+ {
-+ "S25FL129P0",
-+ {0x01, 0x20, 0x18, 0x4d, 0x00}, 5, (_256K * 64), _256K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 40),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(0, INFINITE, 80),
++ {
++ "S25FL129P0",
++ {0x01, 0x20, 0x18, 0x4d, 0x00}, 5, (_256K * 64), _256K, 3,
++ {
++ &READ_STD(0, INFINITE, 40),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(0, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(2, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(2, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_256K(0, _256K, 104),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_256K(0, _256K, 104),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "S25FL129P1/127S",
-+ {0x01, 0x20, 0x18, 0x4d, 0x01}, 5, (_64K * 256), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 40),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 64),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
++ {
++ "S25FL129P1/127S",
++ {0x01, 0x20, 0x18, 0x4d, 0x01}, 5, (_64K * 256), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 40),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 64),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(3, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(3, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "S25FL256S", {0x01, 0x02, 0x19, 0x4d, 0x01}, 5, _32M, _64K, 4,
-+ {
-+ &READ_STD(0, INFINITE, 40),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 64),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
++ {
++ "S25FL256S", {0x01, 0x02, 0x19, 0x4d, 0x01}, 5, _32M, _64K, 4,
++ {
++ &READ_STD(0, INFINITE, 40),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 64),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(3, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(3, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_s25fl256s,
-+ },
-+
-+ /*
-+ The chip and chip W25Q16B have the same chipid,
-+ but clock frequency have some difference
-+
-+ {"S25FL016K", {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
-+ &READ_QUAD(1, INFINITE, 104),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ }
-+ },
-+ */
-+
-+ /* SST -- large erase sizes are "overlays", "sectors" are 4K */
-+ {
-+ "sst25vf040b", {0xbf, 0x25, 0x8d}, 3, (_64K * 8), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "sst25vf080b", {0xbf, 0x25, 0x8e}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "sst25vf016b", {0xbf, 0x25, 0x41}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "sst25vf032b", {0xbf, 0x25, 0x4a}, 3, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "sst25wf512", {0xbf, 0x25, 0x01}, 3, (_64K * 1), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "sst25wf010", {0xbf, 0x25, 0x02}, 3, (_64K * 2), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "sst25wf020", {0xbf, 0x25, 0x03}, 3, (_64K * 4), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "sst25wf040", {0xbf, 0x25, 0x04}, 3, (_64K * 8), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ /* ST Microelectronics -- newer production may have feature updates */
-+ {
-+ "m25p05", {0x20, 0x20, 0x10}, 3, (_32K * 2), _32K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_32K(0, _32K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25p10", {0x20, 0x20, 0x11}, 3, (_32K * 4), _32K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_32K(0, _32K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25p20", {0x20, 0x20, 0x12}, 3, (_64K * 4), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25p40", {0x20, 0x20, 0x13}, 3, (_64K * 8), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25p80", {0x20, 0x20, 0x14}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25p16", {0x20, 0x20, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "M25P32", {0x20, 0x20, 0x16, 0x10}, 4, _4M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 75),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 75),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 75),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25p64", {0x20, 0x20, 0x17}, 3, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "M25P128", {0x20, 0x20, 0x18}, 3, _16M, _256K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 20),
-+ &READ_FAST(1, INFINITE, 50),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 50),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_256K(0, _256K, 50),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m45pe10", {0x20, 0x40, 0x11}, 3, (_64K * 2), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m45pe80", {0x20, 0x40, 0x14}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m45pe16", {0x20, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25pe80", {0x20, 0x80, 0x14}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "m25pe16", {0x20, 0x80, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+
-+ {
-+ "N25Q032", {0x20, 0xba, 0x16}, 3, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 32/*54*/),
-+ &READ_FAST(1, INFINITE, 64/*108*/),
-+ &READ_DUAL(1, INFINITE, 64/*108*/),
-+ &READ_DUAL_ADDR(2, INFINITE, 64/*108*/),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_s25fl256s,
++ },
++
++ /*
++ The chip and chip W25Q16B have the same chipid,
++ but clock frequency have some difference
++
++ {"S25FL016K", {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
++ &READ_QUAD(1, INFINITE, 104),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ }
++ },
++ */
++
++ /* SST -- large erase sizes are "overlays", "sectors" are 4K */
++ {
++ "sst25vf040b", {0xbf, 0x25, 0x8d}, 3, (_64K * 8), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "sst25vf080b", {0xbf, 0x25, 0x8e}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "sst25vf016b", {0xbf, 0x25, 0x41}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "sst25vf032b", {0xbf, 0x25, 0x4a}, 3, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "sst25wf512", {0xbf, 0x25, 0x01}, 3, (_64K * 1), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "sst25wf010", {0xbf, 0x25, 0x02}, 3, (_64K * 2), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "sst25wf020", {0xbf, 0x25, 0x03}, 3, (_64K * 4), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "sst25wf040", {0xbf, 0x25, 0x04}, 3, (_64K * 8), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ /* ST Microelectronics -- newer production may have feature updates */
++ {
++ "m25p05", {0x20, 0x20, 0x10}, 3, (_32K * 2), _32K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_32K(0, _32K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25p10", {0x20, 0x20, 0x11}, 3, (_32K * 4), _32K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_32K(0, _32K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25p20", {0x20, 0x20, 0x12}, 3, (_64K * 4), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25p40", {0x20, 0x20, 0x13}, 3, (_64K * 8), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25p80", {0x20, 0x20, 0x14}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25p16", {0x20, 0x20, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "M25P32", {0x20, 0x20, 0x16, 0x10}, 4, _4M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 75),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 75),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 75),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25p64", {0x20, 0x20, 0x17}, 3, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "M25P128", {0x20, 0x20, 0x18}, 3, _16M, _256K, 3,
++ {
++ &READ_STD(0, INFINITE, 20),
++ &READ_FAST(1, INFINITE, 50),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 50),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_256K(0, _256K, 50),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m45pe10", {0x20, 0x40, 0x11}, 3, (_64K * 2), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m45pe80", {0x20, 0x40, 0x14}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m45pe16", {0x20, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25pe80", {0x20, 0x80, 0x14}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "m25pe16", {0x20, 0x80, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
++
++ {
++ "N25Q032", {0x20, 0xba, 0x16}, 3, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 32/*54*/),
++ &READ_FAST(1, INFINITE, 64/*108*/),
++ &READ_DUAL(1, INFINITE, 64/*108*/),
++ &READ_DUAL_ADDR(2, INFINITE, 64/*108*/),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 64/*108*/),
-+ &READ_QUAD_ADDR(5, INFINITE, 64/*108*/),
++ &READ_QUAD(1, INFINITE, 64/*108*/),
++ &READ_QUAD_ADDR(5, INFINITE, 64/*108*/),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 64/*108*/),
-+ &WRITE_DUAL(0, 256, 64/*108*/),
-+ &WRITE_DUAL_ADDR(0, 256, 64/*108*/),
++ {
++ &WRITE_STD(0, 256, 64/*108*/),
++ &WRITE_DUAL(0, 256, 64/*108*/),
++ &WRITE_DUAL_ADDR(0, 256, 64/*108*/),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 64/*108*/),
-+ /* &WRITE_QUAD_ADDR(0, 256, 64), */
++ &WRITE_QUAD(0, 256, 64/*108*/),
++ /* &WRITE_QUAD_ADDR(0, 256, 64), */
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 64/*108*/),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 64/*108*/),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ /* Micron N25QL064A 3.3V */
-+ {
-+ "N25QL064A", {0x20, 0xba, 0x17}, 3, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 54),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(2, INFINITE, 84),
++ /* Micron N25QL064A 3.3V */
++ {
++ "N25QL064A", {0x20, 0xba, 0x17}, 3, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 54),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(2, INFINITE, 84),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
-+ &READ_QUAD_ADDR(5, INFINITE, 84),
++ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD_ADDR(5, INFINITE, 84),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_DUAL(0, 256, 75),
-+ &WRITE_DUAL_ADDR(0, 256, 75),
++ {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_DUAL(0, 256, 75),
++ &WRITE_DUAL_ADDR(0, 256, 75),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 50),
-+ 0
-+ },
-+ &spi_driver_micron,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 50),
++ 0
++ },
++ &spi_driver_micron,
++ },
+
-+ /* Micron MT(N)25QL128A 3.3V */
-+ {
-+ "N25QL128A", {0x20, 0xba, 0x18}, 3, (_64K * 256), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 54),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 84),
-+ &READ_DUAL_ADDR(2, INFINITE, 84),
++ /* Micron MT(N)25QL128A 3.3V */
++ {
++ "N25QL128A", {0x20, 0xba, 0x18}, 3, (_64K * 256), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 54),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 84),
++ &READ_DUAL_ADDR(2, INFINITE, 84),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 84),
-+ &READ_QUAD_ADDR(5, INFINITE, 84),
++ &READ_QUAD(1, INFINITE, 84),
++ &READ_QUAD_ADDR(5, INFINITE, 84),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 108),
-+ &WRITE_DUAL(0, 256, 108),
-+ &WRITE_DUAL_ADDR(0, 256, 108),
++ {
++ &WRITE_STD(0, 256, 108),
++ &WRITE_DUAL(0, 256, 108),
++ &WRITE_DUAL_ADDR(0, 256, 108),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 108),
++ &WRITE_QUAD(0, 256, 108),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 108),
-+ 0
-+ },
-+ &spi_driver_micron,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 108),
++ 0
++ },
++ &spi_driver_micron,
++ },
+
-+ /* Micron MT25QL256A 3.3V */
-+ {
-+ "MT25QL256A", {0x20, 0xba, 0x19}, 3, (_64K * 512), _64K, 4,
-+ {
-+ &READ_STD(0, INFINITE, 54),
-+ &READ_FAST(1, INFINITE, 133),
-+ &READ_DUAL(1, INFINITE, 133),
-+ &READ_DUAL_ADDR(2, INFINITE, 133),
++ /* Micron MT25QL256A 3.3V */
++ {
++ "MT25QL256A", {0x20, 0xba, 0x19}, 3, (_64K * 512), _64K, 4,
++ {
++ &READ_STD(0, INFINITE, 54),
++ &READ_FAST(1, INFINITE, 133),
++ &READ_DUAL(1, INFINITE, 133),
++ &READ_DUAL_ADDR(2, INFINITE, 133),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 133),
-+ &READ_QUAD_ADDR(5, INFINITE, 125),
++ &READ_QUAD(1, INFINITE, 133),
++ &READ_QUAD_ADDR(5, INFINITE, 125),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 133),
-+ &WRITE_DUAL(0, 256, 133),
-+ &WRITE_DUAL_ADDR(0, 256, 133),
++ {
++ &WRITE_STD(0, 256, 133),
++ &WRITE_DUAL(0, 256, 133),
++ &WRITE_DUAL_ADDR(0, 256, 133),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 133),
-+ /* &WRITE_QUAD_ADDR(0, 256, 133), */
++ &WRITE_QUAD(0, 256, 133),
++ /* &WRITE_QUAD_ADDR(0, 256, 133), */
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 133),
-+ 0
-+ },
-+ &spi_driver_micron,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 133),
++ 0
++ },
++ &spi_driver_micron,
++ },
+
-+ {
-+ "M25PX16", {0x20, 0x71, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 75),
-+ &READ_DUAL(1, INFINITE, 75),
-+ 0
-+ },
++ {
++ "M25PX16", {0x20, 0x71, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 75),
++ &READ_DUAL(1, INFINITE, 75),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 75),
-+ &WRITE_DUAL(0, 256, 75),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 75),
++ &WRITE_DUAL(0, 256, 75),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 75),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 75),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "M25PX32", {0x20, 0x71, 0x16}, 3, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 75),
-+ &READ_DUAL(1, INFINITE, 75),
-+ 0
-+ },
++ {
++ "M25PX32", {0x20, 0x71, 0x16}, 3, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 75),
++ &READ_DUAL(1, INFINITE, 75),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 75),
-+ &WRITE_DUAL(0, 256, 75),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 75),
++ &WRITE_DUAL(0, 256, 75),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 75),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 75),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "m25px64", {0x20, 0x71, 0x17}, 3, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "m25px64", {0x20, 0x71, 0x17}, 3, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
-+ {
-+ "w25x10", {0xef, 0x30, 0x11}, 3, (_64K * 2), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
++ {
++ "w25x10", {0xef, 0x30, 0x11}, 3, (_64K * 2), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "w25x20", {0xef, 0x30, 0x12}, 3, (_64K * 4), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "w25x20", {0xef, 0x30, 0x12}, 3, (_64K * 4), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "w25x40", {0xef, 0x30, 0x13}, 3, (_64K * 8), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "w25x40", {0xef, 0x30, 0x13}, 3, (_64K * 8), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "w25x80", {0xef, 0x30, 0x14}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "w25x80", {0xef, 0x30, 0x14}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "w25x16", {0xef, 0x30, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
++ {
++ "w25x16", {0xef, 0x30, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "w25x32", {0xef, 0x30, 0x16}, 3, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0), 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "w25x32", {0xef, 0x30, 0x16}, 3, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0), 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "w25x64", {0xef, 0x30, 0x17}, 3, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 0),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 0),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 0),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ "w25x64", {0xef, 0x30, 0x17}, 3, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 0),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 0),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 0),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "W25Q80BV", {0xef, 0x40, 0x14}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
++ {
++ "W25Q80BV", {0xef, 0x40, 0x14}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 80),
++ {
++ &WRITE_STD(0, 256, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "W25Q16(B/C)V/S25FL016K",
-+ {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
++ {
++ "W25Q16(B/C)V/S25FL016K",
++ {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 80),
++ {
++ &WRITE_STD(0, 256, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
-+ /*
-+ The follow chips have the same chipid, but command have some difference
-+ {
-+ "W25Q16BV", {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80),
-+ 0
-+ }
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80),
++ 0
++ },
++ &spi_driver_general,
++ },
++ /*
++ The follow chips have the same chipid, but command have some difference
++ {
++ "W25Q16BV", {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80),
++ 0
++ }
++ },
+
-+ {
-+ "W25Q16CV", {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_QUAD(1, INFINITE, 80),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 80),
-+ &WRITE_QUAD(0, 256, 80),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80),
-+ 0
-+ }
-+ },
++ {
++ "W25Q16CV", {0xef, 0x40, 0x15}, 3, (_64K * 32), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80),
++ 0
++ }
++ },
+
-+ */
-+ {
-+ "W25Q32BV", {0xef, 0x40, 0x16}, 3, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
++ */
++ {
++ "W25Q32BV", {0xef, 0x40, 0x16}, 3, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 80),
++ {
++ &WRITE_STD(0, 256, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "W25Q64FV", {0xef, 0x40, 0x17}, 3, _8M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
++ {
++ "W25Q64FV", {0xef, 0x40, 0x17}, 3, _8M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 80),
++ {
++ &WRITE_STD(0, 256, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "W25Q128(B/F)V", {0xEF, 0x40, 0x18}, 3, _16M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 33),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 104),
++ {
++ "W25Q128(B/F)V", {0xEF, 0x40, 0x18}, 3, _16M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 33),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, /*70*/80),
++ &READ_QUAD(1, INFINITE, /*70*/80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, /*70*/80),
++ &WRITE_QUAD(0, 256, /*70*/80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_w25q256fv,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_w25q256fv,
++ },
+
-+ {
-+ "W25Q256FV", {0xEF, 0x40, 0x19}, 3, _32M, _64K, 4,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80),
-+ &READ_DUAL(1, INFINITE, 80),
++ {
++ "W25Q256FV", {0xEF, 0x40, 0x19}, 3, _32M, _64K, 4,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80),
++ &READ_DUAL(1, INFINITE, 80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
++ {
++ &WRITE_STD(0, 256, 104),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_w25q256fv,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_w25q256fv,
++ },
+
-+ /* Eon -- fit clock frequency of RDSR instruction*/
-+ {
-+ "EN25F80", {0x1c, 0x31, 0x14}, 3, (_64K * 16), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 66),
-+ &READ_FAST(1, INFINITE, 66/*100*/),
-+ 0
-+ },
++ /* Eon -- fit clock frequency of RDSR instruction*/
++ {
++ "EN25F80", {0x1c, 0x31, 0x14}, 3, (_64K * 16), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 66),
++ &READ_FAST(1, INFINITE, 66/*100*/),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 66/*100*/),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 66/*100*/),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 66/*100*/),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 66/*100*/),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "EN25F16", {0x1c, 0x31, 0x15}, 3, _2M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 66),
-+ &READ_FAST(1, INFINITE, 66/*100*/),
-+ 0
-+ },
++ {
++ "EN25F16", {0x1c, 0x31, 0x15}, 3, _2M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 66),
++ &READ_FAST(1, INFINITE, 66/*100*/),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 66/*100*/),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 66/*100*/),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 66/*100*/),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 66/*100*/),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "EN25Q32B", {0x1c, 0x30, 0x16}, 3, (_64K * 64), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 80/*104*/),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ /*&READ_QUAD(3, INFINITE, 80), */
-+ 0
-+ },
++ {
++ "EN25Q32B", {0x1c, 0x30, 0x16}, 3, (_64K * 64), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 80/*104*/),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ /*&READ_QUAD(3, INFINITE, 80), */
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 80/*104*/),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 80/*104*/),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 80/*104*/),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 80/*104*/),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "EN25Q64", {0x1c, 0x30, 0x17}, 3, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 100),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ 0
-+ },
++ {
++ "EN25Q64", {0x1c, 0x30, 0x17}, 3, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 100),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 80),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 80),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_no_qe,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_no_qe,
++ },
+
-+ {
-+ "EN25Q128", {0x1c, 0x30, 0x18}, 3, (_64K * 256), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 50),
-+ &READ_FAST(1, INFINITE, 104),
-+ &READ_DUAL(1, INFINITE, 80),
-+ &READ_DUAL_ADDR(1, INFINITE, 80),
-+ 0
-+ },
++ {
++ "EN25Q128", {0x1c, 0x30, 0x18}, 3, (_64K * 256), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 50),
++ &READ_FAST(1, INFINITE, 104),
++ &READ_DUAL(1, INFINITE, 80),
++ &READ_DUAL_ADDR(1, INFINITE, 80),
++ 0
++ },
+
-+ {
-+ &WRITE_STD(0, 256, 104),
-+ 0
-+ },
++ {
++ &WRITE_STD(0, 256, 104),
++ 0
++ },
+
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 104),
-+ 0
-+ },
-+ &spi_driver_no_qe,
-+ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 104),
++ 0
++ },
++ &spi_driver_no_qe,
++ },
+
-+ /* ESMT */
-+ {
-+ "F25L64QA", {0x8C, 0x41, 0x17}, 3, (_64K * 128), _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 66),
-+ &READ_FAST(1, INFINITE, /*66*/100),
-+ &READ_DUAL(1, INFINITE, /*66*/80),
++ /* ESMT */
++ {
++ "F25L64QA", {0x8C, 0x41, 0x17}, 3, (_64K * 128), _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 66),
++ &READ_FAST(1, INFINITE, /*66*/100),
++ &READ_DUAL(1, INFINITE, /*66*/80),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, /*66*/100),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, /*66*/100),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, /*66*/100),
-+ 0
-+ },
-+ &spi_driver_f25l64q,
-+ },
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, /*66*/100),
++ 0
++ },
++ &spi_driver_f25l64q,
++ },
+
-+ {
-+ "GD25Q128", {0xC8, 0x40, 0x18}, 3, _16M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 66),
++ {
++ "GD25Q128", {0xC8, 0x40, 0x18}, 3, _16M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 66),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 100),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 100),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 100),
-+ 0
-+ },
-+ &spi_driver_gd25qxxx,
-+ },
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 100),
++ 0
++ },
++ &spi_driver_gd25qxxx,
++ },
+
-+ {
-+ "GD25Q64", {0xC8, 0x40, 0x17}, 3, _8M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 66),
++ {
++ "GD25Q64", {0xC8, 0x40, 0x17}, 3, _8M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 66),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 100),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 100),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 100),
-+ 0
-+ },
-+ &spi_driver_gd25qxxx,
-+ },
-+ {
-+ "GD25Q32", {0xC8, 0x40, 0x16}, 3, _4M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 66),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 100),
++ 0
++ },
++ &spi_driver_gd25qxxx,
++ },
++ {
++ "GD25Q32", {0xC8, 0x40, 0x16}, 3, _4M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 66),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 80),
++ &READ_QUAD(1, INFINITE, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 100),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 100),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &WRITE_QUAD(0, 256, 80),
++ &WRITE_QUAD(0, 256, 80),
+#endif
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 100),
-+ 0
-+ },
-+ &spi_driver_gd25qxxx,
-+ },
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 100),
++ 0
++ },
++ &spi_driver_gd25qxxx,
++ },
+
-+ /* Paragon 3.3V */
-+ {
-+ "PN25F16S", {0xe0, 0x40, 0x15}, 3, _2M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 55),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 108),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 108),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ /* Paragon 3.3V */
++ {
++ "PN25F16S", {0xe0, 0x40, 0x15}, 3, _2M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 55),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 108),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 108),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {
-+ "PN25F32S", {0xe0, 0x40, 0x16}, 3, _4M, _64K, 3,
-+ {
-+ &READ_STD(0, INFINITE, 55),
-+ &READ_FAST(1, INFINITE, 108),
-+ &READ_DUAL(1, INFINITE, 108),
-+ &READ_DUAL_ADDR(1, INFINITE, 108),
++ {
++ "PN25F32S", {0xe0, 0x40, 0x16}, 3, _4M, _64K, 3,
++ {
++ &READ_STD(0, INFINITE, 55),
++ &READ_FAST(1, INFINITE, 108),
++ &READ_DUAL(1, INFINITE, 108),
++ &READ_DUAL_ADDR(1, INFINITE, 108),
+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
-+ &READ_QUAD(1, INFINITE, 108),
-+ &READ_QUAD_ADDR(3, INFINITE, 108),
++ &READ_QUAD(1, INFINITE, 108),
++ &READ_QUAD_ADDR(3, INFINITE, 108),
+#endif
-+ 0
-+ },
-+ {
-+ &WRITE_STD(0, 256, 108),
-+ 0
-+ },
-+ {
-+ &ERASE_SECTOR_64K(0, _64K, 108),
-+ 0
-+ },
-+ &spi_driver_general,
-+ },
++ 0
++ },
++ {
++ &WRITE_STD(0, 256, 108),
++ 0
++ },
++ {
++ &ERASE_SECTOR_64K(0, _64K, 108),
++ 0
++ },
++ &spi_driver_general,
++ },
+
-+ {0, {0}, 0, 0, 0, 0, {0}, {0}, {0}, NULL},
++ {0, {0}, 0, 0, 0, 0, {0}, {0}, {0}, NULL},
+};
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_micron.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_micron.c
new file mode 100644
-index 0000000..9797550
+index 0000000..8a5006c
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_micron.c
@@ -0,0 +1,102 @@
@@ -308909,74 +377124,74 @@ index 0000000..9797550
+/****************************************************************************/
+static int spi_micron_entry_4addr(struct hisfc_spi *spi, int enable)
+{
-+ unsigned char status;
-+ unsigned int reg;
-+ const char *str[] = {"Disable", "Enable"};
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ unsigned char status;
++ unsigned int reg;
++ const char *str[] = {"Disable", "Enable"};
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
-+ return 0;
-+ }
++ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
++ return 0;
++ }
+
-+ status = spi_general_get_flash_register(spi, SPI_CMD_FLAG_SR_MICRON);
-+ if (DEBUG_SPI)
-+ printk(KERN_INFO"\t Read flag status register[%#x]:%#x\n",
-+ SPI_CMD_FLAG_SR_MICRON, status);
++ status = spi_general_get_flash_register(spi, SPI_CMD_FLAG_SR_MICRON);
++ if (DEBUG_SPI)
++ printk(KERN_INFO"\t Read flag status register[%#x]:%#x\n",
++ SPI_CMD_FLAG_SR_MICRON, status);
+
-+ if (SPI_NOR_GET_4BYTE_BY_FLAG_SR(status) == enable) {
-+ if (DEBUG_SPI)
-+ printk(KERN_INFO"\t* 4-byte was %sd, reg:%#x\n", str[enable],
-+ status);
-+ return 0;
-+ }
++ if (SPI_NOR_GET_4BYTE_BY_FLAG_SR(status) == enable) {
++ if (DEBUG_SPI)
++ printk(KERN_INFO"\t* 4-byte was %sd, reg:%#x\n", str[enable],
++ status);
++ return 0;
++ }
+
-+ spi->driver->write_enable(spi);
++ spi->driver->write_enable(spi);
+
-+ if (enable) {
-+ reg = SPI_CMD_EN4B;
-+ } else {
-+ reg = SPI_CMD_EX4B;
-+ }
++ if (enable) {
++ reg = SPI_CMD_EN4B;
++ } else {
++ reg = SPI_CMD_EX4B;
++ }
+
-+ hisfc_write(host, HISFC350_CMD_INS, reg);
-+ if (DEBUG_SPI) {
-+ printk(KERN_INFO"\t Set CMD[%#x]%#x\n", HISFC350_CMD_INS, reg);
-+ }
++ hisfc_write(host, HISFC350_CMD_INS, reg);
++ if (DEBUG_SPI) {
++ printk(KERN_INFO"\t Set CMD[%#x]%#x\n", HISFC350_CMD_INS, reg);
++ }
+
-+ reg = HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START;
-+ hisfc_write(host, HISFC350_CMD_CONFIG, reg);
++ reg = HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START;
++ hisfc_write(host, HISFC350_CMD_CONFIG, reg);
+
-+ if (DEBUG_SPI) {
-+ printk(KERN_INFO"\t Set OP_CFG[%#x]%#x\n", HISFC350_CMD_CONFIG, reg);
-+ }
++ if (DEBUG_SPI) {
++ printk(KERN_INFO"\t Set OP_CFG[%#x]%#x\n", HISFC350_CMD_CONFIG, reg);
++ }
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ host->set_host_addr_mode(host, enable);
++ host->set_host_addr_mode(host, enable);
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ status = spi_general_get_flash_register(spi,
-+ SPI_CMD_FLAG_SR_MICRON);
-+ if (DEBUG_SPI)
-+ printk(KERN_INFO"\t Read flag status register[%#x]:%#x\n",
-+ SPI_CMD_FLAG_SR_MICRON, status);
-+ if (SPI_NOR_GET_4BYTE_BY_FLAG_SR(status) != enable) {
-+ printk(KERN_INFO"Error: %s 4-byte failed! SR3:%#x\n",
-+ str[enable], status);
-+ return status;
-+ }
++ status = spi_general_get_flash_register(spi,
++ SPI_CMD_FLAG_SR_MICRON);
++ if (DEBUG_SPI)
++ printk(KERN_INFO"\t Read flag status register[%#x]:%#x\n",
++ SPI_CMD_FLAG_SR_MICRON, status);
++ if (SPI_NOR_GET_4BYTE_BY_FLAG_SR(status) != enable) {
++ printk(KERN_INFO"Error: %s 4-byte failed! SR3:%#x\n",
++ str[enable], status);
++ return status;
++ }
+
-+ if (DEBUG_SPI) {
-+ printk(KERN_INFO"\t %s 4-byte success, SR3:%#x\n", str[enable], status);
-+ printk(KERN_INFO"\t* End SPI Nor flash %s 4-byte mode.\n", str[enable]);
-+ }
-+ return 0;
++ if (DEBUG_SPI) {
++ printk(KERN_INFO"\t %s 4-byte success, SR3:%#x\n", str[enable], status);
++ printk(KERN_INFO"\t* End SPI Nor flash %s 4-byte mode.\n", str[enable]);
++ }
++ return 0;
+}
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_mx25l25635e.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_mx25l25635e.c
new file mode 100644
-index 0000000..23fcf9f
+index 0000000..92ed47c
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_mx25l25635e.c
@@ -0,0 +1,103 @@
@@ -309015,77 +377230,77 @@ index 0000000..23fcf9f
+*/
+static int spi_mx25l25635e_qe_enable(struct hisfc_spi *spi)
+{
-+ unsigned char status, op;
-+ unsigned int reg;
-+ const char *str[] = {"Disable", "Enable"};
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ unsigned char status, op;
++ unsigned int reg;
++ const char *str[] = {"Disable", "Enable"};
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ op = hisfc350_is_quad(spi);
++ op = hisfc350_is_quad(spi);
+
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO "* Start SPI Nor %s Quad.\n", str[op]);
-+ }
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO "* Start SPI Nor %s Quad.\n", str[op]);
++ }
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
-+ if (DEBUG_SPI_QE)
-+ printk(KERN_INFO " Read status %#x, val[%#x]\n", SPI_CMD_RDSR,
-+ status);
-+ if (((status & MX_SPI_NOR_SR_QE_MASK) >> MX_SPI_NOR_SR_QE_SHIFT)
-+ == op) {
-+ if (DEBUG_SPI_QE) {
-+ printk(KERN_INFO "* Quad was %sd!\n", str[op]);
-+ }
-+ return op;
-+ }
++ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
++ if (DEBUG_SPI_QE)
++ printk(KERN_INFO " Read status %#x, val[%#x]\n", SPI_CMD_RDSR,
++ status);
++ if (((status & MX_SPI_NOR_SR_QE_MASK) >> MX_SPI_NOR_SR_QE_SHIFT)
++ == op) {
++ if (DEBUG_SPI_QE) {
++ printk(KERN_INFO "* Quad was %sd!\n", str[op]);
++ }
++ return op;
++ }
+
-+ spi->driver->write_enable(spi);
++ spi->driver->write_enable(spi);
+
-+ if (op) {
-+ status |= MX_SPI_NOR_SR_QE_MASK;
-+ } else {
-+ status &= ~MX_SPI_NOR_SR_QE_MASK;
-+ }
-+ hisfc_write(host, HISFC350_CMD_DATABUF0, status);
-+ if (DEBUG_SPI_QE)
-+ printk(KERN_INFO " Set DATA[%#x]%#x\n", HISFC350_CMD_DATABUF0,
-+ status);
++ if (op) {
++ status |= MX_SPI_NOR_SR_QE_MASK;
++ } else {
++ status &= ~MX_SPI_NOR_SR_QE_MASK;
++ }
++ hisfc_write(host, HISFC350_CMD_DATABUF0, status);
++ if (DEBUG_SPI_QE)
++ printk(KERN_INFO " Set DATA[%#x]%#x\n", HISFC350_CMD_DATABUF0,
++ status);
+
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR);
-+ if (DEBUG_SPI_QE)
-+ printk(KERN_INFO " Set INS[%#x]%#x\n", HISFC350_CMD_INS,
-+ SPI_CMD_WRSR);
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR);
++ if (DEBUG_SPI_QE)
++ printk(KERN_INFO " Set INS[%#x]%#x\n", HISFC350_CMD_INS,
++ SPI_CMD_WRSR);
+
-+ reg = HISFC350_CMD_CONFIG_DATA_CNT(SPI_NOR_SR_LEN)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START;
-+ hisfc_write(host, HISFC350_CMD_CONFIG, reg);
-+ if (DEBUG_SPI_QE)
-+ printk(KERN_INFO " Set CONFIG[%#x]%#x\n", HISFC350_CMD_CONFIG,
-+ reg);
++ reg = HISFC350_CMD_CONFIG_DATA_CNT(SPI_NOR_SR_LEN)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START;
++ hisfc_write(host, HISFC350_CMD_CONFIG, reg);
++ if (DEBUG_SPI_QE)
++ printk(KERN_INFO " Set CONFIG[%#x]%#x\n", HISFC350_CMD_CONFIG,
++ reg);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ if (DEBUG_SPI_QE) {
-+ spi->driver->wait_ready(spi);
++ if (DEBUG_SPI_QE) {
++ spi->driver->wait_ready(spi);
+
-+ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
-+ if (((status & MX_SPI_NOR_SR_QE_MASK) >> MX_SPI_NOR_SR_QE_SHIFT)
-+ == op) {
-+ printk(KERN_INFO "* SPI %s Quad succeed.\n", str[op]);
-+ } else {
-+ DBG_MSG("%s Quad failed! [%#x]\n", str[op], status);
-+ }
-+ }
++ status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
++ if (((status & MX_SPI_NOR_SR_QE_MASK) >> MX_SPI_NOR_SR_QE_SHIFT)
++ == op) {
++ printk(KERN_INFO "* SPI %s Quad succeed.\n", str[op]);
++ } else {
++ DBG_MSG("%s Quad failed! [%#x]\n", str[op], status);
++ }
++ }
+
-+ return op;
++ return op;
+}
+
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_n25q256a.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_n25q256a.c
new file mode 100644
-index 0000000..a4a4a02
+index 0000000..8f38f23
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_n25q256a.c
@@ -0,0 +1,54 @@
@@ -309116,36 +377331,36 @@ index 0000000..a4a4a02
+
+static int spi_n25q256a_entry_4addr(struct hisfc_spi *spi, int enable)
+{
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ if (spi->addrcycle != 4) {
-+ return 0;
-+ }
++ if (spi->addrcycle != 4) {
++ return 0;
++ }
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ if (enable) {
-+ spi->driver->write_enable(spi);
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EN4B);
-+ } else {
-+ spi->driver->write_enable(spi);
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EX4B);
-+ }
++ if (enable) {
++ spi->driver->write_enable(spi);
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EN4B);
++ } else {
++ spi->driver->write_enable(spi);
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EX4B);
++ }
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
-+ host->set_host_addr_mode(host, enable);
++ host->set_host_addr_mode(host, enable);
+
-+ return 0;
++ return 0;
+}
+
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_s25fl256s.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_s25fl256s.c
new file mode 100644
-index 0000000..6c79036
+index 0000000..8d8a65b
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_s25fl256s.c
@@ -0,0 +1,70 @@
@@ -309180,48 +377395,48 @@ index 0000000..6c79036
+
+static int spi_s25fl256s_entry_4addr(struct hisfc_spi *spi, int enable)
+{
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
-+ unsigned int regval = 0;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ unsigned int regval = 0;
+
-+ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
-+ return 0;
-+ }
++ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
++ return 0;
++ }
+
-+ spi->driver->wait_ready(spi);
++ spi->driver->wait_ready(spi);
+
-+ if (enable) {
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_BRWR);
-+ hisfc_write(host, HISFC350_CMD_DATABUF0, SPI_EN4B);
-+ } else {
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_BRWR);
-+ hisfc_write(host, HISFC350_CMD_DATABUF0, SPI_EX4B);
-+ }
++ if (enable) {
++ hisfc_write(host, HISFC350_CMD_INS, SPI_BRWR);
++ hisfc_write(host, HISFC350_CMD_DATABUF0, SPI_EN4B);
++ } else {
++ hisfc_write(host, HISFC350_CMD_INS, SPI_BRWR);
++ hisfc_write(host, HISFC350_CMD_DATABUF0, SPI_EX4B);
++ }
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_DATA_CNT(1)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_DATA_CNT(1)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
-+ if (DEBUG_SPI) {
-+ regval = hisfc_read(host, HISFC350_CMD_DATABUF0);
-+ if (!(regval & SPI_EN4B)) {
-+ printk(KERN_INFO "now is 3-byte address mode\n");
-+ printk(KERN_INFO "regval_read_SPI : 0x%x\n", regval);
-+ } else {
-+ printk(KERN_INFO "now is 4-byte address mode\n");
-+ }
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ if (DEBUG_SPI) {
++ regval = hisfc_read(host, HISFC350_CMD_DATABUF0);
++ if (!(regval & SPI_EN4B)) {
++ printk(KERN_INFO "now is 3-byte address mode\n");
++ printk(KERN_INFO "regval_read_SPI : 0x%x\n", regval);
++ } else {
++ printk(KERN_INFO "now is 4-byte address mode\n");
++ }
+
-+ }
-+ host->set_host_addr_mode(host, enable);
++ }
++ host->set_host_addr_mode(host, enable);
+
-+ return 0;
++ return 0;
+}
+
diff --git a/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_w25q256fv.c b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_w25q256fv.c
new file mode 100644
-index 0000000..0d43968
+index 0000000..5a04ebc
--- /dev/null
+++ b/drivers/mtd/spi-nor/hisfc350/hisfc350_spi_w25q256fv.c
@@ -0,0 +1,85 @@
@@ -309255,59 +377470,59 @@ index 0000000..0d43968
+
+static int spi_w25q256fv_entry_4addr(struct hisfc_spi *spi, int enable)
+{
-+ struct hisfc_host *host = (struct hisfc_host *)spi->host;
++ struct hisfc_host *host = (struct hisfc_host *)spi->host;
+
-+ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
-+ return 0;
-+ }
++ if (spi->addrcycle != SPI_4BYTE_ADDR_LEN) {
++ return 0;
++ }
+
-+ spi->driver->wait_ready(spi);
-+ /* This chip should not enable write here,
-+ * we have confirmed with the WINBOND */
-+ /* spi->driver->write_enable(spi); */
-+ if (enable) {
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EN4B);
-+ if (DEBUG_SPI) {
-+ printk(KERN_INFO "now w25q256fv is 4-byte address mode\n");
-+ }
++ spi->driver->wait_ready(spi);
++ /* This chip should not enable write here,
++ * we have confirmed with the WINBOND */
++ /* spi->driver->write_enable(spi); */
++ if (enable) {
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_EN4B);
++ if (DEBUG_SPI) {
++ printk(KERN_INFO "now w25q256fv is 4-byte address mode\n");
++ }
+
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
-+ } else {
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_FIRST_RESET_4ADDR);
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ } else {
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_FIRST_RESET_4ADDR);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
+
+
-+ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_SECOND_RESET_4ADDR);
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_START);
++ hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_SECOND_RESET_4ADDR);
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
-+ if (DEBUG_SPI) {
-+ printk(KERN_INFO "now W25Q256FV 6699 cmd\n");
-+ }
-+ }
-+ /*
-+ hisfc_write(host, HISFC350_CMD_CONFIG,
-+ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
-+ | HISFC350_CMD_CONFIG_DATA_CNT(1)
-+ | HISFC350_CMD_CONFIG_DATA_EN
-+ | HISFC350_CMD_CONFIG_START);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ if (DEBUG_SPI) {
++ printk(KERN_INFO "now W25Q256FV 6699 cmd\n");
++ }
++ }
++ /*
++ hisfc_write(host, HISFC350_CMD_CONFIG,
++ HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
++ | HISFC350_CMD_CONFIG_DATA_CNT(1)
++ | HISFC350_CMD_CONFIG_DATA_EN
++ | HISFC350_CMD_CONFIG_START);
+
-+ HISFC350_CMD_WAIT_CPU_FINISH(host);
-+ */
-+ host->set_host_addr_mode(host, enable);
++ HISFC350_CMD_WAIT_CPU_FINISH(host);
++ */
++ host->set_host_addr_mode(host, enable);
+
-+ return 0;
++ return 0;
+}
+
diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c
@@ -309968,10 +378183,21 @@ index 20378b0..ffe6dd5 100644
module_platform_driver(hisi_spi_nor_driver);
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
-index 21dde52..638c9ca 100644
+index 21dde52..6440d77 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -75,6 +75,13 @@ struct flash_info {
+@@ -23,6 +23,10 @@
+ #include <linux/spi/flash.h>
+ #include <linux/mtd/spi-nor.h>
+
++#if defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
++#define CONFIG_AUTOMOTIVE_GRADE
++#endif
++
+ /* Define max times to check status register before we give up. */
+
+ /*
+@@ -75,6 +79,13 @@ struct flash_info {
* bit. Must be used with
* SPI_NOR_HAS_LOCK.
*/
@@ -309985,16 +378211,19 @@ index 21dde52..638c9ca 100644
};
#define JEDEC_MFR(info) ((info)->id[0])
-@@ -139,24 +146,6 @@ static int read_cr(struct spi_nor *nor)
+@@ -139,31 +150,24 @@ static int read_cr(struct spi_nor *nor)
}
/*
- * Dummy Cycle calculation for different type of read.
- * It can be used to support more commands with
- * different dummy cycle requirements.
-- */
++ * Write status register 1 byte
++ * Returns negative if error occurred.
+ */
-static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
--{
++static inline int write_sr(struct spi_nor *nor, u8 val)
+ {
- switch (nor->flash_read) {
- case SPI_NOR_FAST:
- case SPI_NOR_DUAL:
@@ -310004,13 +378233,26 @@ index 21dde52..638c9ca 100644
- return 0;
- }
- return 0;
--}
--
--/*
- * Write status register 1 byte
++ nor->cmd_buf[0] = val;
++ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
+ }
+
++
+ /*
+- * Write status register 1 byte
++ * Write status register-2 1 byte
* Returns negative if error occurred.
*/
-@@ -188,9 +177,83 @@ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
+-static inline int write_sr(struct spi_nor *nor, u8 val)
++static inline int write_sr2(struct spi_nor *nor, u8 val)
+ {
+ nor->cmd_buf[0] = val;
+- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
++ return nor->write_reg(nor, SPINOR_OP_WRSR2, nor->cmd_buf, 1);
+ }
+
+ /*
+@@ -188,9 +192,83 @@ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
@@ -310095,7 +378337,7 @@ index 21dde52..638c9ca 100644
{
int status;
bool need_wren = false;
-@@ -201,16 +264,26 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
+@@ -201,16 +279,26 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
/* Some Micron need WREN command; all will accept it */
need_wren = true;
case SNOR_MFR_MACRONIX:
@@ -310123,7 +378365,7 @@ index 21dde52..638c9ca 100644
default:
/* Spansion style */
nor->cmd_buf[0] = enable << 7;
-@@ -220,24 +293,28 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
+@@ -220,24 +308,28 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
static inline int spi_nor_sr_ready(struct spi_nor *nor)
{
int sr = read_sr(nor);
@@ -310131,7 +378373,8 @@ index 21dde52..638c9ca 100644
if (sr < 0)
return sr;
else
- return !(sr & SR_WIP);
+- return !(sr & SR_WIP);
++ return !((unsigned int)sr & SR_WIP);
}
-static inline int spi_nor_fsr_ready(struct spi_nor *nor)
@@ -310154,7 +378397,39 @@ index 21dde52..638c9ca 100644
sr = spi_nor_sr_ready(nor);
if (sr < 0)
return sr;
-@@ -367,6 +444,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
+@@ -282,7 +374,31 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
+ return spi_nor_wait_till_ready_with_timeout(nor,
+ DEFAULT_READY_WAIT_JIFFIES);
+ }
++static int issi_spi_nor_wait_till_ready(struct spi_nor *nor)
++{
++ unsigned long deadline;
++ int timeout = 0;
++ int ret;
++
++ deadline = jiffies + DEFAULT_READY_WAIT_JIFFIES;
++
++ while (!timeout) {
++ if (time_after_eq(jiffies, deadline))
++ timeout = 1;
++
++ ret = spi_nor_sr_ready(nor);
++ if (ret < 0)
++ return ret;
++ if (ret)
++ return 0;
++
++ cond_resched();
++ }
++
++ dev_err(nor->dev, "flash operation timed out\n");
+
++ return -ETIMEDOUT;
++}
+ /*
+ * Erase the whole flash memory
+ *
+@@ -367,6 +483,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (ret)
return ret;
@@ -310167,7 +378442,7 @@ index 21dde52..638c9ca 100644
/* whole-chip erase? */
if (len == mtd->size) {
unsigned long timeout;
-@@ -745,6 +828,239 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+@@ -745,6 +867,280 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
return ret;
}
@@ -310187,6 +378462,9 @@ index 21dde52..638c9ca 100644
+static int macronix_quad_enable(struct spi_nor *nor);
+static int gd_quad_enable(struct spi_nor *nor);
+static int xtx_quad_enable(struct spi_nor *nor);
++static int issi_quad_enable(struct spi_nor *nor);
++static int puya_quad_enable(struct spi_nor *nor);
++static int puya_quad_enable(struct spi_nor *nor);
+
+#define SNOR_EON_RD_MODES \
+ (SNOR_MODE_SLOW | \
@@ -310310,6 +378588,25 @@ index 21dde52..638c9ca 100644
+
+};
+
++static const struct spi_nor_basic_flash_parameter issi_params = {
++ .rd_modes = SNOR_RD_MODES,
++ .reads[SNOR_MIDX_SLOW] = SNOR_OP_READ(0, 0, SPINOR_OP_READ),
++ .reads[SNOR_MIDX_1_1_1] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST),
++ .reads[SNOR_MIDX_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2),
++ .reads[SNOR_MIDX_1_2_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2),
++ .reads[SNOR_MIDX_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4),
++ .reads[SNOR_MIDX_1_4_4] = SNOR_OP_READ(8, 16, SPINOR_OP_READ_1_4_4),
++
++ .wr_modes = SNOR_WR_MODES,
++ .page_programs[SNOR_MIDX_1_1_1] = SPINOR_OP_PP,
++ .page_programs[SNOR_MIDX_1_1_4] = SPINOR_OP_PP_1_1_4,
++
++ .erase_types[0] = SNOR_OP_ERASE_64K(SPINOR_OP_SE),
++
++ .enable_quad_io = issi_quad_enable,
++
++};
++
+#define SNOR_MXIC_WR_MODES \
+ (SNOR_MODE_1_1_1 | \
+ SNOR_MODE_1_4_4)
@@ -310402,12 +378699,31 @@ index 21dde52..638c9ca 100644
+ .enable_quad_io = xtx_quad_enable,
+
+};
++
++static const struct spi_nor_basic_flash_parameter puya_params = {
++ .rd_modes= SNOR_RD_MODES,
++ .reads[SNOR_MIDX_SLOW]= SNOR_OP_READ(0, 0, SPINOR_OP_READ),
++ .reads[SNOR_MIDX_1_1_1]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST),
++ .reads[SNOR_MIDX_1_1_2]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2),
++ .reads[SNOR_MIDX_1_2_2]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2),
++ .reads[SNOR_MIDX_1_1_4]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4),
++ .reads[SNOR_MIDX_1_4_4]= SNOR_OP_READ(0, 24, SPINOR_OP_READ_1_4_4),
++
++ .wr_modes= SNOR_WR_MODES,
++ .page_programs[SNOR_MIDX_1_1_1]= SPINOR_OP_PP,
++ .page_programs[SNOR_MIDX_1_1_4]= SPINOR_OP_PP_1_1_4,
++
++ .erase_types[0]= SNOR_OP_ERASE_64K(SPINOR_OP_SE),
++
++ .enable_quad_io = puya_quad_enable,
++};
++
+#define PARAMS(_name) .params = &_name##_params
+
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
-@@ -758,7 +1074,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+@@ -758,7 +1154,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
.sector_size = (_sector_size), \
.n_sectors = (_n_sectors), \
.page_size = 256, \
@@ -310416,18 +378732,18 @@ index 21dde52..638c9ca 100644
#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
-@@ -782,6 +1098,10 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+@@ -782,6 +1178,10 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
.addr_width = (_addr_width), \
.flags = (_flags),
-+/* Different from spi-max-frequency in DTS, the clk here stands for the clock
++/* Different from spi-max-frequency in DTS, the clk here stands for the clock
+ * rate on SPI interface, it is half of the FMC CRG configuration */
+#define CLK_MHZ_2X(clk) .clkrate = (clk * 2000000),
+
/* NOTE: double check command sets and memory organization when you add
* more nor chips. This current list focusses on newer chips, which
* have been converging on command sets which including JEDEC ID.
-@@ -793,6 +1113,54 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+@@ -793,6 +1193,63 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
* For historical (and compatibility) reasons (before we got above config) some
* old entries may be missing 4K flag.
*/
@@ -310445,6 +378761,8 @@ index 21dde52..638c9ca 100644
+ * Macronix/MXIC MX25U25635F/45G 32M 64K 1V8 25645G-DTR
+ * Macronix/MXIC MX25L(256/257) 32M 64K 3V3 25645G-DTR
+ * Macronix/MXIC MX25U51245G 64M 64K 1V8 51245G-DTR
++ * Macronix/MXIC MX25L51245G 64M 64K 3V3
++ * Macronix/MXIC MX66U1G45GM 128M 64K 1V8
+ * Spansion S25FL129P1 16M 64K 3V3
+ * Spansion S25FL256S 32M 64K 3V3
+ * Micron N25Q064A 8M 64K 3V3
@@ -310457,10 +378775,12 @@ index 21dde52..638c9ca 100644
+ * Winbond W25Q32(B/F)V 4M 64K 3V3
+ * Winbond W25Q32FW 4M 64K 1V8
+ * Winbond W25Q64FW 8M 64K 1V8
-+ * Winbond W25Q64FV(SPI)/W25Q64JV_IQ 8M 64K 3V3
++ * Winbond W25Q64FV(SPI)/W25Q64JV_IQ 8M 64K 3V3
+ * Winbond W25Q128FW 16M 64K 1V8
+ * Winbond W25Q128(B/F)V 16M 64K 3V3
+ * Winbond W25Q128JV_IM 16M 64K 3V3 DTR
++ * Winbond W25Q256JWEIQ 32M 64K 1V8
++ * Winbond W25Q256JWFIM 32M 64K 1V8
+ * ESMT/CFEON EN25Q32B 4M 64K 3V3
+ * ESMT/CFEON EN25Q64 8M 64K 3V3
+ * ESMT/CFEON EN25Q128 16M 64K 3V3
@@ -310478,11 +378798,16 @@ index 21dde52..638c9ca 100644
+ * 1.2 XMC XM25QH64AHIG 8M 64K 3V3
+ * XMC XM25QH128A 16M 64K 3V3
+ * XMC XM25QH128B 16M 64K 3V3
++ * Puya P25Q128H-SUH-IT 16M 64K 3V3
++ * FM FM25Q64-SOB-T-G 8M 64K 3V3
++ * FM FM25Q128-SOB-T-G 16M 64K 3V3
++ * HUAHONG H25S64 8M 64K 3V3
++ * HUAHONG H25S128 16M 64K 3V3
+ ********************************************************************************************/
static const struct flash_info spi_nor_ids[] = {
/* Atmel -- some are (confusingly) marketed as "DataFlash" */
{ "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
-@@ -812,44 +1180,51 @@ static const struct flash_info spi_nor_ids[] = {
+@@ -812,44 +1269,51 @@ static const struct flash_info spi_nor_ids[] = {
/* EON -- en25xxx */
{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
{ "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
@@ -310545,7 +378870,7 @@ index 21dde52..638c9ca 100644
+ SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(120) },
+ { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(120) },
-+ { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
++ { "gd25q128/gd25q127", INFO(0xc84018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(80) },
+ { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(gd), CLK_MHZ_2X(80) },
@@ -310559,11 +378884,14 @@ index 21dde52..638c9ca 100644
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
-@@ -859,68 +1234,124 @@ static const struct flash_info spi_nor_ids[] = {
+@@ -859,68 +1323,130 @@ static const struct flash_info spi_nor_ids[] = {
/* ISSI */
{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
- /* Macronix */
++ { "IS25WP512M-RMLA3", INFO(0x9d701a, 0, 64 * 1024, 1024,
++ SPI_NOR_QUAD_READ), PARAMS(issi), CLK_MHZ_2X(80) },
++
+ /* Macronix/MXIC 3.3V */
{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
{ "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
@@ -310604,7 +378932,8 @@ index 21dde52..638c9ca 100644
- { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
- { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
- { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
-+ { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ)},
++ { "mx66l51235l/mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
++ SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(133)},
+ { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ)},
+ { "mx25v1635f", INFO(0xc22315, 0, 64 * 1024, 32 ,
+ SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(80) },
@@ -310622,6 +378951,8 @@ index 21dde52..638c9ca 100644
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(84) },
+ { "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(166) },
++ { "mx66u1g45gm", INFO(0xc2253b, 0, 64 * 1024, 2048,
++ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(133) },
+
+ /* Micron 3.3V */
+ { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ),
@@ -310730,7 +379061,7 @@ index 21dde52..638c9ca 100644
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
-@@ -972,43 +1403,66 @@ static const struct flash_info spi_nor_ids[] = {
+@@ -972,43 +1498,93 @@ static const struct flash_info spi_nor_ids[] = {
{ "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
{ "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
@@ -310775,8 +379106,13 @@ index 21dde52..638c9ca 100644
+ SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(104) },
+ { "w25q128jv_im", INFO(0xef7018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
-+ { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
++#ifdef CONFIG_AUTOMOTIVE_GRADE
++ { "w25q256(f/j)v", INFO(0xef4019, 0, 64 * 1024, 512,
++ SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
++#else
++ { "w25q256(f/j)v", INFO(0xef4019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(winbond), CLK_MHZ_2X(80) },
++#endif
+ /* Winbond 1.8V */
+ { "w25q32fw", INFO(0xef6016, 0, 64 * 1024, 64,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
@@ -310787,10 +379123,14 @@ index 21dde52..638c9ca 100644
+ { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB), PARAMS(winbond), CLK_MHZ_2X(80) },
-+ { "w25q256jw", INFO(0xef8019, 0, 64 * 1024, 512,
++ { "w25q256jw-im", INFO(0xef8019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES),
+ PARAMS(winbond), CLK_MHZ_2X(80) },
++ { "w25q256jw-iq", INFO(0xef6019, 0, 64 * 1024, 512,
++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
++ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES),
++ PARAMS(winbond), CLK_MHZ_2X(133) },
/* Catalyst / On Semiconductor -- non-JEDEC */
- { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
@@ -310820,10 +379160,28 @@ index 21dde52..638c9ca 100644
+
+ { "xt25f64b", INFO(0x0b4017, 0, 64 * 1024, 128,
+ SPI_NOR_QUAD_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
++
++ /*puya 3.3V */
++ {"p25q128h", INFO(0x856018, 0, 64 * 1024, 256,
++ SPI_NOR_QUAD_READ), PARAMS(puya), CLK_MHZ_2X(104) },
++
++ /* FM 3.3v */
++ { "FM25Q64-SOB-T-G",INFO(0xa14017, 0, 64 * 1024, 128,
++ SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
++ { "FM25Q128-SOB-T-G",INFO(0xa14018, 0, 64 * 1024, 256,
++ SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
++
++ /* HUAHONG 3.3v */
++ { "H25S64",INFO(0x684017, 0, 64 * 1024, 128,
++ SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
++
++ { "H25S128",INFO(0x684018, 0, 64 * 1024, 256,
++ SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
++
{ },
};
-@@ -1024,6 +1478,11 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
+@@ -1024,6 +1600,11 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
return ERR_PTR(tmp);
}
@@ -310835,7 +379193,44 @@ index 21dde52..638c9ca 100644
for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
info = &spi_nor_ids[tmp];
if (info->id_len) {
-@@ -1167,14 +1626,22 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
+@@ -1036,6 +1617,36 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
+ return ERR_PTR(-ENODEV);
+ }
+
++static int puya_quad_enable(struct spi_nor *nor)
++{
++ int ret;
++ u8 val;
++
++ ret = read_cr(nor);
++ if ((unsigned int)ret & CR_QUAD_EN_SPAN)
++ return 0;
++
++ val = (((unsigned int)ret & 0xff) | CR_QUAD_EN_SPAN);
++ write_enable(nor);
++
++ ret = write_sr2(nor, val);
++ if (ret < 0) {
++ dev_err(nor->dev,
++ "error while writing status register-2\n");
++ return -EINVAL;
++ }
++
++ if (spi_nor_wait_till_ready(nor))
++ return 1;
++
++ /* read back and check it */
++ ret = read_cr(nor);
++ if ((unsigned int)ret & CR_QUAD_EN_SPAN)
++ return 0;
++ else
++ return 1;
++}
++
+ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+ {
+@@ -1167,14 +1778,22 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
if (ret)
return ret;
@@ -310850,7 +379245,7 @@ index 21dde52..638c9ca 100644
ssize_t written;
page_offset = (to + i) & (nor->page_size - 1);
-+#ifndef CONFIG_SPI_HISI_SFC
++#ifndef CONFIG_SPI_HISI_SFC
WARN_ONCE(page_offset,
"Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
page_offset);
@@ -310858,7 +379253,7 @@ index 21dde52..638c9ca 100644
/* the size of data remaining on the first page */
page_remain = min_t(size_t,
nor->page_size - page_offset, len - i);
-@@ -1211,15 +1678,22 @@ static int macronix_quad_enable(struct spi_nor *nor)
+@@ -1211,15 +1830,22 @@ static int macronix_quad_enable(struct spi_nor *nor)
val = read_sr(nor);
if (val < 0)
return val;
@@ -310883,7 +379278,7 @@ index 21dde52..638c9ca 100644
dev_err(nor->dev, "Macronix Quad bit not set\n");
return -EINVAL;
}
-@@ -1227,6 +1701,41 @@ static int macronix_quad_enable(struct spi_nor *nor)
+@@ -1227,6 +1853,41 @@ static int macronix_quad_enable(struct spi_nor *nor)
return 0;
}
@@ -310925,7 +379320,7 @@ index 21dde52..638c9ca 100644
/*
* Write status Register and configuration register with 2 bytes
* The first byte will be written to the status register, while the
-@@ -1243,29 +1752,132 @@ static int write_sr_cr(struct spi_nor *nor, u16 val)
+@@ -1243,24 +1904,32 @@ static int write_sr_cr(struct spi_nor *nor, u16 val)
static int spansion_quad_enable(struct spi_nor *nor)
{
@@ -310956,13 +379351,73 @@ index 21dde52..638c9ca 100644
return -EINVAL;
}
+- ret = spi_nor_wait_till_ready(nor);
+- if (ret) {
+- dev_err(nor->dev,
+- "timeout while writing configuration register\n");
+- return ret;
+- }
+ if (spi_nor_wait_till_ready(nor))
++ return 1;
+
+ /* read back and check it */
+ ret = read_cr(nor);
+@@ -1272,32 +1941,197 @@ static int spansion_quad_enable(struct spi_nor *nor)
+ return 0;
+ }
+
+-static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
++static int issi_quad_enable(struct spi_nor *nor)
+ {
+- int status;
++ unsigned int ret;
++ u16 val;
+
+- switch (JEDEC_MFR(info)) {
+- case SNOR_MFR_MACRONIX:
+- status = macronix_quad_enable(nor);
+- if (status) {
+- dev_err(nor->dev, "Macronix quad-read not enabled\n");
+- return -EINVAL;
+- }
+- return status;
+- case SNOR_MFR_MICRON:
++ ret = read_sr(nor);
++ if (ret & QUAD_EN_ISSI)
+ return 0;
+- default:
+- status = spansion_quad_enable(nor);
+- if (status) {
+- dev_err(nor->dev, "Spansion quad-read not enabled\n");
+- return -EINVAL;
+- }
+- return status;
+- }
+-}
+
+-static int spi_nor_check(struct spi_nor *nor)
+-{
++ /* Update the Quad Enable bit. */
++ dev_dbg(nor->dev, "setting Quad Enable (non-volatile) bit\n");
++
++ val = ((ret & 0xff) | QUAD_EN_ISSI);
++
++ write_enable(nor);
++
++ ret = write_sr(nor, val);
++ if (ret < 0) {
++ dev_err(nor->dev,
++ "error while writing configuration register\n");
++ return -EINVAL;
++ }
++
++ if (issi_spi_nor_wait_till_ready(nor))
+ return 1;
+
+ /* read back and check it */
-+ ret = read_cr(nor);
-+ if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
-+ dev_err(nor->dev, "Spansion Quad bit not set\n");
++ ret = read_sr(nor);
++ if (!(ret > 0 && (ret & QUAD_EN_ISSI))) {
++ dev_err(nor->dev, "ISSI Quad bit not set\n");
+ return -EINVAL;
+ }
+
@@ -310990,8 +379445,7 @@ index 21dde52..638c9ca 100644
+ return ret;
+ }
+
- ret = spi_nor_wait_till_ready(nor);
-- if (ret) {
++ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ return ret;
+
@@ -311016,17 +379470,16 @@ index 21dde52..638c9ca 100644
+
+ /* First, Quad Enable for 16-Pin GD flash, use WRSR[01h] cmd */
+ ret = read_cr(nor);
-+ val = ((ret & 0xff) | CR_QUAD_EN_SPAN) << 8;
++ val = (((unsigned int)ret & 0xff) | CR_QUAD_EN_SPAN) << 8;
+
+ ret = read_sr(nor);
-+ val |= (ret & 0xff);
++ val |= ((unsigned int)ret & 0xff);
+
+ write_enable(nor);
+
+ ret = write_sr_cr(nor, val);
+ if (ret < 0) {
- dev_err(nor->dev,
-- "timeout while writing configuration register\n");
++ dev_err(nor->dev,
+ "error while writing config and status register\n");
+ return -EINVAL;
+ }
@@ -311036,47 +379489,50 @@ index 21dde52..638c9ca 100644
+
+ /* read back and check it */
+ ret = read_cr(nor);
-+ if (ret & CR_QUAD_EN_SPAN)
++ if ((unsigned int)ret & CR_QUAD_EN_SPAN)
+ return 0;
+
+ /* Second, Quad Enable for 8-Pin GD flash, use WRCR[31h] cmd */
+ ret = read_sr(nor);
-+ if (!(ret & SR_WEL))
++ if (!((unsigned int)ret & SR_WEL))
+ write_enable(nor);
+
+ ret = read_cr(nor);
-+ nor->cmd_buf[0] = (ret & 0xff) | CR_QUAD_EN_SPAN;
++ nor->cmd_buf[0] = ((unsigned int)ret & 0xff) | CR_QUAD_EN_SPAN;
+
+ ret = nor->write_reg(nor, SPINOR_OP_WRCR, nor->cmd_buf, 1);
+ if (ret < 0) {
+ dev_err(nor->dev, "error while writing config register\n");
- return ret;
- }
-
++ return ret;
++ }
++
+ if (spi_nor_wait_till_ready(nor))
+ return 1;
+
- /* read back and check it */
- ret = read_cr(nor);
- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
-- dev_err(nor->dev, "Spansion Quad bit not set\n");
++ /* read back and check it */
++ ret = read_cr(nor);
++ if (!(ret > 0 && ((unsigned int)ret & CR_QUAD_EN_SPAN))) {
+ dev_err(nor->dev, "GigaDevice Quad bit not set\n");
- return -EINVAL;
- }
-
-@@ -1277,6 +1889,7 @@ static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
- int status;
-
- switch (JEDEC_MFR(info)) {
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
++{
++ int status;
++
++ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_ESMT:
- case SNOR_MFR_MACRONIX:
- status = macronix_quad_enable(nor);
- if (status) {
-@@ -1285,7 +1898,26 @@ static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
- }
- return status;
- case SNOR_MFR_MICRON:
-- return 0;
++ case SNOR_MFR_MACRONIX:
++ status = macronix_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev, "Macronix quad-read not enabled\n");
++ return -EINVAL;
++ }
++ return status;
++ case SNOR_MFR_MICRON:
+ status = micron_quad_enable(nor);
+ if (status) {
+ dev_err(nor->dev, "Micron quad-read not enabled\n");
@@ -311097,17 +379553,43 @@ index 21dde52..638c9ca 100644
+ return -EINVAL;
+ }
+ return status;
- default:
- status = spansion_quad_enable(nor);
- if (status) {
-@@ -1307,8 +1939,373 @@ static int spi_nor_check(struct spi_nor *nor)
++ case SNOR_MFR_PUYA:
++ status = puya_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev, "puya quad-read not enabled\n");
++ return -EINVAL;
++ }
++ return status;
++ case SNOR_MFR_ISSI:
++ status = issi_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev, "puya quad-read not enabled\n");
++ return -EINVAL;
++ }
++ return status;
++ default:
++ status = spansion_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev, "Spansion quad-read not enabled\n");
++ return -EINVAL;
++ }
++ return status;
++ }
++}
++
++static int spi_nor_check(struct spi_nor *nor)
++{
+ if (!nor->dev || !nor->read || !nor->write ||
+ !nor->read_reg || !nor->write_reg) {
+ pr_err("spi-nor: please fill all the necessary fields!\n");
+@@ -1307,8 +2141,373 @@ static int spi_nor_check(struct spi_nor *nor)
return 0;
}
-int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+#ifdef CONFIG_HISI_SPI_BLOCK_PROTECT
+static void spi_lock_update_address(struct spi_nor *nor, const struct flash_info *info)
-+{
+ {
+ unsigned int lock_level_max, sectorsize, chipsize;
+
+ if (!nor->level) {
@@ -311470,12 +379952,12 @@ index 21dde52..638c9ca 100644
+
+int spi_nor_scan(struct spi_nor *nor, const char *name,
+ struct spi_nor_modes *modes)
- {
++{
+ const struct spi_nor_basic_flash_parameter *params = NULL;
const struct flash_info *info = NULL;
struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd;
-@@ -1320,11 +2317,19 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+@@ -1320,11 +2519,19 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
if (ret)
return ret;
@@ -311496,7 +379978,7 @@ index 21dde52..638c9ca 100644
if (IS_ERR_OR_NULL(info))
return -ENOENT;
-@@ -1351,9 +2356,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+@@ -1351,9 +2558,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
info = jinfo;
}
}
@@ -311512,7 +379994,7 @@ index 21dde52..638c9ca 100644
/*
* Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
* with the software protection bits set
-@@ -1367,6 +2378,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+@@ -1367,6 +2580,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
write_sr(nor, 0);
spi_nor_wait_till_ready(nor);
}
@@ -311520,7 +380002,7 @@ index 21dde52..638c9ca 100644
if (!mtd->name)
mtd->name = dev_name(dev);
-@@ -1380,7 +2392,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+@@ -1380,7 +2594,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
/* NOR protection support for STmicro/Micron chips and similar */
if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
@@ -311530,7 +380012,7 @@ index 21dde52..638c9ca 100644
nor->flash_lock = stm_lock;
nor->flash_unlock = stm_unlock;
nor->flash_is_locked = stm_is_locked;
-@@ -1428,92 +2441,61 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+@@ -1428,92 +2643,61 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
if (np) {
/* If we were instantiated by DT, use it */
if (of_property_read_bool(np, "m25p,fast-read"))
@@ -311652,7 +380134,7 @@ index 21dde52..638c9ca 100644
dev_dbg(dev,
"mtd .name = %s, .size = 0x%llx (%lldMiB), "
-@@ -1547,6 +2529,64 @@ static const struct flash_info *spi_nor_match_id(const char *name)
+@@ -1547,6 +2731,64 @@ static const struct flash_info *spi_nor_match_id(const char *name)
return NULL;
}
@@ -311719,7 +380201,7 @@ index 21dde52..638c9ca 100644
MODULE_AUTHOR("Mike Lavender");
diff --git a/drivers/mtd/spi-nor/spi_ids.c b/drivers/mtd/spi-nor/spi_ids.c
new file mode 100644
-index 0000000..acdeea7
+index 0000000..ba5ef9e
--- /dev/null
+++ b/drivers/mtd/spi-nor/spi_ids.c
@@ -0,0 +1,262 @@
@@ -311767,201 +380249,201 @@ index 0000000..acdeea7
+/*****************************************************************************/
+static char *int_to_size(unsigned long long size)
+{
-+ int ix;
-+ static char buffer[20];
-+ char *fmt[] = {"%u", "%uK", "%uM", "%uG", "%uT", "%uT"};
++ int ix;
++ static char buffer[20];
++ char *fmt[] = {"%u", "%uK", "%uM", "%uG", "%uT", "%uT"};
+
-+ for (ix = 0; (ix < 5) && !(size & 0x3FF) && size; ix++) {
-+ size = (size >> 10);
-+ }
++ for (ix = 0; (ix < 5) && !(size & 0x3FF) && size; ix++) {
++ size = (size >> 10);
++ }
+
-+ sprintf(buffer, fmt[ix], size);
-+ return buffer;
++ sprintf(buffer, fmt[ix], size);
++ return buffer;
+}
+/*****************************************************************************/
+
+struct spi_info *spi_serach_ids(unsigned char ids[8])
+{
-+ struct spi_info *info;
-+ struct spi_info *fit_info = NULL;
++ struct spi_info *info;
++ struct spi_info *fit_info = NULL;
+
-+ for (info = spi_info_table; info->name; info++) {
-+ if (memcmp(info->id, ids, info->id_len)) {
-+ continue;
-+ }
++ for (info = spi_info_table; info->name; info++) {
++ if (memcmp(info->id, ids, info->id_len)) {
++ continue;
++ }
+
-+ if ((fit_info == NULL) || (fit_info->id_len < info->id_len)) {
-+ fit_info = info;
-+ }
-+ }
-+ return fit_info;
++ if ((fit_info == NULL) || (fit_info->id_len < info->id_len)) {
++ fit_info = info;
++ }
++ }
++ return fit_info;
+}
+/*****************************************************************************/
+
+void spi_search_rw(struct spi_info *spiinfo, struct spi_operation *spiop_rw,
-+ unsigned int iftype, unsigned int max_dummy, int is_read)
++ unsigned int iftype, unsigned int max_dummy, int is_read)
+{
-+ int ix = 0;
-+ struct spi_operation **spiop, **fitspiop;
++ int ix = 0;
++ struct spi_operation **spiop, **fitspiop;
+
-+ for (fitspiop = spiop = (is_read ? spiinfo->read : spiinfo->write);
-+ (*spiop) && ix < MAX_SPI_OP; spiop++, ix++) {
-+ DBG_MSG("dump[%d] %s iftype:0x%02X\n", ix,
-+ (is_read ? "read" : "write"),
-+ (*spiop)->iftype);
++ for (fitspiop = spiop = (is_read ? spiinfo->read : spiinfo->write);
++ (*spiop) && ix < MAX_SPI_OP; spiop++, ix++) {
++ DBG_MSG("dump[%d] %s iftype:0x%02X\n", ix,
++ (is_read ? "read" : "write"),
++ (*spiop)->iftype);
+
-+ if (((*spiop)->iftype & iftype)
-+ && ((*spiop)->dummy <= max_dummy)
-+ && (*fitspiop)->iftype < (*spiop)->iftype) {
-+ fitspiop = spiop;
-+ }
-+ }
-+ memcpy(spiop_rw, (*fitspiop), sizeof(struct spi_operation));
++ if (((*spiop)->iftype & iftype)
++ && ((*spiop)->dummy <= max_dummy)
++ && (*fitspiop)->iftype < (*spiop)->iftype) {
++ fitspiop = spiop;
++ }
++ }
++ memcpy(spiop_rw, (*fitspiop), sizeof(struct spi_operation));
+}
+/*****************************************************************************/
+#ifndef CONFIG_MTD_HISFC300
+void spi_get_erase(struct spi_info *spiinfo, struct spi_operation *spiop_erase)
+{
-+ int ix;
++ int ix;
+
-+ spiop_erase->size = 0;
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spiinfo->erase[ix] == NULL) {
-+ break;
-+ }
-+ if (spiinfo->erasesize == spiinfo->erase[ix]->size) {
-+ memcpy(&spiop_erase[ix], spiinfo->erase[ix],
-+ sizeof(struct spi_operation));
++ spiop_erase->size = 0;
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spiinfo->erase[ix] == NULL) {
++ break;
++ }
++ if (spiinfo->erasesize == spiinfo->erase[ix]->size) {
++ memcpy(&spiop_erase[ix], spiinfo->erase[ix],
++ sizeof(struct spi_operation));
+
-+ break;
-+ }
-+ }
++ break;
++ }
++ }
+}
+#endif
+/*****************************************************************************/
+
+struct spi_tag {
-+ char name[16];
++ char name[16];
+
-+ unsigned char id[8];
-+ unsigned int id_len;
++ unsigned char id[8];
++ unsigned int id_len;
+
-+ unsigned long chipsize;
-+ unsigned int erasesize;
-+ unsigned int addrcycle;
++ unsigned long chipsize;
++ unsigned int erasesize;
++ unsigned int addrcycle;
+
-+ struct spi_operation read[MAX_SPI_OP];
-+ struct spi_operation write[MAX_SPI_OP];
-+ struct spi_operation erase[MAX_SPI_OP];
++ struct spi_operation read[MAX_SPI_OP];
++ struct spi_operation write[MAX_SPI_OP];
++ struct spi_operation erase[MAX_SPI_OP];
+};
+/*****************************************************************************/
+
+static int __init parse_spi_id(const struct tag *tag)
+{
-+ int ix;
-+ static struct spi_tag spitag[1];
-+ struct spi_info *spiinfo = spi_info_table;
++ int ix;
++ static struct spi_tag spitag[1];
++ struct spi_info *spiinfo = spi_info_table;
+
-+ if (tag->hdr.size < ((sizeof(struct tag_header) +
-+ sizeof(struct spi_tag)) >> 2)) {
-+ printk(KERN_ERR "%s(%d):tag->hdr.size(%d) too small.\n",
-+ __func__, __LINE__, tag->hdr.size);
-+ return 0;
-+ }
-+ memset(spiinfo, 0, sizeof(struct spi_info));
-+ memcpy(spitag, &tag->u, sizeof(struct spi_tag));
++ if (tag->hdr.size < ((sizeof(struct tag_header) +
++ sizeof(struct spi_tag)) >> 2)) {
++ printk(KERN_ERR "%s(%d):tag->hdr.size(%d) too small.\n",
++ __func__, __LINE__, tag->hdr.size);
++ return 0;
++ }
++ memset(spiinfo, 0, sizeof(struct spi_info));
++ memcpy(spitag, &tag->u, sizeof(struct spi_tag));
+
-+ spiinfo->name = spitag->name;
++ spiinfo->name = spitag->name;
+
-+ memcpy(spiinfo->id, spitag->id, 8);
-+ spiinfo->id_len = spitag->id_len;
++ memcpy(spiinfo->id, spitag->id, 8);
++ spiinfo->id_len = spitag->id_len;
+
-+ spiinfo->chipsize = spitag->chipsize;
-+ spiinfo->erasesize = spitag->erasesize;
-+ spiinfo->addrcycle = spitag->addrcycle;
++ spiinfo->chipsize = spitag->chipsize;
++ spiinfo->erasesize = spitag->erasesize;
++ spiinfo->addrcycle = spitag->addrcycle;
+
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spitag->read[ix].iftype) {
-+ spiinfo->read[ix] = &spitag->read[ix];
-+ }
-+ }
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spitag->write[ix].iftype) {
-+ spiinfo->write[ix] = &spitag->write[ix];
-+ }
-+ }
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spitag->erase[ix].iftype) {
-+ spiinfo->erase[ix] = &spitag->erase[ix];
-+ }
-+ }
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spitag->read[ix].iftype) {
++ spiinfo->read[ix] = &spitag->read[ix];
++ }
++ }
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spitag->write[ix].iftype) {
++ spiinfo->write[ix] = &spitag->write[ix];
++ }
++ }
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spitag->erase[ix].iftype) {
++ spiinfo->erase[ix] = &spitag->erase[ix];
++ }
++ }
+
-+ printk(KERN_NOTICE "SPI TAG: hdr.tag: 0x%08X, hdr.size: %d\n",
-+ tag->hdr.tag, tag->hdr.size);
-+ printk(KERN_NOTICE "(%dByte): 0x%02X 0x%02X 0x%02X 0x%02X "
-+ "0x%02X 0x%02X 0x%02X 0x%02X\n",
-+ spitag->id_len,
-+ spitag->id[0], spitag->id[1], spitag->id[2], spitag->id[3],
-+ spitag->id[4], spitag->id[5], spitag->id[6], spitag->id[7]);
-+ printk(KERN_NOTICE "Block:%sB ", int_to_size(spitag->erasesize));
-+ printk(KERN_NOTICE "Chip:%sB ", int_to_size(spitag->chipsize));
-+ printk(KERN_NOTICE "AddrCycle:%d ", spitag->addrcycle);
-+ printk(KERN_NOTICE "Name:(%s)", spitag->name);
-+ printk(KERN_NOTICE "\n");
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spitag->read[ix].iftype) {
-+ printk(KERN_NOTICE "R %d: ", ix + 1);
-+ printk(KERN_NOTICE "IF Type:0x%02X ",
-+ spitag->read[ix].iftype);
-+ printk(KERN_NOTICE "CMD:0x%02X ",
-+ spitag->read[ix].cmd);
-+ printk(KERN_NOTICE "Dummy:%d ",
-+ spitag->read[ix].dummy);
-+ if (spitag->read[ix].size == INFINITE) {
-+ printk(KERN_NOTICE "Size:-1 ");
-+ } else {
-+ printk(KERN_NOTICE "Size:%6sB ",
-+ int_to_size(spitag->read[ix].size));
-+ }
-+ printk(KERN_NOTICE "Clock:%dMHz ",
-+ spitag->read[ix].clock);
-+ printk(KERN_NOTICE "\n");
-+ }
-+ }
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spitag->write[ix].iftype) {
-+ printk(KERN_NOTICE "W %d: ", ix + 1);
-+ printk(KERN_NOTICE "IF Type:0x%02X ",
-+ spitag->write[ix].iftype);
-+ printk(KERN_NOTICE "CMD:0x%02X ",
-+ spitag->write[ix].cmd);
-+ printk(KERN_NOTICE "Dummy:%d ",
-+ spitag->write[ix].dummy);
-+ printk(KERN_NOTICE "Size:%6sB ",
-+ int_to_size(spitag->write[ix].size));
-+ printk(KERN_NOTICE "Clock:%dMHz ",
-+ spitag->write[ix].clock);
-+ printk(KERN_NOTICE "\n");
-+ }
-+ }
-+ for (ix = 0; ix < MAX_SPI_OP; ix++) {
-+ if (spitag->erase[ix].iftype) {
-+ printk(KERN_NOTICE "E %d: ", ix + 1);
-+ printk(KERN_NOTICE "IF Type:0x%02X ",
-+ spitag->erase[ix].iftype);
-+ printk(KERN_NOTICE "CMD:0x%02X ",
-+ spitag->erase[ix].cmd);
-+ printk(KERN_NOTICE "Dummy:%d ",
-+ spitag->erase[ix].dummy);
-+ printk(KERN_NOTICE "Size:0x%02X ",
-+ spitag->erase[ix].size);
-+ printk(KERN_NOTICE "Clock:%dMHz ",
-+ spitag->erase[ix].clock);
-+ printk(KERN_NOTICE "\n");
-+ }
-+ }
++ printk(KERN_NOTICE "SPI TAG: hdr.tag: 0x%08X, hdr.size: %d\n",
++ tag->hdr.tag, tag->hdr.size);
++ printk(KERN_NOTICE "(%dByte): 0x%02X 0x%02X 0x%02X 0x%02X "
++ "0x%02X 0x%02X 0x%02X 0x%02X\n",
++ spitag->id_len,
++ spitag->id[0], spitag->id[1], spitag->id[2], spitag->id[3],
++ spitag->id[4], spitag->id[5], spitag->id[6], spitag->id[7]);
++ printk(KERN_NOTICE "Block:%sB ", int_to_size(spitag->erasesize));
++ printk(KERN_NOTICE "Chip:%sB ", int_to_size(spitag->chipsize));
++ printk(KERN_NOTICE "AddrCycle:%d ", spitag->addrcycle);
++ printk(KERN_NOTICE "Name:(%s)", spitag->name);
++ printk(KERN_NOTICE "\n");
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spitag->read[ix].iftype) {
++ printk(KERN_NOTICE "R %d: ", ix + 1);
++ printk(KERN_NOTICE "IF Type:0x%02X ",
++ spitag->read[ix].iftype);
++ printk(KERN_NOTICE "CMD:0x%02X ",
++ spitag->read[ix].cmd);
++ printk(KERN_NOTICE "Dummy:%d ",
++ spitag->read[ix].dummy);
++ if (spitag->read[ix].size == INFINITE) {
++ printk(KERN_NOTICE "Size:-1 ");
++ } else {
++ printk(KERN_NOTICE "Size:%6sB ",
++ int_to_size(spitag->read[ix].size));
++ }
++ printk(KERN_NOTICE "Clock:%dMHz ",
++ spitag->read[ix].clock);
++ printk(KERN_NOTICE "\n");
++ }
++ }
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spitag->write[ix].iftype) {
++ printk(KERN_NOTICE "W %d: ", ix + 1);
++ printk(KERN_NOTICE "IF Type:0x%02X ",
++ spitag->write[ix].iftype);
++ printk(KERN_NOTICE "CMD:0x%02X ",
++ spitag->write[ix].cmd);
++ printk(KERN_NOTICE "Dummy:%d ",
++ spitag->write[ix].dummy);
++ printk(KERN_NOTICE "Size:%6sB ",
++ int_to_size(spitag->write[ix].size));
++ printk(KERN_NOTICE "Clock:%dMHz ",
++ spitag->write[ix].clock);
++ printk(KERN_NOTICE "\n");
++ }
++ }
++ for (ix = 0; ix < MAX_SPI_OP; ix++) {
++ if (spitag->erase[ix].iftype) {
++ printk(KERN_NOTICE "E %d: ", ix + 1);
++ printk(KERN_NOTICE "IF Type:0x%02X ",
++ spitag->erase[ix].iftype);
++ printk(KERN_NOTICE "CMD:0x%02X ",
++ spitag->erase[ix].cmd);
++ printk(KERN_NOTICE "Dummy:%d ",
++ spitag->erase[ix].dummy);
++ printk(KERN_NOTICE "Size:0x%02X ",
++ spitag->erase[ix].size);
++ printk(KERN_NOTICE "Clock:%dMHz ",
++ spitag->erase[ix].clock);
++ printk(KERN_NOTICE "\n");
++ }
++ }
+
-+ return 0;
++ return 0;
+}
+
+/* turn to ascii is "S_ID" */
@@ -311970,8 +380452,8 @@ index 0000000..acdeea7
+
+static int __init spi_ids_init(void)
+{
-+ printk(KERN_INFO "Spi id table Version %s\n", SPI_DRV_VERSION);
-+ return 0;
++ printk(KERN_INFO "Spi id table Version %s\n", SPI_DRV_VERSION);
++ return 0;
+}
+/*****************************************************************************/
+
@@ -311987,7 +380469,7 @@ index 0000000..acdeea7
+MODULE_DESCRIPTION("Spi id table");
diff --git a/drivers/mtd/spi-nor/spi_ids.h b/drivers/mtd/spi-nor/spi_ids.h
new file mode 100644
-index 0000000..d2d6fa7
+index 0000000..7a5d654
--- /dev/null
+++ b/drivers/mtd/spi-nor/spi_ids.h
@@ -0,0 +1,171 @@
@@ -312122,29 +380604,29 @@ index 0000000..d2d6fa7
+/*****************************************************************************/
+
+struct spi_operation {
-+ unsigned char iftype;
-+ unsigned char cmd;
-+ unsigned char dummy;
-+ unsigned int size;
-+ unsigned int clock;
++ unsigned char iftype;
++ unsigned char cmd;
++ unsigned char dummy;
++ unsigned int size;
++ unsigned int clock;
+};
+
+struct spi_info {
-+ char *name;
++ char *name;
+
-+ unsigned char id[8];
-+ unsigned int id_len;
++ unsigned char id[8];
++ unsigned int id_len;
+
-+ unsigned long chipsize;
-+ unsigned int erasesize;
-+ unsigned int addrcycle;
++ unsigned long chipsize;
++ unsigned int erasesize;
++ unsigned int addrcycle;
+
+#define MAX_SPI_OP (8)
-+ struct spi_operation *read[8];
-+ struct spi_operation *write[8];
-+ struct spi_operation *erase[8];
++ struct spi_operation *read[8];
++ struct spi_operation *write[8];
++ struct spi_operation *erase[8];
+#ifndef CONFIG_MTD_HISFC300
-+ struct spi_driver *driver;
++ struct spi_driver *driver;
+#endif
+};
+/*****************************************************************************/
@@ -312152,7 +380634,7 @@ index 0000000..d2d6fa7
+struct spi_info *spi_serach_ids(unsigned char ids[8]);
+
+void spi_search_rw(struct spi_info *spiinfo, struct spi_operation *spiop_rw,
-+ unsigned int iftype, unsigned int max_dummy, int is_read);
++ unsigned int iftype, unsigned int max_dummy, int is_read);
+
+#ifndef CONFIG_MTD_HISFC300
+void spi_get_erase(struct spi_info *spiinfo, struct spi_operation *spiop_erase);
@@ -312306,10 +380788,10 @@ index 0000000..e3d9c53
+hieth-gmac-objs := board.o higmac.o autoeee/autoeee.o autoeee/phy_id_table.o
diff --git a/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.c b/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.c
new file mode 100644
-index 0000000..b1a3f09
+index 0000000..9a1367b
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.c
-@@ -0,0 +1,132 @@
+@@ -0,0 +1,126 @@
+#include <linux/phy.h>
+#include <linux/micrel_phy.h>
+#include "../higmac.h"
@@ -312317,174 +380799,168 @@ index 0000000..b1a3f09
+
+void init_autoeee(struct higmac_netdev_local *ld)
+{
-+ int phy_id = ld->phy->phy_id;
-+ struct phy_info *phy_info;
++ int phy_id = ld->phy->phy_id;
++ struct phy_info *phy_info = NULL;
+
-+ if (ld->eee_init) {
-+ goto eee_init;
-+ }
++ if (ld->eee_init)
++ goto eee_init;
+
-+ phy_info = phy_search_ids(phy_id);
-+ if (phy_info) {
-+ int eee_available, lp_eee_capable, v;
-+ u32 link_stat = 0;
++ phy_info = phy_search_ids(phy_id);
++ if (phy_info) {
++ int eee_available, lp_eee_capable;
++ u32 v;
++ u32 link_stat = 0;
+
-+ eee_available = phy_info->eee_available;
-+ if (netif_msg_wol(ld)) {
-+ pr_info("fit phy_id:0x%x, phy_name:%s, eee:%d\n",
-+ phy_info->phy_id, phy_info->name,
-+ eee_available);
-+ }
-+ if (!eee_available) {
-+ goto not_support;
-+ }
++ eee_available = phy_info->eee_available;
++ if (netif_msg_wol(ld))
++ pr_info("fit phy_id:0x%x, phy_name:%s, eee:%d\n",
++ phy_info->phy_id, phy_info->name,
++ eee_available);
+
-+ if (eee_available == PHY_EEE) {
-+ if (netif_msg_wol(ld)) {
-+ pr_info("enter phy-EEE mode\n");
-+ }
++ if (!eee_available)
++ goto not_support;
+
-+ v = readl(ld->gmac_iobase + EEE_ENABLE);
-+ v &= ~BIT_EEE_ENABLE; /* disable auto-EEE */
-+ writel(v, ld->gmac_iobase + EEE_ENABLE);
-+ return;
-+ }
++ if (eee_available == PHY_EEE) {
++ if (netif_msg_wol(ld))
++ pr_info("enter phy-EEE mode\n");
+
-+ ld->eee_init = phy_info->eee_init;
++ v = readl(ld->gmac_iobase + EEE_ENABLE);
++ v &= ~BIT_EEE_ENABLE; /* disable auto-EEE */
++ writel(v, ld->gmac_iobase + EEE_ENABLE);
++ return;
++ }
++
++ ld->eee_init = phy_info->eee_init;
+eee_init:
-+ switch (ld->phy->speed) {
-+ case SPEED_10:
-+ link_stat |= HIGMAC_SPD_10M;
-+ break;
-+ case SPEED_100:
-+ link_stat |= HIGMAC_SPD_100M;
-+ break;
-+ case SPEED_1000:
-+ link_stat |= HIGMAC_SPD_1000M;
-+ break;
-+ default:
-+ break;
-+ }
++ switch (ld->phy->speed) {
++ case SPEED_10:
++ link_stat |= HIGMAC_SPD_10M;
++ break;
++ case SPEED_100:
++ link_stat |= HIGMAC_SPD_100M;
++ break;
++ case SPEED_1000:
++ link_stat |= HIGMAC_SPD_1000M;
++ break;
++ default:
++ break;
++ }
+
-+ lp_eee_capable = ld->eee_init(ld->phy);
-+ if (lp_eee_capable < 0) {
-+ return;
-+ }
++ lp_eee_capable = ld->eee_init(ld->phy);
++ if (lp_eee_capable < 0)
++ return;
+
-+ if (ld->phy->link) {
-+ if (((u32)lp_eee_capable) & link_stat) {
-+ if ((phy_id & REALTEK_PHY_MASK) ==
-+ REALTEK_PHY_ID_8211E) {
-+ v = readl(ld->gmac_iobase + EEE_CLK);
-+ v &= ~MASK_EEE_CLK;
-+ v |= BIT_DISABLE_TX_CLK;
-+ writel(v, ld->gmac_iobase + EEE_CLK);
-+ } else if ((phy_id & MICREL_PHY_ID_MASK) ==
-+ PHY_ID_KSZ9031) {
-+ v = readl(ld->gmac_iobase + EEE_CLK);
-+ v &= ~MASK_EEE_CLK;
-+ v |= (BIT_DISABLE_TX_CLK |
-+ BIT_PHY_KSZ9031);
-+ writel(v, ld->gmac_iobase + EEE_CLK);
-+ }
++ if (ld->phy->link) {
++ if (((u32)lp_eee_capable) & link_stat) {
++ if (((u32)phy_id & REALTEK_PHY_MASK) ==
++ REALTEK_PHY_ID_8211E) {
++ v = readl(ld->gmac_iobase + EEE_CLK);
++ v &= ~MASK_EEE_CLK;
++ v |= BIT_DISABLE_TX_CLK;
++ writel(v, ld->gmac_iobase + EEE_CLK);
++ } else if (((u32)phy_id & MICREL_PHY_ID_MASK) ==
++ PHY_ID_KSZ9031) {
++ v = readl(ld->gmac_iobase + EEE_CLK);
++ v &= ~MASK_EEE_CLK;
++ v |= (BIT_DISABLE_TX_CLK |
++ BIT_PHY_KSZ9031);
++ writel(v, ld->gmac_iobase + EEE_CLK);
++ }
+
-+ /* EEE_1us: 0x7c for 125M */
-+ writel(0x7c, ld->gmac_iobase +
-+ EEE_TIME_CLK_CNT);
-+ writel(0x1e0400, ld->gmac_iobase +
-+ EEE_TIMER); /* FIXME */
++ /* EEE_1us: 0x7c for 125M */
++ writel(0x7c, ld->gmac_iobase +
++ EEE_TIME_CLK_CNT);
++ writel(0x1e0400, ld->gmac_iobase +
++ EEE_TIMER);/* FIXME */
+
-+ v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
-+ v |= 0x3 << 1; /* auto EEE and ... */
-+ v |= BIT_PHY_LINK_STATUS; /* phy linkup */
-+ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
++ v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
++ v |= 0x3 << 1; /* auto EEE and ... */
++ v |= BIT_PHY_LINK_STATUS; /* phy linkup */
++ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
+
-+ v = readl(ld->gmac_iobase + EEE_ENABLE);
-+ v |= BIT_EEE_ENABLE; /* enable EEE */
-+ writel(v, ld->gmac_iobase + EEE_ENABLE);
++ v = readl(ld->gmac_iobase + EEE_ENABLE);
++ v |= BIT_EEE_ENABLE; /* enable EEE */
++ writel(v, ld->gmac_iobase + EEE_ENABLE);
+
-+ if (netif_msg_wol(ld)) {
-+ pr_info("enter auto-EEE mode\n");
-+ }
-+ } else {
-+ if (netif_msg_wol(ld)) {
-+ pr_info("link partner not support EEE\n");
-+ }
-+ }
-+ } else {
-+ v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
-+ v &= ~(BIT_PHY_LINK_STATUS); /* phy linkdown */
-+ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
-+ }
++ if (netif_msg_wol(ld))
++ pr_info("enter auto-EEE mode\n");
++ } else {
++ if (netif_msg_wol(ld))
++ pr_info("link partner not support EEE\n");
++ }
++ } else {
++ v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
++ v &= ~(BIT_PHY_LINK_STATUS); /* phy linkdown */
++ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
++ }
+
-+ return;
-+ }
++ return;
++ }
+
+not_support:
-+ ld->eee_init = NULL;
-+ if (netif_msg_wol(ld)) {
-+ pr_info("non-EEE mode\n");
-+ }
++ ld->eee_init = NULL;
++ if (netif_msg_wol(ld))
++ pr_info("non-EEE mode\n");
+}
+
+void eee_phy_linkdown(struct higmac_netdev_local *ld)
+{
-+ int v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
-+ /* update phy link state */
-+ v &= ~BIT_PHY_LINK_STATUS;
-+ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
++ u32 v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
++ /* update phy link state */
++ v &= ~BIT_PHY_LINK_STATUS;
++ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
+}
+
+void eee_phy_linkup(struct higmac_netdev_local *ld)
+{
-+ int v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
-+ /* update phy link state */
-+ v |= BIT_PHY_LINK_STATUS;
-+ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
++ u32 v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
++ /* update phy link state */
++ v |= BIT_PHY_LINK_STATUS;
++ writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
+}
diff --git a/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.h b/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.h
new file mode 100644
-index 0000000..10bdab3
+index 0000000..8f75a7a
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.h
@@ -0,0 +1,42 @@
-+#ifndef _AUTO_EEE_H
++#ifndef _AUTO_EEE_H
+
-+#define NO_EEE 0
-+#define MAC_EEE 1
-+#define PHY_EEE 2
-+#define PARTNER_EEE 2
++#define NO_EEE 0
++#define MAC_EEE 1
++#define PHY_EEE 2
++#define PARTNER_EEE 2
+
+struct phy_info {
-+ char *name;
-+ int phy_id;
-+ char eee_available; /* eee support by this phy */
-+ int (*eee_init)(struct phy_device *phy_dev);
++ char *name;
++ int phy_id;
++ char eee_available; /* eee support by this phy */
++ int (*eee_init)(struct phy_device *phy_dev);
+};
+
+/* GMAC register definition */
-+#define EEE_CLK 0x800
-+#define MASK_EEE_CLK (0x3 << 20)
-+#define BIT_DISABLE_TX_CLK BIT(21)
-+#define BIT_PHY_KSZ9031 BIT(20)
-+#define EEE_ENABLE 0x808
-+#define BIT_EEE_ENABLE BIT(0)
-+#define EEE_TIMER 0x80C
-+#define EEE_LINK_STATUS 0x810
-+#define BIT_PHY_LINK_STATUS BIT(0)
-+#define EEE_TIME_CLK_CNT 0x814
++#define EEE_CLK 0x800
++#define MASK_EEE_CLK (0x3 << 20)
++#define BIT_DISABLE_TX_CLK BIT(21)
++#define BIT_PHY_KSZ9031 BIT(20)
++#define EEE_ENABLE 0x808
++#define BIT_EEE_ENABLE BIT(0)
++#define EEE_TIMER 0x80C
++#define EEE_LINK_STATUS 0x810
++#define BIT_PHY_LINK_STATUS BIT(0)
++#define EEE_TIME_CLK_CNT 0x814
+
-+/* ----------------------------phy register------------------------------- */
++/* ----------------------------phy register-------------------------------*/
+/* MMD: MDIO Manageable Device */
-+#define MACR 0x0D
-+#define MAADR 0x0E
-+#define EEE_DEV 0x3
-+#define EEE_CAPABILITY 0x14
-+#define EEELPAR_DEV 0x7
-+#define EEELPAR 0x3D /* EEE link partner ability register */
-+#define EEE_ADVERTISE 0x3c
-+#define LP_1000BASE_EEE BIT(2)
-+#define LP_100BASE_EEE BIT(1)
++#define MACR 0x0D
++#define MAADR 0x0E
++#define EEE_DEV 0x3
++#define EEE_CAPABILITY 0x14
++#define EEELPAR_DEV 0x7
++#define EEELPAR 0x3D /* EEE link partner ability register */
++#define EEE_ADVERTISE 0x3c
++#define LP_1000BASE_EEE BIT(2)
++#define LP_100BASE_EEE BIT(1)
+
+struct phy_info *phy_search_ids(int phy_id);
+void init_autoeee(struct higmac_netdev_local *ld);
@@ -312492,10 +380968,10 @@ index 0000000..10bdab3
+#endif
diff --git a/drivers/net/ethernet/hisilicon/higmac/autoeee/phy_id_table.c b/drivers/net/ethernet/hisilicon/higmac/autoeee/phy_id_table.c
new file mode 100644
-index 0000000..0ee92c9
+index 0000000..f45276d
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/autoeee/phy_id_table.c
-@@ -0,0 +1,190 @@
+@@ -0,0 +1,180 @@
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/phy.h>
@@ -312506,192 +380982,182 @@ index 0000000..0ee92c9
+
+struct phy_info *phy_search_ids(int phy_id)
+{
-+ int i;
-+ struct phy_info *fit_info = NULL;
++ int i;
++ struct phy_info *fit_info = NULL;
+
-+ for (i = 0; phy_info_table[i].name; i++) {
-+ if (phy_id == phy_info_table[i].phy_id) {
-+ fit_info = &phy_info_table[i];
-+ }
-+ }
++ for (i = 0; phy_info_table[i].name; i++) {
++ if (phy_id == phy_info_table[i].phy_id)
++ fit_info = &phy_info_table[i];
++ }
+
-+ return fit_info;
++ return fit_info;
+}
+
+static inline int phy_mmd_read(struct phy_device *phy_dev,
-+ u32 mmd_device, u32 regnum)
++ u32 mmd_device, u32 regnum)
+{
-+ phy_write(phy_dev, MACR, mmd_device); /* function = 00 address */
-+ phy_write(phy_dev, MAADR, regnum);
-+ phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
++ phy_write(phy_dev, MACR, mmd_device); /* function = 00 address */
++ phy_write(phy_dev, MAADR, regnum);
++ phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
+
-+ return phy_read(phy_dev, MAADR);
++ return phy_read(phy_dev, MAADR);
+}
+
+static inline int phy_mmd_write(struct phy_device *phy_dev, u32 mmd_device,
-+ u32 regnum, u16 val)
++ u32 regnum, u16 val)
+{
-+ phy_write(phy_dev, MACR, mmd_device); /* function = 00 address */
-+ phy_write(phy_dev, MAADR, regnum);
-+ phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
++ phy_write(phy_dev, MACR, mmd_device); /* function = 00 address */
++ phy_write(phy_dev, MAADR, regnum);
++ phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
+
-+ return phy_write(phy_dev, MAADR, val);
++ return phy_write(phy_dev, MAADR, val);
+}
+
+static int smsc_lan8740_init(struct phy_device *phy_dev)
+{
-+ static int first_time;
-+ int v, eee_type = 0;
++ static int first_time;
++ int v;
++ u32 eee_type = 0;
+
-+ if (!first_time) {
-+ /* Realtek LAN 8740 start to enable eee */
-+ int eee_lan;
++ if (!first_time) {
++ /* Realtek LAN 8740 start to enable eee */
++ int eee_lan;
+
-+ eee_lan = phy_read(phy_dev, 0x10);
-+ if (eee_lan < 0) {
-+ return eee_lan;
-+ }
-+ eee_lan |= 0x4;
-+ phy_write(phy_dev, 0x10, eee_lan);
-+ eee_lan = phy_read(phy_dev, 0x10);
-+ if (eee_lan < 0) {
-+ return eee_lan;
-+ }
-+ /* auto negotiate after enable eee */
-+ eee_lan = phy_read(phy_dev, 0x0);
-+ if (eee_lan < 0) {
-+ return eee_lan;
-+ }
-+ eee_lan |= 0x200;
-+ phy_write(phy_dev, 0x0, eee_lan);
-+ first_time = 1;
-+ }
++ eee_lan = phy_read(phy_dev, 0x10);
++ if (eee_lan < 0)
++ return eee_lan;
++ eee_lan = (u32)eee_lan | 0x4;
++ phy_write(phy_dev, 0x10, eee_lan);
++ eee_lan = phy_read(phy_dev, 0x10);
++ if (eee_lan < 0)
++ return eee_lan;
++ /* auto negotiate after enable eee */
++ eee_lan = phy_read(phy_dev, 0x0);
++ if (eee_lan < 0)
++ return eee_lan;
++ eee_lan = (u32)eee_lan | 0x200;
++ phy_write(phy_dev, 0x0, eee_lan);
++ first_time = 1;
++ }
+
-+ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
+
-+ if (v & LP_1000BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_1000M;
-+ }
-+ if (v & LP_100BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_100M;
-+ }
++ if ((u32)v & LP_1000BASE_EEE)
++ eee_type |= HIGMAC_SPD_1000M;
++ if ((u32)v & LP_100BASE_EEE)
++ eee_type |= HIGMAC_SPD_100M;
+
-+ return eee_type;
++ return (int)eee_type;
+}
+
-+#define RTL8211EG_MAC 0
++#define RTL8211EG_MAC 0
+#if RTL8211EG_MAC
+static int rtl8211EG_mac_init(struct phy_device *phy_dev)
+{
-+ static int first_time;
-+ /* Realtek 8211EG start reset to change eee to mac */
-+ int v, eee_type = 0;
++ static int first_time;
++ /* Realtek 8211EG start reset to change eee to mac */
++ int v;
++ u32 eee_type = 0;
+
-+ if (!first_time) {
-+ int tmp = 0;
++ if (!first_time) {
++ int tmp = 0;
+
-+ phy_write(phy_dev, 0x1f, 0x0);
-+ phy_write(phy_dev, MII_BMCR, BMCR_RESET); /* reset phy */
-+ do { /* wait phy restart over */
-+ udelay(1);
-+ tmp = phy_read(phy_dev, MII_BMSR);
-+ /* no need to wait AN finished */
-+ tmp &= (BMSR_ANEGCOMPLETE | BMSR_ANEGCAPABLE);
-+ } while (!tmp);
++ phy_write(phy_dev, 0x1f, 0x0);
++ phy_write(phy_dev, MII_BMCR, BMCR_RESET); /* reset phy */
++ do { /* wait phy restart over */
++ udelay(1);
++ tmp = phy_read(phy_dev, MII_BMSR);
++ /* no need to wait AN finished */
++ tmp &= (BMSR_ANEGCOMPLETE | BMSR_ANEGCAPABLE);
++ } while (!tmp);
+
-+ phy_write(phy_dev, 0x1f, 0x7);
-+ phy_write(phy_dev, 0x1e, 0x20);
-+ phy_write(phy_dev, 0x1b, 0xa03a);
-+ phy_write(phy_dev, 0x1f, 0x0);
++ phy_write(phy_dev, 0x1f, 0x7);
++ phy_write(phy_dev, 0x1e, 0x20);
++ phy_write(phy_dev, 0x1b, 0xa03a);
++ phy_write(phy_dev, 0x1f, 0x0);
+
-+ first_time = 1;
-+ }
++ first_time = 1;
++ }
+
-+ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
+
-+ if (v & LP_1000BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_1000M;
-+ }
-+ if (v & LP_100BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_100M;
-+ }
++ if ((u32)v & LP_1000BASE_EEE)
++ eee_type |= HIGMAC_SPD_1000M;
++ if ((u32)v & LP_100BASE_EEE)
++ eee_type |= HIGMAC_SPD_100M;
+
-+ return eee_type;
++ return (int)eee_type;
+}
+#else
+static int rtl8211EG_init(struct phy_device *phy_dev)
+{
-+ int eee_type = 0, v;
++ u32 eee_type = 0;
++ u32 v;
++ v = (u32)phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
+
-+ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
++ if (v & LP_1000BASE_EEE)
++ eee_type |= HIGMAC_SPD_1000M;
++ if (v & LP_100BASE_EEE)
++ eee_type |= HIGMAC_SPD_100M;
+
-+ if (v & LP_1000BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_1000M;
-+ }
-+ if (v & LP_100BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_100M;
-+ }
-+
-+ return eee_type;
++ return (int)eee_type;
+}
+#endif
+
+static int festa_v200_init(struct phy_device *phy_dev)
+{
-+ static int first_time_init;
-+ int v, eee_type = 0;
++ static int first_time_init;
++ int v;
++ u32 eee_type = 0;
+
-+ if (!first_time_init) {
-+ /* EEE_CAPABILITY register: support 100M-BaseT */
-+ v = phy_mmd_read(phy_dev, EEE_DEV, EEE_CAPABILITY);
-+ phy_mmd_write(phy_dev, EEE_DEV, EEE_CAPABILITY,
-+ ((u32)v) | BIT(1));
++ if (!first_time_init) {
++ /* EEE_CAPABILITY register: support 100M-BaseT */
++ v = phy_mmd_read(phy_dev, EEE_DEV, EEE_CAPABILITY);
++ phy_mmd_write(phy_dev, EEE_DEV, EEE_CAPABILITY,
++ ((u32)v) | BIT(1));
+
-+ /* EEE_ADVERTISEMENT register: advertising 100M-BaseT */
-+ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEE_ADVERTISE);
-+ phy_mmd_write(phy_dev, EEELPAR_DEV, EEE_ADVERTISE,
-+ ((u32)v) | BIT(1));
++ /* EEE_ADVERTISEMENT register: advertising 100M-BaseT */
++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEE_ADVERTISE);
++ phy_mmd_write(phy_dev, EEELPAR_DEV, EEE_ADVERTISE,
++ ((u32)v) | BIT(1));
+
-+ v = phy_read(phy_dev, MII_BMCR);
-+ if (v < 0) {
-+ return v;
-+ }
-+ v |= (BMCR_ANENABLE | BMCR_ANRESTART);
-+ phy_write(phy_dev, MII_BMCR, v); /* auto-neg restart */
++ v = phy_read(phy_dev, MII_BMCR);
++ if (v < 0)
++ return v;
++ v = (u32)v | (BMCR_ANENABLE | BMCR_ANRESTART);
++ phy_write(phy_dev, MII_BMCR, v); /* auto-neg restart */
+
-+ first_time_init = 1;
-+ }
++ first_time_init = 1;
++ }
+
-+ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR);
+
-+ if (v & LP_1000BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_1000M;
-+ }
-+ if (v & LP_100BASE_EEE) {
-+ eee_type |= HIGMAC_SPD_100M;
-+ }
++ if ((u32)v & LP_1000BASE_EEE)
++ eee_type |= HIGMAC_SPD_1000M;
++ if ((u32)v & LP_100BASE_EEE)
++ eee_type |= HIGMAC_SPD_100M;
+
-+ return eee_type;
++ return (int)eee_type;
+}
+
+struct phy_info phy_info_table[] = {
-+ /* phy_name phy_id eee_available phy_driver */
-+ /* SMSC */
-+ { "SMSC LAN8740", 0x0007c110, MAC_EEE, &smsc_lan8740_init },
-+ /* Realtek */
++ /* phy_name phy_id eee_available phy_driver */
++/* SMSC */
++ {"SMSC LAN8740", 0x0007c110, MAC_EEE, &smsc_lan8740_init},
++/* Realtek */
+#if RTL8211EG_MAC
-+ { "Realtek 8211EG", 0x001cc915, MAC_EEE, &rtl8211EG_mac_init },
++ {"Realtek 8211EG", 0x001cc915, MAC_EEE, &rtl8211EG_mac_init},
+#else
-+ { "Realtek 8211EG", 0x001cc915, PHY_EEE, &rtl8211EG_init },
++ {"Realtek 8211EG", 0x001cc915, PHY_EEE, &rtl8211EG_init},
+#endif
-+ { "Festa V200", HISILICON_PHY_ID_FESTAV200, MAC_EEE, &festa_v200_init },
++ {"Festa V200", HISILICON_PHY_ID_FESTAV200, MAC_EEE, &festa_v200_init},
+};
diff --git a/drivers/net/ethernet/hisilicon/higmac/board.c b/drivers/net/ethernet/hisilicon/higmac/board.c
new file mode 100644
-index 0000000..6b37ab4
+index 0000000..89b9d16
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/board.c
-@@ -0,0 +1,103 @@
+@@ -0,0 +1,96 @@
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/reset.h>
@@ -312699,15 +381165,15 @@ index 0000000..6b37ab4
+
+void higmac_mac_core_reset(struct higmac_netdev_local *priv)
+{
-+ /* undo reset */
-+ reset_control_deassert(priv->port_rst);
-+ usleep_range(50, 60);
++ /* undo reset */
++ reset_control_deassert(priv->port_rst);
++ usleep_range(50, 60);
+
-+ /* soft reset mac port */
-+ reset_control_assert(priv->port_rst);
-+ usleep_range(50, 60);
-+ /* undo reset */
-+ reset_control_deassert(priv->port_rst);
++ /* soft reset mac port */
++ reset_control_assert(priv->port_rst);
++ usleep_range(50, 60);
++ /* undo reset */
++ reset_control_deassert(priv->port_rst);
+}
+
+void higmac_hw_internal_phy_reset(struct higmac_netdev_local *priv)
@@ -312716,34 +381182,33 @@ index 0000000..6b37ab4
+
+void higmac_hw_phy_reset(struct higmac_netdev_local *priv)
+{
-+ if (priv->internal_phy) {
-+ higmac_hw_internal_phy_reset(priv);
-+ } else {
-+ higmac_hw_external_phy_reset(priv);
-+ }
++ if (priv->internal_phy)
++ higmac_hw_internal_phy_reset(priv);
++ else
++ higmac_hw_external_phy_reset(priv);
+}
+
+void higmac_hw_external_phy_reset(struct higmac_netdev_local *priv)
+{
-+ if (priv->phy_rst) {
-+ /* write 0 to cancel reset */
-+ reset_control_deassert(priv->phy_rst);
-+ msleep(50);
++ if (priv->phy_rst) {
++ /* write 0 to cancel reset */
++ reset_control_deassert(priv->phy_rst);
++ msleep(50);
+
-+ /* HIFONE or 98cv200 use CRG register to reset phy */
-+ /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */
-+ reset_control_assert(priv->phy_rst);
++ /* HIFONE or 98cv200 use CRG register to reset phy */
++ /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */
++ reset_control_assert(priv->phy_rst);
+
-+ /* delay some time to ensure reset ok,
-+ * this depends on PHY hardware feature
-+ */
-+ msleep(50);
++ /* delay some time to ensure reset ok,
++ * this depends on PHY hardware feature
++ */
++ msleep(50);
+
-+ /* write 0 to cancel reset */
-+ reset_control_deassert(priv->phy_rst);
-+ /* delay some time to ensure later MDIO access */
-+ msleep(50);
-+ }
++ /* write 0 to cancel reset */
++ reset_control_deassert(priv->phy_rst);
++ /* delay some time to ensure later MDIO access */
++ msleep(50);
++ }
+}
+
+void higmac_internal_phy_clk_disable(struct higmac_netdev_local *priv)
@@ -312756,51 +381221,45 @@ index 0000000..6b37ab4
+
+void higmac_hw_all_clk_disable(struct higmac_netdev_local *priv)
+{
-+ /* If macif clock is enabled when suspend, we should
-+ * disable it here.
-+ * Because when resume, PHY will link up again and
-+ * macif clock will be enabled too. If we don't disable
-+ * macif clock in suspend, macif clock will be enabled twice.
-+ */
-+ if (priv->netdev->flags & IFF_UP) {
-+ clk_disable_unprepare(priv->macif_clk);
-+ }
++ /* If macif clock is enabled when suspend, we should
++ * disable it here.
++ * Because when resume, PHY will link up again and
++ * macif clock will be enabled too. If we don't disable
++ * macif clock in suspend, macif clock will be enabled twice.
++ */
++ if (priv->netdev->flags & IFF_UP)
++ clk_disable_unprepare(priv->macif_clk);
+
-+ /* This is called in suspend, when net device is down,
-+ * MAC clk is disabled.
-+ * So we need to judge whether MAC clk is enabled,
-+ * otherwise kernel will WARNING if clk disable twice.
-+ */
-+ if (priv->netdev->flags & IFF_UP) {
-+ clk_disable_unprepare(priv->clk);
-+ }
++ /* This is called in suspend, when net device is down,
++ * MAC clk is disabled.
++ * So we need to judge whether MAC clk is enabled,
++ * otherwise kernel will WARNING if clk disable twice.
++ */
++ if (priv->netdev->flags & IFF_UP)
++ clk_disable_unprepare(priv->clk);
+
-+ if (priv->internal_phy) {
-+ higmac_internal_phy_clk_disable(priv);
-+ }
++ if (priv->internal_phy)
++ higmac_internal_phy_clk_disable(priv);
+}
+
+void higmac_hw_all_clk_enable(struct higmac_netdev_local *priv)
+{
-+ if (priv->internal_phy) {
-+ higmac_internal_phy_clk_enable(priv);
-+ }
++ if (priv->internal_phy)
++ higmac_internal_phy_clk_enable(priv);
+
-+ if (priv->netdev->flags & IFF_UP) {
-+ clk_prepare_enable(priv->macif_clk);
-+ }
++ if (priv->netdev->flags & IFF_UP)
++ clk_prepare_enable(priv->macif_clk);
+
-+ /* If net device is down when suspend, we should not enable MAC clk. */
-+ if (priv->netdev->flags & IFF_UP) {
-+ clk_prepare_enable(priv->clk);
-+ }
++ /* If net device is down when suspend, we should not enable MAC clk. */
++ if (priv->netdev->flags & IFF_UP)
++ clk_prepare_enable(priv->clk);
+}
diff --git a/drivers/net/ethernet/hisilicon/higmac/higmac.c b/drivers/net/ethernet/hisilicon/higmac/higmac.c
new file mode 100644
-index 0000000..5d172c3
+index 0000000..762d599
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/higmac.c
-@@ -0,0 +1,3457 @@
+@@ -0,0 +1,3307 @@
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
@@ -312841,25 +381300,25 @@ index 0000000..5d172c3
+#include "autoeee/autoeee.h"
+#include "sockioctl.h"
+
-+#define HAS_TSO_CAP(hw_cap) ((((hw_cap) >> 28) & 0x3) == VER_TSO)
-+#define HAS_RXHASH_CAP(hw_cap) ((hw_cap) & BIT(30))
-+#define HAS_RSS_CAP(hw_cap) ((hw_cap) & BIT(31))
++#define HAS_TSO_CAP(hw_cap) ((((hw_cap) >> 28) & 0x3) == VER_TSO)
++#define HAS_RXHASH_CAP(hw_cap) ((hw_cap) & BIT(30))
++#define HAS_RSS_CAP(hw_cap) ((hw_cap) & BIT(31))
+
-+#define RGMII_SPEED_1000 0x2c
-+#define RGMII_SPEED_100 0x2f
-+#define RGMII_SPEED_10 0x2d
-+#define MII_SPEED_100 0x0f
-+#define MII_SPEED_10 0x0d
-+#define RMII_SPEED_100 0x8f
-+#define RMII_SPEED_10 0x8d
-+#define GMAC_FULL_DUPLEX BIT(4)
++#define RGMII_SPEED_1000 0x2c
++#define RGMII_SPEED_100 0x2f
++#define RGMII_SPEED_10 0x2d
++#define MII_SPEED_100 0x0f
++#define MII_SPEED_10 0x0d
++#define RMII_SPEED_100 0x8f
++#define RMII_SPEED_10 0x8d
++#define GMAC_FULL_DUPLEX BIT(4)
+
+static unsigned int flow_ctrl_en = FLOW_OFF;
+static int tx_flow_ctrl_pause_time = CONFIG_TX_FLOW_CTRL_PAUSE_TIME;
+static int tx_flow_ctrl_pause_interval = CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL;
+static int tx_flow_ctrl_active_threshold = CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD;
+static int tx_flow_ctrl_deactive_threshold =
-+ CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD;
++ CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD;
+
+#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
+static int debug = -1;
@@ -312868,489 +381327,478 @@ index 0000000..5d172c3
+
+static void higmac_config_port(struct net_device *dev, u32 speed, u32 duplex)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(dev);
-+ u32 val;
++ struct higmac_netdev_local *priv = netdev_priv(dev);
++ u32 val;
+
-+ switch (priv->phy_mode) {
-+ case PHY_INTERFACE_MODE_RGMII:
-+ if (speed == SPEED_1000) {
-+ val = RGMII_SPEED_1000;
-+ } else if (speed == SPEED_100) {
-+ val = RGMII_SPEED_100;
-+ } else {
-+ val = RGMII_SPEED_10;
-+ }
-+ break;
-+ case PHY_INTERFACE_MODE_MII:
-+ if (speed == SPEED_100) {
-+ val = MII_SPEED_100;
-+ } else {
-+ val = MII_SPEED_10;
-+ }
-+ break;
-+ case PHY_INTERFACE_MODE_RMII:
-+ if (speed == SPEED_100) {
-+ val = RMII_SPEED_100;
-+ } else {
-+ val = RMII_SPEED_10;
-+ }
-+ break;
-+ default:
-+ netdev_warn(dev, "not supported mode\n");
-+ val = MII_SPEED_10;
-+ break;
-+ }
++ switch (priv->phy_mode) {
++ case PHY_INTERFACE_MODE_RGMII:
++ if (speed == SPEED_1000)
++ val = RGMII_SPEED_1000;
++ else if (speed == SPEED_100)
++ val = RGMII_SPEED_100;
++ else
++ val = RGMII_SPEED_10;
++ break;
++ case PHY_INTERFACE_MODE_MII:
++ if (speed == SPEED_100)
++ val = MII_SPEED_100;
++ else
++ val = MII_SPEED_10;
++ break;
++ case PHY_INTERFACE_MODE_RMII:
++ if (speed == SPEED_100)
++ val = RMII_SPEED_100;
++ else
++ val = RMII_SPEED_10;
++ break;
++ default:
++ netdev_warn(dev, "not supported mode\n");
++ val = MII_SPEED_10;
++ break;
++ }
+
-+ if (duplex) {
-+ val |= GMAC_FULL_DUPLEX;
-+ }
++ if (duplex)
++ val |= GMAC_FULL_DUPLEX;
+
-+ reset_control_assert(priv->macif_rst);
-+ writel_relaxed(val, priv->macif_base);
-+ reset_control_deassert(priv->macif_rst);
++ reset_control_assert(priv->macif_rst);
++ writel_relaxed(val, priv->macif_base);
++ reset_control_deassert(priv->macif_rst);
+
-+ writel_relaxed(BIT_MODE_CHANGE_EN, priv->gmac_iobase + MODE_CHANGE_EN);
-+ if (speed == SPEED_1000) {
-+ val = GMAC_SPEED_1000;
-+ } else if (speed == SPEED_100) {
-+ val = GMAC_SPEED_100;
-+ } else {
-+ val = GMAC_SPEED_10;
-+ }
-+ writel_relaxed(val, priv->gmac_iobase + PORT_MODE);
-+ writel_relaxed(0, priv->gmac_iobase + MODE_CHANGE_EN);
-+ writel_relaxed(duplex, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL);
++ writel_relaxed(BIT_MODE_CHANGE_EN, priv->gmac_iobase + MODE_CHANGE_EN);
++ if (speed == SPEED_1000)
++ val = GMAC_SPEED_1000;
++ else if (speed == SPEED_100)
++ val = GMAC_SPEED_100;
++ else
++ val = GMAC_SPEED_10;
++ writel_relaxed(val, priv->gmac_iobase + PORT_MODE);
++ writel_relaxed(0, priv->gmac_iobase + MODE_CHANGE_EN);
++ writel_relaxed(duplex, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL);
+}
+
+static void higmac_set_desc_depth(struct higmac_netdev_local *priv,
-+ u32 rx, u32 tx)
++ u32 rx, u32 tx)
+{
-+ u32 reg;
-+ int i;
-+ u32 val;
++ u32 reg;
++ int i;
++ u32 val;
+
-+ writel(BITS_RX_FQ_DEPTH_EN, priv->gmac_iobase + RX_FQ_REG_EN);
-+ val = readl(priv->gmac_iobase + RX_FQ_DEPTH);
-+ val &= ~Q_ADDR_HI8_MASK;
-+ val |= rx << DESC_WORD_SHIFT;
-+ writel(val, priv->gmac_iobase + RX_FQ_DEPTH);
-+ writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
++ writel(BITS_RX_FQ_DEPTH_EN, priv->gmac_iobase + RX_FQ_REG_EN);
++ val = readl(priv->gmac_iobase + RX_FQ_DEPTH);
++ val &= ~Q_ADDR_HI8_MASK;
++ val |= rx << DESC_WORD_SHIFT;
++ writel(val, priv->gmac_iobase + RX_FQ_DEPTH);
++ writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
+
-+ writel(BITS_RX_BQ_DEPTH_EN, priv->gmac_iobase + RX_BQ_REG_EN);
-+ val = readl(priv->gmac_iobase + RX_BQ_DEPTH);
-+ val &= ~Q_ADDR_HI8_MASK;
-+ val |= rx << DESC_WORD_SHIFT;
-+ writel(val, priv->gmac_iobase + RX_BQ_DEPTH);
-+ for (i = 1; i < priv->num_rxqs; i++) {
-+ reg = RX_BQ_DEPTH_QUEUE(i);
-+ val = readl(priv->gmac_iobase + reg);
-+ val &= ~Q_ADDR_HI8_MASK;
-+ val |= rx << DESC_WORD_SHIFT;
-+ writel(val, priv->gmac_iobase + reg);
-+ }
-+ writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
++ writel(BITS_RX_BQ_DEPTH_EN, priv->gmac_iobase + RX_BQ_REG_EN);
++ val = readl(priv->gmac_iobase + RX_BQ_DEPTH);
++ val &= ~Q_ADDR_HI8_MASK;
++ val |= rx << DESC_WORD_SHIFT;
++ writel(val, priv->gmac_iobase + RX_BQ_DEPTH);
++ for (i = 1; i < priv->num_rxqs; i++) {
++ reg = RX_BQ_DEPTH_QUEUE(i);
++ val = readl(priv->gmac_iobase + reg);
++ val &= ~Q_ADDR_HI8_MASK;
++ val |= rx << DESC_WORD_SHIFT;
++ writel(val, priv->gmac_iobase + reg);
++ }
++ writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
+
-+ writel(BITS_TX_BQ_DEPTH_EN, priv->gmac_iobase + TX_BQ_REG_EN);
-+ val = readl(priv->gmac_iobase + TX_BQ_DEPTH);
-+ val &= ~Q_ADDR_HI8_MASK;
-+ val |= tx << DESC_WORD_SHIFT;
-+ writel(val, priv->gmac_iobase + TX_BQ_DEPTH);
-+ writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
++ writel(BITS_TX_BQ_DEPTH_EN, priv->gmac_iobase + TX_BQ_REG_EN);
++ val = readl(priv->gmac_iobase + TX_BQ_DEPTH);
++ val &= ~Q_ADDR_HI8_MASK;
++ val |= tx << DESC_WORD_SHIFT;
++ writel(val, priv->gmac_iobase + TX_BQ_DEPTH);
++ writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
+
-+ writel(BITS_TX_RQ_DEPTH_EN, priv->gmac_iobase + TX_RQ_REG_EN);
-+ val = readl(priv->gmac_iobase + TX_RQ_DEPTH);
-+ val &= ~Q_ADDR_HI8_MASK;
-+ val |= tx << DESC_WORD_SHIFT;
-+ writel(val, priv->gmac_iobase + TX_RQ_DEPTH);
-+ writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
++ writel(BITS_TX_RQ_DEPTH_EN, priv->gmac_iobase + TX_RQ_REG_EN);
++ val = readl(priv->gmac_iobase + TX_RQ_DEPTH);
++ val &= ~Q_ADDR_HI8_MASK;
++ val |= tx << DESC_WORD_SHIFT;
++ writel(val, priv->gmac_iobase + TX_RQ_DEPTH);
++ writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
+}
+
+static void higmac_set_rx_fq(struct higmac_netdev_local *priv,
-+ dma_addr_t phy_addr)
++ dma_addr_t phy_addr)
+{
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ u32 val;
++ u32 val;
+#endif
-+ writel(BITS_RX_FQ_START_ADDR_EN, priv->gmac_iobase + RX_FQ_REG_EN);
++ writel(BITS_RX_FQ_START_ADDR_EN, priv->gmac_iobase + RX_FQ_REG_EN);
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ val = readl(priv->gmac_iobase + RX_FQ_DEPTH);
-+ val &= Q_ADDR_HI8_MASK;
-+ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
-+ writel(val, priv->gmac_iobase + RX_FQ_DEPTH);
++ val = readl(priv->gmac_iobase + RX_FQ_DEPTH);
++ val &= Q_ADDR_HI8_MASK;
++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
++ writel(val, priv->gmac_iobase + RX_FQ_DEPTH);
+#endif
-+ writel((u32)phy_addr, priv->gmac_iobase + RX_FQ_START_ADDR);
-+ writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
++ writel((u32)phy_addr, priv->gmac_iobase + RX_FQ_START_ADDR);
++ writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
+}
+
+static void higmac_set_rx_bq(struct higmac_netdev_local *priv,
-+ dma_addr_t phy_addr)
++ dma_addr_t phy_addr)
+{
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ u32 val;
++ u32 val;
+#endif
-+ writel(BITS_RX_BQ_START_ADDR_EN, priv->gmac_iobase + RX_BQ_REG_EN);
++ writel(BITS_RX_BQ_START_ADDR_EN, priv->gmac_iobase + RX_BQ_REG_EN);
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ val = readl(priv->gmac_iobase + RX_BQ_DEPTH);
-+ val &= Q_ADDR_HI8_MASK;
-+ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
-+ writel(val, priv->gmac_iobase + RX_BQ_DEPTH);
++ val = readl(priv->gmac_iobase + RX_BQ_DEPTH);
++ val &= Q_ADDR_HI8_MASK;
++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
++ writel(val, priv->gmac_iobase + RX_BQ_DEPTH);
+#endif
-+ writel((u32)phy_addr, priv->gmac_iobase + RX_BQ_START_ADDR);
-+ writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
++ writel((u32)phy_addr, priv->gmac_iobase + RX_BQ_START_ADDR);
++ writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
+}
+
+static void higmac_set_tx_bq(struct higmac_netdev_local *priv,
-+ dma_addr_t phy_addr)
++ dma_addr_t phy_addr)
+{
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ u32 val;
++ u32 val;
+#endif
-+ writel(BITS_TX_BQ_START_ADDR_EN, priv->gmac_iobase + TX_BQ_REG_EN);
++ writel(BITS_TX_BQ_START_ADDR_EN, priv->gmac_iobase + TX_BQ_REG_EN);
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ val = readl(priv->gmac_iobase + TX_BQ_DEPTH);
-+ val &= Q_ADDR_HI8_MASK;
-+ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
-+ writel(val, priv->gmac_iobase + TX_BQ_DEPTH);
++ val = readl(priv->gmac_iobase + TX_BQ_DEPTH);
++ val &= Q_ADDR_HI8_MASK;
++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
++ writel(val, priv->gmac_iobase + TX_BQ_DEPTH);
+#endif
-+ writel((u32)phy_addr, priv->gmac_iobase + TX_BQ_START_ADDR);
-+ writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
++ writel((u32)phy_addr, priv->gmac_iobase + TX_BQ_START_ADDR);
++ writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
+}
+
+static void higmac_set_tx_rq(struct higmac_netdev_local *priv,
-+ dma_addr_t phy_addr)
++ dma_addr_t phy_addr)
+{
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ u32 val;
++ u32 val;
+#endif
-+ writel(BITS_TX_RQ_START_ADDR_EN, priv->gmac_iobase + TX_RQ_REG_EN);
++ writel(BITS_TX_RQ_START_ADDR_EN, priv->gmac_iobase + TX_RQ_REG_EN);
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ val = readl(priv->gmac_iobase + TX_RQ_DEPTH);
-+ val &= Q_ADDR_HI8_MASK;
-+ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
-+ writel(val, priv->gmac_iobase + TX_RQ_DEPTH);
++ val = readl(priv->gmac_iobase + TX_RQ_DEPTH);
++ val &= Q_ADDR_HI8_MASK;
++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
++ writel(val, priv->gmac_iobase + TX_RQ_DEPTH);
+#endif
-+ writel((u32)phy_addr, priv->gmac_iobase + TX_RQ_START_ADDR);
-+ writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
++ writel((u32)phy_addr, priv->gmac_iobase + TX_RQ_START_ADDR);
++ writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
+}
+
+static void higmac_hw_set_desc_addr(struct higmac_netdev_local *priv)
+{
-+ u32 reg;
-+ int i;
++ u32 reg;
++ int i;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ u32 val;
++ u32 val;
+#endif
+
-+ higmac_set_rx_fq(priv, priv->rx_fq.phys_addr);
-+ higmac_set_rx_bq(priv, priv->rx_bq.phys_addr);
-+ higmac_set_tx_rq(priv, priv->tx_rq.phys_addr);
-+ higmac_set_tx_bq(priv, priv->tx_bq.phys_addr);
++ higmac_set_rx_fq(priv, priv->rx_fq.phys_addr);
++ higmac_set_rx_bq(priv, priv->rx_bq.phys_addr);
++ higmac_set_tx_rq(priv, priv->tx_rq.phys_addr);
++ higmac_set_tx_bq(priv, priv->tx_bq.phys_addr);
+
-+ for (i = 1; i < priv->num_rxqs; i++) {
-+ reg = RX_BQ_START_ADDR_QUEUE(i);
-+ writel(BITS_RX_BQ_START_ADDR_EN,
-+ priv->gmac_iobase + RX_BQ_REG_EN);
++ for (i = 1; i < priv->num_rxqs; i++) {
++ reg = RX_BQ_START_ADDR_QUEUE(i);
++ writel(BITS_RX_BQ_START_ADDR_EN,
++ priv->gmac_iobase + RX_BQ_REG_EN);
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ val = readl(priv->gmac_iobase + reg);
-+ val &= Q_ADDR_HI8_MASK;
-+ val |= ((priv->pool[3 + i].phys_addr) >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
-+ writel(val, priv->gmac_iobase + reg);
++ val = readl(priv->gmac_iobase + reg);
++ val &= Q_ADDR_HI8_MASK;
++ val |= ((priv->pool[3 + i].phys_addr) >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET;
++ writel(val, priv->gmac_iobase + reg);
+#endif
-+ writel((u32)(priv->pool[3 + i].phys_addr), priv->gmac_iobase + reg);
-+ writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
-+ }
++ writel((u32)(priv->pool[3 + i].phys_addr), priv->gmac_iobase + reg);
++ writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
++ }
+}
+
+static void higmac_set_rss_cap(struct higmac_netdev_local *priv)
+{
-+ u32 val = 0;
++ u32 val = 0;
+
-+ if (priv->has_rxhash_cap) {
-+ val |= BIT_RXHASH_CAP;
-+ }
-+ if (priv->has_rss_cap) {
-+ val |= BIT_RSS_CAP;
-+ }
-+ writel(val, priv->gmac_iobase + HW_CAP_EN);
++ if (priv->has_rxhash_cap)
++ val |= BIT_RXHASH_CAP;
++ if (priv->has_rss_cap)
++ val |= BIT_RSS_CAP;
++ writel(val, priv->gmac_iobase + HW_CAP_EN);
+}
+
+/* config AXI bus burst and outstanding for better performance */
+static void higmac_axi_bus_cfg(struct higmac_netdev_local *priv)
+{
-+ if (!priv->axi_bus_cfg_base) {
-+ return;
-+ }
++ if (!priv->axi_bus_cfg_base)
++ return;
+
-+#if defined(CONFIG_ARCH_HI3519) || defined(CONFIG_ARCH_HI3519V101) || \
-+ defined(CONFIG_ARCH_HI3559) || defined(CONFIG_ARCH_HI3556) || \
-+ defined(CONFIG_ARCH_HI3516AV200)
-+ if (!(readl(priv->axi_bus_cfg_base) >> BURST_OUTSTANDING_OFFSET)) {
-+ writel(BURST4_OUTSTANDING1, priv->axi_bus_cfg_base);
-+ }
++#if defined(CONFIG_ARCH_HI3519) || defined(CONFIG_ARCH_HI3519V101) || \
++ defined(CONFIG_ARCH_HI3559) || defined(CONFIG_ARCH_HI3556) || \
++ defined(CONFIG_ARCH_HI3516AV200)
++ if (!(readl(priv->axi_bus_cfg_base) >> BURST_OUTSTANDING_OFFSET))
++ writel(BURST4_OUTSTANDING1, priv->axi_bus_cfg_base);
+#elif defined(CONFIG_ARCH_HI3521A) || defined(CONFIG_ARCH_HI3531A)
-+ writel(BURST4_OUTSTANDING1, priv->axi_bus_cfg_base);
++ writel(BURST4_OUTSTANDING1, priv->axi_bus_cfg_base);
+#endif
+}
+
+static void higmac_hw_init(struct higmac_netdev_local *priv)
+{
-+ u32 val;
-+ u32 reg;
-+ int i;
++ u32 val;
++ u32 reg;
++ int i;
+
-+ higmac_axi_bus_cfg(priv);
++ higmac_axi_bus_cfg(priv);
+
-+ /* disable and clear all interrupts */
-+ writel(0, priv->gmac_iobase + ENA_PMU_INT);
-+ writel(~0, priv->gmac_iobase + RAW_PMU_INT);
++ /* disable and clear all interrupts */
++ writel(0, priv->gmac_iobase + ENA_PMU_INT);
++ writel(~0, priv->gmac_iobase + RAW_PMU_INT);
+
-+ for (i = 1; i < priv->num_rxqs; i++) {
-+ reg = RSS_ENA_INT_QUEUE(i);
-+ writel(0, priv->gmac_iobase + reg);
-+ }
-+ writel(~0, priv->gmac_iobase + RSS_RAW_PMU_INT);
++ for (i = 1; i < priv->num_rxqs; i++) {
++ reg = RSS_ENA_INT_QUEUE(i);
++ writel(0, priv->gmac_iobase + reg);
++ }
++ writel(~0, priv->gmac_iobase + RSS_RAW_PMU_INT);
+
-+ /* enable CRC erro packets filter */
-+ val = readl(priv->gmac_iobase + REC_FILT_CONTROL);
-+ val |= BIT_CRC_ERR_PASS;
-+ writel(val, priv->gmac_iobase + REC_FILT_CONTROL);
++ /* enable CRC erro packets filter */
++ val = readl(priv->gmac_iobase + REC_FILT_CONTROL);
++ val |= BIT_CRC_ERR_PASS;
++ writel(val, priv->gmac_iobase + REC_FILT_CONTROL);
+
-+ /* set tx min packet length */
-+ val = readl(priv->gmac_iobase + CRF_MIN_PACKET);
-+ val &= ~BIT_MASK_TX_MIN_LEN;
-+ val |= ETH_HLEN << BIT_OFFSET_TX_MIN_LEN;
-+ writel(val, priv->gmac_iobase + CRF_MIN_PACKET);
++ /* set tx min packet length */
++ val = readl(priv->gmac_iobase + CRF_MIN_PACKET);
++ val &= ~BIT_MASK_TX_MIN_LEN;
++ val |= ETH_HLEN << BIT_OFFSET_TX_MIN_LEN;
++ writel(val, priv->gmac_iobase + CRF_MIN_PACKET);
+
-+ /* fix bug for udp and ip error check */
-+ writel(CONTROL_WORD_CONFIG, priv->gmac_iobase + CONTROL_WORD);
++ /* fix bug for udp and ip error check */
++ writel(CONTROL_WORD_CONFIG, priv->gmac_iobase + CONTROL_WORD);
+
-+ writel(0, priv->gmac_iobase + COL_SLOT_TIME);
++ writel(0, priv->gmac_iobase + COL_SLOT_TIME);
+
-+ writel(DUPLEX_HALF, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL);
++ writel(DUPLEX_HALF, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL);
+
-+ /* FIXME: interrupt when rcv packets >= RX_BQ_INT_THRESHOLD */
-+ val = RX_BQ_INT_THRESHOLD |
-+ (TX_RQ_INT_THRESHOLD << BITS_OFFSET_TX_RQ_IN_TH);
-+ writel(val, priv->gmac_iobase + IN_QUEUE_TH);
++ /* FIXME: interrupt when rcv packets >= RX_BQ_INT_THRESHOLD */
++ val = RX_BQ_INT_THRESHOLD |
++ (TX_RQ_INT_THRESHOLD << BITS_OFFSET_TX_RQ_IN_TH);
++ writel(val, priv->gmac_iobase + IN_QUEUE_TH);
+
-+ /* FIXME: rx_bq/tx_rq in timeout threshold */
-+ writel(0x10000, priv->gmac_iobase + RX_BQ_IN_TIMEOUT_TH);
++ /* FIXME: rx_bq/tx_rq in timeout threshold */
++ writel(0x10000, priv->gmac_iobase + RX_BQ_IN_TIMEOUT_TH);
+
-+ writel(0x18000, priv->gmac_iobase + TX_RQ_IN_TIMEOUT_TH);
++ writel(0x18000, priv->gmac_iobase + TX_RQ_IN_TIMEOUT_TH);
+
-+ higmac_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM);
++ higmac_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM);
+}
+
+static inline void higmac_irq_enable(struct higmac_netdev_local *ld)
+{
-+ writel(RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT,
-+ ld->gmac_iobase + ENA_PMU_INT);
++ writel(RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT
++ | TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT,
++ ld->gmac_iobase + ENA_PMU_INT);
+}
+
+static inline void higmac_irq_enable_queue(struct higmac_netdev_local *ld,
-+ int rxq_id)
++ int rxq_id)
+{
-+ if (rxq_id) {
-+ u32 reg;
++ if (rxq_id) {
++ u32 reg;
+
-+ reg = RSS_ENA_INT_QUEUE(rxq_id);
-+ writel(~0, ld->gmac_iobase + reg);
-+ } else {
-+ higmac_irq_enable(ld);
-+ }
++ reg = RSS_ENA_INT_QUEUE(rxq_id);
++ writel(~0, ld->gmac_iobase + reg);
++ } else {
++ higmac_irq_enable(ld);
++ }
+}
+
+static inline void higmac_irq_enable_all_queue(struct higmac_netdev_local *ld)
+{
-+ int i;
++ int i;
+
-+ for (i = 0; i < ld->num_rxqs; i++) {
-+ higmac_irq_enable_queue(ld, i);
-+ }
++ for (i = 0; i < ld->num_rxqs; i++)
++ higmac_irq_enable_queue(ld, i);
+}
+
+static inline void higmac_irq_disable(struct higmac_netdev_local *ld)
+{
-+ writel(0, ld->gmac_iobase + ENA_PMU_INT);
++ writel(0, ld->gmac_iobase + ENA_PMU_INT);
+}
+
+static inline void higmac_irq_disable_queue(struct higmac_netdev_local *ld,
-+ int rxq_id)
++ int rxq_id)
+{
-+ if (rxq_id) {
-+ u32 reg;
++ if (rxq_id) {
++ u32 reg;
+
-+ reg = RSS_ENA_INT_QUEUE(rxq_id);
-+ writel(0, ld->gmac_iobase + reg);
-+ } else {
-+ higmac_irq_disable(ld);
-+ }
++ reg = RSS_ENA_INT_QUEUE(rxq_id);
++ writel(0, ld->gmac_iobase + reg);
++ } else {
++ higmac_irq_disable(ld);
++ }
+}
+
+static inline void higmac_irq_disable_all_queue(struct higmac_netdev_local *ld)
+{
-+ int i;
++ int i;
+
-+ for (i = 0; i < ld->num_rxqs; i++) {
-+ higmac_irq_disable_queue(ld, i);
-+ }
++ for (i = 0; i < ld->num_rxqs; i++)
++ higmac_irq_disable_queue(ld, i);
+}
+
+static inline bool higmac_queue_irq_disabled(struct higmac_netdev_local *ld,
-+ int rxq_id)
++ int rxq_id)
+{
-+ u32 reg, val;
++ u32 reg, val;
+
-+ if (rxq_id) {
-+ reg = RSS_ENA_INT_QUEUE(rxq_id);
-+ } else {
-+ reg = ENA_PMU_INT;
-+ }
-+ val = readl(ld->gmac_iobase + reg);
++ if (rxq_id)
++ reg = RSS_ENA_INT_QUEUE(rxq_id);
++ else
++ reg = ENA_PMU_INT;
++ val = readl(ld->gmac_iobase + reg);
+
-+ return !val;
++ return !val;
+}
+
+static inline void higmac_hw_desc_enable(struct higmac_netdev_local *ld)
+{
-+ writel(0xF, ld->gmac_iobase + DESC_WR_RD_ENA);
++ writel(0xF, ld->gmac_iobase + DESC_WR_RD_ENA);
+}
+
+static inline void higmac_hw_desc_disable(struct higmac_netdev_local *ld)
+{
-+ writel(0, ld->gmac_iobase + DESC_WR_RD_ENA);
++ writel(0, ld->gmac_iobase + DESC_WR_RD_ENA);
+}
+
+static inline void higmac_port_enable(struct higmac_netdev_local *ld)
+{
-+ writel(BITS_TX_EN | BITS_RX_EN, ld->gmac_iobase + PORT_EN);
++ writel(BITS_TX_EN | BITS_RX_EN, ld->gmac_iobase + PORT_EN);
+}
+
+static inline void higmac_port_disable(struct higmac_netdev_local *ld)
+{
-+ writel(0, ld->gmac_iobase + PORT_EN);
++ writel(0, ld->gmac_iobase + PORT_EN);
+}
+
+void higmac_set_flow_ctrl_params(struct higmac_netdev_local *ld)
+{
-+ unsigned int rx_fq_empty_th;
-+ unsigned int rx_fq_full_th;
-+ unsigned int rx_bq_empty_th;
-+ unsigned int rx_bq_full_th;
-+ unsigned int rec_filter;
++ unsigned int rx_fq_empty_th;
++ unsigned int rx_fq_full_th;
++ unsigned int rx_bq_empty_th;
++ unsigned int rx_bq_full_th;
++ unsigned int rec_filter;
+
-+ writel(ld->pause, ld->gmac_iobase + FC_TX_TIMER);
-+ writel(ld->pause_interval, ld->gmac_iobase + PAUSE_THR);
++ writel(ld->pause, ld->gmac_iobase + FC_TX_TIMER);
++ writel(ld->pause_interval, ld->gmac_iobase + PAUSE_THR);
+
-+ rx_fq_empty_th = readl(ld->gmac_iobase + RX_FQ_ALEMPTY_TH);
-+ rx_fq_empty_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
-+ rx_fq_empty_th |= (ld->flow_ctrl_active_threshold << BITS_Q_PAUSE_TH_OFFSET);
-+ writel(rx_fq_empty_th, ld->gmac_iobase + RX_FQ_ALEMPTY_TH);
++ rx_fq_empty_th = readl(ld->gmac_iobase + RX_FQ_ALEMPTY_TH);
++ rx_fq_empty_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
++ rx_fq_empty_th |= (ld->flow_ctrl_active_threshold <<
++ BITS_Q_PAUSE_TH_OFFSET);
++ writel(rx_fq_empty_th, ld->gmac_iobase + RX_FQ_ALEMPTY_TH);
+
-+ rx_fq_full_th = readl(ld->gmac_iobase + RX_FQ_ALFULL_TH);
-+ rx_fq_full_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
-+ rx_fq_full_th |= (ld->flow_ctrl_deactive_threshold << BITS_Q_PAUSE_TH_OFFSET);
-+ writel(rx_fq_full_th, ld->gmac_iobase + RX_FQ_ALFULL_TH);
++ rx_fq_full_th = readl(ld->gmac_iobase + RX_FQ_ALFULL_TH);
++ rx_fq_full_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
++ rx_fq_full_th |= (ld->flow_ctrl_deactive_threshold <<
++ BITS_Q_PAUSE_TH_OFFSET);
++ writel(rx_fq_full_th, ld->gmac_iobase + RX_FQ_ALFULL_TH);
+
-+ rx_bq_empty_th = readl(ld->gmac_iobase + RX_BQ_ALEMPTY_TH);
-+ rx_bq_empty_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
-+ rx_bq_empty_th |= (ld->flow_ctrl_active_threshold << BITS_Q_PAUSE_TH_OFFSET);
-+ writel(rx_bq_empty_th, ld->gmac_iobase + RX_BQ_ALEMPTY_TH);
++ rx_bq_empty_th = readl(ld->gmac_iobase + RX_BQ_ALEMPTY_TH);
++ rx_bq_empty_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
++ rx_bq_empty_th |= (ld->flow_ctrl_active_threshold <<
++ BITS_Q_PAUSE_TH_OFFSET);
++ writel(rx_bq_empty_th, ld->gmac_iobase + RX_BQ_ALEMPTY_TH);
+
-+ rx_bq_full_th = readl(ld->gmac_iobase + RX_BQ_ALFULL_TH);
-+ rx_bq_full_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
-+ rx_bq_full_th |= (ld->flow_ctrl_deactive_threshold << BITS_Q_PAUSE_TH_OFFSET);
-+ writel(rx_bq_full_th, ld->gmac_iobase + RX_BQ_ALFULL_TH);
++ rx_bq_full_th = readl(ld->gmac_iobase + RX_BQ_ALFULL_TH);
++ rx_bq_full_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET);
++ rx_bq_full_th |= (ld->flow_ctrl_deactive_threshold <<
++ BITS_Q_PAUSE_TH_OFFSET);
++ writel(rx_bq_full_th, ld->gmac_iobase + RX_BQ_ALFULL_TH);
+
-+ writel(0, ld->gmac_iobase + CRF_TX_PAUSE);
++ writel(0, ld->gmac_iobase + CRF_TX_PAUSE);
+
-+ rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL);
-+ rec_filter |= BIT_PAUSE_FRM_PASS;
-+ writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL);
++ rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL);
++ rec_filter |= BIT_PAUSE_FRM_PASS;
++ writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL);
+}
+
+void higmac_set_flow_ctrl_state(struct higmac_netdev_local *ld, int pause)
+{
-+ unsigned int flow_rx_q_en;
-+ unsigned int flow;
++ unsigned int flow_rx_q_en;
++ unsigned int flow;
+
-+ flow_rx_q_en = readl(ld->gmac_iobase + RX_PAUSE_EN);
-+ flow_rx_q_en &= ~(BIT_RX_FQ_PAUSE_EN | BIT_RX_BQ_PAUSE_EN);
-+ if (pause && (ld->flow_ctrl & FLOW_TX)) {
-+ flow_rx_q_en |= (BIT_RX_FQ_PAUSE_EN | BIT_RX_BQ_PAUSE_EN);
-+ }
-+ writel(flow_rx_q_en, ld->gmac_iobase + RX_PAUSE_EN);
++ flow_rx_q_en = readl(ld->gmac_iobase + RX_PAUSE_EN);
++ flow_rx_q_en &= ~(BIT_RX_FQ_PAUSE_EN | BIT_RX_BQ_PAUSE_EN);
++ if (pause && (ld->flow_ctrl & FLOW_TX))
++ flow_rx_q_en |= (BIT_RX_FQ_PAUSE_EN | BIT_RX_BQ_PAUSE_EN);
++ writel(flow_rx_q_en, ld->gmac_iobase + RX_PAUSE_EN);
+
-+ flow = readl(ld->gmac_iobase + PAUSE_EN);
-+ flow &= ~(BIT_RX_FDFC | BIT_TX_FDFC);
-+ if (pause) {
-+ if (ld->flow_ctrl & FLOW_RX) {
-+ flow |= BIT_RX_FDFC;
-+ }
-+ if (ld->flow_ctrl & FLOW_TX) {
-+ flow |= BIT_TX_FDFC;
-+ }
-+ }
-+ writel(flow, ld->gmac_iobase + PAUSE_EN);
++ flow = readl(ld->gmac_iobase + PAUSE_EN);
++ flow &= ~(BIT_RX_FDFC | BIT_TX_FDFC);
++ if (pause) {
++ if (ld->flow_ctrl & FLOW_RX)
++ flow |= BIT_RX_FDFC;
++ if (ld->flow_ctrl & FLOW_TX)
++ flow |= BIT_TX_FDFC;
++ }
++ writel(flow, ld->gmac_iobase + PAUSE_EN);
+}
+
+static void higmac_set_flow_ctrl_args(struct higmac_netdev_local *ld)
+{
-+ ld->flow_ctrl = flow_ctrl_en;
-+ ld->pause = tx_flow_ctrl_pause_time;
-+ ld->pause_interval = tx_flow_ctrl_pause_interval;
-+ ld->flow_ctrl_active_threshold = tx_flow_ctrl_active_threshold;
-+ ld->flow_ctrl_deactive_threshold = tx_flow_ctrl_deactive_threshold;
++ ld->flow_ctrl = flow_ctrl_en;
++ ld->pause = tx_flow_ctrl_pause_time;
++ ld->pause_interval = tx_flow_ctrl_pause_interval;
++ ld->flow_ctrl_active_threshold = tx_flow_ctrl_active_threshold;
++ ld->flow_ctrl_deactive_threshold = tx_flow_ctrl_deactive_threshold;
+}
+
+/* set gmac's multicast list, here we setup gmac's mc filter */
+static void higmac_gmac_multicast_list(struct net_device *dev)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(dev);
-+ unsigned int rec_filter;
++ struct higmac_netdev_local *ld = netdev_priv(dev);
++ unsigned int rec_filter;
+
-+ rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL);
-+ /* when set gmac in promisc mode
-+ * a. dev in IFF_PROMISC mode
-+ */
-+ if ((dev->flags & IFF_PROMISC)) {
-+ /* promisc mode.received all pkgs. */
-+ rec_filter &= ~(BIT_BC_DROP_EN | BIT_MC_MATCH_EN |
-+ BIT_UC_MATCH_EN);
-+ } else {
-+ /* drop uc pkgs with field 'DA' not match our's */
-+ rec_filter |= BIT_UC_MATCH_EN;
++ rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL);
++ /* when set gmac in promisc mode
++ * a. dev in IFF_PROMISC mode
++ */
++ if ((dev->flags & IFF_PROMISC)) {
++ /* promisc mode.received all pkgs. */
++ rec_filter &= ~(BIT_BC_DROP_EN | BIT_MC_MATCH_EN |
++ BIT_UC_MATCH_EN);
++ } else {
++ /* drop uc pkgs with field 'DA' not match our's */
++ rec_filter |= BIT_UC_MATCH_EN;
+
-+ if (dev->flags & IFF_BROADCAST) { /* no broadcast */
-+ rec_filter &= ~BIT_BC_DROP_EN;
-+ }
-+ else {
-+ rec_filter |= BIT_BC_DROP_EN;
-+ }
++ if (dev->flags & IFF_BROADCAST) /* no broadcast */
++ rec_filter &= ~BIT_BC_DROP_EN;
++ else
++ rec_filter |= BIT_BC_DROP_EN;
+
-+ if (netdev_mc_empty(dev) || !(dev->flags & IFF_MULTICAST)) {
-+ /* haven't join any mc group */
-+ writel(0, ld->gmac_iobase + PORT_MC_ADDR_LOW);
-+ writel(0, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
-+ rec_filter |= BIT_MC_MATCH_EN;
-+ } else if (netdev_mc_count(dev) == 1 &&
-+ (dev->flags & IFF_MULTICAST)) {
-+ struct netdev_hw_addr *ha;
-+ unsigned int d = 0;
++ if (netdev_mc_empty(dev) || !(dev->flags & IFF_MULTICAST)) {
++ /* haven't join any mc group */
++ writel(0, ld->gmac_iobase + PORT_MC_ADDR_LOW);
++ writel(0, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
++ rec_filter |= BIT_MC_MATCH_EN;
++ } else if (netdev_mc_count(dev) == 1 &&
++ (dev->flags & IFF_MULTICAST)) {
++ struct netdev_hw_addr *ha = NULL;
++ unsigned int d = 0;
+
-+ netdev_for_each_mc_addr(ha, dev) {
-+ d = (ha->addr[0] << 8) | (ha->addr[1]);
-+ writel(d, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
++ netdev_for_each_mc_addr(ha, dev) {
++ d = (ha->addr[0] << 8) | (ha->addr[1]);
++ writel(d, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
+
-+ d = (ha->addr[2] << 24) | (ha->addr[3] << 16) | (ha->addr[4] << 8) | (ha->addr[5]);
-+ writel(d, ld->gmac_iobase + PORT_MC_ADDR_LOW);
-+ }
-+ rec_filter |= BIT_MC_MATCH_EN;
-+ } else {
-+ rec_filter &= ~BIT_MC_MATCH_EN;
-+ }
-+ }
-+ writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL);
++ d = (ha->addr[2] << 24) | (ha->addr[3] << 16)
++ | (ha->addr[4] << 8) | (ha->addr[5]);
++ writel(d, ld->gmac_iobase + PORT_MC_ADDR_LOW);
++ }
++ rec_filter |= BIT_MC_MATCH_EN;
++ } else {
++ rec_filter &= ~BIT_MC_MATCH_EN;
++ }
++ }
++ writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL);
+}
+
+/* the func stop the hw desc and relaim the software skb resource
@@ -313358,78 +381806,74 @@ index 0000000..5d172c3
+ */
+void higmac_reclaim_rx_tx_resource(struct higmac_netdev_local *ld)
+{
-+ unsigned long rxflags, txflags;
-+ int rd_offset, wr_offset;
-+ int i;
++ unsigned long rxflags, txflags;
++ int rd_offset, wr_offset;
++ int i;
+
-+ higmac_irq_disable_all_queue(ld);
-+ higmac_hw_desc_disable(ld);
-+ writel(STOP_RX_TX, ld->gmac_iobase + STOP_CMD);
++ higmac_irq_disable_all_queue(ld);
++ higmac_hw_desc_disable(ld);
++ writel(STOP_RX_TX, ld->gmac_iobase + STOP_CMD);
+
-+ spin_lock_irqsave(&ld->rxlock, rxflags);
-+ /* rx_bq: logic write pointer */
-+ wr_offset = readl(ld->gmac_iobase + RX_BQ_WR_ADDR);
-+ /* rx_bq: software read pointer */
-+ rd_offset = readl(ld->gmac_iobase + RX_BQ_RD_ADDR);
-+ /* FIXME: prevent to reclaim skb in rx bottom half */
-+ writel(wr_offset, ld->gmac_iobase + RX_BQ_RD_ADDR);
++ spin_lock_irqsave(&ld->rxlock, rxflags);
++ /* rx_bq: logic write pointer */
++ wr_offset = readl(ld->gmac_iobase + RX_BQ_WR_ADDR);
++ /* rx_bq: software read pointer */
++ rd_offset = readl(ld->gmac_iobase + RX_BQ_RD_ADDR);
++ /* FIXME: prevent to reclaim skb in rx bottom half */
++ writel(wr_offset, ld->gmac_iobase + RX_BQ_RD_ADDR);
+
-+ for (i = 1; i < ld->num_rxqs; i++) {
-+ u32 rx_bq_wr_reg, rx_bq_rd_reg;
++ for (i = 1; i < ld->num_rxqs; i++) {
++ u32 rx_bq_wr_reg, rx_bq_rd_reg;
+
-+ rx_bq_wr_reg = RX_BQ_WR_ADDR_QUEUE(i);
-+ rx_bq_rd_reg = RX_BQ_RD_ADDR_QUEUE(i);
++ rx_bq_wr_reg = RX_BQ_WR_ADDR_QUEUE(i);
++ rx_bq_rd_reg = RX_BQ_RD_ADDR_QUEUE(i);
+
-+ wr_offset = readl(ld->gmac_iobase + rx_bq_wr_reg);
-+ writel(wr_offset, ld->gmac_iobase + rx_bq_rd_reg);
-+ }
++ wr_offset = readl(ld->gmac_iobase + rx_bq_wr_reg);
++ writel(wr_offset, ld->gmac_iobase + rx_bq_rd_reg);
++ }
+
-+ /* rx_fq: software write pointer */
-+ wr_offset = readl(ld->gmac_iobase + RX_FQ_WR_ADDR);
-+ /* rx_fq: logic read pointer */
-+ rd_offset = readl(ld->gmac_iobase + RX_FQ_RD_ADDR);
-+ if (!rd_offset) {
-+ rd_offset = (RX_DESC_NUM - 1) << DESC_BYTE_SHIFT;
-+ } else {
-+ rd_offset -= DESC_SIZE;
-+ }
-+ /* FIXME: stop to feed hw desc */
-+ writel(rd_offset, ld->gmac_iobase + RX_FQ_WR_ADDR);
++ /* rx_fq: software write pointer */
++ wr_offset = readl(ld->gmac_iobase + RX_FQ_WR_ADDR);
++ /* rx_fq: logic read pointer */
++ rd_offset = readl(ld->gmac_iobase + RX_FQ_RD_ADDR);
++ if (!rd_offset)
++ rd_offset = (RX_DESC_NUM - 1) << DESC_BYTE_SHIFT;
++ else
++ rd_offset -= DESC_SIZE;
++ /* FIXME: stop to feed hw desc */
++ writel(rd_offset, ld->gmac_iobase + RX_FQ_WR_ADDR);
+
-+ for (i = 0; i < ld->rx_fq.count; i++) {
-+ if (!ld->rx_fq.skb[i]) {
-+ ld->rx_fq.skb[i] = SKB_MAGIC;
-+ }
-+ }
-+ spin_unlock_irqrestore(&ld->rxlock, rxflags);
++ for (i = 0; i < ld->rx_fq.count; i++) {
++ if (!ld->rx_fq.skb[i])
++ ld->rx_fq.skb[i] = SKB_MAGIC;
++ }
++ spin_unlock_irqrestore(&ld->rxlock, rxflags);
+
-+ /* no need to wait pkts in tx_rq finish to free all skb,
-+ * because higmac_xmit_reclaim is in the tx_lock,
-+ */
-+ spin_lock_irqsave(&ld->txlock, txflags);
-+ /* tx_rq: logic write */
-+ wr_offset = readl(ld->gmac_iobase + TX_RQ_WR_ADDR);
-+ /* tx_rq: software read */
-+ rd_offset = readl(ld->gmac_iobase + TX_RQ_RD_ADDR);
-+ /* FIXME: stop to reclaim tx skb */
-+ writel(wr_offset, ld->gmac_iobase + TX_RQ_RD_ADDR);
++ /* no need to wait pkts in tx_rq finish to free all skb,
++ * because higmac_xmit_reclaim is in the tx_lock,
++ */
++ spin_lock_irqsave(&ld->txlock, txflags);
++ /* tx_rq: logic write */
++ wr_offset = readl(ld->gmac_iobase + TX_RQ_WR_ADDR);
++ /* tx_rq: software read */
++ rd_offset = readl(ld->gmac_iobase + TX_RQ_RD_ADDR);
++ /* FIXME: stop to reclaim tx skb */
++ writel(wr_offset, ld->gmac_iobase + TX_RQ_RD_ADDR);
+
-+ /* tx_bq: logic read */
-+ rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
-+ if (!rd_offset) {
-+ rd_offset = (TX_DESC_NUM - 1) << DESC_BYTE_SHIFT;
-+ } else {
-+ rd_offset -= DESC_SIZE;
-+ }
-+ /* FIXME: stop software tx skb */
-+ writel(rd_offset, ld->gmac_iobase + TX_BQ_WR_ADDR);
++ /* tx_bq: logic read */
++ rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
++ if (!rd_offset)
++ rd_offset = (TX_DESC_NUM - 1) << DESC_BYTE_SHIFT;
++ else
++ rd_offset -= DESC_SIZE;
++ /* FIXME: stop software tx skb */
++ writel(rd_offset, ld->gmac_iobase + TX_BQ_WR_ADDR);
+
-+ for (i = 0; i < ld->tx_bq.count; i++) {
-+ if (!ld->tx_bq.skb[i]) {
-+ ld->tx_bq.skb[i] = SKB_MAGIC;
-+ }
-+ }
-+ spin_unlock_irqrestore(&ld->txlock, txflags);
++ for (i = 0; i < ld->tx_bq.count; i++) {
++ if (!ld->tx_bq.skb[i])
++ ld->tx_bq.skb[i] = SKB_MAGIC;
++ }
++ spin_unlock_irqrestore(&ld->txlock, txflags);
+}
+
+static void higmac_monitor_func(unsigned long arg);
@@ -313437,512 +381881,495 @@ index 0000000..5d172c3
+
+static void higmac_hw_set_mac_addr(struct net_device *dev)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(dev);
-+ unsigned char *mac = dev->dev_addr;
-+ u32 val;
++ struct higmac_netdev_local *priv = netdev_priv(dev);
++ unsigned char *mac = dev->dev_addr;
++ u32 val;
+
-+ val = mac[1] | (mac[0] << 8);
-+ writel(val, priv->gmac_iobase + STATION_ADDR_HIGH);
++ val = mac[1] | (mac[0] << 8);
++ writel(val, priv->gmac_iobase + STATION_ADDR_HIGH);
+
-+ val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
-+ writel(val, priv->gmac_iobase + STATION_ADDR_LOW);
++ val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
++ writel(val, priv->gmac_iobase + STATION_ADDR_LOW);
+}
+
+static u32 higmac_rx_refill(struct higmac_netdev_local *priv);
+
+static void higmac_free_rx_skb(struct higmac_netdev_local *ld)
+{
-+ struct sk_buff *skb = NULL;
-+ int i;
++ struct sk_buff *skb = NULL;
++ int i;
+
-+ for (i = 0; i < ld->rx_fq.count; i++) {
-+ skb = ld->rx_fq.skb[i];
-+ if (skb) {
-+ ld->rx_skb[i] = NULL;
-+ ld->rx_fq.skb[i] = NULL;
-+ if (skb == SKB_MAGIC) {
-+ continue;
-+ }
-+ dev_kfree_skb_any(skb);
-+ /* TODO: need to unmap the skb here
-+ * but there is no way to get the dma_addr here,
-+ * and unmap(TO_DEVICE) ops do nothing in fact,
-+ * so we ignore to call
-+ * dma_unmap_single(dev, dma_addr, skb->len,
-+ * DMA_TO_DEVICE)
-+ */
-+ }
-+ }
++ for (i = 0; i < ld->rx_fq.count; i++) {
++ skb = ld->rx_fq.skb[i];
++ if (skb) {
++ ld->rx_skb[i] = NULL;
++ ld->rx_fq.skb[i] = NULL;
++ if (skb == SKB_MAGIC)
++ continue;
++ dev_kfree_skb_any(skb);
++ /* TODO: need to unmap the skb here
++ * but there is no way to get the dma_addr here,
++ * and unmap(TO_DEVICE) ops do nothing in fact,
++ * so we ignore to call
++ * dma_unmap_single(dev, dma_addr, skb->len,
++ * DMA_TO_DEVICE)
++ */
++ }
++ }
+}
+
+static void higmac_free_tx_skb(struct higmac_netdev_local *ld)
+{
-+ struct sk_buff *skb = NULL;
-+ int i;
++ struct sk_buff *skb = NULL;
++ int i;
+
-+ for (i = 0; i < ld->tx_bq.count; i++) {
-+ skb = ld->tx_bq.skb[i];
-+ if (skb) {
-+ ld->tx_skb[i] = NULL;
-+ ld->tx_bq.skb[i] = NULL;
-+ if (skb == SKB_MAGIC) {
-+ continue;
-+ }
-+ dev_kfree_skb_any(skb);
-+ /* TODO: unmap the skb */
-+ }
-+ }
++ for (i = 0; i < ld->tx_bq.count; i++) {
++ skb = ld->tx_bq.skb[i];
++ if (skb) {
++ ld->tx_skb[i] = NULL;
++ ld->tx_bq.skb[i] = NULL;
++ if (skb == SKB_MAGIC)
++ continue;
++ dev_kfree_skb_any(skb);
++ /* TODO: unmap the skb */
++ }
++ }
+}
+
+/* reset and re-config gmac */
+void higmac_restart(struct higmac_netdev_local *ld)
+{
-+ unsigned long rxflags, txflags;
++ unsigned long rxflags, txflags;
+
-+ /* restart hw engine now */
-+ higmac_mac_core_reset(ld);
++ /* restart hw engine now */
++ higmac_mac_core_reset(ld);
+
-+ spin_lock_irqsave(&ld->rxlock, rxflags);
-+ spin_lock_irqsave(&ld->txlock, txflags);
++ spin_lock_irqsave(&ld->rxlock, rxflags);
++ spin_lock_irqsave(&ld->txlock, txflags);
+
-+ higmac_free_rx_skb(ld);
-+ higmac_free_tx_skb(ld);
++ higmac_free_rx_skb(ld);
++ higmac_free_tx_skb(ld);
+
-+ pmt_reg_restore(ld);
-+ higmac_hw_init(ld);
-+ higmac_hw_set_mac_addr(ld->netdev);
-+ higmac_hw_set_desc_addr(ld);
++ pmt_reg_restore(ld);
++ higmac_hw_init(ld);
++ higmac_hw_set_mac_addr(ld->netdev);
++ higmac_hw_set_desc_addr(ld);
+
-+ /* we don't set macif here, it will be set in adjust_link */
-+ if (ld->netdev->flags & IFF_UP) {
-+ /* when resume, only do the following operations
-+ * when dev is up before suspend.
-+ */
-+ higmac_rx_refill(ld);
-+ higmac_set_multicast_list(ld->netdev);
++ /* we don't set macif here, it will be set in adjust_link */
++ if (ld->netdev->flags & IFF_UP) {
++ /* when resume, only do the following operations
++ * when dev is up before suspend.
++ */
++ higmac_rx_refill(ld);
++ higmac_set_multicast_list(ld->netdev);
+
-+ higmac_hw_desc_enable(ld);
-+ higmac_port_enable(ld);
-+ higmac_irq_enable_all_queue(ld);
-+ }
-+ spin_unlock_irqrestore(&ld->txlock, txflags);
-+ spin_unlock_irqrestore(&ld->rxlock, rxflags);
++ higmac_hw_desc_enable(ld);
++ higmac_port_enable(ld);
++ higmac_irq_enable_all_queue(ld);
++ }
++ spin_unlock_irqrestore(&ld->txlock, txflags);
++ spin_unlock_irqrestore(&ld->rxlock, rxflags);
+}
+
+static int higmac_net_set_mac_address(struct net_device *dev, void *p)
+{
-+ int ret;
++ int ret;
+
-+ ret = eth_mac_addr(dev, p);
-+ if (!ret) {
-+ higmac_hw_set_mac_addr(dev);
-+ }
++ ret = eth_mac_addr(dev, p);
++ if (!ret)
++ higmac_hw_set_mac_addr(dev);
+
-+ return ret;
++ return ret;
+}
+
+#define HIGMAC_LINK_CHANGE_PROTECT
+#define HIGMAC_MAC_TX_RESET_IN_LINKUP
+
+#ifdef HIGMAC_LINK_CHANGE_PROTECT
-+#define HIGMAC_MS_TO_NS (1000000ULL)
-+#define HIGMAC_FLUSH_WAIT_TIME (100 * HIGMAC_MS_TO_NS)
++#define HIGMAC_MS_TO_NS (1000000ULL)
++#define HIGMAC_FLUSH_WAIT_TIME (100*HIGMAC_MS_TO_NS)
+/* protect code */
+static void higmac_linkup_flush(struct higmac_netdev_local *ld)
+{
-+ int tx_bq_wr_offset, tx_bq_rd_offset;
-+ unsigned long long time_limit, time_now;
++ int tx_bq_wr_offset, tx_bq_rd_offset;
++ unsigned long long time_limit, time_now;
+
-+ time_now = sched_clock();
-+ time_limit = time_now + HIGMAC_FLUSH_WAIT_TIME;
++ time_now = sched_clock();
++ time_limit = time_now + HIGMAC_FLUSH_WAIT_TIME;
+
-+ do {
-+ tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR);
-+ tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
++ do {
++ tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR);
++ tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
+
-+ time_now = sched_clock();
-+ if (unlikely((long long)time_now -
-+ (long long)time_limit >=
-+ 0)) {
-+ break;
-+ }
-+ } while (tx_bq_rd_offset != tx_bq_wr_offset);
++ time_now = sched_clock();
++ if (unlikely((long long)time_now -
++ (long long)time_limit >= 0))
++ break;
++ } while (tx_bq_rd_offset != tx_bq_wr_offset);
+
-+ mdelay(1);
++ mdelay(1);
+}
+#endif
+
+#ifdef HIGMAC_MAC_TX_RESET_IN_LINKUP
+static void higmac_mac_tx_state_engine_reset(struct higmac_netdev_local *priv)
+{
-+ u32 val;
++ u32 val;
+
-+ val = readl(priv->gmac_iobase + MAC_CLEAR);
-+ val |= BIT_TX_SOFT_RESET;
-+ writel(val, priv->gmac_iobase + MAC_CLEAR);
++ val = readl(priv->gmac_iobase + MAC_CLEAR);
++ val |= BIT_TX_SOFT_RESET;
++ writel(val, priv->gmac_iobase + MAC_CLEAR);
+
-+ mdelay(5);
++ mdelay(5);
+
-+ val = readl(priv->gmac_iobase + MAC_CLEAR);
-+ val &= ~BIT_TX_SOFT_RESET;
-+ writel(val, priv->gmac_iobase + MAC_CLEAR);
++ val = readl(priv->gmac_iobase + MAC_CLEAR);
++ val &= ~BIT_TX_SOFT_RESET;
++ writel(val, priv->gmac_iobase + MAC_CLEAR);
+}
+#endif
+
+static void higmac_adjust_link(struct net_device *dev)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(dev);
-+ struct phy_device *phy = priv->phy;
-+ bool link_status_changed = false;
++ struct higmac_netdev_local *priv = netdev_priv(dev);
++ struct phy_device *phy = priv->phy;
++ bool link_status_changed = false;
+
-+ if (phy->link) {
-+ if ((priv->old_speed != phy->speed) ||
-+ (priv->old_duplex != phy->duplex)) {
++ if (phy->link) {
++ if ((priv->old_speed != phy->speed) ||
++ (priv->old_duplex != phy->duplex)) {
+#ifdef HIGMAC_LINK_CHANGE_PROTECT
-+ unsigned long txflags;
++ unsigned long txflags;
+
-+ spin_lock_irqsave(&priv->txlock, txflags);
++ spin_lock_irqsave(&priv->txlock, txflags);
+
-+ higmac_linkup_flush(priv);
++ higmac_linkup_flush(priv);
+#endif
-+ higmac_config_port(dev, phy->speed, phy->duplex);
++ higmac_config_port(dev, phy->speed, phy->duplex);
+#ifdef HIGMAC_MAC_TX_RESET_IN_LINKUP
-+ higmac_mac_tx_state_engine_reset(priv);
++ higmac_mac_tx_state_engine_reset(priv);
+#endif
+#ifdef HIGMAC_LINK_CHANGE_PROTECT
-+ spin_unlock_irqrestore(&priv->txlock, txflags);
++ spin_unlock_irqrestore(&priv->txlock, txflags);
+#endif
-+ higmac_set_flow_ctrl_state(priv, phy->pause);
++ higmac_set_flow_ctrl_state(priv, phy->pause);
+
-+ if (priv->autoeee) {
-+ init_autoeee(priv);
-+ }
++ if (priv->autoeee)
++ init_autoeee(priv);
+
-+ link_status_changed = true;
-+ priv->old_link = 1;
-+ priv->old_speed = phy->speed;
-+ priv->old_duplex = phy->duplex;
-+ }
-+ } else if (priv->old_link) {
-+ link_status_changed = true;
-+ priv->old_link = 0;
-+ priv->old_speed = SPEED_UNKNOWN;
-+ priv->old_duplex = DUPLEX_UNKNOWN;
-+ }
++ link_status_changed = true;
++ priv->old_link = 1;
++ priv->old_speed = phy->speed;
++ priv->old_duplex = phy->duplex;
++ }
++ } else if (priv->old_link) {
++ link_status_changed = true;
++ priv->old_link = 0;
++ priv->old_speed = SPEED_UNKNOWN;
++ priv->old_duplex = DUPLEX_UNKNOWN;
++ }
+
-+ if (link_status_changed && netif_msg_link(priv)) {
-+ phy_print_status(phy);
-+ }
++ if (link_status_changed && netif_msg_link(priv))
++ phy_print_status(phy);
+}
+
+int higmac_tx_avail(struct higmac_netdev_local *ld)
+{
-+ int tx_bq_wr_offset, tx_bq_rd_offset;
++ unsigned int tx_bq_wr_offset, tx_bq_rd_offset;
+
-+ tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR);
-+ tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
++ tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR);
++ tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
+
-+ return (tx_bq_rd_offset >> DESC_BYTE_SHIFT) + TX_DESC_NUM - (tx_bq_wr_offset >> DESC_BYTE_SHIFT) - 1;
++ return (tx_bq_rd_offset >> DESC_BYTE_SHIFT) + TX_DESC_NUM
++ - (tx_bq_wr_offset >> DESC_BYTE_SHIFT) - 1;
+}
+
+static int higmac_init_sg_desc_queue(struct higmac_netdev_local *ld)
+{
-+ ld->sg_count = ld->tx_bq.count + HIGMAC_SG_DESC_ADD;
-+ if (HAS_CAP_CCI(ld->hw_cap)) {
-+ ld->dma_sg_desc = kmalloc_array(ld->sg_count,
-+ sizeof(struct sg_desc),
-+ GFP_KERNEL);
-+ if (ld->dma_sg_desc) {
-+ ld->dma_sg_phy = virt_to_phys(ld->dma_sg_desc);
-+ }
-+ } else {
-+ ld->dma_sg_desc = (struct sg_desc *)dma_alloc_coherent(ld->dev,
-+ ld->sg_count * sizeof(struct sg_desc),
-+ &ld->dma_sg_phy, GFP_KERNEL);
-+ }
++ ld->sg_count = ld->tx_bq.count + HIGMAC_SG_DESC_ADD;
++ if (HAS_CAP_CCI(ld->hw_cap)) {
++ ld->dma_sg_desc = kmalloc_array(ld->sg_count,
++ sizeof(struct sg_desc),
++ GFP_KERNEL);
++ if (ld->dma_sg_desc)
++ ld->dma_sg_phy = virt_to_phys(ld->dma_sg_desc);
++ } else {
++ ld->dma_sg_desc = (struct sg_desc *)dma_alloc_coherent(ld->dev,
++ ld->sg_count * sizeof(struct sg_desc),
++ &ld->dma_sg_phy, GFP_KERNEL);
++ }
+
-+ if (!ld->dma_sg_desc) {
-+ pr_err("alloc sg desc dma error!\n");
-+ return -ENOMEM;
-+ }
++ if (!ld->dma_sg_desc) {
++ pr_err("alloc sg desc dma error!\n");
++ return -ENOMEM;
++ }
+#ifdef HIGMAC_TSO_DEBUG
-+ pr_info("Higmac dma_sg_phy: 0x%p\n", (void *)ld->dma_sg_phy);
++ pr_info("Higmac dma_sg_phy: 0x%p\n", (void *)ld->dma_sg_phy);
+#endif
+
-+ ld->sg_head = 0;
-+ ld->sg_tail = 0;
++ ld->sg_head = 0;
++ ld->sg_tail = 0;
+
-+ return 0;
++ return 0;
+}
+
+static void higmac_destroy_sg_desc_queue(struct higmac_netdev_local *ld)
+{
-+ if (ld->dma_sg_desc) {
-+ if (HAS_CAP_CCI(ld->hw_cap)) {
-+ kfree(ld->dma_sg_desc);
-+ } else {
-+ dma_free_coherent(ld->dev,
-+ ld->sg_count * sizeof(struct sg_desc),
-+ ld->dma_sg_desc, ld->dma_sg_phy);
-+ }
-+ ld->dma_sg_desc = NULL;
-+ }
++ if (ld->dma_sg_desc) {
++ if (HAS_CAP_CCI(ld->hw_cap))
++ kfree(ld->dma_sg_desc);
++ else
++ dma_free_coherent(ld->dev,
++ ld->sg_count * sizeof(struct sg_desc),
++ ld->dma_sg_desc, ld->dma_sg_phy);
++ ld->dma_sg_desc = NULL;
++ }
+}
+
+static bool higmac_rx_fq_empty(struct higmac_netdev_local *priv)
+{
-+ u32 start, end;
++ u32 start, end;
+
-+ start = readl(priv->gmac_iobase + RX_FQ_WR_ADDR);
-+ end = readl(priv->gmac_iobase + RX_FQ_RD_ADDR);
++ start = readl(priv->gmac_iobase + RX_FQ_WR_ADDR);
++ end = readl(priv->gmac_iobase + RX_FQ_RD_ADDR);
+
-+ if (start == end) {
-+ return true;
-+ } else {
-+ return false;
-+ }
++ if (start == end)
++ return true;
++ else
++ return false;
+}
+
+static bool higmac_rxq_has_packets(struct higmac_netdev_local *priv, int rxq_id)
+{
-+ u32 rx_bq_rd_reg, rx_bq_wr_reg;
-+ u32 start, end;
++ u32 rx_bq_rd_reg, rx_bq_wr_reg;
++ u32 start, end;
+
-+ rx_bq_rd_reg = RX_BQ_RD_ADDR_QUEUE(rxq_id);
-+ rx_bq_wr_reg = RX_BQ_WR_ADDR_QUEUE(rxq_id);
++ rx_bq_rd_reg = RX_BQ_RD_ADDR_QUEUE(rxq_id);
++ rx_bq_wr_reg = RX_BQ_WR_ADDR_QUEUE(rxq_id);
+
-+ start = readl(priv->gmac_iobase + rx_bq_rd_reg);
-+ end = readl(priv->gmac_iobase + rx_bq_wr_reg);
++ start = readl(priv->gmac_iobase + rx_bq_rd_reg);
++ end = readl(priv->gmac_iobase + rx_bq_wr_reg);
+
-+ if (start == end) {
-+ return false;
-+ } else {
-+ return true;
-+ }
++ if (start == end)
++ return false;
++ else
++ return true;
+}
+
+static void higmac_monitor_func(unsigned long arg)
+{
-+ struct net_device *dev = (struct net_device *)arg;
-+ struct higmac_netdev_local *ld = netdev_priv(dev);
-+ u32 refill_cnt;
++ struct net_device *dev = (struct net_device *)arg;
++ struct higmac_netdev_local *ld = netdev_priv(dev);
++ u32 refill_cnt;
+
-+ if (!ld || !netif_running(dev)) {
-+ higmac_trace(7, "network driver is stopped.");
-+ return;
-+ }
++ if (!ld || !netif_running(dev)) {
++ higmac_trace(7, "network driver is stopped.");
++ return;
++ }
+
-+ spin_lock(&ld->rxlock);
-+ refill_cnt = higmac_rx_refill(ld);
-+ if (!refill_cnt && higmac_rx_fq_empty(ld)) {
-+ int rxq_id;
++ spin_lock(&ld->rxlock);
++ refill_cnt = higmac_rx_refill(ld);
++ if (!refill_cnt && higmac_rx_fq_empty(ld)) {
++ int rxq_id;
+
-+ for (rxq_id = 0; rxq_id < ld->num_rxqs; rxq_id++) {
-+ if (higmac_rxq_has_packets(ld, rxq_id)) {
-+ napi_schedule(&ld->q_napi[rxq_id].napi);
-+ }
-+ }
-+ }
-+ spin_unlock(&ld->rxlock);
++ for (rxq_id = 0; rxq_id < ld->num_rxqs; rxq_id++) {
++ if (higmac_rxq_has_packets(ld, rxq_id))
++ napi_schedule(&ld->q_napi[rxq_id].napi);
++ }
++ }
++ spin_unlock(&ld->rxlock);
+
-+ ld->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
-+ mod_timer(&ld->monitor, ld->monitor.expires);
++ ld->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
++ mod_timer(&ld->monitor, ld->monitor.expires);
+}
+
+static u32 higmac_rx_refill(struct higmac_netdev_local *priv)
+{
-+ struct higmac_desc *desc;
-+ struct sk_buff *skb;
-+ u32 start, end, num, pos, i;
-+ u32 len = HIETH_MAX_FRAME_SIZE;
-+ dma_addr_t addr;
-+ u32 refill_cnt = 0;
++ struct higmac_desc *desc = NULL;
++ struct sk_buff *skb = NULL;
++ u32 start, end, num, pos, i;
++ u32 len = HIETH_MAX_FRAME_SIZE;
++ dma_addr_t addr;
++ u32 refill_cnt = 0;
+
-+ /* software write pointer */
-+ start = dma_cnt(readl(priv->gmac_iobase + RX_FQ_WR_ADDR));
-+ /* logic read pointer */
-+ end = dma_cnt(readl(priv->gmac_iobase + RX_FQ_RD_ADDR));
-+ num = CIRC_SPACE(start, end, RX_DESC_NUM);
++ /* software write pointer */
++ start = dma_cnt(readl(priv->gmac_iobase + RX_FQ_WR_ADDR));
++ /* logic read pointer */
++ end = dma_cnt(readl(priv->gmac_iobase + RX_FQ_RD_ADDR));
++ num = CIRC_SPACE(start, end, RX_DESC_NUM);
+
-+ for (i = 0, pos = start; i < num; i++) {
-+ if (priv->rx_fq.skb[pos] || priv->rx_skb[pos]) {
-+ break;
-+ }
++ for (i = 0, pos = start; i < num; i++) {
++ if (priv->rx_fq.skb[pos] || priv->rx_skb[pos])
++ break;
+
-+ skb = netdev_alloc_skb_ip_align(priv->netdev, len);
-+ if (unlikely(!skb)) {
-+ break;
-+ }
++ skb = netdev_alloc_skb_ip_align(priv->netdev, len);
++ if (unlikely(!skb))
++ break;
+
-+ if (!HAS_CAP_CCI(priv->hw_cap)) {
-+ addr = dma_map_single(priv->dev, skb->data, len,
-+ DMA_FROM_DEVICE);
-+ if (dma_mapping_error(priv->dev, addr)) {
-+ dev_kfree_skb_any(skb);
-+ break;
-+ }
-+ } else {
-+ addr = virt_to_phys(skb->data);
-+ }
++ if (!HAS_CAP_CCI(priv->hw_cap)) {
++ addr = dma_map_single(priv->dev, skb->data, len,
++ DMA_FROM_DEVICE);
++ if (dma_mapping_error(priv->dev, addr)) {
++ dev_kfree_skb_any(skb);
++ break;
++ }
++ } else {
++ addr = virt_to_phys(skb->data);
++ }
+
-+ desc = priv->rx_fq.desc + pos;
-+ desc->data_buff_addr = (u32)addr;
++ desc = priv->rx_fq.desc + pos;
++ desc->data_buff_addr = (u32)addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ desc->reserve31 = addr >> REG_BIT_WIDTH;
++ desc->reserve31 = addr >> REG_BIT_WIDTH;
+#endif
-+ priv->rx_fq.skb[pos] = skb;
-+ priv->rx_skb[pos] = skb;
++ priv->rx_fq.skb[pos] = skb;
++ priv->rx_skb[pos] = skb;
+
-+ desc->buffer_len = len - 1;
-+ desc->data_len = 0;
-+ desc->fl = 0;
-+ desc->descvid = DESC_VLD_FREE;
-+ desc->skb_id = pos;
++ desc->buffer_len = len - 1;
++ desc->data_len = 0;
++ desc->fl = 0;
++ desc->descvid = DESC_VLD_FREE;
++ desc->skb_id = pos;
+
-+ refill_cnt++;
-+ pos = dma_ring_incr(pos, RX_DESC_NUM);
-+ }
++ refill_cnt++;
++ pos = dma_ring_incr(pos, RX_DESC_NUM);
++ }
+
-+ /* This barrier is important here. It is required to ensure
-+ * the ARM CPU flushes it's DMA write buffers before proceeding
-+ * to the next instruction, to ensure that GMAC will see
-+ * our descriptor changes in memory
-+ */
-+ HIGMAC_SYNC_BARRIER();
++ /* This barrier is important here. It is required to ensure
++ * the ARM CPU flushes it's DMA write buffers before proceeding
++ * to the next instruction, to ensure that GMAC will see
++ * our descriptor changes in memory
++ */
++ HIGMAC_SYNC_BARRIER();
+
-+ if (pos != start) {
-+ writel(dma_byte(pos), priv->gmac_iobase + RX_FQ_WR_ADDR);
-+ }
++ if (pos != start)
++ writel(dma_byte(pos), priv->gmac_iobase + RX_FQ_WR_ADDR);
+
-+ return refill_cnt;
++ return refill_cnt;
+}
+
+static int higmac_rx(struct net_device *dev, int limit, int rxq_id)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(dev);
-+ struct sk_buff *skb;
-+ struct higmac_desc *desc;
-+ dma_addr_t addr;
-+ u32 start, end, num, pos, i, len;
-+ u32 rx_bq_rd_reg, rx_bq_wr_reg;
-+ u16 skb_id;
++ struct higmac_netdev_local *ld = netdev_priv(dev);
++ struct sk_buff *skb = NULL;
++ struct higmac_desc *desc = NULL;
++ dma_addr_t addr;
++ u32 start, end, num, pos, i, len;
++ u32 rx_bq_rd_reg, rx_bq_wr_reg;
++ u16 skb_id;
+
-+ rx_bq_rd_reg = RX_BQ_RD_ADDR_QUEUE(rxq_id);
-+ rx_bq_wr_reg = RX_BQ_WR_ADDR_QUEUE(rxq_id);
++ rx_bq_rd_reg = RX_BQ_RD_ADDR_QUEUE(rxq_id);
++ rx_bq_wr_reg = RX_BQ_WR_ADDR_QUEUE(rxq_id);
+
-+ /* software read pointer */
-+ start = dma_cnt(readl(ld->gmac_iobase + rx_bq_rd_reg));
-+ /* logic write pointer */
-+ end = dma_cnt(readl(ld->gmac_iobase + rx_bq_wr_reg));
-+ num = CIRC_CNT(end, start, RX_DESC_NUM);
-+ if (num > limit) {
-+ num = limit;
-+ }
++ /* software read pointer */
++ start = dma_cnt(readl(ld->gmac_iobase + rx_bq_rd_reg));
++ /* logic write pointer */
++ end = dma_cnt(readl(ld->gmac_iobase + rx_bq_wr_reg));
++ num = CIRC_CNT(end, start, RX_DESC_NUM);
++ if (num > limit)
++ num = limit;
+
-+ /* ensure get updated desc */
-+ rmb();
-+ for (i = 0, pos = start; i < num; i++) {
-+ if (rxq_id) {
-+ desc = ld->pool[3 + rxq_id].desc + pos;
-+ } else {
-+ desc = ld->rx_bq.desc + pos;
-+ }
-+ skb_id = desc->skb_id;
++ /* ensure get updated desc */
++ rmb();
++ for (i = 0, pos = start; i < num; i++) {
++ if (rxq_id)
++ desc = ld->pool[3 + rxq_id].desc + pos;
++ else
++ desc = ld->rx_bq.desc + pos;
++ skb_id = desc->skb_id;
+
-+ spin_lock(&ld->rxlock);
-+ skb = ld->rx_skb[skb_id];
-+ if (unlikely(!skb)) {
-+ spin_unlock(&ld->rxlock);
-+ netdev_err(dev, "inconsistent rx_skb\n");
-+ break;
-+ }
++ spin_lock(&ld->rxlock);
++ skb = ld->rx_skb[skb_id];
++ if (unlikely(!skb)) {
++ spin_unlock(&ld->rxlock);
++ netdev_err(dev, "inconsistent rx_skb\n");
++ break;
++ }
+
-+ /* data consistent check */
-+ if (unlikely(skb != ld->rx_fq.skb[skb_id])) {
-+ netdev_err(dev, "desc->skb(0x%p),rx_fq.skb[%d](0x%p)\n",
-+ skb, skb_id, ld->rx_fq.skb[skb_id]);
-+ if (ld->rx_fq.skb[skb_id] == SKB_MAGIC) {
-+ spin_unlock(&ld->rxlock);
-+ goto next;
-+ }
-+ WARN_ON(1);
-+ } else {
-+ ld->rx_fq.skb[skb_id] = NULL;
-+ }
-+ spin_unlock(&ld->rxlock);
++ /* data consistent check */
++ if (unlikely(skb != ld->rx_fq.skb[skb_id])) {
++ netdev_err(dev, "desc->skb(0x%p),rx_fq.skb[%d](0x%p)\n",
++ skb, skb_id, ld->rx_fq.skb[skb_id]);
++ if (ld->rx_fq.skb[skb_id] == SKB_MAGIC) {
++ spin_unlock(&ld->rxlock);
++ goto next;
++ }
++ WARN_ON(1);
++ } else {
++ ld->rx_fq.skb[skb_id] = NULL;
++ }
++ spin_unlock(&ld->rxlock);
+
-+ len = desc->data_len;
++ len = desc->data_len;
+
-+ if (!HAS_CAP_CCI(ld->hw_cap)) {
-+ addr = desc->data_buff_addr;
++ if (!HAS_CAP_CCI(ld->hw_cap)) {
++ addr = desc->data_buff_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ addr |= (dma_addr_t)(desc->reserve31) << REG_BIT_WIDTH;
++ addr |= (dma_addr_t)(desc->reserve31) << REG_BIT_WIDTH;
+#endif
-+ dma_unmap_single(ld->dev, addr, HIETH_MAX_FRAME_SIZE,
-+ DMA_FROM_DEVICE);
-+ }
++ dma_unmap_single(ld->dev, addr, HIETH_MAX_FRAME_SIZE,
++ DMA_FROM_DEVICE);
++ }
+
-+ skb_put(skb, len);
-+ if (skb->len > HIETH_MAX_FRAME_SIZE) {
-+ netdev_err(dev, "rcv len err, len = %d\n", skb->len);
-+ dev->stats.rx_errors++;
-+ dev->stats.rx_length_errors++;
-+ dev_kfree_skb_any(skb);
-+ goto next;
-+ }
++ skb_put(skb, len);
++ if (skb->len > HIETH_MAX_FRAME_SIZE) {
++ netdev_err(dev, "rcv len err, len = %d\n", skb->len);
++ dev->stats.rx_errors++;
++ dev->stats.rx_length_errors++;
++ dev_kfree_skb_any(skb);
++ goto next;
++ }
+
-+ skb->protocol = eth_type_trans(skb, dev);
-+ skb->ip_summed = CHECKSUM_NONE;
++ skb->protocol = eth_type_trans(skb, dev);
++ skb->ip_summed = CHECKSUM_NONE;
+#if defined(CONFIG_HIGMAC_RXCSUM)
-+ if (dev->features & NETIF_F_RXCSUM) {
-+ int hdr_csum_done =
-+ desc->header_csum_done;
-+ int payload_csum_done =
-+ desc->payload_csum_done;
-+ int hdr_csum_err =
-+ desc->header_csum_err;
-+ int payload_csum_err =
-+ desc->payload_csum_err;
++ if (dev->features & NETIF_F_RXCSUM) {
++ int hdr_csum_done =
++ desc->header_csum_done;
++ int payload_csum_done =
++ desc->payload_csum_done;
++ int hdr_csum_err =
++ desc->header_csum_err;
++ int payload_csum_err =
++ desc->payload_csum_err;
+
-+ if (hdr_csum_done && payload_csum_done) {
-+ if (unlikely(hdr_csum_err ||
-+ payload_csum_err)) {
-+ dev->stats.rx_errors++;
-+ dev->stats.rx_crc_errors++;
-+ dev_kfree_skb_any(skb);
-+ goto next;
-+ } else {
-+ skb->ip_summed = CHECKSUM_UNNECESSARY;
-+ }
-+ }
-+ }
++ if (hdr_csum_done && payload_csum_done) {
++ if (unlikely(hdr_csum_err ||
++ payload_csum_err)) {
++ dev->stats.rx_errors++;
++ dev->stats.rx_crc_errors++;
++ dev_kfree_skb_any(skb);
++ goto next;
++ } else {
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++ }
++ }
++ }
+#endif
-+ if ((dev->features & NETIF_F_RXHASH) && desc->has_hash) {
-+ skb_set_hash(skb, desc->rxhash, desc->l3_hash ? PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4);
-+ }
++ if ((dev->features & NETIF_F_RXHASH) && desc->has_hash)
++ skb_set_hash(skb, desc->rxhash, desc->l3_hash ?
++ PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4);
+
-+ skb_record_rx_queue(skb, rxq_id);
++ skb_record_rx_queue(skb, rxq_id);
+
-+ napi_gro_receive(&ld->q_napi[rxq_id].napi, skb);
-+ dev->stats.rx_packets++;
-+ dev->stats.rx_bytes += len;
-+ dev->last_rx = jiffies;
++ napi_gro_receive(&ld->q_napi[rxq_id].napi, skb);
++ dev->stats.rx_packets++;
++ dev->stats.rx_bytes += len;
++ dev->last_rx = jiffies;
+next:
-+ spin_lock(&ld->rxlock);
-+ ld->rx_skb[skb_id] = NULL;
-+ spin_unlock(&ld->rxlock);
-+ pos = dma_ring_incr(pos, RX_DESC_NUM);
-+ }
++ spin_lock(&ld->rxlock);
++ ld->rx_skb[skb_id] = NULL;
++ spin_unlock(&ld->rxlock);
++ pos = dma_ring_incr(pos, RX_DESC_NUM);
++ }
+
-+ if (pos != start) {
-+ writel(dma_byte(pos), ld->gmac_iobase + rx_bq_rd_reg);
-+ }
++ if (pos != start)
++ writel(dma_byte(pos), ld->gmac_iobase + rx_bq_rd_reg);
+
-+ spin_lock(&ld->rxlock);
-+ higmac_rx_refill(ld);
-+ spin_unlock(&ld->rxlock);
++ spin_lock(&ld->rxlock);
++ higmac_rx_refill(ld);
++ spin_unlock(&ld->rxlock);
+
-+ return num;
++ return num;
+}
+
+#ifdef HIGMAC_TSO_DEBUG
@@ -313952,2093 +382379,2001 @@ index 0000000..5d172c3
+#endif
+
+static int higmac_check_tx_err(struct higmac_netdev_local *ld,
-+ struct higmac_tso_desc *tx_bq_desc,
-+ unsigned int desc_pos)
++ struct higmac_tso_desc *tx_bq_desc,
++ unsigned int desc_pos)
+{
-+ unsigned int tx_err = tx_bq_desc->tx_err;
++ unsigned int tx_err = tx_bq_desc->tx_err;
+
-+ if (unlikely(tx_err & ERR_ALL)) {
-+ struct sg_desc *desc_cur;
-+ int *sg_word;
-+ int i;
++ if (unlikely(tx_err & ERR_ALL)) {
++ struct sg_desc *desc_cur = NULL;
++ int *sg_word = NULL;
++ int i;
+
-+ WARN((tx_err & ERR_ALL),
-+ "TX ERR: desc1=0x%x, desc2=0x%x, desc5=0x%x\n",
-+ tx_bq_desc->data_buff_addr,
-+ tx_bq_desc->desc1.val, tx_bq_desc->tx_err);
++ WARN((tx_err & ERR_ALL),
++ "TX ERR: desc1=0x%x, desc2=0x%x, desc5=0x%x\n",
++ tx_bq_desc->data_buff_addr,
++ tx_bq_desc->desc1.val, tx_bq_desc->tx_err);
+
-+ desc_cur = ld->dma_sg_desc + ld->tx_bq.sg_desc_offset[desc_pos];
-+ sg_word = (int *)desc_cur;
-+ for (i = 0; i < sizeof(struct sg_desc) / sizeof(int); i++) {
-+ pr_err("%s,%d: sg_desc word[%d]=0x%x\n",
-+ __func__, __LINE__, i, sg_word[i]);
-+ }
-+ return -1;
-+ }
++ desc_cur = ld->dma_sg_desc + ld->tx_bq.sg_desc_offset[desc_pos];
++ sg_word = (int *)desc_cur;
++ for (i = 0; i < sizeof(struct sg_desc) / sizeof(int); i++)
++ pr_err("%s,%d: sg_desc word[%d]=0x%x\n",
++ __func__, __LINE__, i, sg_word[i]);
+
-+ return 0;
++ return -1;
++ }
++
++ return 0;
+}
+
+static int higmac_xmit_release_gso(struct higmac_netdev_local *ld,
-+ struct higmac_tso_desc *tx_rq_desc,
-+ unsigned int desc_pos)
++ struct higmac_tso_desc *tx_rq_desc,
++ unsigned int desc_pos)
+{
-+ int pkt_type;
-+ int nfrags = tx_rq_desc->desc1.tx.nfrags_num;
-+ dma_addr_t addr;
-+ size_t len;
++ int pkt_type;
++ int nfrags = tx_rq_desc->desc1.tx.nfrags_num;
++ dma_addr_t addr;
++ size_t len;
+
-+ if (unlikely(higmac_check_tx_err(ld, tx_rq_desc, desc_pos) < 0)) {
-+ /* dev_close */
-+ higmac_irq_disable_all_queue(ld);
-+ higmac_hw_desc_disable(ld);
++ if (unlikely(higmac_check_tx_err(ld, tx_rq_desc, desc_pos) < 0)) {
++ /* dev_close */
++ higmac_irq_disable_all_queue(ld);
++ higmac_hw_desc_disable(ld);
+
-+ netif_carrier_off(ld->netdev);
-+ netif_stop_queue(ld->netdev);
++ netif_carrier_off(ld->netdev);
++ netif_stop_queue(ld->netdev);
+
-+ phy_stop(ld->phy);
-+ del_timer_sync(&ld->monitor);
-+ return -1;
-+ }
++ phy_stop(ld->phy);
++ del_timer_sync(&ld->monitor);
++ return -1;
++ }
+
-+ if (tx_rq_desc->desc1.tx.tso_flag || nfrags) {
-+ pkt_type = PKT_SG;
-+ } else {
-+ pkt_type = PKT_NORMAL;
-+ }
++ if (tx_rq_desc->desc1.tx.tso_flag || nfrags)
++ pkt_type = PKT_SG;
++ else
++ pkt_type = PKT_NORMAL;
+
-+ if (pkt_type == PKT_NORMAL) {
-+ if (!HAS_CAP_CCI(ld->hw_cap)) {
-+ addr = tx_rq_desc->data_buff_addr;
++ if (pkt_type == PKT_NORMAL) {
++ if (!HAS_CAP_CCI(ld->hw_cap)) {
++ addr = tx_rq_desc->data_buff_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ addr |= (dma_addr_t)(tx_rq_desc->reserve_desc2 &
-+ TX_DESC_HI8_MASK)
-+ << REG_BIT_WIDTH;
++ addr |= (dma_addr_t)(tx_rq_desc->reserve_desc2 &
++ TX_DESC_HI8_MASK) <<
++ REG_BIT_WIDTH;
+#endif
-+ len = tx_rq_desc->desc1.tx.data_len;
-+ dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE);
-+ }
-+ } else {
-+ if (!HAS_CAP_CCI(ld->hw_cap)) {
-+ struct sg_desc *desc_cur;
-+ unsigned int desc_offset;
-+ int i;
++ len = tx_rq_desc->desc1.tx.data_len;
++ dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE);
++ }
++ } else {
++ if (!HAS_CAP_CCI(ld->hw_cap)) {
++ struct sg_desc *desc_cur = NULL;
++ unsigned int desc_offset;
++ int i;
+
-+ desc_offset = ld->tx_bq.sg_desc_offset[desc_pos];
-+ WARN_ON(desc_offset != ld->sg_tail);
-+ desc_cur = ld->dma_sg_desc + desc_offset;
++ desc_offset = ld->tx_bq.sg_desc_offset[desc_pos];
++ WARN_ON(desc_offset != ld->sg_tail);
++ desc_cur = ld->dma_sg_desc + desc_offset;
+
-+ addr = desc_cur->linear_addr;
++ addr = desc_cur->linear_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ addr |= (dma_addr_t)(desc_cur->reserv3 >>
-+ SG_DESC_HI8_OFFSET)
-+ << REG_BIT_WIDTH;
++ addr |= (dma_addr_t)(desc_cur->reserv3 >>
++ SG_DESC_HI8_OFFSET) <<
++ REG_BIT_WIDTH;
+#endif
-+ len = desc_cur->linear_len;
-+ dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE);
-+ for (i = 0; i < nfrags; i++) {
-+ addr = desc_cur->frags[i].addr;
++ len = desc_cur->linear_len;
++ dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE);
++ for (i = 0; i < nfrags; i++) {
++ addr = desc_cur->frags[i].addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ addr |= (dma_addr_t)(desc_cur->frags[i].reserved >>
-+ SG_DESC_HI8_OFFSET)
-+ << REG_BIT_WIDTH;
++ addr |= (dma_addr_t)
++ (desc_cur->frags[i].reserved >>
++ SG_DESC_HI8_OFFSET) <<
++ REG_BIT_WIDTH;
+#endif
-+ len = desc_cur->frags[i].size;
-+ dma_unmap_page(ld->dev, addr, len,
-+ DMA_TO_DEVICE);
-+ }
-+ }
++ len = desc_cur->frags[i].size;
++ dma_unmap_page(ld->dev, addr, len,
++ DMA_TO_DEVICE);
++ }
++ }
+
-+ ld->sg_tail = (ld->sg_tail + 1) % ld->sg_count;
-+ }
++ ld->sg_tail = (ld->sg_tail + 1) % ld->sg_count;
++ }
+
+#ifdef HIGMAC_TSO_DEBUG
-+ pkt_rec[id_free].status = 0;
-+ id_free++;
-+ if (id_free == MAX_RECORD) {
-+ id_free = 0;
-+ }
++ if (id_free >= MAX_RECORD)
++ id_free = 0;
++ pkt_rec[id_free].status = 0;
++ id_free++;
+#endif
+
-+ return 0;
++ return 0;
+}
+
+static void higmac_xmit_reclaim(struct net_device *dev)
+{
-+ struct sk_buff *skb;
-+ struct higmac_desc *desc;
-+ struct higmac_tso_desc *tso_desc;
-+ struct higmac_netdev_local *priv = netdev_priv(dev);
-+ unsigned int bytes_compl = 0, pkts_compl = 0;
-+ u32 start, end, num, pos, i;
-+ dma_addr_t addr;
-+ int ret;
++ struct sk_buff *skb = NULL;
++ struct higmac_desc *desc = NULL;
++ struct higmac_tso_desc *tso_desc = NULL;
++ struct higmac_netdev_local *priv = netdev_priv(dev);
++ unsigned int bytes_compl = 0, pkts_compl = 0;
++ u32 start, end, num, pos, i;
++ dma_addr_t addr;
++ int ret;
+
-+ spin_lock(&priv->txlock);
++ spin_lock(&priv->txlock);
+
-+ /* software read */
-+ start = dma_cnt(readl(priv->gmac_iobase + TX_RQ_RD_ADDR));
-+ /* logic write */
-+ end = dma_cnt(readl(priv->gmac_iobase + TX_RQ_WR_ADDR));
-+ num = CIRC_CNT(end, start, TX_DESC_NUM);
++ /* software read */
++ start = dma_cnt(readl(priv->gmac_iobase + TX_RQ_RD_ADDR));
++ /* logic write */
++ end = dma_cnt(readl(priv->gmac_iobase + TX_RQ_WR_ADDR));
++ num = CIRC_CNT(end, start, TX_DESC_NUM);
+
-+ for (i = 0, pos = start; i < num; i++) {
-+ skb = priv->tx_skb[pos];
-+ if (unlikely(!skb)) {
-+ netdev_err(dev, "inconsistent tx_skb\n");
-+ break;
-+ }
++ for (i = 0, pos = start; i < num; i++) {
++ skb = priv->tx_skb[pos];
++ if (unlikely(!skb)) {
++ netdev_err(dev, "inconsistent tx_skb\n");
++ break;
++ }
+
-+ if (skb != priv->tx_bq.skb[pos]) {
-+ netdev_err(dev, "wired, tx skb[%d](%p) != skb(%p)\n",
-+ pos, priv->tx_bq.skb[pos], skb);
-+ if (priv->tx_bq.skb[pos] == SKB_MAGIC) {
-+ goto next;
-+ }
-+ }
++ if (skb != priv->tx_bq.skb[pos]) {
++ netdev_err(dev, "wired, tx skb[%d](%p) != skb(%p)\n",
++ pos, priv->tx_bq.skb[pos], skb);
++ if (priv->tx_bq.skb[pos] == SKB_MAGIC)
++ goto next;
++ }
+
-+ pkts_compl++;
-+ bytes_compl += skb->len;
-+ desc = priv->tx_rq.desc + pos;
-+ if (priv->tso_supported) {
-+ tso_desc = (struct higmac_tso_desc *)desc;
-+ ret = higmac_xmit_release_gso(priv, tso_desc, pos);
-+ if (ret < 0) {
-+ break;
-+ }
-+ } else if (!HAS_CAP_CCI(priv->hw_cap)) {
-+ addr = desc->data_buff_addr;
++ pkts_compl++;
++ bytes_compl += skb->len;
++ desc = priv->tx_rq.desc + pos;
++ if (priv->tso_supported) {
++ tso_desc = (struct higmac_tso_desc *)desc;
++ ret = higmac_xmit_release_gso(priv, tso_desc, pos);
++ if (ret < 0)
++ break;
++ } else if (!HAS_CAP_CCI(priv->hw_cap)) {
++ addr = desc->data_buff_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ addr |= (dma_addr_t)(desc->rxhash &
-+ TX_DESC_HI8_MASK)
-+ << REG_BIT_WIDTH;
++ addr |= (dma_addr_t)(desc->rxhash &
++ TX_DESC_HI8_MASK) <<
++ REG_BIT_WIDTH;
+#endif
-+ dma_unmap_single(priv->dev, addr, skb->len,
-+ DMA_TO_DEVICE);
-+ }
-+ priv->tx_bq.skb[pos] = NULL;
++ dma_unmap_single(priv->dev, addr, skb->len,
++ DMA_TO_DEVICE);
++ }
++ priv->tx_bq.skb[pos] = NULL;
+next:
-+ priv->tx_skb[pos] = NULL;
-+ dev_consume_skb_any(skb);
-+ pos = dma_ring_incr(pos, TX_DESC_NUM);
-+ }
++ priv->tx_skb[pos] = NULL;
++ dev_consume_skb_any(skb);
++ pos = dma_ring_incr(pos, TX_DESC_NUM);
++ }
+
-+ if (pos != start) {
-+ writel(dma_byte(pos), priv->gmac_iobase + TX_RQ_RD_ADDR);
-+ }
++ if (pos != start)
++ writel(dma_byte(pos), priv->gmac_iobase + TX_RQ_RD_ADDR);
+
-+ if (pkts_compl || bytes_compl) {
-+ netdev_completed_queue(dev, pkts_compl, bytes_compl);
-+ }
++ if (pkts_compl || bytes_compl)
++ netdev_completed_queue(dev, pkts_compl, bytes_compl);
+
-+ if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl) {
-+ netif_wake_queue(priv->netdev);
-+ }
++ if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl)
++ netif_wake_queue(priv->netdev);
+
-+ spin_unlock(&priv->txlock);
++ spin_unlock(&priv->txlock);
+}
+
+static int higmac_poll(struct napi_struct *napi, int budget)
+{
-+ struct higmac_napi *q_napi = container_of(napi,
-+ struct higmac_napi, napi);
-+ struct higmac_netdev_local *priv = q_napi->ndev_priv;
-+ struct net_device *dev = priv->netdev;
-+ int work_done = 0, task = budget;
-+ u32 ints, num;
-+ u32 raw_int_reg, raw_int_mask;
++ struct higmac_napi *q_napi = container_of(napi,
++ struct higmac_napi, napi);
++ struct higmac_netdev_local *priv = q_napi->ndev_priv;
++ struct net_device *dev = NULL;
++ int work_done = 0, task = budget;
++ u32 ints, num;
++ u32 raw_int_reg, raw_int_mask;
+
-+ if (q_napi->rxq_id) {
-+ raw_int_reg = RSS_RAW_PMU_INT;
-+ raw_int_mask = DEF_INT_MASK_QUEUE(q_napi->rxq_id);
-+ } else {
-+ raw_int_reg = RAW_PMU_INT;
-+ raw_int_mask = DEF_INT_MASK;
-+ }
++ dev_hold(priv->netdev);
++ dev = priv->netdev;
++ if (q_napi->rxq_id) {
++ raw_int_reg = RSS_RAW_PMU_INT;
++ raw_int_mask = DEF_INT_MASK_QUEUE((u32)q_napi->rxq_id);
++ } else {
++ raw_int_reg = RAW_PMU_INT;
++ raw_int_mask = DEF_INT_MASK;
++ }
+
-+ do {
-+ if (!q_napi->rxq_id) {
-+ higmac_xmit_reclaim(dev);
-+ }
-+ num = higmac_rx(dev, task, q_napi->rxq_id);
-+ work_done += num;
-+ task -= num;
-+ if (work_done >= budget) {
-+ break;
-+ }
++ do {
++ if (!q_napi->rxq_id)
++ higmac_xmit_reclaim(dev);
++ num = higmac_rx(dev, task, q_napi->rxq_id);
++ work_done += num;
++ task -= num;
++ if (work_done >= budget)
++ break;
+
-+ ints = readl(priv->gmac_iobase + raw_int_reg);
-+ ints &= raw_int_mask;
-+ writel(ints, priv->gmac_iobase + raw_int_reg);
-+ } while (ints || higmac_rxq_has_packets(priv, q_napi->rxq_id));
++ ints = readl(priv->gmac_iobase + raw_int_reg);
++ ints &= raw_int_mask;
++ writel(ints, priv->gmac_iobase + raw_int_reg);
++ } while (ints || higmac_rxq_has_packets(priv, q_napi->rxq_id));
+
-+ if (work_done < budget) {
-+ napi_complete(napi);
-+ higmac_irq_enable_queue(priv, q_napi->rxq_id);
-+ }
++ if (work_done < budget) {
++ napi_complete(napi);
++ higmac_irq_enable_queue(priv, q_napi->rxq_id);
++ }
+
-+ return work_done;
++ dev_put(dev);
++ return work_done;
+}
+
+static irqreturn_t higmac_interrupt(int irq, void *dev_id)
+{
-+ struct higmac_napi *q_napi = (struct higmac_napi *)dev_id;
-+ struct higmac_netdev_local *ld = q_napi->ndev_priv;
-+ u32 ints;
-+ u32 raw_int_reg, raw_int_mask;
++ struct higmac_napi *q_napi = (struct higmac_napi *)dev_id;
++ struct higmac_netdev_local *ld = q_napi->ndev_priv;
++ u32 ints;
++ u32 raw_int_reg, raw_int_mask;
+
-+ if (higmac_queue_irq_disabled(ld, q_napi->rxq_id)) {
-+ return IRQ_NONE;
-+ }
++ if (higmac_queue_irq_disabled(ld, q_napi->rxq_id))
++ return IRQ_NONE;
+
-+ if (q_napi->rxq_id) {
-+ raw_int_reg = RSS_RAW_PMU_INT;
-+ raw_int_mask = DEF_INT_MASK_QUEUE(q_napi->rxq_id);
-+ } else {
-+ raw_int_reg = RAW_PMU_INT;
-+ raw_int_mask = DEF_INT_MASK;
-+ }
++ if (q_napi->rxq_id) {
++ raw_int_reg = RSS_RAW_PMU_INT;
++ raw_int_mask = DEF_INT_MASK_QUEUE((u32)q_napi->rxq_id);
++ } else {
++ raw_int_reg = RAW_PMU_INT;
++ raw_int_mask = DEF_INT_MASK;
++ }
+
-+ ints = readl(ld->gmac_iobase + raw_int_reg);
-+ ints &= raw_int_mask;
-+ writel(ints, ld->gmac_iobase + raw_int_reg);
++ ints = readl(ld->gmac_iobase + raw_int_reg);
++ ints &= raw_int_mask;
++ writel(ints, ld->gmac_iobase + raw_int_reg);
+
-+ if (likely(ints || higmac_rxq_has_packets(ld, q_napi->rxq_id))) {
-+ higmac_irq_disable_queue(ld, q_napi->rxq_id);
-+ napi_schedule(&q_napi->napi);
-+ }
++ if (likely(ints || higmac_rxq_has_packets(ld, q_napi->rxq_id))) {
++ higmac_irq_disable_queue(ld, q_napi->rxq_id);
++ napi_schedule(&q_napi->napi);
++ }
+
-+ return IRQ_HANDLED;
++ return IRQ_HANDLED;
+}
+
+static inline __be16 higmac_get_l3_proto(struct sk_buff *skb)
+{
-+ __be16 l3_proto;
++ __be16 l3_proto;
+
-+ l3_proto = skb->protocol;
-+ if (skb->protocol == htons(ETH_P_8021Q)) {
-+ l3_proto = vlan_get_protocol(skb);
-+ }
++ l3_proto = skb->protocol;
++ if (skb->protocol == htons(ETH_P_8021Q))
++ l3_proto = vlan_get_protocol(skb);
+
-+ return l3_proto;
++ return l3_proto;
+}
+
+static inline unsigned int higmac_get_l4_proto(struct sk_buff *skb)
+{
-+ __be16 l3_proto;
-+ unsigned int l4_proto = IPPROTO_MAX;
++ __be16 l3_proto;
++ unsigned int l4_proto = IPPROTO_MAX;
+
-+ l3_proto = higmac_get_l3_proto(skb);
-+ if (l3_proto == htons(ETH_P_IP)) {
-+ l4_proto = ip_hdr(skb)->protocol;
-+ } else if (l3_proto == htons(ETH_P_IPV6)) {
-+ l4_proto = ipv6_hdr(skb)->nexthdr;
-+ }
++ l3_proto = higmac_get_l3_proto(skb);
++ if (l3_proto == htons(ETH_P_IP))
++ l4_proto = ip_hdr(skb)->protocol;
++ else if (l3_proto == htons(ETH_P_IPV6))
++ l4_proto = ipv6_hdr(skb)->nexthdr;
+
-+ return l4_proto;
++ return l4_proto;
+}
+
+static inline bool higmac_skb_is_ipv6(struct sk_buff *skb)
+{
-+ return (higmac_get_l3_proto(skb) == htons(ETH_P_IPV6));
++ return (higmac_get_l3_proto(skb) == htons(ETH_P_IPV6));
+}
+
+static inline bool higmac_skb_is_udp(struct sk_buff *skb)
+{
-+ return (higmac_get_l4_proto(skb) == IPPROTO_UDP);
++ return (higmac_get_l4_proto(skb) == IPPROTO_UDP);
+}
+
+static int higmac_check_hw_capability_for_udp(struct sk_buff *skb)
+{
-+ struct ethhdr *eth;
++ struct ethhdr *eth;
+
-+ /* hardware can't dea with UFO broadcast packet */
-+ eth = (struct ethhdr *)(skb->data);
-+ if (skb_is_gso(skb) && is_broadcast_ether_addr(eth->h_dest)) {
-+ return -ENOTSUPP;
-+ }
++ /* hardware can't dea with UFO broadcast packet */
++ eth = (struct ethhdr *)(skb->data);
++ if (skb_is_gso(skb) && is_broadcast_ether_addr(eth->h_dest))
++ return -ENOTSUPP;
+
-+ return 0;
++ return 0;
+}
+
+static int higmac_check_hw_capability_for_ipv6(struct sk_buff *skb)
+{
-+ unsigned int l4_proto = IPPROTO_MAX;
++ unsigned int l4_proto;
+
-+ l4_proto = ipv6_hdr(skb)->nexthdr;
++ l4_proto = ipv6_hdr(skb)->nexthdr;
+
-+ if ((l4_proto != IPPROTO_TCP) && (l4_proto != IPPROTO_UDP)) {
-+ /* when IPv6 next header is not tcp or udp,
-+ * it means that IPv6 next header is extension header.
-+ * Hardware can't deal with this case,
-+ * so do checksumming by software or do GSO by software.
-+ */
-+ if (skb_is_gso(skb)) {
-+ return -ENOTSUPP;
-+ }
++ if ((l4_proto != IPPROTO_TCP) && (l4_proto != IPPROTO_UDP)) {
++ /* when IPv6 next header is not tcp or udp,
++ * it means that IPv6 next header is extension header.
++ * Hardware can't deal with this case,
++ * so do checksumming by software or do GSO by software.
++ */
++ if (skb_is_gso(skb))
++ return -ENOTSUPP;
+
-+ if (skb->ip_summed == CHECKSUM_PARTIAL &&
-+ skb_checksum_help(skb)) {
-+ return -EFAULT;
-+ }
-+ }
++ if (skb->ip_summed == CHECKSUM_PARTIAL &&
++ skb_checksum_help(skb))
++ return -EFAULT;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static inline bool higmac_skb_is_ipv4_with_options(struct sk_buff *skb)
+{
-+ return ((higmac_get_l3_proto(skb) == htons(ETH_P_IP)) &&
-+ (ip_hdr(skb)->ihl > 5));
++ return ((higmac_get_l3_proto(skb) == htons(ETH_P_IP)) &&
++ (ip_hdr(skb)->ihl > 5));
+}
+
+static int higmac_check_hw_capability(struct sk_buff *skb)
+{
-+ int ret = 0;
++ int ret = 0;
+
-+ /* if tcp_mtu_probe() use (2 * tp->mss_cache) as probe_size,
-+ * the linear data length will be larger than 2048,
-+ * the MAC can't handle it, so let the software do it.
-+ */
-+ if (skb_is_gso(skb) && (skb_headlen(skb) > 2048)) {
-+ return -ENOTSUPP;
-+ }
++ /* if tcp_mtu_probe() use (2 * tp->mss_cache) as probe_size,
++ * the linear data length will be larger than 2048,
++ * the MAC can't handle it, so let the software do it.
++ */
++ if (skb_is_gso(skb) && (skb_headlen(skb) > 2048))
++ return -ENOTSUPP;
+
-+ if (higmac_skb_is_ipv6(skb)) {
-+ ret = higmac_check_hw_capability_for_ipv6(skb);
-+ if (ret) {
-+ return ret;
-+ }
-+ }
++ if (higmac_skb_is_ipv6(skb)) {
++ ret = higmac_check_hw_capability_for_ipv6(skb);
++ if (ret)
++ return ret;
++ }
+
-+ if (higmac_skb_is_udp(skb)) {
-+ ret = higmac_check_hw_capability_for_udp(skb);
-+ if (ret) {
-+ return ret;
-+ }
-+ }
++ if (higmac_skb_is_udp(skb)) {
++ ret = higmac_check_hw_capability_for_udp(skb);
++ if (ret)
++ return ret;
++ }
+
-+ if (((skb->ip_summed == CHECKSUM_PARTIAL) || skb_is_gso(skb)) &&
-+ higmac_skb_is_ipv4_with_options(skb)) {
-+ return -ENOTSUPP;
-+ }
++ if (((skb->ip_summed == CHECKSUM_PARTIAL) || skb_is_gso(skb)) &&
++ higmac_skb_is_ipv4_with_options(skb))
++ return -ENOTSUPP;
+
-+ return 0;
++ return 0;
+}
+
+static void higmac_do_udp_checksum(struct sk_buff *skb)
+{
-+ int offset;
-+ __wsum csum;
-+ __sum16 udp_csum;
++ int offset;
++ __wsum csum;
++ __sum16 udp_csum;
+
-+ offset = skb_checksum_start_offset(skb);
-+ WARN_ON(offset >= skb_headlen(skb));
-+ csum = skb_checksum(skb, offset, skb->len - offset, 0);
++ offset = skb_checksum_start_offset(skb);
++ WARN_ON(offset >= skb_headlen(skb));
++ csum = skb_checksum(skb, offset, skb->len - offset, 0);
+
-+ offset += skb->csum_offset;
-+ WARN_ON(offset + sizeof(__sum16) > skb_headlen(skb));
-+ udp_csum = csum_fold(csum);
-+ if (udp_csum == 0) {
-+ udp_csum = CSUM_MANGLED_0;
-+ }
++ offset += skb->csum_offset;
++ WARN_ON(offset + sizeof(__sum16) > skb_headlen(skb));
++ udp_csum = csum_fold(csum);
++ if (udp_csum == 0)
++ udp_csum = CSUM_MANGLED_0;
+
-+ *(__sum16 *)(skb->data + offset) = udp_csum;
++ *(__sum16 *)(skb->data + offset) = udp_csum;
+
-+ skb->ip_summed = CHECKSUM_NONE;
++ skb->ip_summed = CHECKSUM_NONE;
+}
+
-+static void higmac_get_pkt_info(struct higmac_netdev_local *ld,
-+ struct sk_buff *skb,
-+ struct higmac_tso_desc *tx_bq_desc)
++static int higmac_get_pkt_info(struct higmac_netdev_local *ld,
++ struct sk_buff *skb,
++ struct higmac_tso_desc *tx_bq_desc)
+{
-+ int nfrags = skb_shinfo(skb)->nr_frags;
++ int nfrags = skb_shinfo(skb)->nr_frags;
+
-+ __be16 l3_proto; /* level 3 protocol */
-+ unsigned int l4_proto = IPPROTO_MAX;
-+ unsigned int max_mss = ETH_DATA_LEN;
-+ unsigned char coe_enable = 0;
-+ int max_data_len = skb->len - ETH_HLEN;
++ __be16 l3_proto; /* level 3 protocol */
++ unsigned int l4_proto = IPPROTO_MAX;
++ unsigned int max_mss = ETH_DATA_LEN;
++ unsigned char coe_enable = 0;
++ int max_data_len = skb->len - ETH_HLEN;
+
-+ if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
-+ coe_enable = 1;
-+ }
++ if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
++ coe_enable = 1;
+
-+ tx_bq_desc->desc1.val = 0;
++ tx_bq_desc->desc1.val = 0;
+
-+ if (skb_is_gso(skb)) {
-+ tx_bq_desc->desc1.tx.tso_flag = 1;
-+ tx_bq_desc->desc1.tx.sg_flag = 1;
-+ } else if (nfrags) {
-+ tx_bq_desc->desc1.tx.sg_flag = 1;
-+ }
++ if (skb_is_gso(skb)) {
++ tx_bq_desc->desc1.tx.tso_flag = 1;
++ tx_bq_desc->desc1.tx.sg_flag = 1;
++ } else if (nfrags) {
++ tx_bq_desc->desc1.tx.sg_flag = 1;
++ }
+
-+ l3_proto = skb->protocol;
-+ if (skb->protocol == htons(ETH_P_8021Q)) {
-+ l3_proto = vlan_get_protocol(skb);
-+ tx_bq_desc->desc1.tx.vlan_flag = 1;
-+ max_data_len -= VLAN_HLEN;
-+ }
++ l3_proto = skb->protocol;
++ if (skb->protocol == htons(ETH_P_8021Q)) {
++ l3_proto = vlan_get_protocol(skb);
++ tx_bq_desc->desc1.tx.vlan_flag = 1;
++ max_data_len -= VLAN_HLEN;
++ }
+
-+ if (l3_proto == htons(ETH_P_IP)) {
-+ struct iphdr *iph;
++ if (l3_proto == htons(ETH_P_IP)) {
++ struct iphdr *iph;
+
-+ iph = ip_hdr(skb);
-+ tx_bq_desc->desc1.tx.ip_ver = PKT_IPV4;
-+ tx_bq_desc->desc1.tx.ip_hdr_len = iph->ihl;
++ iph = ip_hdr(skb);
++ tx_bq_desc->desc1.tx.ip_ver = PKT_IPV4;
++ tx_bq_desc->desc1.tx.ip_hdr_len = iph->ihl;
+
-+ if ((max_data_len >= GSO_MAX_SIZE) &&
-+ (ntohs(iph->tot_len) <= (iph->ihl << 2))) {
-+ iph->tot_len = htons(GSO_MAX_SIZE - 1);
-+ }
++ if ((max_data_len >= GSO_MAX_SIZE) &&
++ (ntohs(iph->tot_len) <= (iph->ihl << 2)))
++ iph->tot_len = htons(GSO_MAX_SIZE - 1);
+
-+ max_mss -= iph->ihl * WORD_TO_BYTE;
-+ l4_proto = iph->protocol;
-+ } else if (l3_proto == htons(ETH_P_IPV6)) {
-+ tx_bq_desc->desc1.tx.ip_ver = PKT_IPV6;
-+ tx_bq_desc->desc1.tx.ip_hdr_len = PKT_IPV6_HDR_LEN;
-+ max_mss -= PKT_IPV6_HDR_LEN * WORD_TO_BYTE;
-+ l4_proto = ipv6_hdr(skb)->nexthdr;
-+ } else {
-+ coe_enable = 0;
-+ }
++ max_mss -= iph->ihl * WORD_TO_BYTE;
++ l4_proto = iph->protocol;
++ } else if (l3_proto == htons(ETH_P_IPV6)) {
++ tx_bq_desc->desc1.tx.ip_ver = PKT_IPV6;
++ tx_bq_desc->desc1.tx.ip_hdr_len = PKT_IPV6_HDR_LEN;
++ max_mss -= PKT_IPV6_HDR_LEN * WORD_TO_BYTE;
++ l4_proto = ipv6_hdr(skb)->nexthdr;
++ } else {
++ coe_enable = 0;
++ }
+
-+ if (l4_proto == IPPROTO_TCP) {
-+ tx_bq_desc->desc1.tx.prot_type = PKT_TCP;
-+ tx_bq_desc->desc1.tx.prot_hdr_len = tcp_hdr(skb)->doff;
-+ max_mss -= tcp_hdr(skb)->doff * WORD_TO_BYTE;
-+ } else if (l4_proto == IPPROTO_UDP) {
-+ tx_bq_desc->desc1.tx.prot_type = PKT_UDP;
-+ tx_bq_desc->desc1.tx.prot_hdr_len = PKT_UDP_HDR_LEN;
-+ if (l3_proto == htons(ETH_P_IPV6)) {
-+ max_mss -= sizeof(struct frag_hdr);
-+ }
-+ } else {
-+ coe_enable = 0;
-+ }
++ if (l4_proto == IPPROTO_TCP) {
++ tx_bq_desc->desc1.tx.prot_type = PKT_TCP;
++ tx_bq_desc->desc1.tx.prot_hdr_len = tcp_hdr(skb)->doff;
++ max_mss -= tcp_hdr(skb)->doff * WORD_TO_BYTE;
++ } else if (l4_proto == IPPROTO_UDP) {
++ tx_bq_desc->desc1.tx.prot_type = PKT_UDP;
++ tx_bq_desc->desc1.tx.prot_hdr_len = PKT_UDP_HDR_LEN;
++ if (l3_proto == htons(ETH_P_IPV6))
++ max_mss -= sizeof(struct frag_hdr);
++ } else {
++ coe_enable = 0;
++ }
+
-+ if (skb_is_gso(skb)) {
-+ tx_bq_desc->desc1.tx.data_len =
-+ (skb_shinfo(skb)->gso_size > max_mss) ? max_mss : skb_shinfo(skb)->gso_size;
-+ } else {
-+ tx_bq_desc->desc1.tx.data_len = skb->len;
-+ }
++ if (skb_is_gso(skb))
++ tx_bq_desc->desc1.tx.data_len =
++ (skb_shinfo(skb)->gso_size > max_mss) ? max_mss :
++ skb_shinfo(skb)->gso_size;
++ else
++ tx_bq_desc->desc1.tx.data_len = skb->len;
+
-+ if (coe_enable && skb_is_gso(skb) && (l4_proto == IPPROTO_UDP)) {
-+ higmac_do_udp_checksum(skb);
-+ }
++ if (coe_enable && skb_is_gso(skb) && (l4_proto == IPPROTO_UDP))
++ higmac_do_udp_checksum(skb);
+
-+ if (coe_enable) {
-+ tx_bq_desc->desc1.tx.coe_flag = 1;
-+ }
++ if (coe_enable)
++ tx_bq_desc->desc1.tx.coe_flag = 1;
+
-+ tx_bq_desc->desc1.tx.nfrags_num = nfrags;
++ tx_bq_desc->desc1.tx.nfrags_num = nfrags;
+
-+ tx_bq_desc->desc1.tx.hw_own = DESC_VLD_BUSY;
++ tx_bq_desc->desc1.tx.hw_own = DESC_VLD_BUSY;
++ return 0;
+}
+
+static int higmac_xmit_gso(struct higmac_netdev_local *ld, struct sk_buff *skb,
-+ struct higmac_tso_desc *tx_bq_desc,
-+ unsigned int desc_pos)
++ struct higmac_tso_desc *tx_bq_desc,
++ unsigned int desc_pos)
+{
-+ int pkt_type = PKT_NORMAL;
-+ int nfrags = skb_shinfo(skb)->nr_frags;
-+ dma_addr_t addr;
-+ int ret;
++ int pkt_type = PKT_NORMAL;
++ int nfrags = skb_shinfo(skb)->nr_frags;
++ dma_addr_t addr;
++ int ret;
+
-+ if (skb_is_gso(skb) || nfrags) {
-+ /* TSO pkt or SG pkt */
-+ pkt_type = PKT_SG;
-+ } else { /* Normal pkt */
-+ pkt_type = PKT_NORMAL;
-+ }
++ if (skb_is_gso(skb) || nfrags) {
++ /* TSO pkt or SG pkt */
++ pkt_type = PKT_SG;
++ } else { /* Normal pkt */
++ pkt_type = PKT_NORMAL;
++ }
+
-+ ret = higmac_check_hw_capability(skb);
-+ if (unlikely(ret)) {
-+ return ret;
-+ }
++ ret = higmac_check_hw_capability(skb);
++ if (unlikely(ret))
++ return ret;
+
-+ higmac_get_pkt_info(ld, skb, tx_bq_desc);
++ ret = higmac_get_pkt_info(ld, skb, tx_bq_desc);
++ if (unlikely(ret))
++ return ret;
+
-+ if (pkt_type == PKT_NORMAL) {
-+ if (!HAS_CAP_CCI(ld->hw_cap)) {
-+ addr = dma_map_single(ld->dev, skb->data, skb->len,
-+ DMA_TO_DEVICE);
-+ ret = dma_mapping_error(ld->dev, addr);
-+ if (unlikely(ret)) {
-+ pr_err("Normal Packet DMA Mapping fail.\n");
-+ return -EFAULT;
-+ }
-+ tx_bq_desc->data_buff_addr = (u32)addr;
++ if (pkt_type == PKT_NORMAL) {
++ if (!HAS_CAP_CCI(ld->hw_cap)) {
++ addr = dma_map_single(ld->dev, skb->data, skb->len,
++ DMA_TO_DEVICE);
++ ret = dma_mapping_error(ld->dev, addr);
++ if (unlikely(ret)) {
++ pr_err("Normal Packet DMA Mapping fail.\n");
++ return -EFAULT;
++ }
++ tx_bq_desc->data_buff_addr = (u32)addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
-+ TX_DESC_HI8_MASK;
++ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
++ TX_DESC_HI8_MASK;
+#endif
-+ } else {
-+ addr = virt_to_phys(skb->data);
-+ tx_bq_desc->data_buff_addr = (u32)addr;
++ } else {
++ addr = virt_to_phys(skb->data);
++ tx_bq_desc->data_buff_addr = (u32)addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
-+ TX_DESC_HI8_MASK;
++ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
++ TX_DESC_HI8_MASK;
+#endif
-+ }
-+ } else {
-+ struct sg_desc *desc_cur;
-+ int i;
-+ dma_addr_t dma_addr;
-+ phys_addr_t phys_addr;
++ }
++ } else {
++ struct sg_desc *desc_cur = NULL;
++ int i;
++ dma_addr_t dma_addr;
++ phys_addr_t phys_addr;
+
-+ if (unlikely(((ld->sg_head + 1) % ld->sg_count) ==
-+ ld->sg_tail)) {
-+ /* SG pkt, but sg desc all used */
-+ pr_err("WARNING: sg desc all used.\n");
-+ return -EBUSY;
-+ }
++ if (unlikely(((ld->sg_head + 1) % ld->sg_count) ==
++ ld->sg_tail)) {
++ /* SG pkt, but sg desc all used */
++ pr_err("WARNING: sg desc all used.\n");
++ return -EBUSY;
++ }
+
-+ desc_cur = ld->dma_sg_desc + ld->sg_head;
++ desc_cur = ld->dma_sg_desc + ld->sg_head;
+
-+ /* TODO: deal with ipv6_id */
-+ if (tx_bq_desc->desc1.tx.tso_flag &&
-+ tx_bq_desc->desc1.tx.ip_ver == PKT_IPV6 &&
-+ tx_bq_desc->desc1.tx.prot_type == PKT_UDP) {
-+ desc_cur->ipv6_id = ntohl(skb_shinfo(skb)->ip6_frag_id);
-+ }
++ /* TODO: deal with ipv6_id */
++ if (tx_bq_desc->desc1.tx.tso_flag &&
++ tx_bq_desc->desc1.tx.ip_ver == PKT_IPV6 &&
++ tx_bq_desc->desc1.tx.prot_type == PKT_UDP) {
++ desc_cur->ipv6_id = ntohl(skb_shinfo(skb)->ip6_frag_id);
++ }
+
-+ desc_cur->total_len = skb->len;
-+ desc_cur->linear_len = skb_headlen(skb);
-+ if (!HAS_CAP_CCI(ld->hw_cap)) {
-+ dma_addr = dma_map_single(ld->dev, skb->data,
-+ desc_cur->linear_len,
-+ DMA_TO_DEVICE);
-+ ret = dma_mapping_error(ld->dev, dma_addr);
-+ if (unlikely(ret)) {
-+ pr_err("DMA Mapping fail.");
-+ return -EFAULT;
-+ }
-+ desc_cur->linear_addr = (u32)dma_addr;
++ desc_cur->total_len = skb->len;
++ desc_cur->linear_len = skb_headlen(skb);
++ if (!HAS_CAP_CCI(ld->hw_cap)) {
++ dma_addr = dma_map_single(ld->dev, skb->data,
++ desc_cur->linear_len,
++ DMA_TO_DEVICE);
++ ret = dma_mapping_error(ld->dev, dma_addr);
++ if (unlikely(ret)) {
++ pr_err("DMA Mapping fail.");
++ return -EFAULT;
++ }
++ desc_cur->linear_addr = (u32)dma_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ desc_cur->reserv3 = (dma_addr >> REG_BIT_WIDTH) << SG_DESC_HI8_OFFSET;
++ desc_cur->reserv3 = (dma_addr >> REG_BIT_WIDTH) <<
++ SG_DESC_HI8_OFFSET;
+#endif
-+ } else {
-+ phys_addr = virt_to_phys(skb->data);
-+ desc_cur->linear_addr = (u32)phys_addr;
++ } else {
++ phys_addr = virt_to_phys(skb->data);
++ desc_cur->linear_addr = (u32)phys_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ desc_cur->reserv3 = (phys_addr >> REG_BIT_WIDTH) << SG_DESC_HI8_OFFSET;
++ desc_cur->reserv3 = (phys_addr >> REG_BIT_WIDTH) <<
++ SG_DESC_HI8_OFFSET;
+#endif
-+ }
++ }
+
-+ for (i = 0; i < nfrags; i++) {
-+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-+ int len = frag->size;
++ for (i = 0; i < nfrags; i++) {
++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
++ int len = frag->size;
+
-+ if (!HAS_CAP_CCI(ld->hw_cap)) {
-+ dma_addr = skb_frag_dma_map(ld->dev, frag, 0,
-+ len,
-+ DMA_TO_DEVICE);
-+ ret = dma_mapping_error(ld->dev, dma_addr);
-+ if (unlikely(ret)) {
-+ pr_err("skb frag DMA Mapping fail.");
-+ return -EFAULT;
-+ }
-+ desc_cur->frags[i].addr = (u32)dma_addr;
++ if (!HAS_CAP_CCI(ld->hw_cap)) {
++ dma_addr = skb_frag_dma_map(ld->dev, frag, 0,
++ len,
++ DMA_TO_DEVICE);
++ ret = dma_mapping_error(ld->dev, dma_addr);
++ if (unlikely(ret)) {
++ pr_err("skb frag DMA Mapping fail.");
++ return -EFAULT;
++ }
++ desc_cur->frags[i].addr = (u32)dma_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ desc_cur->frags[i].reserved =
-+ (dma_addr >> REG_BIT_WIDTH) << SG_DESC_HI8_OFFSET;
++ desc_cur->frags[i].reserved =
++ (dma_addr >> REG_BIT_WIDTH) <<
++ SG_DESC_HI8_OFFSET;
+#endif
-+ } else {
-+ phys_addr =
-+ page_to_phys(skb_frag_page(frag)) +
-+ frag->page_offset;
-+ desc_cur->frags[i].addr = (u32)phys_addr;
++ } else {
++ phys_addr =
++ page_to_phys(skb_frag_page(frag)) +
++ frag->page_offset;
++ desc_cur->frags[i].addr = (u32)phys_addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ desc_cur->frags[i].reserved =
-+ (phys_addr >> REG_BIT_WIDTH) << SG_DESC_HI8_OFFSET;
++ desc_cur->frags[i].reserved =
++ (phys_addr >> REG_BIT_WIDTH) <<
++ SG_DESC_HI8_OFFSET;
+#endif
-+ }
-+ desc_cur->frags[i].size = len;
-+ }
-+ addr = ld->dma_sg_phy + ld->sg_head * sizeof(struct sg_desc);
-+ tx_bq_desc->data_buff_addr = (u32)addr;
++ }
++ desc_cur->frags[i].size = len;
++ }
++ addr = ld->dma_sg_phy + ld->sg_head * sizeof(struct sg_desc);
++ tx_bq_desc->data_buff_addr = (u32)addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
-+ TX_DESC_HI8_MASK;
++ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
++ TX_DESC_HI8_MASK;
+#endif
-+ ld->tx_bq.sg_desc_offset[desc_pos] = ld->sg_head;
++ ld->tx_bq.sg_desc_offset[desc_pos] = ld->sg_head;
+
-+ ld->sg_head = (ld->sg_head + 1) % ld->sg_count;
-+ }
++ ld->sg_head = (ld->sg_head + 1) % ld->sg_count;
++ }
+
+#ifdef HIGMAC_TSO_DEBUG
-+ memcpy(&pkt_rec[id_send].desc, tx_bq_desc,
-+ sizeof(struct higmac_tso_desc));
-+ pkt_rec[id_send].status = 1;
-+ id_send++;
-+ if (id_send == MAX_RECORD) {
-+ id_send = 0;
-+ }
++ if (id_send >= MAX_RECORD)
++ id_send = 0;
++ memcpy(&pkt_rec[id_send].desc, tx_bq_desc,
++ sizeof(struct higmac_tso_desc));
++ pkt_rec[id_send].status = 1;
++ id_send++;
+#endif
-+ return 0;
++ return 0;
+}
+
+static netdev_tx_t higmac_net_xmit(struct sk_buff *skb, struct net_device *dev);
+
+static netdev_tx_t higmac_sw_gso(struct higmac_netdev_local *ld,
-+ struct sk_buff *skb)
++ struct sk_buff *skb)
+{
-+ struct sk_buff *segs, *curr_skb;
-+ int gso_segs = skb_shinfo(skb)->gso_segs;
++ struct sk_buff *segs = NULL;
++ struct sk_buff *curr_skb = NULL;
++ int gso_segs = skb_shinfo(skb)->gso_segs;
+
-+ if (gso_segs == 0 && skb_shinfo(skb)->gso_size != 0) {
-+ gso_segs = DIV_ROUND_UP(skb->len, skb_shinfo(skb)->gso_size);
-+ }
++ if (gso_segs == 0 && skb_shinfo(skb)->gso_size != 0)
++ gso_segs = DIV_ROUND_UP(skb->len, skb_shinfo(skb)->gso_size);
+
-+ /* Estimate the number of fragments in the worst case */
-+ if (unlikely(higmac_tx_avail(ld) < gso_segs)) {
-+ netif_stop_queue(ld->netdev);
-+ if (higmac_tx_avail(ld) < gso_segs) {
-+ ld->netdev->stats.tx_dropped++;
-+ ld->netdev->stats.tx_fifo_errors++;
-+ return NETDEV_TX_BUSY;
-+ }
++ /* Estimate the number of fragments in the worst case */
++ if (unlikely(higmac_tx_avail(ld) < gso_segs)) {
++ netif_stop_queue(ld->netdev);
++ if (higmac_tx_avail(ld) < gso_segs) {
++ ld->netdev->stats.tx_dropped++;
++ ld->netdev->stats.tx_fifo_errors++;
++ return NETDEV_TX_BUSY;
++ }
+
-+ netif_wake_queue(ld->netdev);
-+ }
++ netif_wake_queue(ld->netdev);
++ }
+
-+ segs = skb_gso_segment(skb, ld->netdev->features & ~(NETIF_F_CSUM_MASK |
-+ NETIF_F_SG | NETIF_F_GSO_SOFTWARE));
++ segs = skb_gso_segment(skb, ld->netdev->features & ~(NETIF_F_CSUM_MASK |
++ NETIF_F_SG | NETIF_F_GSO_SOFTWARE));
+
-+ if (IS_ERR_OR_NULL(segs)) {
-+ goto drop;
-+ }
++ if (IS_ERR_OR_NULL(segs))
++ goto drop;
+
-+ do {
-+ curr_skb = segs;
-+ segs = segs->next;
-+ curr_skb->next = NULL;
-+ higmac_net_xmit(curr_skb, ld->netdev);
-+ } while (segs);
++ do {
++ curr_skb = segs;
++ segs = segs->next;
++ curr_skb->next = NULL;
++ higmac_net_xmit(curr_skb, ld->netdev);
++ } while (segs);
+
-+ dev_kfree_skb_any(skb);
-+ return NETDEV_TX_OK;
++ dev_kfree_skb_any(skb);
++ return NETDEV_TX_OK;
+
+drop:
-+ dev_kfree_skb_any(skb);
-+ ld->netdev->stats.tx_dropped++;
-+ return NETDEV_TX_OK;
++ dev_kfree_skb_any(skb);
++ ld->netdev->stats.tx_dropped++;
++ return NETDEV_TX_OK;
+}
+
+static netdev_tx_t higmac_net_xmit(struct sk_buff *skb, struct net_device *dev)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(dev);
-+ struct higmac_desc *desc;
-+ dma_addr_t addr;
-+ unsigned long txflags;
-+ int ret;
-+ u32 pos;
++ struct higmac_netdev_local *ld = netdev_priv(dev);
++ struct higmac_desc *desc = NULL;
++ dma_addr_t addr;
++ unsigned long txflags;
++ int ret;
++ u32 pos;
+
-+ if (skb->len < ETH_HLEN) {
-+ dev_kfree_skb_any(skb);
-+ dev->stats.tx_errors++;
-+ dev->stats.tx_dropped++;
-+ return NETDEV_TX_OK;
-+ }
++ if (skb->len < ETH_HLEN) {
++ dev_kfree_skb_any(skb);
++ dev->stats.tx_errors++;
++ dev->stats.tx_dropped++;
++ return NETDEV_TX_OK;
++ }
+
-+ /* if adding higmac_xmit_reclaim here, iperf tcp client
-+ * performance will be affected, from 550M(avg) to 513M~300M
-+ */
++ /* if adding higmac_xmit_reclaim here, iperf tcp client
++ * performance will be affected, from 550M(avg) to 513M~300M
++ */
+
-+ /* software write pointer */
-+ pos = dma_cnt(readl(ld->gmac_iobase + TX_BQ_WR_ADDR));
++ /* software write pointer */
++ pos = dma_cnt(readl(ld->gmac_iobase + TX_BQ_WR_ADDR));
+
-+ spin_lock_irqsave(&ld->txlock, txflags);
++ spin_lock_irqsave(&ld->txlock, txflags);
+
-+ if (unlikely(ld->tx_skb[pos] || ld->tx_bq.skb[pos])) {
-+ dev->stats.tx_dropped++;
-+ dev->stats.tx_fifo_errors++;
-+ netif_stop_queue(dev);
-+ spin_unlock_irqrestore(&ld->txlock, txflags);
++ if (unlikely(ld->tx_skb[pos] || ld->tx_bq.skb[pos])) {
++ dev->stats.tx_dropped++;
++ dev->stats.tx_fifo_errors++;
++ netif_stop_queue(dev);
++ spin_unlock_irqrestore(&ld->txlock, txflags);
+
-+ return NETDEV_TX_BUSY;
-+ }
++ return NETDEV_TX_BUSY;
++ }
+
-+ ld->tx_bq.skb[pos] = skb;
-+ ld->tx_skb[pos] = skb;
++ ld->tx_bq.skb[pos] = skb;
++ ld->tx_skb[pos] = skb;
+
-+ desc = ld->tx_bq.desc + pos;
++ desc = ld->tx_bq.desc + pos;
+
-+ if (ld->tso_supported) {
-+ ret = higmac_xmit_gso(ld, skb,
-+ (struct higmac_tso_desc *)desc,
-+ pos);
-+ if (unlikely(ret < 0)) {
-+ ld->tx_skb[pos] = NULL;
-+ ld->tx_bq.skb[pos] = NULL;
-+ spin_unlock_irqrestore(&ld->txlock, txflags);
++ if (ld->tso_supported) {
++ ret = higmac_xmit_gso(ld, skb,
++ (struct higmac_tso_desc *)desc,
++ pos);
++ if (unlikely(ret < 0)) {
++ ld->tx_skb[pos] = NULL;
++ ld->tx_bq.skb[pos] = NULL;
++ spin_unlock_irqrestore(&ld->txlock, txflags);
+
-+ if (ret == -ENOTSUPP) {
-+ return higmac_sw_gso(ld, skb);
-+ }
++ if (ret == -ENOTSUPP)
++ return higmac_sw_gso(ld, skb);
+
-+ dev_kfree_skb_any(skb);
-+ dev->stats.tx_dropped++;
-+ return NETDEV_TX_OK;
-+ }
-+ } else {
-+ if (!HAS_CAP_CCI(ld->hw_cap)) {
-+ addr = dma_map_single(ld->dev, skb->data, skb->len,
-+ DMA_TO_DEVICE);
-+ if (unlikely(dma_mapping_error(ld->dev, addr))) {
-+ dev_kfree_skb_any(skb);
-+ dev->stats.tx_dropped++;
-+ ld->tx_skb[pos] = NULL;
-+ ld->tx_bq.skb[pos] = NULL;
-+ spin_unlock_irqrestore(&ld->txlock, txflags);
-+ return NETDEV_TX_OK;
-+ }
-+ desc->data_buff_addr = (u32)addr;
++ dev_kfree_skb_any(skb);
++ dev->stats.tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++ } else {
++ if (!HAS_CAP_CCI(ld->hw_cap)) {
++ addr = dma_map_single(ld->dev, skb->data, skb->len,
++ DMA_TO_DEVICE);
++ if (unlikely(dma_mapping_error(ld->dev, addr))) {
++ dev_kfree_skb_any(skb);
++ dev->stats.tx_dropped++;
++ ld->tx_skb[pos] = NULL;
++ ld->tx_bq.skb[pos] = NULL;
++ spin_unlock_irqrestore(&ld->txlock, txflags);
++ return NETDEV_TX_OK;
++ }
++ desc->data_buff_addr = (u32)addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ desc->rxhash = (addr >> REG_BIT_WIDTH) &
-+ TX_DESC_HI8_MASK;
++ desc->rxhash = (addr >> REG_BIT_WIDTH) &
++ TX_DESC_HI8_MASK;
+#endif
-+ } else {
-+ addr = virt_to_phys(skb->data);
-+ desc->data_buff_addr = (u32)addr;
++ } else {
++ addr = virt_to_phys(skb->data);
++ desc->data_buff_addr = (u32)addr;
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ desc->rxhash = (addr >> REG_BIT_WIDTH) &
-+ TX_DESC_HI8_MASK;
++ desc->rxhash = (addr >> REG_BIT_WIDTH) &
++ TX_DESC_HI8_MASK;
+#endif
-+ }
-+ desc->buffer_len = HIETH_MAX_FRAME_SIZE - 1;
-+ desc->data_len = skb->len;
-+ desc->fl = DESC_FL_FULL;
-+ desc->descvid = DESC_VLD_BUSY;
-+ }
++ }
++ desc->buffer_len = HIETH_MAX_FRAME_SIZE - 1;
++ desc->data_len = skb->len;
++ desc->fl = DESC_FL_FULL;
++ desc->descvid = DESC_VLD_BUSY;
++ }
+
-+ /* This barrier is important here. It is required to ensure
-+ * the ARM CPU flushes it's DMA write buffers before proceeding
-+ * to the next instruction, to ensure that GMAC will see
-+ * our descriptor changes in memory
-+ */
-+ HIGMAC_SYNC_BARRIER();
++ /* This barrier is important here. It is required to ensure
++ * the ARM CPU flushes it's DMA write buffers before proceeding
++ * to the next instruction, to ensure that GMAC will see
++ * our descriptor changes in memory
++ */
++ HIGMAC_SYNC_BARRIER();
++ pos = dma_ring_incr(pos, TX_DESC_NUM);
++ writel(dma_byte(pos), ld->gmac_iobase + TX_BQ_WR_ADDR);
+
-+ pos = dma_ring_incr(pos, TX_DESC_NUM);
-+ writel(dma_byte(pos), ld->gmac_iobase + TX_BQ_WR_ADDR);
++ netif_trans_update(dev);
++ dev->stats.tx_packets++;
++ dev->stats.tx_bytes += skb->len;
++ netdev_sent_queue(dev, skb->len);
+
-+ netif_trans_update(dev);
-+ dev->stats.tx_packets++;
-+ dev->stats.tx_bytes += skb->len;
-+ netdev_sent_queue(dev, skb->len);
++ spin_unlock_irqrestore(&ld->txlock, txflags);
+
-+ spin_unlock_irqrestore(&ld->txlock, txflags);
-+
-+ return NETDEV_TX_OK;
++ return NETDEV_TX_OK;
+}
+
+void higmac_enable_napi(struct higmac_netdev_local *priv)
+{
-+ struct higmac_napi *q_napi;
-+ int i;
++ struct higmac_napi *q_napi = NULL;
++ int i;
+
-+ for (i = 0; i < priv->num_rxqs; i++) {
-+ q_napi = &priv->q_napi[i];
-+ napi_enable(&q_napi->napi);
-+ }
++ for (i = 0; i < priv->num_rxqs; i++) {
++ q_napi = &priv->q_napi[i];
++ napi_enable(&q_napi->napi);
++ }
+}
+
+void higmac_disable_napi(struct higmac_netdev_local *priv)
+{
-+ struct higmac_napi *q_napi;
-+ int i;
++ struct higmac_napi *q_napi = NULL;
++ int i;
+
-+ for (i = 0; i < priv->num_rxqs; i++) {
-+ q_napi = &priv->q_napi[i];
-+ napi_disable(&q_napi->napi);
-+ }
++ for (i = 0; i < priv->num_rxqs; i++) {
++ q_napi = &priv->q_napi[i];
++ napi_disable(&q_napi->napi);
++ }
+}
+
+static int higmac_net_open(struct net_device *dev)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(dev);
-+ unsigned long flags;
++ struct higmac_netdev_local *ld = netdev_priv(dev);
++ unsigned long flags;
+
-+ clk_prepare_enable(ld->macif_clk);
-+ clk_prepare_enable(ld->clk);
++ clk_prepare_enable(ld->macif_clk);
++ clk_prepare_enable(ld->clk);
+
-+ /* If we configure mac address by
-+ * "ifconfig ethX hw ether XX:XX:XX:XX:XX:XX",
-+ * the ethX must be down state and mac core clock is disabled
-+ * which results the mac address has not been configured
-+ * in mac core register.
-+ * So we must set mac address again here,
-+ * because mac core clock is enabled at this time
-+ * and we can configure mac address to mac core register.
-+ */
-+ higmac_hw_set_mac_addr(dev);
++ /* If we configure mac address by
++ * "ifconfig ethX hw ether XX:XX:XX:XX:XX:XX",
++ * the ethX must be down state and mac core clock is disabled
++ * which results the mac address has not been configured
++ * in mac core register.
++ * So we must set mac address again here,
++ * because mac core clock is enabled at this time
++ * and we can configure mac address to mac core register.
++ */
++ higmac_hw_set_mac_addr(dev);
+
-+ /* We should use netif_carrier_off() here,
-+ * because the default state should be off.
-+ * And this call should before phy_start().
-+ */
-+ netif_carrier_off(dev);
-+ higmac_enable_napi(ld);
-+ phy_start(ld->phy);
++ /* We should use netif_carrier_off() here,
++ * because the default state should be off.
++ * And this call should before phy_start().
++ */
++ netif_carrier_off(dev);
++ higmac_enable_napi(ld);
++ phy_start(ld->phy);
+
-+ higmac_hw_desc_enable(ld);
-+ higmac_port_enable(ld);
-+ higmac_irq_enable_all_queue(ld);
++ higmac_hw_desc_enable(ld);
++ higmac_port_enable(ld);
++ higmac_irq_enable_all_queue(ld);
+
-+ spin_lock_irqsave(&ld->rxlock, flags);
-+ higmac_rx_refill(ld);
-+ spin_unlock_irqrestore(&ld->rxlock, flags);
++ spin_lock_irqsave(&ld->rxlock, flags);
++ higmac_rx_refill(ld);
++ spin_unlock_irqrestore(&ld->rxlock, flags);
+
-+ ld->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
-+ mod_timer(&ld->monitor, ld->monitor.expires);
++ ld->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
++ mod_timer(&ld->monitor, ld->monitor.expires);
+
-+ netif_start_queue(dev);
++ netif_start_queue(dev);
+
-+ return 0;
++ return 0;
+}
+
+static int higmac_net_close(struct net_device *dev)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(dev);
++ struct higmac_netdev_local *ld = netdev_priv(dev);
+
-+ higmac_irq_disable_all_queue(ld);
-+ higmac_hw_desc_disable(ld);
++ higmac_irq_disable_all_queue(ld);
++ higmac_hw_desc_disable(ld);
+
-+ higmac_disable_napi(ld);
++ higmac_disable_napi(ld);
+
-+ netif_carrier_off(dev);
-+ netif_stop_queue(dev);
++ netif_carrier_off(dev);
++ netif_stop_queue(dev);
+
-+ phy_stop(ld->phy);
-+ del_timer_sync(&ld->monitor);
++ phy_stop(ld->phy);
++ del_timer_sync(&ld->monitor);
+
-+ clk_disable_unprepare(ld->clk);
-+ clk_disable_unprepare(ld->macif_clk);
++ clk_disable_unprepare(ld->clk);
++ clk_disable_unprepare(ld->macif_clk);
+
-+ return 0;
++ return 0;
+}
+
+static void higmac_net_timeout(struct net_device *dev)
+{
-+ dev->stats.tx_errors++;
++ dev->stats.tx_errors++;
+
-+ pr_err("tx timeout!\n");
++ pr_err("tx timeout!\n");
+}
+
+static void higmac_set_multicast_list(struct net_device *dev)
+{
-+ higmac_gmac_multicast_list(dev);
++ higmac_gmac_multicast_list(dev);
+}
+
+static inline void higmac_enable_rxcsum_drop(struct higmac_netdev_local *ld,
-+ bool drop)
++ bool drop)
+{
-+ unsigned int v;
++ unsigned int v;
+
-+ v = readl(ld->gmac_iobase + TSO_COE_CTRL);
-+ if (drop) {
-+ v |= COE_ERR_DROP;
-+ } else {
-+ v &= ~COE_ERR_DROP;
-+ }
-+ writel(v, ld->gmac_iobase + TSO_COE_CTRL);
++ v = readl(ld->gmac_iobase + TSO_COE_CTRL);
++ if (drop)
++ v |= COE_ERR_DROP;
++ else
++ v &= ~COE_ERR_DROP;
++ writel(v, ld->gmac_iobase + TSO_COE_CTRL);
+}
+
+static int higmac_set_features(struct net_device *dev,
-+ netdev_features_t features)
++ netdev_features_t features)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(dev);
-+ netdev_features_t changed = dev->features ^ features;
++ struct higmac_netdev_local *ld = netdev_priv(dev);
++ netdev_features_t changed = dev->features ^ features;
+
-+ if (changed & NETIF_F_RXCSUM) {
-+ if (features & NETIF_F_RXCSUM) {
-+ higmac_enable_rxcsum_drop(ld, true);
-+ } else {
-+ higmac_enable_rxcsum_drop(ld, false);
-+ }
-+ }
++ if (changed & NETIF_F_RXCSUM) {
++ if (features & NETIF_F_RXCSUM)
++ higmac_enable_rxcsum_drop(ld, true);
++ else
++ higmac_enable_rxcsum_drop(ld, false);
++ }
+
-+ return 0;
++ return 0;
+}
+
+static struct net_device_stats *higmac_net_get_stats(struct net_device *dev)
+{
-+ return &dev->stats;
++ return &dev->stats;
+}
+
+static void higmac_get_drvinfo(struct net_device *net_dev,
-+ struct ethtool_drvinfo *info)
++ struct ethtool_drvinfo *info)
+{
-+ strncpy(info->driver, "higmac driver", 15);
-+ strncpy(info->version, "higmac v200", 15);
-+ strncpy(info->bus_info, "platform", 15);
++ strncpy(info->driver, "higmac driver", 15);
++ strncpy(info->version, "higmac v200", 15);
++ strncpy(info->bus_info, "platform", 15);
+}
+
+static unsigned int higmac_get_link(struct net_device *net_dev)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(net_dev);
++ struct higmac_netdev_local *ld = netdev_priv(net_dev);
+
-+ return ld->phy->link ? HIGMAC_LINKED : 0;
++ return ld->phy->link ? HIGMAC_LINKED : 0;
+}
+
+static int higmac_get_settings(struct net_device *net_dev,
-+ struct ethtool_cmd *cmd)
++ struct ethtool_cmd *cmd)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(net_dev);
++ struct higmac_netdev_local *ld = netdev_priv(net_dev);
+
-+ if (ld->phy) {
-+ return phy_ethtool_gset(ld->phy, cmd);
-+ }
++ if (ld->phy)
++ return phy_ethtool_gset(ld->phy, cmd);
+
-+ return -EINVAL;
++ return -EINVAL;
+}
+
+static int higmac_set_settings(struct net_device *net_dev,
-+ struct ethtool_cmd *cmd)
++ struct ethtool_cmd *cmd)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(net_dev);
++ struct higmac_netdev_local *ld = netdev_priv(net_dev);
+
-+ if (!capable(CAP_NET_ADMIN)) {
-+ return -EPERM;
-+ }
++ if (!capable(CAP_NET_ADMIN))
++ return -EPERM;
+
-+ if (ld->phy) {
-+ return phy_ethtool_sset(ld->phy, cmd);
-+ }
++ if (ld->phy)
++ return phy_ethtool_sset(ld->phy, cmd);
+
-+ return -EINVAL;
++ return -EINVAL;
+}
+
+static void higmac_get_pauseparam(struct net_device *net_dev,
-+ struct ethtool_pauseparam *pause)
++ struct ethtool_pauseparam *pause)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(net_dev);
++ struct higmac_netdev_local *ld = netdev_priv(net_dev);
+
-+ pause->rx_pause = 0;
-+ pause->tx_pause = 0;
-+ pause->autoneg = ld->phy->autoneg;
++ pause->rx_pause = 0;
++ pause->tx_pause = 0;
++ pause->autoneg = ld->phy->autoneg;
+
-+ if (ld->flow_ctrl & FLOW_RX) {
-+ pause->rx_pause = 1;
-+ }
-+ if (ld->flow_ctrl & FLOW_TX) {
-+ pause->tx_pause = 1;
-+ }
++ if (ld->flow_ctrl & FLOW_RX)
++ pause->rx_pause = 1;
++ if (ld->flow_ctrl & FLOW_TX)
++ pause->tx_pause = 1;
+}
+
+static int higmac_set_pauseparam(struct net_device *net_dev,
-+ struct ethtool_pauseparam *pause)
++ struct ethtool_pauseparam *pause)
+{
-+ struct higmac_netdev_local *ld = netdev_priv(net_dev);
-+ struct phy_device *phy = ld->phy;
-+ int new_pause = FLOW_OFF;
-+ int ret = 0;
++ struct higmac_netdev_local *ld = netdev_priv(net_dev);
++ struct phy_device *phy = ld->phy;
++ unsigned int new_pause = FLOW_OFF;
++ int ret = 0;
+
-+ if (pause->rx_pause) {
-+ new_pause |= FLOW_RX;
-+ }
-+ if (pause->tx_pause) {
-+ new_pause |= FLOW_TX;
-+ }
++ if (pause->rx_pause)
++ new_pause |= FLOW_RX;
++ if (pause->tx_pause)
++ new_pause |= FLOW_TX;
+
-+ if (new_pause != ld->flow_ctrl) {
-+ ld->flow_ctrl = new_pause;
-+ }
++ if (new_pause != ld->flow_ctrl)
++ ld->flow_ctrl = new_pause;
+
-+ higmac_set_flow_ctrl_state(ld, phy->pause);
-+ phy->advertising &= ~SUPPORTED_Pause;
-+ if (ld->flow_ctrl) {
-+ phy->advertising |= SUPPORTED_Pause;
-+ }
++ higmac_set_flow_ctrl_state(ld, phy->pause);
++ phy->advertising &= ~SUPPORTED_Pause;
++ if (ld->flow_ctrl)
++ phy->advertising |= SUPPORTED_Pause;
+
-+ if (phy->autoneg) {
-+ if (netif_running(net_dev)) {
-+ return phy_start_aneg(phy);
-+ }
-+ }
++ if (phy->autoneg) {
++ if (netif_running(net_dev))
++ return phy_start_aneg(phy);
++ }
+
-+ return ret;
++ return ret;
+}
+
+static u32 higmac_ethtool_getmsglevel(struct net_device *ndev)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
+
-+ return priv->msg_enable;
++ return priv->msg_enable;
+}
+
+static void higmac_ethtool_setmsglevel(struct net_device *ndev, u32 level)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
+
-+ priv->msg_enable = level;
++ priv->msg_enable = level;
+}
+
+static u32 higmac_get_rxfh_key_size(struct net_device *ndev)
+{
-+ return RSS_HASH_KEY_SIZE;
++ return RSS_HASH_KEY_SIZE;
+}
+
+static u32 higmac_get_rxfh_indir_size(struct net_device *ndev)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
+
-+ return priv->rss_info.ind_tbl_size;
++ return priv->rss_info.ind_tbl_size;
+}
+
+static int higmac_get_rxfh(struct net_device *ndev, u32 *indir, u8 *hkey,
-+ u8 *hfunc)
++ u8 *hfunc)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
-+ struct higmac_rss_info *rss = &priv->rss_info;
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct higmac_rss_info *rss = &priv->rss_info;
+
-+ if (hfunc) {
-+ *hfunc = ETH_RSS_HASH_TOP;
-+ }
++ if (hfunc)
++ *hfunc = ETH_RSS_HASH_TOP;
+
-+ if (hkey) {
-+ memcpy(hkey, rss->key, RSS_HASH_KEY_SIZE);
-+ }
++ if (hkey)
++ memcpy(hkey, rss->key, RSS_HASH_KEY_SIZE);
+
-+ if (indir) {
-+ int i;
++ if (indir) {
++ int i;
+
-+ for (i = 0; i < rss->ind_tbl_size; i++) {
-+ indir[i] = rss->ind_tbl[i];
-+ }
-+ }
++ for (i = 0; i < rss->ind_tbl_size; i++)
++ indir[i] = rss->ind_tbl[i];
++ }
+
-+ return 0;
++ return 0;
+}
+
+static void higmac_get_rss_key(struct higmac_netdev_local *priv)
+{
-+ struct higmac_rss_info *rss = &priv->rss_info;
-+ u32 hkey;
++ struct higmac_rss_info *rss = &priv->rss_info;
++ u32 hkey;
+
-+ hkey = readl(priv->gmac_iobase + RSS_HASH_KEY);
-+ *((u32 *)rss->key) = hkey;
++ hkey = readl(priv->gmac_iobase + RSS_HASH_KEY);
++ *((u32 *)rss->key) = hkey;
+}
+
+static void higmac_set_rss_key(struct higmac_netdev_local *priv)
+{
-+ struct higmac_rss_info *rss = &priv->rss_info;
++ struct higmac_rss_info *rss = &priv->rss_info;
+
-+ writel(*((u32 *)rss->key), priv->gmac_iobase + RSS_HASH_KEY);
++ writel(*((u32 *)rss->key), priv->gmac_iobase + RSS_HASH_KEY);
+}
+
+static int higmac_wait_rss_ready(struct higmac_netdev_local *priv)
+{
-+ void __iomem *base = priv->gmac_iobase;
-+ int i, timeout = 10000;
++ void __iomem *base = priv->gmac_iobase;
++ int i, timeout = 10000;
+
-+ for (i = 0; !(readl(base + RSS_IND_TBL) & BIT_IND_TBL_READY); i++) {
-+ if (i == timeout) {
-+ netdev_err(priv->netdev, "wait rss ready timeout!\n");
-+ return -ETIMEDOUT;
-+ }
-+ usleep_range(10, 20);
-+ }
++ for (i = 0; !(readl(base + RSS_IND_TBL) & BIT_IND_TBL_READY); i++) {
++ if (i == timeout) {
++ netdev_err(priv->netdev, "wait rss ready timeout!\n");
++ return -ETIMEDOUT;
++ }
++ usleep_range(10, 20);
++ }
+
-+ return 0;
++ return 0;
+}
+
+static void higmac_config_rss(struct higmac_netdev_local *priv)
+{
-+ struct higmac_rss_info *rss = &priv->rss_info;
-+ u32 rss_val;
-+ int i;
++ struct higmac_rss_info *rss = &priv->rss_info;
++ u32 rss_val;
++ unsigned int i;
+
-+ for (i = 0; i < rss->ind_tbl_size; i++) {
-+ if (higmac_wait_rss_ready(priv)) {
-+ break;
-+ }
-+ rss_val = BIT_IND_TLB_WR | (rss->ind_tbl[i] << 8) | i;
-+ writel(rss_val, priv->gmac_iobase + RSS_IND_TBL);
-+ }
++ for (i = 0; i < rss->ind_tbl_size; i++) {
++ if (higmac_wait_rss_ready(priv))
++ break;
++ rss_val = BIT_IND_TLB_WR | (rss->ind_tbl[i] << 8) | i;
++ writel(rss_val, priv->gmac_iobase + RSS_IND_TBL);
++ }
+}
+
+static void higmac_get_rss(struct higmac_netdev_local *priv)
+{
-+ struct higmac_rss_info *rss = &priv->rss_info;
-+ u32 rss_val;
-+ int i;
++ struct higmac_rss_info *rss = &priv->rss_info;
++ u32 rss_val;
++ int i;
+
-+ for (i = 0; i < rss->ind_tbl_size; i++) {
-+ if (higmac_wait_rss_ready(priv)) {
-+ break;
-+ }
-+ writel(i, priv->gmac_iobase + RSS_IND_TBL);
-+ if (higmac_wait_rss_ready(priv)) {
-+ break;
-+ }
-+ rss_val = readl(priv->gmac_iobase + RSS_IND_TBL);
-+ rss->ind_tbl[i] = (rss_val >> 10) & 0x3;
-+ }
++ for (i = 0; i < rss->ind_tbl_size; i++) {
++ if (higmac_wait_rss_ready(priv))
++ break;
++ writel(i, priv->gmac_iobase + RSS_IND_TBL);
++ if (higmac_wait_rss_ready(priv))
++ break;
++ rss_val = readl(priv->gmac_iobase + RSS_IND_TBL);
++ rss->ind_tbl[i] = (rss_val >> 10) & 0x3;
++ }
+}
+
+static int higmac_set_rxfh(struct net_device *ndev, const u32 *indir,
-+ const u8 *hkey, const u8 hfunc)
++ const u8 *hkey, const u8 hfunc)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
-+ struct higmac_rss_info *rss = &priv->rss_info;
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct higmac_rss_info *rss = &priv->rss_info;
+
-+ if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) {
-+ return -EOPNOTSUPP;
-+ }
++ if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
++ return -EOPNOTSUPP;
+
-+ if (indir) {
-+ int i;
++ if (indir) {
++ int i;
+
-+ for (i = 0; i < rss->ind_tbl_size; i++) {
-+ rss->ind_tbl[i] = indir[i];
-+ }
-+ }
++ for (i = 0; i < rss->ind_tbl_size; i++)
++ rss->ind_tbl[i] = indir[i];
++ }
+
-+ if (hkey) {
-+ memcpy(rss->key, hkey, RSS_HASH_KEY_SIZE);
-+ higmac_set_rss_key(priv);
-+ }
++ if (hkey) {
++ memcpy(rss->key, hkey, RSS_HASH_KEY_SIZE);
++ higmac_set_rss_key(priv);
++ }
+
-+ higmac_config_rss(priv);
++ higmac_config_rss(priv);
+
-+ return 0;
++ return 0;
+}
+
+static int higmac_get_rss_hash_opts(struct higmac_netdev_local *priv,
-+ struct ethtool_rxnfc *info)
++ struct ethtool_rxnfc *info)
+{
-+ u32 hash_cfg = priv->rss_info.hash_cfg;
++ u32 hash_cfg = priv->rss_info.hash_cfg;
+
-+ info->data = 0;
++ info->data = 0;
+
-+ switch (info->flow_type) {
-+ case TCP_V4_FLOW:
-+ if (hash_cfg & TCPV4_L3_HASH_EN) {
-+ info->data |= RXH_IP_SRC | RXH_IP_DST;
-+ }
-+ if (hash_cfg & TCPV4_L4_HASH_EN) {
-+ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
-+ }
-+ if (hash_cfg & TCPV4_VLAN_HASH_EN) {
-+ info->data |= RXH_VLAN;
-+ }
-+ break;
-+ case TCP_V6_FLOW:
-+ if (hash_cfg & TCPV6_L3_HASH_EN) {
-+ info->data |= RXH_IP_SRC | RXH_IP_DST;
-+ }
-+ if (hash_cfg & TCPV6_L4_HASH_EN) {
-+ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
-+ }
-+ if (hash_cfg & TCPV6_VLAN_HASH_EN) {
-+ info->data |= RXH_VLAN;
-+ }
-+ break;
-+ case UDP_V4_FLOW:
-+ if (hash_cfg & UDPV4_L3_HASH_EN) {
-+ info->data |= RXH_IP_SRC | RXH_IP_DST;
-+ }
-+ if (hash_cfg & UDPV4_L4_HASH_EN) {
-+ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
-+ }
-+ if (hash_cfg & UDPV4_VLAN_HASH_EN) {
-+ info->data |= RXH_VLAN;
-+ }
-+ break;
-+ case UDP_V6_FLOW:
-+ if (hash_cfg & UDPV6_L3_HASH_EN) {
-+ info->data |= RXH_IP_SRC | RXH_IP_DST;
-+ }
-+ if (hash_cfg & UDPV6_L4_HASH_EN) {
-+ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
-+ }
-+ if (hash_cfg & UDPV6_VLAN_HASH_EN) {
-+ info->data |= RXH_VLAN;
-+ }
-+ break;
-+ case IPV4_FLOW:
-+ if (hash_cfg & IPV4_L3_HASH_EN) {
-+ info->data |= RXH_IP_SRC | RXH_IP_DST;
-+ }
-+ if (hash_cfg & IPV4_VLAN_HASH_EN) {
-+ info->data |= RXH_VLAN;
-+ }
-+ break;
-+ case IPV6_FLOW:
-+ if (hash_cfg & IPV6_L3_HASH_EN) {
-+ info->data |= RXH_IP_SRC | RXH_IP_DST;
-+ }
-+ if (hash_cfg & IPV6_VLAN_HASH_EN) {
-+ info->data |= RXH_VLAN;
-+ }
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
++ switch (info->flow_type) {
++ case TCP_V4_FLOW:
++ if (hash_cfg & TCPV4_L3_HASH_EN)
++ info->data |= RXH_IP_SRC | RXH_IP_DST;
++ if (hash_cfg & TCPV4_L4_HASH_EN)
++ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
++ if (hash_cfg & TCPV4_VLAN_HASH_EN)
++ info->data |= RXH_VLAN;
++ break;
++ case TCP_V6_FLOW:
++ if (hash_cfg & TCPV6_L3_HASH_EN)
++ info->data |= RXH_IP_SRC | RXH_IP_DST;
++ if (hash_cfg & TCPV6_L4_HASH_EN)
++ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
++ if (hash_cfg & TCPV6_VLAN_HASH_EN)
++ info->data |= RXH_VLAN;
++ break;
++ case UDP_V4_FLOW:
++ if (hash_cfg & UDPV4_L3_HASH_EN)
++ info->data |= RXH_IP_SRC | RXH_IP_DST;
++ if (hash_cfg & UDPV4_L4_HASH_EN)
++ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
++ if (hash_cfg & UDPV4_VLAN_HASH_EN)
++ info->data |= RXH_VLAN;
++ break;
++ case UDP_V6_FLOW:
++ if (hash_cfg & UDPV6_L3_HASH_EN)
++ info->data |= RXH_IP_SRC | RXH_IP_DST;
++ if (hash_cfg & UDPV6_L4_HASH_EN)
++ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
++ if (hash_cfg & UDPV6_VLAN_HASH_EN)
++ info->data |= RXH_VLAN;
++ break;
++ case IPV4_FLOW:
++ if (hash_cfg & IPV4_L3_HASH_EN)
++ info->data |= RXH_IP_SRC | RXH_IP_DST;
++ if (hash_cfg & IPV4_VLAN_HASH_EN)
++ info->data |= RXH_VLAN;
++ break;
++ case IPV6_FLOW:
++ if (hash_cfg & IPV6_L3_HASH_EN)
++ info->data |= RXH_IP_SRC | RXH_IP_DST;
++ if (hash_cfg & IPV6_VLAN_HASH_EN)
++ info->data |= RXH_VLAN;
++ break;
++ default:
++ return -EINVAL;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static int higmac_get_rxnfc(struct net_device *ndev,
-+ struct ethtool_rxnfc *info, u32 *rules)
++ struct ethtool_rxnfc *info, u32 *rules)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
-+ int ret = -EOPNOTSUPP;
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ int ret = -EOPNOTSUPP;
+
-+ switch (info->cmd) {
-+ case ETHTOOL_GRXRINGS:
-+ info->data = priv->num_rxqs;
-+ ret = 0;
-+ break;
-+ case ETHTOOL_GRXFH:
-+ return higmac_get_rss_hash_opts(priv, info);
-+ default:
-+ break;
-+ }
-+ return ret;
++ switch (info->cmd) {
++ case ETHTOOL_GRXRINGS:
++ info->data = priv->num_rxqs;
++ ret = 0;
++ break;
++ case ETHTOOL_GRXFH:
++ return higmac_get_rss_hash_opts(priv, info);
++ default:
++ break;
++ }
++ return ret;
+}
+
+static void higmac_config_hash_policy(struct higmac_netdev_local *priv)
+{
-+ writel(priv->rss_info.hash_cfg, priv->gmac_iobase + RSS_HASH_CONFIG);
++ writel(priv->rss_info.hash_cfg, priv->gmac_iobase + RSS_HASH_CONFIG);
+}
+
+static int higmac_set_rss_hash_opts(struct higmac_netdev_local *priv,
-+ struct ethtool_rxnfc *info)
++ struct ethtool_rxnfc *info)
+{
-+ u32 hash_cfg = priv->rss_info.hash_cfg;
++ u32 hash_cfg = priv->rss_info.hash_cfg;
+
-+ netdev_info(priv->netdev, "Set RSS flow type = %d, data = %lld\n",
-+ info->flow_type, info->data);
++ netdev_info(priv->netdev, "Set RSS flow type = %d, data = %lld\n",
++ info->flow_type, info->data);
+
-+ if (!(info->data & RXH_IP_SRC) || !(info->data & RXH_IP_DST)) {
-+ return -EINVAL;
-+ }
++ if (!(info->data & RXH_IP_SRC) || !(info->data & RXH_IP_DST))
++ return -EINVAL;
+
-+ switch (info->flow_type) {
-+ case TCP_V4_FLOW:
-+ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
-+ case 0:
-+ hash_cfg &= ~TCPV4_L4_HASH_EN;
-+ break;
-+ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
-+ hash_cfg |= TCPV4_L4_HASH_EN;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ if (info->data & RXH_VLAN) {
-+ hash_cfg |= TCPV4_VLAN_HASH_EN;
-+ } else {
-+ hash_cfg &= ~TCPV4_VLAN_HASH_EN;
-+ }
-+ break;
-+ case TCP_V6_FLOW:
-+ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
-+ case 0:
-+ hash_cfg &= ~TCPV6_L4_HASH_EN;
-+ break;
-+ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
-+ hash_cfg |= TCPV6_L4_HASH_EN;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ if (info->data & RXH_VLAN) {
-+ hash_cfg |= TCPV6_VLAN_HASH_EN;
-+ } else {
-+ hash_cfg &= ~TCPV6_VLAN_HASH_EN;
-+ }
-+ break;
-+ case UDP_V4_FLOW:
-+ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
-+ case 0:
-+ hash_cfg &= ~UDPV4_L4_HASH_EN;
-+ break;
-+ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
-+ hash_cfg |= UDPV4_L4_HASH_EN;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ if (info->data & RXH_VLAN) {
-+ hash_cfg |= UDPV4_VLAN_HASH_EN;
-+ } else {
-+ hash_cfg &= ~UDPV4_VLAN_HASH_EN;
-+ }
-+ break;
-+ case UDP_V6_FLOW:
-+ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
-+ case 0:
-+ hash_cfg &= ~UDPV6_L4_HASH_EN;
-+ break;
-+ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
-+ hash_cfg |= UDPV6_L4_HASH_EN;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ if (info->data & RXH_VLAN) {
-+ hash_cfg |= UDPV6_VLAN_HASH_EN;
-+ } else {
-+ hash_cfg &= ~UDPV6_VLAN_HASH_EN;
-+ }
-+ break;
-+ case IPV4_FLOW:
-+ if (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
-+ return -EINVAL;
-+ }
-+ if (info->data & RXH_VLAN) {
-+ hash_cfg |= IPV4_VLAN_HASH_EN;
-+ } else {
-+ hash_cfg &= ~IPV4_VLAN_HASH_EN;
-+ }
-+ break;
-+ case IPV6_FLOW:
-+ if (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
-+ return -EINVAL;
-+ }
-+ if (info->data & RXH_VLAN) {
-+ hash_cfg |= IPV6_VLAN_HASH_EN;
-+ } else {
-+ hash_cfg &= ~IPV6_VLAN_HASH_EN;
-+ }
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
++ switch (info->flow_type) {
++ case TCP_V4_FLOW:
++ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
++ case 0:
++ hash_cfg &= ~TCPV4_L4_HASH_EN;
++ break;
++ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
++ hash_cfg |= TCPV4_L4_HASH_EN;
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (info->data & RXH_VLAN)
++ hash_cfg |= TCPV4_VLAN_HASH_EN;
++ else
++ hash_cfg &= ~TCPV4_VLAN_HASH_EN;
++ break;
++ case TCP_V6_FLOW:
++ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
++ case 0:
++ hash_cfg &= ~TCPV6_L4_HASH_EN;
++ break;
++ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
++ hash_cfg |= TCPV6_L4_HASH_EN;
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (info->data & RXH_VLAN)
++ hash_cfg |= TCPV6_VLAN_HASH_EN;
++ else
++ hash_cfg &= ~TCPV6_VLAN_HASH_EN;
++ break;
++ case UDP_V4_FLOW:
++ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
++ case 0:
++ hash_cfg &= ~UDPV4_L4_HASH_EN;
++ break;
++ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
++ hash_cfg |= UDPV4_L4_HASH_EN;
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (info->data & RXH_VLAN)
++ hash_cfg |= UDPV4_VLAN_HASH_EN;
++ else
++ hash_cfg &= ~UDPV4_VLAN_HASH_EN;
++ break;
++ case UDP_V6_FLOW:
++ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
++ case 0:
++ hash_cfg &= ~UDPV6_L4_HASH_EN;
++ break;
++ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
++ hash_cfg |= UDPV6_L4_HASH_EN;
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (info->data & RXH_VLAN)
++ hash_cfg |= UDPV6_VLAN_HASH_EN;
++ else
++ hash_cfg &= ~UDPV6_VLAN_HASH_EN;
++ break;
++ case IPV4_FLOW:
++ if (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))
++ return -EINVAL;
++ if (info->data & RXH_VLAN)
++ hash_cfg |= IPV4_VLAN_HASH_EN;
++ else
++ hash_cfg &= ~IPV4_VLAN_HASH_EN;
++ break;
++ case IPV6_FLOW:
++ if (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))
++ return -EINVAL;
++ if (info->data & RXH_VLAN)
++ hash_cfg |= IPV6_VLAN_HASH_EN;
++ else
++ hash_cfg &= ~IPV6_VLAN_HASH_EN;
++ break;
++ default:
++ return -EINVAL;
++ }
+
-+ priv->rss_info.hash_cfg = hash_cfg;
-+ higmac_config_hash_policy(priv);
++ priv->rss_info.hash_cfg = hash_cfg;
++ higmac_config_hash_policy(priv);
+
-+ return 0;
++ return 0;
+}
+
+static int higmac_set_rxnfc(struct net_device *ndev, struct ethtool_rxnfc *info)
+{
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
+
-+ switch (info->cmd) {
-+ case ETHTOOL_SRXFH:
-+ return higmac_set_rss_hash_opts(priv, info);
-+ default:
-+ break;
-+ }
-+ return -EOPNOTSUPP;
++ switch (info->cmd) {
++ case ETHTOOL_SRXFH:
++ return higmac_set_rss_hash_opts(priv, info);
++ default:
++ break;
++ }
++ return -EOPNOTSUPP;
+}
+
+static const struct ethtool_ops hieth_ethtools_ops = {
-+ .get_drvinfo = higmac_get_drvinfo,
-+ .get_link = higmac_get_link,
-+ .get_settings = higmac_get_settings,
-+ .set_settings = higmac_set_settings,
-+ .get_pauseparam = higmac_get_pauseparam,
-+ .set_pauseparam = higmac_set_pauseparam,
-+ .get_msglevel = higmac_ethtool_getmsglevel,
-+ .set_msglevel = higmac_ethtool_setmsglevel,
-+ .get_rxfh_key_size = higmac_get_rxfh_key_size,
-+ .get_rxfh_indir_size = higmac_get_rxfh_indir_size,
-+ .get_rxfh = higmac_get_rxfh,
-+ .set_rxfh = higmac_set_rxfh,
-+ .get_rxnfc = higmac_get_rxnfc,
-+ .set_rxnfc = higmac_set_rxnfc,
++ .get_drvinfo = higmac_get_drvinfo,
++ .get_link = higmac_get_link,
++ .get_settings = higmac_get_settings,
++ .set_settings = higmac_set_settings,
++ .get_pauseparam = higmac_get_pauseparam,
++ .set_pauseparam = higmac_set_pauseparam,
++ .get_msglevel = higmac_ethtool_getmsglevel,
++ .set_msglevel = higmac_ethtool_setmsglevel,
++ .get_rxfh_key_size = higmac_get_rxfh_key_size,
++ .get_rxfh_indir_size = higmac_get_rxfh_indir_size,
++ .get_rxfh = higmac_get_rxfh,
++ .set_rxfh = higmac_set_rxfh,
++ .get_rxnfc = higmac_get_rxnfc,
++ .set_rxnfc = higmac_set_rxnfc,
+};
+
+static const struct net_device_ops hieth_netdev_ops = {
-+ .ndo_open = higmac_net_open,
-+ .ndo_stop = higmac_net_close,
-+ .ndo_start_xmit = higmac_net_xmit,
-+ .ndo_tx_timeout = higmac_net_timeout,
-+ .ndo_set_rx_mode = higmac_set_multicast_list,
-+ .ndo_set_features = higmac_set_features,
-+ .ndo_do_ioctl = higmac_ioctl,
-+ .ndo_set_mac_address = higmac_net_set_mac_address,
-+ .ndo_change_mtu = eth_change_mtu,
-+ .ndo_get_stats = higmac_net_get_stats,
++ .ndo_open = higmac_net_open,
++ .ndo_stop = higmac_net_close,
++ .ndo_start_xmit = higmac_net_xmit,
++ .ndo_tx_timeout = higmac_net_timeout,
++ .ndo_set_rx_mode = higmac_set_multicast_list,
++ .ndo_set_features = higmac_set_features,
++ .ndo_do_ioctl = higmac_ioctl,
++ .ndo_set_mac_address = higmac_net_set_mac_address,
++ .ndo_change_mtu = eth_change_mtu,
++ .ndo_get_stats = higmac_net_get_stats,
+};
+
+static int higmac_of_get_param(struct higmac_netdev_local *ld,
-+ struct device_node *node)
++ struct device_node *node)
+{
-+ /* get auto eee */
-+ ld->autoeee = of_property_read_bool(node, "autoeee");
-+ /* get internal flag */
-+ ld->internal_phy =
-+ of_property_read_bool(node, "internal-phy");
++ /* get auto eee */
++ ld->autoeee = of_property_read_bool(node, "autoeee");
++ /* get internal flag */
++ ld->internal_phy =
++ of_property_read_bool(node, "internal-phy");
+
-+ return 0;
++ return 0;
+}
+
+static int KSZ8051MNL_phy_fix(struct phy_device *phy_dev)
+{
-+ u32 v;
-+ int ret;
++ u32 v;
++ int ret;
+
-+ if (phy_dev->interface != PHY_INTERFACE_MODE_RMII) {
-+ return 0;
-+ }
++ if (phy_dev->interface != PHY_INTERFACE_MODE_RMII)
++ return 0;
+
-+ ret = phy_read(phy_dev, 0x1F);
-+ if (ret < 0) {
-+ return ret;
-+ }
-+ v = ret;
-+ v |= (1 << 7); /* set phy RMII 50MHz clk; */
-+ phy_write(phy_dev, 0x1F, v);
++ ret = phy_read(phy_dev, 0x1F);
++ if (ret < 0)
++ return ret;
++ v = ret;
++ v |= (1 << 7); /* set phy RMII 50MHz clk; */
++ phy_write(phy_dev, 0x1F, v);
+
-+ ret = phy_read(phy_dev, 0x16);
-+ if (ret < 0) {
-+ return ret;
-+ }
-+ v = ret;
-+ v |= (1 << 1); /* set phy RMII override; */
-+ phy_write(phy_dev, 0x16, v);
++ ret = phy_read(phy_dev, 0x16);
++ if (ret < 0)
++ return ret;
++ v = ret;
++ v |= (1 << 1); /* set phy RMII override; */
++ phy_write(phy_dev, 0x16, v);
+
-+ return 0;
++ return 0;
+}
+
+static int KSZ8081RNB_phy_fix(struct phy_device *phy_dev)
+{
-+ u32 v;
-+ int ret;
++ u32 v;
++ int ret;
+
-+ if (phy_dev->interface != PHY_INTERFACE_MODE_RMII) {
-+ return 0;
-+ }
++ if (phy_dev->interface != PHY_INTERFACE_MODE_RMII)
++ return 0;
+
-+ ret = phy_read(phy_dev, 0x1F);
-+ if (ret < 0) {
-+ return ret;
-+ }
-+ v = ret;
-+ v |= (1 << 7); /* set phy RMII 50MHz clk; */
-+ phy_write(phy_dev, 0x1F, v);
++ ret = phy_read(phy_dev, 0x1F);
++ if (ret < 0)
++ return ret;
++ v = ret;
++ v |= (1 << 7); /* set phy RMII 50MHz clk; */
++ phy_write(phy_dev, 0x1F, v);
+
-+ return 0;
++ return 0;
+}
+
+static int rtl8211e_phy_fix(struct phy_device *phy_dev)
+{
-+ u32 v;
-+ int ret;
++ u32 v;
++ int ret;
+
-+ /* select Extension page */
-+ phy_write(phy_dev, 0x1f, 0x7);
-+ /* switch ExtPage 164 */
-+ phy_write(phy_dev, 0x1e, 0xa4);
++ /* select Extension page */
++ phy_write(phy_dev, 0x1f, 0x7);
++ /* switch ExtPage 164 */
++ phy_write(phy_dev, 0x1e, 0xa4);
+
-+ /* config RGMII rx pin io driver max */
-+ ret = phy_read(phy_dev, 0x1c);
-+ if (ret < 0) {
-+ return ret;
-+ }
-+ v = ret;
-+ v = (v & 0xff03) | 0xfc;
-+ phy_write(phy_dev, 0x1c, v);
++ /* config RGMII rx pin io driver max */
++ ret = phy_read(phy_dev, 0x1c);
++ if (ret < 0)
++ return ret;
++ v = ret;
++ v = (v & 0xff03) | 0xfc;
++ phy_write(phy_dev, 0x1c, v);
+
-+ /* select to page 0 */
-+ phy_write(phy_dev, 0x1f, 0);
++ /* select to page 0 */
++ phy_write(phy_dev, 0x1f, 0);
+
-+ return 0;
++ return 0;
+}
+
+static void phy_register_fixups(void)
+{
-+ phy_register_fixup_for_uid(PHY_ID_KSZ8051MNL, DEFAULT_PHY_MASK,
-+ KSZ8051MNL_phy_fix);
-+ phy_register_fixup_for_uid(PHY_ID_KSZ8081RNB, DEFAULT_PHY_MASK,
-+ KSZ8081RNB_phy_fix);
-+ phy_register_fixup_for_uid(REALTEK_PHY_ID_8211E, REALTEK_PHY_MASK,
-+ rtl8211e_phy_fix);
++ phy_register_fixup_for_uid(PHY_ID_KSZ8051MNL, DEFAULT_PHY_MASK,
++ KSZ8051MNL_phy_fix);
++ phy_register_fixup_for_uid(PHY_ID_KSZ8081RNB, DEFAULT_PHY_MASK,
++ KSZ8081RNB_phy_fix);
++ phy_register_fixup_for_uid(REALTEK_PHY_ID_8211E, REALTEK_PHY_MASK,
++ rtl8211e_phy_fix);
+}
+
+static void phy_unregister_fixups(void)
+{
-+ phy_unregister_fixup_for_uid(PHY_ID_KSZ8051MNL, DEFAULT_PHY_MASK);
-+ phy_unregister_fixup_for_uid(PHY_ID_KSZ8081RNB, DEFAULT_PHY_MASK);
-+ phy_unregister_fixup_for_uid(REALTEK_PHY_ID_8211E, REALTEK_PHY_MASK);
++ phy_unregister_fixup_for_uid(PHY_ID_KSZ8051MNL, DEFAULT_PHY_MASK);
++ phy_unregister_fixup_for_uid(PHY_ID_KSZ8081RNB, DEFAULT_PHY_MASK);
++ phy_unregister_fixup_for_uid(REALTEK_PHY_ID_8211E, REALTEK_PHY_MASK);
+}
+
+static void higmac_verify_flow_ctrl_args(void)
+{
+#if defined(CONFIG_TX_FLOW_CTRL_SUPPORT)
-+ flow_ctrl_en |= FLOW_TX;
++ flow_ctrl_en |= FLOW_TX;
+#endif
+#if defined(CONFIG_RX_FLOW_CTRL_SUPPORT)
-+ flow_ctrl_en |= FLOW_RX;
++ flow_ctrl_en |= FLOW_RX;
+#endif
-+ if (tx_flow_ctrl_active_threshold < FC_ACTIVE_MIN ||
-+ tx_flow_ctrl_active_threshold > FC_ACTIVE_MAX) {
-+ tx_flow_ctrl_active_threshold = FC_ACTIVE_DEFAULT;
-+ }
++ if (tx_flow_ctrl_active_threshold < FC_ACTIVE_MIN ||
++ tx_flow_ctrl_active_threshold > FC_ACTIVE_MAX)
++ tx_flow_ctrl_active_threshold = FC_ACTIVE_DEFAULT;
+
-+ if (tx_flow_ctrl_deactive_threshold < FC_DEACTIVE_MIN ||
-+ tx_flow_ctrl_deactive_threshold > FC_DEACTIVE_MAX) {
-+ tx_flow_ctrl_deactive_threshold = FC_DEACTIVE_DEFAULT;
-+ }
++ if (tx_flow_ctrl_deactive_threshold < FC_DEACTIVE_MIN ||
++ tx_flow_ctrl_deactive_threshold > FC_DEACTIVE_MAX)
++ tx_flow_ctrl_deactive_threshold = FC_DEACTIVE_DEFAULT;
+
-+ if (tx_flow_ctrl_active_threshold >= tx_flow_ctrl_deactive_threshold) {
-+ tx_flow_ctrl_active_threshold = FC_ACTIVE_DEFAULT;
-+ tx_flow_ctrl_deactive_threshold = FC_DEACTIVE_DEFAULT;
-+ }
++ if (tx_flow_ctrl_active_threshold >= tx_flow_ctrl_deactive_threshold) {
++ tx_flow_ctrl_active_threshold = FC_ACTIVE_DEFAULT;
++ tx_flow_ctrl_deactive_threshold = FC_DEACTIVE_DEFAULT;
++ }
+
-+ if (tx_flow_ctrl_pause_time < 0 ||
-+ tx_flow_ctrl_pause_time > FC_PAUSE_TIME_MAX) {
-+ tx_flow_ctrl_pause_time = FC_PAUSE_TIME_DEFAULT;
-+ }
++ if (tx_flow_ctrl_pause_time < 0 ||
++ tx_flow_ctrl_pause_time > FC_PAUSE_TIME_MAX)
++ tx_flow_ctrl_pause_time = FC_PAUSE_TIME_DEFAULT;
+
-+ if (tx_flow_ctrl_pause_interval < 0 ||
-+ tx_flow_ctrl_pause_interval > FC_PAUSE_TIME_MAX) {
-+ tx_flow_ctrl_pause_interval = FC_PAUSE_INTERVAL_DEFAULT;
-+ }
++ if (tx_flow_ctrl_pause_interval < 0 ||
++ tx_flow_ctrl_pause_interval > FC_PAUSE_TIME_MAX)
++ tx_flow_ctrl_pause_interval = FC_PAUSE_INTERVAL_DEFAULT;
+
-+ /* pause interval should not bigger than pause time,
-+ * but should not too smaller to avoid sending too many pause frame.
-+ */
-+ if ((tx_flow_ctrl_pause_interval > tx_flow_ctrl_pause_time) ||
-+ (tx_flow_ctrl_pause_interval < (tx_flow_ctrl_pause_time >> 1))) {
-+ tx_flow_ctrl_pause_interval = tx_flow_ctrl_pause_time;
-+ }
++ /* pause interval should not bigger than pause time,
++ * but should not too smaller to avoid sending too many pause frame.
++ */
++ if ((tx_flow_ctrl_pause_interval > tx_flow_ctrl_pause_time) ||
++ (tx_flow_ctrl_pause_interval < ((unsigned int)tx_flow_ctrl_pause_time >> 1)))
++ tx_flow_ctrl_pause_interval = tx_flow_ctrl_pause_time;
+}
+
+static void higmac_destroy_hw_desc_queue(struct higmac_netdev_local *priv)
+{
-+ int i;
++ int i;
+
-+ for (i = 0; i < QUEUE_NUMS + RSS_NUM_RXQS - 1; i++) {
-+ if (priv->pool[i].desc) {
-+ if (HAS_CAP_CCI(priv->hw_cap)) {
-+ kfree(priv->pool[i].desc);
-+ } else {
-+ dma_free_coherent(priv->dev, priv->pool[i].size,
-+ priv->pool[i].desc,
-+ priv->pool[i].phys_addr);
-+ }
-+ priv->pool[i].desc = NULL;
-+ }
-+ }
++ for (i = 0; i < QUEUE_NUMS + RSS_NUM_RXQS - 1; i++) {
++ if (priv->pool[i].desc) {
++ if (HAS_CAP_CCI(priv->hw_cap))
++ kfree(priv->pool[i].desc);
++ else
++ dma_free_coherent(priv->dev, priv->pool[i].size,
++ priv->pool[i].desc,
++ priv->pool[i].phys_addr);
++ priv->pool[i].desc = NULL;
++ }
++ }
+
-+ kfree(priv->rx_fq.skb);
-+ kfree(priv->tx_bq.skb);
-+ priv->rx_fq.skb = NULL;
-+ priv->tx_bq.skb = NULL;
++ kfree(priv->rx_fq.skb);
++ kfree(priv->tx_bq.skb);
++ priv->rx_fq.skb = NULL;
++ priv->tx_bq.skb = NULL;
+
-+ if (priv->tso_supported) {
-+ kfree(priv->tx_bq.sg_desc_offset);
-+ priv->tx_bq.sg_desc_offset = NULL;
-+ }
++ if (priv->tso_supported) {
++ kfree(priv->tx_bq.sg_desc_offset);
++ priv->tx_bq.sg_desc_offset = NULL;
++ }
+
-+ kfree(priv->tx_skb);
-+ priv->tx_skb = NULL;
++ kfree(priv->tx_skb);
++ priv->tx_skb = NULL;
+
-+ kfree(priv->rx_skb);
-+ priv->rx_skb = NULL;
++ kfree(priv->rx_skb);
++ priv->rx_skb = NULL;
+}
+
+static int higmac_init_hw_desc_queue(struct higmac_netdev_local *priv)
+{
-+ struct device *dev = priv->dev;
-+ struct higmac_desc *virt_addr;
-+ dma_addr_t phys_addr = 0;
-+ int size, i;
++ struct device *dev = priv->dev;
++ struct higmac_desc *virt_addr = NULL;
++ dma_addr_t phys_addr = 0;
++ int size, i;
+
-+ priv->rx_fq.count = RX_DESC_NUM;
-+ priv->rx_bq.count = RX_DESC_NUM;
-+ priv->tx_bq.count = TX_DESC_NUM;
-+ priv->tx_rq.count = TX_DESC_NUM;
++ priv->rx_fq.count = RX_DESC_NUM;
++ priv->rx_bq.count = RX_DESC_NUM;
++ priv->tx_bq.count = TX_DESC_NUM;
++ priv->tx_rq.count = TX_DESC_NUM;
+
-+ for (i = 1; i < RSS_NUM_RXQS; i++) {
-+ priv->pool[3 + i].count = RX_DESC_NUM;
-+ }
++ for (i = 1; i < RSS_NUM_RXQS; i++)
++ priv->pool[3 + i].count = RX_DESC_NUM;
+
-+ for (i = 0; i < (QUEUE_NUMS + RSS_NUM_RXQS - 1); i++) {
-+ size = priv->pool[i].count * sizeof(struct higmac_desc);
-+ if (HAS_CAP_CCI(priv->hw_cap)) {
-+ virt_addr = kmalloc(size, GFP_KERNEL);
-+ if (virt_addr) {
-+ phys_addr = virt_to_phys(virt_addr);
-+ }
-+ } else {
-+ virt_addr = dma_alloc_coherent(dev, size, &phys_addr,
-+ GFP_KERNEL);
-+ }
-+ if (!virt_addr) {
-+ goto error_free_pool;
-+ }
++ for (i = 0; i < (QUEUE_NUMS + RSS_NUM_RXQS - 1); i++) {
++ size = priv->pool[i].count * sizeof(struct higmac_desc);
++ if (HAS_CAP_CCI(priv->hw_cap)) {
++ virt_addr = kmalloc(size, GFP_KERNEL);
++ if (virt_addr) {
++ memset(virt_addr, 0, size);
++ phys_addr = virt_to_phys(virt_addr);
++ }
++ } else {
++ virt_addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
++ if (virt_addr) {
++ memset(virt_addr, 0, size);
++ }
++ }
++ if (virt_addr == NULL)
++ goto error_free_pool;
+
-+ memset(virt_addr, 0, size);
-+ priv->pool[i].size = size;
-+ priv->pool[i].desc = virt_addr;
-+ priv->pool[i].phys_addr = phys_addr;
-+ }
-+ priv->rx_fq.skb = kzalloc(priv->rx_fq.count * sizeof(struct sk_buff *), GFP_KERNEL);
-+ if (!priv->rx_fq.skb) {
-+ goto error_free_pool;
-+ }
++ priv->pool[i].size = size;
++ priv->pool[i].desc = virt_addr;
++ priv->pool[i].phys_addr = phys_addr;
++ }
++ priv->rx_fq.skb = kzalloc(priv->rx_fq.count
++ * sizeof(struct sk_buff *), GFP_KERNEL);
++ if (!priv->rx_fq.skb)
++ goto error_free_pool;
+
-+ priv->rx_skb = kzalloc(priv->rx_fq.count * sizeof(struct sk_buff *), GFP_KERNEL);
-+ if (!priv->rx_skb) {
-+ goto error_free_pool;
-+ }
++ priv->rx_skb = kzalloc(priv->rx_fq.count
++ * sizeof(struct sk_buff *), GFP_KERNEL);
++ if (!priv->rx_skb)
++ goto error_free_pool;
+
-+ priv->tx_bq.skb = kzalloc(priv->tx_bq.count * sizeof(struct sk_buff *), GFP_KERNEL);
-+ if (!priv->tx_bq.skb) {
-+ goto error_free_pool;
-+ }
++ priv->tx_bq.skb = kzalloc(priv->tx_bq.count
++ * sizeof(struct sk_buff *), GFP_KERNEL);
++ if (!priv->tx_bq.skb)
++ goto error_free_pool;
+
-+ priv->tx_skb = kzalloc(priv->tx_bq.count * sizeof(struct sk_buff *), GFP_KERNEL);
-+ if (!priv->tx_skb) {
-+ goto error_free_pool;
-+ }
++ priv->tx_skb = kzalloc(priv->tx_bq.count
++ * sizeof(struct sk_buff *), GFP_KERNEL);
++ if (!priv->tx_skb)
++ goto error_free_pool;
+
-+ if (priv->tso_supported) {
-+ priv->tx_bq.sg_desc_offset = kzalloc(priv->tx_bq.count * sizeof(int), GFP_KERNEL);
-+ if (!priv->tx_bq.sg_desc_offset) {
-+ goto error_free_pool;
-+ }
-+ }
++ if (priv->tso_supported) {
++ priv->tx_bq.sg_desc_offset = kzalloc(priv->tx_bq.count
++ * sizeof(int), GFP_KERNEL);
++ if (!priv->tx_bq.sg_desc_offset)
++ goto error_free_pool;
++ }
+
-+ higmac_hw_set_desc_addr(priv);
-+ if (HAS_CAP_CCI(priv->hw_cap)) {
-+ pr_info("higmac: ETH MAC supporte CCI.\n");
-+ }
++ higmac_hw_set_desc_addr(priv);
++ if (HAS_CAP_CCI(priv->hw_cap))
++ pr_info("higmac: ETH MAC supporte CCI.\n");
+
-+ return 0;
++ return 0;
+
+error_free_pool:
-+ higmac_destroy_hw_desc_queue(priv);
++ higmac_destroy_hw_desc_queue(priv);
+
-+ return -ENOMEM;
++ return -ENOMEM;
+}
+
+void higmac_init_napi(struct higmac_netdev_local *priv)
+{
-+ struct higmac_napi *q_napi;
-+ int i;
++ struct higmac_napi *q_napi = NULL;
++ int i;
+
-+ for (i = 0; i < priv->num_rxqs; i++) {
-+ q_napi = &priv->q_napi[i];
-+ q_napi->rxq_id = i;
-+ q_napi->ndev_priv = priv;
-+ netif_napi_add(priv->netdev, &q_napi->napi, higmac_poll,
-+ NAPI_POLL_WEIGHT);
-+ }
++ for (i = 0; i < priv->num_rxqs; i++) {
++ q_napi = &priv->q_napi[i];
++ q_napi->rxq_id = i;
++ q_napi->ndev_priv = priv;
++ netif_napi_add(priv->netdev, &q_napi->napi, higmac_poll,
++ NAPI_POLL_WEIGHT);
++ }
+}
+
+void higmac_destroy_napi(struct higmac_netdev_local *priv)
+{
-+ struct higmac_napi *q_napi;
-+ int i;
++ struct higmac_napi *q_napi = NULL;
++ int i;
+
-+ for (i = 0; i < priv->num_rxqs; i++) {
-+ q_napi = &priv->q_napi[i];
-+ netif_napi_del(&q_napi->napi);
-+ }
++ for (i = 0; i < priv->num_rxqs; i++) {
++ q_napi = &priv->q_napi[i];
++ netif_napi_del(&q_napi->napi);
++ }
+}
+
+int higmac_request_irqs(struct platform_device *pdev,
-+ struct higmac_netdev_local *priv)
++ struct higmac_netdev_local *priv)
+{
-+ struct device *dev = priv->dev;
-+ int ret;
-+ int i;
++ struct device *dev = priv->dev;
++ int ret;
++ int i;
+
-+ for (i = 0; i < priv->num_rxqs; i++) {
-+ ret = platform_get_irq(pdev, i);
-+ if (ret < 0) {
-+ dev_err(dev, "No irq[%d] resource, ret=%d\n", i, ret);
-+ return ret;
-+ }
-+ priv->irq[i] = ret;
++ for (i = 0; i < priv->num_rxqs; i++) {
++ ret = platform_get_irq(pdev, i);
++ if (ret < 0) {
++ dev_err(dev, "No irq[%d] resource, ret=%d\n", i, ret);
++ return ret;
++ }
++ priv->irq[i] = ret;
+
-+ ret = devm_request_irq(dev, priv->irq[i], higmac_interrupt,
-+ IRQF_SHARED, pdev->name,
-+ &priv->q_napi[i]);
-+ if (ret) {
-+ dev_err(dev, "devm_request_irq failed, ret=%d\n", ret);
-+ return ret;
-+ }
-+ }
++ ret = devm_request_irq(dev, priv->irq[i], higmac_interrupt,
++ IRQF_SHARED, pdev->name,
++ &priv->q_napi[i]);
++ if (ret) {
++ dev_err(dev, "devm_request_irq failed, ret=%d\n", ret);
++ return ret;
++ }
++ }
+
-+ return 0;
++ return 0;
+}
+
+static int higmac_dev_probe(struct platform_device *pdev)
+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *node = dev->of_node;
-+ struct net_device *ndev;
-+ struct higmac_netdev_local *priv;
-+ struct resource *res;
-+ const char *mac_addr;
-+ unsigned int hw_cap;
-+ int ret;
-+ int num_rxqs;
-+ bool fixed_link = false;
++ struct device *dev = &pdev->dev;
++ struct device_node *node = dev->of_node;
++ struct net_device *ndev = NULL;
++ struct higmac_netdev_local *priv = NULL;
++ struct resource *res = NULL;
++ const char *mac_addr = NULL;
++ unsigned int hw_cap;
++ int ret;
++ int num_rxqs;
++ bool fixed_link = false;
+
-+ higmac_verify_flow_ctrl_args();
++ higmac_verify_flow_ctrl_args();
+
-+ if (of_device_is_compatible(node, "hisilicon,higmac-v5")) {
-+ num_rxqs = RSS_NUM_RXQS;
-+ } else {
-+ num_rxqs = 1;
-+ }
++ if (of_device_is_compatible(node, "hisilicon,higmac-v5"))
++ num_rxqs = RSS_NUM_RXQS;
++ else
++ num_rxqs = 1;
+
-+ ndev = alloc_etherdev_mqs(sizeof(struct higmac_netdev_local), 1,
-+ num_rxqs);
-+ if (!ndev) {
-+ return -ENOMEM;
-+ }
++ ndev = alloc_etherdev_mqs(sizeof(struct higmac_netdev_local), 1,
++ num_rxqs);
++ if (!ndev)
++ return -ENOMEM;
+
-+ platform_set_drvdata(pdev, ndev);
-+ SET_NETDEV_DEV(ndev, dev);
++ platform_set_drvdata(pdev, ndev);
++ SET_NETDEV_DEV(ndev, dev);
+
-+ priv = netdev_priv(ndev);
-+ priv->dev = dev;
-+ priv->netdev = ndev;
-+ priv->num_rxqs = num_rxqs;
++ priv = netdev_priv(ndev);
++ priv->dev = dev;
++ dev_hold(ndev);
++ priv->netdev = ndev;
++ priv->num_rxqs = num_rxqs;
+
-+ if (of_device_is_compatible(node, "hisilicon,higmac-v3")) {
-+ priv->hw_cap |= HW_CAP_CCI;
-+ }
++ if (of_device_is_compatible(node, "hisilicon,higmac-v3"))
++ priv->hw_cap |= HW_CAP_CCI;
+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, MEM_GMAC_IOBASE);
-+ priv->gmac_iobase = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(priv->gmac_iobase)) {
-+ ret = PTR_ERR(priv->gmac_iobase);
-+ goto out_free_netdev;
-+ }
++ res = platform_get_resource(pdev, IORESOURCE_MEM, MEM_GMAC_IOBASE);
++ priv->gmac_iobase = devm_ioremap_resource(dev, res);
++ if (IS_ERR(priv->gmac_iobase)) {
++ ret = PTR_ERR(priv->gmac_iobase);
++ goto out_free_netdev;
++ }
+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM,
-+ MEM_MACIF_IOBASE);
-+ priv->macif_base = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(priv->macif_base)) {
-+ ret = PTR_ERR(priv->macif_base);
-+ goto out_free_netdev;
-+ }
++ res = platform_get_resource(pdev, IORESOURCE_MEM,
++ MEM_MACIF_IOBASE);
++ priv->macif_base = devm_ioremap_resource(dev, res);
++ if (IS_ERR(priv->macif_base)) {
++ ret = PTR_ERR(priv->macif_base);
++ goto out_free_netdev;
++ }
+
-+ /* only for some chip to fix AXI bus burst and outstanding config */
-+ res = platform_get_resource(pdev, IORESOURCE_MEM,
-+ MEM_AXI_BUS_CFG_IOBASE);
-+ priv->axi_bus_cfg_base = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(priv->axi_bus_cfg_base)) {
-+ priv->axi_bus_cfg_base = NULL;
-+ }
++ /* only for some chip to fix AXI bus burst and outstanding config */
++ res = platform_get_resource(pdev, IORESOURCE_MEM,
++ MEM_AXI_BUS_CFG_IOBASE);
++ priv->axi_bus_cfg_base = devm_ioremap_resource(dev, res);
++ if (IS_ERR(priv->axi_bus_cfg_base))
++ priv->axi_bus_cfg_base = NULL;
+
-+ priv->port_rst = devm_reset_control_get(dev, HIGMAC_PORT_RST_NAME);
-+ if (IS_ERR(priv->port_rst)) {
-+ ret = PTR_ERR(priv->port_rst);
-+ goto out_free_netdev;
-+ }
++ priv->port_rst = devm_reset_control_get(dev, HIGMAC_PORT_RST_NAME);
++ if (IS_ERR(priv->port_rst)) {
++ ret = PTR_ERR(priv->port_rst);
++ goto out_free_netdev;
++ }
+
-+ priv->macif_rst = devm_reset_control_get(dev, HIGMAC_MACIF_RST_NAME);
-+ if (IS_ERR(priv->macif_rst)) {
-+ ret = PTR_ERR(priv->macif_rst);
-+ goto out_free_netdev;
-+ }
++ priv->macif_rst = devm_reset_control_get(dev, HIGMAC_MACIF_RST_NAME);
++ if (IS_ERR(priv->macif_rst)) {
++ ret = PTR_ERR(priv->macif_rst);
++ goto out_free_netdev;
++ }
+
-+ priv->phy_rst = devm_reset_control_get(dev, HIGMAC_PHY_RST_NAME);
-+ if (IS_ERR(priv->phy_rst)) {
-+ priv->phy_rst = NULL;
-+ }
++ priv->phy_rst = devm_reset_control_get(dev, HIGMAC_PHY_RST_NAME);
++ if (IS_ERR(priv->phy_rst))
++ priv->phy_rst = NULL;
+
-+ priv->clk = devm_clk_get(&pdev->dev, HIGMAC_MAC_CLK_NAME);
-+ if (IS_ERR(priv->clk)) {
-+ netdev_err(ndev, "failed to get clk\n");
-+ ret = -ENODEV;
-+ goto out_free_netdev;
-+ }
++ priv->clk = devm_clk_get(&pdev->dev, HIGMAC_MAC_CLK_NAME);
++ if (IS_ERR(priv->clk)) {
++ netdev_err(ndev, "failed to get clk\n");
++ ret = -ENODEV;
++ goto out_free_netdev;
++ }
+
-+ ret = clk_prepare_enable(priv->clk);
-+ if (ret < 0) {
-+ netdev_err(ndev, "failed to enable clk %d\n", ret);
-+ goto out_free_netdev;
-+ }
++ ret = clk_prepare_enable(priv->clk);
++ if (ret < 0) {
++ netdev_err(ndev, "failed to enable clk %d\n", ret);
++ goto out_free_netdev;
++ }
+
-+ priv->macif_clk = devm_clk_get(&pdev->dev, HIGMAC_MACIF_CLK_NAME);
-+ if (IS_ERR(priv->macif_clk)) {
-+ priv->macif_clk = NULL;
-+ }
++ priv->macif_clk = devm_clk_get(&pdev->dev, HIGMAC_MACIF_CLK_NAME);
++ if (IS_ERR(priv->macif_clk))
++ priv->macif_clk = NULL;
+
-+ if (priv->macif_clk) {
-+ ret = clk_prepare_enable(priv->macif_clk);
-+ if (ret < 0) {
-+ netdev_err(ndev, "failed enable macif_clk %d\n", ret);
-+ goto out_clk_disable;
-+ }
-+ }
++ if (priv->macif_clk) {
++ ret = clk_prepare_enable(priv->macif_clk);
++ if (ret < 0) {
++ netdev_err(ndev, "failed enable macif_clk %d\n", ret);
++ goto out_clk_disable;
++ }
++ }
+
-+ higmac_mac_core_reset(priv);
++ higmac_mac_core_reset(priv);
+
-+ /* phy reset, should be early than "of_mdiobus_register".
-+ * becausue "of_mdiobus_register" will read PHY register by MDIO.
-+ */
-+ higmac_hw_phy_reset(priv);
++ /* phy reset, should be early than "of_mdiobus_register".
++ * becausue "of_mdiobus_register" will read PHY register by MDIO.
++ */
++ higmac_hw_phy_reset(priv);
+
-+ higmac_of_get_param(priv, node);
++ higmac_of_get_param(priv, node);
+
-+ ret = of_get_phy_mode(node);
-+ if (ret < 0) {
-+ netdev_err(ndev, "not find phy-mode\n");
-+ goto out_macif_clk_disable;
-+ }
-+ priv->phy_mode = ret;
++ ret = of_get_phy_mode(node);
++ if (ret < 0) {
++ netdev_err(ndev, "not find phy-mode\n");
++ goto out_macif_clk_disable;
++ }
++ priv->phy_mode = ret;
+
-+ priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
-+ if (!priv->phy_node) {
-+ /* check if a fixed-link is defined in device-tree */
-+ if (of_phy_is_fixed_link(node)) {
-+ ret = of_phy_register_fixed_link(node);
-+ if (ret < 0) {
-+ dev_err(dev, "cannot register fixed PHY %d\n", ret);
-+ goto out_macif_clk_disable;
-+ }
++ priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
++ if (!priv->phy_node) {
++ /* check if a fixed-link is defined in device-tree */
++ if (of_phy_is_fixed_link(node)) {
++ ret = of_phy_register_fixed_link(node);
++ if (ret < 0) {
++ dev_err(dev, "cannot register fixed PHY %d\n", ret);
++ goto out_macif_clk_disable;
++ }
+
-+ /* In the case of a fixed PHY, the DT node associated
-+ * to the PHY is the Ethernet MAC DT node.
-+ */
-+ priv->phy_node = of_node_get(node);
-+ fixed_link = true;
-+ } else {
-+ netdev_err(ndev, "not find phy-handle\n");
-+ ret = -EINVAL;
-+ goto out_macif_clk_disable;
-+ }
-+ }
++ /* In the case of a fixed PHY, the DT node associated
++ * to the PHY is the Ethernet MAC DT node.
++ */
++ priv->phy_node = of_node_get(node);
++ fixed_link = true;
++ } else {
++ netdev_err(ndev, "not find phy-handle\n");
++ ret = -EINVAL;
++ goto out_macif_clk_disable;
++ }
++ }
+
-+ mac_addr = of_get_mac_address(node);
-+ if (mac_addr) {
-+ ether_addr_copy(ndev->dev_addr, mac_addr);
-+ }
-+ if (!is_valid_ether_addr(ndev->dev_addr)) {
-+ eth_hw_addr_random(ndev);
-+ netdev_warn(ndev, "using random MAC address %pM\n",
-+ ndev->dev_addr);
-+ }
++ mac_addr = of_get_mac_address(node);
++ if (mac_addr)
++ ether_addr_copy(ndev->dev_addr, mac_addr);
++ if (!is_valid_ether_addr(ndev->dev_addr)) {
++ eth_hw_addr_random(ndev);
++ netdev_warn(ndev, "using random MAC address %pM\n",
++ ndev->dev_addr);
++ }
+
-+ higmac_hw_set_mac_addr(ndev);
++ higmac_hw_set_mac_addr(ndev);
+
-+ hw_cap = readl(priv->gmac_iobase + CRF_MIN_PACKET);
-+ priv->tso_supported = HAS_TSO_CAP(hw_cap);
-+ priv->has_rxhash_cap = HAS_RXHASH_CAP(hw_cap);
-+ priv->has_rss_cap = HAS_RSS_CAP(hw_cap);
++ hw_cap = readl(priv->gmac_iobase + CRF_MIN_PACKET);
++ priv->tso_supported = HAS_TSO_CAP(hw_cap);
++ priv->has_rxhash_cap = HAS_RXHASH_CAP(hw_cap);
++ priv->has_rss_cap = HAS_RSS_CAP(hw_cap);
+
-+ higmac_set_rss_cap(priv);
-+ higmac_get_rss_key(priv);
-+ if (priv->has_rss_cap) {
-+ priv->rss_info.ind_tbl_size = RSS_INDIRECTION_TABLE_SIZE;
-+ higmac_get_rss(priv);
-+ }
++ higmac_set_rss_cap(priv);
++ higmac_get_rss_key(priv);
++ if (priv->has_rss_cap) {
++ priv->rss_info.ind_tbl_size = RSS_INDIRECTION_TABLE_SIZE;
++ higmac_get_rss(priv);
++ }
+
-+ if (priv->has_rxhash_cap) {
-+ priv->rss_info.hash_cfg = DEF_HASH_CFG;
-+ higmac_config_hash_policy(priv);
-+ }
++ if (priv->has_rxhash_cap) {
++ priv->rss_info.hash_cfg = DEF_HASH_CFG;
++ higmac_config_hash_policy(priv);
++ }
+
-+ /* init hw controller */
-+ higmac_hw_init(priv);
++ /* init hw controller */
++ higmac_hw_init(priv);
+
-+ /* TODO: phy fix here?? other way ??? */
-+ phy_register_fixups();
++ /* TODO: phy fix here?? other way ??? */
++ phy_register_fixups();
+
-+ priv->phy = of_phy_connect(ndev, priv->phy_node,
-+ &higmac_adjust_link, 0, priv->phy_mode);
-+ if (!priv->phy) {
-+ ret = -ENODEV;
-+ goto out_phy_node;
-+ }
++ priv->phy = of_phy_connect(ndev, priv->phy_node,
++ &higmac_adjust_link, 0, priv->phy_mode);
++ if (!priv->phy) {
++ ret = -ENODEV;
++ goto out_phy_node;
++ }
+
-+ /* If the phy_id is all zero and not fixed link, there is no device there */
-+ if ((priv->phy->phy_id == 0) && !fixed_link) {
-+ pr_info("phy %d not found\n", priv->phy->mdio.addr);
-+ ret = -ENODEV;
-+ goto out_phy_disconnect;
-+ }
++ /* If the phy_id is all zero and not fixed link, there is no device there */
++ if ((priv->phy->phy_id == 0) && !fixed_link) {
++ pr_info("phy %d not found\n", priv->phy->mdio.addr);
++ ret = -ENODEV;
++ goto out_phy_disconnect;
++ }
+
-+ pr_info("attached PHY %d to driver %s, PHY_ID=0x%x\n",
-+ priv->phy->mdio.addr, priv->phy->drv->name, priv->phy->phy_id);
++ pr_info("attached PHY %d to driver %s, PHY_ID=0x%x\n",
++ priv->phy->mdio.addr, priv->phy->drv->name, priv->phy->phy_id);
+
-+ /* Stop Advertising 1000BASE Capability if interface is not RGMII */
-+ if ((priv->phy_mode == PHY_INTERFACE_MODE_MII) ||
-+ (priv->phy_mode == PHY_INTERFACE_MODE_RMII)) {
-+ priv->phy->advertising &= ~(SUPPORTED_1000baseT_Half |
-+ SUPPORTED_1000baseT_Full);
++ /* Stop Advertising 1000BASE Capability if interface is not RGMII */
++ if ((priv->phy_mode == PHY_INTERFACE_MODE_MII) ||
++ (priv->phy_mode == PHY_INTERFACE_MODE_RMII)) {
++ priv->phy->advertising &= ~(SUPPORTED_1000baseT_Half |
++ SUPPORTED_1000baseT_Full);
+
-+ /* Internal FE phy's reg BMSR bit8 is wrong, make the kernel
-+ * believe it has the 1000base Capability, so fix it here
-+ */
-+ if (priv->phy->phy_id == HISILICON_PHY_ID_FESTAV200)
-+ priv->phy->supported &= ~(ADVERTISED_1000baseT_Full |
-+ ADVERTISED_1000baseT_Half);
-+ }
++ /* Internal FE phy's reg BMSR bit8 is wrong, make the kernel
++ * believe it has the 1000base Capability, so fix it here
++ */
++ if (priv->phy->phy_id == HISILICON_PHY_ID_FESTAV200)
++ priv->phy->supported &= ~(ADVERTISED_1000baseT_Full |
++ ADVERTISED_1000baseT_Half);
++ }
+
-+ higmac_set_flow_ctrl_args(priv);
-+ higmac_set_flow_ctrl_params(priv);
-+ priv->phy->supported |= SUPPORTED_Pause;
-+ if (priv->flow_ctrl) {
-+ priv->phy->advertising |= SUPPORTED_Pause;
-+ }
++ higmac_set_flow_ctrl_args(priv);
++ higmac_set_flow_ctrl_params(priv);
++ priv->phy->supported |= SUPPORTED_Pause;
++ if (priv->flow_ctrl)
++ priv->phy->advertising |= SUPPORTED_Pause;
+
-+ if (priv->autoeee) {
-+ init_autoeee(priv);
-+ }
++ if (priv->autoeee)
++ init_autoeee(priv);
+
-+ ret = higmac_request_irqs(pdev, priv);
-+ if (ret) {
-+ goto out_phy_disconnect;
-+ }
++ ret = higmac_request_irqs(pdev, priv);
++ if (ret)
++ goto out_phy_disconnect;
+
-+ higmac_init_napi(priv);
-+ spin_lock_init(&priv->rxlock);
-+ spin_lock_init(&priv->txlock);
-+ spin_lock_init(&priv->pmtlock);
++ higmac_init_napi(priv);
++ spin_lock_init(&priv->rxlock);
++ spin_lock_init(&priv->txlock);
++ spin_lock_init(&priv->pmtlock);
+
-+ /* init netdevice */
-+ ndev->irq = priv->irq[0];
-+ ndev->watchdog_timeo = 3 * HZ;
-+ ndev->netdev_ops = &hieth_netdev_ops;
-+ ndev->ethtool_ops = &hieth_ethtools_ops;
++ /* init netdevice */
++ ndev->irq = priv->irq[0];
++ ndev->watchdog_timeo = 3 * HZ;
++ ndev->netdev_ops = &hieth_netdev_ops;
++ ndev->ethtool_ops = &hieth_ethtools_ops;
+
-+ if (priv->has_rxhash_cap) {
-+ ndev->hw_features |= NETIF_F_RXHASH;
-+ }
-+ if (priv->has_rss_cap) {
-+ ndev->hw_features |= NETIF_F_NTUPLE;
-+ }
-+ if (priv->tso_supported) {
-+ ndev->hw_features |= NETIF_F_SG |
-+ NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
-+ NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_UFO;
-+ }
++ if (priv->has_rxhash_cap)
++ ndev->hw_features |= NETIF_F_RXHASH;
++ if (priv->has_rss_cap)
++ ndev->hw_features |= NETIF_F_NTUPLE;
++ if (priv->tso_supported) {
++ ndev->hw_features |= NETIF_F_SG |
++ NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
++ NETIF_F_TSO | NETIF_F_TSO6 ;
++ }
+#if defined(CONFIG_HIGMAC_RXCSUM)
-+ ndev->hw_features |= NETIF_F_RXCSUM;
-+ higmac_enable_rxcsum_drop(priv, true);
++ ndev->hw_features |= NETIF_F_RXCSUM;
++ higmac_enable_rxcsum_drop(priv, true);
+#endif
+
-+ ndev->features |= ndev->hw_features;
-+ ndev->features |= NETIF_F_HIGHDMA | NETIF_F_GSO;
-+ ndev->vlan_features |= ndev->features;
++ ndev->features |= ndev->hw_features;
++ ndev->features |= NETIF_F_HIGHDMA | NETIF_F_GSO;
++ ndev->vlan_features |= ndev->features;
+
+ init_timer(&priv->monitor);
+ priv->monitor.function = higmac_monitor_func;
-+ priv->monitor.data = (unsigned long)ndev;
++ priv->monitor.data = (uintptr_t)ndev;
+ priv->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
+
-+ device_set_wakeup_capable(priv->dev, 1);
-+ /* TODO: when we can let phy powerdown?
-+ * In some mode, we don't want phy powerdown,
-+ * so I set wakeup enable all the time
-+ */
-+ device_set_wakeup_enable(priv->dev, 1);
++ device_set_wakeup_capable(priv->dev, 1);
++ /* TODO: when we can let phy powerdown?
++ * In some mode, we don't want phy powerdown,
++ * so I set wakeup enable all the time
++ */
++ device_set_wakeup_enable(priv->dev, 1);
+
-+ priv->wol_enable = false;
++ priv->wol_enable = false;
+
-+ priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
++ priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
+
+#if defined(CONFIG_HIGMAC_DDR_64BIT)
-+ if (!HAS_CAP_CCI(priv->hw_cap)) {
-+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
-+ if (ret) {
-+ pr_err("dma set mask 64 failed! ret=%d", ret);
-+ goto _error_hw_desc_queue;
-+ }
-+ }
++ if (!HAS_CAP_CCI(priv->hw_cap)) {
++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
++ if (ret) {
++ pr_err("dma set mask 64 failed! ret=%d", ret);
++ goto _error_hw_desc_queue;
++ }
++ }
+#endif
+
-+ /* init hw desc queue */
-+ ret = higmac_init_hw_desc_queue(priv);
-+ if (ret) {
-+ goto _error_hw_desc_queue;
-+ }
++ /* init hw desc queue */
++ ret = higmac_init_hw_desc_queue(priv);
++ if (ret)
++ goto _error_hw_desc_queue;
+
-+ if (priv->tso_supported) {
-+ ret = higmac_init_sg_desc_queue(priv);
-+ if (ret) {
-+ goto _error_sg_desc_queue;
-+ }
-+ }
++ if (priv->tso_supported) {
++ ret = higmac_init_sg_desc_queue(priv);
++ if (ret)
++ goto _error_sg_desc_queue;
++ }
+
-+ /* register netdevice */
-+ ret = register_netdev(priv->netdev);
-+ if (ret) {
-+ pr_err("register_ndev failed!");
-+ goto _error_sg_desc_queue;
-+ }
++ /* register netdevice */
++ ret = register_netdev(priv->netdev);
++ if (ret) {
++ pr_err("register_ndev failed!");
++ goto _error_sg_desc_queue;
++ }
+
-+ /* reset queue here to make BQL only reset once.
-+ * if we put netdev_reset_queue() in higmac_net_open(),
-+ * the BQL will be reset when ifconfig eth0 down and up,
-+ * but the tx ring is not cleared before.
-+ * As a result, the NAPI poll will call netdev_completed_queue()
-+ * and BQL throw a bug.
-+ */
-+ netdev_reset_queue(ndev);
++ /* reset queue here to make BQL only reset once.
++ * if we put netdev_reset_queue() in higmac_net_open(),
++ * the BQL will be reset when ifconfig eth0 down and up,
++ * but the tx ring is not cleared before.
++ * As a result, the NAPI poll will call netdev_completed_queue()
++ * and BQL throw a bug.
++ */
++ netdev_reset_queue(ndev);
+
-+ clk_disable_unprepare(priv->clk);
-+ if (priv->macif_clk) {
-+ clk_disable_unprepare(priv->macif_clk);
-+ }
++ clk_disable_unprepare(priv->clk);
++ if (priv->macif_clk)
++ clk_disable_unprepare(priv->macif_clk);
+
-+ pr_info("ETH: %s, phy_addr=%d\n",
-+ phy_modes(priv->phy_mode), priv->phy->mdio.addr);
++ pr_info("ETH: %s, phy_addr=%d\n",
++ phy_modes(priv->phy_mode), priv->phy->mdio.addr);
+
-+ return ret;
++ dev_put(ndev);
++ return ret;
+
+_error_sg_desc_queue:
-+ if (priv->tso_supported) {
-+ higmac_destroy_sg_desc_queue(priv);
-+ }
++ if (priv->tso_supported)
++ higmac_destroy_sg_desc_queue(priv);
+
+_error_hw_desc_queue:
-+ higmac_destroy_hw_desc_queue(priv);
-+ higmac_destroy_napi(priv);
++ higmac_destroy_hw_desc_queue(priv);
++ higmac_destroy_napi(priv);
+out_phy_disconnect:
-+ phy_disconnect(priv->phy);
++ phy_disconnect(priv->phy);
+out_phy_node:
-+ of_node_put(priv->phy_node);
++ of_node_put(priv->phy_node);
+out_macif_clk_disable:
-+ if (priv->macif_clk) {
-+ clk_disable_unprepare(priv->macif_clk);
-+ }
++ if (priv->macif_clk)
++ clk_disable_unprepare(priv->macif_clk);
+out_clk_disable:
-+ clk_disable_unprepare(priv->clk);
++ clk_disable_unprepare(priv->clk);
+out_free_netdev:
-+ free_netdev(ndev);
++ dev_put(ndev);
++ free_netdev(ndev);
+
-+ return ret;
++ return ret;
+}
+
+static int higmac_dev_remove(struct platform_device *pdev)
+{
-+ struct net_device *ndev = platform_get_drvdata(pdev);
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct net_device *ndev = platform_get_drvdata(pdev);
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
+
-+ /* TODO: stop the gmac and free all resource */
-+ del_timer_sync(&priv->monitor);
-+ higmac_destroy_napi(priv);
++ /* TODO: stop the gmac and free all resource */
++ del_timer_sync(&priv->monitor);
++ higmac_destroy_napi(priv);
+
-+ unregister_netdev(ndev);
++ unregister_netdev(ndev);
+
-+ higmac_reclaim_rx_tx_resource(priv);
-+ higmac_free_rx_skb(priv);
-+ higmac_free_tx_skb(priv);
++ higmac_reclaim_rx_tx_resource(priv);
++ higmac_free_rx_skb(priv);
++ higmac_free_tx_skb(priv);
+
-+ if (priv->tso_supported) {
-+ higmac_destroy_sg_desc_queue(priv);
-+ }
-+ higmac_destroy_hw_desc_queue(priv);
++ if (priv->tso_supported)
++ higmac_destroy_sg_desc_queue(priv);
++ higmac_destroy_hw_desc_queue(priv);
+
-+ phy_disconnect(priv->phy);
-+ of_node_put(priv->phy_node);
++ phy_disconnect(priv->phy);
++ of_node_put(priv->phy_node);
+
-+ free_netdev(ndev);
++ free_netdev(ndev);
+
-+ phy_unregister_fixups();
++ phy_unregister_fixups();
+
-+ return 0;
++ return 0;
+}
+
+#include "pm.c"
@@ -316046,210 +384381,184 @@ index 0000000..5d172c3
+
+static void higmac_disable_irq(struct higmac_netdev_local *priv)
+{
-+ int i;
++ int i;
+
-+ for (i = 0; i < priv->num_rxqs; i++) {
-+ disable_irq(priv->irq[i]);
-+ }
++ for (i = 0; i < priv->num_rxqs; i++)
++ disable_irq(priv->irq[i]);
+}
+
+static void higmac_enable_irq(struct higmac_netdev_local *priv)
+{
-+ int i;
++ int i;
+
-+ for (i = 0; i < priv->num_rxqs; i++) {
-+ enable_irq(priv->irq[i]);
-+ }
++ for (i = 0; i < priv->num_rxqs; i++)
++ enable_irq(priv->irq[i]);
+}
+
+int higmac_dev_suspend(struct platform_device *pdev, pm_message_t state)
+{
-+ struct net_device *ndev = platform_get_drvdata(pdev);
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ struct net_device *ndev = platform_get_drvdata(pdev);
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
+
-+ higmac_disable_irq(priv);
-+ /* If support Wake on LAN, we should not disconnect phy
-+ * because it will call phy_suspend to power down phy.
-+ */
-+ if (!priv->wol_enable) {
-+ phy_disconnect(priv->phy);
-+ }
-+ del_timer_sync(&priv->monitor);
-+ /* If suspend when netif is not up, the napi_disable will run into
-+ * dead loop and dpm_drv_timeout will give warning.
-+ */
-+ if (netif_running(ndev)) {
-+ higmac_disable_napi(priv);
-+ }
-+ netif_device_detach(ndev);
++ higmac_disable_irq(priv);
++ /* If support Wake on LAN, we should not disconnect phy
++ * because it will call phy_suspend to power down phy.
++ */
++ if (!priv->wol_enable)
++ phy_disconnect(priv->phy);
++ del_timer_sync(&priv->monitor);
++ /* If suspend when netif is not up, the napi_disable will run into
++ * dead loop and dpm_drv_timeout will give warning.
++ */
++ if (netif_running(ndev))
++ higmac_disable_napi(priv);
++ netif_device_detach(ndev);
+
-+ netif_carrier_off(ndev);
++ netif_carrier_off(ndev);
+
-+ /* If netdev is down, MAC clock is disabled.
-+ * So if we want to reclaim MAC rx and tx resource,
-+ * we must first enable MAC clock and then disable it.
-+ */
-+ if (!(ndev->flags & IFF_UP)) {
-+ clk_prepare_enable(priv->clk);
-+ }
++ /* If netdev is down, MAC clock is disabled.
++ * So if we want to reclaim MAC rx and tx resource,
++ * we must first enable MAC clock and then disable it.
++ */
++ if (!(ndev->flags & IFF_UP))
++ clk_prepare_enable(priv->clk);
+
-+ higmac_reclaim_rx_tx_resource(priv);
++ higmac_reclaim_rx_tx_resource(priv);
+
-+ if (!(ndev->flags & IFF_UP)) {
-+ clk_disable_unprepare(priv->clk);
-+ }
++ if (!(ndev->flags & IFF_UP))
++ clk_disable_unprepare(priv->clk);
+
-+ pmt_enter(priv);
++ pmt_enter(priv);
+
-+ if (!priv->wol_enable) { /* if no WOL, then poweroff */
-+ /* pr_info("power off gmac.\n"); */
-+ /* no need to call genphy_resume() in resume,
-+ * because we reset everything
-+ */
-+ genphy_suspend(priv->phy); /* power down phy */
-+ msleep(20);
-+ higmac_hw_all_clk_disable(priv);
-+ }
++ if (!priv->wol_enable) { /* if no WOL, then poweroff */
++ /* pr_info("power off gmac.\n"); */
++ /* no need to call genphy_resume() in resume,
++ * because we reset everything
++ */
++ genphy_suspend(priv->phy); /* power down phy */
++ msleep(20);
++ higmac_hw_all_clk_disable(priv);
++ }
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(higmac_dev_suspend);
+
+int higmac_dev_resume(struct platform_device *pdev)
+{
-+ struct net_device *ndev = platform_get_drvdata(pdev);
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
-+ int ret = 0;
++ struct net_device *ndev = platform_get_drvdata(pdev);
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ int ret = 0;
+
-+ /* If we support Wake on LAN, we doesn't call clk_disable.
-+ * But when we resume, the uboot may off mac clock and reset phy
-+ * by re-write the mac CRG register.
-+ * So we first call clk_disable, and then clk_enable.
-+ */
-+ if (priv->wol_enable) {
-+ higmac_hw_all_clk_disable(priv);
-+ }
++ /* If we support Wake on LAN, we doesn't call clk_disable.
++ * But when we resume, the uboot may off mac clock and reset phy
++ * by re-write the mac CRG register.
++ * So we first call clk_disable, and then clk_enable.
++ */
++ if (priv->wol_enable)
++ higmac_hw_all_clk_disable(priv);
+
-+ higmac_hw_all_clk_enable(priv);
-+ /* internal FE_PHY: enable clk and reset */
-+ higmac_hw_phy_reset(priv);
++ higmac_hw_all_clk_enable(priv);
++ /* internal FE_PHY: enable clk and reset */
++ higmac_hw_phy_reset(priv);
+
-+ /* If netdev is down, MAC clock is disabled.
-+ * So if we want to restart MAC and re-initialize it,
-+ * we must first enable MAC clock and then disable it.
-+ */
-+ if (!(ndev->flags & IFF_UP)) {
-+ clk_prepare_enable(priv->clk);
-+ }
++ /* If netdev is down, MAC clock is disabled.
++ * So if we want to restart MAC and re-initialize it,
++ * we must first enable MAC clock and then disable it.
++ */
++ if (!(ndev->flags & IFF_UP))
++ clk_prepare_enable(priv->clk);
+
-+ /* power on gmac */
-+ higmac_restart(priv);
++ /* power on gmac */
++ higmac_restart(priv);
+
-+ /* If support WoL, we didn't disconnect phy.
-+ * But when we resume, we reset PHY, so we want to
-+ * call phy_connect to make phy_fixup excuted.
-+ * This is important for internal PHY fix.
-+ */
-+ if (priv->wol_enable) {
-+ phy_disconnect(priv->phy);
-+ }
++ /* If support WoL, we didn't disconnect phy.
++ * But when we resume, we reset PHY, so we want to
++ * call phy_connect to make phy_fixup excuted.
++ * This is important for internal PHY fix.
++ */
++ if (priv->wol_enable)
++ phy_disconnect(priv->phy);
+
-+ ret = phy_connect_direct(ndev, priv->phy, higmac_adjust_link,
-+ priv->phy_mode);
-+ if (ret) {
-+ return ret;
-+ }
++ ret = phy_connect_direct(ndev, priv->phy, higmac_adjust_link,
++ priv->phy_mode);
++ if (ret)
++ return ret;
+
-+ /* If we suspend and resume when net device is down,
-+ * some operations are unnecessary.
-+ */
-+ if (ndev->flags & IFF_UP) {
-+ priv->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
-+ mod_timer(&priv->monitor, priv->monitor.expires);
-+ priv->old_link = 0;
-+ priv->old_speed = SPEED_UNKNOWN;
-+ priv->old_duplex = DUPLEX_UNKNOWN;
-+ }
-+ if (netif_running(ndev)) {
-+ higmac_enable_napi(priv);
-+ }
-+ netif_device_attach(ndev);
-+ if (ndev->flags & IFF_UP) {
-+ phy_start(priv->phy);
-+ }
-+ higmac_enable_irq(priv);
++ /* If we suspend and resume when net device is down,
++ * some operations are unnecessary.
++ */
++ if (ndev->flags & IFF_UP) {
++ priv->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
++ mod_timer(&priv->monitor, priv->monitor.expires);
++ priv->old_link = 0;
++ priv->old_speed = SPEED_UNKNOWN;
++ priv->old_duplex = DUPLEX_UNKNOWN;
++ }
++ if (netif_running(ndev))
++ higmac_enable_napi(priv);
++ netif_device_attach(ndev);
++ if (ndev->flags & IFF_UP)
++ phy_start(priv->phy);
++ higmac_enable_irq(priv);
+
-+ pmt_exit(priv);
++ pmt_exit(priv);
+
-+ if (!(ndev->flags & IFF_UP)) {
-+ clk_disable_unprepare(priv->clk);
-+ }
++ if (!(ndev->flags & IFF_UP))
++ clk_disable_unprepare(priv->clk);
+
-+ return 0;
++ return 0;
+}
+EXPORT_SYMBOL(higmac_dev_resume);
+#else
-+#define higmac_dev_suspend NULL
-+#define higmac_dev_resume NULL
++#define higmac_dev_suspend NULL
++#define higmac_dev_resume NULL
+#endif
+
+static const struct of_device_id higmac_of_match[] = {
-+ {
-+ .compatible = "hisilicon,higmac",
-+ },
-+ {
-+ .compatible = "hisilicon,higmac-v1",
-+ },
-+ {
-+ .compatible = "hisilicon,higmac-v2",
-+ },
-+ {
-+ .compatible = "hisilicon,higmac-v3",
-+ },
-+ {
-+ .compatible = "hisilicon,higmac-v4",
-+ },
-+ {
-+ .compatible = "hisilicon,higmac-v5",
-+ },
-+ {},
++ {.compatible = "hisilicon,higmac",},
++ {.compatible = "hisilicon,higmac-v1",},
++ {.compatible = "hisilicon,higmac-v2",},
++ {.compatible = "hisilicon,higmac-v3",},
++ {.compatible = "hisilicon,higmac-v4",},
++ {.compatible = "hisilicon,higmac-v5",},
++ { },
+};
+
+MODULE_DEVICE_TABLE(of, higmac_of_match);
+
+static struct platform_driver higmac_dev_driver = {
-+ .probe = higmac_dev_probe,
-+ .remove = higmac_dev_remove,
-+ .suspend = higmac_dev_suspend,
-+ .resume = higmac_dev_resume,
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = HIGMAC_DRIVER_NAME,
-+ .of_match_table = higmac_of_match,
-+ },
++ .probe = higmac_dev_probe,
++ .remove = higmac_dev_remove,
++ .suspend = higmac_dev_suspend,
++ .resume = higmac_dev_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = HIGMAC_DRIVER_NAME,
++ .of_match_table = higmac_of_match,
++ },
+};
+
+#include "proc-dev.c"
+
+static int __init higmac_init(void)
+{
-+ int ret = 0;
++ int ret;
+
-+ ret = platform_driver_register(&higmac_dev_driver);
-+ if (ret) {
-+ return ret;
-+ }
++ ret = platform_driver_register(&higmac_dev_driver);
++ if (ret)
++ return ret;
+
-+ higmac_proc_create();
++ higmac_proc_create();
+
-+ return ret;
++ return ret;
+}
+
+static void __exit higmac_exit(void)
+{
-+ platform_driver_unregister(&higmac_dev_driver);
++ platform_driver_unregister(&higmac_dev_driver);
+
-+ higmac_proc_destroy();
++ higmac_proc_destroy();
+}
+
+module_init(higmac_init);
@@ -316260,10 +384569,10 @@ index 0000000..5d172c3
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/ethernet/hisilicon/higmac/higmac.h b/drivers/net/ethernet/hisilicon/higmac/higmac.h
new file mode 100644
-index 0000000..0d2ccb2
+index 0000000..cdd5385
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/higmac.h
-@@ -0,0 +1,628 @@
+@@ -0,0 +1,622 @@
+#ifndef __HIGMAC_H__
+#define __HIGMAC_H__
+
@@ -316275,604 +384584,598 @@ index 0000000..0d2ccb2
+#include <linux/io.h>
+#include <linux/interrupt.h>
+
-+#define STATION_ADDR_LOW 0x0000
-+#define STATION_ADDR_HIGH 0x0004
-+#define MAC_DUPLEX_HALF_CTRL 0x0008
++#define STATION_ADDR_LOW 0x0000
++#define STATION_ADDR_HIGH 0x0004
++#define MAC_DUPLEX_HALF_CTRL 0x0008
+
-+#define PORT_MODE 0x0040
++#define PORT_MODE 0x0040
+
-+#define PORT_EN 0x0044
-+#define BITS_TX_EN BIT(2)
-+#define BITS_RX_EN BIT(1)
++#define PORT_EN 0x0044
++#define BITS_TX_EN BIT(2)
++#define BITS_RX_EN BIT(1)
+
-+#define FC_TX_TIMER 0x001C
++#define FC_TX_TIMER 0x001C
+
-+#define PAUSE_THR 0x0038
++#define PAUSE_THR 0x0038
+
-+#define PAUSE_EN 0x0048
-+#define BIT_RX_FDFC BIT(0)
-+#define BIT_TX_FDFC BIT(1)
++#define PAUSE_EN 0x0048
++#define BIT_RX_FDFC BIT(0)
++#define BIT_TX_FDFC BIT(1)
+
-+#define RX_PAUSE_EN 0x02A4
-+#define BIT_RX_FQ_PAUSE_EN BIT(0)
-+#define BIT_RX_BQ_PAUSE_EN BIT(1)
++#define RX_PAUSE_EN 0x02A4
++#define BIT_RX_FQ_PAUSE_EN BIT(0)
++#define BIT_RX_BQ_PAUSE_EN BIT(1)
+
-+#define CRF_TX_PAUSE 0x0340
++#define CRF_TX_PAUSE 0x0340
+
-+#define BITS_Q_PAUSE_TH_OFFSET 16
-+#define BITS_Q_PAUSE_TH_MASK 0xFFFF
++#define BITS_Q_PAUSE_TH_OFFSET 16
++#define BITS_Q_PAUSE_TH_MASK 0xFFFF
+
-+#define REC_FILT_CONTROL 0x0064
-+#define BIT_CRC_ERR_PASS BIT(5)
-+#define BIT_PAUSE_FRM_PASS BIT(4)
-+#define BIT_VLAN_DROP_EN BIT(3)
-+#define BIT_BC_DROP_EN BIT(2)
-+#define BIT_MC_MATCH_EN BIT(1)
-+#define BIT_UC_MATCH_EN BIT(0)
++#define REC_FILT_CONTROL 0x0064
++#define BIT_CRC_ERR_PASS BIT(5)
++#define BIT_PAUSE_FRM_PASS BIT(4)
++#define BIT_VLAN_DROP_EN BIT(3)
++#define BIT_BC_DROP_EN BIT(2)
++#define BIT_MC_MATCH_EN BIT(1)
++#define BIT_UC_MATCH_EN BIT(0)
+
-+#define PORT_MC_ADDR_LOW 0x0068
-+#define PORT_MC_ADDR_HIGH 0x006C
-+#define MAC_CLEAR 0x0070
-+#define BIT_TX_SOFT_RESET BIT(0)
++#define PORT_MC_ADDR_LOW 0x0068
++#define PORT_MC_ADDR_HIGH 0x006C
++#define MAC_CLEAR 0x0070
++#define BIT_TX_SOFT_RESET BIT(0)
+
-+#define MODE_CHANGE_EN 0x01b4
-+#define BIT_MODE_CHANGE_EN BIT(0)
++#define MODE_CHANGE_EN 0x01b4
++#define BIT_MODE_CHANGE_EN BIT(0)
+
-+#define COL_SLOT_TIME 0x01c0
++#define COL_SLOT_TIME 0x01c0
+
-+#define CRF_MIN_PACKET 0x0210
-+#define BIT_OFFSET_TX_MIN_LEN 8
-+#define BIT_MASK_TX_MIN_LEN GENMASK(13, 8)
++#define CRF_MIN_PACKET 0x0210
++#define BIT_OFFSET_TX_MIN_LEN 8
++#define BIT_MASK_TX_MIN_LEN GENMASK(13, 8)
+
-+#define CONTROL_WORD 0x0214
-+#define CONTROL_WORD_CONFIG 0x640
++#define CONTROL_WORD 0x0214
++#define CONTROL_WORD_CONFIG 0x640
+
-+#define TSO_COE_CTRL 0x02e8
-+#define BIT_COE_IPHDR_DROP BIT(4)
-+#define BIT_COE_PAYLOAD_DROP BIT(5)
-+#define BIT_COE_IPV6_UDP_ZERO_DROP BIT(6)
-+#define COE_ERR_DROP (BIT_COE_IPHDR_DROP | \
-+ BIT_COE_PAYLOAD_DROP | \
-+ BIT_COE_IPV6_UDP_ZERO_DROP)
++#define TSO_COE_CTRL 0x02e8
++#define BIT_COE_IPHDR_DROP BIT(4)
++#define BIT_COE_PAYLOAD_DROP BIT(5)
++#define BIT_COE_IPV6_UDP_ZERO_DROP BIT(6)
++#define COE_ERR_DROP (BIT_COE_IPHDR_DROP | \
++ BIT_COE_PAYLOAD_DROP | \
++ BIT_COE_IPV6_UDP_ZERO_DROP)
+
-+#define RX_FQ_START_ADDR 0x0500
-+#define RX_FQ_DEPTH 0x0504
-+#define REG_BIT_WIDTH 32
-+#define Q_ADDR_HI8_OFFSET 24
-+#define Q_ADDR_HI8_MASK (BIT(Q_ADDR_HI8_OFFSET) - 1)
-+#define TX_DESC_HI8_MASK 0xff
-+#define SG_DESC_HI8_OFFSET 8
-+#define RX_FQ_WR_ADDR 0x0508
-+#define BITS_RX_FQ_WR_ADDR MK_BITS(0, 21)
-+#define RX_FQ_RD_ADDR 0x050c
-+#define BITS_RX_FQ_RD_ADDR MK_BITS(0, 21)
-+#define RX_FQ_VLDDESC_CNT 0x0510
-+#define BITS_RX_FQ_VLDDESC_CNT MK_BITS(0, 16)
-+#define RX_FQ_ALEMPTY_TH 0x0514
-+#define BITS_RX_FQ_ALEMPTY_TH MK_BITS(0, 16)
-+#define RX_FQ_REG_EN 0x0518
-+#define BITS_RX_FQ_START_ADDR_EN BIT(2)
-+#define BITS_RX_FQ_DEPTH_EN BIT(1)
-+#define BITS_RX_FQ_RD_ADDR_EN MK_BITS(0, 1)
-+#define RX_FQ_ALFULL_TH 0x051c
-+#define BITS_RX_FQ_ALFULL_TH MK_BITS(0, 16)
++#define RX_FQ_START_ADDR 0x0500
++#define RX_FQ_DEPTH 0x0504
++#define REG_BIT_WIDTH 32
++#define Q_ADDR_HI8_OFFSET 24
++#define Q_ADDR_HI8_MASK (BIT(Q_ADDR_HI8_OFFSET) - 1)
++#define TX_DESC_HI8_MASK 0xff
++#define SG_DESC_HI8_OFFSET 8
++#define RX_FQ_WR_ADDR 0x0508
++#define BITS_RX_FQ_WR_ADDR MK_BITS(0, 21)
++#define RX_FQ_RD_ADDR 0x050c
++#define BITS_RX_FQ_RD_ADDR MK_BITS(0, 21)
++#define RX_FQ_VLDDESC_CNT 0x0510
++#define BITS_RX_FQ_VLDDESC_CNT MK_BITS(0, 16)
++#define RX_FQ_ALEMPTY_TH 0x0514
++#define BITS_RX_FQ_ALEMPTY_TH MK_BITS(0, 16)
++#define RX_FQ_REG_EN 0x0518
++#define BITS_RX_FQ_START_ADDR_EN BIT(2)
++#define BITS_RX_FQ_DEPTH_EN BIT(1)
++#define BITS_RX_FQ_RD_ADDR_EN MK_BITS(0, 1)
++#define RX_FQ_ALFULL_TH 0x051c
++#define BITS_RX_FQ_ALFULL_TH MK_BITS(0, 16)
+
-+#define RX_BQ_START_ADDR 0x0520
-+#define RX_BQ_DEPTH 0x0524
-+#define RX_BQ_WR_ADDR 0x0528
-+#define RX_BQ_RD_ADDR 0x052c
-+#define RX_BQ_FREE_DESC_CNT 0x0530
-+#define BITS_RX_BQ_FREE_DESC_CNT MK_BITS(0, 16)
-+#define RX_BQ_ALEMPTY_TH 0x0534
-+#define BITS_RX_BQ_ALEMPTY_TH MK_BITS(0, 16)
-+#define RX_BQ_REG_EN 0x0538
-+#define BITS_RX_BQ_START_ADDR_EN BIT(2)
-+#define BITS_RX_BQ_DEPTH_EN BIT(1)
-+#define BITS_RX_BQ_WR_ADDR_EN MK_BITS(0, 1)
-+#define RX_BQ_ALFULL_TH 0x053c
-+#define BITS_RX_BQ_ALFULL_TH MK_BITS(0, 16)
++#define RX_BQ_START_ADDR 0x0520
++#define RX_BQ_DEPTH 0x0524
++#define RX_BQ_WR_ADDR 0x0528
++#define RX_BQ_RD_ADDR 0x052c
++#define RX_BQ_FREE_DESC_CNT 0x0530
++#define BITS_RX_BQ_FREE_DESC_CNT MK_BITS(0, 16)
++#define RX_BQ_ALEMPTY_TH 0x0534
++#define BITS_RX_BQ_ALEMPTY_TH MK_BITS(0, 16)
++#define RX_BQ_REG_EN 0x0538
++#define BITS_RX_BQ_START_ADDR_EN BIT(2)
++#define BITS_RX_BQ_DEPTH_EN BIT(1)
++#define BITS_RX_BQ_WR_ADDR_EN MK_BITS(0, 1)
++#define RX_BQ_ALFULL_TH 0x053c
++#define BITS_RX_BQ_ALFULL_TH MK_BITS(0, 16)
+
-+#define TX_BQ_START_ADDR 0x0580
-+#define TX_BQ_DEPTH 0x0584
-+#define TX_BQ_WR_ADDR 0x0588
-+#define BITS_TX_BQ_WR_ADDR MK_BITS(0, 21)
-+#define TX_BQ_RD_ADDR 0x058c
-+#define BITS_TX_BQ_RD_ADDR MK_BITS(0, 21)
-+#define TX_BQ_VLDDESC_CNT 0x0590
-+#define BITS_TX_BQ_VLDDESC_CNT MK_BITS(0, 16)
-+#define TX_BQ_ALEMPTY_TH 0x0594
-+#define BITS_TX_BQ_ALEMPTY_TH MK_BITS(0, 16)
-+#define TX_BQ_REG_EN 0x0598
-+#define BITS_TX_BQ_START_ADDR_EN BIT(2)
-+#define BITS_TX_BQ_DEPTH_EN BIT(1)
-+#define BITS_TX_BQ_RD_ADDR_EN MK_BITS(0, 1)
-+#define TX_BQ_ALFULL_TH 0x059c
-+#define BITS_TX_BQ_ALFULL_TH MK_BITS(0, 16)
++#define TX_BQ_START_ADDR 0x0580
++#define TX_BQ_DEPTH 0x0584
++#define TX_BQ_WR_ADDR 0x0588
++#define BITS_TX_BQ_WR_ADDR MK_BITS(0, 21)
++#define TX_BQ_RD_ADDR 0x058c
++#define BITS_TX_BQ_RD_ADDR MK_BITS(0, 21)
++#define TX_BQ_VLDDESC_CNT 0x0590
++#define BITS_TX_BQ_VLDDESC_CNT MK_BITS(0, 16)
++#define TX_BQ_ALEMPTY_TH 0x0594
++#define BITS_TX_BQ_ALEMPTY_TH MK_BITS(0, 16)
++#define TX_BQ_REG_EN 0x0598
++#define BITS_TX_BQ_START_ADDR_EN BIT(2)
++#define BITS_TX_BQ_DEPTH_EN BIT(1)
++#define BITS_TX_BQ_RD_ADDR_EN MK_BITS(0, 1)
++#define TX_BQ_ALFULL_TH 0x059c
++#define BITS_TX_BQ_ALFULL_TH MK_BITS(0, 16)
+
-+#define TX_RQ_START_ADDR 0x05a0
-+#define TX_RQ_DEPTH 0x05a4
-+#define TX_RQ_WR_ADDR 0x05a8
-+#define BITS_TX_RQ_WR_ADDR MK_BITS(0, 21)
-+#define TX_RQ_RD_ADDR 0x05ac
-+#define BITS_TX_RQ_RD_ADDR MK_BITS(0, 21)
-+#define TX_RQ_FREE_DESC_CNT 0x05b0
-+#define BITS_TX_RQ_FREE_DESC_CNT MK_BITS(0, 16)
-+#define TX_RQ_ALEMPTY_TH 0x05b4
-+#define BITS_TX_RQ_ALEMPTY_TH MK_BITS(0, 16)
-+#define TX_RQ_REG_EN 0x05b8
-+#define BITS_TX_RQ_START_ADDR_EN BIT(2)
-+#define BITS_TX_RQ_DEPTH_EN BIT(1)
-+#define BITS_TX_RQ_WR_ADDR_EN MK_BITS(0, 1)
-+#define TX_RQ_ALFULL_TH 0x05bc
-+#define BITS_TX_RQ_ALFULL_TH MK_BITS(0, 16)
++#define TX_RQ_START_ADDR 0x05a0
++#define TX_RQ_DEPTH 0x05a4
++#define TX_RQ_WR_ADDR 0x05a8
++#define BITS_TX_RQ_WR_ADDR MK_BITS(0, 21)
++#define TX_RQ_RD_ADDR 0x05ac
++#define BITS_TX_RQ_RD_ADDR MK_BITS(0, 21)
++#define TX_RQ_FREE_DESC_CNT 0x05b0
++#define BITS_TX_RQ_FREE_DESC_CNT MK_BITS(0, 16)
++#define TX_RQ_ALEMPTY_TH 0x05b4
++#define BITS_TX_RQ_ALEMPTY_TH MK_BITS(0, 16)
++#define TX_RQ_REG_EN 0x05b8
++#define BITS_TX_RQ_START_ADDR_EN BIT(2)
++#define BITS_TX_RQ_DEPTH_EN BIT(1)
++#define BITS_TX_RQ_WR_ADDR_EN MK_BITS(0, 1)
++#define TX_RQ_ALFULL_TH 0x05bc
++#define BITS_TX_RQ_ALFULL_TH MK_BITS(0, 16)
+
-+#define RAW_PMU_INT 0x05c0
-+#define ENA_PMU_INT 0x05c4
++#define RAW_PMU_INT 0x05c0
++#define ENA_PMU_INT 0x05c4
+
-+#define DESC_WR_RD_ENA 0x05CC
++#define DESC_WR_RD_ENA 0x05CC
+
-+#define IN_QUEUE_TH 0x05d8
-+#define BITS_OFFSET_TX_RQ_IN_TH 16
++#define IN_QUEUE_TH 0x05d8
++#define BITS_OFFSET_TX_RQ_IN_TH 16
+
-+#define RX_BQ_IN_TIMEOUT_TH 0x05E0
++#define RX_BQ_IN_TIMEOUT_TH 0x05E0
+
-+#define TX_RQ_IN_TIMEOUT_TH 0x05e4
++#define TX_RQ_IN_TIMEOUT_TH 0x05e4
+
-+#define STOP_CMD 0x05e8
-+#define BITS_TX_STOP_EN BIT(1)
-+#define BITS_RX_STOP_EN BIT(0)
-+#define STOP_RX_TX (BITS_TX_STOP_EN | BITS_RX_STOP_EN)
++#define STOP_CMD 0x05e8
++#define BITS_TX_STOP_EN BIT(1)
++#define BITS_RX_STOP_EN BIT(0)
++#define STOP_RX_TX (BITS_TX_STOP_EN | BITS_RX_STOP_EN)
+
-+#define HW_CAP_EN 0x0c00
-+#define BIT_RSS_CAP BIT(0)
-+#define BIT_RXHASH_CAP BIT(1)
-+#define RSS_HASH_KEY 0x0c04
-+#define RSS_HASH_CONFIG 0x0c08
-+#define TCPV4_L3_HASH_EN BIT(0)
-+#define TCPV4_L4_HASH_EN BIT(1)
-+#define TCPV4_VLAN_HASH_EN BIT(2)
-+#define UDPV4_L3_HASH_EN BIT(4)
-+#define UDPV4_L4_HASH_EN BIT(5)
-+#define UDPV4_VLAN_HASH_EN BIT(6)
-+#define IPV4_L3_HASH_EN BIT(8)
-+#define IPV4_VLAN_HASH_EN BIT(9)
-+#define TCPV6_L3_HASH_EN BIT(12)
-+#define TCPV6_L4_HASH_EN BIT(13)
-+#define TCPV6_VLAN_HASH_EN BIT(14)
-+#define UDPV6_L3_HASH_EN BIT(16)
-+#define UDPV6_L4_HASH_EN BIT(17)
-+#define UDPV6_VLAN_HASH_EN BIT(18)
-+#define IPV6_L3_HASH_EN BIT(20)
-+#define IPV6_VLAN_HASH_EN BIT(21)
-+#define DEF_HASH_CFG 0x377377
++#define HW_CAP_EN 0x0c00
++#define BIT_RSS_CAP BIT(0)
++#define BIT_RXHASH_CAP BIT(1)
++#define RSS_HASH_KEY 0x0c04
++#define RSS_HASH_CONFIG 0x0c08
++#define TCPV4_L3_HASH_EN BIT(0)
++#define TCPV4_L4_HASH_EN BIT(1)
++#define TCPV4_VLAN_HASH_EN BIT(2)
++#define UDPV4_L3_HASH_EN BIT(4)
++#define UDPV4_L4_HASH_EN BIT(5)
++#define UDPV4_VLAN_HASH_EN BIT(6)
++#define IPV4_L3_HASH_EN BIT(8)
++#define IPV4_VLAN_HASH_EN BIT(9)
++#define TCPV6_L3_HASH_EN BIT(12)
++#define TCPV6_L4_HASH_EN BIT(13)
++#define TCPV6_VLAN_HASH_EN BIT(14)
++#define UDPV6_L3_HASH_EN BIT(16)
++#define UDPV6_L4_HASH_EN BIT(17)
++#define UDPV6_VLAN_HASH_EN BIT(18)
++#define IPV6_L3_HASH_EN BIT(20)
++#define IPV6_VLAN_HASH_EN BIT(21)
++#define DEF_HASH_CFG 0x377377
+
-+#define RSS_IND_TBL 0x0c0c
-+#define BIT_IND_TBL_READY BIT(13)
-+#define BIT_IND_TLB_WR BIT(12)
-+#define RSS_RAW_PMU_INT 0x0c10
-+#define RSS_QUEUE1_START_ADDR 0x0c20
-+#define RX_BQ_START_ADDR_QUEUE(i) (RSS_QUEUE1_START_ADDR + \
-+ ((i) - 1) * 0x10)
-+#define RSS_QUEUE1_DEPTH 0x0c24
-+#define RX_BQ_WR_ADDR_QUEUE1 0x0c28
-+#define RX_BQ_RD_ADDR_QUEUE1 0x0c2c
-+#define RSS_QUEUE1_ENA_INT 0x0c90
-+#define RSS_ENA_INT_QUEUE(i) (RSS_QUEUE1_ENA_INT + ((i) - 1) * 0x4)
-+#define RX_BQ_DEPTH_QUEUE(i) (RSS_QUEUE1_DEPTH + ((i) - 1) * 0x10)
-+#define RX_BQ_WR_ADDR_QUEUE(i) ((i) ? (RX_BQ_WR_ADDR_QUEUE1 + \
-+ ((i) - 1) * 0x10) \
-+ : RX_BQ_WR_ADDR)
-+#define RX_BQ_RD_ADDR_QUEUE(i) ((i) ? (RX_BQ_RD_ADDR_QUEUE1 + \
-+ ((i) - 1) * 0x10) \
-+ : RX_BQ_RD_ADDR)
++#define RSS_IND_TBL 0x0c0c
++#define BIT_IND_TBL_READY BIT(13)
++#define BIT_IND_TLB_WR BIT(12)
++#define RSS_RAW_PMU_INT 0x0c10
++#define RSS_QUEUE1_START_ADDR 0x0c20
++#define RX_BQ_START_ADDR_QUEUE(i) (RSS_QUEUE1_START_ADDR + \
++ ((i) - 1) * 0x10)
++#define RSS_QUEUE1_DEPTH 0x0c24
++#define RX_BQ_WR_ADDR_QUEUE1 0x0c28
++#define RX_BQ_RD_ADDR_QUEUE1 0x0c2c
++#define RSS_QUEUE1_ENA_INT 0x0c90
++#define RSS_ENA_INT_QUEUE(i) (RSS_QUEUE1_ENA_INT + ((i) - 1) * 0x4)
++#define RX_BQ_DEPTH_QUEUE(i) (RSS_QUEUE1_DEPTH + ((i) - 1) * 0x10)
++#define RX_BQ_WR_ADDR_QUEUE(i) ((i) ? (RX_BQ_WR_ADDR_QUEUE1 + \
++ ((i) - 1) * 0x10) : RX_BQ_WR_ADDR)
++#define RX_BQ_RD_ADDR_QUEUE(i) ((i) ? (RX_BQ_RD_ADDR_QUEUE1 + \
++ ((i) - 1) * 0x10) : RX_BQ_RD_ADDR)
+
-+#define DEF_INT_MASK_QUEUE(i) (0x3 << (2 * ((i) - 1)))
++#define DEF_INT_MASK_QUEUE(i) (0x3 << (2 * ((i) - 1)))
+
+/* AXI burst and outstanding config */
-+#define BURST_OUTSTANDING_REG 0x3014
-+#define BURST4_OUTSTANDING1 0x81ff
-+#define BURST_OUTSTANDING_OFFSET 16
++#define BURST_OUTSTANDING_REG 0x3014
++#define BURST4_OUTSTANDING1 0x81ff
++#define BURST_OUTSTANDING_OFFSET 16
+
-+#define GMAC_SPEED_1000 0x05
-+#define GMAC_SPEED_100 0x01
-+#define GMAC_SPEED_10 0x00
++#define GMAC_SPEED_1000 0x05
++#define GMAC_SPEED_100 0x01
++#define GMAC_SPEED_10 0x00
+
+enum higmac_tx_err {
-+ ERR_NONE = 0,
-+ ERR_DESC_CFG = (1 << 0),
-+ ERR_DATA_LEN = (1 << 1),
-+ ERR_DESC_NFRAG_NUM = (1 << 2),
-+ ERR_DESC_IP_HDR_LEN = (1 << 3),
-+ ERR_DESC_PROT_HDR_LEN = (1 << 4),
-+ ERR_DESC_MTU = (1 << 5),
-+ ERR_LINK_SGPKT_LEN = (1 << 8),
-+ ERR_LINK_TSOPKT_LINEAR = (1 << 9),
-+ ERR_LINK_NFRAG_LEN = (1 << 10),
-+ ERR_LINK_TOTAL_LEN = (1 << 11),
-+ ERR_HDR_TCP_BCMC = (1 << 12),
-+ ERR_HDR_UDP_BC = (1 << 13),
-+ ERR_HDR_VLAN_IP_TYPE = (1 << 14),
-+ ERR_HDR_IP_TYPE = (1 << 15),
-+ ERR_HDR_IP_VERSION = (1 << 16),
-+ ERR_HDR_IP_HDR_LEN = (1 << 17),
-+ ERR_HDR_IP_TOTAL_LEN = (1 << 18),
-+ ERR_HDR_IPV6_TTL_PROT = (1 << 19),
-+ ERR_HDR_IPV4_OFFSET = (1 << 20),
-+ ERR_HDR_IPV4_TTL_PROT = (1 << 21),
-+ ERR_HDR_UDP_LEN = (1 << 22),
-+ ERR_HDR_TCP_LEN = (1 << 23),
-+ ERR_DESC = (ERR_DESC_CFG | ERR_DATA_LEN |
-+ ERR_DESC_NFRAG_NUM | ERR_DESC_IP_HDR_LEN |
-+ ERR_DESC_PROT_HDR_LEN | ERR_DESC_MTU),
-+ ERR_LINK = (ERR_LINK_SGPKT_LEN | ERR_LINK_TSOPKT_LINEAR |
-+ ERR_LINK_NFRAG_LEN | ERR_LINK_TOTAL_LEN),
-+ ERR_HDR = (ERR_HDR_TCP_BCMC | ERR_HDR_UDP_BC |
-+ ERR_HDR_VLAN_IP_TYPE | ERR_HDR_IP_TYPE |
-+ ERR_HDR_IP_VERSION | ERR_HDR_IP_HDR_LEN |
-+ ERR_HDR_IP_TOTAL_LEN | ERR_HDR_IPV6_TTL_PROT |
-+ ERR_HDR_IPV4_OFFSET | ERR_HDR_IPV4_TTL_PROT |
-+ ERR_HDR_UDP_LEN | ERR_HDR_TCP_LEN),
-+ ERR_ALL = (ERR_DESC | ERR_LINK | ERR_HDR),
++ ERR_NONE = 0,
++ ERR_DESC_CFG = (1 << 0),
++ ERR_DATA_LEN = (1 << 1),
++ ERR_DESC_NFRAG_NUM = (1 << 2),
++ ERR_DESC_IP_HDR_LEN = (1 << 3),
++ ERR_DESC_PROT_HDR_LEN = (1 << 4),
++ ERR_DESC_MTU = (1 << 5),
++ ERR_LINK_SGPKT_LEN = (1 << 8),
++ ERR_LINK_TSOPKT_LINEAR = (1 << 9),
++ ERR_LINK_NFRAG_LEN = (1 << 10),
++ ERR_LINK_TOTAL_LEN = (1 << 11),
++ ERR_HDR_TCP_BCMC = (1 << 12),
++ ERR_HDR_UDP_BC = (1 << 13),
++ ERR_HDR_VLAN_IP_TYPE = (1 << 14),
++ ERR_HDR_IP_TYPE = (1 << 15),
++ ERR_HDR_IP_VERSION = (1 << 16),
++ ERR_HDR_IP_HDR_LEN = (1 << 17),
++ ERR_HDR_IP_TOTAL_LEN = (1 << 18),
++ ERR_HDR_IPV6_TTL_PROT = (1 << 19),
++ ERR_HDR_IPV4_OFFSET = (1 << 20),
++ ERR_HDR_IPV4_TTL_PROT = (1 << 21),
++ ERR_HDR_UDP_LEN = (1 << 22),
++ ERR_HDR_TCP_LEN = (1 << 23),
++ ERR_DESC = (ERR_DESC_CFG | ERR_DATA_LEN |
++ ERR_DESC_NFRAG_NUM | ERR_DESC_IP_HDR_LEN |
++ ERR_DESC_PROT_HDR_LEN | ERR_DESC_MTU),
++ ERR_LINK = (ERR_LINK_SGPKT_LEN | ERR_LINK_TSOPKT_LINEAR |
++ ERR_LINK_NFRAG_LEN | ERR_LINK_TOTAL_LEN),
++ ERR_HDR = (ERR_HDR_TCP_BCMC | ERR_HDR_UDP_BC |
++ ERR_HDR_VLAN_IP_TYPE | ERR_HDR_IP_TYPE |
++ ERR_HDR_IP_VERSION | ERR_HDR_IP_HDR_LEN |
++ ERR_HDR_IP_TOTAL_LEN | ERR_HDR_IPV6_TTL_PROT |
++ ERR_HDR_IPV4_OFFSET | ERR_HDR_IPV4_TTL_PROT |
++ ERR_HDR_UDP_LEN | ERR_HDR_TCP_LEN),
++ ERR_ALL = (ERR_DESC | ERR_LINK | ERR_HDR),
+};
+
-+#define HIGMAC_DRIVER_NAME "hi_gmac_v200"
++#define HIGMAC_DRIVER_NAME "hi_gmac_v200"
+
-+#define HIGMAC_MAC_CLK_NAME "higmac_clk"
-+#define HIGMAC_MACIF_CLK_NAME "macif_clk"
++#define HIGMAC_MAC_CLK_NAME "higmac_clk"
++#define HIGMAC_MACIF_CLK_NAME "macif_clk"
+
-+#define HIGMAC_PORT_RST_NAME "port_reset"
-+#define HIGMAC_MACIF_RST_NAME "macif_reset"
-+#define HIGMAC_PHY_RST_NAME "phy_reset"
++#define HIGMAC_PORT_RST_NAME "port_reset"
++#define HIGMAC_MACIF_RST_NAME "macif_reset"
++#define HIGMAC_PHY_RST_NAME "phy_reset"
+
+#define HIGMAC_TSO_DEBUG
+
+#include "tso.h"
+
-+#if defined(CONFIG_ARCH_HI3519) || defined(CONFIG_ARCH_HI3519V101) || \
-+ defined(CONFIG_ARCH_HI3516AV200)
++#if defined(CONFIG_ARCH_HI3519) || defined(CONFIG_ARCH_HI3519V101) || \
++ defined(CONFIG_ARCH_HI3516AV200)
+#ifdef readl
+#undef readl
+#undef readl_relaxed
+#undef writel
+#undef writel_relaxed
-+#define readl hi_readl
-+#define readl_relaxed hi_readl_relaxed
-+#define writel hi_writel
-+#define writel_relaxed hi_writel_relaxed
++#define readl hi_readl
++#define readl_relaxed hi_readl_relaxed
++#define writel hi_writel
++#define writel_relaxed hi_writel_relaxed
+#endif /* readl */
+#endif /* defined(CONFIG_ARCH_HI3519) || defined(CONFIG_HI3519V101) */
+
-+#define HIGMAC_IOSIZE (0x1000)
-+#define HIGMAC_OFFSET (HIGMAC_IOSIZE)
++#define HIGMAC_IOSIZE (0x1000)
++#define HIGMAC_OFFSET (HIGMAC_IOSIZE)
+
-+#define RX_BQ_IN_INT BIT(17)
-+#define TX_RQ_IN_INT BIT(19)
-+#define RX_BQ_IN_TIMEOUT_INT BIT(28)
-+#define TX_RQ_IN_TIMEOUT_INT BIT(29)
++#define RX_BQ_IN_INT BIT(17)
++#define TX_RQ_IN_INT BIT(19)
++#define RX_BQ_IN_TIMEOUT_INT BIT(28)
++#define TX_RQ_IN_TIMEOUT_INT BIT(29)
+
-+#define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \
-+ TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT)
++#define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \
++ TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT)
+
+/* write or read descriptor need memory barrier */
-+#define HIGMAC_SYNC_BARRIER() \
-+ do { \
-+ isb(); \
-+ smp_mb(); \
-+ } while (0)
++#define HIGMAC_SYNC_BARRIER() do { isb(); smp_mb(); } while (0)
+
-+#define HISILICON_PHY_ID_FESTAV200 (0x20669823)
-+#define PHY_ID_KSZ8051MNL (0x00221550)
-+#define PHY_ID_KSZ8081RNB (0x00221560)
-+#define DEFAULT_PHY_MASK (0xfffffff0)
-+#define REALTEK_PHY_ID_8211E (0x001cc915)
-+#define REALTEK_PHY_MASK (0x001fffff)
++#define HISILICON_PHY_ID_FESTAV200 (0x20669823)
++#define PHY_ID_KSZ8051MNL (0x00221550)
++#define PHY_ID_KSZ8081RNB (0x00221560)
++#define DEFAULT_PHY_MASK (0xfffffff0)
++#define REALTEK_PHY_ID_8211E (0x001cc915)
++#define REALTEK_PHY_MASK (0x001fffff)
+
+enum {
-+ GMAC_PORT0,
-+ GMAC_PORT1,
-+ GMAC_MAX_PORT,
++ GMAC_PORT0,
++ GMAC_PORT1,
++ GMAC_MAX_PORT,
+};
+
+enum {
-+ MEM_GMAC_IOBASE,
-+ MEM_MACIF_IOBASE,
-+ MEM_AXI_BUS_CFG_IOBASE,
-+ MEM_FWD_IOBASE,
-+ MEM_CTRL_IOBASE,
++ MEM_GMAC_IOBASE,
++ MEM_MACIF_IOBASE,
++ MEM_AXI_BUS_CFG_IOBASE,
++ MEM_FWD_IOBASE,
++ MEM_CTRL_IOBASE,
+};
+
-+#define HIGMAC_LINKED BIT(0)
-+#define HIGMAC_DUP_FULL BIT(1)
-+#define HIGMAC_SPD_10M BIT(2)
-+#define HIGMAC_SPD_100M BIT(3)
-+#define HIGMAC_SPD_1000M BIT(4)
++#define HIGMAC_LINKED BIT(0)
++#define HIGMAC_DUP_FULL BIT(1)
++#define HIGMAC_SPD_10M BIT(2)
++#define HIGMAC_SPD_100M BIT(3)
++#define HIGMAC_SPD_1000M BIT(4)
+/* Flow Control defines */
-+#define FLOW_OFF 0
-+#define FLOW_RX 1
-+#define FLOW_TX 2
-+#define FLOW_AUTO (FLOW_TX | FLOW_RX)
++#define FLOW_OFF 0
++#define FLOW_RX 1
++#define FLOW_TX 2
++#define FLOW_AUTO (FLOW_TX | FLOW_RX)
+
-+#define FC_ACTIVE_MIN 1
-+#define FC_ACTIVE_DEFAULT 16
-+#define FC_ACTIVE_MAX 127
-+#define FC_DEACTIVE_MIN 1
-+#define FC_DEACTIVE_DEFAULT 32
-+#define FC_DEACTIVE_MAX 127
++#define FC_ACTIVE_MIN 1
++#define FC_ACTIVE_DEFAULT 16
++#define FC_ACTIVE_MAX 127
++#define FC_DEACTIVE_MIN 1
++#define FC_DEACTIVE_DEFAULT 32
++#define FC_DEACTIVE_MAX 127
+
-+#define FC_PAUSE_TIME_DEFAULT 0xFFFF
-+#define FC_PAUSE_INTERVAL_DEFAULT 0xFFFF
-+#define FC_PAUSE_TIME_MAX 0xFFFF
++#define FC_PAUSE_TIME_DEFAULT 0xFFFF
++#define FC_PAUSE_INTERVAL_DEFAULT 0xFFFF
++#define FC_PAUSE_TIME_MAX 0xFFFF
+
-+#define RX_BQ_INT_THRESHOLD 0x40 /* TODO: */
-+#define TX_RQ_INT_THRESHOLD 0x20 /* TODO: */
++#define RX_BQ_INT_THRESHOLD 0x40 /* TODO: */
++#define TX_RQ_INT_THRESHOLD 0x20 /* TODO: */
+
-+#define HIGMAC_MONITOR_TIMER (msecs_to_jiffies(200))
++#define HIGMAC_MONITOR_TIMER (msecs_to_jiffies(200))
+
-+#define HIETH_MAX_FRAME_SIZE (1600 + 128)
-+#define SKB_SIZE (HIETH_MAX_FRAME_SIZE)
++#define HIETH_MAX_FRAME_SIZE (1600 + 128)
++#define SKB_SIZE (HIETH_MAX_FRAME_SIZE)
+
-+#define DESC_VLD_FREE 0
-+#define DESC_VLD_BUSY 1
++#define DESC_VLD_FREE 0
++#define DESC_VLD_BUSY 1
+
-+#define DESC_FL_FIRST 2
-+#define DESC_FL_MID 0
-+#define DESC_FL_LAST 1
-+#define DESC_FL_FULL 3
++#define DESC_FL_FIRST 2
++#define DESC_FL_MID 0
++#define DESC_FL_LAST 1
++#define DESC_FL_FULL 3
+
+#if defined(CONFIG_HIGMAC_DESC_4WORD)
-+#define DESC_WORD_SHIFT 2
++#define DESC_WORD_SHIFT 2
+#else
-+#define DESC_WORD_SHIFT 3
++#define DESC_WORD_SHIFT 3
+#endif
-+#define DESC_BYTE_SHIFT (DESC_WORD_SHIFT + 2)
-+#define DESC_WORD_CNT (1 << DESC_WORD_SHIFT)
-+#define DESC_SIZE (1 << DESC_BYTE_SHIFT)
++#define DESC_BYTE_SHIFT (DESC_WORD_SHIFT + 2)
++#define DESC_WORD_CNT (1 << DESC_WORD_SHIFT)
++#define DESC_SIZE (1 << DESC_BYTE_SHIFT)
+
-+#define RX_DESC_NUM 1024
-+#define TX_DESC_NUM 1024
++#define RX_DESC_NUM 1024
++#define TX_DESC_NUM 1024
+
+/* DMA descriptor ring helpers */
-+#define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
-+#define dma_cnt(n) ((n) >> DESC_BYTE_SHIFT)
-+#define dma_byte(n) ((n) << DESC_BYTE_SHIFT)
++#define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
++#define dma_cnt(n) ((n) >> DESC_BYTE_SHIFT)
++#define dma_byte(n) ((n) << DESC_BYTE_SHIFT)
+
-+#define RSS_HASH_KEY_SIZE 4
-+#define RSS_INDIRECTION_TABLE_SIZE 128
-+#define RSS_NUM_RXQS 4
++#define RSS_HASH_KEY_SIZE 4
++#define RSS_INDIRECTION_TABLE_SIZE 128
++#define RSS_NUM_RXQS 4
+
-+#define HW_CAP_TSO BIT(0)
-+#define HW_CAP_RXCSUM BIT(1)
-+#define HW_CAP_CCI BIT(2)
-+#define HAS_CAP_TSO(hw_cap) ((hw_cap) & HW_CAP_TSO)
-+#define HAS_CAP_RXCSUM(hw_cap) ((hw_cap) & HW_CAP_RXCSUM)
-+#define HAS_CAP_CCI(hw_cap) ((hw_cap) & HW_CAP_CCI)
++#define HW_CAP_TSO BIT(0)
++#define HW_CAP_RXCSUM BIT(1)
++#define HW_CAP_CCI BIT(2)
++#define HAS_CAP_TSO(hw_cap) ((hw_cap) & HW_CAP_TSO)
++#define HAS_CAP_RXCSUM(hw_cap) ((hw_cap) & HW_CAP_RXCSUM)
++#define HAS_CAP_CCI(hw_cap) ((hw_cap) & HW_CAP_CCI)
+
+#if defined(CONFIG_HIGMAC_DESC_4WORD)
+struct higmac_desc {
-+ unsigned int data_buff_addr;
++ unsigned int data_buff_addr;
+
-+ unsigned int buffer_len : 11;
++ unsigned int buffer_len:11;
+#if defined(CONFIG_HIGMAC_RXCSUM)
-+ unsigned int reserve2 : 1;
-+ unsigned int payload_csum_err : 1;
-+ unsigned int header_csum_err : 1;
-+ unsigned int payload_csum_done : 1;
-+ unsigned int header_csum_done : 1;
++ unsigned int reserve2:1;
++ unsigned int payload_csum_err:1;
++ unsigned int header_csum_err:1;
++ unsigned int payload_csum_done:1;
++ unsigned int header_csum_done:1;
+#else
-+ unsigned int reserve2 : 5;
++ unsigned int reserve2:5;
+#endif
-+ unsigned int data_len : 11;
-+ unsigned int reserve1 : 2;
-+ unsigned int fl : 2;
-+ unsigned int descvid : 1;
++ unsigned int data_len:11;
++ unsigned int reserve1:2;
++ unsigned int fl:2;
++ unsigned int descvid:1;
+
-+ unsigned int rxhash;
-+ unsigned int reserve3 : 8;
-+ unsigned int l3_hash : 1;
-+ unsigned int has_hash : 1;
-+ unsigned int skb_id : 14;
-+ unsigned int reserve31 : 8;
++ unsigned int rxhash;
++ unsigned int reserve3:8;
++ unsigned int l3_hash:1;
++ unsigned int has_hash:1;
++ unsigned int skb_id:14;
++ unsigned int reserve31:8;
+};
+
+struct higmac_tso_desc {
-+ unsigned int data_buff_addr;
-+ union {
-+ struct {
-+ unsigned int prot_hdr_len : 4;
-+ unsigned int ip_hdr_len : 4;
-+ unsigned int prot_type : 1;
-+ unsigned int ip_ver : 1;
-+ unsigned int vlan_flag : 1;
-+ unsigned int nfrags_num : 5;
-+ unsigned int data_len : 11;
-+ unsigned int reservel : 1;
-+ unsigned int tso_flag : 1;
-+ unsigned int coe_flag : 1;
-+ unsigned int sg_flag : 1;
-+ unsigned int hw_own : 1;
-+ } tx;
-+ unsigned int val;
-+ } desc1;
-+ unsigned int reserve_desc2;
-+ unsigned int tx_err;
++ unsigned int data_buff_addr;
++ union {
++ struct {
++ unsigned int prot_hdr_len:4;
++ unsigned int ip_hdr_len:4;
++ unsigned int prot_type:1;
++ unsigned int ip_ver:1;
++ unsigned int vlan_flag:1;
++ unsigned int nfrags_num:5;
++ unsigned int data_len:11;
++ unsigned int reservel:1;
++ unsigned int tso_flag:1;
++ unsigned int coe_flag:1;
++ unsigned int sg_flag:1;
++ unsigned int hw_own:1;
++ } tx;
++ unsigned int val;
++ } desc1;
++ unsigned int reserve_desc2;
++ unsigned int tx_err;
+};
+#else
+struct higmac_desc {
-+ unsigned int data_buff_addr;
++ unsigned int data_buff_addr;
+
-+ unsigned int buffer_len : 11;
++ unsigned int buffer_len:11;
+#if defined(CONFIG_HIGMAC_RXCSUM)
-+ unsigned int reserve2 : 1;
-+ unsigned int payload_csum_err : 1;
-+ unsigned int header_csum_err : 1;
-+ unsigned int payload_csum_done : 1;
++ unsigned int reserve2:1;
++ unsigned int payload_csum_err:1;
++ unsigned int header_csum_err:1;
++ unsigned int payload_csum_done:1;
+#else
-+ unsigned int reserve2 : 5;
++ unsigned int reserve2:5;
+#endif
-+ unsigned int data_len : 11;
-+ unsigned int reserve1 : 2;
-+ unsigned int fl : 2;
-+ unsigned int descvid : 1;
++ unsigned int data_len:11;
++ unsigned int reserve1:2;
++ unsigned int fl:2;
++ unsigned int descvid:1;
+
-+ unsigned int rxhash;
-+ unsigned int reserve3 : 8;
-+ unsigned int l3_hash : 1;
-+ unsigned int has_hash : 1;
-+ unsigned int skb_id : 14;
-+ unsigned int reserve31 : 8;
++ unsigned int rxhash;
++ unsigned int reserve3:8;
++ unsigned int l3_hash:1;
++ unsigned int has_hash:1;
++ unsigned int skb_id:14;
++ unsigned int reserve31:8;
+
-+ unsigned int reserve4;
-+ unsigned int reserve5;
-+ unsigned int reserve6;
-+ unsigned int reserve7;
++ unsigned int reserve4;
++ unsigned int reserve5;
++ unsigned int reserve6;
++ unsigned int reserve7;
+};
+
+struct higmac_tso_desc {
-+ unsigned int data_buff_addr;
-+ union {
-+ struct {
-+ unsigned int prot_hdr_len : 4;
-+ unsigned int ip_hdr_len : 4;
-+ unsigned int prot_type : 1;
-+ unsigned int ip_ver : 1;
-+ unsigned int vlan_flag : 1;
-+ unsigned int nfrags_num : 5;
-+ unsigned int data_len : 11;
-+ unsigned int reservel : 1;
-+ unsigned int tso_flag : 1;
-+ unsigned int coe_flag : 1;
-+ unsigned int sg_flag : 1;
-+ unsigned int hw_own : 1;
-+ } tx;
-+ unsigned int val;
-+ } desc1;
-+ unsigned int reserve_desc2;
-+ unsigned int reserve3;
++ unsigned int data_buff_addr;
++ union {
++ struct {
++ unsigned int prot_hdr_len:4;
++ unsigned int ip_hdr_len:4;
++ unsigned int prot_type:1;
++ unsigned int ip_ver:1;
++ unsigned int vlan_flag:1;
++ unsigned int nfrags_num:5;
++ unsigned int data_len:11;
++ unsigned int reservel:1;
++ unsigned int tso_flag:1;
++ unsigned int coe_flag:1;
++ unsigned int sg_flag:1;
++ unsigned int hw_own:1;
++ } tx;
++ unsigned int val;
++ } desc1;
++ unsigned int reserve_desc2;
++ unsigned int reserve3;
+
-+ unsigned int tx_err;
-+ unsigned int reserve5;
-+ unsigned int reserve6;
-+ unsigned int reserve7;
++ unsigned int tx_err;
++ unsigned int reserve5;
++ unsigned int reserve6;
++ unsigned int reserve7;
+};
+#endif
+
-+#define SKB_MAGIC ((struct sk_buff *)0x5a)
++#define SKB_MAGIC ((struct sk_buff *)0x5a)
+
+struct higmac_napi {
-+ struct napi_struct napi;
-+ struct higmac_netdev_local *ndev_priv;
-+ int rxq_id;
++ struct napi_struct napi;
++ struct higmac_netdev_local *ndev_priv;
++ int rxq_id;
+};
+
+struct higmac_rss_info {
-+ u32 hash_cfg;
-+ u32 ind_tbl_size;
-+ u8 ind_tbl[RSS_INDIRECTION_TABLE_SIZE];
-+ u8 key[RSS_HASH_KEY_SIZE];
++ u32 hash_cfg;
++ u32 ind_tbl_size;
++ u8 ind_tbl[RSS_INDIRECTION_TABLE_SIZE];
++ u8 key[RSS_HASH_KEY_SIZE];
+};
+
-+#define QUEUE_NUMS (4)
++#define QUEUE_NUMS (4)
+struct higmac_netdev_local {
-+#define HIGMAC_SG_DESC_ADD (64U)
-+ struct sg_desc *dma_sg_desc ____cacheline_aligned;
-+ dma_addr_t dma_sg_phy;
-+ unsigned int sg_head;
-+ unsigned int sg_tail;
-+ unsigned int sg_count;
++#define HIGMAC_SG_DESC_ADD (64U)
++ struct sg_desc *dma_sg_desc ____cacheline_aligned;
++ dma_addr_t dma_sg_phy;
++ unsigned int sg_head;
++ unsigned int sg_tail;
++ unsigned int sg_count;
+
-+ void __iomem *gmac_iobase;
-+ void __iomem *macif_base;
-+ void __iomem *axi_bus_cfg_base;
-+ int index; /* 0 -- mac0, 1 -- mac1 */
++ void __iomem *gmac_iobase;
++ void __iomem *macif_base;
++ void __iomem *axi_bus_cfg_base;
++ int index; /* 0 -- mac0, 1 -- mac1 */
+
-+ u32 hw_cap;
-+ bool tso_supported;
-+ bool has_rxhash_cap;
-+ bool has_rss_cap;
-+ int num_rxqs;
-+ struct higmac_napi q_napi[RSS_NUM_RXQS];
-+ int irq[RSS_NUM_RXQS];
-+ struct higmac_rss_info rss_info;
++ u32 hw_cap;
++ bool tso_supported;
++ bool has_rxhash_cap;
++ bool has_rss_cap;
++ int num_rxqs;
++ struct higmac_napi q_napi[RSS_NUM_RXQS];
++ int irq[RSS_NUM_RXQS];
++ struct higmac_rss_info rss_info;
+
-+ struct reset_control *port_rst;
-+ struct reset_control *macif_rst;
-+ struct reset_control *phy_rst;
++ struct reset_control *port_rst;
++ struct reset_control *macif_rst;
++ struct reset_control *phy_rst;
+
-+ struct {
-+ struct higmac_desc *desc;
-+ dma_addr_t phys_addr;
-+ int *sg_desc_offset;
++ struct {
++ struct higmac_desc *desc;
++ dma_addr_t phys_addr;
++ int *sg_desc_offset;
+
-+ /* how many desc in the desc pool */
-+ unsigned int count;
-+ struct sk_buff **skb;
++ /* how many desc in the desc pool */
++ unsigned int count;
++ struct sk_buff **skb;
+
-+ /* sizeof(desc) * count */
-+ unsigned int size;
-+ } pool[QUEUE_NUMS + RSS_NUM_RXQS - 1];
-+#define rx_fq pool[0]
-+#define rx_bq pool[1]
-+#define tx_bq pool[2]
-+#define tx_rq pool[3]
++ /* sizeof(desc) * count */
++ unsigned int size;
++ } pool[QUEUE_NUMS + RSS_NUM_RXQS - 1];
++#define rx_fq pool[0]
++#define rx_bq pool[1]
++#define tx_bq pool[2]
++#define tx_rq pool[3]
+
-+ struct sk_buff **tx_skb;
-+ struct sk_buff **rx_skb;
++ struct sk_buff **tx_skb;
++ struct sk_buff **rx_skb;
+
-+ struct device *dev;
-+ struct net_device *netdev;
-+ struct clk *clk;
-+ struct clk *macif_clk;
++ struct device *dev;
++ struct net_device *netdev;
++ struct clk *clk;
++ struct clk *macif_clk;
+
-+ struct higmac_adapter *adapter;
++ struct higmac_adapter *adapter;
+
-+ struct timer_list monitor;
++ struct timer_list monitor;
+
-+ char phy_name[MII_BUS_ID_SIZE];
-+ struct phy_device *phy;
-+ struct device_node *phy_node;
-+ phy_interface_t phy_mode;
-+ bool autoeee;
-+ bool internal_phy;
-+ int (*eee_init)(struct phy_device *phy_dev);
++ char phy_name[MII_BUS_ID_SIZE];
++ struct phy_device *phy;
++ struct device_node *phy_node;
++ phy_interface_t phy_mode;
++ bool autoeee;
++ bool internal_phy;
++ int (*eee_init)(struct phy_device *phy_dev);
+
-+ unsigned int flow_ctrl;
-+ unsigned int pause;
-+ unsigned int pause_interval;
-+ unsigned int flow_ctrl_active_threshold;
-+ unsigned int flow_ctrl_deactive_threshold;
++ unsigned int flow_ctrl;
++ unsigned int pause;
++ unsigned int pause_interval;
++ unsigned int flow_ctrl_active_threshold;
++ unsigned int flow_ctrl_deactive_threshold;
+
-+ int old_link;
-+ int old_speed;
-+ int old_duplex;
++ int old_link;
++ int old_speed;
++ int old_duplex;
+
-+ /* receive packet lock */
-+ spinlock_t rxlock;
-+ /* transmit packet lock */
-+ spinlock_t txlock;
-+ /* power management lock */
-+ spinlock_t pmtlock;
++ /* receive packet lock */
++ spinlock_t rxlock;
++ /* transmit packet lock */
++ spinlock_t txlock;
++ /* power management lock */
++ spinlock_t pmtlock;
+
-+ int dev_state; /* INIT/OPEN/CLOSE */
-+ char pm_state;
-+ bool wol_enable;
-+ u32 msg_enable;
-+#define INIT (0) /* power off gmac */
-+#define OPEN (1) /* power on gmac */
-+#define CLOSE (2) /* power off gmac */
++ int dev_state; /* INIT/OPEN/CLOSE */
++ char pm_state;
++ bool wol_enable;
++ u32 msg_enable;
++#define INIT (0) /* power off gmac */
++#define OPEN (1) /* power on gmac */
++#define CLOSE (2) /* power off gmac */
+};
+
+enum tso_version {
-+ VER_NO_TSO = 0x0,
-+ VER_BYTE_SPLICE = 0x1,
-+ VER_SG_COE = 0x2,
-+ VER_TSO = 0x3,
++ VER_NO_TSO = 0x0,
++ VER_BYTE_SPLICE = 0x1,
++ VER_SG_COE = 0x2,
++ VER_TSO = 0x3,
+};
+
+#ifdef HIGMAC_TSO_DEBUG
-+#define MAX_RECORD (100)
++#define MAX_RECORD (100)
+struct send_pkt_info {
-+ struct higmac_tso_desc desc;
-+ int status;
++ struct higmac_tso_desc desc;
++ int status;
+};
+#endif
+
@@ -316894,311 +385197,303 @@ index 0000000..0d2ccb2
+#endif
diff --git a/drivers/net/ethernet/hisilicon/higmac/pm.c b/drivers/net/ethernet/hisilicon/higmac/pm.c
new file mode 100644
-index 0000000..1b0ceac
+index 0000000..213cec4
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/pm.c
-@@ -0,0 +1,370 @@
+@@ -0,0 +1,359 @@
+#include <linux/crc16.h>
+#include "higmac.h"
+
-+#define N (31)
-+#define FILTERS (4)
++#define N (31)
++#define FILTERS (4)
+struct pm_config {
-+ unsigned char index; /* bit0--eth0 bit1--eth1 */
-+ unsigned char uc_pkts_enable;
-+ unsigned char magic_pkts_enable;
-+ unsigned char wakeup_pkts_enable;
-+ struct {
-+unsigned int mask_bytes : N;
-+ unsigned int reserved : 1; /* userspace ignore this bit */
-+ unsigned char offset; /* >= 12 */
-+ unsigned char value[N]; /* byte string */
-+ unsigned char valid; /* valid filter */
-+ } filter[FILTERS];
++ unsigned char index; /* bit0--eth0 bit1--eth1 */
++ unsigned char uc_pkts_enable;
++ unsigned char magic_pkts_enable;
++ unsigned char wakeup_pkts_enable;
++ struct {
++ unsigned int mask_bytes:N;
++ unsigned int reserved:1; /* userspace ignore this bit */
++ unsigned char offset; /* >= 12 */
++ unsigned char value[N]; /* byte string */
++ unsigned char valid; /* valid filter */
++ } filter[FILTERS];
+};
+
+struct pm_reg_config {
-+ unsigned int pmt_ctrl;
-+ unsigned int pmt_mask0;
-+ unsigned int pmt_mask1;
-+ unsigned int pmt_mask2;
-+ unsigned int pmt_mask3;
-+ unsigned int pmt_cmd;
-+ unsigned int pmt_offset;
-+ unsigned int pmt_crc1_0;
-+ unsigned int pmt_crc3_2;
++ unsigned int pmt_ctrl;
++ unsigned int pmt_mask0;
++ unsigned int pmt_mask1;
++ unsigned int pmt_mask2;
++ unsigned int pmt_mask3;
++ unsigned int pmt_cmd;
++ unsigned int pmt_offset;
++ unsigned int pmt_crc1_0;
++ unsigned int pmt_crc3_2;
+};
+
+struct pm_reg_config pm_reg_config_backup;
+
-+#define PMT_CTRL 0xa00
-+#define PMT_MASK0 0xa04
-+#define PMT_MASK1 0xa08
-+#define PMT_MASK2 0xa0c
-+#define PMT_MASK3 0xa10
-+#define PMT_CMD 0xa14
-+#define PMT_OFFSET 0xa18
-+#define PMT_CRC1_0 0xa1c
-+#define PMT_CRC3_2 0xa20
-+#define MASK_INVALID_BIT BIT(31)
++#define PMT_CTRL 0xa00
++#define PMT_MASK0 0xa04
++#define PMT_MASK1 0xa08
++#define PMT_MASK2 0xa0c
++#define PMT_MASK3 0xa10
++#define PMT_CMD 0xa14
++#define PMT_OFFSET 0xa18
++#define PMT_CRC1_0 0xa1c
++#define PMT_CRC3_2 0xa20
++#define MASK_INVALID_BIT BIT(31)
+
+static void init_crc_table(void);
-+static unsigned short compute_crc(char *message, int nbytes);
-+static unsigned short calculate_crc16(char *buf, unsigned int mask)
++static unsigned short compute_crc(const char *message, int nbytes);
++static unsigned short calculate_crc16(const char *buf, unsigned int mask)
+{
-+ char data[N];
-+ int i, len = 0;
++ char data[N];
++ int i, len = 0;
+
-+ memset(data, 0, sizeof(data));
++ memset(data, 0, sizeof(data));
+
-+ for (i = 0; i < N; i++) {
-+ if (mask & 0x1) {
-+ data[len++] = buf[i];
-+ }
++ for (i = 0; i < N; i++) {
++ if (mask & 0x1)
++ data[len++] = buf[i];
+
-+ mask >>= 1;
-+ }
++ mask >>= 1;
++ }
+
-+ return compute_crc(data, len);
++ return compute_crc(data, len);
+}
+
+/* use this func in config pm func */
+void _pmt_reg_backup(struct higmac_netdev_local *ld)
+{
-+ pm_reg_config_backup.pmt_ctrl = readl(ld->gmac_iobase + PMT_CTRL);
-+ pm_reg_config_backup.pmt_mask0 = readl(ld->gmac_iobase + PMT_MASK0);
-+ pm_reg_config_backup.pmt_mask1 = readl(ld->gmac_iobase + PMT_MASK1);
-+ pm_reg_config_backup.pmt_mask2 = readl(ld->gmac_iobase + PMT_MASK2);
-+ pm_reg_config_backup.pmt_mask3 = readl(ld->gmac_iobase + PMT_MASK3);
-+ pm_reg_config_backup.pmt_cmd = readl(ld->gmac_iobase + PMT_CMD);
-+ pm_reg_config_backup.pmt_offset = readl(ld->gmac_iobase + PMT_OFFSET);
-+ pm_reg_config_backup.pmt_crc1_0 = readl(ld->gmac_iobase + PMT_CRC1_0);
-+ pm_reg_config_backup.pmt_crc3_2 = readl(ld->gmac_iobase + PMT_CRC3_2);
++ pm_reg_config_backup.pmt_ctrl = readl(ld->gmac_iobase + PMT_CTRL);
++ pm_reg_config_backup.pmt_mask0 = readl(ld->gmac_iobase + PMT_MASK0);
++ pm_reg_config_backup.pmt_mask1 = readl(ld->gmac_iobase + PMT_MASK1);
++ pm_reg_config_backup.pmt_mask2 = readl(ld->gmac_iobase + PMT_MASK2);
++ pm_reg_config_backup.pmt_mask3 = readl(ld->gmac_iobase + PMT_MASK3);
++ pm_reg_config_backup.pmt_cmd = readl(ld->gmac_iobase + PMT_CMD);
++ pm_reg_config_backup.pmt_offset = readl(ld->gmac_iobase + PMT_OFFSET);
++ pm_reg_config_backup.pmt_crc1_0 = readl(ld->gmac_iobase + PMT_CRC1_0);
++ pm_reg_config_backup.pmt_crc3_2 = readl(ld->gmac_iobase + PMT_CRC3_2);
+}
+
-+#define PM_SET (1)
-+#define PM_CLEAR (0)
++#define PM_SET (1)
++#define PM_CLEAR (0)
+
+int pmt_config_gmac(struct pm_config *config, struct higmac_netdev_local *ld)
+{
-+ unsigned int v = 0, cmd = 0, offset = 0;
-+ unsigned short crc[FILTERS] = { 0 };
-+ unsigned long flags;
-+ int reg_mask = 0;
-+ int i;
++ unsigned int v = 0, cmd = 0, offset = 0;
++ unsigned short crc[FILTERS] = { 0 };
++ unsigned long flags;
++ int reg_mask = 0;
++ unsigned int i;
+
-+ if (!ld) {
-+ return -EINVAL;
-+ }
++ if (!ld)
++ return -EINVAL;
+
-+ spin_lock_irqsave(&ld->pmtlock, flags);
-+ if (config->wakeup_pkts_enable) {
-+ /* disable wakeup_pkts_enable before reconfig? */
-+ v = readl(ld->gmac_iobase + PMT_CTRL);
-+ v &= ~BIT(2);
-+ writel(v, ld->gmac_iobase + PMT_CTRL); /* any side effect? */
-+ } else {
-+ goto config_ctrl;
-+ }
++ spin_lock_irqsave(&ld->pmtlock, flags);
++ if (config->wakeup_pkts_enable) {
++ /* disable wakeup_pkts_enable before reconfig? */
++ v = readl(ld->gmac_iobase + PMT_CTRL);
++ v &= ~BIT(2);
++ writel(v, ld->gmac_iobase + PMT_CTRL); /* any side effect? */
++ } else {
++ goto config_ctrl;
++ }
+
-+ /* filter.valid mask.valid mask_bytes effect
-+ * 0 * * no use the filter
-+ * 1 0 * all pkts can wake-up(non-exist)
-+ * 1 1 0 all pkts can wake-up
-+ * 1 1 !0 normal filter
-+ */
-+ /* setup filter */
-+ for (i = 0; i < FILTERS; i++) {
-+ if (config->filter[i].valid) {
-+ if (config->filter[i].offset < 12) {
-+ continue;
-+ }
-+ /* offset and valid bit */
-+ offset |= config->filter[i].offset << (i * 8);
-+ cmd |= BIT(i * 8); /* valid bit */
-+ /* mask */
-+ reg_mask = PMT_MASK0 + (i * 4);
++/* filter.valid mask.valid mask_bytes effect
++ * 0 * * no use the filter
++ * 1 0 * all pkts can wake-up(non-exist)
++ * 1 1 0 all pkts can wake-up
++ * 1 1 !0 normal filter
++ */
++ /* setup filter */
++ for (i = 0; i < FILTERS; i++) {
++ if (config->filter[i].valid) {
++ if (config->filter[i].offset < 12)
++ continue;
++ /* offset and valid bit */
++ offset |= config->filter[i].offset << (i * 8);
++ cmd |= BIT(i * 8); /* valid bit */
++ /* mask */
++ reg_mask = PMT_MASK0 + (i * 4);
+
-+ /* for logic, mask valid bit(bit31) must set to 0,
-+ * 0 is enable
-+ */
-+ v = config->filter[i].mask_bytes;
-+ v &= ~BIT(31);
-+ writel(v, ld->gmac_iobase + reg_mask);
++ /* for logic, mask valid bit(bit31) must set to 0,
++ * 0 is enable
++ */
++ v = config->filter[i].mask_bytes;
++ v &= ~BIT(31);
++ writel(v, ld->gmac_iobase + reg_mask);
+
-+ /* crc */
-+ crc[i] = calculate_crc16(config->filter[i].value, v);
-+ if (i <= 1) { /* for filter0 and filter 1 */
-+ v = readl(ld->gmac_iobase + PMT_CRC1_0);
-+ v &= ~(0xFFFF << (16 * i));
-+ v |= crc[i] << (16 * i);
-+ writel(v, ld->gmac_iobase + PMT_CRC1_0);
-+ } else { /* filter2 and filter3 */
-+ v = readl(ld->gmac_iobase + PMT_CRC3_2);
-+ v &= ~(0xFFFF << (16 * (i - 2)));
-+ v |= crc[i] << (16 * (i - 2));
-+ writel(v, ld->gmac_iobase + PMT_CRC3_2);
-+ }
-+ }
-+ }
++ /* crc */
++ crc[i] = calculate_crc16(config->filter[i].value, v);
++ if (i <= 1) { /* for filter0 and filter 1 */
++ v = readl(ld->gmac_iobase + PMT_CRC1_0);
++ v &= ~(0xFFFF << (16 * i));
++ v |= crc[i] << (16 * i);
++ writel(v, ld->gmac_iobase + PMT_CRC1_0);
++ } else { /* filter2 and filter3 */
++ v = readl(ld->gmac_iobase + PMT_CRC3_2);
++ v &= ~(0xFFFF << (16 * (i - 2)));
++ v |= crc[i] << (16 * (i - 2));
++ writel(v, ld->gmac_iobase + PMT_CRC3_2);
++ }
++ }
++ }
+
-+ if (cmd) {
-+ writel(offset, ld->gmac_iobase + PMT_OFFSET);
-+ writel(cmd, ld->gmac_iobase + PMT_CMD);
-+ }
++ if (cmd) {
++ writel(offset, ld->gmac_iobase + PMT_OFFSET);
++ writel(cmd, ld->gmac_iobase + PMT_CMD);
++ }
+
+config_ctrl:
-+ v = 0;
-+ if (config->uc_pkts_enable) {
-+ v |= BIT(9); /* uc pkts wakeup */
-+ }
-+ if (config->wakeup_pkts_enable) {
-+ v |= BIT(2); /* use filter framework */
-+ }
-+ if (config->magic_pkts_enable) {
-+ v |= BIT(1); /* magic pkts wakeup */
-+ }
++ v = 0;
++ if (config->uc_pkts_enable)
++ v |= BIT(9); /* uc pkts wakeup */
++ if (config->wakeup_pkts_enable)
++ v |= BIT(2); /* use filter framework */
++ if (config->magic_pkts_enable)
++ v |= BIT(1); /* magic pkts wakeup */
+
-+ v |= 3 << 5; /* clear irq status */
-+ writel(v, ld->gmac_iobase + PMT_CTRL);
++ v |= 3 << 5; /* clear irq status */
++ writel(v, ld->gmac_iobase + PMT_CTRL);
+
-+ _pmt_reg_backup(ld);
++ _pmt_reg_backup(ld);
+
-+ spin_unlock_irqrestore(&ld->pmtlock, flags);
++ spin_unlock_irqrestore(&ld->pmtlock, flags);
+
-+ return 0;
++ return 0;
+}
+
+/* pmt_config will overwrite pre-config */
+int pmt_config(struct net_device *ndev, struct pm_config *config)
+{
-+ static int init;
-+ int ret = -EINVAL;
-+ struct higmac_netdev_local *priv = netdev_priv(ndev);
++ static int init;
++ int ret = -EINVAL;
++ struct higmac_netdev_local *priv = netdev_priv(ndev);
+
-+ if (!init) {
-+ init_crc_table();
-+ }
++ if (!init)
++ init_crc_table();
+
-+ ret = pmt_config_gmac(config, priv);
-+ if (ret) {
-+ return ret;
-+ }
++ ret = pmt_config_gmac(config, priv);
++ if (ret)
++ return ret;
+
-+ priv->pm_state = PM_SET;
-+ priv->wol_enable = true;
-+ device_set_wakeup_enable(priv->dev, 1);
++ priv->pm_state = PM_SET;
++ priv->wol_enable = true;
++ device_set_wakeup_enable(priv->dev, 1);
+
-+ return ret;
++ return 0;
+}
+
+inline bool pmt_enter(struct higmac_netdev_local *ld)
+{
-+ int pm = false;
-+ unsigned long flags;
++ int pm = false;
++ unsigned long flags;
+
-+ spin_lock_irqsave(&ld->pmtlock, flags);
-+ if (ld->pm_state == PM_SET) {
-+ int v;
++ spin_lock_irqsave(&ld->pmtlock, flags);
++ if (ld->pm_state == PM_SET) {
++ unsigned int v;
+
-+ v = readl(ld->gmac_iobase + PMT_CTRL);
-+ v |= BIT(0); /* enter power down */
-+ v |= BIT(3); /* enable wakeup irq */
-+ v |= 3 << 5; /* clear irq status */
-+ writel(v, ld->gmac_iobase + PMT_CTRL);
++ v = readl(ld->gmac_iobase + PMT_CTRL);
++ v |= BIT(0); /* enter power down */
++ v |= BIT(3); /* enable wakeup irq */
++ v |= 3 << 5; /* clear irq status */
++ writel(v, ld->gmac_iobase + PMT_CTRL);
+
-+ ld->pm_state = PM_CLEAR;
-+ pm = true;
-+ }
-+ spin_unlock_irqrestore(&ld->pmtlock, flags);
-+ return pm;
++ ld->pm_state = PM_CLEAR;
++ pm = true;
++ }
++ spin_unlock_irqrestore(&ld->pmtlock, flags);
++ return pm;
+}
+
+inline void pmt_exit(struct higmac_netdev_local *ld)
+{
-+ int v;
-+ unsigned long flags;
++ unsigned int v;
++ unsigned long flags;
+
-+ /* logic auto exit power down mode */
-+ spin_lock_irqsave(&ld->pmtlock, flags);
++ /* logic auto exit power down mode */
++ spin_lock_irqsave(&ld->pmtlock, flags);
+
-+ v = readl(ld->gmac_iobase + PMT_CTRL);
-+ v &= ~BIT(0); /* enter power down */
-+ v &= ~BIT(3); /* enable wakeup irq */
++ v = readl(ld->gmac_iobase + PMT_CTRL);
++ v &= ~BIT(0); /* enter power down */
++ v &= ~BIT(3); /* enable wakeup irq */
+
-+ v |= 3 << 5; /* clear irq status */
-+ writel(v, ld->gmac_iobase + PMT_CTRL);
++ v |= 3 << 5; /* clear irq status */
++ writel(v, ld->gmac_iobase + PMT_CTRL);
+
-+ spin_unlock_irqrestore(&ld->pmtlock, flags);
++ spin_unlock_irqrestore(&ld->pmtlock, flags);
+
-+ ld->wol_enable = false;
-+ /* device_set_wakeup_enable(ld->dev, 0); */
++ ld->wol_enable = false;
++ /* device_set_wakeup_enable(ld->dev, 0); */
+}
+
+void pmt_reg_restore(struct higmac_netdev_local *ld)
+{
-+ unsigned int v;
-+ unsigned long flags;
++ unsigned int v;
++ unsigned long flags;
+
-+ spin_lock_irqsave(&ld->pmtlock, flags);
-+ v = pm_reg_config_backup.pmt_mask0;
-+ writel(v, ld->gmac_iobase + PMT_MASK0);
++ spin_lock_irqsave(&ld->pmtlock, flags);
++ v = pm_reg_config_backup.pmt_mask0;
++ writel(v, ld->gmac_iobase + PMT_MASK0);
+
-+ v = pm_reg_config_backup.pmt_mask1;
-+ writel(v, ld->gmac_iobase + PMT_MASK1);
++ v = pm_reg_config_backup.pmt_mask1;
++ writel(v, ld->gmac_iobase + PMT_MASK1);
+
-+ v = pm_reg_config_backup.pmt_mask2;
-+ writel(v, ld->gmac_iobase + PMT_MASK2);
++ v = pm_reg_config_backup.pmt_mask2;
++ writel(v, ld->gmac_iobase + PMT_MASK2);
+
-+ v = pm_reg_config_backup.pmt_mask3;
-+ writel(v, ld->gmac_iobase + PMT_MASK3);
++ v = pm_reg_config_backup.pmt_mask3;
++ writel(v, ld->gmac_iobase + PMT_MASK3);
+
-+ v = pm_reg_config_backup.pmt_cmd;
-+ writel(v, ld->gmac_iobase + PMT_CMD);
++ v = pm_reg_config_backup.pmt_cmd;
++ writel(v, ld->gmac_iobase + PMT_CMD);
+
-+ v = pm_reg_config_backup.pmt_offset;
-+ writel(v, ld->gmac_iobase + PMT_OFFSET);
++ v = pm_reg_config_backup.pmt_offset;
++ writel(v, ld->gmac_iobase + PMT_OFFSET);
+
-+ v = pm_reg_config_backup.pmt_crc1_0;
-+ writel(v, ld->gmac_iobase + PMT_CRC1_0);
++ v = pm_reg_config_backup.pmt_crc1_0;
++ writel(v, ld->gmac_iobase + PMT_CRC1_0);
+
-+ v = pm_reg_config_backup.pmt_crc3_2;
-+ writel(v, ld->gmac_iobase + PMT_CRC3_2);
++ v = pm_reg_config_backup.pmt_crc3_2;
++ writel(v, ld->gmac_iobase + PMT_CRC3_2);
+
-+ v = pm_reg_config_backup.pmt_ctrl;
-+ writel(v, ld->gmac_iobase + PMT_CTRL);
-+ spin_unlock_irqrestore(&ld->pmtlock, flags);
++ v = pm_reg_config_backup.pmt_ctrl;
++ writel(v, ld->gmac_iobase + PMT_CTRL);
++ spin_unlock_irqrestore(&ld->pmtlock, flags);
+}
+
+/* ========the following code copy from Synopsys DWC_gmac_crc_example.c====== */
-+#define CRC16 /* Change it to CRC16 for CRC16 Computation */
++#define CRC16 /* Change it to CRC16 for CRC16 Computation */
+
+#if defined(CRC16)
-+#define CRC_NAME "CRC-16"
-+#define POLYNOMIAL 0x8005
-+#define INITIAL_REMAINDER 0xFFFF
-+#define FINAL_XOR_VALUE 0x0000
++#define CRC_NAME "CRC-16"
++#define POLYNOMIAL 0x8005
++#define INITIAL_REMAINDER 0xFFFF
++#define FINAL_XOR_VALUE 0x0000
+#define REVERSE_DATA
+#undef REVERSE_REMAINDER
+#endif
+
-+#define WIDTH (8 * sizeof(unsigned short))
-+#define TOPBIT BIT(WIDTH - 1)
++#define WIDTH (8 * sizeof(unsigned short))
++#define TOPBIT BIT(WIDTH - 1)
+
+#ifdef REVERSE_DATA
-+#undef REVERSE_DATA
-+#define REVERSE_DATA(X) ((unsigned char)reverse((X), 8))
++#undef REVERSE_DATA
++#define REVERSE_DATA(X) ((unsigned char)reverse((X), 8))
+#else
-+#undef REVERSE_DATA
-+#define REVERSE_DATA(X) (X)
++#undef REVERSE_DATA
++#define REVERSE_DATA(X) (X)
+#endif
+
+#ifdef REVERSE_REMAINDER
-+#undef REVERSE_REMAINDER
-+#define REVERSE_REMAINDER(X) ((unsigned short)reverse((X), WIDTH))
++#undef REVERSE_REMAINDER
++#define REVERSE_REMAINDER(X) ((unsigned short)reverse((X), WIDTH))
+#else
-+#undef REVERSE_REMAINDER
-+#define REVERSE_REMAINDER(X) (X)
++#undef REVERSE_REMAINDER
++#define REVERSE_REMAINDER(X) (X)
+#endif
+
+static unsigned short crc_table[256];
@@ -317210,63 +385505,60 @@ index 0000000..1b0ceac
+ */
+static unsigned int reverse(unsigned int data, unsigned char nbits)
+{
-+ unsigned int reversed = 0x00000000;
-+ unsigned char bit;
++ unsigned int reversed = 0x00000000;
++ unsigned char bit;
+
-+ /* Reverse the data about the center bit. */
-+ for (bit = 0; bit < nbits; ++bit) {
-+ /* If the LSB bit is set, set the reflection of it. */
-+ if (data & 0x01) {
-+ reversed |= BIT((nbits - 1) - bit);
-+ }
++ /* Reverse the data about the center bit. */
++ for (bit = 0; bit < nbits; ++bit) {
++ /* If the LSB bit is set, set the reflection of it. */
++ if (data & 0x01)
++ reversed |= BIT((nbits - 1) - bit);
+
-+ data = (data >> 1);
-+ }
-+ return reversed;
++ data = (data >> 1);
++ }
++ return reversed;
+}
+
+/* This Initializes the partial CRC look up table */
+static void init_crc_table(void)
+{
-+ unsigned short remainder;
-+ int dividend;
-+ unsigned char bit;
++ unsigned short remainder;
++ unsigned int dividend;
++ unsigned char bit;
+
-+ /* Compute the remainder of each possible dividend. */
-+ for (dividend = 0; dividend < 256; ++dividend) {
-+ /* Start with the dividend followed by zeros. */
-+ remainder = (unsigned short)(dividend << (WIDTH - 8));
++ /* Compute the remainder of each possible dividend. */
++ for (dividend = 0; dividend < 256; ++dividend) {
++ /* Start with the dividend followed by zeros. */
++ remainder = (unsigned short)(dividend << (WIDTH - 8));
+
-+ /* Perform modulo-2 division, a bit at a time. */
-+ for (bit = 8; bit > 0; --bit) {
-+ /* Try to divide the current data bit. */
-+ if (remainder & TOPBIT) {
-+ remainder = (remainder << 1) ^ POLYNOMIAL;
-+ }
-+ else {
-+ remainder = (remainder << 1);
-+ }
-+ }
++ /* Perform modulo-2 division, a bit at a time. */
++ for (bit = 8; bit > 0; --bit) {
++ /* Try to divide the current data bit. */
++ if (remainder & TOPBIT)
++ remainder = (remainder << 1) ^ POLYNOMIAL;
++ else
++ remainder = (remainder << 1);
++ }
+
-+ /* Store the result into the table. */
-+ crc_table[dividend] = remainder;
-+ }
++ /* Store the result into the table. */
++ crc_table[dividend] = remainder;
++ }
+}
+
-+static unsigned short compute_crc(char *message, int nbytes)
++static unsigned short compute_crc(const char *message, int nbytes)
+{
-+ unsigned short remainder = INITIAL_REMAINDER;
-+ int byte;
-+ unsigned char data;
++ unsigned short remainder = INITIAL_REMAINDER;
++ int byte;
++ unsigned char data;
+
-+ /* Divide the message by the polynomial, a byte at a time. */
-+ for (byte = 0; byte < nbytes; ++byte) {
-+ data = REVERSE_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
-+ remainder = crc_table[data] ^ (remainder << 8);
-+ }
++ /* Divide the message by the polynomial, a byte at a time. */
++ for (byte = 0; byte < nbytes; ++byte) {
++ data = REVERSE_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
++ remainder = crc_table[data] ^ (remainder << 8);
++ }
+
-+ /* The final remainder is the CRC. */
-+ return (REVERSE_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
++ /* The final remainder is the CRC. */
++ return (REVERSE_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+}
diff --git a/drivers/net/ethernet/hisilicon/higmac/proc-dev.c b/drivers/net/ethernet/hisilicon/higmac/proc-dev.c
new file mode 100644
@@ -317395,7 +385687,7 @@ index 0000000..582a9ec
+}
diff --git a/drivers/net/ethernet/hisilicon/higmac/sockioctl.h b/drivers/net/ethernet/hisilicon/higmac/sockioctl.h
new file mode 100644
-index 0000000..b5d9aca
+index 0000000..571c71a
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/sockioctl.h
@@ -0,0 +1,12 @@
@@ -317404,107 +385696,103 @@ index 0000000..b5d9aca
+
+#include <linux/sockios.h>
+
-+#define SIOCSETPM (SIOCDEVPRIVATE + 4) /* set pmt wake up config */
-+#define SIOCSETSUSPEND (SIOCDEVPRIVATE + 5) /* call dev->suspend, debug */
-+#define SIOCSETRESUME (SIOCDEVPRIVATE + 6) /* call dev->resume, debug */
++#define SIOCSETPM (SIOCDEVPRIVATE + 4) /* set pmt wake up config */
++#define SIOCSETSUSPEND (SIOCDEVPRIVATE + 5) /* call dev->suspend, debug */
++#define SIOCSETRESUME (SIOCDEVPRIVATE + 6) /* call dev->resume, debug */
+
+int higmac_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd);
+
+#endif
diff --git a/drivers/net/ethernet/hisilicon/higmac/tso.h b/drivers/net/ethernet/hisilicon/higmac/tso.h
new file mode 100644
-index 0000000..72aeea6
+index 0000000..6416eef
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/tso.h
@@ -0,0 +1,53 @@
+#ifndef __HIETH_TSO_H
+#define __HIETH_TSO_H
+
-+#define SG_FLAG BIT(30)
-+#define COE_FLAG BIT(29)
-+#define TSO_FLAG BIT(28)
-+#define VLAN_FLAG BIT(10)
-+#define IPV6_FLAG BIT(9)
-+#define UDP_FLAG BIT(8)
++#define SG_FLAG BIT(30)
++#define COE_FLAG BIT(29)
++#define TSO_FLAG BIT(28)
++#define VLAN_FLAG BIT(10)
++#define IPV6_FLAG BIT(9)
++#define UDP_FLAG BIT(8)
+
-+#define PKT_IPV6_HDR_LEN 10
-+#define PKT_UDP_HDR_LEN 2
-+#define WORD_TO_BYTE 4
++#define PKT_IPV6_HDR_LEN 10
++#define PKT_UDP_HDR_LEN 2
++#define WORD_TO_BYTE 4
+enum {
-+ PKT_NORMAL,
-+ PKT_SG
++ PKT_NORMAL,
++ PKT_SG
+};
+
+enum {
-+ PKT_IPV4,
-+ PKT_IPV6
++ PKT_IPV4,
++ PKT_IPV6
+};
+
+enum {
-+ PKT_TCP,
-+ PKT_UDP
++ PKT_TCP,
++ PKT_UDP
+};
+
+struct frags_info {
-+ /* Word(2*i+2) */
-+ u32 addr;
-+ /* Word(2*i+3) */
-+ u32 size : 16;
-+ u32 reserved : 16;
++ /* Word(2*i+2) */
++ u32 addr;
++ /* Word(2*i+3) */
++ u32 size:16;
++ u32 reserved:16;
+};
+
+struct sg_desc {
-+ /* Word0 */
-+ u32 total_len : 17;
-+ u32 reserv : 15;
-+ /* Word1 */
-+ u32 ipv6_id;
-+ /* Word2 */
-+ u32 linear_addr;
-+ /* Word3 */
-+ u32 linear_len : 16;
-+ u32 reserv3 : 16;
-+ /* MAX_SKB_FRAGS = 17 */
-+ struct frags_info frags[18];
-+ /* struct frags_info frags[MAX_SKB_FRAGS]; */
++ /* Word0 */
++ u32 total_len:17;
++ u32 reserv:15;
++ /* Word1 */
++ u32 ipv6_id;
++ /* Word2 */
++ u32 linear_addr;
++ /* Word3 */
++ u32 linear_len:16;
++ u32 reserv3:16;
++ /* MAX_SKB_FRAGS = 17 */
++ struct frags_info frags[18];
++ /* struct frags_info frags[MAX_SKB_FRAGS]; */
+};
+
+#endif
diff --git a/drivers/net/ethernet/hisilicon/higmac/util.h b/drivers/net/ethernet/hisilicon/higmac/util.h
new file mode 100644
-index 0000000..fd90b5b
+index 0000000..f08cbf6
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/higmac/util.h
-@@ -0,0 +1,33 @@
+@@ -0,0 +1,29 @@
+#ifndef __HIGMAC_UTIL_H__
+#define __HIGMAC_UTIL_H__
+
+#define HIGMAC_TRACE_LEVEL 10
+
-+#define higmac_trace(level, msg...) \
-+ do { \
-+ if ((level) >= HIGMAC_TRACE_LEVEL) { \
-+ pr_info("higmac_trace:%s:%d: ", __FILE__, __LINE__); \
-+ printk(msg); \
-+ printk("\n"); \
-+ } \
-+ } while (0)
++#define higmac_trace(level, msg...) do { \
++ if ((level) >= HIGMAC_TRACE_LEVEL) { \
++ pr_info("higmac_trace:%s:%d: ", __FILE__, __LINE__); \
++ printk(msg); \
++ printk("\n"); \
++ } \
++} while (0)
+
-+#define higmac_error(args...) \
-+ do { \
-+ pr_err("higmac:%s:%d: ", __FILE__, __LINE__); \
-+ printk(args); \
-+ printk("\n"); \
-+ } while (0)
++#define higmac_error(args...) do { \
++ pr_err("higmac:%s:%d: ", __FILE__, __LINE__); \
++ printk(args); \
++ printk("\n"); \
++} while (0)
+
-+#define higmac_assert(cond) \
-+ do { \
-+ if (!(cond)) { \
-+ pr_alert("Assert:higmac:%s:%d\n", \
-+ __FILE__, \
-+ __LINE__); \
-+ } \
-+ } while (0)
++#define higmac_assert(cond) do { \
++ if (!(cond)) \
++ pr_alert("Assert:higmac:%s:%d\n", \
++ __FILE__, \
++ __LINE__);\
++} while (0)
+
+#define MK_BITS(shift, nbits) ((((shift) & 0x1F) << 16) | ((nbits) & 0x3F))
+
@@ -318181,10 +386469,10 @@ index 0000000..94e68cf
+ 0x33f8, 0x01
diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/hisi_femac.c b/drivers/net/ethernet/hisilicon/hisi-femac/hisi_femac.c
new file mode 100644
-index 0000000..832485d
+index 0000000..bb03ac7
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/hisi-femac/hisi_femac.c
-@@ -0,0 +1,2083 @@
+@@ -0,0 +1,2084 @@
+/*
+ * Hisilicon Fast Ethernet MAC Driver
+ *
@@ -318320,7 +386608,7 @@ index 0000000..832485d
+/* software tx and rx queue number, should be power of 2 */
+#define TXQ_NUM 64
+#define RXQ_NUM 128
-+#define FEMAC_POLL_WEIGHT 16
++#define FEMAC_POLL_WEIGHT 64
+#define HW_CAP_TSO BIT(0)
+#define HW_CAP_RXCSUM BIT(1)
+#define HAS_TSO_CAP(hw_cap) ((hw_cap) & HW_CAP_TSO)
@@ -318480,7 +386768,7 @@ index 0000000..832485d
+ /* struct frags_info frags[MAX_SKB_FRAGS]; */
+};
+
-+static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, u32 irqs)
++static void hisi_femac_irq_enable(const struct hisi_femac_priv *priv, u32 irqs)
+{
+ u32 val;
+
@@ -318488,7 +386776,7 @@ index 0000000..832485d
+ writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
+}
+
-+static void hisi_femac_irq_disable(struct hisi_femac_priv *priv, u32 irqs)
++static void hisi_femac_irq_disable(const struct hisi_femac_priv *priv, u32 irqs)
+{
+ u32 val;
+
@@ -318627,7 +386915,7 @@ index 0000000..832485d
+}
+#endif
+
-+static void hisi_femac_set_flow_ctrl(struct hisi_femac_priv *priv)
++static void hisi_femac_set_flow_ctrl(const struct hisi_femac_priv *priv)
+{
+ unsigned int pause_en;
+ unsigned int tx_flow_ctrl;
@@ -318653,8 +386941,8 @@ index 0000000..832485d
+ writel(pause_en, priv->port_base + MAC_SET);
+}
+
-+static void hisi_femac_tx_sg_dma_unmap(struct hisi_femac_priv *priv,
-+ struct sk_buff *skb, unsigned int pos)
++static void hisi_femac_tx_sg_dma_unmap(const struct hisi_femac_priv *priv,
++ const struct sk_buff *skb, unsigned int pos)
+{
+ struct tx_desc *desc_cur;
+ dma_addr_t addr;
@@ -318674,8 +386962,8 @@ index 0000000..832485d
+ }
+}
+
-+static void hisi_femac_tx_dma_unmap(struct hisi_femac_priv *priv,
-+ struct sk_buff *skb, unsigned int pos)
++static void hisi_femac_tx_dma_unmap(const struct hisi_femac_priv *priv,
++ const struct sk_buff *skb, unsigned int pos)
+{
+ if (!(skb_is_gso(skb) || skb_shinfo(skb)->nr_frags)) {
+ dma_addr_t dma_addr;
@@ -318689,7 +386977,7 @@ index 0000000..832485d
+
+static void hisi_femac_xmit_reclaim(struct net_device *dev)
+{
-+ struct sk_buff *skb;
++ struct sk_buff *skb = NULL;
+ struct hisi_femac_priv *priv = netdev_priv(dev);
+ struct hisi_femac_queue *txq = &priv->txq;
+ unsigned int bytes_compl = 0, pkts_compl = 0;
@@ -318726,12 +387014,12 @@ index 0000000..832485d
+ netif_tx_unlock(dev);
+}
+
-+static void hisi_femac_get_tso_err_info(struct hisi_femac_priv *priv)
++static void hisi_femac_get_tso_err_info(const struct hisi_femac_priv *priv)
+{
+ unsigned int reg_addr, reg_tx_info, reg_tx_err;
+ unsigned int sg_index;
-+ struct tx_desc *sg_desc;
-+ int *sg_word;
++ struct tx_desc *sg_desc = NULL;
++ int *sg_word = NULL;
+ int i;
+
+ reg_addr = readl(priv->port_base + TSO_DBG_ADDR);
@@ -318765,7 +387053,8 @@ index 0000000..832485d
+static netdev_tx_t hisi_femac_sw_gso(struct sk_buff *skb,
+ struct net_device *dev)
+{
-+ struct sk_buff *segs, *curr_skb;
++ struct sk_buff *segs = NULL;
++ struct sk_buff *curr_skb = NULL;
+ netdev_features_t features = dev->features;
+
+ features &= ~(NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
@@ -318842,7 +387131,7 @@ index 0000000..832485d
+
+static int hisi_femac_check_hw_capability_for_ipv6(struct sk_buff *skb)
+{
-+ unsigned int l4_proto = IPPROTO_MAX;
++ unsigned int l4_proto;
+
+ l4_proto = ipv6_hdr(skb)->nexthdr;
+
@@ -318962,8 +387251,8 @@ index 0000000..832485d
+ return pkt_info;
+}
+
-+static int hisi_femac_fill_sg_desc(struct hisi_femac_priv *priv,
-+ struct sk_buff *skb, unsigned int pos)
++static int hisi_femac_fill_sg_desc(const struct hisi_femac_priv *priv,
++ const struct sk_buff *skb, unsigned int pos)
+{
+ struct tx_desc *desc_cur;
+ dma_addr_t addr;
@@ -319029,7 +387318,7 @@ index 0000000..832485d
+static void hisi_femac_rx_refill(struct hisi_femac_priv *priv)
+{
+ struct hisi_femac_queue *rxq = &priv->rxq;
-+ struct sk_buff *skb;
++ struct sk_buff *skb = NULL;
+ u32 pos;
+ u32 len = MAX_FRAME_SIZE;
+ dma_addr_t addr;
@@ -319052,7 +387341,7 @@ index 0000000..832485d
+ break;
+ }
+
-+ alloc_rxbuf_align = ((unsigned long)skb->data - NET_IP_ALIGN) &
++ alloc_rxbuf_align = ((uintptr_t)skb->data - NET_IP_ALIGN) &
+ (RXBUF_ADDR_ALIGN_SIZE - 1);
+ if (alloc_rxbuf_align) {
+ reserve_room = RXBUF_ADDR_ALIGN_SIZE -
@@ -319080,7 +387369,7 @@ index 0000000..832485d
+{
+ struct hisi_femac_priv *priv = netdev_priv(dev);
+ struct hisi_femac_queue *rxq = &priv->rxq;
-+ struct sk_buff *skb;
++ struct sk_buff *skb = NULL;
+ dma_addr_t addr;
+ u32 rx_pkt_info, pos, len;
+ int hdr_csum_done, hdr_csum_err;
@@ -319387,7 +387676,7 @@ index 0000000..832485d
+{
+ struct hisi_femac_queue *txq = &priv->txq;
+ struct hisi_femac_queue *rxq = &priv->rxq;
-+ struct sk_buff *skb;
++ struct sk_buff *skb = NULL;
+ dma_addr_t dma_addr;
+ u32 pos;
+
@@ -319429,8 +387718,8 @@ index 0000000..832485d
+ priv->tx_fifo_used_cnt = 0;
+}
+
-+static int hisi_femac_set_hw_mac_addr(struct hisi_femac_priv *priv,
-+ unsigned char *mac)
++static int hisi_femac_set_hw_mac_addr(const struct hisi_femac_priv *priv,
++ const unsigned char *mac)
+{
+ u32 reg;
+
@@ -319443,7 +387732,7 @@ index 0000000..832485d
+ return 0;
+}
+
-+static int hisi_femac_port_reset(struct hisi_femac_priv *priv)
++static int hisi_femac_port_reset(const struct hisi_femac_priv *priv)
+{
+ u32 val;
+
@@ -319617,7 +387906,7 @@ index 0000000..832485d
+ return 0;
+}
+
-+static void hisi_femac_enable_hw_addr_filter(struct hisi_femac_priv *priv,
++static void hisi_femac_enable_hw_addr_filter(const struct hisi_femac_priv *priv,
+ unsigned int reg_n, bool enable)
+{
+ u32 val;
@@ -319631,8 +387920,8 @@ index 0000000..832485d
+ writel(val, priv->glb_base + GLB_MAC_H16(reg_n));
+}
+
-+static void hisi_femac_set_hw_addr_filter(struct hisi_femac_priv *priv,
-+ unsigned char *addr,
++static void hisi_femac_set_hw_addr_filter(const struct hisi_femac_priv *priv,
++ const unsigned char *addr,
+ unsigned int reg_n)
+{
+ unsigned int high, low;
@@ -319651,7 +387940,7 @@ index 0000000..832485d
+ writel(val, priv->glb_base + high);
+}
+
-+static void hisi_femac_set_promisc_mode(struct hisi_femac_priv *priv,
++static void hisi_femac_set_promisc_mode(const struct hisi_femac_priv *priv,
+ bool promisc_mode)
+{
+ u32 val;
@@ -319666,7 +387955,7 @@ index 0000000..832485d
+}
+
+/* Handle multiple multicast addresses (perfect filtering) */
-+static void hisi_femac_set_mc_addr_filter(struct hisi_femac_priv *priv)
++static void hisi_femac_set_mc_addr_filter(const struct hisi_femac_priv *priv)
+{
+ struct net_device *dev = priv->ndev;
+ u32 val;
@@ -319678,7 +387967,7 @@ index 0000000..832485d
+ } else {
+ int reg = MAX_UNICAST_ADDRESSES;
+ int i;
-+ struct netdev_hw_addr *ha;
++ struct netdev_hw_addr *ha = NULL;
+
+ for (i = reg; i < MAX_MAC_FILTER_NUM; i++) {
+ hisi_femac_enable_hw_addr_filter(priv, i, false);
@@ -319695,7 +387984,7 @@ index 0000000..832485d
+}
+
+/* Handle multiple unicast addresses (perfect filtering) */
-+static void hisi_femac_set_uc_addr_filter(struct hisi_femac_priv *priv)
++static void hisi_femac_set_uc_addr_filter(const struct hisi_femac_priv *priv)
+{
+ struct net_device *dev = priv->ndev;
+ u32 val;
@@ -319706,7 +387995,7 @@ index 0000000..832485d
+ } else {
+ int reg = 0;
+ int i;
-+ struct netdev_hw_addr *ha;
++ struct netdev_hw_addr *ha = NULL;
+
+ for (i = reg; i < MAX_UNICAST_ADDRESSES; i++) {
+ hisi_femac_enable_hw_addr_filter(priv, i, false);
@@ -319795,7 +388084,7 @@ index 0000000..832485d
+ return ret;
+}
+
-+static void hisi_femac_enable_rxcsum_drop(struct hisi_femac_priv *priv,
++static void hisi_femac_enable_rxcsum_drop(const struct hisi_femac_priv *priv,
+ bool drop)
+{
+ unsigned int val;
@@ -319862,7 +388151,7 @@ index 0000000..832485d
+ }
+}
+
-+static void hisi_femac_core_reset(struct hisi_femac_priv *priv)
++static void hisi_femac_core_reset(const struct hisi_femac_priv *priv)
+{
+ reset_control_assert(priv->mac_rst);
+ reset_control_deassert(priv->mac_rst);
@@ -319884,7 +388173,7 @@ index 0000000..832485d
+ }
+}
+
-+static void hisi_femac_phy_reset(struct hisi_femac_priv *priv)
++static void hisi_femac_phy_reset(const struct hisi_femac_priv *priv)
+{
+ /* To make sure PHY hardware reset success,
+ * we must keep PHY in deassert state first and
@@ -319953,11 +388242,11 @@ index 0000000..832485d
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
-+ struct resource *res;
-+ struct net_device *ndev;
-+ struct hisi_femac_priv *priv;
-+ struct phy_device *phy;
-+ const char *mac_addr;
++ struct resource *res = NULL;
++ struct net_device *ndev = NULL;
++ struct hisi_femac_priv *priv = NULL;
++ struct phy_device *phy = NULL;
++ const char *mac_addr = NULL;
+ int ret;
+
+ ndev = alloc_etherdev(sizeof(*priv));
@@ -320265,7 +388554,7 @@ index 0000000..832485d
+module_platform_driver(hisi_femac_driver);
+
+MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC driver");
-+MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
++MODULE_AUTHOR("Hisilicon");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:hisi-femac");
diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/phy_fix.c b/drivers/net/ethernet/hisilicon/hisi-femac/phy_fix.c
@@ -321417,7 +389706,7 @@ index e58667d..a6ae694 100644
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o
diff --git a/drivers/net/phy/mdio-hisi-femac.c b/drivers/net/phy/mdio-hisi-femac.c
-index b03fedd..0f290a9 100644
+index b03fedd..ef0166c 100644
--- a/drivers/net/phy/mdio-hisi-femac.c
+++ b/drivers/net/phy/mdio-hisi-femac.c
@@ -24,6 +24,7 @@
@@ -321526,7 +389815,7 @@ index b03fedd..0f290a9 100644
+ msleep(time_ms);
+}
+
-+static void hisi_femac_phy_reset(struct hisi_femac_mdio_data *data)
++static void hisi_femac_phy_reset(const struct hisi_femac_mdio_data *data)
+{
+ /* To make sure PHY hardware reset success,
+ * we must keep PHY in deassert state first and
@@ -321809,7 +390098,7 @@ index b03fedd..0f290a9 100644
mdiobus_free(bus);
diff --git a/drivers/net/phy/mdio-hisi-gemac.c b/drivers/net/phy/mdio-hisi-gemac.c
new file mode 100644
-index 0000000..244ca71
+index 0000000..7755591
--- /dev/null
+++ b/drivers/net/phy/mdio-hisi-gemac.c
@@ -0,0 +1,249 @@
@@ -321972,9 +390261,9 @@ index 0000000..244ca71
+static int hisi_gemac_mdio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
-+ struct mii_bus *bus;
-+ struct hisi_gemac_mdio_data *data;
-+ struct resource *res;
++ struct mii_bus *bus = NULL;
++ struct hisi_gemac_mdio_data *data = NULL;
++ struct resource *res = NULL;
+ int ret;
+
+ bus = mdiobus_alloc_size(sizeof(*data));
@@ -322197,13 +390486,13 @@ index 8db5079..955b899 100644
+obj-$(CONFIG_HIPCIE) += hipcie/
diff --git a/drivers/pci/hipcie/Kconfig b/drivers/pci/hipcie/Kconfig
new file mode 100644
-index 0000000..6e2cc78
+index 0000000..4e9773d
--- /dev/null
+++ b/drivers/pci/hipcie/Kconfig
@@ -0,0 +1,28 @@
+menuconfig HIPCIE
+ bool "Hisilicon PCI Express support"
-+ depends on PCI && (ARCH_HI3559AV100 || ARCH_HI3531A || ARCH_HI3519AV100)
++ depends on PCI && (ARCH_HI3559AV100 || ARCH_HI3531A || ARCH_HI3519AV100 || ARCH_HI3569V100)
+ default y if PCI
+ default n if ! PCI
+ help
@@ -322218,7 +390507,7 @@ index 0000000..6e2cc78
+config LIMIT_MAX_RD_REQ_SIZE
+ bool "limit pcie max read request size"
+ default y
-+ depends on PCI && (ARCH_HI3559AV100 || ARCH_HI3531A || ARCH_HI3519AV100)
++ depends on PCI && (ARCH_HI3559AV100 || ARCH_HI3531A || ARCH_HI3519AV100 || ARCH_HI3569V100)
+ help
+ The default max read request size of pcie device is 512 Byte. When pcie use
+ the card of pcie-to-sata to connect to the sata disk, with the default max read
@@ -322245,7 +390534,7 @@ index 0000000..0455420
+endif
diff --git a/drivers/pci/hipcie/pci.h b/drivers/pci/hipcie/pci.h
new file mode 100644
-index 0000000..318a672
+index 0000000..b1f1ac1
--- /dev/null
+++ b/drivers/pci/hipcie/pci.h
@@ -0,0 +1,80 @@
@@ -322271,24 +390560,24 @@ index 0000000..318a672
+
+struct hw_pci {
+#ifdef CONFIG_PCI_DOMAINS
-+ int domain;
++ int domain;
+#endif
-+ struct pci_ops *ops;
-+ int nr_controllers;
-+ void **private_data;
-+ int (*setup)(int nr, struct pci_sys_data *);
-+ struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
-+ void (*preinit)(void);
-+ void (*postinit)(void);
-+ u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
-+ int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
-+ resource_size_t (*align_resource)(struct pci_dev *dev,
-+ const struct resource *res,
-+ resource_size_t start,
-+ resource_size_t size,
-+ resource_size_t align);
-+ void (*add_bus)(struct pci_bus *bus);
-+ void (*remove_bus)(struct pci_bus *bus);
++ struct pci_ops *ops;
++ int nr_controllers;
++ void **private_data;
++ int (*setup)(int nr, struct pci_sys_data *);
++ struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
++ void (*preinit)(void);
++ void (*postinit)(void);
++ u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
++ int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
++ resource_size_t (*align_resource)(struct pci_dev *dev,
++ const struct resource *res,
++ resource_size_t start,
++ resource_size_t size,
++ resource_size_t align);
++ void (*add_bus)(struct pci_bus *bus);
++ void (*remove_bus)(struct pci_bus *bus);
+};
+
+/*
@@ -322296,42 +390585,42 @@ index 0000000..318a672
+ */
+struct pci_sys_data {
+#ifdef CONFIG_PCI_DOMAINS
-+ int domain;
++ int domain;
+#endif
-+ struct list_head node;
-+ int busnr; /* primary bus number */
-+ u64 mem_offset; /* bus->cpu memory mapping offset */
-+ unsigned long io_offset; /* bus->cpu IO mapping offset */
-+ struct pci_bus *bus; /* PCI bus */
-+ struct list_head resources; /* root bus resources (apertures) */
-+ struct resource io_res;
-+ char io_res_name[12];
-+ /* Bridge swizzling */
-+ u8 (*swizzle)(struct pci_dev *, u8 *);
-+ /* IRQ mapping */
-+ int (*map_irq)(const struct pci_dev *, u8, u8);
-+ /* Resource alignement requirements */
-+ resource_size_t (*align_resource)(struct pci_dev *dev,
-+ const struct resource *res,
-+ resource_size_t start,
-+ resource_size_t size,
-+ resource_size_t align);
-+ void (*add_bus)(struct pci_bus *bus);
-+ void (*remove_bus)(struct pci_bus *bus);
-+ void *private_data; /* platform controller private data */
++ struct list_head node;
++ int busnr; /* primary bus number */
++ u64 mem_offset; /* bus->cpu memory mapping offset */
++ unsigned long io_offset; /* bus->cpu IO mapping offset */
++ struct pci_bus *bus; /* PCI bus */
++ struct list_head resources; /* root bus resources (apertures) */
++ struct resource io_res;
++ char io_res_name[12];
++ /* Bridge swizzling */
++ u8 (*swizzle)(struct pci_dev *, u8 *);
++ /* IRQ mapping */
++ int (*map_irq)(const struct pci_dev *, u8, u8);
++ /* Resource alignement requirements */
++ resource_size_t (*align_resource)(struct pci_dev *dev,
++ const struct resource *res,
++ resource_size_t start,
++ resource_size_t size,
++ resource_size_t align);
++ void (*add_bus)(struct pci_bus *bus);
++ void (*remove_bus)(struct pci_bus *bus);
++ void *private_data; /* platform controller private data */
+};
+
+void __weak pcibios_update_irq(struct pci_dev *dev, int irq)
+{
-+ dev_dbg(&dev->dev, "assigning IRQ %02d\n", irq);
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
++ dev_dbg(&dev->dev, "assigning IRQ %02d\n", irq);
++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
+}
+
+
+#endif /* __ASM_MACH_PCI_H */
diff --git a/drivers/pci/hipcie/pcie.c b/drivers/pci/hipcie/pcie.c
new file mode 100644
-index 0000000..4091716
+index 0000000..a32c2c2
--- /dev/null
+++ b/drivers/pci/hipcie/pcie.c
@@ -0,0 +1,692 @@
@@ -322403,65 +390692,65 @@ index 0000000..4091716
+#define __8KB__ 0x2000
+
+enum pcie_sel {
-+ /*
-+ * No controller selected.
-+ */
-+ pcie_sel_none,
-+ /*
-+ * PCIE0 selected.
-+ */
-+ pcie0_x1_sel,
-+ /*
-+ * PCIE1 selected.
-+ */
-+ pcie1_x1_sel
++ /*
++ * No controller selected.
++ */
++ pcie_sel_none,
++ /*
++ * PCIE0 selected.
++ */
++ pcie0_x1_sel,
++ /*
++ * PCIE1 selected.
++ */
++ pcie1_x1_sel
+};
+
+enum pcie_rc_sel {
-+ pcie_controller_unselected,
-+ pcie_controller_selected
++ pcie_controller_unselected,
++ pcie_controller_selected
+};
+
+enum pcie_controller {
-+ pcie_controller_none = -1,
-+ pcie_controller_0 = 0,
-+ pcie_controller_1 = 1
++ pcie_controller_none = -1,
++ pcie_controller_0 = 0,
++ pcie_controller_1 = 1
+};
+
+struct pcie_iatu {
-+ unsigned int viewport; /* iATU Viewport Register */
-+ unsigned int region_ctrl_1; /* Region Control 1 Register */
-+ unsigned int region_ctrl_2; /* Region Control 2 Register */
-+ unsigned int lbar; /* Lower Base Address Register */
-+ unsigned int ubar; /* Upper Base Address Register */
-+ unsigned int lar; /* Limit Address Register */
-+ unsigned int ltar; /* Lower Target Address Register */
-+ unsigned int utar; /* Upper Target Address Register */
++ unsigned int viewport; /* iATU Viewport Register */
++ unsigned int region_ctrl_1; /* Region Control 1 Register */
++ unsigned int region_ctrl_2; /* Region Control 2 Register */
++ unsigned int lbar; /* Lower Base Address Register */
++ unsigned int ubar; /* Upper Base Address Register */
++ unsigned int lar; /* Limit Address Register */
++ unsigned int ltar; /* Lower Target Address Register */
++ unsigned int utar; /* Upper Target Address Register */
+};
+
+#define MAX_IATU_PER_CTRLLER (6)
+
+struct pcie_info {
-+ /*
-+ * Root bus number
-+ */
-+ int root_bus_nr;
-+ enum pcie_controller controller;
++ /*
++ * Root bus number
++ */
++ int root_bus_nr;
++ enum pcie_controller controller;
+
-+ /*
-+ * Devices configuration space base
-+ */
-+ unsigned long base_addr;
++ /*
++ * Devices configuration space base
++ */
++ unsigned long base_addr;
+
-+ /*
-+ * RC configuration space base
-+ */
-+ unsigned long conf_base_addr;
++ /*
++ * RC configuration space base
++ */
++ unsigned long conf_base_addr;
+};
+
+static struct pcie_info pcie_info[2] = {
-+ {.root_bus_nr = -1,},
-+ {.root_bus_nr = -1,}
++ {.root_bus_nr = -1,},
++ {.root_bus_nr = -1,}
+};
+
+static int pcie_controllers_nr;
@@ -322479,7 +390768,7 @@ index 0000000..4091716
+#define PCIE1_MODE_SEL (1 << 1)
+
+
-+#if defined(CONFIG_ARCH_HI3559AV100)
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+#include "pcie_hi3559av100.c"
+#elif defined(CONFIG_ARCH_HI3531A)
+#include "pcie_hi3531a.c"
@@ -322494,19 +390783,19 @@ index 0000000..4091716
+ */
+static int __init pcie0_mem_size_parser(char *str)
+{
-+ unsigned int size;
++ unsigned int size;
+
-+ if (kstrtoul(str, 16, (long *)&size) < 0) {
-+ return 0;
-+ }
++ if (kstrtoul(str, 16, (long *)&size) < 0) {
++ return 0;
++ }
+
-+ /* if size >= 256MB, set default 256MB */
-+ if (size >= 0x10000000) {
-+ size = 0x10000000;
-+ }
-+ pcie0_mem_space_size = size;
++ /* if size >= 256MB, set default 256MB */
++ if (size >= 0x10000000) {
++ size = 0x10000000;
++ }
++ pcie0_mem_space_size = size;
+
-+ return 1;
++ return 1;
+}
+__setup("pcie0_mem_size=", pcie0_mem_size_parser);
+
@@ -322518,28 +390807,28 @@ index 0000000..4091716
+ */
+static int __init pcie0_sel_parser(char *str)
+{
-+ if (strncasecmp(str, "x1", 2) == 0) {
-+ pcie0_sel = pcie0_x1_sel;
-+ } else {
-+ pcie0_sel = pcie_sel_none;
-+ }
++ if (strncasecmp(str, "x1", 2) == 0) {
++ pcie0_sel = pcie0_x1_sel;
++ } else {
++ pcie0_sel = pcie_sel_none;
++ }
+
-+ return 1;
++ return 1;
+}
+__setup("pcie0_sel=", pcie0_sel_parser);
+
+static struct pcie_info *bus_to_info(int busnr)
+{
-+ int i = pcie_controllers_nr;
-+ for (; i >= 0; i--) {
-+ if (pcie_info[i].controller != pcie_controller_none
-+ && pcie_info[i].root_bus_nr <= busnr
-+ && pcie_info[i].root_bus_nr != -1) {
-+ return &pcie_info[i];
-+ }
-+ }
++ int i = pcie_controllers_nr;
++ for (; i >= 0; i--) {
++ if (pcie_info[i].controller != pcie_controller_none
++ && pcie_info[i].root_bus_nr <= busnr
++ && pcie_info[i].root_bus_nr != -1) {
++ return &pcie_info[i];
++ }
++ }
+
-+ return NULL;
++ return NULL;
+}
+
+
@@ -322548,427 +390837,427 @@ index 0000000..4091716
+#define PCIE_CFG_REG(reg) (reg & 0xffc) /*set dword align*/
+
+static inline unsigned long to_pcie_address(struct pci_bus *bus,
-+ unsigned int devfn, int where)
++ unsigned int devfn, int where)
+{
-+ struct pcie_info *info = bus_to_info(bus->number);
-+ unsigned long address = 0;
++ struct pcie_info *info = bus_to_info(bus->number);
++ unsigned long address = 0;
+
-+ if (unlikely(!info)) {
-+ pcie_error(
-+ "%s:Cannot find corresponding controller for appointed device!", __func__);
-+ BUG();
-+ }
++ if (unlikely(!info)) {
++ pcie_error(
++ "%s:Cannot find corresponding controller for appointed device!", __func__);
++ BUG();
++ }
+
-+ address = info->base_addr + (PCIE_CFG_BUS(bus->number)
-+ | PCIE_CFG_DEV(devfn) | PCIE_CFG_REG(where));
++ address = info->base_addr + (PCIE_CFG_BUS(bus->number)
++ | PCIE_CFG_DEV(devfn) | PCIE_CFG_REG(where));
+
-+ return address;
++ return address;
+}
+
+static inline int is_pcie_link_up(struct pcie_info *info)
+{
-+ int i;
++ int i;
+
-+ for (i = 0; i < 10000; i++) {
-+ if (__arch_check_pcie_link(info)) {
-+ break;
-+ }
-+ udelay(100);
-+ }
++ for (i = 0; i < 10000; i++) {
++ if (__arch_check_pcie_link(info)) {
++ break;
++ }
++ udelay(100);
++ }
+
-+ return (i < 10000);
++ return (i < 10000);
+}
+
+static int pcie_read_from_device(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *value)
++ int where, int size, u32 *value)
+{
-+ struct pcie_info *info = bus_to_info(bus->number);
-+ unsigned int val;
-+ void __iomem *addr;
-+ int i = 0;
++ struct pcie_info *info = bus_to_info(bus->number);
++ unsigned int val;
++ void __iomem *addr;
++ int i = 0;
+
-+ if (unlikely(!info)) {
-+ pcie_error(
-+ "%s:Cannot find corresponding controller for appointed device!", __func__);
-+ BUG();
-+ }
-+ if (!is_pcie_link_up(info)) {
-+ pcie_debug(PCIE_DBG_MODULE, "pcie %d not link up!",
-+ info->controller);
-+ return -1;
-+ }
++ if (unlikely(!info)) {
++ pcie_error(
++ "%s:Cannot find corresponding controller for appointed device!", __func__);
++ BUG();
++ }
++ if (!is_pcie_link_up(info)) {
++ pcie_debug(PCIE_DBG_MODULE, "pcie %d not link up!",
++ info->controller);
++ return -1;
++ }
+
-+ addr = (void __iomem *)to_pcie_address(bus, devfn, where);
++ addr = (void __iomem *)to_pcie_address(bus, devfn, where);
+
-+ val = readl(addr);
++ val = readl(addr);
+
-+ i = 0;
-+ while (i < 2000) {
-+ __asm__ __volatile__("nop\n");
-+ i++;
-+ }
++ i = 0;
++ while (i < 2000) {
++ __asm__ __volatile__("nop\n");
++ i++;
++ }
+
-+ if (pcie_errorvalue == 1) {
-+ pcie_errorvalue = 0;
-+ val = 0xffffffff;
-+ }
++ if (pcie_errorvalue == 1) {
++ pcie_errorvalue = 0;
++ val = 0xffffffff;
++ }
+
-+ if (size == 1) {
-+ *value = ((val >> ((where & 0x3) << 3)) & 0xff);
-+ } else if (size == 2) {
-+ *value = ((val >> ((where & 0x3) << 3)) & 0xffff);
-+ } else if (size == 4) {
-+ *value = val;
-+ } else {
-+ pcie_error("Unknown size(%d) for read ops", size);
-+ BUG();
-+ }
++ if (size == 1) {
++ *value = ((val >> ((where & 0x3) << 3)) & 0xff);
++ } else if (size == 2) {
++ *value = ((val >> ((where & 0x3) << 3)) & 0xffff);
++ } else if (size == 4) {
++ *value = val;
++ } else {
++ pcie_error("Unknown size(%d) for read ops", size);
++ BUG();
++ }
+
-+ return PCIBIOS_SUCCESSFUL;
++ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcie_read_from_dbi(struct pcie_info *info, unsigned int devfn,
-+ int where, int size, u32 *value)
++ int where, int size, u32 *value)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ /*
-+ * For host-side config space read, ignore device func nr.
-+ */
-+ if (devfn > 0) {
-+ return -EIO;
-+ }
++ /*
++ * For host-side config space read, ignore device func nr.
++ */
++ if (devfn > 0) {
++ return -EIO;
++ }
+
-+ val = (u32)readl((void *)(info->conf_base_addr + (where & (~0x3))));
++ val = (u32)readl((void *)(info->conf_base_addr + (where & (~0x3))));
+
-+ if (1 == size) {
-+ *value = (val >> ((where & 0x3) << 3)) & 0xff;
-+ } else if (2 == size) {
-+ *value = (val >> ((where & 0x3) << 3)) & 0xffff;
-+ } else if (4 == size) {
-+ *value = val;
-+ } else {
-+ pcie_error("Unknown size for config read operation!");
-+ BUG();
-+ }
++ if (1 == size) {
++ *value = (val >> ((where & 0x3) << 3)) & 0xff;
++ } else if (2 == size) {
++ *value = (val >> ((where & 0x3) << 3)) & 0xffff;
++ } else if (4 == size) {
++ *value = val;
++ } else {
++ pcie_error("Unknown size for config read operation!");
++ BUG();
++ }
+
-+ return PCIBIOS_SUCCESSFUL;
++ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *value)
++ int where, int size, u32 *value)
+{
-+ struct pcie_info *info = bus_to_info(bus->number);
-+ int ret;
++ struct pcie_info *info = bus_to_info(bus->number);
++ int ret;
+
-+ if (unlikely(!info)) {
-+ pcie_error(
-+ "%s:Cannot find corresponding controller for appointed device!", __func__);
-+ BUG();
-+ }
++ if (unlikely(!info)) {
++ pcie_error(
++ "%s:Cannot find corresponding controller for appointed device!", __func__);
++ BUG();
++ }
+
-+ if (bus->number == info->root_bus_nr) {
-+ ret = pcie_read_from_dbi(info, devfn, where, size, value);
-+ } else {
-+ ret = pcie_read_from_device(bus, devfn, where, size, value);
-+ }
++ if (bus->number == info->root_bus_nr) {
++ ret = pcie_read_from_dbi(info, devfn, where, size, value);
++ } else {
++ ret = pcie_read_from_device(bus, devfn, where, size, value);
++ }
+
-+ pcie_debug(PCIE_DBG_REG,
-+ "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
-+ bus->number & 0xff, devfn, where, size, *value);
++ pcie_debug(PCIE_DBG_REG,
++ "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
++ bus->number & 0xff, devfn, where, size, *value);
+
-+ return ret;
++ return ret;
+}
+
+static int pcie_write_to_device(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 value)
++ int where, int size, u32 value)
+{
-+ struct pcie_info *info = bus_to_info(bus->number);
-+ void __iomem *addr;
-+ unsigned int org;
-+ unsigned long flag;
++ struct pcie_info *info = bus_to_info(bus->number);
++ void __iomem *addr;
++ unsigned int org;
++ unsigned long flag;
+
-+ if (unlikely(!info)) {
-+ pcie_error(
-+ "%s:Cannot find corresponding controller for appointed device!", __func__);
-+ BUG();
-+ }
++ if (unlikely(!info)) {
++ pcie_error(
++ "%s:Cannot find corresponding controller for appointed device!", __func__);
++ BUG();
++ }
+
-+ if (!is_pcie_link_up(info)) {
-+ pcie_debug(PCIE_DBG_MODULE, "pcie %d not link up!",
-+ info->controller);
-+ return -1;
-+ }
++ if (!is_pcie_link_up(info)) {
++ pcie_debug(PCIE_DBG_MODULE, "pcie %d not link up!",
++ info->controller);
++ return -1;
++ }
+
-+ spin_lock_irqsave(&cw_lock, flag);
++ spin_lock_irqsave(&cw_lock, flag);
+
-+ pcie_read_from_device(bus, devfn, where, 4, &org);
++ pcie_read_from_device(bus, devfn, where, 4, &org);
+
-+ addr = (void __iomem *)to_pcie_address(bus, devfn, where);
++ addr = (void __iomem *)to_pcie_address(bus, devfn, where);
+
-+ if (size == 1) {
-+ org &= (~(0xff << ((where & 0x3) << 3)));
-+ org |= (value << ((where & 0x3) << 3));
-+ } else if (size == 2) {
-+ org &= (~(0xffff << ((where & 0x3) << 3)));
-+ org |= (value << ((where & 0x3) << 3));
-+ } else if (size == 4) {
-+ org = value;
-+ } else {
-+ pcie_error("Unknown size(%d) for read ops", size);
-+ BUG();
-+ }
-+ writel(org, addr);
++ if (size == 1) {
++ org &= (~(0xff << ((where & 0x3) << 3)));
++ org |= (value << ((where & 0x3) << 3));
++ } else if (size == 2) {
++ org &= (~(0xffff << ((where & 0x3) << 3)));
++ org |= (value << ((where & 0x3) << 3));
++ } else if (size == 4) {
++ org = value;
++ } else {
++ pcie_error("Unknown size(%d) for read ops", size);
++ BUG();
++ }
++ writel(org, addr);
+
-+ spin_unlock_irqrestore(&cw_lock, flag);
++ spin_unlock_irqrestore(&cw_lock, flag);
+
-+ return PCIBIOS_SUCCESSFUL;
++ return PCIBIOS_SUCCESSFUL;
+
+}
+
+static int pcie_write_to_dbi(struct pcie_info *info, unsigned int devfn,
-+ int where, int size, u32 value)
++ int where, int size, u32 value)
+{
-+ unsigned long flag;
-+ unsigned int org;
++ unsigned long flag;
++ unsigned int org;
+
-+ spin_lock_irqsave(&cw_lock, flag);
++ spin_lock_irqsave(&cw_lock, flag);
+
-+ if (pcie_read_from_dbi(info, devfn, where, 4, &org)) {
-+ pcie_error("Cannot read from dbi! 0x%x:0x%x:0x%x!",
-+ 0, devfn, where);
-+ spin_unlock_irqrestore(&cw_lock, flag);
-+ return -EIO;
-+ }
-+ if (size == 1) {
-+ org &= (~(0xff << ((where & 0x3) << 3)));
-+ org |= (value << ((where & 0x3) << 3));
-+ } else if (size == 2) {
-+ org &= (~(0xffff << ((where & 0x3) << 3)));
-+ org |= (value << ((where & 0x3) << 3));
-+ } else if (size == 4) {
-+ org = value;
-+ } else {
-+ pcie_error("Unknown size(%d) for read ops", size);
-+ BUG();
-+ }
-+ writel(org, ((void __iomem *)info->conf_base_addr + (where & (~0x3))));
++ if (pcie_read_from_dbi(info, devfn, where, 4, &org)) {
++ pcie_error("Cannot read from dbi! 0x%x:0x%x:0x%x!",
++ 0, devfn, where);
++ spin_unlock_irqrestore(&cw_lock, flag);
++ return -EIO;
++ }
++ if (size == 1) {
++ org &= (~(0xff << ((where & 0x3) << 3)));
++ org |= (value << ((where & 0x3) << 3));
++ } else if (size == 2) {
++ org &= (~(0xffff << ((where & 0x3) << 3)));
++ org |= (value << ((where & 0x3) << 3));
++ } else if (size == 4) {
++ org = value;
++ } else {
++ pcie_error("Unknown size(%d) for read ops", size);
++ BUG();
++ }
++ writel(org, ((void __iomem *)info->conf_base_addr + (where & (~0x3))));
+
-+ spin_unlock_irqrestore(&cw_lock, flag);
++ spin_unlock_irqrestore(&cw_lock, flag);
+
-+ return PCIBIOS_SUCCESSFUL;
++ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 value)
++ int where, int size, u32 value)
+{
-+ struct pcie_info *info = bus_to_info(bus->number);
++ struct pcie_info *info = bus_to_info(bus->number);
+
-+ pcie_debug(PCIE_DBG_REG,
-+ "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
-+ bus->number & 0xff, devfn, where, size, value);
++ pcie_debug(PCIE_DBG_REG,
++ "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
++ bus->number & 0xff, devfn, where, size, value);
+
-+ if (unlikely(!info)) {
-+ pcie_error(
-+ "%s:Cannot find corresponding controller for appointed device!", __func__);
-+ BUG();
-+ }
++ if (unlikely(!info)) {
++ pcie_error(
++ "%s:Cannot find corresponding controller for appointed device!", __func__);
++ BUG();
++ }
+
-+ if (bus->number == info->root_bus_nr) {
-+ return pcie_write_to_dbi(info, devfn, where, size, value);
-+ } else {
-+ return pcie_write_to_device(bus, devfn, where, size, value);
-+ }
++ if (bus->number == info->root_bus_nr) {
++ return pcie_write_to_dbi(info, devfn, where, size, value);
++ } else {
++ return pcie_write_to_device(bus, devfn, where, size, value);
++ }
+}
+
+static struct pci_ops pcie_ops = {
-+ .read = pcie_read_conf,
-+ .write = pcie_write_conf,
++ .read = pcie_read_conf,
++ .write = pcie_write_conf,
+};
+
+void pci_set_max_rd_req_size(const struct pci_bus *bus)
+{
-+ struct pci_dev *dev;
-+ struct pci_bus *child;
-+ int pos;
-+ unsigned short dev_contrl_reg_val = 0;
-+ unsigned int max_rd_req_size = 0;
++ struct pci_dev *dev = NULL;
++ struct pci_bus *child = NULL;
++ int pos;
++ unsigned short dev_contrl_reg_val = 0;
++ unsigned int max_rd_req_size = 0;
+
-+ list_for_each_entry(dev, &bus->devices, bus_list) {
++ list_for_each_entry(dev, &bus->devices, bus_list) {
+
-+ /* set device max read requset size*/
-+ pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-+ if (pos) {
-+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL,
-+ &dev_contrl_reg_val);
-+ max_rd_req_size = (dev_contrl_reg_val >> 12) & 0x7;
-+ if (max_rd_req_size > 0x0) {
-+ dev_contrl_reg_val &= ~(max_rd_req_size << 12);
-+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
-+ dev_contrl_reg_val);
-+ }
++ /* set device max read requset size*/
++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
++ if (pos) {
++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL,
++ &dev_contrl_reg_val);
++ max_rd_req_size = (dev_contrl_reg_val >> 12) & 0x7;
++ if (max_rd_req_size > 0x0) {
++ dev_contrl_reg_val &= ~(max_rd_req_size << 12);
++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
++ dev_contrl_reg_val);
++ }
+
-+ }
-+ }
++ }
++ }
+
-+ list_for_each_entry(dev, &bus->devices, bus_list) {
-+ BUG_ON(!dev->is_added);
-+ child = dev->subordinate;
-+ if (child) {
-+ pci_set_max_rd_req_size(child);
-+ }
-+ }
++ list_for_each_entry(dev, &bus->devices, bus_list) {
++ BUG_ON(!dev->is_added);
++ child = dev->subordinate;
++ if (child) {
++ pci_set_max_rd_req_size(child);
++ }
++ }
+}
+
+static struct hw_pci hipcie __initdata = {
-+ .nr_controllers = 1,
++ .nr_controllers = 1,
+};
+#ifdef CONFIG_ARM64
+
+static int pci_common_init(struct platform_device *pdev, struct hw_pci *hipcie)
+{
-+ struct device_node *dn = pdev->dev.of_node;
-+ struct pcie_info *info;
-+ struct pci_bus *bus;
-+ resource_size_t io_addr;
-+ int ret;
-+ int pcie_contrl;
-+ LIST_HEAD(res);
++ struct device_node *dn = pdev->dev.of_node;
++ struct pcie_info *info = NULL;
++ struct pci_bus *bus = NULL;
++ resource_size_t io_addr;
++ int ret;
++ int pcie_contrl;
++ LIST_HEAD(res);
+
-+ ret = of_property_read_u32(dn, "pcie_controller", &pcie_contrl);
-+ if (ret) {
-+ pr_err("%s:No pcie_controller found!\n", __func__);
-+ return -EINVAL;
-+ }
++ ret = of_property_read_u32(dn, "pcie_controller", &pcie_contrl);
++ if (ret) {
++ pr_err("%s:No pcie_controller found!\n", __func__);
++ return -EINVAL;
++ }
+
-+ ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &io_addr);
-+ if (ret) {
-+ return ret;
-+ }
++ ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &io_addr);
++ if (ret) {
++ return ret;
++ }
+
+
-+ bus = pci_create_root_bus(&pdev->dev, 0, &pcie_ops, hipcie, &res);
-+ if (!bus) {
-+ return -ENOMEM;
-+ }
++ bus = pci_create_root_bus(&pdev->dev, 0, &pcie_ops, hipcie, &res);
++ if (!bus) {
++ return -ENOMEM;
++ }
+
+#ifdef CONFIG_LIMIT_MAX_RD_REQ_SIZE
-+ pci_set_max_rd_req_size(bus);
++ pci_set_max_rd_req_size(bus);
+#endif
+
-+ pcie_info[pcie_contrl].root_bus_nr = bus->number;
-+ info = bus_to_info(bus->number);
-+ if (info != NULL) {
-+ __arch_config_iatu_tbl(info, NULL);
-+ }
++ pcie_info[pcie_contrl].root_bus_nr = bus->number;
++ info = bus_to_info(bus->number);
++ if (info != NULL) {
++ __arch_config_iatu_tbl(info, NULL);
++ }
+
-+ pci_scan_child_bus(bus);
-+ pci_assign_unassigned_bus_resources(bus);
-+ pci_bus_add_devices(bus);
++ pci_scan_child_bus(bus);
++ pci_assign_unassigned_bus_resources(bus);
++ pci_bus_add_devices(bus);
+
-+ platform_set_drvdata(pdev, hipcie);
++ platform_set_drvdata(pdev, hipcie);
+
-+ return 0;
++ return 0;
+}
+#else
+static int pci_common_init_bvt(struct platform_device *pdev, struct hw_pci *hipcie)
+{
-+ struct device_node *dn = pdev->dev.of_node;
-+ struct pcie_info *info;
-+ struct pci_bus *bus;
-+ resource_size_t io_addr;
-+ int ret;
-+ int bus_start;
-+ int pcie_contrl;
++ struct device_node *dn = pdev->dev.of_node;
++ struct pcie_info *info = NULL;
++ struct pci_bus *bus = NULL;
++ resource_size_t io_addr;
++ int ret;
++ int bus_start;
++ int pcie_contrl;
+
-+ LIST_HEAD(res);
++ LIST_HEAD(res);
+
-+ ret = of_property_read_u32(dn, "pcie_controller", &pcie_contrl);
-+ if (ret) {
-+ pr_err("%s:No pcie_controller found!\n", __func__);
-+ return -EINVAL;
-+ }
++ ret = of_property_read_u32(dn, "pcie_controller", &pcie_contrl);
++ if (ret) {
++ pr_err("%s:No pcie_controller found!\n", __func__);
++ return -EINVAL;
++ }
+
-+ if (pcie_contrl == 0) {
-+ bus_start = 0;
-+ } else {
-+ bus_start = 2;
-+ }
++ if (pcie_contrl == 0) {
++ bus_start = 0;
++ } else {
++ bus_start = 2;
++ }
+
-+ ret = of_pci_get_host_bridge_resources(dn, bus_start, 0xff, &res, &io_addr);
-+ if (ret) {
-+ return ret;
-+ }
++ ret = of_pci_get_host_bridge_resources(dn, bus_start, 0xff, &res, &io_addr);
++ if (ret) {
++ return ret;
++ }
+
-+ bus = pci_create_root_bus(&pdev->dev, bus_start, &pcie_ops, hipcie, &res);
-+ if (!bus) {
-+ return -ENOMEM;
-+ }
++ bus = pci_create_root_bus(&pdev->dev, bus_start, &pcie_ops, hipcie, &res);
++ if (!bus) {
++ return -ENOMEM;
++ }
+
+#ifdef CONFIG_LIMIT_MAX_RD_REQ_SIZE
-+ pci_set_max_rd_req_size(bus);
++ pci_set_max_rd_req_size(bus);
+#endif
+
-+ pcie_info[pcie_contrl].root_bus_nr = bus->number;
-+ info = bus_to_info(bus->number);
-+ if (info != NULL) {
-+ __arch_config_iatu_tbl(info, NULL);
-+ }
++ pcie_info[pcie_contrl].root_bus_nr = bus->number;
++ info = bus_to_info(bus->number);
++ if (info != NULL) {
++ __arch_config_iatu_tbl(info, NULL);
++ }
+
-+ pci_scan_child_bus(bus);
-+ pci_assign_unassigned_bus_resources(bus);
-+ pci_bus_add_devices(bus);
++ pci_scan_child_bus(bus);
++ pci_assign_unassigned_bus_resources(bus);
++ pci_bus_add_devices(bus);
+
-+ platform_set_drvdata(pdev, hipcie);
++ platform_set_drvdata(pdev, hipcie);
+
-+ return 0;
++ return 0;
+
+}
+#endif
+
+static int __init pcie_init(struct platform_device *pdev)
+{
-+ int err;
++ int err;
+
-+ g_of_node = pdev->dev.of_node;
-+ if (!g_of_node) {
-+ pr_err("get node from dts failed! controller:%d\n", pcie_controllers_nr);
-+ return -EIO;
-+ }
++ g_of_node = pdev->dev.of_node;
++ if (!g_of_node) {
++ pr_err("get node from dts failed! controller:%d\n", pcie_controllers_nr);
++ return -EIO;
++ }
+
-+ err = of_property_read_u32(g_of_node, "pcie_controller", &pcie_controllers_nr);
-+ if (err) {
-+ pr_err("%s:No pcie_controller found!\n", __func__);
-+ return -EINVAL;
-+ }
++ err = of_property_read_u32(g_of_node, "pcie_controller", &pcie_controllers_nr);
++ if (err) {
++ pr_err("%s:No pcie_controller found!\n", __func__);
++ return -EINVAL;
++ }
+
-+ if (__arch_pcie_info_setup(pcie_info, &pcie_controllers_nr)) {
-+ return -EIO;
-+ }
++ if (__arch_pcie_info_setup(pcie_info, &pcie_controllers_nr)) {
++ return -EIO;
++ }
+
-+ if (__arch_pcie_sys_init(pcie_info)) {
-+ goto pcie_init_err;
-+ }
-+ hipcie.nr_controllers = pcie_controllers_nr;
-+ pr_err("Number of PCIe controllers: %d\n",
-+ hipcie.nr_controllers);
++ if (__arch_pcie_sys_init(pcie_info)) {
++ goto pcie_init_err;
++ }
++ hipcie.nr_controllers = pcie_controllers_nr;
++ pr_err("Number of PCIe controllers: %d\n",
++ hipcie.nr_controllers);
+
+#ifdef CONFIG_ARM64
-+ pci_common_init(pdev, &hipcie);
++ pci_common_init(pdev, &hipcie);
+#else
-+ pci_common_init_bvt(pdev, &hipcie);
++ pci_common_init_bvt(pdev, &hipcie);
+#endif
-+ return 0;
++ return 0;
+pcie_init_err:
-+ __arch_pcie_info_release(pcie_info);
++ __arch_pcie_info_release(pcie_info);
+
-+ return -EIO;
++ return -EIO;
+}
+
+static int __exit pcie_uinit(struct platform_device *pdev)
+{
-+ __arch_pcie_info_release(pcie_info);
-+ return 0;
++ __arch_pcie_info_release(pcie_info);
++ return 0;
+}
+
+#include <linux/platform_device.h>
@@ -322976,30 +391265,30 @@ index 0000000..4091716
+
+int hisi_pcie_plat_driver_probe(struct platform_device *pdev)
+{
-+ return 0;
++ return 0;
+}
+int hisi_pcie_plat_driver_remove(struct platform_device *pdev)
+{
-+ return 0;
++ return 0;
+}
+
+#ifdef CONFIG_PM
+int hisi_pcie_plat_driver_suspend(struct device *dev)
+{
-+ __arch_pcie_sys_exit();
-+ return 0;
++ __arch_pcie_sys_exit();
++ return 0;
+}
+
+int hisi_pcie_plat_driver_resume(struct device *dev)
+{
-+ return __arch_pcie_sys_init(pcie_info);
++ return __arch_pcie_sys_init(pcie_info);
+}
+
+const struct dev_pm_ops hisi_pcie_pm_ops = {
-+ .suspend = NULL,
-+ .suspend_noirq = hisi_pcie_plat_driver_suspend,
-+ .resume = NULL,
-+ .resume_noirq = hisi_pcie_plat_driver_resume
++ .suspend = NULL,
++ .suspend_noirq = hisi_pcie_plat_driver_suspend,
++ .resume = NULL,
++ .resume_noirq = hisi_pcie_plat_driver_resume
+};
+
+#define HISI_PCIE_PM_OPS (&hisi_pcie_pm_ops)
@@ -323011,17 +391300,17 @@ index 0000000..4091716
+
+
+static const struct of_device_id hisi_pcie_match_table[] = {
-+ {.compatible = "hisilicon,hisi-pcie",},
-+ {},
++ {.compatible = "hisilicon,hisi-pcie",},
++ {},
+};
+
+static struct platform_driver hisi_pcie_driver = {
-+ .driver = {
-+ .name = "hisi-pcie",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(hisi_pcie_match_table),
-+ },
-+ .probe = pcie_init,
++ .driver = {
++ .name = "hisi-pcie",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(hisi_pcie_match_table),
++ },
++ .probe = pcie_init,
+};
+module_platform_driver(hisi_pcie_driver);
+
@@ -323029,7 +391318,7 @@ index 0000000..4091716
+MODULE_LICENSE("GPL");
diff --git a/drivers/pci/hipcie/pcie_hi3519av100.c b/drivers/pci/hipcie/pcie_hi3519av100.c
new file mode 100644
-index 0000000..241dd5d
+index 0000000..211eca2
--- /dev/null
+++ b/drivers/pci/hipcie/pcie_hi3519av100.c
@@ -0,0 +1,284 @@
@@ -323059,56 +391348,56 @@ index 0000000..241dd5d
+static void __arch_pcie_info_release(struct pcie_info *info);
+
+struct pcie_iatu iatu_table[] = {
-+ {
-+ .viewport = 0,
-+ .region_ctrl_1 = 0x00000004,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE_EP_CONF_BASE + (1 << 20),
-+ .ubar = 0x0,
-+ .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1,
-+ .ltar = 0x01000000,
-+ .utar = 0x00000000,
-+ },
-+ {
-+ .viewport = 1,
-+ .region_ctrl_1 = 0x00000005,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE_EP_CONF_BASE + (2 << 20),
-+ .ubar = 0x0,
-+ .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1),
-+ .ltar = 0x02000000,
-+ .utar = 0x00000000,
-+ },
++ {
++ .viewport = 0,
++ .region_ctrl_1 = 0x00000004,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE_EP_CONF_BASE + (1 << 20),
++ .ubar = 0x0,
++ .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1,
++ .ltar = 0x01000000,
++ .utar = 0x00000000,
++ },
++ {
++ .viewport = 1,
++ .region_ctrl_1 = 0x00000005,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE_EP_CONF_BASE + (2 << 20),
++ .ubar = 0x0,
++ .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1),
++ .ltar = 0x02000000,
++ .utar = 0x00000000,
++ },
+};
+
+static void __arch_config_iatu_tbl(struct pcie_info *info,
-+ struct pci_sys_data *sys)
++ struct pci_sys_data *sys)
+{
-+ int i;
-+ void __iomem *config_base = (void __iomem *)info->conf_base_addr;
-+ struct pcie_iatu *ptable = iatu_table;
-+ int table_size = ARRAY_SIZE(iatu_table);
++ int i;
++ void __iomem *config_base = (void __iomem *)info->conf_base_addr;
++ struct pcie_iatu *ptable = iatu_table;
++ int table_size = ARRAY_SIZE(iatu_table);
+
-+ for (i = 0; i < table_size; i++) {
-+ writel((ptable + i)->viewport, config_base + 0x900);
-+ writel((ptable + i)->lbar, config_base + 0x90c);
-+ writel((ptable + i)->ubar, config_base + 0x910);
-+ writel((ptable + i)->lar, config_base + 0x914);
-+ writel((ptable + i)->ltar, config_base + 0x918);
-+ writel((ptable + i)->utar, config_base + 0x91c);
-+ writel((ptable + i)->region_ctrl_1, config_base + 0x904);
-+ writel((ptable + i)->region_ctrl_2, config_base + 0x908);
-+ }
++ for (i = 0; i < table_size; i++) {
++ writel((ptable + i)->viewport, config_base + 0x900);
++ writel((ptable + i)->lbar, config_base + 0x90c);
++ writel((ptable + i)->ubar, config_base + 0x910);
++ writel((ptable + i)->lar, config_base + 0x914);
++ writel((ptable + i)->ltar, config_base + 0x918);
++ writel((ptable + i)->utar, config_base + 0x91c);
++ writel((ptable + i)->region_ctrl_1, config_base + 0x904);
++ writel((ptable + i)->region_ctrl_2, config_base + 0x908);
++ }
+
+}
+
+static inline int __arch_check_pcie_link(struct pcie_info *info)
+{
-+ int val;
++ int val;
+
-+ val = readl(dbi_base + PCIE_SYS_STATE0);
-+ return ((val & (1 << PCIE_XMLH_LINK_UP))
-+ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
++ val = readl(dbi_base + PCIE_SYS_STATE0);
++ return ((val & (1 << PCIE_XMLH_LINK_UP))
++ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
+}
+
+/*
@@ -323116,206 +391405,206 @@ index 0000000..241dd5d
+ */
+static int __arch_pcie_info_setup(struct pcie_info *info, int *controllers_nr)
+{
-+ unsigned int pcie_mem_size;
-+ unsigned int pcie_cfg_size;
-+ unsigned int pcie_dbi_base;
-+ unsigned int pcie_ep_conf_base;
-+ unsigned int pcie_contrl;
-+ int err;
++ unsigned int pcie_mem_size;
++ unsigned int pcie_cfg_size;
++ unsigned int pcie_dbi_base;
++ unsigned int pcie_ep_conf_base;
++ unsigned int pcie_contrl;
++ int err;
+
-+ /* Get pcie deice memory size */
-+ err = of_property_read_u32(g_of_node, "dev_mem_size", &pcie_mem_size);
-+ if (err) {
-+ pcie_error("No dev_mem_size found!");
-+ return -EINVAL;
-+ }
++ /* Get pcie deice memory size */
++ err = of_property_read_u32(g_of_node, "dev_mem_size", &pcie_mem_size);
++ if (err) {
++ pcie_error("No dev_mem_size found!");
++ return -EINVAL;
++ }
+
-+ /* Get pcie config space size*/
-+ err = of_property_read_u32(g_of_node, "dev_conf_size", &pcie_cfg_size);
-+ if (err) {
-+ pcie_error("No dev_conf_size founcd!");
-+ return -EINVAL;
-+ }
++ /* Get pcie config space size*/
++ err = of_property_read_u32(g_of_node, "dev_conf_size", &pcie_cfg_size);
++ if (err) {
++ pcie_error("No dev_conf_size founcd!");
++ return -EINVAL;
++ }
+
-+ /* Get pcie dib base address */
-+ err = of_property_read_u32(g_of_node, "pcie_dbi_base", &pcie_dbi_base);
-+ if (err) {
-+ pcie_error("No pcie_dbi_base found!");
-+ return -EINVAL;
-+ }
++ /* Get pcie dib base address */
++ err = of_property_read_u32(g_of_node, "pcie_dbi_base", &pcie_dbi_base);
++ if (err) {
++ pcie_error("No pcie_dbi_base found!");
++ return -EINVAL;
++ }
+
-+ /* Get pcie device config base address */
-+ err = of_property_read_u32(g_of_node, "ep_conf_base", &pcie_ep_conf_base);
-+ if (err) {
-+ pcie_error("No ep_conf_base found!");
-+ return -EINVAL;
-+ }
++ /* Get pcie device config base address */
++ err = of_property_read_u32(g_of_node, "ep_conf_base", &pcie_ep_conf_base);
++ if (err) {
++ pcie_error("No ep_conf_base found!");
++ return -EINVAL;
++ }
+
-+ if ((pcie_mem_size > __128MB__) || (pcie_cfg_size > __128MB__)) {
-+ pcie_error(
-+ "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
-+ pcie_mem_size, pcie_cfg_size);
-+ return -EINVAL;
-+ }
++ if ((pcie_mem_size > __128MB__) || (pcie_cfg_size > __128MB__)) {
++ pcie_error(
++ "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
++ pcie_mem_size, pcie_cfg_size);
++ return -EINVAL;
++ }
+
-+ err = of_property_read_u32(g_of_node, "pcie_controller", &pcie_contrl);
-+ if (err) {
-+ pcie_error("No pcie_controller found!");
-+ return -EINVAL;
-+ }
++ err = of_property_read_u32(g_of_node, "pcie_controller", &pcie_contrl);
++ if (err) {
++ pcie_error("No pcie_controller found!");
++ return -EINVAL;
++ }
+
-+ info->controller = pcie_contrl;
++ info->controller = pcie_contrl;
+
-+ /* RC configuration space */
-+ info->conf_base_addr = (unsigned int)ioremap_nocache(pcie_dbi_base,
-+ __8KB__);
-+ if (!info->conf_base_addr) {
-+ pcie_error("Address mapping for RC dbi failed!");
-+ return -EIO;
-+ }
++ /* RC configuration space */
++ info->conf_base_addr = (unsigned int)ioremap_nocache(pcie_dbi_base,
++ __8KB__);
++ if (!info->conf_base_addr) {
++ pcie_error("Address mapping for RC dbi failed!");
++ return -EIO;
++ }
+
-+ /* Configuration space for all EPs */
-+ info->base_addr = (unsigned int)ioremap_nocache(pcie_ep_conf_base,
-+ pcie_cfg_size);
-+ if (!info->base_addr) {
-+ iounmap((void *)info->conf_base_addr);
-+ pcie_error("Address mapping for EPs cfg failed!");
-+ return -EIO;
-+ }
++ /* Configuration space for all EPs */
++ info->base_addr = (unsigned int)ioremap_nocache(pcie_ep_conf_base,
++ pcie_cfg_size);
++ if (!info->base_addr) {
++ iounmap((void *)info->conf_base_addr);
++ pcie_error("Address mapping for EPs cfg failed!");
++ return -EIO;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static void __arch_pcie_info_release(struct pcie_info *info)
+{
-+ if (info->base_addr) {
-+ iounmap((void *)info->base_addr);
-+ }
++ if (info->base_addr) {
++ iounmap((void *)info->base_addr);
++ }
+
-+ if (info->conf_base_addr) {
-+ iounmap((void *)info->conf_base_addr);
-+ }
++ if (info->conf_base_addr) {
++ iounmap((void *)info->conf_base_addr);
++ }
+}
+
+static int __arch_pcie_sys_init(struct pcie_info *info)
+{
-+ unsigned int val;
-+ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
++ unsigned int val;
++ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
+
-+ dbi_base = (void *)info->conf_base_addr;
++ dbi_base = (void *)info->conf_base_addr;
+
-+ /*
-+ * Disable PCIE
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, dbi_base + PCIE_SYS_CTRL7);
++ /*
++ * Disable PCIE
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, dbi_base + PCIE_SYS_CTRL7);
+
-+ /*
-+ * Reset
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val |= (1 << PCIE_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Reset
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val |= (1 << PCIE_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG99);
+
-+ /*
-+ * Retreat from the reset state
-+ */
-+ udelay(500);
-+ val = readl(crg_base + PERI_CRG99);
-+ val &= ~(1 << PCIE_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG99);
-+ mdelay(10);
++ /*
++ * Retreat from the reset state
++ */
++ udelay(500);
++ val = readl(crg_base + PERI_CRG99);
++ val &= ~(1 << PCIE_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG99);
++ mdelay(10);
+
+
-+ /*
-+ * PCIE RC work mode
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL0);
-+ val &= (~(0xf << PCIE_DEVICE_TYPE));
-+ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
-+ writel(val, dbi_base + PCIE_SYS_CTRL0);
++ /*
++ * PCIE RC work mode
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL0);
++ val &= (~(0xf << PCIE_DEVICE_TYPE));
++ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
++ writel(val, dbi_base + PCIE_SYS_CTRL0);
+
-+ /*
-+ * Enable clk
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val |= ((1 << PCIE_X2_BUS_CKEN)
-+ | (1 << PCIE_X2_SYS_CKEN)
-+ | (1 << PCIE_X2_PIPE_CKEN)
-+ | (1 << PCIE_X2_AUX_CKEN));
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Enable clk
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val |= ((1 << PCIE_X2_BUS_CKEN)
++ | (1 << PCIE_X2_SYS_CKEN)
++ | (1 << PCIE_X2_PIPE_CKEN)
++ | (1 << PCIE_X2_AUX_CKEN));
++ writel(val, crg_base + PERI_CRG99);
+
-+ mdelay(10);
++ mdelay(10);
+
-+ /*
-+ * Set PCIE controller class code to be PCI-PCI bridge device
-+ */
-+ val = readl(dbi_base + PCI_CLASS_REVISION);
-+ val &= ~(0xffffff00);
-+ val |= (0x60400 << 8);
-+ writel(val, dbi_base + PCI_CLASS_REVISION);
-+ udelay(1000);
++ /*
++ * Set PCIE controller class code to be PCI-PCI bridge device
++ */
++ val = readl(dbi_base + PCI_CLASS_REVISION);
++ val &= ~(0xffffff00);
++ val |= (0x60400 << 8);
++ writel(val, dbi_base + PCI_CLASS_REVISION);
++ udelay(1000);
+
+
-+ /*
-+ * Enable controller
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL7);
-+ val |= (1 << PCIE_APP_LTSSM_ENBALE);
-+ writel(val, dbi_base + PCIE_SYS_CTRL7);
-+ udelay(1000);
++ /*
++ * Enable controller
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL7);
++ val |= (1 << PCIE_APP_LTSSM_ENBALE);
++ writel(val, dbi_base + PCIE_SYS_CTRL7);
++ udelay(1000);
+
-+ val = readl(dbi_base + PCI_COMMAND);
-+ val |= 7;
-+ writel(val, dbi_base + PCI_COMMAND);
++ val = readl(dbi_base + PCI_COMMAND);
++ val |= 7;
++ writel(val, dbi_base + PCI_COMMAND);
+
-+ /* set pcie to gen 1*/
++ /* set pcie to gen 1*/
+#ifdef PCIE_GEN1_ENABLE
-+ writel(0x1, dbi_base + 0x8BC);
-+ val = readl(dbi_base + 0x7C);
-+ val = ((val >> 4) << 4) | 0x1;
-+ writel(val, dbi_base + 0x7C);
++ writel(0x1, dbi_base + 0x8BC);
++ val = readl(dbi_base + 0x7C);
++ val = ((val >> 4) << 4) | 0x1;
++ writel(val, dbi_base + 0x7C);
+#endif
+
-+ iounmap(crg_base);
++ iounmap(crg_base);
+
-+ return 0;
++ return 0;
+}
+
+static void __arch_pcie_sys_exit(void)
+{
-+ unsigned int val;
-+ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
-+ /*
-+ * Disable PCIE
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, dbi_base + PCIE_SYS_CTRL7);
++ unsigned int val;
++ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
++ /*
++ * Disable PCIE
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, dbi_base + PCIE_SYS_CTRL7);
+
-+ /*
-+ * Reset
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val |= (1 << PCIE_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Reset
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val |= (1 << PCIE_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG99);
+
-+ udelay(1000);
++ udelay(1000);
+
-+ /*
-+ * Disable clk
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val &= (~(1 << PCIE_X2_AUX_CKEN));
-+ val &= (~(1 << PCIE_X2_PIPE_CKEN));
-+ val &= (~(1 << PCIE_X2_SYS_CKEN));
-+ val &= (~(1 << PCIE_X2_BUS_CKEN));
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Disable clk
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val &= (~(1 << PCIE_X2_AUX_CKEN));
++ val &= (~(1 << PCIE_X2_PIPE_CKEN));
++ val &= (~(1 << PCIE_X2_SYS_CKEN));
++ val &= (~(1 << PCIE_X2_BUS_CKEN));
++ writel(val, crg_base + PERI_CRG99);
+
-+ iounmap(crg_base);
++ iounmap(crg_base);
+
-+ udelay(1000);
++ udelay(1000);
+}
diff --git a/drivers/pci/hipcie/pcie_hi3519av100.h b/drivers/pci/hipcie/pcie_hi3519av100.h
new file mode 100644
@@ -323389,7 +391678,7 @@ index 0000000..2803f45
+#endif
diff --git a/drivers/pci/hipcie/pcie_hi3531a.c b/drivers/pci/hipcie/pcie_hi3531a.c
new file mode 100644
-index 0000000..1867d24
+index 0000000..d73b4ca
--- /dev/null
+++ b/drivers/pci/hipcie/pcie_hi3531a.c
@@ -0,0 +1,659 @@
@@ -323418,109 +391707,109 @@ index 0000000..1867d24
+static void __arch_pcie_info_release(struct pcie_info *info);
+
+struct pcie_iatu pcie0_iatu_table[] = {
-+ {
-+ .viewport = 0,
-+ .region_ctrl_1 = 0x00000004,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE0_EP_CONF_BASE + (1 << 20),
-+ .ubar = 0x0,
-+ .lar = PCIE0_EP_CONF_BASE + (2 << 20) - 1,
-+ .ltar = 0x01000000,
-+ .utar = 0x00000000,
-+ },
-+ {
-+ .viewport = 1,
-+ .region_ctrl_1 = 0x00000005,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE0_EP_CONF_BASE + (2 << 20),
-+ .ubar = 0x0,
-+ .lar = PCIE0_EP_CONF_BASE + (__128MB__ - 1),
-+ .ltar = 0x02000000,
-+ .utar = 0x00000000,
-+ },
++ {
++ .viewport = 0,
++ .region_ctrl_1 = 0x00000004,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE0_EP_CONF_BASE + (1 << 20),
++ .ubar = 0x0,
++ .lar = PCIE0_EP_CONF_BASE + (2 << 20) - 1,
++ .ltar = 0x01000000,
++ .utar = 0x00000000,
++ },
++ {
++ .viewport = 1,
++ .region_ctrl_1 = 0x00000005,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE0_EP_CONF_BASE + (2 << 20),
++ .ubar = 0x0,
++ .lar = PCIE0_EP_CONF_BASE + (__128MB__ - 1),
++ .ltar = 0x02000000,
++ .utar = 0x00000000,
++ },
+};
+
+struct pcie_iatu pcie1_iatu_table[] = {
-+ {
-+ .viewport = 0,
-+ .region_ctrl_1 = 0x00000004,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE1_EP_CONF_BASE,
-+ .ubar = 0x0,
-+ .lar = PCIE1_EP_CONF_BASE + (1 << 20) - 1,
-+ .ltar = 0x01000000,
-+ .utar = 0x00000000,
-+ },
-+ {
-+ .viewport = 1,
-+ .region_ctrl_1 = 0x00000005,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE1_EP_CONF_BASE,
-+ .ubar = 0x0,
-+ .lar = PCIE1_EP_CONF_BASE + (__128MB__ - 1),
-+ .ltar = 0x02000000,
-+ .utar = 0x00000000,
-+ },
++ {
++ .viewport = 0,
++ .region_ctrl_1 = 0x00000004,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE1_EP_CONF_BASE,
++ .ubar = 0x0,
++ .lar = PCIE1_EP_CONF_BASE + (1 << 20) - 1,
++ .ltar = 0x01000000,
++ .utar = 0x00000000,
++ },
++ {
++ .viewport = 1,
++ .region_ctrl_1 = 0x00000005,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE1_EP_CONF_BASE,
++ .ubar = 0x0,
++ .lar = PCIE1_EP_CONF_BASE + (__128MB__ - 1),
++ .ltar = 0x02000000,
++ .utar = 0x00000000,
++ },
+};
+
+static void __arch_config_iatu_tbl(struct pcie_info *info,
-+ struct pci_sys_data *sys)
++ struct pci_sys_data *sys)
+{
-+ int i;
-+ void __iomem *config_base;
-+ struct pcie_iatu *ptable;
-+ int table_size;
-+ unsigned int ctl1_lbar_offset;
++ int i;
++ void __iomem *config_base;
++ struct pcie_iatu *ptable = NULL;
++ int table_size;
++ unsigned int ctl1_lbar_offset;
+
-+ config_base = (void __iomem *)info->conf_base_addr;
-+ if (pcie_controller_0 == info->controller) {
-+ ptable = pcie0_iatu_table;
-+ table_size = ARRAY_SIZE(pcie0_iatu_table);
-+ }
++ config_base = (void __iomem *)info->conf_base_addr;
++ if (pcie_controller_0 == info->controller) {
++ ptable = pcie0_iatu_table;
++ table_size = ARRAY_SIZE(pcie0_iatu_table);
++ }
+
-+ if (pcie_controller_1 == info->controller) {
-+ ptable = pcie1_iatu_table;
-+ table_size = ARRAY_SIZE(pcie1_iatu_table);
++ if (pcie_controller_1 == info->controller) {
++ ptable = pcie1_iatu_table;
++ table_size = ARRAY_SIZE(pcie1_iatu_table);
+
+
-+ ctl1_lbar_offset = (info->root_bus_nr + 1) << 20;
-+ ptable->lbar |= ctl1_lbar_offset;
-+ ptable->lar |= ctl1_lbar_offset;
++ ctl1_lbar_offset = (info->root_bus_nr + 1) << 20;
++ ptable->lbar |= ctl1_lbar_offset;
++ ptable->lar |= ctl1_lbar_offset;
+
-+ ctl1_lbar_offset = (info->root_bus_nr + 2) << 20;
-+ (ptable + 1)->lbar |= ctl1_lbar_offset;
-+ }
++ ctl1_lbar_offset = (info->root_bus_nr + 2) << 20;
++ (ptable + 1)->lbar |= ctl1_lbar_offset;
++ }
+
-+ for (i = 0; i < table_size; i++) {
-+ writel((ptable + i)->viewport, config_base + 0x900);
-+ writel((ptable + i)->lbar, config_base + 0x90c);
-+ writel((ptable + i)->ubar, config_base + 0x910);
-+ writel((ptable + i)->lar, config_base + 0x914);
-+ writel((ptable + i)->ltar, config_base + 0x918);
-+ writel((ptable + i)->utar, config_base + 0x91c);
-+ writel((ptable + i)->region_ctrl_1, config_base + 0x904);
-+ writel((ptable + i)->region_ctrl_2, config_base + 0x908);
-+ }
++ for (i = 0; i < table_size; i++) {
++ writel((ptable + i)->viewport, config_base + 0x900);
++ writel((ptable + i)->lbar, config_base + 0x90c);
++ writel((ptable + i)->ubar, config_base + 0x910);
++ writel((ptable + i)->lar, config_base + 0x914);
++ writel((ptable + i)->ltar, config_base + 0x918);
++ writel((ptable + i)->utar, config_base + 0x91c);
++ writel((ptable + i)->region_ctrl_1, config_base + 0x904);
++ writel((ptable + i)->region_ctrl_2, config_base + 0x908);
++ }
+
+}
+
+static inline int __arch_check_pcie_link(struct pcie_info *info)
+{
-+ int val;
++ int val;
+
-+ if (pcie_controller_0 == info->controller) {
-+ val = readl(misc_ctrl_virt + PCIE0_SYS_STATE0);
-+ return ((val & (1 << PCIE_XMLH_LINK_UP))
-+ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
-+ }
++ if (pcie_controller_0 == info->controller) {
++ val = readl(misc_ctrl_virt + PCIE0_SYS_STATE0);
++ return ((val & (1 << PCIE_XMLH_LINK_UP))
++ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
++ }
+
-+ if (pcie_controller_1 == info->controller) {
-+ val = readl(misc_ctrl_virt + PCIE1_SYS_STATE0);
-+ return ((val & (1 << PCIE_XMLH_LINK_UP))
-+ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
-+ }
++ if (pcie_controller_1 == info->controller) {
++ val = readl(misc_ctrl_virt + PCIE1_SYS_STATE0);
++ return ((val & (1 << PCIE_XMLH_LINK_UP))
++ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
++ }
+
-+ return 0;
++ return 0;
+}
+
+/*
@@ -323528,528 +391817,528 @@ index 0000000..1867d24
+ */
+static int __arch_pcie_info_set(struct pcie_info *info, int controller)
+{
-+ unsigned int pcie_mem_size;
-+ unsigned int pcie_cfg_size;
-+ unsigned int pcie_dbi_base;
-+ unsigned int pcie_ep_conf_base;
-+ unsigned int pcie_contrl;
++ unsigned int pcie_mem_size;
++ unsigned int pcie_cfg_size;
++ unsigned int pcie_dbi_base;
++ unsigned int pcie_ep_conf_base;
++ unsigned int pcie_contrl;
+
-+ /* Get pcie deice memory size */
-+ of_property_read_u32(g_of_node, "dev_mem_size", &pcie_mem_size);
++ /* Get pcie deice memory size */
++ of_property_read_u32(g_of_node, "dev_mem_size", &pcie_mem_size);
+
-+ /* Get pcie config space size*/
-+ of_property_read_u32(g_of_node, "dev_conf_size", &pcie_cfg_size);
++ /* Get pcie config space size*/
++ of_property_read_u32(g_of_node, "dev_conf_size", &pcie_cfg_size);
+
-+ /* Get pcie dib base address */
-+ of_property_read_u32(g_of_node, "pcie_dbi_base", &pcie_dbi_base);
++ /* Get pcie dib base address */
++ of_property_read_u32(g_of_node, "pcie_dbi_base", &pcie_dbi_base);
+
-+ /* Get pcie device config base address */
-+ of_property_read_u32(g_of_node, "ep_conf_base", &pcie_ep_conf_base);
++ /* Get pcie device config base address */
++ of_property_read_u32(g_of_node, "ep_conf_base", &pcie_ep_conf_base);
+
-+ if ((pcie_mem_size > __128MB__) || (pcie_cfg_size > __128MB__)) {
-+ pcie_error(
-+ "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
-+ pcie_mem_size, pcie_cfg_size);
-+ return -EINVAL;
-+ }
++ if ((pcie_mem_size > __128MB__) || (pcie_cfg_size > __128MB__)) {
++ pcie_error(
++ "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
++ pcie_mem_size, pcie_cfg_size);
++ return -EINVAL;
++ }
+
-+ of_property_read_u32(g_of_node, "pcie_controller", &pcie_contrl);
-+ info->controller = pcie_contrl;
++ of_property_read_u32(g_of_node, "pcie_controller", &pcie_contrl);
++ info->controller = pcie_contrl;
+
-+ /* RC configuration space */
-+ info->conf_base_addr = (unsigned int)ioremap_nocache(pcie_dbi_base,
-+ __4KB__);
-+ if (!info->conf_base_addr) {
-+ pcie_error("Address mapping for RC dbi failed!");
-+ return -EIO;
-+ }
++ /* RC configuration space */
++ info->conf_base_addr = (unsigned int)ioremap_nocache(pcie_dbi_base,
++ __4KB__);
++ if (!info->conf_base_addr) {
++ pcie_error("Address mapping for RC dbi failed!");
++ return -EIO;
++ }
+
-+ /* Configuration space for all EPs */
-+ info->base_addr = (unsigned int)ioremap_nocache(pcie_ep_conf_base,
-+ pcie_cfg_size);
-+ if (!info->base_addr) {
-+ iounmap((void *)info->conf_base_addr);
-+ pcie_error("Address mapping for EPs cfg failed!");
-+ return -EIO;
-+ }
++ /* Configuration space for all EPs */
++ info->base_addr = (unsigned int)ioremap_nocache(pcie_ep_conf_base,
++ pcie_cfg_size);
++ if (!info->base_addr) {
++ iounmap((void *)info->conf_base_addr);
++ pcie_error("Address mapping for EPs cfg failed!");
++ return -EIO;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static void __arch_pcie_info_clr(struct pcie_info *info)
+{
-+ if (info->base_addr) {
-+ iounmap((void *)info->base_addr);
-+ }
++ if (info->base_addr) {
++ iounmap((void *)info->base_addr);
++ }
+
-+ if (info->conf_base_addr) {
-+ iounmap((void *)info->conf_base_addr);
-+ }
++ if (info->conf_base_addr) {
++ iounmap((void *)info->conf_base_addr);
++ }
+}
+
+static int __arch_get_port_nr(void)
+{
-+ unsigned int val, mode;
-+ int nr;
++ unsigned int val, mode;
++ int nr;
+
-+ val = readl((void *)PCIE_SYS_STAT);
-+ mode = (val >> 12) & 0xf;
-+ switch (mode) {
-+ case 0x1:
-+ case 0x2:
-+ case 0x9:
-+ case 0xa:
-+ nr = 1;
-+ break;
++ val = readl((void *)PCIE_SYS_STAT);
++ mode = (val >> 12) & 0xf;
++ switch (mode) {
++ case 0x1:
++ case 0x2:
++ case 0x9:
++ case 0xa:
++ nr = 1;
++ break;
+
-+ case 0x3:
-+ case 0x4:
-+ case 0xb:
-+ case 0xc:
-+ nr = 2;
-+ break;
++ case 0x3:
++ case 0x4:
++ case 0xb:
++ case 0xc:
++ nr = 2;
++ break;
+
-+ default:
-+ nr = 0;
-+ break;
-+ }
++ default:
++ nr = 0;
++ break;
++ }
+
-+ return nr;
++ return nr;
+}
+
+static int __arch_pcie_info_setup(struct pcie_info *info, int *controllers_nr)
+{
-+ int nr;
++ int nr;
+
-+ misc_ctrl_virt = (void *)IO_ADDRESS(MISC_CTRL_BASE);
++ misc_ctrl_virt = (void *)IO_ADDRESS(MISC_CTRL_BASE);
+
-+ nr = __arch_get_port_nr();
-+ if (!nr) {
-+ pr_err("Pcie port number: 0\n");
-+ return -EINVAL;
-+ }
++ nr = __arch_get_port_nr();
++ if (!nr) {
++ pr_err("Pcie port number: 0\n");
++ return -EINVAL;
++ }
+
-+ /* If only one pcie, it couldn't be pcie1, so don't init pcie1 */
-+ if (nr == 1 && *controllers_nr == 1) {
-+ return -EINVAL;
-+ }
++ /* If only one pcie, it couldn't be pcie1, so don't init pcie1 */
++ if (nr == 1 && *controllers_nr == 1) {
++ return -EINVAL;
++ }
+
-+ if (__arch_pcie_info_set(&info[*controllers_nr], *controllers_nr)) {
-+ pr_err("__arch_pcie_info_set failed, func:%s, line:%d\n", __func__, __LINE__);
-+ return -EIO;
-+ }
++ if (__arch_pcie_info_set(&info[*controllers_nr], *controllers_nr)) {
++ pr_err("__arch_pcie_info_set failed, func:%s, line:%d\n", __func__, __LINE__);
++ return -EIO;
++ }
+
-+ return 0;
++ return 0;
+}
+
+static void __arch_pcie_info_release(struct pcie_info *info)
+{
-+ int nr;
-+ for (nr = 0; nr < pcie_controllers_nr; nr++) {
-+ __arch_pcie_info_clr(&info[nr]);
-+ }
++ int nr;
++ for (nr = 0; nr < pcie_controllers_nr; nr++) {
++ __arch_pcie_info_clr(&info[nr]);
++ }
+}
+
+void set_pcie_phy0_porta(void *crg_base)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(crg_base + REG_CRG72);
-+ val |= (0x1 << 2);
-+ writel(val, crg_base + REG_CRG72);
++ val = readl(crg_base + REG_CRG72);
++ val |= (0x1 << 2);
++ writel(val, crg_base + REG_CRG72);
+
-+ udelay(500);
-+ val = readl(crg_base + REG_CRG72);
-+ val &= ~(0x1 << 2);
-+ writel(val, crg_base + REG_CRG72);
++ udelay(500);
++ val = readl(crg_base + REG_CRG72);
++ val &= ~(0x1 << 2);
++ writel(val, crg_base + REG_CRG72);
+
-+ writel(0x41a, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x45a, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x41a, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x41a, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x45a, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x41a, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
+
+
-+ writel(0x303, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x343, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x303, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x303, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x343, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x303, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
+
+
+}
+
+void set_pice_phy0_portb(void *crg_base)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(crg_base + REG_CRG72);
-+ val |= (0x1 << 3);
-+ writel(val, crg_base + REG_CRG72);
++ val = readl(crg_base + REG_CRG72);
++ val |= (0x1 << 3);
++ writel(val, crg_base + REG_CRG72);
+
-+ udelay(500);
-+ val = readl(crg_base + REG_CRG72);
-+ val &= ~(0x1 << 3);
-+ writel(val, crg_base + REG_CRG72);
++ udelay(500);
++ val = readl(crg_base + REG_CRG72);
++ val &= ~(0x1 << 3);
++ writel(val, crg_base + REG_CRG72);
+
-+ writel(0x43a, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x47a, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x43a, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x43a, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x47a, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x43a, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
+
+
-+ writel(0x323, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x363, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x323, misc_ctrl_virt + MISC_CTRL77);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x323, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x363, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x323, misc_ctrl_virt + MISC_CTRL77);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL77);
+
+
+}
+
+void set_pcie_phy1_porta(void *crg_base)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(crg_base + REG_CRG72);
-+ val |= (0x1 << 10);
-+ writel(val, crg_base + REG_CRG72);
++ val = readl(crg_base + REG_CRG72);
++ val |= (0x1 << 10);
++ writel(val, crg_base + REG_CRG72);
+
-+ udelay(500);
-+ val = readl(crg_base + REG_CRG72);
-+ val &= ~(0x1 << 10);
-+ writel(val, crg_base + REG_CRG72);
++ udelay(500);
++ val = readl(crg_base + REG_CRG72);
++ val &= ~(0x1 << 10);
++ writel(val, crg_base + REG_CRG72);
+
-+ writel(0x41a, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x45a, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x41a, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x41a, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x45a, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x41a, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
+
-+ writel(0x303, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x343, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x303, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x303, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x343, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x303, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
+
+
+}
+
+void set_pcie_phy1_portb(void *crg_base)
+{
-+ unsigned int val;
++ unsigned int val;
+
-+ val = readl(crg_base + REG_CRG72);
-+ val |= (0x1 << 11);
-+ writel(val, crg_base + REG_CRG72);
++ val = readl(crg_base + REG_CRG72);
++ val |= (0x1 << 11);
++ writel(val, crg_base + REG_CRG72);
+
-+ udelay(500);
-+ val = readl(crg_base + REG_CRG72);
-+ val &= ~(0x1 << 11);
-+ writel(val, crg_base + REG_CRG72);
++ udelay(500);
++ val = readl(crg_base + REG_CRG72);
++ val &= ~(0x1 << 11);
++ writel(val, crg_base + REG_CRG72);
+
-+ writel(0x43a, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x47a, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x43a, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x43a, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x47a, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x43a, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
+
-+ writel(0x323, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x363, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x323, misc_ctrl_virt + MISC_CTRL78);
-+ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x323, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x363, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x323, misc_ctrl_virt + MISC_CTRL78);
++ writel(0x0, misc_ctrl_virt + MISC_CTRL78);
+
+
+}
+
+void set_pcie0_para(void *crg_base)
+{
-+ unsigned int val;
-+ unsigned int flag;
++ unsigned int val;
++ unsigned int flag;
+
-+ val = readl((void *)PCIE_SYS_STAT);
-+ flag = (val >> 12) & 0xf;
++ val = readl((void *)PCIE_SYS_STAT);
++ flag = (val >> 12) & 0xf;
+
-+ switch(flag) {
-+ case 0x1:
-+ case 0x3:
-+ case 0x9:
-+ case 0xb:
-+ val = readl(crg_base + REG_CRG73);
-+ val |= (0x1 << 7);
-+ writel(val, crg_base + REG_CRG73);
++ switch(flag) {
++ case 0x1:
++ case 0x3:
++ case 0x9:
++ case 0xb:
++ val = readl(crg_base + REG_CRG73);
++ val |= (0x1 << 7);
++ writel(val, crg_base + REG_CRG73);
+
-+ set_pcie_phy0_porta(crg_base);
++ set_pcie_phy0_porta(crg_base);
+
-+ break;
-+ case 0x2:
-+ case 0xa:
-+ case 0xc:
-+ case 0x4:
-+ val = readl(crg_base + REG_CRG73);
-+ val |= (0x1 << 7);
-+ writel(val, crg_base + REG_CRG73);
++ break;
++ case 0x2:
++ case 0xa:
++ case 0xc:
++ case 0x4:
++ val = readl(crg_base + REG_CRG73);
++ val |= (0x1 << 7);
++ writel(val, crg_base + REG_CRG73);
+
-+ set_pcie_phy0_porta(crg_base);
-+ set_pice_phy0_portb(crg_base);
++ set_pcie_phy0_porta(crg_base);
++ set_pice_phy0_portb(crg_base);
+
+
-+ break;
-+ default:
-+ break;
++ break;
++ default:
++ break;
+
-+ }
++ }
+}
+
+void set_pcie1_para(void *crg_base)
+{
-+ unsigned int val;
-+ unsigned int flag;
++ unsigned int val;
++ unsigned int flag;
+
-+ val = readl((void *)PCIE_SYS_STAT);
-+ flag = (val >> 12) & 0xf;
++ val = readl((void *)PCIE_SYS_STAT);
++ flag = (val >> 12) & 0xf;
+
-+ switch(flag) {
-+ case 0x3:
-+ case 0xb:
-+ val = readl(crg_base + REG_CRG73);
-+ val |= (0x1 << 15);
-+ writel(val, crg_base + REG_CRG73);
++ switch(flag) {
++ case 0x3:
++ case 0xb:
++ val = readl(crg_base + REG_CRG73);
++ val |= (0x1 << 15);
++ writel(val, crg_base + REG_CRG73);
+
-+ set_pice_phy0_portb(crg_base);
++ set_pice_phy0_portb(crg_base);
+
+
+
-+ break;
-+ case 0xc:
-+ val = readl(crg_base + REG_CRG73);
-+ val |= (0x1 << 15);
-+ writel(val, crg_base + REG_CRG73);
++ break;
++ case 0xc:
++ val = readl(crg_base + REG_CRG73);
++ val |= (0x1 << 15);
++ writel(val, crg_base + REG_CRG73);
+
-+ set_pcie_phy1_porta(crg_base);
++ set_pcie_phy1_porta(crg_base);
+
+
-+ break;
++ break;
+
-+ case 0x4:
-+ val = readl(crg_base + REG_CRG73);
-+ val |= (0x1 << 15);
-+ writel(val, crg_base + REG_CRG73);
++ case 0x4:
++ val = readl(crg_base + REG_CRG73);
++ val |= (0x1 << 15);
++ writel(val, crg_base + REG_CRG73);
+
-+ set_pcie_phy1_porta(crg_base);
-+ set_pcie_phy1_portb(crg_base);
++ set_pcie_phy1_porta(crg_base);
++ set_pcie_phy1_portb(crg_base);
+
+
-+ break;
-+ default:
-+ break;
++ break;
++ default:
++ break;
+
-+ }
++ }
+}
+
+static void __arch_pcie_sys_config(struct pcie_info *info)
+{
-+ unsigned int val;
-+ void *dbi_base = (void *)info->conf_base_addr;
-+ void *crg_base = (void *)IO_ADDRESS(PERI_CRG_BASE);
++ unsigned int val;
++ void *dbi_base = (void *)info->conf_base_addr;
++ void *crg_base = (void *)IO_ADDRESS(PERI_CRG_BASE);
+
-+ if (pcie_controller_0 == info->controller) {
-+ /*
-+ * Disable PCIE
-+ */
-+ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL7);
++ if (pcie_controller_0 == info->controller) {
++ /*
++ * Disable PCIE
++ */
++ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL7);
+
-+ /*
-+ * Reset
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val |= (1 << PCIE0_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG73);
++ /*
++ * Reset
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val |= (1 << PCIE0_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG73);
+
-+ /*
-+ * Retreat from the reset state
-+ */
-+ udelay(500);
-+ val = readl(crg_base + PERI_CRG73);
-+ val &= ~(1 << PCIE0_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG73);
-+ mdelay(10);
++ /*
++ * Retreat from the reset state
++ */
++ udelay(500);
++ val = readl(crg_base + PERI_CRG73);
++ val &= ~(1 << PCIE0_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG73);
++ mdelay(10);
+
-+ /* Set pcie phy0 parameter */
-+ set_pcie0_para(crg_base);
-+ mdelay(10);
++ /* Set pcie phy0 parameter */
++ set_pcie0_para(crg_base);
++ mdelay(10);
+
-+ /*
-+ * PCIE RC work mode
-+ */
-+ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL0);
-+ val &= (~(0xf << PCIE_DEVICE_TYPE));
-+ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
-+ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL0);
++ /*
++ * PCIE RC work mode
++ */
++ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL0);
++ val &= (~(0xf << PCIE_DEVICE_TYPE));
++ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
++ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL0);
+
-+ /*
-+ * Enable clk
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val |= ((1 << PCIE0_X2_BUS_CKEN)
-+ | (1 << PCIE0_X2_SYS_CKEN)
-+ | (1 << PCIE0_X2_PIPE_CKEN)
-+ | (1 << PCIE0_X2_AUX_CKEN));
-+ writel(val, crg_base + PERI_CRG73);
-+ mdelay(10);
++ /*
++ * Enable clk
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val |= ((1 << PCIE0_X2_BUS_CKEN)
++ | (1 << PCIE0_X2_SYS_CKEN)
++ | (1 << PCIE0_X2_PIPE_CKEN)
++ | (1 << PCIE0_X2_AUX_CKEN));
++ writel(val, crg_base + PERI_CRG73);
++ mdelay(10);
+
-+ val = readl(dbi_base + LINK_CTRL2_STATUS2);
-+ val &= ~((0xF << 12) | (0x7 << 7) | (0x1 << 6));
-+ val |= ((0x1 << 12) | (0x1 << 7) | (0x1 << 6));
-+ writel(val, dbi_base + LINK_CTRL2_STATUS2);
++ val = readl(dbi_base + LINK_CTRL2_STATUS2);
++ val &= ~((0xF << 12) | (0x7 << 7) | (0x1 << 6));
++ val |= ((0x1 << 12) | (0x1 << 7) | (0x1 << 6));
++ writel(val, dbi_base + LINK_CTRL2_STATUS2);
+
-+ /*
-+ * Enable controller
-+ */
-+ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL7);
-+ val |= (1 << PCIE_APP_LTSSM_ENBALE);
-+ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL7);
-+ udelay(1000);
++ /*
++ * Enable controller
++ */
++ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL7);
++ val |= (1 << PCIE_APP_LTSSM_ENBALE);
++ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL7);
++ udelay(1000);
+
-+ }
++ }
+
-+ if (pcie_controller_1 == info->controller) {
-+ /*
-+ * Disable PCIE
-+ */
-+ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL7);
++ if (pcie_controller_1 == info->controller) {
++ /*
++ * Disable PCIE
++ */
++ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL7);
+
-+ /*
-+ * Reset
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val |= (1 << PCIE1_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG73);
++ /*
++ * Reset
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val |= (1 << PCIE1_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG73);
+
-+ /*
-+ * Retreat from the reset state
-+ */
-+ udelay(500);
-+ val = readl(crg_base + PERI_CRG73);
-+ val &= ~(1 << PCIE1_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG73);
-+ mdelay(10);
++ /*
++ * Retreat from the reset state
++ */
++ udelay(500);
++ val = readl(crg_base + PERI_CRG73);
++ val &= ~(1 << PCIE1_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG73);
++ mdelay(10);
+
-+ /* Set pcie phy1 parameter */
-+ set_pcie1_para(crg_base);
-+ mdelay(10);
++ /* Set pcie phy1 parameter */
++ set_pcie1_para(crg_base);
++ mdelay(10);
+
-+ /*
-+ * PCIE RC work mode
-+ */
-+ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL0);
-+ val &= (~(0xf << PCIE_DEVICE_TYPE));
-+ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
-+ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL0);
++ /*
++ * PCIE RC work mode
++ */
++ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL0);
++ val &= (~(0xf << PCIE_DEVICE_TYPE));
++ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
++ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL0);
+
-+ /*
-+ * Enable clk
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val |= ((1 << PCIE1_X2_BUS_CKEN)
-+ | (1 << PCIE1_X2_SYS_CKEN)
-+ | (1 << PCIE1_X2_PIPE_CKEN)
-+ | (1 << PCIE1_X2_AUX_CKEN));
-+ writel(val, crg_base + PERI_CRG73);
++ /*
++ * Enable clk
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val |= ((1 << PCIE1_X2_BUS_CKEN)
++ | (1 << PCIE1_X2_SYS_CKEN)
++ | (1 << PCIE1_X2_PIPE_CKEN)
++ | (1 << PCIE1_X2_AUX_CKEN));
++ writel(val, crg_base + PERI_CRG73);
+
-+ val = readl(dbi_base + LINK_CTRL2_STATUS2);
-+ val &= ~((0xF << 12) | (0x7 << 7) | (0x1 << 6));
-+ val |= ((0x1 << 12) | (0x1 << 7) | (0x1 << 6));
-+ writel(val, dbi_base + LINK_CTRL2_STATUS2);
++ val = readl(dbi_base + LINK_CTRL2_STATUS2);
++ val &= ~((0xF << 12) | (0x7 << 7) | (0x1 << 6));
++ val |= ((0x1 << 12) | (0x1 << 7) | (0x1 << 6));
++ writel(val, dbi_base + LINK_CTRL2_STATUS2);
+
-+ /*
-+ * Enable controller
-+ */
-+ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL7);
-+ val |= (1 << PCIE_APP_LTSSM_ENBALE);
-+ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL7);
-+ udelay(1000);
-+ }
++ /*
++ * Enable controller
++ */
++ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL7);
++ val |= (1 << PCIE_APP_LTSSM_ENBALE);
++ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL7);
++ udelay(1000);
++ }
+
-+ /*
-+ * Set PCIE controller class code to be PCI-PCI bridge device
-+ */
-+ val = readl(dbi_base + PCI_CLASS_REVISION);
-+ val &= ~(0xffffff00);
-+ val |= (0x60400 << 8);
-+ writel(val, dbi_base + PCI_CLASS_REVISION);
-+ udelay(1000);
++ /*
++ * Set PCIE controller class code to be PCI-PCI bridge device
++ */
++ val = readl(dbi_base + PCI_CLASS_REVISION);
++ val &= ~(0xffffff00);
++ val |= (0x60400 << 8);
++ writel(val, dbi_base + PCI_CLASS_REVISION);
++ udelay(1000);
+
-+ val = readl(dbi_base + PCI_COMMAND);
-+ val |= 7;
-+ writel(val, dbi_base + PCI_COMMAND);
++ val = readl(dbi_base + PCI_COMMAND);
++ val |= 7;
++ writel(val, dbi_base + PCI_COMMAND);
+}
+
+static int __arch_pcie_sys_init(struct pcie_info *info)
+{
-+ __arch_pcie_sys_config(&info[pcie_controllers_nr]);
++ __arch_pcie_sys_config(&info[pcie_controllers_nr]);
+
-+ return 0;
++ return 0;
+}
+
+static void __arch_pcie_sys_exit(void)
+{
-+ void *crg_base = (void *)IO_ADDRESS(PERI_CRG_BASE);
-+ unsigned int val;
++ void *crg_base = (void *)IO_ADDRESS(PERI_CRG_BASE);
++ unsigned int val;
+
-+ /*
-+ * Disable PCIE0
-+ */
-+ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL7);
++ /*
++ * Disable PCIE0
++ */
++ val = readl(misc_ctrl_virt + PCIE0_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, misc_ctrl_virt + PCIE0_SYS_CTRL7);
+
-+ /*
-+ * Reset PCIE0
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val |= (1 << PCIE0_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG73);
++ /*
++ * Reset PCIE0
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val |= (1 << PCIE0_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG73);
+
-+ udelay(1000);
++ udelay(1000);
+
-+ /*
-+ * Disable clk of PCIE0
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val &= (~(1 << PCIE0_X2_AUX_CKEN));
-+ val &= (~(1 << PCIE0_X2_PIPE_CKEN));
-+ val &= (~(1 << PCIE0_X2_SYS_CKEN));
-+ val &= (~(1 << PCIE0_X2_BUS_CKEN));
-+ writel(val, crg_base + PERI_CRG73);
++ /*
++ * Disable clk of PCIE0
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val &= (~(1 << PCIE0_X2_AUX_CKEN));
++ val &= (~(1 << PCIE0_X2_PIPE_CKEN));
++ val &= (~(1 << PCIE0_X2_SYS_CKEN));
++ val &= (~(1 << PCIE0_X2_BUS_CKEN));
++ writel(val, crg_base + PERI_CRG73);
+
-+ udelay(1000);
++ udelay(1000);
+
-+ /*
-+ * Disable PCIE1
-+ */
-+ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL7);
++ /*
++ * Disable PCIE1
++ */
++ val = readl(misc_ctrl_virt + PCIE1_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, misc_ctrl_virt + PCIE1_SYS_CTRL7);
+
-+ /*
-+ * Reset PCIE1
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val |= (1 << PCIE1_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG73);
++ /*
++ * Reset PCIE1
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val |= (1 << PCIE1_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG73);
+
-+ udelay(1000);
++ udelay(1000);
+
-+ /*
-+ * Disable clk of PCIE1
-+ */
-+ val = readl(crg_base + PERI_CRG73);
-+ val &= (~(1 << PCIE1_X2_AUX_CKEN));
-+ val &= (~(1 << PCIE1_X2_PIPE_CKEN));
-+ val &= (~(1 << PCIE1_X2_SYS_CKEN));
-+ val &= (~(1 << PCIE1_X2_BUS_CKEN));
-+ writel(val, crg_base + PERI_CRG73);
++ /*
++ * Disable clk of PCIE1
++ */
++ val = readl(crg_base + PERI_CRG73);
++ val &= (~(1 << PCIE1_X2_AUX_CKEN));
++ val &= (~(1 << PCIE1_X2_PIPE_CKEN));
++ val &= (~(1 << PCIE1_X2_SYS_CKEN));
++ val &= (~(1 << PCIE1_X2_BUS_CKEN));
++ writel(val, crg_base + PERI_CRG73);
+
-+ udelay(1000);
++ udelay(1000);
+}
+
diff --git a/drivers/pci/hipcie/pcie_hi3531a.h b/drivers/pci/hipcie/pcie_hi3531a.h
@@ -324156,7 +392445,7 @@ index 0000000..bb00de5
+#endif
diff --git a/drivers/pci/hipcie/pcie_hi3559av100.c b/drivers/pci/hipcie/pcie_hi3559av100.c
new file mode 100644
-index 0000000..d962de5
+index 0000000..8c797dc
--- /dev/null
+++ b/drivers/pci/hipcie/pcie_hi3559av100.c
@@ -0,0 +1,393 @@
@@ -324189,93 +392478,93 @@ index 0000000..d962de5
+static void __arch_pcie_info_release(struct pcie_info *info);
+
+struct pcie_iatu iatu_table[] = {
-+ {
-+ .viewport = 0,
-+ .region_ctrl_1 = 0x00000004,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE_EP_CONF_BASE + (1 << 20),
-+ .ubar = 0x0,
-+ .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1,
-+ .ltar = 0x01000000,
-+ .utar = 0x00000000,
-+ },
-+ {
-+ .viewport = 1,
-+ .region_ctrl_1 = 0x00000005,
-+ .region_ctrl_2 = 0x90000000,
-+ .lbar = PCIE_EP_CONF_BASE + (2 << 20),
-+ .ubar = 0x0,
-+ .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1),
-+ .ltar = 0x02000000,
-+ .utar = 0x00000000,
-+ },
++ {
++ .viewport = 0,
++ .region_ctrl_1 = 0x00000004,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE_EP_CONF_BASE + (1 << 20),
++ .ubar = 0x0,
++ .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1,
++ .ltar = 0x01000000,
++ .utar = 0x00000000,
++ },
++ {
++ .viewport = 1,
++ .region_ctrl_1 = 0x00000005,
++ .region_ctrl_2 = 0x90000000,
++ .lbar = PCIE_EP_CONF_BASE + (2 << 20),
++ .ubar = 0x0,
++ .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1),
++ .ltar = 0x02000000,
++ .utar = 0x00000000,
++ },
+};
+
+static void __arch_config_iatu_tbl(struct pcie_info *info,
-+ struct pci_sys_data *sys)
++ struct pci_sys_data *sys)
+{
-+ int i;
-+ void __iomem *config_base = (void __iomem *)info->conf_base_addr;
-+ struct pcie_iatu *ptable = iatu_table;
-+ int table_size = ARRAY_SIZE(iatu_table);
++ int i;
++ void __iomem *config_base = (void __iomem *)info->conf_base_addr;
++ struct pcie_iatu *ptable = iatu_table;
++ int table_size = ARRAY_SIZE(iatu_table);
+
-+ for (i = 0; i < table_size; i++) {
-+ writel((ptable + i)->viewport, config_base + 0x900);
-+ writel((ptable + i)->lbar, config_base + 0x90c);
-+ writel((ptable + i)->ubar, config_base + 0x910);
-+ writel((ptable + i)->lar, config_base + 0x914);
-+ writel((ptable + i)->ltar, config_base + 0x918);
-+ writel((ptable + i)->utar, config_base + 0x91c);
-+ writel((ptable + i)->region_ctrl_1, config_base + 0x904);
-+ writel((ptable + i)->region_ctrl_2, config_base + 0x908);
-+ }
++ for (i = 0; i < table_size; i++) {
++ writel((ptable + i)->viewport, config_base + 0x900);
++ writel((ptable + i)->lbar, config_base + 0x90c);
++ writel((ptable + i)->ubar, config_base + 0x910);
++ writel((ptable + i)->lar, config_base + 0x914);
++ writel((ptable + i)->ltar, config_base + 0x918);
++ writel((ptable + i)->utar, config_base + 0x91c);
++ writel((ptable + i)->region_ctrl_1, config_base + 0x904);
++ writel((ptable + i)->region_ctrl_2, config_base + 0x908);
++ }
+
+}
+
+static inline int __arch_check_pcie_link(struct pcie_info *info)
+{
-+ int val;
++ int val;
+
-+ val = readl(dbi_base + PCIE_SYS_STATE0);
-+ return ((val & (1 << PCIE_XMLH_LINK_UP))
-+ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
++ val = readl(dbi_base + PCIE_SYS_STATE0);
++ return ((val & (1 << PCIE_XMLH_LINK_UP))
++ && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
+}
+
+static int __arch_get_port_nr(void)
+{
-+ unsigned int val, mode;
-+ int nr;
-+ void *pcie_sys_stat;
-+ unsigned int sys_ctrl_base;
++ unsigned int val, mode;
++ int nr;
++ void *pcie_sys_stat = NULL;
++ unsigned int sys_ctrl_base;
+
-+ /* Get sys ctrl base address */
-+ of_property_read_u32(g_of_node, "sys_ctrl_base", &sys_ctrl_base);
++ /* Get sys ctrl base address */
++ of_property_read_u32(g_of_node, "sys_ctrl_base", &sys_ctrl_base);
+
-+ pcie_sys_stat = ioremap_nocache(sys_ctrl_base + REG_SC_STAT, sizeof(int));
-+ if (!pcie_sys_stat) {
-+ pr_err("ioremap pcie sys status register failed!\n");
-+ return 0;
-+ }
++ pcie_sys_stat = ioremap_nocache(sys_ctrl_base + REG_SC_STAT, sizeof(int));
++ if (!pcie_sys_stat) {
++ pr_err("ioremap pcie sys status register failed!\n");
++ return 0;
++ }
+
-+ val = readl(pcie_sys_stat);
-+ mode = (val >> 12) & 0x3;
-+ switch (mode) {
-+ case 0x1:
-+ nr = 1;
-+ break;
++ val = readl(pcie_sys_stat);
++ mode = (val >> 12) & 0x3;
++ switch (mode) {
++ case 0x1:
++ nr = 1;
++ break;
+
-+ case 0x0:
-+ nr = 2;
-+ break;
++ case 0x0:
++ nr = 2;
++ break;
+
-+ default:
-+ nr = 0;
-+ break;
-+ }
++ default:
++ nr = 0;
++ break;
++ }
+
-+ iounmap(pcie_sys_stat);
++ iounmap(pcie_sys_stat);
+
-+ return nr;
++ return nr;
+}
+
+/*
@@ -324283,275 +392572,275 @@ index 0000000..d962de5
+ */
+static int __arch_pcie_info_setup(struct pcie_info *info, int *controllers_nr)
+{
-+ unsigned int mem_size;
-+ unsigned int cfg_size;
-+ int nr;
++ unsigned int mem_size;
++ unsigned int cfg_size;
++ int nr;
+
-+ /* Get pcie deice memory size */
-+ of_property_read_u32(g_of_node, "dev_mem_size", &mem_size);
++ /* Get pcie deice memory size */
++ of_property_read_u32(g_of_node, "dev_mem_size", &mem_size);
+
-+ /* Get pcie config space size*/
-+ of_property_read_u32(g_of_node, "dev_conf_size", &cfg_size);
++ /* Get pcie config space size*/
++ of_property_read_u32(g_of_node, "dev_conf_size", &cfg_size);
+
-+ nr = __arch_get_port_nr();
-+ if (!nr) {
-+ pr_err("Pcie port number: 0\n");
-+ *controllers_nr = 0;
-+ return -EINVAL;
-+ }
++ nr = __arch_get_port_nr();
++ if (!nr) {
++ pr_err("Pcie port number: 0\n");
++ *controllers_nr = 0;
++ return -EINVAL;
++ }
+
-+ if ((mem_size > __256MB__) || (cfg_size > __256MB__)) {
-+ pcie_error(
-+ "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
-+ mem_size, cfg_size);
-+ return -EINVAL;
-+ }
++ if ((mem_size > __256MB__) || (cfg_size > __256MB__)) {
++ pcie_error(
++ "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
++ mem_size, cfg_size);
++ return -EINVAL;
++ }
+
-+ info->controller = 0;
++ info->controller = 0;
+
-+ /* RC configuration space */
-+ info->conf_base_addr = (unsigned long)ioremap_nocache(PCIE_DBI_BASE,
-+ __8KB__);
-+ if (!info->conf_base_addr) {
-+ pcie_error("Address mapping for RC dbi failed!");
-+ return -EIO;
-+ }
++ /* RC configuration space */
++ info->conf_base_addr = (unsigned long)ioremap_nocache(PCIE_DBI_BASE,
++ __8KB__);
++ if (!info->conf_base_addr) {
++ pcie_error("Address mapping for RC dbi failed!");
++ return -EIO;
++ }
+
-+ /* Configuration space for all EPs */
-+ info->base_addr = (unsigned long)ioremap_nocache(PCIE_EP_CONF_BASE,
-+ cfg_size);
-+ if (!info->base_addr) {
-+ iounmap((void *)info->conf_base_addr);
-+ pcie_error("Address mapping for EPs cfg failed!");
-+ return -EIO;
-+ }
++ /* Configuration space for all EPs */
++ info->base_addr = (unsigned long)ioremap_nocache(PCIE_EP_CONF_BASE,
++ cfg_size);
++ if (!info->base_addr) {
++ iounmap((void *)info->conf_base_addr);
++ pcie_error("Address mapping for EPs cfg failed!");
++ return -EIO;
++ }
+
-+ return 0;
++ return 0;
+
+}
+
+static void __arch_pcie_info_release(struct pcie_info *info)
+{
-+ if (info->base_addr) {
-+ iounmap((void *)info->base_addr);
-+ }
++ if (info->base_addr) {
++ iounmap((void *)info->base_addr);
++ }
+
-+ if (info->conf_base_addr) {
-+ iounmap((void *)info->conf_base_addr);
-+ }
++ if (info->conf_base_addr) {
++ iounmap((void *)info->conf_base_addr);
++ }
+}
+
+static int __arch_pcie_sys_init(struct pcie_info *info)
+{
-+ unsigned int val;
-+ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
-+ void *misc_base = (void *)ioremap_nocache(MISC_CTRL_BASE, __4KB__);
-+ void *sys_base = (void *)ioremap_nocache(SYS_CTRL_BASE, __4KB__);
++ unsigned int val;
++ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
++ void *misc_base = (void *)ioremap_nocache(MISC_CTRL_BASE, __4KB__);
++ void *sys_base = (void *)ioremap_nocache(SYS_CTRL_BASE, __4KB__);
+
-+ dbi_base = (void *)info->conf_base_addr;
++ dbi_base = (void *)info->conf_base_addr;
+
-+ /*
-+ * Disable PCIE
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, dbi_base + PCIE_SYS_CTRL7);
++ /*
++ * Disable PCIE
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, dbi_base + PCIE_SYS_CTRL7);
+
-+ /*
-+ * Reset
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val |= (1 << PCIE_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Reset
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val |= (1 << PCIE_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG99);
+
-+ /*
-+ * Retreat from the reset state
-+ */
-+ udelay(500);
-+ val = readl(crg_base + PERI_CRG99);
-+ val &= ~(1 << PCIE_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG99);
-+ mdelay(10);
++ /*
++ * Retreat from the reset state
++ */
++ udelay(500);
++ val = readl(crg_base + PERI_CRG99);
++ val &= ~(1 << PCIE_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG99);
++ mdelay(10);
+
-+ val = readl(sys_base + SYS_SATA);
-+ if((val & (0x3 << PCIE_MODE)) == 0) {
-+ /*X2 select phy reset from crg*/
-+ val = readl(crg_base + PERI_CRG98);
-+ val |= (0x1 << phy1_srs_req_sel) | (0x1 << phy0_srs_req_sel);
-+ writel(val, crg_base + PERI_CRG98);
-+ mdelay(10);
++ val = readl(sys_base + SYS_SATA);
++ if((val & (0x3 << PCIE_MODE)) == 0) {
++ /*X2 select phy reset from crg*/
++ val = readl(crg_base + PERI_CRG98);
++ val |= (0x1 << phy1_srs_req_sel) | (0x1 << phy0_srs_req_sel);
++ writel(val, crg_base + PERI_CRG98);
++ mdelay(10);
+
-+ /*X2 reset phy reset*/
-+ val = readl(crg_base + PERI_CRG98);
-+ val |= ((0x1 << phy1_srs_req) | (0x1 << phy0_srs_req));
-+ writel(val, crg_base + PERI_CRG98);
-+ udelay(500);
++ /*X2 reset phy reset*/
++ val = readl(crg_base + PERI_CRG98);
++ val |= ((0x1 << phy1_srs_req) | (0x1 << phy0_srs_req));
++ writel(val, crg_base + PERI_CRG98);
++ udelay(500);
+
-+ /*X2 release phy reset*/
-+ val = readl(crg_base + PERI_CRG98);
-+ val &= ((~(0x1 << phy1_srs_req)) & (~(0x1 << phy0_srs_req)));
-+ writel(val, crg_base + PERI_CRG98);
++ /*X2 release phy reset*/
++ val = readl(crg_base + PERI_CRG98);
++ val &= ((~(0x1 << phy1_srs_req)) & (~(0x1 << phy0_srs_req)));
++ writel(val, crg_base + PERI_CRG98);
+
-+ /*
-+ * X2 seperate_rate=1
-+ */
-+ writel(0x90f, misc_base + MISC_CTRL5);
-+ writel(0x94f, misc_base + MISC_CTRL5);
-+ writel(0x90f, misc_base + MISC_CTRL5);
-+ writel(0x0, misc_base + MISC_CTRL5);
-+ writel(0x92f, misc_base + MISC_CTRL5);
-+ writel(0x96f, misc_base + MISC_CTRL5);
-+ writel(0x92f, misc_base + MISC_CTRL5);
-+ writel(0x0, misc_base + MISC_CTRL5);
-+ mdelay(10);
++ /*
++ * X2 seperate_rate=1
++ */
++ writel(0x90f, misc_base + MISC_CTRL5);
++ writel(0x94f, misc_base + MISC_CTRL5);
++ writel(0x90f, misc_base + MISC_CTRL5);
++ writel(0x0, misc_base + MISC_CTRL5);
++ writel(0x92f, misc_base + MISC_CTRL5);
++ writel(0x96f, misc_base + MISC_CTRL5);
++ writel(0x92f, misc_base + MISC_CTRL5);
++ writel(0x0, misc_base + MISC_CTRL5);
++ mdelay(10);
+
-+ /*
-+ * X2 split_cp_dis
-+ */
-+ writel(0xd11, misc_base + MISC_CTRL5);
-+ writel(0xd51, misc_base + MISC_CTRL5);
-+ writel(0xd11, misc_base + MISC_CTRL5);
-+ writel(0x0, misc_base + MISC_CTRL5);
-+ writel(0xd31, misc_base + MISC_CTRL5);
-+ writel(0xd71, misc_base + MISC_CTRL5);
-+ writel(0xd31, misc_base + MISC_CTRL5);
-+ writel(0x0, misc_base + MISC_CTRL5);
-+ mdelay(10);
-+ } else {
++ /*
++ * X2 split_cp_dis
++ */
++ writel(0xd11, misc_base + MISC_CTRL5);
++ writel(0xd51, misc_base + MISC_CTRL5);
++ writel(0xd11, misc_base + MISC_CTRL5);
++ writel(0x0, misc_base + MISC_CTRL5);
++ writel(0xd31, misc_base + MISC_CTRL5);
++ writel(0xd71, misc_base + MISC_CTRL5);
++ writel(0xd31, misc_base + MISC_CTRL5);
++ writel(0x0, misc_base + MISC_CTRL5);
++ mdelay(10);
++ } else {
+
-+ /*X1 select phy reset from crg*/
-+ val = readl(crg_base + PERI_CRG98);
-+ val |= (0x1 << phy0_srs_req_sel);
-+ writel(val, crg_base + PERI_CRG98);
-+ mdelay(10);
++ /*X1 select phy reset from crg*/
++ val = readl(crg_base + PERI_CRG98);
++ val |= (0x1 << phy0_srs_req_sel);
++ writel(val, crg_base + PERI_CRG98);
++ mdelay(10);
+
-+ /*X1 reset phy reset*/
-+ val = readl(crg_base + PERI_CRG98);
-+ val |= (0x1 << phy0_srs_req);
-+ writel(val, crg_base + PERI_CRG98);
-+ udelay(500);
++ /*X1 reset phy reset*/
++ val = readl(crg_base + PERI_CRG98);
++ val |= (0x1 << phy0_srs_req);
++ writel(val, crg_base + PERI_CRG98);
++ udelay(500);
+
-+ /*X1 release phy reset*/
-+ val = readl(crg_base + PERI_CRG98);
-+ val &= ~(0x1 << phy0_srs_req);
-+ writel(val, crg_base + PERI_CRG98);
++ /*X1 release phy reset*/
++ val = readl(crg_base + PERI_CRG98);
++ val &= ~(0x1 << phy0_srs_req);
++ writel(val, crg_base + PERI_CRG98);
+
-+ /*
-+ * X1 seperate_rate=1
-+ */
-+ writel(0x90f, misc_base + MISC_CTRL5);
-+ writel(0x94f, misc_base + MISC_CTRL5);
-+ writel(0x90f, misc_base + MISC_CTRL5);
-+ writel(0x0, misc_base + MISC_CTRL5);
-+ mdelay(10);
++ /*
++ * X1 seperate_rate=1
++ */
++ writel(0x90f, misc_base + MISC_CTRL5);
++ writel(0x94f, misc_base + MISC_CTRL5);
++ writel(0x90f, misc_base + MISC_CTRL5);
++ writel(0x0, misc_base + MISC_CTRL5);
++ mdelay(10);
+
-+ /*
-+ * X1 split_cp_dis
-+ */
-+ writel(0xd11, misc_base + MISC_CTRL5);
-+ writel(0xd51, misc_base + MISC_CTRL5);
-+ writel(0xd11, misc_base + MISC_CTRL5);
-+ writel(0x0, misc_base + MISC_CTRL5);
-+ mdelay(10);
++ /*
++ * X1 split_cp_dis
++ */
++ writel(0xd11, misc_base + MISC_CTRL5);
++ writel(0xd51, misc_base + MISC_CTRL5);
++ writel(0xd11, misc_base + MISC_CTRL5);
++ writel(0x0, misc_base + MISC_CTRL5);
++ mdelay(10);
+
-+ };
++ };
+
-+ /*
-+ * PCIE RC work mode
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL0);
-+ val &= (~(0xf << PCIE_DEVICE_TYPE));
-+ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
-+ writel(val, dbi_base + PCIE_SYS_CTRL0);
++ /*
++ * PCIE RC work mode
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL0);
++ val &= (~(0xf << PCIE_DEVICE_TYPE));
++ val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
++ writel(val, dbi_base + PCIE_SYS_CTRL0);
+
-+ /*
-+ * Enable clk
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val |= ((1 << PCIE_X2_BUS_CKEN)
-+ | (1 << PCIE_X2_SYS_CKEN)
-+ | (1 << PCIE_X2_PIPE_CKEN)
-+ | (1 << PCIE_X2_AUX_CKEN));
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Enable clk
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val |= ((1 << PCIE_X2_BUS_CKEN)
++ | (1 << PCIE_X2_SYS_CKEN)
++ | (1 << PCIE_X2_PIPE_CKEN)
++ | (1 << PCIE_X2_AUX_CKEN));
++ writel(val, crg_base + PERI_CRG99);
+
-+ mdelay(10);
++ mdelay(10);
+
-+ /*
-+ * * Set PCIe support the identification Board card
-+ */
-+ val = readl(dbi_base + PCI_CARD);
-+ val |= (1 << 3);
-+ writel(val, dbi_base + PCI_CARD);
-+ mdelay(10);
++ /*
++ * * Set PCIe support the identification Board card
++ */
++ val = readl(dbi_base + PCI_CARD);
++ val |= (1 << 3);
++ writel(val, dbi_base + PCI_CARD);
++ mdelay(10);
+
-+ /*
-+ * Set PCIE controller class code to be PCI-PCI bridge device
-+ */
-+ val = readl(dbi_base + PCI_CLASS_REVISION);
-+ val &= ~(0xffffff00);
-+ val |= (0x60400 << 8);
-+ writel(val, dbi_base + PCI_CLASS_REVISION);
-+ udelay(1000);
++ /*
++ * Set PCIE controller class code to be PCI-PCI bridge device
++ */
++ val = readl(dbi_base + PCI_CLASS_REVISION);
++ val &= ~(0xffffff00);
++ val |= (0x60400 << 8);
++ writel(val, dbi_base + PCI_CLASS_REVISION);
++ udelay(1000);
+
-+ /*
-+ * Enable controller
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL7);
-+ val |= (1 << PCIE_APP_LTSSM_ENBALE);
-+ writel(val, dbi_base + PCIE_SYS_CTRL7);
-+ udelay(1000);
++ /*
++ * Enable controller
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL7);
++ val |= (1 << PCIE_APP_LTSSM_ENBALE);
++ writel(val, dbi_base + PCIE_SYS_CTRL7);
++ udelay(1000);
+
-+ val = readl(dbi_base + PCI_COMMAND);
-+ val |= 7;
-+ writel(val, dbi_base + PCI_COMMAND);
++ val = readl(dbi_base + PCI_COMMAND);
++ val |= 7;
++ writel(val, dbi_base + PCI_COMMAND);
+
+#ifdef CONFIG_ENABLE_PCIE_1
-+ /* set pcie to gen 1*/
-+ writel(0x1, dbi_base + 0x8BC);
-+ val = readl(dbi_base + 0x7C);
-+ val = ((val >> 4) << 4) | 0x1;
-+ writel(val, dbi_base + 0x7C);
++ /* set pcie to gen 1*/
++ writel(0x1, dbi_base + 0x8BC);
++ val = readl(dbi_base + 0x7C);
++ val = ((val >> 4) << 4) | 0x1;
++ writel(val, dbi_base + 0x7C);
+#endif
+
-+ iounmap(misc_base);
-+ iounmap(crg_base);
-+ return 0;
++ iounmap(misc_base);
++ iounmap(crg_base);
++ return 0;
+}
+
+static void __arch_pcie_sys_exit(void)
+{
-+ unsigned int val;
-+ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
++ unsigned int val;
++ void *crg_base = (void *)ioremap_nocache(PERI_CRG_BASE, __8KB__);
+
-+ /*
-+ * Disable PCIE
-+ */
-+ val = readl(dbi_base + PCIE_SYS_CTRL7);
-+ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
-+ writel(val, dbi_base + PCIE_SYS_CTRL7);
++ /*
++ * Disable PCIE
++ */
++ val = readl(dbi_base + PCIE_SYS_CTRL7);
++ val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
++ writel(val, dbi_base + PCIE_SYS_CTRL7);
+
-+ /*
-+ * Reset
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val |= (1 << PCIE_X2_SRST_REQ);
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Reset
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val |= (1 << PCIE_X2_SRST_REQ);
++ writel(val, crg_base + PERI_CRG99);
+
-+ udelay(1000);
++ udelay(1000);
+
-+ /*
-+ * Disable clk
-+ */
-+ val = readl(crg_base + PERI_CRG99);
-+ val &= (~(1 << PCIE_X2_AUX_CKEN));
-+ val &= (~(1 << PCIE_X2_PIPE_CKEN));
-+ val &= (~(1 << PCIE_X2_SYS_CKEN));
-+ val &= (~(1 << PCIE_X2_BUS_CKEN));
-+ writel(val, crg_base + PERI_CRG99);
++ /*
++ * Disable clk
++ */
++ val = readl(crg_base + PERI_CRG99);
++ val &= (~(1 << PCIE_X2_AUX_CKEN));
++ val &= (~(1 << PCIE_X2_PIPE_CKEN));
++ val &= (~(1 << PCIE_X2_SYS_CKEN));
++ val &= (~(1 << PCIE_X2_BUS_CKEN));
++ writel(val, crg_base + PERI_CRG99);
+
-+ iounmap(crg_base);
++ iounmap(crg_base);
+
-+ udelay(1000);
++ udelay(1000);
+}
diff --git a/drivers/pci/hipcie/pcie_hi3559av100.h b/drivers/pci/hipcie/pcie_hi3559av100.h
new file mode 100644
@@ -324641,6 +392930,20 @@ index 0000000..69baebc
+#define PCI_CARD 0x44
+#define MISC_CTRL5 0x14
+#endif
+diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
+index 56154c2..cfe6966 100644
+--- a/drivers/pci/host/pcie-hisi.c
++++ b/drivers/pci/host/pcie-hisi.c
+@@ -3,9 +3,6 @@
+ *
+ * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+- * Authors: Zhou Wang <wangzhou1@hisilicon.com>
+- * Dacai Zhu <zhudacai@hisilicon.com>
+- * Gabriele Paoloni <gabriele.paoloni@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 1ccce1c..2638d29 100644
--- a/drivers/pci/pci-driver.c
@@ -324722,7 +393025,7 @@ index a534cf5..b69cc4b 100644
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
diff --git a/drivers/phy/hibvt/Kconfig b/drivers/phy/hibvt/Kconfig
new file mode 100644
-index 0000000..7cdc3d3
+index 0000000..2aaa628
--- /dev/null
+++ b/drivers/phy/hibvt/Kconfig
@@ -0,0 +1,76 @@
@@ -324791,23 +393094,23 @@ index 0000000..7cdc3d3
+
+config USB_DRD1_IN_HOST
+ bool "USB DRD1 Mode Select HOST"
-+ depends on (ARCH_HI3519AV100 || ARCH_HI3556AV100 || ARCH_HI3559AV100)
++ depends on (ARCH_HI3519AV100 || ARCH_HI3556AV100 || ARCH_HI3559AV100 || ARCH_HI3569V100)
+ help
+ Select whether the USB drd1 is working in host mode.
+
+config USB_DRD1_IN_DEVICE
+ bool "USB DRD1 Mode Select DEVICE"
-+ depends on (ARCH_HI3519AV100 || ARCH_HI3556AV100 || ARCH_HI3559AV100)
++ depends on (ARCH_HI3519AV100 || ARCH_HI3556AV100 || ARCH_HI3559AV100 || ARCH_HI3569V100)
+ help
+ Select whether the USB drd1 is working in device mode.
+
+endif # USB_MODE_OPTION
diff --git a/drivers/phy/hibvt/Makefile b/drivers/phy/hibvt/Makefile
new file mode 100644
-index 0000000..974751c
+index 0000000..953587f
--- /dev/null
+++ b/drivers/phy/hibvt/Makefile
-@@ -0,0 +1,17 @@
+@@ -0,0 +1,20 @@
+obj-$(CONFIG_PHY_HISI_SATA) += phy-hisi-sata.o
+obj-$(CONFIG_PHY_HISI_USB2) += phy-hisi-usb.o
+obj-$(CONFIG_PHY_HISI_USB3) += phy-hisi-usb3.o
@@ -324818,21 +393121,28 @@ index 0000000..974751c
+obj-$(CONFIG_ARCH_HI3531A) += hiusb-ehci-hi3531a.o
+obj-$(CONFIG_ARCH_HI3531A) += hiusb-xhci-hi3531a.o
+obj-$(CONFIG_ARCH_HI3559AV100) += phy-hi3559av100-usb.o
++obj-$(CONFIG_ARCH_HI3569V100) += phy-hi3559av100-usb.o
+obj-$(CONFIG_ARCH_HI3556AV100) += phy-hi3556av100-usb.o
+obj-$(CONFIG_ARCH_HI3519AV100) += phy-hi3519av100-usb.o
+obj-$(CONFIG_ARCH_HI3516CV500) += phy-hi3516cv500-usb.o
+obj-$(CONFIG_ARCH_HI3516DV300) += phy-hi3516dv300-usb.o
+obj-$(CONFIG_ARCH_HI3559V200) += phy-hi3559v200-usb.o
++obj-$(CONFIG_ARCH_HI3562V100) += phy-hi3559v200-usb.o
++obj-$(CONFIG_ARCH_HI3566V100) += phy-hi3559v200-usb.o
+obj-$(CONFIG_ARCH_HI3556V200) += phy-hi3556v200-usb.o
+obj-$(CONFIG_PHY_HISI_XVP_USB2) += phy-hixvp-hisi-usb.o
diff --git a/drivers/phy/hibvt/hiusb-ehci-hi3531a.c b/drivers/phy/hibvt/hiusb-ehci-hi3531a.c
new file mode 100644
-index 0000000..bfb7061
+index 0000000..9ebd747
--- /dev/null
+++ b/drivers/phy/hibvt/hiusb-ehci-hi3531a.c
-@@ -0,0 +1,142 @@
+@@ -0,0 +1,150 @@
+/*
-+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
++ * hiusb-ehci-hi3531a.c
++ *
++ * USB2 phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -324880,9 +393190,13 @@ index 0000000..bfb7061
+#define CONFIG_CLK ((0x1 << 5) | (0x6 << 0) | (0x4 << 8))
+#define IO_REG_USB2_CTRL1 0x0094
+
++#define CONFIG_CLK_ENABLE 0x0
++#define HS_PRE_ENABLE 0x0
++#define HS_PRE_CONFIG_VAL 0x1820
++
+void hisi_usb_phy_on(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* reset enable */
@@ -324918,7 +393232,7 @@ index 0000000..bfb7061
+ udelay(U_LEVEL7);
+
+ /* config clock */
-+ writel(0x0, priv->misc_ctrl + IO_REG_USB2_CTRL1);
++ writel(CONFIG_CLK_ENABLE, priv->misc_ctrl + IO_REG_USB2_CTRL1);
+ mdelay(M_LEVEL7);
+
+ reg = readl(priv->misc_ctrl + IO_REG_USB2_CTRL1);
@@ -324928,9 +393242,9 @@ index 0000000..bfb7061
+
+ /* config u2 eye diagram */
+ /* close HS pre-emphasis */
-+ writel(0x0, priv->misc_ctrl + IO_REG_USB2_CTRL1);
++ writel(HS_PRE_ENABLE, priv->misc_ctrl + IO_REG_USB2_CTRL1);
+ udelay(U_LEVEL1);
-+ writel(0x1820, priv->misc_ctrl + IO_REG_USB2_CTRL1);
++ writel(HS_PRE_CONFIG_VAL, priv->misc_ctrl + IO_REG_USB2_CTRL1);
+ udelay(U_LEVEL5);
+
+ /* cancel port reset */
@@ -324943,7 +393257,7 @@ index 0000000..bfb7061
+ reg = readl(priv->peri_ctrl + IO_REG_USB2_CTRL);
+ reg &= ~(USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ | USB2_HST_PHY_SYST_REQ);
+ reg |= (USB2_BUS_CKEN | USB2_OHCI48M_CKEN | USB2_OHCI12M_CKEN |
-+ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
++ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
+ writel(reg, priv->peri_ctrl + IO_REG_USB2_CTRL);
+ udelay(U_LEVEL6);
+}
@@ -324951,7 +393265,7 @@ index 0000000..bfb7061
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->peri_ctrl + IO_REG_USB2_PHY0);
@@ -324968,19 +393282,23 @@ index 0000000..bfb7061
+ /* close clock */
+ reg = readl(priv->peri_ctrl + IO_REG_USB2_CTRL);
+ reg &= ~(USB2_BUS_CKEN | USB2_OHCI48M_CKEN | USB2_OHCI12M_CKEN |
-+ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
++ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
+ writel(reg, priv->peri_ctrl + IO_REG_USB2_CTRL);
+ udelay(U_LEVEL6);
+}
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/hiusb-xhci-hi3531a.c b/drivers/phy/hibvt/hiusb-xhci-hi3531a.c
new file mode 100644
-index 0000000..69b0103
+index 0000000..5cb10f6
--- /dev/null
+++ b/drivers/phy/hibvt/hiusb-xhci-hi3531a.c
-@@ -0,0 +1,164 @@
+@@ -0,0 +1,168 @@
+/*
-+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
++ * hiusb-xhci-hi3531a.c
++ *
++ * USB3 phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -325025,7 +393343,7 @@ index 0000000..69b0103
+
+void usb_ctrl_config(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -325043,7 +393361,7 @@ index 0000000..69b0103
+
+void usb2_phy_config(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->peri_ctrl + PERI_CRG91);
@@ -325085,7 +393403,7 @@ index 0000000..69b0103
+
+void hisi_usb3_phy_on(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* reset enable */
@@ -325118,7 +393436,7 @@ index 0000000..69b0103
+
+void hisi_usb3_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* reset enable */
@@ -325145,27 +393463,31 @@ index 0000000..69b0103
+EXPORT_SYMBOL(hisi_usb3_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3516a-usb.c b/drivers/phy/hibvt/phy-hi3516a-usb.c
new file mode 100644
-index 0000000..5963a49
+index 0000000..e789f70
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3516a-usb.c
-@@ -0,0 +1,167 @@
+@@ -0,0 +1,168 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * phy-hi3516a-usb.c
+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
++
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
@@ -325189,66 +393511,63 @@ index 0000000..5963a49
+#define USBOVR_P_CTRL (1 << 17)
+#define MISC_USB 0x80
+
-+static int *usb2_switch_base;
-+
-+void hisi_switch_func(int otg)
-+{
-+ int reg;
-+
-+ reg = readl(usb2_switch_base);
-+ if (otg) {
-+ reg |= 0x1;
-+ writel(reg, usb2_switch_base);
-+ } else {
-+ reg &= ~(0x1);
-+ writel(reg, usb2_switch_base);
-+ }
-+}
-+EXPORT_SYMBOL(hisi_switch_func);
++#define EYE_PATTERN0 0x908
++#define EYE_VAL0 0x928
++#define EYE_PATTERN1 0xc06
++#define EYE_VAL1 0xc26
++#define EYE_PATTERN2 0x108
++#define EYE_VAL2 0x128
++#define EYE_PATTERN3 0x1c00
++#define EYE_VAL3 0x1c20
++#define EYE_PATTERN4 0xc09
++#define EYE_VAL4 0xc29
++#define EYE_PATTERN5 0x1a0a
++#define EYE_VAL5 0x1a2a
++#define EYE_PATTERN6 0xa
++#define EYE_VAL6 0x92a
+
+void usb_phy_eye_config(struct phy *phy)
+{
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ writel(0x908, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN0, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x928, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL0, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL1);
+
+ /* open phy clk */
-+ writel(0xc06, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN1, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0xc26, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL1, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
-+ writel(0x108, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN2, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x128, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL2, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
+ /* usb2.0 phy eye pattern */
-+ writel(0x1c00, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN3, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x1c20, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL3, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
-+ writel(0x0c09, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN4, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x0c29, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL4, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
-+ writel(0x1a0a, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN5, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x1a2a, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL5, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+}
+
+void hisi_usb_phy_on(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ usb2_switch_base = priv->switch_base + USB2_SWITCH_OFFSET;
+ /* enable phy ref clk to enable phy */
+ reg = readl(priv->peri_ctrl + PERI_CRG46);
+ reg |= USB_CKEN;
@@ -325286,16 +393605,16 @@ index 0000000..5963a49
+ udelay(U_LEVEL6);
+
+ /* decrease the threshold value from 650 to 550 */
-+ writel(0xa, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN6, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x092a, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL6, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+}
+EXPORT_SYMBOL(hisi_usb_phy_on);
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->peri_ctrl + PERI_CRG46);
@@ -325318,12 +393637,16 @@ index 0000000..5963a49
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3516cv500-usb.c b/drivers/phy/hibvt/phy-hi3516cv500-usb.c
new file mode 100644
-index 0000000..90d4435
+index 0000000..d8c8fd5
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3516cv500-usb.c
-@@ -0,0 +1,304 @@
+@@ -0,0 +1,310 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
++ * phy-hi3516cv500-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -325418,8 +393741,8 @@ index 0000000..90d4435
+
+static void usb_vbus_multi_gpio(void)
+{
-+ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, 0x100);
-+ if (!vbus)
++ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, __1K__);
++ if (vbus == NULL)
+ return;
+
+ writel(USB2_VBUS_IO_VAL, vbus + USB2_VBUS_IO_OFFSET);
@@ -325430,17 +393753,17 @@ index 0000000..90d4435
+
+static void usb_trim_c(void)
+{
-+ int reg;
-+ int trim_val;
-+ void __iomem *inno_clk_output;
-+ void __iomem *usb_trim;
++ unsigned int reg;
++ unsigned int trim_val;
++ void __iomem *inno_clk_output = NULL;
++ void __iomem *usb_trim = NULL;
+
-+ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_clk_output)
++ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_clk_output == NULL)
+ return;
+
-+ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, 0x100);
-+ if (!usb_trim)
++ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, __1K__);
++ if (usb_trim == NULL)
+ goto free;
+
+ /* set inno phy output clock */
@@ -325470,7 +393793,7 @@ index 0000000..90d4435
+
+static void usb_crg_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb phy reset */
@@ -325525,11 +393848,11 @@ index 0000000..90d4435
+
+static void usb_ctrl_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -325552,7 +393875,7 @@ index 0000000..90d4435
+
+ reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
+ reg &= ~PCS_SSP_SOFT_RESET;
-+ reg &= ~PORT_DISABLE_SUSPEND; // disable suspend
++ reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */
+ writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
+ udelay(U_LEVEL2);
+
@@ -325565,10 +393888,11 @@ index 0000000..90d4435
+
+static void usb_eye_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
++ void __iomem *inno_base = NULL;
+
-+ void __iomem *inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_base)
++ inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_base == NULL)
+ return;
+
+ /* HS eye height tuning */
@@ -325600,6 +393924,7 @@ index 0000000..90d4435
+ reg &= ~DISCONNECT_TRIGGER_MASK;
+ reg |= DISCONNECT_TRIGGER_VAL;
+ writel(reg, inno_base + DISCONNECT_TRIGGER_OFFSET);
++ iounmap(inno_base);
+}
+
+void hisi_usb_phy_on(struct phy *phy)
@@ -325616,7 +393941,7 @@ index 0000000..90d4435
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb2 vcc reset */
@@ -325628,12 +393953,16 @@ index 0000000..90d4435
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3516dv300-usb.c b/drivers/phy/hibvt/phy-hi3516dv300-usb.c
new file mode 100644
-index 0000000..90d4435
+index 0000000..6bee762
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3516dv300-usb.c
-@@ -0,0 +1,304 @@
+@@ -0,0 +1,310 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
++ * phy-hi3516dv300-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -325728,8 +394057,8 @@ index 0000000..90d4435
+
+static void usb_vbus_multi_gpio(void)
+{
-+ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, 0x100);
-+ if (!vbus)
++ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, __1K__);
++ if (vbus == NULL)
+ return;
+
+ writel(USB2_VBUS_IO_VAL, vbus + USB2_VBUS_IO_OFFSET);
@@ -325740,17 +394069,17 @@ index 0000000..90d4435
+
+static void usb_trim_c(void)
+{
-+ int reg;
-+ int trim_val;
-+ void __iomem *inno_clk_output;
-+ void __iomem *usb_trim;
++ unsigned int reg;
++ unsigned int trim_val;
++ void __iomem *inno_clk_output = NULL;
++ void __iomem *usb_trim = NULL;
+
-+ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_clk_output)
++ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_clk_output == NULL)
+ return;
+
-+ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, 0x100);
-+ if (!usb_trim)
++ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, __1K__);
++ if (usb_trim == NULL)
+ goto free;
+
+ /* set inno phy output clock */
@@ -325780,7 +394109,7 @@ index 0000000..90d4435
+
+static void usb_crg_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb phy reset */
@@ -325835,11 +394164,11 @@ index 0000000..90d4435
+
+static void usb_ctrl_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -325862,7 +394191,7 @@ index 0000000..90d4435
+
+ reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
+ reg &= ~PCS_SSP_SOFT_RESET;
-+ reg &= ~PORT_DISABLE_SUSPEND; // disable suspend
++ reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */
+ writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
+ udelay(U_LEVEL2);
+
@@ -325875,10 +394204,11 @@ index 0000000..90d4435
+
+static void usb_eye_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
++ void __iomem *inno_base = NULL;
+
-+ void __iomem *inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_base)
++ inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_base == NULL)
+ return;
+
+ /* HS eye height tuning */
@@ -325910,6 +394240,7 @@ index 0000000..90d4435
+ reg &= ~DISCONNECT_TRIGGER_MASK;
+ reg |= DISCONNECT_TRIGGER_VAL;
+ writel(reg, inno_base + DISCONNECT_TRIGGER_OFFSET);
++ iounmap(inno_base);
+}
+
+void hisi_usb_phy_on(struct phy *phy)
@@ -325926,7 +394257,7 @@ index 0000000..90d4435
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb2 vcc reset */
@@ -325938,12 +394269,16 @@ index 0000000..90d4435
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3518ev20x-usb.c b/drivers/phy/hibvt/phy-hi3518ev20x-usb.c
new file mode 100644
-index 0000000..08f5f6c
+index 0000000..dbed8c7
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3518ev20x-usb.c
-@@ -0,0 +1,151 @@
+@@ -0,0 +1,145 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * phy-hi3518ev20x-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2017-2018. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -325982,29 +394317,23 @@ index 0000000..08f5f6c
+#define USBOVR_P_CTRL (1 << 17)
+#define MISC_USB 0x80
+
-+static int *usb2_switch_base;
++#define PHY_CLK_ENABLE 0xc06
++#define PHY_CLK_OPEN 0xc26
+
-+void hisi_switch_func(int otg)
-+{
-+ int reg;
-+
-+ reg = readl(usb2_switch_base);
-+ if (otg) {
-+ reg |= 0x1;
-+ writel(reg, usb2_switch_base);
-+ } else {
-+ reg &= ~(0x1);
-+ writel(reg, usb2_switch_base);
-+ }
-+}
-+EXPORT_SYMBOL(hisi_switch_func);
++#define EYE_PATTERN0 0x1c00
++#define EYE_VAL0 0x1c20
++#define EYE_PATTERN1 0xc09
++#define EYE_VAL1 0xc29
++#define EYE_PATTERN2 0x1a0a
++#define EYE_VAL2 0x1a2a
++#define EYE_PATTERN3 0xa
++#define EYE_VAL3 0x92a
+
+void hisi_usb_phy_on(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ usb2_switch_base = priv->switch_base + USB2_SWITCH_OFFSET;
+ /* enable phy ref clk to enable phy */
+ reg = readl(priv->peri_ctrl + PERI_CRG46);
+ reg |= USB_CKEN;
@@ -326013,9 +394342,7 @@ index 0000000..08f5f6c
+
+ /* config controller */
+ reg = readl(priv->misc_ctrl + PERI_USB);
-+ reg &= ~(WORDINTERFACE); /* 8bit */
-+ /* disable ehci burst16 mode */
-+ reg &= ~(SS_BURST16_EN);
++ reg &= ~(WORDINTERFACE | SS_BURST16_EN);
+ reg |= USBOVR_P_CTRL;
+ writel(reg, priv->misc_ctrl + PERI_USB);
+ udelay(U_LEVEL5);
@@ -326027,25 +394354,25 @@ index 0000000..08f5f6c
+ udelay(U_LEVEL5);
+
+ /* open phy clk */
-+ writel(0xc06, priv->misc_ctrl + MISC_USB);
++ writel(PHY_CLK_ENABLE, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0xc26, priv->misc_ctrl + MISC_USB);
++ writel(PHY_CLK_OPEN, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
+ /* usb2.0 phy eye pattern */
-+ writel(0x1c00, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN0, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x1c20, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL0, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
-+ writel(0x0c09, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN1, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x0c29, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL1, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
-+ writel(0x1a0a, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN2, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x1a2a, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL2, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+
+ /* cancel phy utmi reset */
@@ -326056,23 +394383,21 @@ index 0000000..08f5f6c
+
+ /* de-assert all the rsts of ctrl */
+ reg = readl(priv->peri_ctrl + PERI_CRG46);
-+ reg &= ~(USB_CTRL_UTMI0_REG);
-+ reg &= ~(USB_CTRL_HUB_REG);
-+ reg &= ~(USB_AHB_SRST_REQ);
++ reg &= ~(USB_CTRL_UTMI0_REG | USB_CTRL_HUB_REG | USB_AHB_SRST_REQ);
+ writel(reg, priv->peri_ctrl + PERI_CRG46);
+ udelay(U_LEVEL6);
+
+ /* decrease the threshold value from 650 to 550 */
-+ writel(0xa, priv->misc_ctrl + MISC_USB);
++ writel(EYE_PATTERN3, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x092a, priv->misc_ctrl + MISC_USB);
++ writel(EYE_VAL3, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL2);
+}
+EXPORT_SYMBOL(hisi_usb_phy_on);
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->peri_ctrl + PERI_CRG46);
@@ -326095,12 +394420,16 @@ index 0000000..08f5f6c
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3519av100-usb.c b/drivers/phy/hibvt/phy-hi3519av100-usb.c
new file mode 100644
-index 0000000..ab80fee
+index 0000000..2f12495
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3519av100-usb.c
-@@ -0,0 +1,442 @@
+@@ -0,0 +1,446 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
++ * phy-hi3519av100-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -326201,6 +394530,9 @@ index 0000000..ab80fee
+#define USB2_DEF_CRG 0x00001301
+#define USB2_DEF_CFG_MASK 0x0000ffff
+
++#define COMBPHY_IN_USE 0x1
++#define COMBPHY_NO_IN_USE 0x0
++
+void hisi_usb_crg_config(struct phy *phy)
+{
+ unsigned int reg;
@@ -326255,8 +394587,8 @@ index 0000000..ab80fee
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(USB2_CTRL_REGBASE, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(USB2_CTRL_REGBASE, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -326306,8 +394638,8 @@ index 0000000..ab80fee
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, 0x1000);
-+ if (!priv->sys_ctrl)
++ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, __4K__);
++ if (priv->sys_ctrl == NULL)
+ return;
+
+ if (rst) {
@@ -326367,7 +394699,7 @@ index 0000000..ab80fee
+ writel(reg, priv->misc_ctrl + PORT0_CTRL);
+ udelay(U_LEVEL5);
+
-+ usb_combphy_config(phy, 1);
++ usb_combphy_config(phy, COMBPHY_IN_USE);
+
+ /* release TPOR default release */
+ reg = readl(priv->peri_ctrl + USB2_PHY);
@@ -326393,7 +394725,7 @@ index 0000000..ab80fee
+ writel(reg, priv->peri_ctrl + USB2_PHY);
+ udelay(U_LEVEL6);
+
-+ usb_combphy_config(phy, 0);
++ usb_combphy_config(phy, COMBPHY_NO_IN_USE);
+
+ /* config U3 Controller release */
+ reg = readl(priv->peri_ctrl + USB3_CTRL);
@@ -326407,8 +394739,8 @@ index 0000000..ab80fee
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -326447,13 +394779,13 @@ index 0000000..ab80fee
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
-+ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, 0x1000);
-+ if (!priv->sys_ctrl)
-+ goto err;
++ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, __4K__);
++ if (priv->sys_ctrl == NULL)
++ goto usb_unmap;
+
+ /*
+ * If HPM core less than or equal to FLAG, TX_SWING_COMP
@@ -326474,10 +394806,7 @@ index 0000000..ab80fee
+ writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
+
+ iounmap(priv->sys_ctrl);
-+ iounmap(priv->ctrl_base);
-+
-+ return;
-+err:
++usb_unmap:
+ iounmap(priv->ctrl_base);
+ return;
+}
@@ -326520,8 +394849,8 @@ index 0000000..ab80fee
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, 0x1000);
-+ if (!priv->sys_ctrl)
++ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, __4K__);
++ if (priv->sys_ctrl == NULL)
+ return;
+
+ /* U3 vcc reset */
@@ -326543,7 +394872,7 @@ index 0000000..ab80fee
+EXPORT_SYMBOL(hisi_usb3_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3521a-sata.c b/drivers/phy/hibvt/phy-hi3521a-sata.c
new file mode 100644
-index 0000000..ed3fc47
+index 0000000..33b10c4
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3521a-sata.c
@@ -0,0 +1,288 @@
@@ -326594,13 +394923,13 @@ index 0000000..ed3fc47
+ HISI_SATA_RX0_CKEN = BIT(5),
+ HISI_SATA_BUS_CKEN = BIT(4),
+ HISI_SATA_PORT01_CLK_EN = HISI_SATA_BUS_CKEN
-+ | HISI_SATA_RX0_CKEN
-+ | HISI_SATA_RX1_CKEN
-+ | HISI_SATA_CKO_ALIVE_CKEN
-+ | HISI_SATA_PORT0_MPLL_CKEN
-+ | HISI_SATA_PORT0_REFCLK_CKEN
-+ | HISI_SATA_PORT1_MPLL_CKEN
-+ | HISI_SATA_PORT1_REFCLK_CKEN,
++ | HISI_SATA_RX0_CKEN
++ | HISI_SATA_RX1_CKEN
++ | HISI_SATA_CKO_ALIVE_CKEN
++ | HISI_SATA_PORT0_MPLL_CKEN
++ | HISI_SATA_PORT0_REFCLK_CKEN
++ | HISI_SATA_PORT1_MPLL_CKEN
++ | HISI_SATA_PORT1_REFCLK_CKEN,
+
+ FIFOTH_VALUE = 0x66d9f24,
+ PHY_VALUE = 0x4900003d,
@@ -326695,9 +395024,9 @@ index 0000000..ed3fc47
+
+ tmp_val = readl((void *)HISI_SATA_PERI_CRG26);
+ tmp_val |= HISI_PHY1_REFCLK_SEL_100M
-+ | HISI_PHY0_REFCLK_SEL_100M
-+ | HISI_PHY1_REFCKEN
-+ | HISI_PHY0_REFCKEN;
++ | HISI_PHY0_REFCLK_SEL_100M
++ | HISI_PHY1_REFCKEN
++ | HISI_PHY0_REFCKEN;
+ writel(tmp_val, (void *)HISI_SATA_PERI_CRG26);
+}
+
@@ -326707,7 +395036,7 @@ index 0000000..ed3fc47
+
+ for (i = 0; i < ports_num; i++)
+ writel(FIFOTH_VALUE, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_FIFOTH));
++ + HISI_SATA_PORT_FIFOTH));
+}
+EXPORT_SYMBOL(hisi_sata_set_fifoth);
+
@@ -326725,7 +395054,7 @@ index 0000000..ed3fc47
+
+ for (i = 0; i < ports_num; i++)
+ writel(PHYCTL2_VALUE, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL2));
++ + HISI_SATA_PORT_PHYCTL2));
+
+ tmp_val = readl(mmio + HISI_SATA_PHY0_CTLL);
+ tmp_val |= HISI_SATA_PHY_REV_CLK;
@@ -326736,10 +395065,10 @@ index 0000000..ed3fc47
+
+ for (i = 0; i < ports_num; i++) {
+ tmp_val = readl(mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL2);
++ + HISI_SATA_PORT_PHYCTL2);
+ tmp_val &= ~HISI_SATA_LANE0_RESET;
+ writel(tmp_val, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL2));
++ + HISI_SATA_PORT_PHYCTL2));
+ }
+
+ tmp_val = readl(mmio + HISI_SATA_PHY0_CTLL);
@@ -326760,14 +395089,14 @@ index 0000000..ed3fc47
+ for (i = 0; i < ports_num; i++) {
+ tmp_val = PX_TX_AMPLITUDE;
+ writel(tmp_val, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL1));
++ + HISI_SATA_PORT_PHYCTL1));
+ }
+
+ /* set phy PX TX pre-emphasis */
+ for (i = 0; i < ports_num; i++) {
+ tmp_val = PX_TX_PREEMPH;
+ writel(tmp_val, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL2));
++ + HISI_SATA_PORT_PHYCTL2));
+ }
+
+ for (i = 0; i < ports_num; i++)
@@ -326775,10 +395104,10 @@ index 0000000..ed3fc47
+ + HISI_SATA_PORT_PHYCTL));
+ for (i = 0; i < ports_num; i++)
+ writel(PHY_FORCE_3G, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL));
++ + HISI_SATA_PORT_PHYCTL));
+ for (i = 0; i < ports_num; i++)
+ writel(PHY_FORCE_6G, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL));
++ + HISI_SATA_PORT_PHYCTL));
+
+ if (phy_mode == PHY_MODE_1_5G)
+ phy_config = PHY_SG_1_5G;
@@ -326789,7 +395118,7 @@ index 0000000..ed3fc47
+
+ for (i = 0; i < ports_num; i++)
+ writel(phy_config, (mmio + 0x100 + i*0x80
-+ + HISI_SATA_PORT_PHYCTL));
++ + HISI_SATA_PORT_PHYCTL));
+ mdelay(100);
+ writel(0x10000000, (void *)HISI_SATA_MISC_PHY0_CTRL0);
+ writel(0x10000001, (void *)HISI_SATA_MISC_PHY0_CTRL0);
@@ -326837,12 +395166,16 @@ index 0000000..ed3fc47
+}
diff --git a/drivers/phy/hibvt/phy-hi3521a-usb.c b/drivers/phy/hibvt/phy-hi3521a-usb.c
new file mode 100644
-index 0000000..92cca01
+index 0000000..0867448
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3521a-usb.c
-@@ -0,0 +1,117 @@
+@@ -0,0 +1,181 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * phy-hi3521a-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -326882,10 +395215,66 @@ index 0000000..92cca01
+#define USBOVR_P_CTRL (1 << 17)
+#define MISC_USB 0x54
+
++#define PHY_CLK_ENABLE 0x406
++#define OPEN_PHY_CLK 0x426
++
++#define EYE_PATTERN0 0xa
++#define EYE_VAL0 0xbb2a
++#define EYE_PATTERN1 0x5
++#define EYE_VAL1 0x9225
++#define EYE_PATTERN2 0x6
++#define EYE_VAL2 0x626
++#define EYE_PATTERN3 0x0
++#define EYE_VAL3 0x1820
++#define EYE_PATTERN4 0x10
++#define EYE_VAL4 0x1830
++#define EYE_PATTERN5 0x10
++#define EYE_VAL5 0x1c30
++
++void usb_eye_config(struct phy *phy)
++{
++ unsigned int reg;
++ struct hisi_priv *priv = phy_get_drvdata(phy);
++
++ /* usb2.0 phy eye pattern:Icomp = 212.5 RCOMP = 212.5 */
++ writel(EYE_PATTERN0, priv->misc_ctrl + MISC_USB);
++ udelay(U_LEVEL1);
++ writel(EYE_VAL0, priv->misc_ctrl + MISC_USB);
++ mdelay(M_LEVEL3);
++
++ writel(EYE_PATTERN1, priv->misc_ctrl + MISC_USB);
++ udelay(U_LEVEL1);
++ writel(EYE_VAL1, priv->misc_ctrl + MISC_USB);
++ mdelay(M_LEVEL3);
++
++ writel(EYE_PATTERN2, priv->misc_ctrl + MISC_USB);
++ udelay(U_LEVEL1);
++ writel(EYE_VAL2, priv->misc_ctrl + MISC_USB);
++ mdelay(M_LEVEL3);
++
++ /* close eop pre-emphasis */
++ writel(EYE_PATTERN3, priv->misc_ctrl + MISC_USB);
++ udelay(U_LEVEL1);
++ writel(EYE_VAL3, priv->misc_ctrl + MISC_USB);
++ mdelay(M_LEVEL3);
++
++ writel(EYE_PATTERN4, priv->misc_ctrl + MISC_USB);
++ udelay(U_LEVEL1);
++ writel(EYE_VAL4, priv->misc_ctrl + MISC_USB);
++ mdelay(M_LEVEL3);
++
++ /* open port1 pre-emphasis */
++ writel(EYE_PATTERN5, priv->misc_ctrl + MISC_USB);
++ udelay(U_LEVEL1);
++ writel(EYE_VAL5, priv->misc_ctrl + MISC_USB);
++ mdelay(M_LEVEL3);
++}
++
+void hisi_usb_phy_on(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
++
+ /* enable phy ref clk to enable phy */
+ reg = readl(priv->peri_ctrl + PERI_CRG28);
+ reg |= USB_CKEN;
@@ -326907,11 +395296,13 @@ index 0000000..92cca01
+ udelay(U_LEVEL7);
+
+ /* open phy clk */
-+ writel(0x406, priv->misc_ctrl + MISC_USB);
++ writel(PHY_CLK_ENABLE, priv->misc_ctrl + MISC_USB);
+ udelay(U_LEVEL1);
-+ writel(0x426, priv->misc_ctrl + MISC_USB);
++ writel(OPEN_PHY_CLK, priv->misc_ctrl + MISC_USB);
+ mdelay(M_LEVEL3);
+
++ usb_eye_config(phy);
++
+ /* cancel phy utmi reset */
+ reg = readl(priv->peri_ctrl + PERI_CRG28);
+ reg &= ~(USBPHY_PORT0_TREQ);
@@ -326932,11 +395323,13 @@ index 0000000..92cca01
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
-+ /* Disable EHCI clock.
-+ If the HS PHY is unused disable it too. */
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
++ /*
++ * Disable EHCI clock.
++ * If the HS PHY is unused disable it too.
++ */
+ reg = readl(priv->peri_ctrl + PERI_CRG28);
+ reg &= ~(USB_CKEN);
+ reg |= (USB_CTRL_UTMI0_REG);
@@ -326960,7 +395353,7 @@ index 0000000..92cca01
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3531a-sata.c b/drivers/phy/hibvt/phy-hi3531a-sata.c
new file mode 100644
-index 0000000..ef59cc8
+index 0000000..a88850e
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3531a-sata.c
@@ -0,0 +1,539 @@
@@ -327009,31 +395402,31 @@ index 0000000..ef59cc8
+ HISI_SATA_PHY1_REFCK1_SEL_25M = (0x1 << 14),
+ HISI_SATA_PHY1_REFCK1_SEL_24M = (0x0 << 14),
+ HISI_SATA_CLK_VALUE = HISI_SATA_PHY0_REF0_CKEN
-+ | HISI_SATA_PHY0_REF1_CKEN
-+ | HISI_SATA_PHY0_REFCK0_SEL_100M
-+ | HISI_SATA_PHY0_REFCK1_SEL_100M
-+ | HISI_SATA_PHY1_REF0_CKEN
-+ | HISI_SATA_PHY1_REF1_CKEN
-+ | HISI_SATA_PHY1_REFCK0_SEL_100M
-+ | HISI_SATA_PHY1_REFCK1_SEL_100M,
++ | HISI_SATA_PHY0_REF1_CKEN
++ | HISI_SATA_PHY0_REFCK0_SEL_100M
++ | HISI_SATA_PHY0_REFCK1_SEL_100M
++ | HISI_SATA_PHY1_REF0_CKEN
++ | HISI_SATA_PHY1_REF1_CKEN
++ | HISI_SATA_PHY1_REFCK0_SEL_100M
++ | HISI_SATA_PHY1_REFCK1_SEL_100M,
+
+ HISI_SATA_PHY0A_RST = BIT(2),
+ HISI_SATA_PHY0B_RST = BIT(3),
+ HISI_SATA_PHY1A_RST = BIT(10),
+ HISI_SATA_PHY1B_RST = BIT(11),
+ HISI_SATA_PHY0_RST = HISI_SATA_PHY0A_RST
-+ | HISI_SATA_PHY0B_RST,
++ | HISI_SATA_PHY0B_RST,
+ HISI_SATA_PHY1_RST = HISI_SATA_PHY1A_RST
-+ | HISI_SATA_PHY1B_RST,
++ | HISI_SATA_PHY1B_RST,
+
+ HISI_SATA_PHY0A_RST_MASK = BIT(7),
+ HISI_SATA_PHY0B_RST_MASK = BIT(6),
+ HISI_SATA_PHY1A_RST_MASK = BIT(5),
+ HISI_SATA_PHY1B_RST_MASK = BIT(4),
+ HISI_SATA_PHY0_RST_MASK = HISI_SATA_PHY0A_RST_MASK
-+ | HISI_SATA_PHY0B_RST_MASK,
++ | HISI_SATA_PHY0B_RST_MASK,
+ HISI_SATA_PHY1_RST_MASK = HISI_SATA_PHY1A_RST_MASK
-+ | HISI_SATA_PHY1B_RST_MASK,
++ | HISI_SATA_PHY1B_RST_MASK,
+
+ HISI_SATA_PERI_CRG74 = (HISI_SATA_PERI_CTRL + 0x128),
+
@@ -327085,42 +395478,42 @@ index 0000000..ef59cc8
+ mode = (tmp_val >> HISI_SATA_PCIE_MODE_SHIFT) & 0xf;
+
+ switch (mode) {
-+ case 0x0:
-+ ports_num = 4;
-+ sata_port_map = 0xf;
-+ break;
++ case 0x0:
++ ports_num = 4;
++ sata_port_map = 0xf;
++ break;
+
-+ case 0x1:
-+ ports_num = 3;
-+ sata_port_map = 0x7;
-+ break;
++ case 0x1:
++ ports_num = 3;
++ sata_port_map = 0x7;
++ break;
+
-+ case 0x8:
-+ ports_num = 3;
-+ sata_port_map = 0xe;
-+ break;
++ case 0x8:
++ ports_num = 3;
++ sata_port_map = 0xe;
++ break;
+
-+ case 0x2:
-+ case 0x3:
-+ ports_num = 2;
-+ sata_port_map = 0x3;
-+ break;
++ case 0x2:
++ case 0x3:
++ ports_num = 2;
++ sata_port_map = 0x3;
++ break;
+
-+ case 0x9:
-+ ports_num = 2;
-+ sata_port_map = 0x6;
-+ break;
++ case 0x9:
++ ports_num = 2;
++ sata_port_map = 0x6;
++ break;
+
-+ case 0xa:
-+ case 0xb:
-+ ports_num = 1;
-+ sata_port_map = 0x2;
-+ break;
++ case 0xa:
++ case 0xb:
++ ports_num = 1;
++ sata_port_map = 0x2;
++ break;
+
-+ default:
-+ ports_num = 0;
-+ sata_port_map = 0x0;
-+ break;
++ default:
++ ports_num = 0;
++ sata_port_map = 0x0;
++ break;
+ }
+
+ mplx_port0 = (mode & 0x8) ? 1 : 0;
@@ -327142,16 +395535,16 @@ index 0000000..ef59cc8
+
+ if (port_no == 0) {
+ tmp_val |= HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ;
++ | HISI_SATA0_SRST_REQ;
+ } else if (port_no == 1) {
+ tmp_val |= HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ;
++ | HISI_SATA1_SRST_REQ;
+ } else if (port_no == 2) {
+ tmp_val |= HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ;
++ | HISI_SATA2_SRST_REQ;
+ } else if (port_no == 3) {
+ tmp_val |= HISI_SATA_RX3_SRST_REQ
-+ | HISI_SATA3_SRST_REQ;
++ | HISI_SATA3_SRST_REQ;
+ }
+
+ writel(tmp_val, (void *)HISI_SATA_PERI_CRG74);
@@ -327166,16 +395559,16 @@ index 0000000..ef59cc8
+
+ if (port_no == 0) {
+ tmp_val &= ~(HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ);
++ | HISI_SATA0_SRST_REQ);
+ } else if (port_no == 1) {
+ tmp_val &= ~(HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ);
++ | HISI_SATA1_SRST_REQ);
+ } else if (port_no == 2) {
+ tmp_val &= ~(HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ);
++ | HISI_SATA2_SRST_REQ);
+ } else if (port_no == 3) {
+ tmp_val &= ~(HISI_SATA_RX3_SRST_REQ
-+ | HISI_SATA3_SRST_REQ);
++ | HISI_SATA3_SRST_REQ);
+ }
+
+ writel(tmp_val, (void *)HISI_SATA_PERI_CRG74);
@@ -327192,44 +395585,44 @@ index 0000000..ef59cc8
+
+ if (ports_num == 4) {
+ tmp_val |= HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ
-+ | HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ
-+ | HISI_SATA_RX3_SRST_REQ
-+ | HISI_SATA3_SRST_REQ;
++ | HISI_SATA0_SRST_REQ
++ | HISI_SATA_RX1_SRST_REQ
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ
++ | HISI_SATA_RX3_SRST_REQ
++ | HISI_SATA3_SRST_REQ;
+ } else if (ports_num == 3) {
+ if (mplx_port0) {
+ tmp_val |= HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ
-+ | HISI_SATA_RX3_SRST_REQ
-+ | HISI_SATA3_SRST_REQ;
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ
++ | HISI_SATA_RX3_SRST_REQ
++ | HISI_SATA3_SRST_REQ;
+ } else {
+ tmp_val |= HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ
-+ | HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ;
++ | HISI_SATA0_SRST_REQ
++ | HISI_SATA_RX1_SRST_REQ
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ;
+ }
+ } else if (ports_num == 2) {
+ if (mplx_port0) {
+ tmp_val |= HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ;
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ;
+ } else {
+ tmp_val |= HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ
-+ | HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ;
++ | HISI_SATA0_SRST_REQ
++ | HISI_SATA_RX1_SRST_REQ
++ | HISI_SATA1_SRST_REQ;
+ }
+ } else if (ports_num == 1) {
+ tmp_val |= HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ;
++ | HISI_SATA1_SRST_REQ;
+ }
+
+ writel(tmp_val, (void *)HISI_SATA_PERI_CRG74);
@@ -327245,44 +395638,44 @@ index 0000000..ef59cc8
+
+ if (ports_num == 4) {
+ tmp_val &= ~(HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ
-+ | HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ
-+ | HISI_SATA_RX3_SRST_REQ
-+ | HISI_SATA3_SRST_REQ);
++ | HISI_SATA0_SRST_REQ
++ | HISI_SATA_RX1_SRST_REQ
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ
++ | HISI_SATA_RX3_SRST_REQ
++ | HISI_SATA3_SRST_REQ);
+ } else if (ports_num == 3) {
+ if (mplx_port0) {
+ tmp_val &= ~(HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ
-+ | HISI_SATA_RX3_SRST_REQ
-+ | HISI_SATA3_SRST_REQ);
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ
++ | HISI_SATA_RX3_SRST_REQ
++ | HISI_SATA3_SRST_REQ);
+ } else {
+ tmp_val &= ~(HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ
-+ | HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ);
++ | HISI_SATA0_SRST_REQ
++ | HISI_SATA_RX1_SRST_REQ
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ);
+ }
+ } else if (ports_num == 2) {
+ if (mplx_port0) {
+ tmp_val &= ~(HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ
-+ | HISI_SATA_RX2_SRST_REQ
-+ | HISI_SATA2_SRST_REQ);
++ | HISI_SATA1_SRST_REQ
++ | HISI_SATA_RX2_SRST_REQ
++ | HISI_SATA2_SRST_REQ);
+ } else {
+ tmp_val &= ~(HISI_SATA_RX0_SRST_REQ
-+ | HISI_SATA0_SRST_REQ
-+ | HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ);
++ | HISI_SATA0_SRST_REQ
++ | HISI_SATA_RX1_SRST_REQ
++ | HISI_SATA1_SRST_REQ);
+ }
+ } else if (ports_num == 1) {
+ tmp_val &= ~(HISI_SATA_RX1_SRST_REQ
-+ | HISI_SATA1_SRST_REQ);
++ | HISI_SATA1_SRST_REQ);
+ }
+
+ writel(tmp_val, (void *)HISI_SATA_PERI_CRG74);
@@ -327370,7 +395763,7 @@ index 0000000..ef59cc8
+ port_no++;
+
+ writel(HISI_SATA_FIFOTH_VALUE, (mmio + 0x100 + port_no*0x80
-+ + HISI_SATA_PORT_FIFOTH));
++ + HISI_SATA_PORT_FIFOTH));
+ }
+}
+EXPORT_SYMBOL(hisi_sata_set_fifoth);
@@ -327497,20 +395890,24 @@ index 0000000..ef59cc8
+ port_no++;
+
+ writel(phy_config, (mmio + 0x100 + port_no*0x80
-+ + HISI_SATA_PORT_PHYCTL));
++ + HISI_SATA_PORT_PHYCTL));
+
+ writel(phy_sg, (mmio + 0x100 + port_no*0x80
-+ + HISI_SATA_PORT_PHYCTL1));
++ + HISI_SATA_PORT_PHYCTL1));
+ }
+}
diff --git a/drivers/phy/hibvt/phy-hi3536d-usb.c b/drivers/phy/hibvt/phy-hi3536d-usb.c
new file mode 100644
-index 0000000..979774c
+index 0000000..60464fd
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3536d-usb.c
-@@ -0,0 +1,216 @@
+@@ -0,0 +1,220 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * phy-hi3536d-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2017-2018. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -327619,31 +396016,31 @@ index 0000000..979774c
+
+void usb_trim_config(struct phy *phy)
+{
-+ int reg, trim_reg;
++ unsigned int reg, trim_reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* Trim config */
+ reg = readl(priv->misc_ctrl + MISC_CTRL_TRIM);
+ reg &= (MISC_CTRL_23 | MISC_CTRL_24 | MISC_CTRL_25 | MISC_CTRL_26 |
-+ MISC_CTRL_27);
++ MISC_CTRL_27);
+ reg = usb_r_tuning_val(reg);
+ if (reg) {
+ trim_reg = readl(priv->misc_ctrl + USB_R_TUNING_1);
+ trim_reg &= ~(TRIM_CONFIG_2 | TRIM_CONFIG_3 | TRIM_CONFIG_4 |
-+ TRIM_CONFIG_5 | TRIM_CONFIG_6);
++ TRIM_CONFIG_5 | TRIM_CONFIG_6);
+ trim_reg |= reg;
+ writel(trim_reg, priv->misc_ctrl + USB_R_TUNING_1);
+
+ trim_reg = readl(priv->misc_ctrl + USB_R_TUNING_2);
+ trim_reg &= ~(TRIM_CONFIG_2 | TRIM_CONFIG_3 | TRIM_CONFIG_4 |
-+ TRIM_CONFIG_5 | TRIM_CONFIG_6);
++ TRIM_CONFIG_5 | TRIM_CONFIG_6);
+ trim_reg |= reg;
+ writel(trim_reg, priv->misc_ctrl + USB_R_TUNING_2);
+ }
+}
+void hisi_usb_phy_on(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* misc ctrl */
@@ -327655,7 +396052,7 @@ index 0000000..979774c
+ /* reset enable */
+ reg = readl(priv->peri_ctrl + USB2_CTRL);
+ reg |= (USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
-+ USB2_HST_PHY_SYST_REQ | USB2_UTMI1_SRST_REQ);
++ USB2_HST_PHY_SYST_REQ | USB2_UTMI1_SRST_REQ);
+ writel(reg, priv->peri_ctrl + USB2_CTRL);
+ udelay(U_LEVEL6);
+
@@ -327689,9 +396086,9 @@ index 0000000..979774c
+ /* cancel control reset */
+ reg = readl(priv->peri_ctrl + USB2_CTRL);
+ reg &= ~(USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
-+ USB2_HST_PHY_SYST_REQ | USB2_UTMI1_SRST_REQ);
++ USB2_HST_PHY_SYST_REQ | USB2_UTMI1_SRST_REQ);
+ reg |= (USB2_BUS_CKEN | USB2_OHCI48M_CKEN | USB2_OHCI12M_CKEN |
-+ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN | USB2_UTMI1_CKEN);
++ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN | USB2_UTMI1_CKEN);
+ writel(reg, priv->peri_ctrl + USB2_CTRL);
+ udelay(U_LEVEL6);
+
@@ -327703,7 +396100,7 @@ index 0000000..979774c
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->peri_ctrl + REG_USB2_PHY0);
@@ -327720,14 +396117,14 @@ index 0000000..979774c
+ /* close clock */
+ reg = readl(priv->peri_ctrl + USB2_CTRL);
+ reg &= ~(USB2_BUS_CKEN | USB2_OHCI48M_CKEN | USB2_OHCI12M_CKEN |
-+ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN | USB2_UTMI1_CKEN);
++ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN | USB2_UTMI1_CKEN);
+ writel(reg, priv->peri_ctrl + USB2_CTRL);
+ udelay(U_LEVEL6);
+}
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3536dv100-sata.c b/drivers/phy/hibvt/phy-hi3536dv100-sata.c
new file mode 100644
-index 0000000..ad49d19
+index 0000000..1351a73
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3536dv100-sata.c
@@ -0,0 +1,208 @@
@@ -327822,7 +396219,7 @@ index 0000000..ad49d19
+ tmp_val = readl((void *)HISI_SATA_PERI_CRG45);
+
+ tmp_val |= HISI_SATA_BUS_SRST_REQ | HISI_SATA_CKO_ALIVE_SRST_REQ
-+ | HISI_SATA_RX0_SRST_REQ | HISI_SATA0_SRST_REQ;
++ | HISI_SATA_RX0_SRST_REQ | HISI_SATA0_SRST_REQ;
+ writel(tmp_val, (void *)HISI_SATA_PERI_CRG45);
+}
+
@@ -327833,7 +396230,7 @@ index 0000000..ad49d19
+ tmp_val = readl((void *)HISI_SATA_PERI_CRG45);
+
+ tmp_val &= ~(HISI_SATA_BUS_SRST_REQ | HISI_SATA_CKO_ALIVE_SRST_REQ
-+ | HISI_SATA_RX0_SRST_REQ | HISI_SATA0_SRST_REQ);
++ | HISI_SATA_RX0_SRST_REQ | HISI_SATA0_SRST_REQ);
+
+ writel(tmp_val, (void *)HISI_SATA_PERI_CRG45);
+}
@@ -327941,12 +396338,16 @@ index 0000000..ad49d19
+}
diff --git a/drivers/phy/hibvt/phy-hi3556av100-usb.c b/drivers/phy/hibvt/phy-hi3556av100-usb.c
new file mode 100644
-index 0000000..d986779
+index 0000000..2722355
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3556av100-usb.c
-@@ -0,0 +1,442 @@
+@@ -0,0 +1,446 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
++ * phy-hi3556av100-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -328047,6 +396448,9 @@ index 0000000..d986779
+#define USB2_DEF_CRG 0x00001301
+#define USB2_DEF_CFG_MASK 0x0000ffff
+
++#define COMBPHY_IN_USE 0x1
++#define COMBPHY_NO_IN_USE 0x0
++
+void hisi_usb_crg_config(struct phy *phy)
+{
+ unsigned int reg;
@@ -328101,8 +396505,8 @@ index 0000000..d986779
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(USB2_CTRL_REGBASE, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(USB2_CTRL_REGBASE, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -328152,8 +396556,8 @@ index 0000000..d986779
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, 0x1000);
-+ if (!priv->sys_ctrl)
++ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, __4K__);
++ if (priv->sys_ctrl == NULL)
+ return;
+
+ if (rst) {
@@ -328213,7 +396617,7 @@ index 0000000..d986779
+ writel(reg, priv->misc_ctrl + PORT0_CTRL);
+ udelay(U_LEVEL5);
+
-+ usb_combphy_config(phy, 1);
++ usb_combphy_config(phy, COMBPHY_IN_USE);
+
+ /* release TPOR default release */
+ reg = readl(priv->peri_ctrl + USB2_PHY);
@@ -328239,7 +396643,7 @@ index 0000000..d986779
+ writel(reg, priv->peri_ctrl + USB2_PHY);
+ udelay(U_LEVEL6);
+
-+ usb_combphy_config(phy, 0);
++ usb_combphy_config(phy, COMBPHY_NO_IN_USE);
+
+ /* config U3 Controller release */
+ reg = readl(priv->peri_ctrl + USB3_CTRL);
@@ -328253,8 +396657,8 @@ index 0000000..d986779
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -328293,13 +396697,13 @@ index 0000000..d986779
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
-+ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, 0x1000);
-+ if (!priv->sys_ctrl)
-+ goto err;
++ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, __4K__);
++ if (priv->sys_ctrl == NULL)
++ goto usb_unmap;
+
+ /*
+ * If HPM core less than or equal to FLAG, TX_SWING_COMP
@@ -328320,10 +396724,7 @@ index 0000000..d986779
+ writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
+
+ iounmap(priv->sys_ctrl);
-+ iounmap(priv->ctrl_base);
-+
-+ return;
-+err:
++usb_unmap:
+ iounmap(priv->ctrl_base);
+ return;
+}
@@ -328366,8 +396767,8 @@ index 0000000..d986779
+ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, 0x1000);
-+ if (!priv->sys_ctrl)
++ priv->sys_ctrl = ioremap_nocache(SYSCTRL_REGBASE, __4K__);
++ if (priv->sys_ctrl == NULL)
+ return;
+
+ /* U3 vcc reset */
@@ -328389,12 +396790,16 @@ index 0000000..d986779
+EXPORT_SYMBOL(hisi_usb3_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3556v200-usb.c b/drivers/phy/hibvt/phy-hi3556v200-usb.c
new file mode 100644
-index 0000000..90d4435
+index 0000000..a9c9d19
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3556v200-usb.c
-@@ -0,0 +1,304 @@
+@@ -0,0 +1,310 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
++ * phy-hi3556v200-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -328489,8 +396894,8 @@ index 0000000..90d4435
+
+static void usb_vbus_multi_gpio(void)
+{
-+ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, 0x100);
-+ if (!vbus)
++ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, __1K__);
++ if (vbus == NULL)
+ return;
+
+ writel(USB2_VBUS_IO_VAL, vbus + USB2_VBUS_IO_OFFSET);
@@ -328501,17 +396906,17 @@ index 0000000..90d4435
+
+static void usb_trim_c(void)
+{
-+ int reg;
-+ int trim_val;
-+ void __iomem *inno_clk_output;
-+ void __iomem *usb_trim;
++ unsigned int reg;
++ unsigned int trim_val;
++ void __iomem *inno_clk_output = NULL;
++ void __iomem *usb_trim = NULL;
+
-+ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_clk_output)
++ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_clk_output == NULL)
+ return;
+
-+ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, 0x100);
-+ if (!usb_trim)
++ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, __1K__);
++ if (usb_trim == NULL)
+ goto free;
+
+ /* set inno phy output clock */
@@ -328541,7 +396946,7 @@ index 0000000..90d4435
+
+static void usb_crg_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb phy reset */
@@ -328596,11 +397001,11 @@ index 0000000..90d4435
+
+static void usb_ctrl_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -328623,7 +397028,7 @@ index 0000000..90d4435
+
+ reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
+ reg &= ~PCS_SSP_SOFT_RESET;
-+ reg &= ~PORT_DISABLE_SUSPEND; // disable suspend
++ reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */
+ writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
+ udelay(U_LEVEL2);
+
@@ -328636,10 +397041,11 @@ index 0000000..90d4435
+
+static void usb_eye_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
++ void __iomem *inno_base = NULL;
+
-+ void __iomem *inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_base)
++ inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_base == NULL)
+ return;
+
+ /* HS eye height tuning */
@@ -328671,6 +397077,7 @@ index 0000000..90d4435
+ reg &= ~DISCONNECT_TRIGGER_MASK;
+ reg |= DISCONNECT_TRIGGER_VAL;
+ writel(reg, inno_base + DISCONNECT_TRIGGER_OFFSET);
++ iounmap(inno_base);
+}
+
+void hisi_usb_phy_on(struct phy *phy)
@@ -328687,7 +397094,7 @@ index 0000000..90d4435
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb2 vcc reset */
@@ -328699,12 +397106,16 @@ index 0000000..90d4435
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hi3559av100-usb.c b/drivers/phy/hibvt/phy-hi3559av100-usb.c
new file mode 100644
-index 0000000..c32393a
+index 0000000..e98489b
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3559av100-usb.c
-@@ -0,0 +1,385 @@
+@@ -0,0 +1,394 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * phy-hi3559av100-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -328797,19 +397208,18 @@ index 0000000..c32393a
+
+#define USB3_PORT1_CLK (0x1 << 14)
+
++#define COMBPHY_IN_USE 0x1
++#define COMBPHY_NO_IN_USE 0x0
++
++#define IS_CTRL1 1 /* ctrl1 init need offset */
+#define U2_CRG_OFFSET 1
+#define U3_CRG_OFFSET 16
+
+static combphy_mode mode_flag;
+
-+void hisi_switch_func(int otg)
-+{
-+}
-+EXPORT_SYMBOL(hisi_switch_func);
-+
+static void get_combphy_mode(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->combphy_base + SYSSTAT);
@@ -328817,13 +397227,13 @@ index 0000000..c32393a
+
+ switch (reg) {
+ case PCIE_X2_MODE:
-+ mode_flag = 0;
++ mode_flag = PCIE_X2;
+ break;
+ case PCIE_X1_MODE:
-+ mode_flag = 1;
++ mode_flag = PCIE_X1;
+ break;
+ case USB3_MODE:
-+ mode_flag = 2;
++ mode_flag = USB3;
+ break;
+ default:
+ break;
@@ -328891,7 +397301,7 @@ index 0000000..c32393a
+ writel(reg, priv->peri_ctrl + USB3_CTRL);
+ udelay(U_LEVEL8);
+
-+ usb_combphy_config(phy, u3_offset, 1);
++ usb_combphy_config(phy, u3_offset, COMBPHY_IN_USE);
+
+ /* enable port0 ss */
+ reg = readl(priv->misc_ctrl + USB_PORT0);
@@ -328927,7 +397337,7 @@ index 0000000..c32393a
+ writel(reg, priv->peri_ctrl + USB2_PHY);
+ udelay(U_LEVEL6);
+
-+ usb_combphy_config(phy, u3_offset, 0);
++ usb_combphy_config(phy, u3_offset, COMBPHY_NO_IN_USE);
+
+ /* config U3 Controller USB3_0 PHY OUTPUT */
+ reg = readl(priv->peri_ctrl + USB3_CTRL);
@@ -328938,7 +397348,7 @@ index 0000000..c32393a
+
+static void hisi_usb3_ctrl_config(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -328961,7 +397371,7 @@ index 0000000..c32393a
+
+ reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
+ reg &= ~PCS_SSP_SOFT_RESET;
-+ reg &= ~SUSPEND_USB3_SS_PHY; // disable suspend
++ reg &= ~SUSPEND_USB3_SS_PHY; /* disable suspend */
+ writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
+ udelay(U_LEVEL2);
+
@@ -328977,11 +397387,12 @@ index 0000000..c32393a
+
+static void hisi_usb3_eye_config(struct phy *phy)
+{
-+ int reg;
-+ struct hisi_priv *priv = phy_get_drvdata(phy);
-+ void __iomem *otp_reg = ioremap_nocache(OTP_CPU_REGBASE, 0x1000);
++ unsigned int reg;
++ void __iomem *otp_reg = NULL;
++ struct hisi_priv *priv = phy_get_drvdata(phy);;
+
-+ if (!otp_reg)
++ otp_reg = ioremap_nocache(OTP_CPU_REGBASE, __4K__);
++ if (otp_reg == NULL)
+ return;
+
+ /* Port0 usb2 phy0 misc ctrl */
@@ -329029,7 +397440,7 @@ index 0000000..c32393a
+ unsigned int u3 = 0;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ if (priv->phyid == 1) {
++ if (priv->phyid == IS_CTRL1) {
+ u2 = U2_CRG_OFFSET;
+ u3 = U3_CRG_OFFSET;
+ }
@@ -329050,7 +397461,7 @@ index 0000000..c32393a
+ unsigned int usb3_offset = 0;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ if (priv->phyid == 1)
++ if (priv->phyid == IS_CTRL1)
+ usb3_offset = U3_CRG_OFFSET;
+
+ reg = readl(priv->peri_ctrl + USB3_CTRL);
@@ -329074,28 +397485,37 @@ index 0000000..c32393a
+{
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->combphy_base = of_iomap(np, 2);
-+ if (IS_ERR(priv->combphy_base))
-+ priv->combphy_base = NULL;
-+
-+ priv->ctrl_base = of_iomap(np, 3);
++ priv->ctrl_base = of_iomap(np, CTRL_REGBASE_NODE_IDX);
+ if (IS_ERR(priv->ctrl_base))
-+ priv->ctrl_base = NULL;
++ return PTR_ERR(priv->ctrl_base);
+
-+ if (of_property_read_u32(np, "phyid", &priv->phyid))
++ priv->combphy_base = of_iomap(np, PHY_REGBASE_NODE_IDX);
++ if (IS_ERR(priv->combphy_base)) {
++ iounmap(priv->ctrl_base);
++ return PTR_ERR(priv->combphy_base);
++ }
++
++ if (of_property_read_u32(np, "phyid", &priv->phyid)) {
++ iounmap(priv->combphy_base);
++ iounmap(priv->ctrl_base);
+ return -EINVAL;
++ }
+
+ return 0;
+}
+EXPORT_SYMBOL(hisi_usb3_init_para);
diff --git a/drivers/phy/hibvt/phy-hi3559v200-usb.c b/drivers/phy/hibvt/phy-hi3559v200-usb.c
new file mode 100644
-index 0000000..90d4435
+index 0000000..6b5211e
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hi3559v200-usb.c
-@@ -0,0 +1,304 @@
+@@ -0,0 +1,310 @@
+/*
-+ * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
++ * phy-hi3559v200-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -329190,8 +397610,8 @@ index 0000000..90d4435
+
+static void usb_vbus_multi_gpio(void)
+{
-+ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, 0x100);
-+ if (!vbus)
++ void __iomem *vbus = ioremap_nocache(USB2_VBUS_IO_BASE_REG, __1K__);
++ if (vbus == NULL)
+ return;
+
+ writel(USB2_VBUS_IO_VAL, vbus + USB2_VBUS_IO_OFFSET);
@@ -329202,17 +397622,17 @@ index 0000000..90d4435
+
+static void usb_trim_c(void)
+{
-+ int reg;
-+ int trim_val;
-+ void __iomem *inno_clk_output;
-+ void __iomem *usb_trim;
++ unsigned int reg;
++ unsigned int trim_val;
++ void __iomem *inno_clk_output = NULL;
++ void __iomem *usb_trim = NULL;
+
-+ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_clk_output)
++ inno_clk_output = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_clk_output == NULL)
+ return;
+
-+ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, 0x100);
-+ if (!usb_trim)
++ usb_trim = ioremap_nocache(USB_TRIM_BASE_REG, __1K__);
++ if (usb_trim == NULL)
+ goto free;
+
+ /* set inno phy output clock */
@@ -329242,7 +397662,7 @@ index 0000000..90d4435
+
+static void usb_crg_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb phy reset */
@@ -329297,11 +397717,11 @@ index 0000000..90d4435
+
+static void usb_ctrl_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
-+ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, 0x10000);
-+ if (!priv->ctrl_base)
++ priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
++ if (priv->ctrl_base == NULL)
+ return;
+
+ reg = readl(priv->ctrl_base + REG_GUCTL1);
@@ -329324,7 +397744,7 @@ index 0000000..90d4435
+
+ reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
+ reg &= ~PCS_SSP_SOFT_RESET;
-+ reg &= ~PORT_DISABLE_SUSPEND; // disable suspend
++ reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */
+ writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
+ udelay(U_LEVEL2);
+
@@ -329337,10 +397757,11 @@ index 0000000..90d4435
+
+static void usb_eye_c(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
++ void __iomem *inno_base = NULL;
+
-+ void __iomem *inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, 0x100);
-+ if (!inno_base)
++ inno_base = ioremap_nocache(USB2_INNO_PHY_BASE_REG, __1K__);
++ if (inno_base == NULL)
+ return;
+
+ /* HS eye height tuning */
@@ -329372,6 +397793,7 @@ index 0000000..90d4435
+ reg &= ~DISCONNECT_TRIGGER_MASK;
+ reg |= DISCONNECT_TRIGGER_VAL;
+ writel(reg, inno_base + DISCONNECT_TRIGGER_OFFSET);
++ iounmap(inno_base);
+}
+
+void hisi_usb_phy_on(struct phy *phy)
@@ -329388,7 +397810,7 @@ index 0000000..90d4435
+
+void hisi_usb_phy_off(struct phy *phy)
+{
-+ int reg;
++ unsigned int reg;
+ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ /* usb2 vcc reset */
@@ -329400,7 +397822,7 @@ index 0000000..90d4435
+EXPORT_SYMBOL(hisi_usb_phy_off);
diff --git a/drivers/phy/hibvt/phy-hisi-sata.c b/drivers/phy/hibvt/phy-hisi-sata.c
new file mode 100644
-index 0000000..86bedbe
+index 0000000..2acb268
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hisi-sata.c
@@ -0,0 +1,171 @@
@@ -329500,10 +397922,10 @@ index 0000000..86bedbe
+
+static int hisi_sata_phy_probe(struct platform_device *pdev)
+{
-+ struct phy_provider *phy_provider;
++ struct phy_provider *phy_provider = NULL;
+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ struct phy *phy;
++ struct resource *res = NULL;
++ struct phy *phy = NULL;
+ void __iomem *mmio;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -329534,7 +397956,7 @@ index 0000000..86bedbe
+}
+
+static int hisi_sata_phy_suspend(struct platform_device *pdev,
-+ pm_message_t state)
++ pm_message_t state)
+{
+ struct device *dev = &pdev->dev;
+ struct phy *phy = to_phy(dev);
@@ -329621,12 +398043,16 @@ index 0000000..a767c68
+};
diff --git a/drivers/phy/hibvt/phy-hisi-usb.c b/drivers/phy/hibvt/phy-hisi-usb.c
new file mode 100644
-index 0000000..5cbe38e
+index 0000000..4c47517
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hisi-usb.c
-@@ -0,0 +1,110 @@
+@@ -0,0 +1,146 @@
+/*
-+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
++ * phy-hisi-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2017-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -329649,45 +398075,78 @@ index 0000000..5cbe38e
+
+#include "phy-hisi-usb.h"
+
++static int hisi_usb_iomap(struct device_node *np, struct hisi_priv *priv)
++{
++ if ((np == NULL) || (priv == NULL))
++ return -EINVAL;
++
++ priv->peri_ctrl = of_iomap(np, CRG_REGBASE_NODE_IDX);
++ if (IS_ERR(priv->peri_ctrl))
++ return PTR_ERR(priv->peri_ctrl);
++
++ priv->misc_ctrl = of_iomap(np, MISC_REGBASE_NODE_IDX);
++ if (IS_ERR(priv->misc_ctrl)) {
++ iounmap(priv->peri_ctrl);
++ return PTR_ERR(priv->misc_ctrl);
++ }
++
++ return 0;
++}
++
+static int hisi_usb_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
-+ struct phy *phy;
-+ struct hisi_priv *priv;
++ struct phy *phy = NULL;
++ struct hisi_priv *priv = NULL;
+ struct device_node *np = pdev->dev.of_node;
++ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
++ if (priv == NULL)
+ return -ENOMEM;
+
-+ priv->peri_ctrl = of_iomap(np, 0);
-+ if (IS_ERR(priv->peri_ctrl))
-+ priv->peri_ctrl = NULL;
-+
-+ priv->misc_ctrl = of_iomap(np, 1);
-+ if (IS_ERR(priv->misc_ctrl))
-+ priv->misc_ctrl = NULL;
-+
-+ priv->switch_base = of_iomap(np, 2);
-+ if (IS_ERR(priv->switch_base))
-+ priv->switch_base = NULL;
-+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
-+ if (!phy)
++ if (phy == NULL) {
++ devm_kfree(dev, priv);
++ priv = NULL;
+ return -ENOMEM;
++ }
++
++ ret = hisi_usb_iomap(np, priv);
++ if (ret)
++ goto usb2_unmap;
+
+ platform_set_drvdata(pdev, phy);
+ phy_set_drvdata(phy, priv);
+ hisi_usb_phy_on(phy);
+
++ iounmap(priv->misc_ctrl);
++ iounmap(priv->peri_ctrl);
++
+ return 0;
++usb2_unmap:
++ devm_kfree(dev, priv);
++ priv = NULL;
++
++ devm_kfree(dev, phy);
++ phy = NULL;
++
++ return ret;
+}
+
+static int hisi_usb_phy_remove(struct platform_device *pdev)
+{
++ struct device *dev = &pdev->dev;
+ struct phy *phy = dev_get_drvdata(&pdev->dev);
++ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ hisi_usb_phy_off(phy);
++
++ devm_kfree(dev, priv);
++ priv = NULL;
++
++ devm_kfree(dev, phy);
++ phy = NULL;
+ return 0;
+}
+
@@ -329718,7 +398177,7 @@ index 0000000..5cbe38e
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(hisi_usb2_pm_ops, hisi_usb_phy_suspend,
-+ hisi_usb_phy_resume);
++ hisi_usb_phy_resume);
+
+static struct platform_driver hisi_usb_phy_driver = {
+ .probe = hisi_usb_phy_probe,
@@ -329731,18 +398190,21 @@ index 0000000..5cbe38e
+};
+module_platform_driver(hisi_usb_phy_driver);
+
-+MODULE_AUTHOR("Pengcheng Li <lpc.li@hisilicon.com>");
+MODULE_DESCRIPTION("HISILICON USB PHY driver");
+MODULE_ALIAS("platform:hisi-usb-phy");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/hibvt/phy-hisi-usb.h b/drivers/phy/hibvt/phy-hisi-usb.h
new file mode 100644
-index 0000000..4b72697
+index 0000000..426932a
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hisi-usb.h
-@@ -0,0 +1,63 @@
+@@ -0,0 +1,78 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * phy-hisi-usb.h
++ *
++ * The headerfile with USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -329766,7 +398228,7 @@ index 0000000..4b72697
+extern void hisi_usb3_phy_on(struct phy *phy);
+extern void hisi_usb3_phy_off(struct phy *phy);
+
-+#if defined(CONFIG_ARCH_HI3559AV100)
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+extern int hisi_usb3_init_para(struct phy *phy, struct device_node *np);
+#endif
+
@@ -329803,15 +398265,30 @@ index 0000000..4b72697
+#define M_LEVEL6 100
+#define M_LEVEL7 200
+
-+#endif
++#define __1K__ 0x400
++#define __2K__ 0x800
++#define __4K__ 0x1000
++#define __8K__ 0x2000
++#define __64K__ 0x10000
++
++#define CRG_REGBASE_NODE_IDX 0
++#define MISC_REGBASE_NODE_IDX 1
++#define CTRL_REGBASE_NODE_IDX 2
++#define PHY_REGBASE_NODE_IDX 3
++
++#endif /* USB2_INCLUDE_PHY_H */
diff --git a/drivers/phy/hibvt/phy-hisi-usb3.c b/drivers/phy/hibvt/phy-hisi-usb3.c
new file mode 100644
-index 0000000..dc874c7
+index 0000000..fca88ff
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hisi-usb3.c
-@@ -0,0 +1,115 @@
+@@ -0,0 +1,169 @@
+/*
-+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
++ * phy-hisi-usb3.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -329834,48 +398311,98 @@ index 0000000..dc874c7
+
+#include "phy-hisi-usb.h"
+
++static int hisi_usb3_iomap(struct device_node *np, struct hisi_priv *priv)
++{
++ if ((np == NULL) || (priv == NULL))
++ return -EINVAL;
++
++ priv->peri_ctrl = of_iomap(np, CRG_REGBASE_NODE_IDX);
++ if (IS_ERR(priv->peri_ctrl))
++ return PTR_ERR(priv->peri_ctrl);
++
++ priv->misc_ctrl = of_iomap(np, MISC_REGBASE_NODE_IDX);
++ if (IS_ERR(priv->misc_ctrl)) {
++ iounmap(priv->peri_ctrl);
++ return PTR_ERR(priv->misc_ctrl);
++ }
++#if defined(CONFIG_ARCH_HI3531A)
++ priv->ctrl_base = of_iomap(np, CTRL_REGBASE_NODE_IDX);
++ if (IS_ERR(priv->ctrl_base)) {
++ iounmap(priv->peri_ctrl);
++ iounmap(priv->misc_ctrl);
++ return PTR_ERR(priv->ctrl_base);
++ }
++#endif
++ return 0;
++}
++
+static int hisi_usb3_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
-+ struct phy *phy;
-+ struct hisi_priv *priv;
++ struct phy *phy = NULL;
++ struct hisi_priv *priv = NULL;
+ struct device_node *np = pdev->dev.of_node;
++ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
++ if (priv == NULL)
+ return -ENOMEM;
+
-+ priv->peri_ctrl = of_iomap(np, 0);
-+ if (IS_ERR(priv->peri_ctrl))
-+ priv->peri_ctrl = NULL;
-+
-+ priv->misc_ctrl = of_iomap(np, 1);
-+ if (IS_ERR(priv->misc_ctrl))
-+ priv->misc_ctrl = NULL;
-+#if defined(CONFIG_ARCH_HI3531A)
-+ priv->ctrl_base = of_iomap(np, 2);
-+ if (IS_ERR(priv->ctrl_base))
-+ priv->ctrl_base = NULL;
-+#endif
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
-+ if (!phy)
++ if (phy == NULL) {
++ devm_kfree(dev, priv);
++ priv = NULL;
+ return -ENOMEM;
++ }
++
++ ret = hisi_usb3_iomap(np, priv);
++ if (ret)
++ goto usb3_kfree;
+
+ platform_set_drvdata(pdev, phy);
+ phy_set_drvdata(phy, priv);
-+#if defined(CONFIG_ARCH_HI3559AV100)
-+ if (hisi_usb3_init_para(phy, np))
-+ return -EINVAL;
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
++ ret = hisi_usb3_init_para(phy, np);
++ if (ret)
++ goto usb3_unmap;
+#endif
+ hisi_usb3_phy_on(phy);
-+ return 0;
++
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
++usb3_unmap:
++ iounmap(priv->combphy_base);
++ iounmap(priv->ctrl_base);
++#endif
++#if defined(CONFIG_ARCH_HI3531A)
++ iounmap(priv->ctrl_base);
++#endif
++ iounmap(priv->misc_ctrl);
++ iounmap(priv->peri_ctrl);
++usb3_kfree:
++ if (ret) {
++ devm_kfree(dev, priv);
++ priv = NULL;
++
++ devm_kfree(dev, phy);
++ phy = NULL;
++ }
++
++ return ret;
+}
+
+static int hisi_usb3_phy_remove(struct platform_device *pdev)
+{
++ struct device *dev = &pdev->dev;
+ struct phy *phy = dev_get_drvdata(&pdev->dev);
++ struct hisi_priv *priv = phy_get_drvdata(phy);
+
+ hisi_usb3_phy_off(phy);
++
++ devm_kfree(dev, priv);
++ priv = NULL;
++
++ devm_kfree(dev, phy);
++ phy = NULL;
+ return 0;
+}
+
@@ -329912,7 +398439,7 @@ index 0000000..dc874c7
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(hisi_usb3_pm_ops, hisi_usb3_phy_suspend,
-+ hisi_usb3_phy_resume);
++ hisi_usb3_phy_resume);
+
+static struct platform_driver hisi_usb3_phy_driver = {
+ .probe = hisi_usb3_phy_probe,
@@ -329927,12 +398454,16 @@ index 0000000..dc874c7
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/hibvt/phy-hixvp-hisi-usb.c b/drivers/phy/hibvt/phy-hixvp-hisi-usb.c
new file mode 100644
-index 0000000..b7f11bd
+index 0000000..ff007ef
--- /dev/null
+++ b/drivers/phy/hibvt/phy-hixvp-hisi-usb.c
-@@ -0,0 +1,716 @@
+@@ -0,0 +1,781 @@
+/*
-+ * Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
++ * phy-hixvp-hisi-usb.c
++ *
++ * USB phy driver.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -329958,6 +398489,8 @@ index 0000000..b7f11bd
+#include <linux/reset.h>
+#include <linux/usb/ch9.h>
+
++#include "phy-hisi-usb.h"
++
+#define HIXVP_PHY_TRIM_OFFSET 0x0008
+#define HIXVP_PHY_TRIM_MASK 0x1f00
+#define HIXVP_PHY_TRIM_VAL(a) (((a) << 8) & HIXVP_PHY_TRIM_MASK)
@@ -330025,6 +398558,9 @@ index 0000000..b7f11bd
+
+void hisi_usb_hixvp_def_all_exist(struct hisi_hixvp_priv *priv)
+{
++ if (priv == NULL)
++ return;
++
+ /* All parameters exist by default */
+ priv->vbus_flag = 1;
+
@@ -330050,46 +398586,53 @@ index 0000000..b7f11bd
+}
+
+void hisi_usb_hixvp_get_eye_para(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+
-+ /* Get phy eye parameters,if you want to change them,please open
++ if ((dev == NULL) || (priv == NULL))
++ return;
++
++ /*
++ * Get phy eye parameters,if you want to change them,please open
+ * dtsi file and modify parameters at phy node.
+ */
+ ret = of_property_read_u32(dev->of_node, "ana_cfg_0_eye_val",
-+ &(priv->ana_cfg_0_eye_val));
++ &(priv->ana_cfg_0_eye_val));
+ if (ret)
+ priv->ana_cfg_0_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "ana_cfg_0_offset",
-+ &(priv->ana_cfg_0_offset));
++ &(priv->ana_cfg_0_offset));
+ if (ret)
+ priv->ana_cfg_0_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "ana_cfg_2_eye_val",
-+ &(priv->ana_cfg_2_eye_val));
++ &(priv->ana_cfg_2_eye_val));
+ if (ret)
+ priv->ana_cfg_2_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "ana_cfg_2_offset",
-+ &(priv->ana_cfg_2_offset));
++ &(priv->ana_cfg_2_offset));
+ if (ret)
+ priv->ana_cfg_2_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "ana_cfg_4_eye_val",
-+ &(priv->ana_cfg_4_eye_val));
++ &(priv->ana_cfg_4_eye_val));
+ if (ret)
+ priv->ana_cfg_4_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "ana_cfg_4_offset",
-+ &(priv->ana_cfg_4_offset));
++ &(priv->ana_cfg_4_offset));
+ if (ret)
+ priv->ana_cfg_4_flag = 0;
+}
+
+void hisi_usb_hixvp_phy_eye_config(struct hisi_hixvp_priv *priv)
+{
++ if (priv == NULL)
++ return;
++
+ if (priv->ana_cfg_0_flag)
+ writel(priv->ana_cfg_0_eye_val, priv->phy_base + priv->ana_cfg_0_offset);
+
@@ -330101,23 +398644,26 @@ index 0000000..b7f11bd
+}
+
+void hisi_usb_hixvp_get_trim_para(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+
++ if ((dev == NULL) || (priv == NULL))
++ return;
++
+ /* get phy trim parameters */
+ ret = of_property_read_u32(dev->of_node, "trim_otp_addr",
-+ &(priv->trim_otp_addr));
++ &(priv->trim_otp_addr));
+ if (ret)
+ priv->trim_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "trim_otp_mask",
-+ &(priv->trim_otp_mask));
++ &(priv->trim_otp_mask));
+ if (ret)
+ priv->trim_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "trim_otp_bit_offset",
-+ &(priv->trim_otp_bit_offset));
++ &(priv->trim_otp_bit_offset));
+ if (ret)
+ priv->trim_flag = 0;
+
@@ -330134,9 +398680,16 @@ index 0000000..b7f11bd
+{
+ unsigned int trim_otp_val;
+ unsigned int reg;
-+ void __iomem *phy_trim;
++ void __iomem *phy_trim = NULL;
++
++ if (priv == NULL)
++ return;
++
+ if (priv->trim_flag) {
-+ phy_trim = ioremap_nocache(priv->trim_otp_addr, 0x100);
++ phy_trim = ioremap_nocache(priv->trim_otp_addr, __1K__);
++ if (phy_trim == NULL)
++ return;
++
+ reg = readl(phy_trim);
+ trim_otp_val = (reg & priv->trim_otp_mask);
+ if ((trim_otp_val >= priv->trim_otp_min) &&
@@ -330152,78 +398705,84 @@ index 0000000..b7f11bd
+}
+
+void hisi_usb_hixvp_get_svb_para_1(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+
++ if ((dev == NULL) || (priv == NULL))
++ return;
++
+ /* get phy svb parmteters */
+ ret = of_property_read_u32(dev->of_node, "svb_otp_addr", &(priv->svb_otp_addr));
+ if (ret)
+ priv->svb_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev5_min",
-+ &(priv->svb_otp_predev5_min));
++ &(priv->svb_otp_predev5_min));
+ if (ret)
+ priv->svb_predev5_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev5_max",
-+ &(priv->svb_otp_predev5_max));
++ &(priv->svb_otp_predev5_max));
+ if (ret)
+ priv->svb_predev5_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_phy_predev5_val",
-+ &(priv->svb_phy_predev5_val));
++ &(priv->svb_phy_predev5_val));
+ if (ret)
+ priv->svb_predev5_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev4_min",
-+ &(priv->svb_otp_predev4_min));
++ &(priv->svb_otp_predev4_min));
+ if (ret)
+ priv->svb_predev4_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev4_max",
-+ &(priv->svb_otp_predev4_max));
++ &(priv->svb_otp_predev4_max));
+ if (ret)
+ priv->svb_predev4_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_phy_predev4_val",
-+ &(priv->svb_phy_predev4_val));
++ &(priv->svb_phy_predev4_val));
+ if (ret)
+ priv->svb_predev4_flag = 0;
+}
+
+void hisi_usb_hixvp_get_svb_para_2(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+
++ if ((dev == NULL) || (priv == NULL))
++ return;
++
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev3_min",
-+ &(priv->svb_otp_predev3_min));
++ &(priv->svb_otp_predev3_min));
+ if (ret)
+ priv->svb_predev3_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev3_max",
-+ &(priv->svb_otp_predev3_max));
++ &(priv->svb_otp_predev3_max));
+ if (ret)
+ priv->svb_predev3_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_phy_predev3_val",
-+ &(priv->svb_phy_predev3_val));
++ &(priv->svb_phy_predev3_val));
+ if (ret)
+ priv->svb_predev3_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev2_min",
-+ &(priv->svb_otp_predev2_min));
++ &(priv->svb_otp_predev2_min));
+ if (ret)
+ priv->svb_predev2_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_otp_predev2_max",
-+ &(priv->svb_otp_predev2_max));
++ &(priv->svb_otp_predev2_max));
+ if (ret)
+ priv->svb_predev2_flag = 0;
+
+ ret = of_property_read_u32(dev->of_node, "svb_phy_predev2_val",
-+ &(priv->svb_phy_predev2_val));
++ &(priv->svb_phy_predev2_val));
+ if (ret)
+ priv->svb_predev2_flag = 0;
+}
@@ -330232,9 +398791,16 @@ index 0000000..b7f11bd
+{
+ unsigned int reg;
+ unsigned int ret;
-+ void __iomem *phy_svb;
++ void __iomem *phy_svb = NULL;
++
++ if (priv == NULL)
++ return;
++
+ if (priv->svb_flag) {
-+ phy_svb = ioremap_nocache(priv->svb_otp_addr, 0x100);
++ phy_svb = ioremap_nocache(priv->svb_otp_addr, __1K__);
++ if (phy_svb == NULL)
++ return;
++
+ ret = readl(phy_svb);
+ reg = readl(priv->phy_base + HIXVP_PHY_SVB_OFFSET);
+ reg &= ~HIXVP_PHY_SVB_MASK;
@@ -330242,13 +398808,13 @@ index 0000000..b7f11bd
+ (ret < priv->svb_otp_predev5_max) && (priv->svb_predev5_flag))
+ reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev5_val);
+ else if ((ret >= priv->svb_otp_predev4_min) &&
-+ (ret < priv->svb_otp_predev4_max) && (priv->svb_predev4_flag))
++ (ret < priv->svb_otp_predev4_max) && (priv->svb_predev4_flag))
+ reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev4_val);
+ else if ((ret >= priv->svb_otp_predev3_min) &&
-+ (ret <= priv->svb_otp_predev3_max) && (priv->svb_predev3_flag))
++ (ret <= priv->svb_otp_predev3_max) && (priv->svb_predev3_flag))
+ reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev3_val);
+ else if ((ret > priv->svb_otp_predev2_min) &&
-+ (ret <= priv->svb_otp_predev2_max) && (priv->svb_predev2_flag))
++ (ret <= priv->svb_otp_predev2_max) && (priv->svb_predev2_flag))
+ reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev2_val);
+ else
+ reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev4_val);
@@ -330259,10 +398825,13 @@ index 0000000..b7f11bd
+}
+
+static void hisi_usb_vbus_and_pwren_config(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+
++ if ((dev == NULL) || (priv == NULL))
++ return;
++
+ /* Some chips do not have VBUS encapsulation and need to be configured */
+ ret = of_property_read_u32(dev->of_node, "vbus_offset", &(priv->vbus_offset));
+ if (ret)
@@ -330284,22 +398853,25 @@ index 0000000..b7f11bd
+ if (priv->vbus_flag)
+ writel(priv->vbus_val, priv->pin_base + priv->vbus_offset);
+
-+ udelay(20);
++ udelay(U_LEVEL2);
+
+ if (priv->pwren_flag)
+ writel(priv->pwren_val, priv->pin_base + priv->pwren_offset);
+
-+ udelay(20);
++ udelay(U_LEVEL2);
+}
+
+static int hisi_usb_hixvp_get_pll_clk(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+
++ if ((dev == NULL) || (priv == NULL))
++ return -EINVAL;
++
+ /* Get phy pll clk config parameters from the phy node of the dtsi file */
+ ret = of_property_read_u32(dev->of_node, "phy_pll_offset",
-+ &(priv->phy_pll_offset));
++ &(priv->phy_pll_offset));
+ if (ret) {
+ dev_err(dev, "get phy_pll_offset failed: %d\n", ret);
+ return ret;
@@ -330321,11 +398893,14 @@ index 0000000..b7f11bd
+}
+
+static int hisi_usb_hixvp_set_crg_val(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+ unsigned int reg;
+
++ if ((dev == NULL) || (priv == NULL))
++ return -EINVAL;
++
+ /* Get CRG default value from the phy node of the dtsi file */
+ ret = of_property_read_u32(dev->of_node, "crg_offset", &(priv->crg_offset));
+ if (ret) {
@@ -330334,14 +398909,14 @@ index 0000000..b7f11bd
+ }
+
+ ret = of_property_read_u32(dev->of_node, "crg_defal_mask",
-+ &(priv->crg_defal_mask));
++ &(priv->crg_defal_mask));
+ if (ret) {
+ dev_err(dev, "get crg_defal_mask failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "crg_defal_val",
-+ &(priv->crg_defal_val));
++ &(priv->crg_defal_val));
+ if (ret) {
+ dev_err(dev, "get crg_defal_val failed: %d\n", ret);
+ return ret;
@@ -330357,10 +398932,13 @@ index 0000000..b7f11bd
+}
+
+static int hisi_usb_hixvp_phy_get_para(struct device *dev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ unsigned int ret;
+
++ if ((dev == NULL) || (priv == NULL))
++ return -EINVAL;
++
+ hisi_usb_hixvp_def_all_exist(priv);
+
+ ret = hisi_usb_hixvp_get_pll_clk(dev, priv);
@@ -330370,18 +398948,14 @@ index 0000000..b7f11bd
+ }
+
+ hisi_usb_hixvp_get_trim_para(dev, priv);
-+
+ hisi_usb_hixvp_get_eye_para(dev, priv);
-+
+ hisi_usb_hixvp_get_svb_para_1(dev, priv);
-+
+ hisi_usb_hixvp_get_svb_para_2(dev, priv);
+
+ return 0;
+}
+
-+static int hisi_usb_hixvp_phy_get_clks(struct hisi_hixvp_priv *priv,
-+ int count)
++static int hisi_usb_hixvp_phy_get_clks(struct hisi_hixvp_priv *priv, int count)
+{
+ struct device *dev = priv->dev;
+ struct device_node *np = dev->of_node;
@@ -330393,8 +398967,8 @@ index 0000000..b7f11bd
+ return 0;
+
+ priv->clks =
-+ devm_kcalloc(dev, priv->num_clocks, sizeof(struct clk *), GFP_KERNEL);
-+ if (!priv->clks)
++ devm_kcalloc(dev, priv->num_clocks, sizeof(struct clk *), GFP_KERNEL);
++ if (priv->clks == NULL)
+ return -ENOMEM;
+
+ for (i = 0; i < priv->num_clocks; i++) {
@@ -330405,6 +398979,8 @@ index 0000000..b7f11bd
+ while (--i >= 0)
+ clk_put(priv->clks[i]);
+
++ devm_kfree(dev, priv->clks);
++ priv->clks = NULL;
+ return PTR_ERR(clk);
+ }
+
@@ -330414,7 +398990,7 @@ index 0000000..b7f11bd
+}
+
+static int hisi_usb_hixvp_clk_rst_config(struct platform_device *pdev,
-+ struct hisi_hixvp_priv *priv)
++ struct hisi_hixvp_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
@@ -330428,16 +399004,40 @@ index 0000000..b7f11bd
+
+ priv->usb_phy_tpor_rst = devm_reset_control_get(dev, "phy_tpor_reset");
+ if (IS_ERR_OR_NULL(priv->usb_phy_tpor_rst)) {
-+ ret = PTR_ERR(priv->usb_phy_tpor_rst);
+ dev_err(dev, "get phy_tpor_reset failed: %d\n", ret);
-+ return ret;
++ return PTR_ERR(priv->usb_phy_tpor_rst);
+ }
+
+ priv->usb_phy_por_rst = devm_reset_control_get(dev, "phy_por_reset");
+ if (IS_ERR_OR_NULL(priv->usb_phy_por_rst)) {
-+ ret = PTR_ERR(priv->usb_phy_por_rst);
+ dev_err(dev, "get phy_por_reset failed: %d\n", ret);
-+ return ret;
++ return PTR_ERR(priv->usb_phy_por_rst);;
++ }
++
++ return 0;
++}
++
++static int hisi_usb_hixvp_iomap(struct device_node *np,
++ struct hisi_hixvp_priv *priv)
++{
++ if ((np == NULL) || (priv == NULL))
++ return -EINVAL;
++
++ priv->phy_base = of_iomap(np, 0);
++ if (IS_ERR(priv->phy_base))
++ return -ENOMEM;
++
++ priv->crg_base = of_iomap(np, 1);
++ if (IS_ERR(priv->crg_base)) {
++ iounmap(priv->phy_base);
++ return -ENOMEM;
++ }
++
++ priv->pin_base = of_iomap(np, 2);
++ if (IS_ERR(priv->pin_base)) {
++ iounmap(priv->phy_base);
++ iounmap(priv->crg_base);
++ return -ENOMEM;
+ }
+
+ return 0;
@@ -330446,8 +399046,7 @@ index 0000000..b7f11bd
+static int hisi_usb_hixvp_phy_init(struct phy *phy)
+{
+ struct hisi_hixvp_priv *priv = phy_get_drvdata(phy);
-+ int i;
-+ int ret;
++ int i, ret;
+ unsigned int reg;
+
+ for (i = 0; i < priv->num_clocks; i++) {
@@ -330460,7 +399059,7 @@ index 0000000..b7f11bd
+ }
+ }
+
-+ udelay(100);
++ udelay(U_LEVEL5);
+
+ /* undo por reset */
+ ret = reset_control_deassert(priv->usb_phy_por_rst);
@@ -330473,14 +399072,14 @@ index 0000000..b7f11bd
+ reg |= priv->phy_pll_val;
+ writel(reg, priv->phy_base + priv->phy_pll_offset);
+
-+ udelay(2000);
++ mdelay(M_LEVEL1);
+
+ /* undo tpor reset */
+ ret = reset_control_deassert(priv->usb_phy_tpor_rst);
+ if (ret)
+ return ret;
+
-+ udelay(200);
++ udelay(U_LEVEL6);
+
+ hisi_usb_hixvp_phy_eye_config(priv);
+
@@ -330493,8 +399092,7 @@ index 0000000..b7f11bd
+static int hisi_usb_hixvp_phy_exit(struct phy *phy)
+{
+ struct hisi_hixvp_priv *priv = phy_get_drvdata(phy);
-+ int i;
-+ int ret;
++ int i, ret;
+
+ for (i = 0; i < priv->num_clocks; i++)
+ clk_disable_unprepare(priv->clks[i]);
@@ -330519,82 +399117,69 @@ index 0000000..b7f11bd
+static int hisi_usb_hixvp_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
-+ struct phy *phy;
-+ struct hisi_hixvp_priv *priv;
++ struct phy *phy = NULL;
++ struct hisi_hixvp_priv *priv = NULL;
+ struct device_node *np = pdev->dev.of_node;
-+ struct phy_provider *phy_provider;
++ struct phy_provider *phy_provider = NULL;
+ unsigned int ret;
+
+ phy = devm_phy_create(dev, dev->of_node, &hisi_usb_hixvp_phy_ops);
-+ if (IS_ERR(phy)) {
-+ dev_err(dev, "Failed to create usb_phy\n");
++ if (IS_ERR(phy))
+ return PTR_ERR(phy);
-+ }
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
++ if (priv == NULL)
+ return -ENOMEM;
+
++ ret = hisi_usb_hixvp_iomap(np, priv);
++ if (ret) {
++ devm_kfree(dev, priv);
++ priv = NULL;
++
++ return -ENOMEM;
++ }
++
+ platform_set_drvdata(pdev, priv);
+ priv->dev = dev;
+
-+ priv->phy_base = of_iomap(np, 0);
-+ if (!priv->phy_base)
-+ return -ENOMEM;
-+
-+ priv->crg_base = of_iomap(np, 1);
-+ if (!priv->crg_base) {
-+ iounmap(priv->phy_base);
-+ return -ENOMEM;
-+ }
-+
-+ priv->pin_base = of_iomap(np, 2);
-+ if (!priv->pin_base) {
-+ iounmap(priv->phy_base);
-+ iounmap(priv->crg_base);
-+ return -ENOMEM;
-+ }
-+
+ ret = hisi_usb_hixvp_clk_rst_config(pdev, priv);
-+ if (ret) {
-+ dev_err(dev, "get clk or set reset failed: %d\n", ret);
-+ goto err_0;
-+ }
++ if (ret)
++ goto xvp_unmap;
+
+ ret = hisi_usb_hixvp_phy_get_para(dev, priv);
+ if (ret)
-+ goto err_0;
++ goto xvp_unmap;
+
+ hisi_usb_vbus_and_pwren_config(dev, priv);
+
-+ hisi_usb_hixvp_set_crg_val(dev, priv);
++ ret = hisi_usb_hixvp_set_crg_val(dev, priv);
++ if (ret)
++ goto xvp_unmap;
+
+ platform_set_drvdata(pdev, priv);
-+
+ phy_set_drvdata(phy, priv);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
-+ dev_err(dev, "Failed to register phy provider\n");
-+ goto err_1;
++ ret = PTR_ERR(phy_provider);
++ goto xvp_unmap;
+ }
+
+ return 0;
++xvp_unmap:
++ iounmap(priv->phy_base);
++ iounmap(priv->crg_base);
++ iounmap(priv->pin_base);
++
++ devm_kfree(dev, priv);
++ priv = NULL;
+
-+err_0:
-+ iounmap(priv->phy_base);
-+ iounmap(priv->crg_base);
-+ iounmap(priv->pin_base);
+ return ret;
-+err_1:
-+ iounmap(priv->phy_base);
-+ iounmap(priv->crg_base);
-+ iounmap(priv->pin_base);
-+ return PTR_ERR(phy_provider);
+}
+
+static int hisi_usb_hixvp_phy_remove(struct platform_device *pdev)
+{
++ struct device *dev = &pdev->dev;
+ struct hisi_hixvp_priv *priv = platform_get_drvdata(pdev);
+ int i;
+
@@ -330605,6 +399190,9 @@ index 0000000..b7f11bd
+ iounmap(priv->crg_base);
+ iounmap(priv->pin_base);
+
++ devm_kfree(dev, priv);
++ priv = NULL;
++
+ return 0;
+}
+
@@ -330613,7 +399201,9 @@ index 0000000..b7f11bd
+{
+ struct phy *phy = dev_get_drvdata(dev);
+
-+ hisi_usb_hixvp_phy_exit(phy);
++ if (hisi_usb_hixvp_phy_exit(phy))
++ return -1;
++
+ return 0;
+}
+
@@ -330621,13 +399211,15 @@ index 0000000..b7f11bd
+{
+ struct phy *phy = dev_get_drvdata(dev);
+
-+ hisi_usb_hixvp_phy_init(phy);
++ if (hisi_usb_hixvp_phy_init(phy))
++ return -1;
++
+ return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(hisi_usb_pm_ops, hisi_usb_hixvp_phy_suspend,
-+ hisi_usb_hixvp_phy_resume);
++ hisi_usb_hixvp_phy_resume);
+
+static const struct of_device_id hisi_usb_hixvp_phy_of_match[] = {
+ { .compatible = "hisilicon,hixvp-usb2-phy" },
@@ -330660,21 +399252,334 @@ index 02e46bb..cf3e643 100644
help
Reboot support for Hisilicon boards.
+diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
+index bf01288..a5b17b6 100644
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -175,6 +175,14 @@ config PWM_FSL_FTM
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-fsl-ftm.
+
++config PWM_HIBVT
++ tristate "HiSilicon BVT PWM support"
++ help
++ Generic PWM framework driver for HiSilicon BVT SoCs.
++
++ To compile this driver as a module, choose M here: the module
++ will be called pwm-hibvt.
++
+ config PWM_IMG
+ tristate "Imagination Technologies PWM driver"
+ depends on HAS_IOMEM
+diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
+index 1194c54..a48bdb5 100644
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CRC) += pwm-crc.o
+ obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o
+ obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
+ obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o
++obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o
+ obj-$(CONFIG_PWM_IMG) += pwm-img.o
+ obj-$(CONFIG_PWM_IMX) += pwm-imx.o
+ obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
+diff --git a/drivers/pwm/pwm-hibvt.c b/drivers/pwm/pwm-hibvt.c
+new file mode 100644
+index 0000000..30023a0
+--- /dev/null
++++ b/drivers/pwm/pwm-hibvt.c
+@@ -0,0 +1,275 @@
++/*
++ * PWM Controller Driver for HiSilicon BVT SoCs
++ *
++ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http:// www.gnu.org/licenses/>.
++ */
++
++#include <linux/bitops.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/pwm.h>
++#include <linux/reset.h>
++
++#define PWM_CFG0_ADDR(x) (((x)*0x20) + 0x0)
++#define PWM_CFG1_ADDR(x) (((x)*0x20) + 0x4)
++#define PWM_CFG2_ADDR(x) (((x)*0x20) + 0x8)
++#define PWM_CTRL_ADDR(x) (((x)*0x20) + 0xC)
++
++#define PWM_ENABLE_SHIFT 0
++#define PWM_ENABLE_MASK BIT(0)
++
++#define PWM_POLARITY_SHIFT 1
++#define PWM_POLARITY_MASK BIT(1)
++
++#define PWM_KEEP_SHIFT 2
++#define PWM_KEEP_MASK BIT(2)
++
++#define PWM_PERIOD_MASK GENMASK(31, 0)
++#define PWM_DUTY_MASK GENMASK(31, 0)
++
++struct hibvt_pwm_chip {
++ struct pwm_chip chip;
++ struct clk *clk;
++ void __iomem *base;
++ struct reset_control *rstc;
++};
++
++struct hibvt_pwm_soc {
++ u32 num_pwms;
++};
++
++static const struct hibvt_pwm_soc pwm_soc[1] = {
++ { .num_pwms = 2 },
++};
++
++static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip)
++{
++ return container_of(chip, struct hibvt_pwm_chip, chip);
++}
++
++static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
++ u32 mask, u32 data)
++{
++ void __iomem *address = base + offset;
++ u32 value;
++
++ value = readl(address);
++ value &= ~mask;
++ value |= (data & mask);
++ writel(value, address);
++}
++
++static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++ struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
++
++ hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
++ PWM_ENABLE_MASK, 0x1);
++}
++
++static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++ struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
++
++ hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
++ PWM_ENABLE_MASK, 0x0);
++}
++
++static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++ int duty_cycle_ns, int period_ns)
++{
++ struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
++ u32 duty;
++ u64 period, freq;
++
++ freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
++
++ period = div_u64(freq * period_ns, 1000);
++ duty = div_u64(period * duty_cycle_ns, period_ns);
++
++ hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
++ PWM_PERIOD_MASK, period);
++
++ hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
++ PWM_DUTY_MASK, duty);
++}
++
++static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
++ struct pwm_device *pwm,
++ enum pwm_polarity polarity)
++{
++ struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
++
++ if (polarity == PWM_POLARITY_INVERSED)
++ hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
++ PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
++ else
++ hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
++ PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
++}
++
++static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
++ struct pwm_state *state) {
++ struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
++ void __iomem *base;
++ u32 freq;
++ u64 value;
++
++ freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
++ base = hi_pwm_chip->base;
++
++ value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
++ state->period = div_u64(value * 1000, freq);
++
++ value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
++ state->duty_cycle = div_u64(value * 1000, freq);
++
++ value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
++ state->enabled = (PWM_ENABLE_MASK & value);
++}
++
++static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
++ struct pwm_state *state)
++{
++ if (state->polarity != pwm->state.polarity) {
++ hibvt_pwm_set_polarity(chip, pwm, state->polarity);
++ }
++
++ if (state->period != pwm->state.period ||
++ state->duty_cycle != pwm->state.duty_cycle) {
++ hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
++ }
++
++ if (state->enabled != pwm->state.enabled) {
++ if (state->enabled) {
++ hibvt_pwm_enable(chip, pwm);
++ }
++ else {
++ hibvt_pwm_disable(chip, pwm);
++ }
++ }
++
++ return 0;
++}
++
++static struct pwm_ops hibvt_pwm_ops = {
++ .get_state = hibvt_pwm_get_state,
++ .apply = hibvt_pwm_apply,
++
++ .owner = THIS_MODULE,
++};
++
++static int hibvt_pwm_probe(struct platform_device *pdev)
++{
++ const struct hibvt_pwm_soc *soc =
++ of_device_get_match_data(&pdev->dev);
++ struct hibvt_pwm_chip *pwm_chip;
++ struct resource *res;
++ int ret;
++ int i;
++
++ pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
++ if (pwm_chip == NULL) {
++ return -ENOMEM;
++ }
++
++ pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(pwm_chip->clk)) {
++ dev_err(&pdev->dev, "getting clock failed with %ld\n",
++ PTR_ERR(pwm_chip->clk));
++ return PTR_ERR(pwm_chip->clk);
++ }
++
++ pwm_chip->chip.ops = &hibvt_pwm_ops;
++ pwm_chip->chip.dev = &pdev->dev;
++ pwm_chip->chip.base = -1;
++ pwm_chip->chip.npwm = soc->num_pwms;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ pwm_chip->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(pwm_chip->base)) {
++ return PTR_ERR(pwm_chip->base);
++ }
++
++ ret = clk_prepare_enable(pwm_chip->clk);
++ if (ret < 0) {
++ return ret;
++ }
++
++ pwm_chip->rstc = devm_reset_control_get(&pdev->dev, NULL);
++ if (IS_ERR(pwm_chip->rstc)) {
++ clk_disable_unprepare(pwm_chip->clk);
++ return PTR_ERR(pwm_chip->rstc);
++ }
++
++ reset_control_assert(pwm_chip->rstc);
++ msleep(30);
++ reset_control_deassert(pwm_chip->rstc);
++
++ ret = pwmchip_add(&pwm_chip->chip);
++ if (ret < 0) {
++ clk_disable_unprepare(pwm_chip->clk);
++ return ret;
++ }
++
++ for (i = 0; i < pwm_chip->chip.npwm; i++) {
++ hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
++ PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
++ }
++
++ platform_set_drvdata(pdev, pwm_chip);
++
++ return 0;
++}
++
++static int hibvt_pwm_remove(struct platform_device *pdev)
++{
++ struct hibvt_pwm_chip *pwm_chip;
++
++ pwm_chip = platform_get_drvdata(pdev);
++
++ reset_control_assert(pwm_chip->rstc);
++ msleep(30);
++ reset_control_deassert(pwm_chip->rstc);
++
++ clk_disable_unprepare(pwm_chip->clk);
++
++ return pwmchip_remove(&pwm_chip->chip);
++}
++
++static const struct of_device_id hibvt_pwm_of_match[] = {
++ { .compatible = "hisilicon,hibvt-pwm" },
++ { .compatible = "hisilicon,hi3516xx-pwm", .data = &pwm_soc[0] }, {}
++};
++MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);
++
++static struct platform_driver hibvt_pwm_driver = {
++ .driver = {
++ .name = "hibvt-pwm",
++ .of_match_table = hibvt_pwm_of_match,
++ },
++ .probe = hibvt_pwm_probe,
++ .remove = hibvt_pwm_remove,
++};
++module_platform_driver(hibvt_pwm_driver);
++
++MODULE_AUTHOR("Jian Yuan");
++MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
++MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
-index 2142a5d..4001811 100644
+index 2142a5d..d406e98 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
-@@ -5,6 +5,7 @@
+@@ -5,6 +5,8 @@
obj-$(CONFIG_REGULATOR) += core.o dummy.o fixed-helper.o helpers.o devres.o
obj-$(CONFIG_OF) += of_regulator.o
+obj-$(CONFIG_ARCH_HI3559AV100) += hi3559av100-regulator.o
++obj-$(CONFIG_ARCH_HI3569V100) += hi3559av100-regulator.o
obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o
obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o
obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o
diff --git a/drivers/regulator/hi3559av100-regulator.c b/drivers/regulator/hi3559av100-regulator.c
new file mode 100644
-index 0000000..0154127
+index 0000000..f01f0ed
--- /dev/null
+++ b/drivers/regulator/hi3559av100-regulator.c
@@ -0,0 +1,180 @@
@@ -330738,8 +399643,8 @@ index 0000000..0154127
+}
+
+static int hi3559a_gpu_regulator_set_voltage(struct regulator_dev *regdev,
-+ int min_uV, int max_uV,
-+ unsigned *selector)
++ int min_uV, int max_uV,
++ unsigned *selector)
+{
+ struct hi3559a_gpu_regulator *reg = rdev_get_drvdata(regdev);
+ u32 duty, value, mask;
@@ -330768,11 +399673,11 @@ index 0000000..0154127
+
+static int hi3559a_regulator_probe(struct platform_device *pdev)
+{
-+ struct hi3559a_gpu_regulator *reg;
-+ struct regulator_init_data *init_data;
++ struct hi3559a_gpu_regulator *reg = NULL;
++ struct regulator_init_data *init_data = NULL;
+ struct regulator_config config = {0};
-+ struct resource *res;
-+ char *pname;
++ struct resource *res = NULL;
++ char *pname = NULL;
+
+ reg = devm_kzalloc(&pdev->dev, sizeof(*reg), GFP_KERNEL);
+ if (!reg) {
@@ -330900,10 +399805,10 @@ index 1ac694a..c308468 100644
obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
diff --git a/drivers/rtc/rtc-hibvt.c b/drivers/rtc/rtc-hibvt.c
new file mode 100644
-index 0000000..e2623cb
+index 0000000..4f4a095
--- /dev/null
+++ b/drivers/rtc/rtc-hibvt.c
-@@ -0,0 +1,631 @@
+@@ -0,0 +1,636 @@
+/*
+ * RTC driver for Hisilicon BVT
+ * Copyright (C) 2016 HiSilicon Technologies Co., Ltd.
@@ -330990,18 +399895,21 @@ index 0000000..e2623cb
+#define RTC_FREQ_H 0x51
+#define RTC_FREQ_L 0x52
+
-+#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100)\
-+ || defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)\
-+ || defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300)\
-+ || defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300)\
-+ || defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
++#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100) || \
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) || \
++ defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) || \
++ defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || \
++ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200) || \
++ defined(CONFIG_ARCH_HI3562V100) || defined(CONFIG_ARCH_HI3566V100)
++
+#define RTC_REG_LOCK1 0x64
+#define RTC_REG_LOCK2 0x65
+#define RTC_REG_LOCK3 0x66
+#define RTC_REG_LOCK4 0x67
+#endif
+
-+#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100)
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100) || \
++ defined(CONFIG_ARCH_HI3569V100)
+#define PWR_REG_ADDR 0x180C0000
+#define PWR_REG_LENGTH 0x100
+#endif
@@ -331034,7 +399942,7 @@ index 0000000..e2623cb
+};
+
+static int hibvt_spi_write(void *spi_reg, unsigned char reg,
-+ unsigned char val)
++ unsigned char val)
+{
+ union u_spi_rw w_data, r_data;
+ int cnt = SPI_RW_RETRY_CNT;
@@ -331061,13 +399969,13 @@ index 0000000..e2623cb
+
+
+static int hibvt_spi_rtc_write(void *spi_reg, unsigned char reg,
-+ unsigned char val)
++ unsigned char val)
+{
+ return hibvt_spi_write(spi_reg, reg, val);
+}
+
+static int hibvt_spi_read(void *spi_reg, unsigned char reg,
-+ unsigned char *val)
++ unsigned char *val)
+{
+ union u_spi_rw w_data, r_data;
+ int cnt = SPI_RW_RETRY_CNT;
@@ -331093,7 +400001,7 @@ index 0000000..e2623cb
+}
+
+static int hibvt_spi_rtc_read(void *spi_reg, unsigned char reg,
-+ unsigned char *val)
++ unsigned char *val)
+{
+ return hibvt_spi_read(spi_reg, reg, val);
+}
@@ -331101,15 +400009,15 @@ index 0000000..e2623cb
+static int hibvt_rtc_read_time(struct device *dev, struct rtc_time *time)
+{
+ struct hibvt_rtc *rtc = dev_get_drvdata(dev);
-+ unsigned char dayl, dayh;
-+ unsigned char second, minute, hour;
++ unsigned char dayl = 0, dayh = 0;
++ unsigned char second = 0, minute = 0, hour = 0;
+ unsigned long seconds = 0;
-+ unsigned int day;
-+ unsigned char raw_value;
++ unsigned int day = 0;
++ unsigned char raw_value = 0;
+ int cnt = RTC_RW_RETRY_CNT;
-+ int ret = 0;
++ unsigned int ret = 0;
+
-+ ret = hibvt_spi_rtc_read(rtc->regs, RTC_INT_RAW, &raw_value);
++ ret = (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_INT_RAW, &raw_value);
+ if (ret) {
+ dev_err(dev, "IO err.\n");
+ return ret;
@@ -331118,33 +400026,33 @@ index 0000000..e2623cb
+ if (raw_value & LV_INT_MASK) {
+ //dev_err(dev,
+ // "low voltage detected, date/time is not reliable.\n");
-+ hibvt_spi_write(rtc->regs, RTC_INT_CLR, 1);
++ (unsigned int)hibvt_spi_write(rtc->regs, RTC_INT_CLR, 1);
+ //return -EINVAL;
+ }
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
+ if (raw_value & REG_LOCK_BYPASS)
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LORD,
-+ (~(REG_LOCK_BYPASS)) & raw_value);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LORD,
++ (~(REG_LOCK_BYPASS)) & raw_value);
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
+ /* lock the time */
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LORD,
-+ (REG_LOCK_STAT) | raw_value);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LORD,
++ (REG_LOCK_STAT) | raw_value);
+ /* wait rtc load flag */
+ do {
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
+ msleep(RTC_SLEEP_TIME_MS);
+ } while ((ret || (raw_value & REG_LOCK_STAT)) && (--cnt));
+
+ if (!ret && (raw_value & REG_LOCK_STAT))
+ return -EBUSY;
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_S_COUNT, &second);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_M_COUNT, &minute);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_H_COUNT, &hour);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_D_COUNT_L, &dayl);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_D_COUNT_H, &dayh);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_S_COUNT, &second);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_M_COUNT, &minute);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_H_COUNT, &hour);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_D_COUNT_L, &dayl);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_D_COUNT_H, &dayh);
+
+ if (ret) {
+ dev_err(dev, "IO err.\n");
@@ -331162,7 +400070,7 @@ index 0000000..e2623cb
+static int hibvt_rtc_set_time(struct device *dev, struct rtc_time *time)
+{
+ struct hibvt_rtc *rtc = dev_get_drvdata(dev);
-+ int ret;
++ unsigned int ret = 0;
+ unsigned int days;
+ unsigned long seconds = 0;
+ unsigned int cnt = RTC_RW_RETRY_CNT;
@@ -331173,18 +400081,18 @@ index 0000000..e2623cb
+ return ret;
+ days = SEC_TO_DAY(seconds);
+
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LR_10MS, 0);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LR_S, time->tm_sec);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LR_M, time->tm_min);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LR_H, time->tm_hour);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LR_D_L, (days & 0xFF));
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LR_D_H, (days >> 8));
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LR_10MS, 0);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LR_S, time->tm_sec);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LR_M, time->tm_min);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LR_H, time->tm_hour);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LR_D_L, (days & 0xFF));
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LR_D_H, (days >> 8));
+
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_LORD,
-+ (raw_value | REG_LOAD_STAT));
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_LORD,
++ (raw_value | REG_LOAD_STAT));
+ /* wait rtc load flag */
+ do {
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_LORD, &raw_value);
+ msleep(RTC_SLEEP_TIME_MS);
+ } while ((ret || (raw_value & REG_LOAD_STAT)) && (--cnt));
+
@@ -331198,30 +400106,30 @@ index 0000000..e2623cb
+}
+
+static int hibvt_rtc_read_alarm(struct device *dev,
-+ struct rtc_wkalrm *alrm)
++ struct rtc_wkalrm *alrm)
+{
+ struct hibvt_rtc *rtc = dev_get_drvdata(dev);
+ unsigned char dayl = 0, dayh = 0;
-+ unsigned char second, minute, hour;
++ unsigned char second = 0, minute = 0, hour = 0;
+ unsigned long seconds = 0;
-+ unsigned int day;
++ unsigned int day = 0;
+ unsigned char int_state = 0;
-+ int ret = 0;
++ unsigned int ret = 0;
+
+ memset(alrm, 0, sizeof(struct rtc_wkalrm));
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_MR_S, &second);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_MR_M, &minute);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_MR_H, &hour);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_MR_D_L, &dayl);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_MR_D_H, &dayh);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_MR_S, &second);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_MR_M, &minute);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_MR_H, &hour);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_MR_D_L, &dayl);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_MR_D_H, &dayh);
+
+ day = (unsigned int)(dayl | (dayh << 8));
+ seconds = DATE_TO_SEC(day, hour, minute, second);
+
+ rtc_time_to_tm(seconds, &alrm->time);
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_IMSC, &int_state);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_IMSC, &int_state);
+ if (ret) {
+ dev_err(dev, "IO err.\n");
+ return ret;
@@ -331239,26 +400147,26 @@ index 0000000..e2623cb
+ unsigned int days;
+ unsigned long seconds = 0;
+ unsigned char val = 0;
-+ int ret = 0;
++ unsigned int ret = 0;
+
+ rtc_tm_to_time(&alrm->time, &seconds);
+
+ days = SEC_TO_DAY(seconds);
+
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_MR_10MS, 0);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_MR_S, alrm->time.tm_sec);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_MR_M, alrm->time.tm_min);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_MR_H, alrm->time.tm_hour);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_MR_D_L, (days & 0xFF));
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_MR_D_H, (days >> 8));
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_MR_10MS, 0);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_MR_S, alrm->time.tm_sec);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_MR_M, alrm->time.tm_min);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_MR_H, alrm->time.tm_hour);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_MR_D_L, (days & 0xFF));
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_MR_D_H, (days >> 8));
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_IMSC, &val);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_IMSC, &val);
+ if (alrm->enabled)
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
-+ val | AIE_INT_MASK);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
++ val | AIE_INT_MASK);
+ else
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
-+ val & ~AIE_INT_MASK);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
++ val & ~AIE_INT_MASK);
+
+ if (ret) {
+ dev_err(dev, "IO err.\n");
@@ -331269,19 +400177,19 @@ index 0000000..e2623cb
+}
+
+static int hibvt_rtc_alarm_irq_enable(struct device *dev,
-+ unsigned int enabled)
++ unsigned int enabled)
+{
+ struct hibvt_rtc *rtc = dev_get_drvdata(dev);
+ unsigned char val = 0;
-+ int ret = 0;
++ unsigned int ret = 0;
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_IMSC, &val);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_IMSC, &val);
+ if (enabled)
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
-+ val | AIE_INT_MASK);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
++ val | AIE_INT_MASK);
+ else
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
-+ val & ~AIE_INT_MASK);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_IMSC,
++ val & ~AIE_INT_MASK);
+
+ if (ret) {
+ dev_err(dev, "IO err.\n");
@@ -331300,10 +400208,10 @@ index 0000000..e2623cb
+{
+ struct hibvt_rtc *rtc = (struct hibvt_rtc *)data;
+ unsigned char val = 0;
-+ int ret = 0;
++ unsigned int ret = 0;
+
-+ ret |= hibvt_spi_read(rtc->regs, RTC_INT, &val);
-+ ret |= hibvt_spi_write(rtc->regs, RTC_INT_CLR, AIE_INT_MASK);
++ ret |= (unsigned int)hibvt_spi_read(rtc->regs, RTC_INT, &val);
++ ret |= (unsigned int)hibvt_spi_write(rtc->regs, RTC_INT_CLR, AIE_INT_MASK);
+
+ if (ret) {
+ dev_err(&rtc->rtc_dev->dev, "IO err.\n");
@@ -331320,34 +400228,33 @@ index 0000000..e2623cb
+#define FREQ_MIN_VAL 3276000
+
+static int hibvt_rtc_ioctl(struct device *dev,
-+ unsigned int cmd, unsigned long arg)
++ unsigned int cmd, unsigned long arg)
+{
+ struct hibvt_rtc *rtc = dev_get_drvdata(dev);
-+ int ret = 0;
++ unsigned int ret = 0;
+
+ switch (cmd) {
-+ case RTC_PLL_SET:
-+ {
++ case RTC_PLL_SET: {
+ char freq_l, freq_h;
+ struct rtc_pll_info pll_info;
+
-+ if (copy_from_user(&pll_info, (struct rtc_pll_info *)arg,
-+ sizeof(struct rtc_pll_info)))
++ if (copy_from_user(&pll_info, (struct rtc_pll_info *)(uintptr_t)arg,
++ sizeof(struct rtc_pll_info)))
+ return -EFAULT;
+
+ /* freq = 32700 + (freq /3052)*100 */
+ if (pll_info.pll_value > FREQ_MAX_VAL
-+ || pll_info.pll_value < FREQ_MIN_VAL)
++ || pll_info.pll_value < FREQ_MIN_VAL)
+ return -EINVAL;
+
+ pll_info.pll_value = (pll_info.pll_value - 3270000)
-+ * 3052 / 10000;
++ * 3052 / 10000;
+
-+ freq_l = (char)(pll_info.pll_value & 0xff);
-+ freq_h = (char)((pll_info.pll_value >> 8) & 0xf);
++ freq_l = (char)((unsigned int)pll_info.pll_value & 0xff);
++ freq_h = (char)(((unsigned int)pll_info.pll_value >> 8) & 0xf);
+
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_FREQ_H, freq_h);
-+ ret |= hibvt_spi_rtc_write(rtc->regs, RTC_FREQ_L, freq_l);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_FREQ_H, freq_h);
++ ret |= (unsigned int)hibvt_spi_rtc_write(rtc->regs, RTC_FREQ_L, freq_l);
+
+ if (ret) {
+ dev_err(dev, "IO err.\n");
@@ -331356,28 +400263,27 @@ index 0000000..e2623cb
+
+ return 0;
+ }
-+ case RTC_PLL_GET:
-+ {
++ case RTC_PLL_GET: {
+ char freq_l, freq_h;
+ struct rtc_pll_info pll_info;
+
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_FREQ_H, &freq_h);
-+ ret |= hibvt_spi_rtc_read(rtc->regs, RTC_FREQ_L, &freq_l);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_FREQ_H, &freq_h);
++ ret |= (unsigned int)hibvt_spi_rtc_read(rtc->regs, RTC_FREQ_L, &freq_l);
+
+ if (ret) {
+ dev_err(dev, "IO err.\n");
+ return ret;
+ }
+
-+ pll_info.pll_value = ((freq_h & 0xf) << 8) + freq_l;
++ pll_info.pll_value = (((unsigned char)freq_h & 0xf) << 8) + freq_l;
+ pll_info.pll_value = 3270000
-+ + (pll_info.pll_value * 10000) / 3052;
++ + (pll_info.pll_value * 10000) / 3052;
+
+ pll_info.pll_max = FREQ_MAX_VAL;
+ pll_info.pll_min = FREQ_MIN_VAL;
+
-+ if (copy_to_user((void __user *)arg,
-+ &pll_info, sizeof(struct rtc_pll_info)))
++ if (copy_to_user((void __user *)(uintptr_t)arg,
++ &pll_info, sizeof(struct rtc_pll_info)))
+ return -EFAULT;
+
+ return 0;
@@ -331399,66 +400305,69 @@ index 0000000..e2623cb
+static int hibvt_rtc_init(struct hibvt_rtc *rtc)
+{
+ void *spi_reg = rtc->regs;
-+ int ret = 0;
++ unsigned int ret = 0;
+ unsigned char val = 0;
-+ #if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100)
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100) || \
++ defined(CONFIG_ARCH_HI3569V100)
+ void *pwr_reg = NULL;
-+ #endif
++#endif
+ /*
+ * clk div value = (apb_clk/spi_clk)/2-1,
+ * apb clk = 100MHz, spi_clk = 10MHz,so value= 0x4
+ */
+ writel(CLK_DIV_DEFAULT, (spi_reg+SPI_CLK_DIV));
+
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_IMSC, INT_MSK_DEFAULT);
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_SAR_CTRL, LV_CTL_DEFAULT);
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_IMSC, INT_MSK_DEFAULT);
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_SAR_CTRL, LV_CTL_DEFAULT);
+
-+#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100)\
-+ || defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300)\
-+ || defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
-+ /* default driver capability */
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK4, 0x5A);
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK3, 0x5A);
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK2, 0xAB);
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK1, 0xCD);
++#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100) || \
++ defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) || \
++ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
++ /* default driver capability */
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK4, 0x5A);
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK3, 0x5A);
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK2, 0xAB);
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_REG_LOCK1, 0xCD);
+#endif
+
-+#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100)
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100) || \
++ defined(CONFIG_ARCH_HI3569V100)
+ pwr_reg = ioremap(PWR_REG_ADDR, PWR_REG_LENGTH);
+ if(pwr_reg == NULL) {
-+ return -1;
++ return -1;
+ }
+ writel(0x5A5AABCD, pwr_reg+0x58);
+ iounmap(pwr_reg);
+#endif
-+ /*driver capability */
-+#if defined(CONFIG_ARCH_HI3516CV500)|| defined(CONFIG_ARCH_HI3516DV300)\
-+ || defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200)\
-+ || defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100)\
-+ || defined(CONFIG_ARCH_HI3519AV100) || defined(CONFIG_ARCH_HI3556AV100)\
-+ || defined(CONFIG_ARCH_HI3536DV100)
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_CLK_CFG, 0x02);
-+#elif defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300)\
-+ || defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_CLK_CFG, 0x03);
++ /*driver capability */
++#if defined(CONFIG_ARCH_HI3516CV500) || defined(CONFIG_ARCH_HI3516DV300) ||\
++ defined(CONFIG_ARCH_HI3556V200) || defined(CONFIG_ARCH_HI3559V200) ||\
++ defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3559CV100) ||\
++ defined(CONFIG_ARCH_HI3519AV100) || defined(CONFIG_ARCH_HI3556AV100) ||\
++ defined(CONFIG_ARCH_HI3536DV100) || defined(CONFIG_ARCH_HI3562V100) ||\
++ defined(CONFIG_ARCH_HI3566V100) || defined(CONFIG_ARCH_HI3569V100)
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_CLK_CFG, 0x02);
++#elif defined(CONFIG_ARCH_HI3516EV200) || defined(CONFIG_ARCH_HI3516EV300) ||\
++ defined(CONFIG_ARCH_HI3518EV300) || defined(CONFIG_ARCH_HI3516DV200)
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_CLK_CFG, 0x03);
+#else
-+ /* HI3536CV100 */
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_CLK_CFG, 0x01);
++ /* HI3536CV100 */
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_CLK_CFG, 0x01);
+#endif
+
-+ /* default FREQ COEF */
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_FREQ_H, FREQ_H_DEFAULT);
-+ ret |= hibvt_spi_rtc_write(spi_reg, RTC_FREQ_L, FREQ_L_DEFAULT);
++ /* default FREQ COEF */
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_FREQ_H, FREQ_H_DEFAULT);
++ ret |= (unsigned int)hibvt_spi_rtc_write(spi_reg, RTC_FREQ_L, FREQ_L_DEFAULT);
+
-+ ret |= hibvt_spi_rtc_read(spi_reg, RTC_INT_RAW, &val);
++ ret |= (unsigned int)hibvt_spi_rtc_read(spi_reg, RTC_INT_RAW, &val);
+ if (ret) {
+ dev_err(&rtc->rtc_dev->dev, "IO err.\n");
+ return ret;
+ }
-+
++
+ if (val & LV_INT_MASK) {
-+ //dev_err(&rtc->rtc_dev->dev,
-+ // "low voltage detected, date/time is not reliable.\n");
++ /* dev_err(&rtc->rtc_dev->dev,
++ "low voltage detected, date/time is not reliable.\n"); */
+ hibvt_spi_write(rtc->regs, RTC_INT_CLR, 1);
+ }
+
@@ -331467,9 +400376,9 @@ index 0000000..e2623cb
+
+static int hibvt_rtc_probe(struct platform_device *pdev)
+{
-+ struct resource *mem;
++ struct resource *mem = NULL;
+ struct hibvt_rtc *rtc;
-+ int ret;
++ int ret;
+
+ rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
+ if (!rtc)
@@ -331484,7 +400393,7 @@ index 0000000..e2623cb
+
+ rtc->rtc_irq = platform_get_irq(pdev, 0);
+ ret = devm_request_irq(&pdev->dev, rtc->rtc_irq,
-+ hibvt_rtc_alm_interrupt, 0, pdev->name, rtc);
++ hibvt_rtc_alm_interrupt, 0, pdev->name, rtc);
+ if (ret) {
+ dev_err(&pdev->dev, "could not request irq %d\n", rtc->rtc_irq);
+ return ret;
@@ -331521,9 +400430,10 @@ index 0000000..e2623cb
+static struct platform_driver hibvt_rtc_driver = {
+ .probe = hibvt_rtc_probe,
+ .remove = hibvt_rtc_remove,
-+ .driver = { .name = "hibvt_rtc",
-+ .of_match_table = hibvt_rtc_match,
-+ },
++ .driver = {
++ .name = "hibvt_rtc",
++ .of_match_table = hibvt_rtc_match,
++ },
+};
+
+module_platform_driver(hibvt_rtc_driver);
@@ -331614,10 +400524,10 @@ index 6e77cb0..6e4f0cd 100644
+obj-$(CONFIG_SCSI_UFS_CARD) += ufs_proc.o
diff --git a/drivers/scsi/ufs/hi3559av100_ufs.c b/drivers/scsi/ufs/hi3559av100_ufs.c
new file mode 100644
-index 0000000..4ea8f24
+index 0000000..7850ee5
--- /dev/null
+++ b/drivers/scsi/ufs/hi3559av100_ufs.c
-@@ -0,0 +1,1076 @@
+@@ -0,0 +1,1069 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
@@ -331669,8 +400579,7 @@ index 0000000..4ea8f24
+ uint8_t rxLanes;
+ uint8_t pwrMode;
+};
-+struct ufs_phy_remap_add
-+{
++struct ufs_phy_remap_add {
+ void __iomem *crg_base;
+ void __iomem *misc_base;
+};
@@ -331736,15 +400645,15 @@ index 0000000..4ea8f24
+ reg &= ~BIT_DA_UFS_REFCLK_OEN;
+ reg &= ~MASK_DA_UFS_REFCLK_DS;
+ reg |= (BIT_DA_UFS_REFCLK_DS0|
-+ BIT_DA_UFS_REFCLK_DS1|
-+ BIT_DA_UFS_REFCLK_SL);
++ BIT_DA_UFS_REFCLK_DS1|
++ BIT_DA_UFS_REFCLK_SL);
+ writel(reg, misc_base);
+ udelay(1);
+
+ reg = readl(misc_base);
+ reg &= ~(BIT_DA_UFS_RESET_OEN |
-+ MASK_DA_UFS_RESET_DS |
-+ BIT_UFS_PAD_RESET);
++ MASK_DA_UFS_RESET_DS |
++ BIT_UFS_PAD_RESET);
+ reg |= BIT_DA_UFS_RESET_SL;
+ writel(reg, misc_base);
+ udelay(10);
@@ -331766,21 +400675,21 @@ index 0000000..4ea8f24
+#ifdef COMBO_PHY_V120
+ /*Rx SKP_DET_SEL, lane0 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX0(SKP_DET_SEL), 0x00,
-+ SKP_DET_SEL_EN, DME_LOCAL);
++ SKP_DET_SEL_EN, DME_LOCAL);
+ /*Rx SKP_DET_SEL, lane1 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX1(SKP_DET_SEL), 0x00,
-+ SKP_DET_SEL_EN, DME_LOCAL);
++ SKP_DET_SEL_EN, DME_LOCAL);
+
+ /*VCO_AUTO_CHG */
+ ufshcd_dme_set_attr(hba, 0xdf0000, 0x00,
-+ (VCO_AUTO_CHG_EN | VCO_FORCE_ON_EN), DME_LOCAL);
++ (VCO_AUTO_CHG_EN | VCO_FORCE_ON_EN), DME_LOCAL);
+
+ /*RX_SQ_VREF, lane0 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX0(RX_SQ_VREF), 0x00,
-+ RX_SQ_VREF_175mv, DME_LOCAL);
++ RX_SQ_VREF_175mv, DME_LOCAL);
+ /*RX_SQ_VREF, lane1 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX1(RX_SQ_VREF), 0x00,
-+ RX_SQ_VREF_175mv, DME_LOCAL);
++ RX_SQ_VREF_175mv, DME_LOCAL);
+
+ /*Dif_N debouse*/
+ ufshcd_dme_set_attr(hba, ATTR_MRX0(0xeb), 0x00, 0x60, DME_LOCAL);
@@ -331798,10 +400707,10 @@ index 0000000..4ea8f24
+
+ /*AD_DIF_P_LS_TIMEOUT_VAL, lane0 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX0(AD_DIF_P_LS_TIMEOUT_VAL),
-+ 0x00, PWM_PREPARE_TO, DME_LOCAL);
++ 0x00, PWM_PREPARE_TO, DME_LOCAL);
+ /*AD_DIF_P_LS_TIMEOUT_VAL, lane1 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX1(AD_DIF_P_LS_TIMEOUT_VAL),
-+ 0x00, PWM_PREPARE_TO, DME_LOCAL);
++ 0x00, PWM_PREPARE_TO, DME_LOCAL);
+ /*RX_EQ_SEL_R, lane0 */
+ ufshcd_dme_set_attr(hba, 0x00F40004, 0x00, 0x1, DME_LOCAL);
+ /*RX_EQ_SEL_R, lane1 */
@@ -331845,21 +400754,21 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x00d40000, 0x00, 0x51, DME_LOCAL);
+ /* rate A->B 's VCO stable time */
+ /*ufshcd_dme_set_attr(hba, 0x00db0000, 0x00, 0x05, DME_LOCAL);*/
-+ #ifdef COMBO_PHY_V110
++#ifdef COMBO_PHY_V110
+ /* H8's workaround */
+ /*RX_SQ_VREF, lane0 */
+ ufshcd_dme_set_attr(hba, 0x00f10004, 0x00, 0x07, DME_LOCAL);
+ /*RX_SQ_VREF, lane1 */
+ ufshcd_dme_set_attr(hba, 0x00f10005, 0x00, 0x07, DME_LOCAL);
-+ #endif
++#endif
+#endif /*end of COMBO_PHY_V120*/
+
+ /*RX enable, lane0 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX0(MRX_EN), 0x00,
-+ MRX_ENABLE, DME_LOCAL);
++ MRX_ENABLE, DME_LOCAL);
+ /*RX enable, lane1 */
+ ufshcd_dme_set_attr(hba, ATTR_MRX1(MRX_EN), 0x00,
-+ MRX_ENABLE, DME_LOCAL);
++ MRX_ENABLE, DME_LOCAL);
+
+
+#if 0
@@ -331879,15 +400788,15 @@ index 0000000..4ea8f24
+#endif
+
+ /* disable Vswing change */
-+ /* measure the power, can close it */
-+ /*ufshcd_dme_set_attr(hba, 0x00C70000, 0x0, 0x3, DME_LOCAL);*/
-+ /* measure the power, can close it */
-+ /*ufshcd_dme_set_attr(hba, 0x00C80000, 0x0, 0x3, DME_LOCAL);*/
++ /* measure the power, can close it */
++ /*ufshcd_dme_set_attr(hba, 0x00C70000, 0x0, 0x3, DME_LOCAL);*/
++ /* measure the power, can close it */
++ /*ufshcd_dme_set_attr(hba, 0x00C80000, 0x0, 0x3, DME_LOCAL);*/
+#if !defined(COMBO_PHY_V120)
-+ ufshcd_dme_set_attr(hba, 0x007A0000, 0x0, 0x1c, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007A0001, 0x0, 0x1c, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007C0000, 0x0, 0xd4, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007C0001, 0x0, 0xd4, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007A0000, 0x0, 0x1c, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007A0001, 0x0, 0x1c, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007C0000, 0x0, 0xd4, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007C0001, 0x0, 0xd4, DME_LOCAL);
+#endif
+ /* no need to exitH8 before linkup anymore */
+ /*exit TX_HIBERNATE_CONTROL */
@@ -331935,7 +400844,7 @@ index 0000000..4ea8f24
+ /*RX_H8_EXIT*/
+ ufshcd_dme_set_attr(hba, 0x00ce0005, 0x00, 0x03, DME_LOCAL);
+
-+/* try to solve the OCS=5 */
++ /* try to solve the OCS=5 */
+ /*RX_HS_DATA_VALID_TIMER_VAL0*/
+ ufshcd_dme_set_attr(hba, 0x00E90004, 0x00, 0x20, DME_LOCAL);
+ /*RX_HS_DATA_VALID_TIMER_VAL0*/
@@ -331958,13 +400867,13 @@ index 0000000..4ea8f24
+
+ /*enlarge TX_LS_PREPARE_LENGTH*/
+ /*enable override*/
-+/*
-+ temp = uic_cmd_read(0x1, 0xd0f00000);
-+ temp |= (1<<3);
-+ ufshcd_dme_set_attr(hba, 0xd0f00000, 0x00, temp);
-+*/
++ /*
++ temp = uic_cmd_read(0x1, 0xd0f00000);
++ temp |= (1<<3);
++ ufshcd_dme_set_attr(hba, 0xd0f00000, 0x00, temp);
++ */
+ /*Set to max value 0xf*/
-+/* ufshcd_dme_set_attr(hba, 0xd0f40000, 0x00, 0x0f, DME_LOCAL);*/
++ /* ufshcd_dme_set_attr(hba, 0xd0f40000, 0x00, 0x0f, DME_LOCAL);*/
+#endif
+#if defined(OCS_5_WORKAROUND)
+ ufshcd_dme_set_attr(hba, 0x00FF0004, 0x00, 0x2, DME_LOCAL);
@@ -332049,10 +400958,10 @@ index 0000000..4ea8f24
+ //delete
+ ufshcd_dme_set_attr(hba, 0xd0ab0000, 0, 0x0, DME_LOCAL);
+ ufshcd_dme_set_attr(hba, 0xd0a00000, 0, 0xc, DME_LOCAL);
-+/*
-+ ufshcd_writel(hba, UFS_UTP_RUN_BIT, UFS_UTRLRSR_OFF);
-+ ufshcd_writel(hba, UFS_UTP_RUN_BIT, UFS_UTMRLRSR_OFF);
-+*/
++ /*
++ ufshcd_writel(hba, UFS_UTP_RUN_BIT, UFS_UTRLRSR_OFF);
++ ufshcd_writel(hba, UFS_UTP_RUN_BIT, UFS_UTMRLRSR_OFF);
++ */
+
+#ifdef CONFIG_SCSI_UFS_CARD
+ regv = ufshcd_readl(hba, UFS_BUSTHRTL_OFF);
@@ -332072,7 +400981,7 @@ index 0000000..4ea8f24
+}
+
+static int hiufs_link_startup_notify(struct ufs_hba *hba,
-+ enum ufs_notify_change_status status)
++ enum ufs_notify_change_status status)
+{
+ int err = 0;
+
@@ -332100,8 +401009,8 @@ index 0000000..4ea8f24
+}
+
+int do_mode_change(struct ufs_hba *hba,
-+ const struct pwrModeParams *pmp,
-+ int scramble, int termination)
++ const struct pwrModeParams *pmp,
++ int scramble, int termination)
+{
+
+ /*RX enable, lane0 */
@@ -332131,10 +401040,10 @@ index 0000000..4ea8f24
+ }
+
+ if (scramble)
-+ /* PA_Scrambling */
++ /* PA_Scrambling */
+ ufshcd_dme_set_attr(hba, 0x15850000, 0x0, 0x1, DME_LOCAL);
+ else
-+ /* PA_Scrambling */
++ /* PA_Scrambling */
+ ufshcd_dme_set_attr(hba, 0x15850000, 0x0, 0x0, DME_LOCAL);
+
+ } else if (pmp->pwrMode == SLOW_MODE || pmp->pwrMode == SLOWAUTO_MODE) {
@@ -332189,13 +401098,13 @@ index 0000000..4ea8f24
+
+ /* PA_PWRMode */
+ ufshcd_dme_set_attr(hba, 0x15710000, 0x0,
-+ (pmp->pwrMode<<4|pmp->pwrMode), DME_LOCAL);
++ (pmp->pwrMode<<4|pmp->pwrMode), DME_LOCAL);
+ /*FUNC_EXIT();*/
+ return 0;
+}
+
+static void adapt_pll_to_power_mode(struct ufs_hba *hba,
-+ uint8_t pwrmode, uint8_t gear, uint8_t rate, uint32_t line)
++ uint8_t pwrmode, uint8_t gear, uint8_t rate, uint32_t line)
+{
+#ifdef COMBO_PHY_V100
+ uint32_t value;
@@ -332265,7 +401174,7 @@ index 0000000..4ea8f24
+ }
+ }
+ }
-+ #endif
++#endif
+
+ /*the PWM's clk is been derived from the pll above*/
+ if (SLOW_MODE == pwrmode || SLOWAUTO_MODE == pwrmode) {
@@ -332284,13 +401193,13 @@ index 0000000..4ea8f24
+ }
+ }
+
-+ #ifdef COMBO_PHY_V100
++#ifdef COMBO_PHY_V100
+ /* just for test begin */
+ ufshcd_dme_set_attr(hba, 0x00f50004, 0x00, 0x01, DME_LOCAL);
+ /* mphy config update */
+ ufshcd_dme_set_attr(hba, 0xd0850000, 0x00, 0x01, DME_LOCAL);
+ /* just for test end */
-+ #endif
++#endif
+
+ /*ufs_waitms(50);*/
+ /*exit TX_HIBERNATE_CONTROL */
@@ -332302,7 +401211,7 @@ index 0000000..4ea8f24
+}
+
+static void ufsphy_eye_configuration(struct ufs_hba *hba,
-+ uint8_t pwrmode, uint8_t gear, uint8_t rate, uint32_t line)
++ uint8_t pwrmode, uint8_t gear, uint8_t rate, uint32_t line)
+{
+ if (FAST_MODE == pwrmode || FASTAUTO_MODE == pwrmode) {
+ if (UFS_HS_G1 == gear) {
@@ -332313,11 +401222,11 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x00370000, 0x00, 0x20, DME_LOCAL);
+ ufshcd_dme_set_attr(hba, 0x007b0000, 0x00, 0x20, DME_LOCAL);
+ if (line == 2) {
-+ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x13, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x13, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x20, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x20, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x13, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x13, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x20, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x20, DME_LOCAL);
+ }
+ } else if (PA_HS_MODE_B == rate) {
+ ufshcd_dme_set_attr(hba, 0x007e0000, 0x00, 0x05, DME_LOCAL);
@@ -332326,11 +401235,11 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x00370000, 0x00, 0x20, DME_LOCAL);
+ ufshcd_dme_set_attr(hba, 0x007b0000, 0x00, 0x20, DME_LOCAL);
+ if (line == 2) {
-+ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x13, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x13, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x20, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x20, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x13, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x13, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x20, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x20, DME_LOCAL);
+ }
+ }
+
@@ -332342,11 +401251,11 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x00370000, 0x00, 0x23, DME_LOCAL);
+ ufshcd_dme_set_attr(hba, 0x007b0000, 0x00, 0x23, DME_LOCAL);
+ if (line == 2) {
-+ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x21, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x21, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x23, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x23, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x21, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x21, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x23, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x23, DME_LOCAL);
+ }
+ } else if (PA_HS_MODE_B == rate) {
+ ufshcd_dme_set_attr(hba, 0x007e0000, 0x00, 0x05, DME_LOCAL);
@@ -332355,11 +401264,11 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x00370000, 0x00, 0x23, DME_LOCAL);
+ ufshcd_dme_set_attr(hba, 0x007b0000, 0x00, 0x23, DME_LOCAL);
+ if (line == 2) {
-+ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x21, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x21, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x23, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x23, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x21, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x21, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x23, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x23, DME_LOCAL);
+ }
+ }
+ } else if (UFS_HS_G3 == gear) {
@@ -332370,11 +401279,11 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x00370000, 0x00, 0x26, DME_LOCAL);
+ ufshcd_dme_set_attr(hba, 0x007b0000, 0x00, 0x26, DME_LOCAL);
+ if (line == 2) {
-+ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x22, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x22, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x26, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x26, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x22, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x22, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x26, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x26, DME_LOCAL);
+ }
+ } else if (PA_HS_MODE_B == rate) {
+ ufshcd_dme_set_attr(hba, 0x007e0000, 0x00, 0x05, DME_LOCAL);
@@ -332383,11 +401292,11 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x00370000, 0x00, 0x26, DME_LOCAL);
+ ufshcd_dme_set_attr(hba, 0x007b0000, 0x00, 0x26, DME_LOCAL);
+ if (line == 2) {
-+ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x24, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x24, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x26, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x26, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007e0001, 0x00, 0x05, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007f0001, 0x00, 0x24, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007d0001, 0x00, 0x24, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x00370001, 0x00, 0x26, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007b0001, 0x00, 0x26, DME_LOCAL);
+ }
+ }
+ }
@@ -332395,8 +401304,8 @@ index 0000000..4ea8f24
+}
+
+static int change_power_mode(struct ufs_hba *hba, uint8_t pwrmode,
-+ uint8_t gear, uint8_t rate,
-+ int line, int scramble, int termination)
++ uint8_t gear, uint8_t rate,
++ int line, int scramble, int termination)
+{
+ int err;
+ u32 set;
@@ -332426,15 +401335,15 @@ index 0000000..4ea8f24
+ //modefy end
+ if ((tx_lane_num > 1) && (rx_lane_num > 1)) {
+ ufshcd_dme_set_attr(hba, 0x007e0001, 0x0, 0x05, DME_LOCAL);
-+ //modefy begin
-+ //ufshcd_dme_set_attr(hba, 0x00250000, 0x0, 0x22, DME_LOCAL);
-+ ufshcd_dme_set_attr(hba, 0x007f0001, 0x0, 0x22, DME_LOCAL);
-+ //modefy end
++ //modefy begin
++ //ufshcd_dme_set_attr(hba, 0x00250000, 0x0, 0x22, DME_LOCAL);
++ ufshcd_dme_set_attr(hba, 0x007f0001, 0x0, 0x22, DME_LOCAL);
++ //modefy end
+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x0, 0x22, DME_LOCAL);
-+ //modefy add
-+ ufshcd_dme_set_attr(hba, 0x00fc0005, 0x0, 0x1f, DME_LOCAL);/*RX_S*/
-+ ufshcd_dme_set_attr(hba, 0x00fd0005, 0x0, 0x00, DME_LOCAL);/*RX_GEAR1_SET*/
-+ //modefy add
++ //modefy add
++ ufshcd_dme_set_attr(hba, 0x00fc0005, 0x0, 0x1f, DME_LOCAL);/*RX_S*/
++ ufshcd_dme_set_attr(hba, 0x00fd0005, 0x0, 0x00, DME_LOCAL);/*RX_GEAR1_SET*/
++ //modefy add
+ }
+ } else {
+ value = 0x6F; /* 6.85 dB */
@@ -332447,27 +401356,21 @@ index 0000000..4ea8f24
+ ufshcd_dme_set_attr(hba, 0x007d0001, 0x0, 0x15, DME_LOCAL);
+ }
+ //modefy add
-+ ufshcd_dme_set_attr(hba, 0x00fc0004, 0x0, 0x1b, DME_LOCAL);/*RX_S*/
-+ if ((tx_lane_num > 1) && (rx_lane_num > 1))
-+ {
-+ ufshcd_dme_set_attr(hba, 0x00fc0005, 0x0, 0x1b, DME_LOCAL);/*RX_S*/
++ ufshcd_dme_set_attr(hba, 0x00fc0004, 0x0, 0x1b, DME_LOCAL);/*RX_S*/
++ if ((tx_lane_num > 1) && (rx_lane_num > 1)) {
++ ufshcd_dme_set_attr(hba, 0x00fc0005, 0x0, 0x1b, DME_LOCAL);/*RX_S*/
++ }
++ if(1 == gear) {
++ ufshcd_dme_set_attr(hba, 0x00fd0004, 0x0, 0x01, DME_LOCAL);/*RX_GEAR1_SET*/
++ if ((tx_lane_num > 1) && (rx_lane_num > 1)) {
++ ufshcd_dme_set_attr(hba, 0x00fd0005, 0x0, 0x01, DME_LOCAL);/*RX_GEAR1_SET*/
+ }
-+ if(1 == gear)
-+ {
-+ ufshcd_dme_set_attr(hba, 0x00fd0004, 0x0, 0x01, DME_LOCAL);/*RX_GEAR1_SET*/
-+ if ((tx_lane_num > 1) && (rx_lane_num > 1))
-+ {
-+ ufshcd_dme_set_attr(hba, 0x00fd0005, 0x0, 0x01, DME_LOCAL);/*RX_GEAR1_SET*/
-+ }
-+ }
-+ else if(2 == gear)
-+ {
-+ ufshcd_dme_set_attr(hba, 0x00fd0004, 0x0, 0x00, DME_LOCAL);/*RX_GEAR1_SET*/
-+ if ((tx_lane_num > 1) && (rx_lane_num > 1))
-+ {
-+ ufshcd_dme_set_attr(hba, 0x00fd0005, 0x0, 0x00, DME_LOCAL);/*RX_GEAR1_SET*/
-+ }
++ } else if(2 == gear) {
++ ufshcd_dme_set_attr(hba, 0x00fd0004, 0x0, 0x00, DME_LOCAL);/*RX_GEAR1_SET*/
++ if ((tx_lane_num > 1) && (rx_lane_num > 1)) {
++ ufshcd_dme_set_attr(hba, 0x00fd0005, 0x0, 0x00, DME_LOCAL);/*RX_GEAR1_SET*/
+ }
++ }
+ //modefy add
+ }
+
@@ -332513,7 +401416,7 @@ index 0000000..4ea8f24
+ if ( !auto_chg & VCO_AUTO_CHG_EN )
+ adapt_pll_to_power_mode(hba, pwrmode, gear, rate, rx_lane_num);
+#endif
-+ ufsphy_eye_configuration(hba, pwrmode, gear, rate, rx_lane_num);
++ ufsphy_eye_configuration(hba, pwrmode, gear, rate, rx_lane_num);
+ err = do_mode_change(hba, &pmp, scramble, termination);
+ if (err) {
+ UFS_PRINT("do_mode_change failed\n");
@@ -332545,11 +401448,11 @@ index 0000000..4ea8f24
+ UFS_PRINT("power mode change success\n");
+
+ UFS_PRINT("UFS %s Gear-%d Rate-%c Lanes-%d Scrmbl-%d Termn-%d\n",
-+ ((SLOW_MODE == pwrmode)?"Slow" :
-+ ((SLOWAUTO_MODE == pwrmode)?"SlowAuto" :
-+ ((FAST_MODE == pwrmode)?"Fast" : "FastAuto"))),
-+ gear, (rate == 1)?'A' : 'B', rx_lane_num,
-+ scramble, termination);
++ ((SLOW_MODE == pwrmode)?"Slow" :
++ ((SLOWAUTO_MODE == pwrmode)?"SlowAuto" :
++ ((FAST_MODE == pwrmode)?"Fast" : "FastAuto"))),
++ gear, (rate == 1)?'A' : 'B', rx_lane_num,
++ scramble, termination);
+ /* RX_ERR_STATUS */
+ ufshcd_dme_set_attr(hba, 0x00c40004, 0x0, 0x80, DME_LOCAL);
+ /* RX_ERR_STATUS */
@@ -332566,7 +401469,7 @@ index 0000000..4ea8f24
+}
+
+static int hiufs_config_power_mode(struct ufs_hba *hba,
-+ struct ufs_pa_layer_attr *dev_max_params)
++ struct ufs_pa_layer_attr *dev_max_params)
+{
+ uint32_t gear = dev_max_params->gear_rx;
+ uint32_t rate = dev_max_params->hs_rate;
@@ -332580,18 +401483,18 @@ index 0000000..4ea8f24
+}
+
+static int hiufs_pwr_change_notify(struct ufs_hba *hba,
-+ enum ufs_notify_change_status status,
-+ struct ufs_pa_layer_attr *dev_max_params,
-+ struct ufs_pa_layer_attr *dev_req_params)
++ enum ufs_notify_change_status status,
++ struct ufs_pa_layer_attr *dev_max_params,
++ struct ufs_pa_layer_attr *dev_req_params)
+{
+ int err = 0;
+
+ if (status == PRE_CHANGE) {
+ err = hiufs_config_power_mode(hba, dev_max_params);
+ memcpy(dev_req_params, dev_max_params,
-+ sizeof(struct ufs_pa_layer_attr));
-+ memcpy(&hba->pwr_info, dev_max_params,
-+ sizeof(struct ufs_pa_layer_attr));
++ sizeof(struct ufs_pa_layer_attr));
++ memcpy(&hba->pwr_info, dev_max_params,
++ sizeof(struct ufs_pa_layer_attr));
+ }
+
+ return err;
@@ -332847,7 +401750,7 @@ index 845b874..4852b74 100644
};
diff --git a/drivers/scsi/ufs/ufs_proc.c b/drivers/scsi/ufs/ufs_proc.c
new file mode 100644
-index 0000000..0701d93
+index 0000000..004d9d0
--- /dev/null
+++ b/drivers/scsi/ufs/ufs_proc.c
@@ -0,0 +1,245 @@
@@ -332922,21 +401825,21 @@ index 0000000..0701d93
+ iserialnumber = desc_buf[DEVICE_DESC_PARAM_SN];
+
+ err = ufshcd_read_string_desc(hba, imanufacturername, str_desc_buf,
-+ QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
++ QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
+ if (err)
+ return err;
+ strlcpy(card_info->manufacturer_name, (str_desc_buf + 2), str_desc_buf[0] - 2);
+ card_info->manufacturer_name[MAX_MANUF_SIZE - 1] = '\0';
+
+ err = ufshcd_read_string_desc(hba, iproductname, str_desc_buf,
-+ QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
++ QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
+ if (err)
+ return err;
+ strlcpy(card_info->product_name, (str_desc_buf + 2), str_desc_buf[0] - 2);
+ card_info->product_name[MAX_PROD_SIZE - 1] = '\0';
+
+ err = ufshcd_read_string_desc(hba, iserialnumber, str_desc_buf,
-+ QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
++ QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
+ if (err)
+ return err;
+ strlcpy(card_info->serial_number, (str_desc_buf + 2), str_desc_buf[0] - 2);
@@ -332981,17 +401884,17 @@ index 0000000..0701d93
+ continue;
+ }
+
-+ seq_printf(s, "\tType: %s\n", ufs_get_card_type(0));
++ seq_printf(s, "\tType: %s\n", ufs_get_card_type(0));
+
+ pwrmode = hba->pwr_info.pwr_rx;
+ gear = hba->pwr_info.gear_rx;
+ rate = hba->pwr_info.hs_rate;
+ lane = hba->pwr_info.lane_rx;
+ seq_printf(s, "\tMode: %s Gear-%d Rate-%c Lanes-%d\n",
-+ ((FAST_MODE == pwrmode) ? "Fast" :
-+ ((FASTAUTO_MODE == pwrmode) ? "FastAuto" :
-+ ((SLOW_MODE == pwrmode) ? "Slow" : "SlowAuto"))),
-+ gear, (PA_HS_MODE_A == rate) ? 'A' : 'B', lane);
++ ((FAST_MODE == pwrmode) ? "Fast" :
++ ((FASTAUTO_MODE == pwrmode) ? "FastAuto" :
++ ((SLOW_MODE == pwrmode) ? "Slow" : "SlowAuto"))),
++ gear, (PA_HS_MODE_A == rate) ? 'A' : 'B', lane);
+
+ err = ufs_get_card_info(hba, &card_info);
+ if (err)
@@ -333071,15 +401974,15 @@ index 0000000..0701d93
+ proc_ufs_dir = proc_mkdir(UFS_PARENT, NULL);
+ if (!proc_ufs_dir) {
+ pr_err("%s: failed to create proc file %s\n",
-+ __func__, UFS_PARENT);
++ __func__, UFS_PARENT);
+ return 1;
+ }
+
+ proc_stats_entry = proc_create(UFS_STATS_PROC,
-+ 0, proc_ufs_dir, &ufs_stats_proc_ops);
++ 0, proc_ufs_dir, &ufs_stats_proc_ops);
+ if (!proc_stats_entry) {
+ pr_err("%s: failed to create proc file %s\n",
-+ __func__, UFS_STATS_PROC);
++ __func__, UFS_STATS_PROC);
+ return 1;
+ }
+
@@ -333098,7 +402001,7 @@ index 0000000..0701d93
+}
diff --git a/drivers/scsi/ufs/ufs_proc.h b/drivers/scsi/ufs/ufs_proc.h
new file mode 100644
-index 0000000..564b03f
+index 0000000..8135f24
--- /dev/null
+++ b/drivers/scsi/ufs/ufs_proc.h
@@ -0,0 +1,39 @@
@@ -333130,7 +402033,7 @@ index 0000000..564b03f
+
+#define MAX_CARD_TYPE 1
+
-+#ifdef CONFIG_ARCH_HI3559AV100
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+#define UFS_SLOT_NUM 1
+#endif
+
@@ -334327,7 +403230,7 @@ index 9599741..5623317 100644
REG_INTERRUPT_ENABLE = 0x24,
REG_CONTROLLER_STATUS = 0x30,
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
-index f7f7ba1..15aeded 100644
+index f7f7ba1..c3cb37e 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -43,6 +43,7 @@
@@ -334508,7 +403411,19 @@ index f7f7ba1..15aeded 100644
} else {
writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
-@@ -1289,7 +1384,6 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
+@@ -1116,7 +1211,10 @@ static int configure_dma(struct pl022 *pl022)
+ static int pl022_dma_probe(struct pl022 *pl022)
+ {
+ dma_cap_mask_t mask;
+-
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
++ dev_dbg(&pl022->adev->dev, "spi in soc cannot work with dma!\n");
++ return -ENODEV;
++#endif
+ /* Try to acquire a generic DMA engine slave channel */
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+@@ -1289,7 +1387,6 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
dev_err(&pl022->adev->dev,
"RXFIFO is full\n");
@@ -334516,7 +403431,7 @@ index f7f7ba1..15aeded 100644
/*
* Disable and clear interrupts, disable SSP,
* mark message with bad status so it can be
-@@ -1835,6 +1929,13 @@ static int pl022_setup(struct spi_device *spi)
+@@ -1835,6 +1932,13 @@ static int pl022_setup(struct spi_device *spi)
unsigned int bits = spi->bits_per_word;
u32 tmp;
struct device_node *np = spi->dev.of_node;
@@ -334530,7 +403445,7 @@ index f7f7ba1..15aeded 100644
if (!spi->max_speed_hz)
return -EINVAL;
-@@ -1977,7 +2078,12 @@ static int pl022_setup(struct spi_device *spi)
+@@ -1977,7 +2081,12 @@ static int pl022_setup(struct spi_device *spi)
chip->cpsr = clk_freq.cpsdvsr;
/* Special setup for the ST micro extended control registers */
@@ -334543,7 +403458,7 @@ index f7f7ba1..15aeded 100644
u32 etx;
if (pl022->vendor->pl023) {
-@@ -2011,6 +2117,22 @@ static int pl022_setup(struct spi_device *spi)
+@@ -2011,6 +2120,22 @@ static int pl022_setup(struct spi_device *spi)
SSP_CR1_MASK_RXIFLSEL_ST, 7);
SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
SSP_CR1_MASK_TXIFLSEL_ST, 10);
@@ -334566,7 +403481,7 @@ index f7f7ba1..15aeded 100644
} else {
SSP_WRITE_BITS(chip->cr0, bits - 1,
SSP_CR0_MASK_DSS, 0);
-@@ -2042,7 +2164,7 @@ static int pl022_setup(struct spi_device *spi)
+@@ -2042,7 +2167,7 @@ static int pl022_setup(struct spi_device *spi)
}
SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
@@ -334575,7 +403490,7 @@ index f7f7ba1..15aeded 100644
3);
/* Save controller_state */
-@@ -2074,7 +2196,7 @@ pl022_platform_data_dt_get(struct device *dev)
+@@ -2074,7 +2199,7 @@ pl022_platform_data_dt_get(struct device *dev)
{
struct device_node *np = dev->of_node;
struct pl022_ssp_controller *pd;
@@ -334584,7 +403499,7 @@ index f7f7ba1..15aeded 100644
if (!np) {
dev_err(dev, "no dt node defined\n");
-@@ -2099,6 +2221,8 @@ pl022_platform_data_dt_get(struct device *dev)
+@@ -2099,6 +2224,8 @@ pl022_platform_data_dt_get(struct device *dev)
static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
@@ -334593,7 +403508,7 @@ index f7f7ba1..15aeded 100644
struct pl022_ssp_controller *platform_info =
dev_get_platdata(&adev->dev);
struct spi_master *master;
-@@ -2162,6 +2286,43 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
+@@ -2162,6 +2289,43 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
} else if (pl022->vendor->internal_cs_ctrl) {
for (i = 0; i < num_cs; i++)
pl022->chipselects[i] = i;
@@ -334637,7 +403552,7 @@ index f7f7ba1..15aeded 100644
} else if (IS_ENABLED(CONFIG_OF)) {
for (i = 0; i < num_cs; i++) {
int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
-@@ -2288,6 +2449,11 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
+@@ -2288,6 +2452,11 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
err_no_ioremap:
amba_release_regions(adev);
err_no_ioregion:
@@ -334649,7 +403564,7 @@ index f7f7ba1..15aeded 100644
err_no_gpio:
err_no_mem:
spi_master_put(master);
-@@ -2314,6 +2480,11 @@ pl022_remove(struct amba_device *adev)
+@@ -2314,6 +2483,11 @@ pl022_remove(struct amba_device *adev)
clk_disable_unprepare(pl022->clk);
amba_release_regions(adev);
@@ -334661,7 +403576,7 @@ index f7f7ba1..15aeded 100644
tasklet_disable(&pl022->pump_transfers);
return 0;
}
-@@ -2429,6 +2600,18 @@ static struct vendor_data vendor_lsi = {
+@@ -2429,6 +2603,18 @@ static struct vendor_data vendor_lsi = {
.internal_cs_ctrl = true,
};
@@ -334680,7 +403595,7 @@ index f7f7ba1..15aeded 100644
static struct amba_id pl022_ids[] = {
{
/*
-@@ -2469,6 +2652,17 @@ static struct amba_id pl022_ids[] = {
+@@ -2469,6 +2655,17 @@ static struct amba_id pl022_ids[] = {
.mask = 0x000fffff,
.data = &vendor_lsi,
},
@@ -334945,7 +403860,7 @@ index 5133ab9..6e0fcd7 100644
if (urb->number_of_packets <= 0)
return -EINVAL;
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
-index 22420e1..7f5ea26 100644
+index 22420e1..c3dcf13 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -1,9 +1,12 @@
@@ -334957,14 +403872,14 @@ index 22420e1..7f5ea26 100644
-dwc3-y := core.o debug.o trace.o
+dwc3-y := core.o proc.o
-+ifneq ($(CONFIG_FTRACE),)
-+ dwc3-y += debug.o trace.o
++ifneq ($(CONFIG_TRACING),)
++ dwc3-y += trace.o
+endif
ifneq ($(filter y,$(CONFIG_USB_DWC3_HOST) $(CONFIG_USB_DWC3_DUAL_ROLE)),)
dwc3-y += host.o
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
-index fea4469..fc53432 100644
+index fea4469..8f8adf7 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -44,11 +44,27 @@
@@ -334995,7 +403910,48 @@ index fea4469..fc53432 100644
/**
* dwc3_get_dr_mode - Validates and sets dr_mode
* @dwc: pointer to our context structure
-@@ -982,7 +998,8 @@ static int dwc3_probe(struct platform_device *pdev)
+@@ -305,13 +321,7 @@ static int dwc3_event_buffers_setup(struct dwc3 *dwc)
+ struct dwc3_event_buffer *evt;
+
+ evt = dwc->ev_buf;
+- dwc3_trace(trace_dwc3_core,
+- "Event buf %p dma %08llx length %d\n",
+- evt->buf, (unsigned long long) evt->dma,
+- evt->length);
+-
+ evt->lpos = 0;
+-
+ dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
+ lower_32_bits(evt->dma));
+ dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
+@@ -428,9 +438,6 @@ static void dwc3_core_num_eps(struct dwc3 *dwc)
+
+ dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
+ dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
+-
+- dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
+- dwc->num_in_eps, dwc->num_out_eps);
+ }
+
+ static void dwc3_cache_hwparams(struct dwc3 *dwc)
+@@ -683,13 +690,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
+ reg |= DWC3_GCTL_GBLHIBERNATIONEN;
+ break;
+ default:
+- dwc3_trace(trace_dwc3_core, "No power optimization available\n");
++ /* nothing */
++ break;
+ }
+
+ /* check if current dwc3 is on simulation board */
+ if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
+- dwc3_trace(trace_dwc3_core,
+- "running on FPGA platform\n");
++ dev_info(dwc->dev, "Running with FPGA optmizations\n");
+ dwc->is_fpga = true;
+ }
+
+@@ -982,7 +989,8 @@ static int dwc3_probe(struct platform_device *pdev)
*/
hird_threshold = 12;
@@ -335005,7 +403961,7 @@ index fea4469..fc53432 100644
dwc->dr_mode = usb_get_dr_mode(dev);
dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
-@@ -996,6 +1013,8 @@ static int dwc3_probe(struct platform_device *pdev)
+@@ -996,6 +1004,8 @@ static int dwc3_probe(struct platform_device *pdev)
&hird_threshold);
dwc->usb3_lpm_capable = device_property_read_bool(dev,
"snps,usb3_lpm_capable");
@@ -335014,7 +403970,7 @@ index fea4469..fc53432 100644
dwc->disable_scramble_quirk = device_property_read_bool(dev,
"snps,disable_scramble_quirk");
-@@ -1026,6 +1045,16 @@ static int dwc3_probe(struct platform_device *pdev)
+@@ -1026,6 +1036,16 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
"snps,dis-del-phy-power-chg-quirk");
@@ -335031,7 +403987,7 @@ index fea4469..fc53432 100644
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
"snps,tx_de_emphasis_quirk");
device_property_read_u8(dev, "snps,tx_de_emphasis",
-@@ -1087,6 +1116,8 @@ static int dwc3_probe(struct platform_device *pdev)
+@@ -1087,6 +1107,8 @@ static int dwc3_probe(struct platform_device *pdev)
goto err4;
}
@@ -335040,7 +403996,7 @@ index fea4469..fc53432 100644
/* Check the maximum_speed parameter */
switch (dwc->maximum_speed) {
case USB_SPEED_LOW:
-@@ -1177,6 +1208,10 @@ static int dwc3_remove(struct platform_device *pdev)
+@@ -1177,6 +1199,10 @@ static int dwc3_remove(struct platform_device *pdev)
dwc3_free_event_buffers(dwc);
dwc3_free_scratch_buffers(dwc);
@@ -335052,7 +404008,7 @@ index fea4469..fc53432 100644
}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
-index 884c437..3d3cb82 100644
+index 884c437..e0bc26a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -35,6 +35,8 @@
@@ -335074,15 +404030,36 @@ index 884c437..3d3cb82 100644
#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
-@@ -536,6 +541,7 @@ struct dwc3_ep {
+@@ -488,7 +493,7 @@ struct dwc3_event_buffer {
+ #define DWC3_EP_DIRECTION_TX true
+ #define DWC3_EP_DIRECTION_RX false
+
+-#define DWC3_TRB_NUM 256
++#define DWC3_TRB_NUM 4096
+
+ /**
+ * struct dwc3_ep - device side endpoint representation
+@@ -535,7 +540,8 @@ struct dwc3_ep {
+ #define DWC3_EP_WEDGE (1 << 2)
#define DWC3_EP_BUSY (1 << 4)
#define DWC3_EP_PENDING_REQUEST (1 << 5)
- #define DWC3_EP_MISSED_ISOC (1 << 6)
+-#define DWC3_EP_MISSED_ISOC (1 << 6)
++#define DWC3_EP_MISSED_ISOC (1 << 6)
+#define DWC3_EP_UPDATE (1 << 7)
/* This last one is specific to EP0 */
#define DWC3_EP0_DIR_IN (1 << 31)
-@@ -557,6 +563,7 @@ struct dwc3_ep {
+@@ -549,14 +555,15 @@ struct dwc3_ep {
+ * By using u8 types we ensure that our % operator when incrementing
+ * enqueue and dequeue get optimized away by the compiler.
+ */
+- u8 trb_enqueue;
+- u8 trb_dequeue;
++ u32 trb_enqueue;
++ u32 trb_dequeue;
+
+ u8 number;
+ u8 type;
u8 resource_index;
u32 allocated_requests;
u32 queued_requests;
@@ -335155,14 +404132,79 @@ index 884c437..3d3cb82 100644
/* power management interface */
#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
int dwc3_gadget_suspend(struct dwc3 *dwc);
+diff --git a/drivers/usb/dwc3/debug.c b/drivers/usb/dwc3/debug.c
+deleted file mode 100644
+index 0be6885..0000000
+--- a/drivers/usb/dwc3/debug.c
++++ /dev/null
+@@ -1,32 +0,0 @@
+-/**
+- * debug.c - DesignWare USB3 DRD Controller Debug/Trace Support
+- *
+- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+- *
+- * Author: Felipe Balbi <balbi@ti.com>
+- *
+- * This program is free software: you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 of
+- * the License as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- */
+-
+-#include "debug.h"
+-
+-void dwc3_trace(void (*trace)(struct va_format *), const char *fmt, ...)
+-{
+- struct va_format vaf;
+- va_list args;
+-
+- va_start(args, fmt);
+- vaf.fmt = fmt;
+- vaf.va = &args;
+-
+- trace(&vaf);
+-
+- va_end(args);
+-}
diff --git a/drivers/usb/dwc3/debug.h b/drivers/usb/dwc3/debug.h
-index 33ab2a2..cdd644d 100644
+index 33ab2a2..9242f40 100644
--- a/drivers/usb/dwc3/debug.h
+++ b/drivers/usb/dwc3/debug.h
-@@ -124,6 +124,22 @@ dwc3_gadget_link_string(enum dwc3_link_state link_state)
- }
+@@ -125,55 +125,344 @@ dwc3_gadget_link_string(enum dwc3_link_state link_state)
}
+ /**
++ * dwc3_trb_type_string - returns TRB type as a string
++ * @type: the type of the TRB
++ */
++static inline const char *dwc3_trb_type_string(unsigned int type)
++{
++ switch (type) {
++ case DWC3_TRBCTL_NORMAL:
++ return "normal";
++ case DWC3_TRBCTL_CONTROL_SETUP:
++ return "setup";
++ case DWC3_TRBCTL_CONTROL_STATUS2:
++ return "status2";
++ case DWC3_TRBCTL_CONTROL_STATUS3:
++ return "status3";
++ case DWC3_TRBCTL_CONTROL_DATA:
++ return "data";
++ case DWC3_TRBCTL_ISOCHRONOUS_FIRST:
++ return "isoc-first";
++ case DWC3_TRBCTL_ISOCHRONOUS:
++ return "isoc";
++ case DWC3_TRBCTL_LINK_TRB:
++ return "link";
++ default:
++ return "UNKNOWN";
++ }
++}
++
+static inline const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
+{
+ switch (state) {
@@ -335179,23 +404221,336 @@ index 33ab2a2..cdd644d 100644
+ }
+}
+
- /**
++/**
* dwc3_gadget_event_string - returns event name
* @event: the event code
-@@ -184,10 +200,11 @@ dwc3_gadget_event_string(const struct dwc3_event_devt *event)
+ */
+-static inline const char *
+-dwc3_gadget_event_string(const struct dwc3_event_devt *event)
++static inline const char *dwc3_gadget_event_string(char *str, size_t size,
++ const struct dwc3_event_devt *event)
+ {
+- static char str[256];
+ enum dwc3_link_state state = event->event_info & DWC3_LINK_STATE_MASK;
+
+ switch (event->type) {
+ case DWC3_DEVICE_EVENT_DISCONNECT:
+- sprintf(str, "Disconnect: [%s]",
++ snprintf(str, size, "Disconnect: [%s]",
+ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_RESET:
+- sprintf(str, "Reset [%s]", dwc3_gadget_link_string(state));
++ snprintf(str, size, "Reset [%s]",
++ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_CONNECT_DONE:
+- sprintf(str, "Connection Done [%s]",
++ snprintf(str, size, "Connection Done [%s]",
+ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
+- sprintf(str, "Link Change [%s]",
++ snprintf(str, size, "Link Change [%s]",
+ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_WAKEUP:
+- sprintf(str, "WakeUp [%s]", dwc3_gadget_link_string(state));
++ snprintf(str, size, "WakeUp [%s]",
++ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_EOPF:
+- sprintf(str, "End-Of-Frame [%s]",
++ snprintf(str, size, "End-Of-Frame [%s]",
+ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_SOF:
+- sprintf(str, "Start-Of-Frame [%s]",
++ snprintf(str, size, "Start-Of-Frame [%s]",
+ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
+- sprintf(str, "Erratic Error [%s]",
++ snprintf(str, size, "Erratic Error [%s]",
+ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_CMD_CMPL:
+- sprintf(str, "Command Complete [%s]",
++ snprintf(str, size, "Command Complete [%s]",
+ dwc3_gadget_link_string(state));
+ break;
+ case DWC3_DEVICE_EVENT_OVERFLOW:
+- sprintf(str, "Overflow [%s]", dwc3_gadget_link_string(state));
++ snprintf(str, size, "Overflow [%s]",
++ dwc3_gadget_link_string(state));
+ break;
+ default:
+- sprintf(str, "UNKNOWN");
++ snprintf(str, size, "UNKNOWN");
++ }
++
++ return str;
++}
++
++static inline void dwc3_decode_get_status(__u8 t, __u16 i, __u16 l, char *str,
++ size_t size)
++{
++ switch (t & USB_RECIP_MASK) {
++ case USB_RECIP_DEVICE:
++ snprintf(str, size, "Get Device Status(Length = %d)", l);
++ break;
++ case USB_RECIP_INTERFACE:
++ snprintf(str, size, "Get Interface Status(Intf = %d, Length = %d)",
++ i, l);
++ break;
++ case USB_RECIP_ENDPOINT:
++ snprintf(str, size, "Get Endpoint Status(ep%d%s)",
++ i & ~USB_DIR_IN,
++ i & USB_DIR_IN ? "in" : "out");
++ break;
++ }
++}
++
++static inline void dwc3_decode_set_clear_feature(__u8 t, __u8 b, __u16 v,
++ __u16 i, char *str, size_t size)
++{
++ switch (t & USB_RECIP_MASK) {
++ case USB_RECIP_DEVICE:
++ snprintf(str, size, "%s Device Feature(%s%s)",
++ b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
++ ({char *s;
++ switch (v) {
++ case USB_DEVICE_SELF_POWERED:
++ s = "Self Powered";
++ break;
++ case USB_DEVICE_REMOTE_WAKEUP:
++ s = "Remote Wakeup";
++ break;
++ case USB_DEVICE_TEST_MODE:
++ s = "Test Mode";
++ break;
++ default:
++ s = "UNKNOWN";
++ } s; }),
++ v == USB_DEVICE_TEST_MODE ?
++ ({ char *s;
++ switch (i) {
++ case TEST_J:
++ s = ": TEST_J";
++ break;
++ case TEST_K:
++ s = ": TEST_K";
++ break;
++ case TEST_SE0_NAK:
++ s = ": TEST_SE0_NAK";
++ break;
++ case TEST_PACKET:
++ s = ": TEST_PACKET";
++ break;
++ case TEST_FORCE_EN:
++ s = ": TEST_FORCE_EN";
++ break;
++ default:
++ s = ": UNKNOWN";
++ } s; }) : "");
++ break;
++ case USB_RECIP_INTERFACE:
++ snprintf(str, size, "%s Interface Feature(%s)",
++ b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
++ v == USB_INTRF_FUNC_SUSPEND ?
++ "Function Suspend" : "UNKNOWN");
++ break;
++ case USB_RECIP_ENDPOINT:
++ snprintf(str, size, "%s Endpoint Feature(%s ep%d%s)",
++ b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
++ v == USB_ENDPOINT_HALT ? "Halt" : "UNKNOWN",
++ i & ~USB_DIR_IN,
++ i & USB_DIR_IN ? "in" : "out");
++ break;
++ }
++}
++
++static inline void dwc3_decode_set_address(__u16 v, char *str, size_t size)
++{
++ snprintf(str, size, "Set Address(Addr = %02x)", v);
++}
++
++static inline void dwc3_decode_get_set_descriptor(__u8 t, __u8 b, __u16 v,
++ __u16 i, __u16 l, char *str, size_t size)
++{
++ snprintf(str, size, "%s %s Descriptor(Index = %d, Length = %d)",
++ b == USB_REQ_GET_DESCRIPTOR ? "Get" : "Set",
++ ({ char *s;
++ switch (v >> 8) {
++ case USB_DT_DEVICE:
++ s = "Device";
++ break;
++ case USB_DT_CONFIG:
++ s = "Configuration";
++ break;
++ case USB_DT_STRING:
++ s = "String";
++ break;
++ case USB_DT_INTERFACE:
++ s = "Interface";
++ break;
++ case USB_DT_ENDPOINT:
++ s = "Endpoint";
++ break;
++ case USB_DT_DEVICE_QUALIFIER:
++ s = "Device Qualifier";
++ break;
++ case USB_DT_OTHER_SPEED_CONFIG:
++ s = "Other Speed Config";
++ break;
++ case USB_DT_INTERFACE_POWER:
++ s = "Interface Power";
++ break;
++ case USB_DT_OTG:
++ s = "OTG";
++ break;
++ case USB_DT_DEBUG:
++ s = "Debug";
++ break;
++ case USB_DT_INTERFACE_ASSOCIATION:
++ s = "Interface Association";
++ break;
++ case USB_DT_BOS:
++ s = "BOS";
++ break;
++ case USB_DT_DEVICE_CAPABILITY:
++ s = "Device Capability";
++ break;
++ case USB_DT_PIPE_USAGE:
++ s = "Pipe Usage";
++ break;
++ case USB_DT_SS_ENDPOINT_COMP:
++ s = "SS Endpoint Companion";
++ break;
++ case USB_DT_SSP_ISOC_ENDPOINT_COMP:
++ s = "SSP Isochronous Endpoint Companion";
++ break;
++ default:
++ s = "UNKNOWN";
++ break;
++ } s; }), v & 0xff, l);
++}
++
++
++static inline void dwc3_decode_get_configuration(__u16 l, char *str,
++ size_t size)
++{
++ snprintf(str, size, "Get Configuration(Length = %d)", l);
++}
++
++static inline void dwc3_decode_set_configuration(__u8 v, char *str, size_t size)
++{
++ snprintf(str, size, "Set Configuration(Config = %d)", v);
++}
++
++static inline void dwc3_decode_get_intf(__u16 i, __u16 l, char *str,
++ size_t size)
++{
++ snprintf(str, size, "Get Interface(Intf = %d, Length = %d)", i, l);
++}
++
++static inline void dwc3_decode_set_intf(__u8 v, __u16 i, char *str, size_t size)
++{
++ snprintf(str, size, "Set Interface(Intf = %d, Alt.Setting = %d)", i, v);
++}
++
++static inline void dwc3_decode_synch_frame(__u16 i, __u16 l, char *str,
++ size_t size)
++{
++ snprintf(str, size, "Synch Frame(Endpoint = %d, Length = %d)", i, l);
++}
++
++static inline void dwc3_decode_set_sel(__u16 l, char *str, size_t size)
++{
++ snprintf(str, size, "Set SEL(Length = %d)", l);
++}
++
++static inline void dwc3_decode_set_isoch_delay(__u8 v, char *str, size_t size)
++{
++ snprintf(str, size, "Set Isochronous Delay(Delay = %d ns)", v);
++}
++
++/**
++ * dwc3_decode_ctrl - returns a string represetion of ctrl request
++ */
++static inline const char *dwc3_decode_ctrl(char *str, size_t size,
++ __u8 bRequestType, __u8 bRequest, __u16 wValue, __u16 wIndex,
++ __u16 wLength)
++{
++ switch (bRequest) {
++ case USB_REQ_GET_STATUS:
++ dwc3_decode_get_status(bRequestType, wIndex, wLength, str,
++ size);
++ break;
++ case USB_REQ_CLEAR_FEATURE:
++ case USB_REQ_SET_FEATURE:
++ dwc3_decode_set_clear_feature(bRequestType, bRequest, wValue,
++ wIndex, str, size);
++ break;
++ case USB_REQ_SET_ADDRESS:
++ dwc3_decode_set_address(wValue, str, size);
++ break;
++ case USB_REQ_GET_DESCRIPTOR:
++ case USB_REQ_SET_DESCRIPTOR:
++ dwc3_decode_get_set_descriptor(bRequestType, bRequest, wValue,
++ wIndex, wLength, str, size);
++ break;
++ case USB_REQ_GET_CONFIGURATION:
++ dwc3_decode_get_configuration(wLength, str, size);
++ break;
++ case USB_REQ_SET_CONFIGURATION:
++ dwc3_decode_set_configuration(wValue, str, size);
++ break;
++ case USB_REQ_GET_INTERFACE:
++ dwc3_decode_get_intf(wIndex, wLength, str, size);
++ break;
++ case USB_REQ_SET_INTERFACE:
++ dwc3_decode_set_intf(wValue, wIndex, str, size);
++ break;
++ case USB_REQ_SYNCH_FRAME:
++ dwc3_decode_synch_frame(wIndex, wLength, str, size);
++ break;
++ case USB_REQ_SET_SEL:
++ dwc3_decode_set_sel(wLength, str, size);
++ break;
++ case USB_REQ_SET_ISOCH_DELAY:
++ dwc3_decode_set_isoch_delay(wValue, str, size);
++ break;
++ default:
++ snprintf(str, size, "%02x %02x %02x %02x %02x %02x %02x %02x",
++ bRequestType, bRequest,
++ cpu_to_le16(wValue) & 0xff,
++ cpu_to_le16(wValue) >> 8,
++ cpu_to_le16(wIndex) & 0xff,
++ cpu_to_le16(wIndex) >> 8,
++ cpu_to_le16(wLength) & 0xff,
++ cpu_to_le16(wLength) >> 8);
+ }
+
+ return str;
+@@ -183,30 +472,52 @@ dwc3_gadget_event_string(const struct dwc3_event_devt *event)
+ * dwc3_ep_event_string - returns event name
* @event: then event code
*/
- static inline const char *
+-static inline const char *
-dwc3_ep_event_string(const struct dwc3_event_depevt *event)
-+dwc3_ep_event_string(const struct dwc3_event_depevt *event, u32 ep0state)
++static inline const char *dwc3_ep_event_string(char *str, size_t size,
++ const struct dwc3_event_depevt *event, u32 ep0state)
{
u8 epnum = event->endpoint_number;
- static char str[256];
+- static char str[256];
+ size_t len;
int status;
int ret;
-@@ -196,17 +213,34 @@ dwc3_ep_event_string(const struct dwc3_event_depevt *event)
+- ret = sprintf(str, "ep%d%s: ", epnum >> 1,
++ ret = snprintf(str, size, "ep%d%s: ", epnum >> 1,
+ (epnum & 1) ? "in" : "out");
if (ret < 0)
return "UNKNOWN";
@@ -335205,7 +404560,7 @@ index 33ab2a2..cdd644d 100644
case DWC3_DEPEVT_XFERCOMPLETE:
- strcat(str, "Transfer Complete");
+ len = strlen(str);
-+ sprintf(str + len, "Transfer Complete (%c%c%c)",
++ snprintf(str + len, size - len, "Transfer Complete (%c%c%c)",
+ status & DEPEVT_STATUS_SHORT ? 'S' : 's',
+ status & DEPEVT_STATUS_IOC ? 'I' : 'i',
+ status & DEPEVT_STATUS_LST ? 'L' : 'l');
@@ -335213,66 +404568,138 @@ index 33ab2a2..cdd644d 100644
+ len = strlen(str);
+
+ if (epnum <= 1)
-+ sprintf(str + len, " [%s]", dwc3_ep0_state_string(ep0state));
++ snprintf(str + len, size - len, " [%s]",
++ dwc3_ep0_state_string(ep0state));
break;
case DWC3_DEPEVT_XFERINPROGRESS:
- strcat(str, "Transfer In-Progress");
+ len = strlen(str);
+
-+ sprintf(str + len, "Transfer In Progress (%c%c%c)",
++ snprintf(str + len, size - len, "Transfer In Progress [%d] (%c%c%c)",
++ event->parameters,
+ status & DEPEVT_STATUS_SHORT ? 'S' : 's',
+ status & DEPEVT_STATUS_IOC ? 'I' : 'i',
+ status & DEPEVT_STATUS_LST ? 'M' : 'm');
break;
case DWC3_DEPEVT_XFERNOTREADY:
- strcat(str, "Transfer Not Ready");
+- strcat(str, "Transfer Not Ready");
- status = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
- strcat(str, status ? " (Active)" : " (Not Active)");
-+ strcat(str, status & DEPEVT_STATUS_TRANSFER_ACTIVE ?
++ len = strlen(str);
++
++ snprintf(str + len, size - len, "Transfer Not Ready [%d]%s",
++ event->parameters,
++ status & DEPEVT_STATUS_TRANSFER_ACTIVE ?
+ " (Active)" : " (Not Active)");
+
break;
case DWC3_DEPEVT_RXTXFIFOEVT:
strcat(str, "FIFO");
-@@ -270,14 +304,14 @@ static inline const char *dwc3_gadget_event_type_string(u8 event)
+@@ -216,7 +527,7 @@ dwc3_ep_event_string(const struct dwc3_event_depevt *event)
+
+ switch (status) {
+ case DEPEVT_STREAMEVT_FOUND:
+- sprintf(str + ret, " Stream %d Found",
++ snprintf(str + ret, size - ret, " Stream %d Found",
+ event->parameters);
+ break;
+ case DEPEVT_STREAMEVT_NOTFOUND:
+@@ -230,7 +541,7 @@ dwc3_ep_event_string(const struct dwc3_event_depevt *event)
+ strcat(str, "Endpoint Command Complete");
+ break;
+ default:
+- sprintf(str, "UNKNOWN");
++ snprintf(str, size, "UNKNOWN");
+ }
+
+ return str;
+@@ -270,14 +581,15 @@ static inline const char *dwc3_gadget_event_type_string(u8 event)
}
}
-static inline const char *dwc3_decode_event(u32 event)
-+static inline const char *dwc3_decode_event(u32 event, u32 ep0state)
++static inline const char *dwc3_decode_event(char *str, size_t size, u32 event,
++ u32 ep0state)
{
const union dwc3_event evt = (union dwc3_event) event;
if (evt.type.is_devspec)
- return dwc3_gadget_event_string(&evt.devt);
+- return dwc3_gadget_event_string(&evt.devt);
++ return dwc3_gadget_event_string(str, size, &evt.devt);
else
- return dwc3_ep_event_string(&evt.depevt);
-+ return dwc3_ep_event_string(&evt.depevt, ep0state);
++ return dwc3_ep_event_string(str, size, &evt.depevt, ep0state);
}
static inline const char *dwc3_ep_cmd_status_string(int status)
-@@ -310,7 +344,13 @@ static inline const char *dwc3_gadget_generic_cmd_status_string(int status)
+@@ -310,7 +622,6 @@ static inline const char *dwc3_gadget_generic_cmd_status_string(int status)
}
}
-+
-+#if IS_ENABLED(CONFIG_FTRACE)
- void dwc3_trace(void (*trace)(struct va_format *), const char *fmt, ...);
-+#else
-+static inline void dwc3_trace(void (*trace)(struct va_format *), const char *fmt, ...)
-+{ }
-+#endif
+-void dwc3_trace(void (*trace)(struct va_format *), const char *fmt, ...);
#ifdef CONFIG_DEBUG_FS
extern void dwc3_debugfs_init(struct dwc3 *);
+diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
+index 31926dd..c759f35 100644
+--- a/drivers/usb/dwc3/debugfs.c
++++ b/drivers/usb/dwc3/debugfs.c
+@@ -689,30 +689,6 @@ static int dwc3_ep_transfer_type_show(struct seq_file *s, void *unused)
+ return 0;
+ }
+
+-static inline const char *dwc3_trb_type_string(struct dwc3_trb *trb)
+-{
+- switch (DWC3_TRBCTL_TYPE(trb->ctrl)) {
+- case DWC3_TRBCTL_NORMAL:
+- return "normal";
+- case DWC3_TRBCTL_CONTROL_SETUP:
+- return "control-setup";
+- case DWC3_TRBCTL_CONTROL_STATUS2:
+- return "control-status2";
+- case DWC3_TRBCTL_CONTROL_STATUS3:
+- return "control-status3";
+- case DWC3_TRBCTL_CONTROL_DATA:
+- return "control-data";
+- case DWC3_TRBCTL_ISOCHRONOUS_FIRST:
+- return "isoc-first";
+- case DWC3_TRBCTL_ISOCHRONOUS:
+- return "isoc";
+- case DWC3_TRBCTL_LINK_TRB:
+- return "link";
+- default:
+- return "UNKNOWN";
+- }
+-}
+-
+ static int dwc3_ep_trb_ring_show(struct seq_file *s, void *unused)
+ {
+ struct dwc3_ep *dep = s->private;
+@@ -733,10 +709,11 @@ static int dwc3_ep_trb_ring_show(struct seq_file *s, void *unused)
+
+ for (i = 0; i < DWC3_TRB_NUM; i++) {
+ struct dwc3_trb *trb = &dep->trb_pool[i];
++ unsigned int type = DWC3_TRBCTL_TYPE(trb->ctrl);
+
+ seq_printf(s, "%08x%08x,%d,%s,%d,%d,%d,%d,%d,%d\n",
+ trb->bph, trb->bpl, trb->size,
+- dwc3_trb_type_string(trb),
++ dwc3_trb_type_string(type),
+ !!(trb->ctrl & DWC3_TRB_CTRL_IOC),
+ !!(trb->ctrl & DWC3_TRB_CTRL_ISP_IMI),
+ !!(trb->ctrl & DWC3_TRB_CTRL_CSP),
diff --git a/drivers/usb/dwc3/dwc3-hisi.c b/drivers/usb/dwc3/dwc3-hisi.c
new file mode 100644
-index 0000000..e45c81d
+index 0000000..1e3f5b7
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-hisi.c
-@@ -0,0 +1,382 @@
+@@ -0,0 +1,445 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * dwc3-hisi.c
++ *
++ * Dwc3 private driver for Hisilicon.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -335288,6 +404715,7 @@ index 0000000..e45c81d
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
++
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
@@ -335328,15 +404756,18 @@ index 0000000..e45c81d
+#define U2_FREECLK_EXISTS (0x1 << 30)
+#define SOFITPSYNC (0x1 << 10)
+#define REFCLKPER_MASK 0xffc00000
-+#define REFCLKPER_VAL(a) (((a) << 22) & REFCLKPER_MASK)
++#define REFCLKPER_VAL 0x29
++#define set_refclkper(a) (((a) << 22) & REFCLKPER_MASK)
+
+#define PLS1 (0x1 << 31)
+#define DECR_MASK 0x7f000000
-+#define DECR_VAL(a) (((a) << 24) & DECR_MASK)
++#define DECR_VAL 0xa
++#define set_decr(a) (((a) << 24) & DECR_MASK)
+
+#define LPM_SEL (0x1 << 23)
+#define FLADJ_MASK 0x003fff00
-+#define FLADJ_VAL(a) (((a) << 8) & FLADJ_MASK)
++#define FLADJ_VAL 0x7f0
++#define set_fladj(a) (((a) << 8) & FLADJ_MASK)
+
+/* hi3559a */
+#define DOUBLE_PCIE_MODE 0x0
@@ -335347,17 +404778,20 @@ index 0000000..e45c81d
+#define PCIE_X1_MODE (0x0 << 12)
+#define USB3_MODE (0x1 << 12)
+
-+static struct hi_priv *priv;
++static struct hi_priv *usb_priv = NULL;
+
-+#if defined(CONFIG_ARCH_HI3559AV100)
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
+static int speed_adapt_for_hi3559a(struct device_node *np)
+{
+ unsigned int ret;
+ unsigned int reg;
+
-+ priv->speed_id = -1;
++ if (np == NULL)
++ return -EINVAL;
+
-+ reg = readl(priv->sys_ctrl + REG_SYS_STAT);
++ usb_priv->speed_id = -1;
++
++ reg = readl(usb_priv->sys_ctrl + REG_SYS_STAT);
+ reg &= PCIE_USB3_MODE_MASK;
+
+ switch (reg) {
@@ -335365,12 +404799,12 @@ index 0000000..e45c81d
+ ret = USB_SPEED_HIGH;
+ break;
+ case P0_PCIE_ADD_P1_USB3:
-+ if (of_property_read_u32(np, "port_speed", &priv->speed_id))
-+ ret = USB_SPEED_UNKNOWN;
++ if (of_property_read_u32(np, "port_speed", &usb_priv->speed_id))
++ usb_priv->speed_id = -1;
+
-+ if (priv->speed_id == 0)
++ if (usb_priv->speed_id == 0)
+ ret = USB_SPEED_HIGH;
-+ else if (priv->speed_id == 1)
++ else if (usb_priv->speed_id == 1)
+ ret = USB_SPEED_SUPER;
+ else
+ ret = USB_SPEED_UNKNOWN;
@@ -335393,7 +404827,10 @@ index 0000000..e45c81d
+ unsigned int ret;
+ unsigned int reg;
+
-+ reg = readl(priv->sys_ctrl + REG_SYS_STAT);
++ if (dev == NULL)
++ return -EINVAL;
++
++ reg = readl(usb_priv->sys_ctrl + REG_SYS_STAT);
+ reg &= PCIE_USB3_MODE_MASK;
+
+ if (reg == PCIE_X1_MODE)
@@ -335410,38 +404847,48 @@ index 0000000..e45c81d
+ unsigned int ret;
+ struct device_node *np = dev->of_node;
+
-+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
++ if (np == NULL)
++ return -EINVAL;
++
++ usb_priv = kzalloc(sizeof(*usb_priv), GFP_KERNEL);
++ if (usb_priv == NULL)
+ return -ENOMEM;
+
-+ priv->peri_crg = of_iomap(np, 1);
-+ if (IS_ERR(priv->peri_crg)) {
-+ ret = PTR_ERR(priv->peri_crg);
-+ goto err;
++ usb_priv->peri_crg = of_iomap(np, DEV_NODE_FLAG1);
++ if (IS_ERR(usb_priv->peri_crg)) {
++ kfree(usb_priv);
++ usb_priv = NULL;
++ return -ENOMEM;
+ }
+
-+ priv->sys_ctrl = of_iomap(np, 2);
-+ if (IS_ERR(priv->sys_ctrl)) {
-+ ret = PTR_ERR(priv->sys_ctrl);
-+ goto err;
++ usb_priv->sys_ctrl = of_iomap(np, DEV_NODE_FLAG2);
++ if (IS_ERR(usb_priv->sys_ctrl)) {
++ iounmap(usb_priv->peri_crg);
++
++ kfree(usb_priv);
++ usb_priv = NULL;
++ return -ENOMEM;
+ }
+
-+#if defined(CONFIG_ARCH_HI3559AV100)
-+ return speed_adapt_for_hi3559a(np);
++#if defined(CONFIG_ARCH_HI3559AV100) || defined(CONFIG_ARCH_HI3569V100)
++ ret = speed_adapt_for_hi3559a(np);
++#elif defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100)
++ ret = speed_adapt_for_hi3556a(dev);
++#else
++ ret = usb_get_maximum_speed(dev);
+#endif
-+#if defined(CONFIG_ARCH_HI3556AV100) || defined(CONFIG_ARCH_HI3519AV100)
-+ return speed_adapt_for_hi3556a(dev);
-+#endif
-+ return usb_get_maximum_speed(dev);
-+err:
-+ kfree(priv);
-+ return usb_get_maximum_speed(dev);
++
++ iounmap(usb_priv->sys_ctrl);
++ iounmap(usb_priv->peri_crg);
++
++ return ret;
+}
+EXPORT_SYMBOL(usb_get_max_speed);
+
+void hisi_dwc3_exited(void)
+{
-+ kfree(priv);
++ kfree(usb_priv);
++ usb_priv = NULL;
+}
+EXPORT_SYMBOL(hisi_dwc3_exited);
+
@@ -335450,6 +404897,9 @@ index 0000000..e45c81d
+ unsigned int ret;
+ unsigned int reg;
+
++ if ((np == NULL) || (hisi == NULL))
++ return -EINVAL;
++
+ /* get usb ctrl crg para */
+ ret = of_property_read_u32(np, "crg_offset", &hisi->crg_offset);
+ if (ret)
@@ -335476,26 +404926,30 @@ index 0000000..e45c81d
+{
+ struct device *dev = hisi->dev;
+ struct device_node *np = dev->of_node;
-+ int i;
++ int i, ret;
++
++ if (!count)
++ return -EINVAL;
++
++ if (np == NULL)
++ return -EINVAL;
+
+ hisi->num_clocks = count;
-+ if (!count)
-+ return 0;
+
+ hisi->clks = devm_kcalloc(dev, hisi->num_clocks, sizeof(struct clk *), GFP_KERNEL);
-+ if (!hisi->clks)
++ if (hisi->clks == NULL)
+ return -ENOMEM;
+
+ for (i = 0; i < hisi->num_clocks; i++) {
+ struct clk *clk;
-+ int ret;
+
+ clk = of_clk_get(np, i);
+ if (IS_ERR(clk)) {
+ while (--i >= 0)
+ clk_put(hisi->clks[i]);
+
-+ return PTR_ERR(clk);
++ ret = PTR_ERR(clk);
++ goto clk_free;
+ }
+
+ ret = clk_prepare_enable(clk);
@@ -335506,19 +404960,27 @@ index 0000000..e45c81d
+ }
+ clk_put(clk);
+
-+ return ret;
++ goto clk_free;
+ }
+
+ hisi->clks[i] = clk;
+ }
+
+ return 0;
++clk_free:
++ devm_kfree(dev, hisi->clks);
++ hisi->clks = NULL;
++
++ return ret;
+}
+
-+static int control_free_clk_config(struct dwc3_hisi *hisi)
++static void control_free_clk_config(struct dwc3_hisi *hisi)
+{
+ unsigned int reg;
+
++ if (hisi == NULL)
++ return;
++
+ reg = readl(hisi->ctrl_base + GUSB2PHYCFG_OFFSET);
+ reg &= ~U2_FREECLK_EXISTS;
+ writel(reg, hisi->ctrl_base + GUSB2PHYCFG_OFFSET);
@@ -335529,7 +404991,7 @@ index 0000000..e45c81d
+
+ reg = readl(hisi->ctrl_base + GUCTL_OFFSET);
+ reg &= ~REFCLKPER_MASK;
-+ reg |= REFCLKPER_VAL(41);
++ reg |= set_refclkper(REFCLKPER_VAL);
+ writel(reg, hisi->ctrl_base + GUCTL_OFFSET);
+
+ reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
@@ -335538,7 +405000,7 @@ index 0000000..e45c81d
+
+ reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
+ reg &= ~DECR_MASK;
-+ reg |= DECR_VAL(10);
++ reg |= set_decr(DECR_VAL);
+ writel(reg, hisi->ctrl_base + GFLADJ_OFFSET);
+
+ reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
@@ -335547,71 +405009,89 @@ index 0000000..e45c81d
+
+ reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
+ reg &= ~FLADJ_MASK;
-+ reg |= FLADJ_VAL(2032);
++ reg |= set_fladj(FLADJ_VAL);
+ writel(reg, hisi->ctrl_base + GFLADJ_OFFSET);
++}
++
++static int dwc3_hisi_iomap(struct device_node *np, struct dwc3_hisi *hisi)
++{
++ if ((np == NULL) || (hisi == NULL))
++ return -EINVAL;
++
++ hisi->ctrl_base = of_iomap(np, DEV_NODE_FLAG0);
++ if (IS_ERR(hisi->ctrl_base))
++ return -ENOMEM;
++
++ hisi->crg_base = of_iomap(np, DEV_NODE_FLAG1);
++ if (IS_ERR(hisi->crg_base)) {
++ iounmap(hisi->ctrl_base);
++ return -ENOMEM;
++ }
+
+ return 0;
+}
+
+static int dwc3_hisi_probe(struct platform_device *pdev)
+{
-+ struct dwc3_hisi *hisi;
++ struct dwc3_hisi *hisi = NULL;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret, i;
+
+ hisi = devm_kzalloc(dev, sizeof(*hisi), GFP_KERNEL);
-+ if (!hisi)
++ if (hisi == NULL)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, hisi);
-+
+ hisi->dev = dev;
+
++ ret = dwc3_hisi_iomap(np, hisi);
++ if (ret) {
++ devm_kfree(dev, hisi);
++ hisi = NULL;
++
++ return -ENOMEM;
++ }
++
+ hisi->port_rst = devm_reset_control_get(dev, "vcc_reset");
+ if (IS_ERR_OR_NULL(hisi->port_rst)) {
-+ dev_err(dev, "get crg_rst failed.\n");
-+ return PTR_ERR(hisi->port_rst);
++ ret = PTR_ERR(hisi->port_rst);
++ goto hidwc3_unmap;
+ }
+
-+ hisi->ctrl_base = of_iomap(np, 0);
-+ if (!hisi->ctrl_base)
-+ return -ENOMEM;
-+
-+ hisi->crg_base = of_iomap(np, 1);
-+ if (!hisi->crg_base) {
-+ iounmap(hisi->ctrl_base);
-+ return -ENOMEM;
-+ }
-+
-+ set_ctrl_crg_val(np, hisi);
++ ret = set_ctrl_crg_val(np, hisi);
++ if (ret)
++ goto hidwc3_unmap;
+
+ reset_control_assert(hisi->port_rst);
+
+ ret = dwc3_hisi_clk_init(hisi, of_clk_get_parent_count(np));
-+ if (ret) {
-+ goto err_0;
-+ }
++ if (ret)
++ goto hidwc3_unmap;
+
+ reset_control_deassert(hisi->port_rst);
+
+ control_free_clk_config(hisi);
+
-+ udelay(200);
++ udelay(U_LEVEL2);
+
+ ret = of_platform_populate(np, NULL, NULL, dev);
+ if (ret) {
-+ dev_err(dev, "failed to register dwc3 device\n");
+ for (i = 0; i < hisi->num_clocks; i++) {
+ clk_disable_unprepare(hisi->clks[i]);
+ clk_put(hisi->clks[i]);
+ }
-+ goto err_0;
++ goto hidwc3_unmap;
+ }
+
-+err_0:
++ return 0;
++hidwc3_unmap:
+ iounmap(hisi->ctrl_base);
+ iounmap(hisi->crg_base);
++
++ devm_kfree(dev, hisi);
++ hisi = NULL;
++
+ return ret;
+}
+
@@ -335630,6 +405110,12 @@ index 0000000..e45c81d
+
+ of_platform_depopulate(dev);
+
++ iounmap(hisi->ctrl_base);
++ iounmap(hisi->crg_base);
++
++ devm_kfree(dev, hisi);
++ hisi = NULL;
++
+ return 0;
+}
+
@@ -335651,16 +405137,20 @@ index 0000000..e45c81d
+module_platform_driver(dwc3_hisi_driver);
+
+MODULE_LICENSE("GPL v2");
-+MODULE_DESCRIPTION("DesignWare USB3 of HiSi");
-+MODULE_AUTHOR("HiSilicon Technologies Co., Ltd..>");
++MODULE_DESCRIPTION("DesignWare USB3 of Hisilicon");
++MODULE_AUTHOR("Hisilicon Technologies Co., Ltd..>");
diff --git a/drivers/usb/dwc3/dwc3-hisi.h b/drivers/usb/dwc3/dwc3-hisi.h
new file mode 100644
-index 0000000..463f8b4
+index 0000000..606cf05
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-hisi.h
-@@ -0,0 +1,39 @@
+@@ -0,0 +1,54 @@
+/*
-+ * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
++ * dwc3-hisi.h
++ *
++ * Dwc3 private headerfile for Hisilicon.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -335677,6 +405167,9 @@ index 0000000..463f8b4
+ *
+ */
+
++#ifndef USB_INCLUDE_DWC3_HISI_H
++#define USB_INCLUDE_DWC3_HISI_H
++
+struct hi_priv {
+ void __iomem *peri_crg;
+ void __iomem *sys_ctrl;
@@ -335698,8 +405191,16 @@ index 0000000..463f8b4
+
+extern int usb_get_max_speed(struct device *dev);
+extern void hisi_dwc3_exited(void);
++
++#define DEV_NODE_FLAG0 0
++#define DEV_NODE_FLAG1 1
++#define DEV_NODE_FLAG2 2
++
++#define U_LEVEL2 200
++
++#endif
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
-index 2331469..d605058 100644
+index 2331469..cf6252d 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -39,22 +39,6 @@ static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
@@ -335725,7 +405226,18 @@ index 2331469..d605058 100644
static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
dma_addr_t buf_dma, u32 len, u32 type, bool chain)
{
-@@ -102,11 +86,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
+@@ -92,21 +76,16 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
+ int ret;
+
+ dep = dwc->eps[epnum];
+- if (dep->flags & DWC3_EP_BUSY) {
+- dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
++ if (dep->flags & DWC3_EP_BUSY)
+ return 0;
+- }
+
+ memset(¶ms, 0, sizeof(params));
+ params.param0 = upper_32_bits(dwc->ep0_trb_addr);
params.param1 = lower_32_bits(dwc->ep0_trb_addr);
ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
@@ -335738,7 +405250,29 @@ index 2331469..d605058 100644
dep->flags |= DWC3_EP_BUSY;
dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
-@@ -245,11 +226,6 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
+@@ -166,9 +145,6 @@ static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
+
+ if (dwc->ep0state == EP0_STATUS_PHASE)
+ __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
+- else
+- dwc3_trace(trace_dwc3_ep0,
+- "too early for delayed status");
+
+ return 0;
+ }
+@@ -232,9 +208,8 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
+
+ spin_lock_irqsave(&dwc->lock, flags);
+ if (!dep->endpoint.desc) {
+- dwc3_trace(trace_dwc3_ep0,
+- "trying to queue request %p to disabled %s",
+- request, dep->name);
++ dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
++ dep->name);
+ ret = -ESHUTDOWN;
+ goto out;
+ }
+@@ -245,11 +220,6 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
goto out;
}
@@ -335750,7 +405284,7 @@ index 2331469..d605058 100644
ret = __dwc3_gadget_ep0_queue(dep, req);
out:
-@@ -399,126 +375,203 @@ static int dwc3_ep0_handle_status(struct dwc3 *dwc,
+@@ -399,126 +369,203 @@ static int dwc3_ep0_handle_status(struct dwc3 *dwc,
return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
}
@@ -335988,14 +405522,14 @@ index 2331469..d605058 100644
+
+ return 0;
+}
-
++
+static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
+ struct usb_ctrlrequest *ctrl, int set)
+{
+ u32 recip;
+ int ret;
+ enum usb_device_state state;
-+
+
+ recip = ctrl->bRequestType & USB_RECIP_MASK;
+ state = dwc->gadget.state;
+
@@ -336047,7 +405581,23 @@ index 2331469..d605058 100644
}
static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
-@@ -595,7 +648,15 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+@@ -529,13 +576,12 @@ static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+
+ addr = le16_to_cpu(ctrl->wValue);
+ if (addr > 127) {
+- dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
++ dev_err(dwc->dev, "invalid device address %d\n", addr);
+ return -EINVAL;
+ }
+
+ if (state == USB_STATE_CONFIGURED) {
+- dwc3_trace(trace_dwc3_ep0,
+- "trying to set address when configured");
++ dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
+ return -EINVAL;
+ }
+
+@@ -595,7 +641,15 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
* nothing is pending from application.
*/
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
@@ -336064,7 +405614,74 @@ index 2331469..d605058 100644
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
}
break;
-@@ -944,17 +1005,14 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
+@@ -720,35 +774,27 @@ static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_GET_STATUS:
+- dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
+ ret = dwc3_ep0_handle_status(dwc, ctrl);
+ break;
+ case USB_REQ_CLEAR_FEATURE:
+- dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
+ ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
+ break;
+ case USB_REQ_SET_FEATURE:
+- dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
+ ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
+ break;
+ case USB_REQ_SET_ADDRESS:
+- dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
+ ret = dwc3_ep0_set_address(dwc, ctrl);
+ break;
+ case USB_REQ_SET_CONFIGURATION:
+- dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
+ ret = dwc3_ep0_set_config(dwc, ctrl);
+ break;
+ case USB_REQ_SET_SEL:
+- dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
+ ret = dwc3_ep0_set_sel(dwc, ctrl);
+ break;
+ case USB_REQ_SET_ISOCH_DELAY:
+- dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
+ ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
+ break;
+ default:
+- dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
+ ret = dwc3_ep0_delegate_req(dwc, ctrl);
+ break;
+ }
+@@ -824,9 +870,6 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
+ status = DWC3_TRB_SIZE_TRBSTS(trb->size);
+ if (status == DWC3_TRBSTS_SETUP_PENDING) {
+ dwc->setup_packet_pending = true;
+-
+- dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
+-
+ if (r)
+ dwc3_gadget_giveback(ep0, r, -ECONNRESET);
+
+@@ -916,7 +959,7 @@ static void dwc3_ep0_complete_status(struct dwc3 *dwc,
+
+ ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
+ if (ret < 0) {
+- dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
++ dev_err(dwc->dev, "invalid test #%d\n",
+ dwc->test_mode_nr);
+ dwc3_ep0_stall_and_restart(dwc);
+ return;
+@@ -924,10 +967,8 @@ static void dwc3_ep0_complete_status(struct dwc3 *dwc,
+ }
+
+ status = DWC3_TRB_SIZE_TRBSTS(trb->size);
+- if (status == DWC3_TRBSTS_SETUP_PENDING) {
++ if (status == DWC3_TRBSTS_SETUP_PENDING)
+ dwc->setup_packet_pending = true;
+- dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
+- }
+
+ dwc->ep0state = EP0_SETUP_PHASE;
+ dwc3_ep0_out_start(dwc);
+@@ -944,17 +985,14 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
switch (dwc->ep0state) {
case EP0_SETUP_PHASE:
@@ -336082,7 +405699,31 @@ index 2331469..d605058 100644
dwc3_ep0_complete_status(dwc, event);
break;
default:
-@@ -1073,8 +1131,6 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
+@@ -981,10 +1019,8 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
+
+ ret = usb_gadget_map_request(&dwc->gadget, &req->request,
+ dep->number);
+- if (ret) {
+- dwc3_trace(trace_dwc3_ep0, "failed to map request");
++ if (ret)
+ return;
+- }
+
+ maxpacket = dep->endpoint.maxpacket;
+
+@@ -1010,10 +1046,8 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
+ } else {
+ ret = usb_gadget_map_request(&dwc->gadget, &req->request,
+ dep->number);
+- if (ret) {
+- dwc3_trace(trace_dwc3_ep0, "failed to map request");
++ if (ret)
+ return;
+- }
+
+ dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma,
+ req->request.length, DWC3_TRBCTL_CONTROL_DATA,
+@@ -1073,8 +1107,6 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
{
switch (event->status) {
case DEPEVT_STATUS_CONTROL_DATA:
@@ -336091,7 +405732,17 @@ index 2331469..d605058 100644
/*
* We already have a DATA transfer in the controller's cache,
* if we receive a XferNotReady(DATA) we will ignore it, unless
-@@ -1100,8 +1156,6 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
+@@ -1087,8 +1119,7 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
+ if (dwc->ep0_expect_in != event->endpoint_number) {
+ struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
+
+- dwc3_trace(trace_dwc3_ep0,
+- "Wrong direction for Data phase");
++ dev_err(dwc->dev, "unexpected direction for Data Phase\n");
+ dwc3_ep0_end_control_data(dwc, dep);
+ dwc3_ep0_stall_and_restart(dwc);
+ return;
+@@ -1100,13 +1131,10 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
return;
@@ -336100,7 +405751,12 @@ index 2331469..d605058 100644
dwc->ep0state = EP0_STATUS_PHASE;
if (dwc->delayed_status) {
-@@ -1117,10 +1171,6 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
+ WARN_ON_ONCE(event->endpoint_number != 1);
+- dwc3_trace(trace_dwc3_ep0, "Delayed Status");
+ return;
+ }
+
+@@ -1117,10 +1145,6 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
void dwc3_ep0_interrupt(struct dwc3 *dwc,
const struct dwc3_event_depevt *event)
{
@@ -336112,10 +405768,10 @@ index 2331469..d605058 100644
case DWC3_DEPEVT_XFERCOMPLETE:
dwc3_ep0_xfer_complete(dwc, event);
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
-index f92c680..f9ced54 100644
+index f92c680..0b6a901 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
-@@ -35,6 +35,14 @@
+@@ -35,6 +35,15 @@
#include "gadget.h"
#include "io.h"
@@ -336123,6 +405779,7 @@ index f92c680..f9ced54 100644
+static int __dwc3_gadget_get_frame(struct dwc3 *dwc);
+static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
+ const struct dwc3_event_depevt *event);
++static bool __dwc3_gadget_target_frame_elapsed(struct dwc3_ep *dep);
+
+#define DWC3_ALIGN_FRAME(d) (((d)->frame_number + (d)->interval) \
+ & ~((d)->interval - 1))
@@ -336130,7 +405787,26 @@ index f92c680..f9ced54 100644
/**
* dwc3_gadget_set_test_mode - Enables USB2 Test Modes
* @dwc: pointer to our context structure
-@@ -247,7 +255,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
+@@ -139,9 +148,6 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
+ udelay(5);
+ }
+
+- dwc3_trace(trace_dwc3_gadget,
+- "link state change request timed out");
+-
+ return -ETIMEDOUT;
+ }
+
+@@ -153,7 +159,7 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
+ * if it is point to the link TRB, wrap around to the beginning. The
+ * link TRB is always at the last TRB entry.
+ */
+-static void dwc3_ep_inc_trb(u8 *index)
++static void dwc3_ep_inc_trb(u32 *index)
+ {
+ (*index)++;
+ if (*index == (DWC3_TRB_NUM - 1))
+@@ -247,7 +253,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
struct dwc3_gadget_ep_cmd_params *params)
{
struct dwc3 *dwc = dep->dwc;
@@ -336139,7 +405815,32 @@ index f92c680..f9ced54 100644
u32 reg;
int cmd_status = 0;
-@@ -611,12 +619,12 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
+@@ -563,8 +569,6 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
+ u32 reg;
+ int ret;
+
+- dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
+-
+ if (!(dep->flags & DWC3_EP_ENABLED)) {
+ ret = dwc3_gadget_start_config(dwc, dep);
+ if (ret)
+@@ -590,7 +594,7 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
+ dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
+
+ if (usb_endpoint_xfer_control(desc))
+- return 0;
++ goto out;
+
+ /* Initialize the TRB ring */
+ dep->trb_dequeue = 0;
+@@ -608,15 +612,19 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
+ trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
+ }
+
++
++out:
++ trace_dwc3_gadget_ep_enable(dep);
++
return 0;
}
@@ -336154,18 +405855,28 @@ index f92c680..f9ced54 100644
/* - giveback all requests to gadget driver */
while (!list_empty(&dep->started_list)) {
-@@ -788,10 +796,6 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
+@@ -645,7 +653,7 @@ static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
+ struct dwc3 *dwc = dep->dwc;
+ u32 reg;
+
+- dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
++ trace_dwc3_gadget_ep_disable(dep);
+
+ dwc3_remove_requests(dwc, dep);
+
+@@ -787,10 +795,7 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
+ struct dwc3 *dwc = dep->dwc;
struct usb_gadget *gadget = &dwc->gadget;
enum usb_device_speed speed = gadget->speed;
-
+-
- dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s",
- dep->name, req, (unsigned long long) dma,
- length, chain ? " chain" : "");
--
++ unsigned int chain_skip = 0;
+
trb = &dep->trb_pool[dep->trb_enqueue];
- if (!req->trb) {
-@@ -816,10 +820,41 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
+@@ -816,12 +821,55 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
case USB_ENDPOINT_XFER_ISOC:
if (!node) {
trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
@@ -336206,10 +405917,84 @@ index f92c680..f9ced54 100644
+ mult--;
+
+ trb->size |= DWC3_TRB_SIZE_PCM1(mult);
++
++ /*
++ * If there are three transactions per mframe,
++ * and each transcation length = 1024B, no any
++ * chain trb needed, so skip it.
++ */
++ if (length == (3 * maxp))
++ chain_skip = 1;
}
++
++ if (speed == USB_SPEED_SUPER)
++ chain_skip = 1;
} else {
++ chain_skip = 1;
trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
-@@ -994,11 +1029,13 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
+ }
+
+@@ -848,7 +896,7 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
+ (dwc3_calc_trbs_left(dep) == 0))
+ trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
+
+- if (chain)
++ if ((!chain_skip) && chain)
+ trb->ctrl |= DWC3_TRB_CTRL_CHN;
+
+ if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
+@@ -868,9 +916,9 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
+ * index is 0, we will wrap backwards, skip the link TRB, and return
+ * the one just before that.
+ */
+-static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
++static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u32 index)
+ {
+- u8 tmp = index;
++ u32 tmp = index;
+
+ if (!tmp)
+ tmp = DWC3_TRB_NUM - 1;
+@@ -881,7 +929,7 @@ static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
+ static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
+ {
+ struct dwc3_trb *tmp;
+- u8 trbs_left;
++ u32 trbs_left;
+
+ /*
+ * If enqueue & dequeue are equal than it is either full or empty.
+@@ -910,11 +958,13 @@ static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
+ static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
+ struct dwc3_request *req)
+ {
++ struct dwc3 *dwc = dep->dwc;
++ struct usb_gadget *gadget = &dwc->gadget;
++ enum usb_device_speed speed = gadget->speed;
+ struct scatterlist *sg = req->sg;
+ struct scatterlist *s;
+- unsigned int length;
++ unsigned int length, i;
+ dma_addr_t dma;
+- int i;
+
+ for_each_sg(sg, s, req->num_pending_sgs, i) {
+ unsigned chain = true;
+@@ -925,8 +975,11 @@ static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
+ if (sg_is_last(s))
+ chain = false;
+
+- dwc3_prepare_one_trb(dep, req, dma, length,
+- chain, i);
++ if ((speed == USB_SPEED_HIGH) &&
++ usb_endpoint_xfer_isoc(dep->endpoint.desc))
++ dwc3_prepare_one_trb(dep, req, dma, length, chain, 0);
++ else
++ dwc3_prepare_one_trb(dep, req, dma, length, chain, i);
+
+ if (!dwc3_calc_trbs_left(dep))
+ break;
+@@ -994,11 +1047,22 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
memset(¶ms, 0, sizeof(params));
@@ -336217,14 +406002,25 @@ index f92c680..f9ced54 100644
+ if (starting && !(dep->flags&DWC3_EP_UPDATE)) {
params.param0 = upper_32_bits(req->trb_dma);
params.param1 = lower_32_bits(req->trb_dma);
- cmd = DWC3_DEPCMD_STARTTRANSFER |
- DWC3_DEPCMD_PARAM(cmd_param);
+- cmd = DWC3_DEPCMD_STARTTRANSFER |
+- DWC3_DEPCMD_PARAM(cmd_param);
++
++ if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
++ while (__dwc3_gadget_target_frame_elapsed(dep))
++ dep->frame_number = DWC3_ALIGN_FRAME(dep);
++
++ dep->frame_number = DWC3_ALIGN_FRAME(dep);
++ cmd_param = dep->frame_number;
++ }
++
++ cmd = DWC3_DEPCMD_STARTTRANSFER | DWC3_DEPCMD_PARAM(cmd_param);
++
+ if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ dep->flags |= DWC3_EP_UPDATE;
} else {
cmd = DWC3_DEPCMD_UPDATETRANSFER |
DWC3_DEPCMD_PARAM(dep->resource_index);
-@@ -1027,11 +1064,19 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
+@@ -1027,34 +1091,36 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
return 0;
}
@@ -336238,17 +406034,18 @@ index f92c680..f9ced54 100644
+
+ if (eframe == cframe)
+ return true;
-+
+
+ return (((eframe - cframe) & DWC3_EVENT_PRAM_SOFFN_MASK)
+ > DWC3_EVENT_PRAM_MAX_SOFFN / 2);
+}
-
++
+static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
+{
if (list_empty(&dep->pending_list)) {
- dwc3_trace(trace_dwc3_gadget,
- "ISOC ep %s run out for requests",
-@@ -1040,21 +1085,18 @@ static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
+- dwc3_trace(trace_dwc3_gadget,
+- "ISOC ep %s run out for requests",
+- dep->name);
+ dep->flags |= DWC3_EP_PENDING_REQUEST;
return;
}
@@ -336278,7 +406075,28 @@ index f92c680..f9ced54 100644
}
static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
-@@ -1106,7 +1148,7 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
+@@ -1063,16 +1129,15 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
+ int ret;
+
+ if (!dep->endpoint.desc) {
+- dwc3_trace(trace_dwc3_gadget,
+- "trying to queue request %p to disabled %s",
+- &req->request, dep->endpoint.name);
++ dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
++ dep->name);
+ return -ESHUTDOWN;
+ }
+
+ if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
+ &req->request, req->dep->name)) {
+- dwc3_trace(trace_dwc3_gadget, "request %pK belongs to '%s'",
+- &req->request, req->dep->name);
++ dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
++ dep->name, &req->request, req->dep->name);
+ return -EINVAL;
+ }
+
+@@ -1106,7 +1171,7 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
if ((dep->flags & DWC3_EP_PENDING_REQUEST) &&
list_empty(&dep->started_list)) {
@@ -336287,7 +406105,26 @@ index f92c680..f9ced54 100644
dep->flags = DWC3_EP_ENABLED;
}
return 0;
-@@ -1197,6 +1239,10 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
+@@ -1116,10 +1181,6 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
+ return 0;
+
+ ret = __dwc3_gadget_kick_transfer(dep, 0);
+- if (ret && ret != -EBUSY)
+- dwc3_trace(trace_dwc3_gadget,
+- "%s: failed to kick transfers",
+- dep->name);
+ if (ret == -EBUSY)
+ ret = 0;
+
+@@ -1138,7 +1199,6 @@ static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
+ struct usb_request *request;
+ struct usb_ep *ep = &dep->endpoint;
+
+- dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
+ request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
+ if (!request)
+ return -ENOMEM;
+@@ -1197,6 +1257,10 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
spin_lock_irqsave(&dwc->lock, flags);
@@ -336298,7 +406135,7 @@ index f92c680..f9ced54 100644
list_for_each_entry(r, &dep->pending_list, list) {
if (r == req)
break;
-@@ -1209,7 +1255,7 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
+@@ -1209,7 +1273,7 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
}
if (r == req) {
/* wait until it is processed */
@@ -336307,7 +406144,36 @@ index f92c680..f9ced54 100644
goto out1;
}
dev_err(dwc->dev, "request %pK was not queued to %s\n",
-@@ -1355,15 +1401,21 @@ static const struct usb_ep_ops dwc3_gadget_ep_ops = {
+@@ -1247,9 +1311,6 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
+ unsigned transfer_in_flight;
+ unsigned started;
+
+- if (dep->flags & DWC3_EP_STALL)
+- return 0;
+-
+ if (dep->number > 1)
+ trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
+ else
+@@ -1260,9 +1321,6 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
+
+ if (!protocol && ((dep->direction && transfer_in_flight) ||
+ (!dep->direction && started))) {
+- dwc3_trace(trace_dwc3_gadget,
+- "%s: pending request, cannot halt",
+- dep->name);
+ return -EAGAIN;
+ }
+
+@@ -1274,8 +1332,6 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
+ else
+ dep->flags |= DWC3_EP_STALL;
+ } else {
+- if (!(dep->flags & DWC3_EP_STALL))
+- return 0;
+
+ ret = dwc3_send_clear_stall_ep_cmd(dep);
+ if (ret)
+@@ -1355,15 +1411,21 @@ static const struct usb_ep_ops dwc3_gadget_ep_ops = {
/* -------------------------------------------------------------------------- */
@@ -336331,6 +406197,40 @@ index f92c680..f9ced54 100644
static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
{
int retries;
+@@ -1384,10 +1446,8 @@ static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
+
+ speed = reg & DWC3_DSTS_CONNECTSPD;
+ if ((speed == DWC3_DSTS_SUPERSPEED) ||
+- (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
+- dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
++ (speed == DWC3_DSTS_SUPERSPEED_PLUS))
+ return 0;
+- }
+
+ link_state = DWC3_DSTS_USBLNKST(reg);
+
+@@ -1396,9 +1456,6 @@ static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
+ case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
+ break;
+ default:
+- dwc3_trace(trace_dwc3_gadget,
+- "can't wakeup from '%s'",
+- dwc3_gadget_link_string(link_state));
+ return -EINVAL;
+ }
+
+@@ -1503,11 +1560,6 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
+ if (!timeout)
+ return -ETIMEDOUT;
+
+- dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
+- dwc->gadget_driver
+- ? dwc->gadget_driver->function : "no-function",
+- is_on ? "connect" : "disconnect");
+-
+ return 0;
+ }
+
@@ -1677,6 +1729,7 @@ static int __dwc3_gadget_start(struct dwc3 *dwc)
/* begin to receive SETUP packets */
@@ -336339,7 +406239,7 @@ index f92c680..f9ced54 100644
dwc3_ep0_out_start(dwc);
dwc3_gadget_enable_irq(dwc);
-@@ -1767,6 +1820,83 @@ static const struct usb_gadget_ops dwc3_gadget_ops = {
+@@ -1767,6 +1820,81 @@ static const struct usb_gadget_ops dwc3_gadget_ops = {
.udc_stop = dwc3_gadget_stop,
};
@@ -336379,8 +406279,6 @@ index f92c680..f9ced54 100644
+ dep->endpoint.name = dep->name;
+ spin_lock_init(&dep->lock);
+
-+ dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
-+
+ if (epnum == 0 || epnum == 1) {
+ usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
+ dep->endpoint.maxburst = 1;
@@ -336423,15 +406321,23 @@ index f92c680..f9ced54 100644
/* -------------------------------------------------------------------------- */
static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
-@@ -1840,6 +1970,16 @@ static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
+@@ -1794,8 +1922,6 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
+ dep->endpoint.name = dep->name;
+ spin_lock_init(&dep->lock);
+
+- dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
+-
+ if (epnum == 0 || epnum == 1) {
+ usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
+ dep->endpoint.maxburst = 1;
+@@ -1840,17 +1966,24 @@ static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
INIT_LIST_HEAD(&dwc->gadget.ep_list);
+ if (dwc->eps_new_init) {
+ ret = dwc3_gadget_init_hw_all_endpoints(dwc);
+ if (ret < 0) {
-+ dwc3_trace(trace_dwc3_gadget,
-+ "failed to allocate all endpioints");
++ dev_err(dwc->dev, "failed to initialize OUT endpoints\n");
+ return ret;
+ }
+ return 0;
@@ -336439,8 +406345,21 @@ index f92c680..f9ced54 100644
+
ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
if (ret < 0) {
- dwc3_trace(trace_dwc3_gadget,
-@@ -1886,10 +2026,9 @@ static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
+- dwc3_trace(trace_dwc3_gadget,
+- "failed to allocate OUT endpoints");
++ dev_err(dwc->dev, "failed to initialize OUT endpoints\n");
+ return ret;
+ }
+
+ ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
+ if (ret < 0) {
+- dwc3_trace(trace_dwc3_gadget,
+- "failed to allocate IN endpoints");
++ dev_err(dwc->dev, "failed to initialize IN endpoints\n");
+ return ret;
+ }
+
+@@ -1886,14 +2019,12 @@ static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
/* -------------------------------------------------------------------------- */
@@ -336454,16 +406373,49 @@ index f92c680..f9ced54 100644
{
unsigned int count;
unsigned int s_pkt = 0;
-@@ -1945,7 +2084,7 @@ static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
- */
- dep->flags |= DWC3_EP_MISSED_ISOC;
- } else {
+- unsigned int trb_status;
+
+ dwc3_ep_inc_deq(dep);
+
+@@ -1922,37 +2053,6 @@ static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
+ req->request.actual += count;
+
+ if (dep->direction) {
+- if (count) {
+- trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
+- if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
+- dwc3_trace(trace_dwc3_gadget,
+- "%s: incomplete IN transfer",
+- dep->name);
+- /*
+- * If missed isoc occurred and there is
+- * no request queued then issue END
+- * TRANSFER, so that core generates
+- * next xfernotready and we will issue
+- * a fresh START TRANSFER.
+- * If there are still queued request
+- * then wait, do not issue either END
+- * or UPDATE TRANSFER, just attach next
+- * request in pending_list during
+- * giveback.If any future queued request
+- * is successfully transferred then we
+- * will issue UPDATE TRANSFER for all
+- * request in the pending_list.
+- */
+- dep->flags |= DWC3_EP_MISSED_ISOC;
+- } else {
- dev_err(dwc->dev, "incomplete IN transfer %s\n",
-+ dev_err(dep->dwc->dev, "incomplete IN transfer %s\n",
- dep->name);
- status = -ECONNRESET;
- }
-@@ -1967,7 +2106,7 @@ static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
+- dep->name);
+- status = -ECONNRESET;
+- }
+- } else {
+- dep->flags &= ~DWC3_EP_MISSED_ISOC;
+- }
+- } else {
+ if (count && (event->status & DEPEVT_STATUS_SHORT))
+ s_pkt = 1;
+ }
+@@ -1967,7 +2067,7 @@ static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
return 0;
}
@@ -336472,7 +406424,7 @@ index f92c680..f9ced54 100644
const struct dwc3_event_depevt *event, int status)
{
struct dwc3_request *req, *n;
-@@ -1994,14 +2133,14 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
+@@ -1994,14 +2094,14 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
req->sg = sg_next(s);
req->num_pending_sgs--;
@@ -336489,7 +406441,7 @@ index f92c680..f9ced54 100644
event, status, chain);
}
-@@ -2045,9 +2184,9 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
+@@ -2045,9 +2145,9 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
* flag, so that END TRANSFER is issued when an
* entry is added into request list.
*/
@@ -336501,7 +406453,7 @@ index f92c680..f9ced54 100644
dep->flags = DWC3_EP_ENABLED;
}
return 1;
-@@ -2059,19 +2198,28 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
+@@ -2059,19 +2159,28 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
return 1;
}
@@ -336533,7 +406485,7 @@ index f92c680..f9ced54 100644
if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
usb_endpoint_xfer_isoc(dep->endpoint.desc)))
dep->flags &= ~DWC3_EP_BUSY;
-@@ -2109,12 +2257,16 @@ static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
+@@ -2109,12 +2218,16 @@ static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
if (!dep->endpoint.desc)
return;
@@ -336555,7 +406507,7 @@ index f92c680..f9ced54 100644
}
}
-@@ -2139,37 +2291,24 @@ static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
+@@ -2139,37 +2252,24 @@ static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
dep->resource_index = 0;
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
@@ -336597,7 +406549,7 @@ index f92c680..f9ced54 100644
}
break;
-@@ -2179,26 +2318,9 @@ static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
+@@ -2179,26 +2279,9 @@ static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
dep->name);
return;
}
@@ -336624,7 +406576,7 @@ index f92c680..f9ced54 100644
break;
}
}
-@@ -2242,15 +2364,13 @@ static void dwc3_reset_gadget(struct dwc3 *dwc)
+@@ -2242,15 +2325,13 @@ static void dwc3_reset_gadget(struct dwc3 *dwc)
}
}
@@ -336642,7 +406594,29 @@ index f92c680..f9ced54 100644
if (!dep->resource_index)
return;
-@@ -2746,26 +2866,21 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc,
+@@ -2596,8 +2677,6 @@ static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
+ (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
+ if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
+ (next == DWC3_LINK_STATE_RESUME)) {
+- dwc3_trace(trace_dwc3_gadget,
+- "ignoring transition U3 -> Resume");
+ return;
+ }
+ }
+@@ -2731,11 +2810,7 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc,
+ break;
+ case DWC3_DEVICE_EVENT_EOPF:
+ /* It changed to be suspend event for version 2.30a and above */
+- if (dwc->revision < DWC3_REVISION_230A) {
+- dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
+- } else {
+- dwc3_trace(trace_dwc3_gadget, "U3/L1-L2 Suspend Event");
+-
++ if (dwc->revision >= DWC3_REVISION_230A) {
+ /*
+ * Ignore suspend event until the gadget enters into
+ * USB_STATE_CONFIGURED state.
+@@ -2746,26 +2821,21 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc,
}
break;
case DWC3_DEVICE_EVENT_SOF:
@@ -336672,7 +406646,17 @@ index f92c680..f9ced54 100644
/* Endpoint IRQ, handle it and return early */
if (event->type.is_devspec == 0) {
-@@ -3005,6 +3120,8 @@ int dwc3_gadget_init(struct dwc3 *dwc)
+@@ -2984,8 +3054,7 @@ int dwc3_gadget_init(struct dwc3 *dwc)
+ * composite.c that we are USB 2.0 + LPM ECN.
+ */
+ if (dwc->revision < DWC3_REVISION_220A)
+- dwc3_trace(trace_dwc3_gadget,
+- "Changing max_speed on rev %08x",
++ dev_info(dwc->dev, "changing max_speed on rev %08x\n",
+ dwc->revision);
+
+ dwc->gadget.max_speed = dwc->maximum_speed;
+@@ -3005,6 +3074,8 @@ int dwc3_gadget_init(struct dwc3 *dwc)
if (ret)
goto err5;
@@ -336681,7 +406665,7 @@ index f92c680..f9ced54 100644
ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
if (ret) {
dev_err(dwc->dev, "failed to register udc\n");
-@@ -3042,6 +3159,8 @@ void dwc3_gadget_exit(struct dwc3 *dwc)
+@@ -3042,6 +3113,8 @@ void dwc3_gadget_exit(struct dwc3 *dwc)
{
usb_del_gadget_udc(&dwc->gadget);
@@ -336690,7 +406674,7 @@ index f92c680..f9ced54 100644
dwc3_gadget_free_endpoints(dwc);
dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
-@@ -3106,3 +3225,73 @@ void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
+@@ -3106,3 +3179,70 @@ void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
enable_irq(dwc->irq_gadget);
}
}
@@ -336737,7 +406721,6 @@ index f92c680..f9ced54 100644
+ */
+ if (dwc->connected == true) {
+ if (prev != UDC_CONNECT_HOST)
-+ dwc3_trace(trace_dwc3_gadget, "csts: Connect Host");
+ dwc->udc_connect_status = UDC_CONNECT_HOST;
+ goto out;
+ }
@@ -336748,7 +406731,6 @@ index f92c680..f9ced54 100644
+ */
+ if ((speed == DWC3_DSTS_FULLSPEED) && (state != DWC3_LINK_STATE_SS_DIS)) {
+ if (prev != UDC_CONNECT_CHARGER)
-+ dwc3_trace(trace_dwc3_gadget, "csts: Connect Charger");
+ dwc->udc_connect_status = UDC_CONNECT_CHARGER;
+ goto out;
+ }
@@ -336758,7 +406740,6 @@ index f92c680..f9ced54 100644
+ * disconnectd.
+ */
+ if (prev != UDC_DISCONNECTED)
-+ dwc3_trace(trace_dwc3_gadget, "csts: Disconnect");
+ dwc->udc_connect_status = UDC_DISCONNECTED;
+
+out:
@@ -336813,27 +406794,32 @@ index a06f9a8..c69b066 100644
#endif /* __DRIVERS_USB_DWC3_IO_H */
diff --git a/drivers/usb/dwc3/proc.c b/drivers/usb/dwc3/proc.c
new file mode 100644
-index 0000000..1225601
+index 0000000..91ccb2c
--- /dev/null
+++ b/drivers/usb/dwc3/proc.c
-@@ -0,0 +1,125 @@
+@@ -0,0 +1,138 @@
+/*
-+* Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
-+*
-+* This program is free software; you can redistribute it and/or modify it
-+* under the terms of the GNU General Public License as published by the
-+* Free Software Foundation; either version 2 of the License, or (at your
-+* option) any later version.
-+*
-+* This program is distributed in the hope that it will be useful,
-+* but WITHOUT ANY WARRANTY; without even the implied warranty of
-+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+* GNU General Public License for more details.
-+*
-+* You should have received a copy of the GNU General Public License
-+* along with this program. If not, see <http://www.gnu.org/licenses/>.
-+*
-+*/
++ * proc.c
++ *
++ * Dwc3 private driver for Hisilicon.
++ *
++ * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/device.h>
@@ -336852,31 +406838,35 @@ index 0000000..1225601
+{
+ struct dwc3 *dwc = s->private;
+
-+ switch(dwc->udc_connect_status) {
-+ case UDC_CONNECT_HOST:
-+ seq_puts(s, "cnt2host\n");
-+ break;
-+
-+ case UDC_CONNECT_CHARGER:
-+ seq_puts(s, "cnt2charger\n");
-+ break;
-+
-+ default:
-+ seq_puts(s, "disconnected\n");
-+ break;
++ switch (dwc->udc_connect_status) {
++ case UDC_CONNECT_HOST:
++ seq_puts(s, "cnt2host\n");
++ break;
++ case UDC_CONNECT_CHARGER:
++ seq_puts(s, "cnt2charger\n");
++ break;
++ default:
++ seq_puts(s, "disconnected\n");
++ break;
+ }
+}
+
+/* define parameters where showed in proc file */
+static int dwc3_stats_seq_show(struct seq_file *s, void *v)
+{
++ if (s == NULL)
++ return -EINVAL;
++
+ dwc3_stats_seq_printout(s);
+ return 0;
+}
+
-+/* proc file open*/
++/* proc file open */
+static int dwc3_stats_proc_open(struct inode *inode, struct file *file)
+{
++ if ((inode == NULL) || (file == NULL))
++ return -EINVAL;
++
+ return single_open(file, dwc3_stats_seq_show, PDE_DATA(inode));
+};
+
@@ -336890,11 +406880,14 @@ index 0000000..1225601
+
+int dwc3_proc_init(struct dwc3 *dwc)
+{
-+ struct proc_dir_entry *proc_entry;
++ struct proc_dir_entry *proc_entry = NULL;
++
++ if (dwc == NULL)
++ return -EINVAL;
+
+ if (proc_dwc3_dir == NULL) {
+ proc_entry = proc_mkdir(DWC3_PROC_ROOT, NULL);
-+ if (!proc_entry) {
++ if (proc_entry == NULL) {
+ pr_err("%s: failed to create proc file %s\n",
+ __func__, DWC3_PROC_ROOT);
+ return 1;
@@ -336904,7 +406897,7 @@ index 0000000..1225601
+ proc_dwc3_dir_cnt++;
+
+ proc_entry = proc_mkdir(to_platform_device(dwc->dev)->name, proc_dwc3_dir);
-+ if (!proc_entry) {
++ if (proc_entry == NULL) {
+ pr_err("%s: failed to create proc file %s\n",
+ __func__, to_platform_device(dwc->dev)->name);
+ return -1;
@@ -336913,7 +406906,7 @@ index 0000000..1225601
+
+ proc_entry = proc_create_data(DWC3_PROC_CONNECTED_STATUS,
+ 0, dwc->parent_entry, &dwc3_stats_proc_ops, dwc);
-+ if (!proc_entry) {
++ if (proc_entry == NULL) {
+ pr_err("%s: failed to create proc file %s\n",
+ __func__, DWC3_PROC_CONNECTED_STATUS);
+ return -1;
@@ -336928,49 +406921,33 @@ index 0000000..1225601
+
+int dwc3_proc_shutdown(struct dwc3 *dwc)
+{
-+ if (proc_dwc3_dir) {
++ if (proc_dwc3_dir != NULL) {
+ remove_proc_entry(DWC3_PROC_CONNECTED_STATUS, dwc->parent_entry);
+ remove_proc_entry(to_platform_device(dwc->dev)->name, proc_dwc3_dir);
-+ remove_proc_entry(DWC3_PROC_ROOT, NULL);
+ }
+
+ if (proc_dwc3_dir_cnt)
+ proc_dwc3_dir_cnt--;
+
-+ if (proc_dwc3_dir_cnt == 0)
++ if (proc_dwc3_dir_cnt == 0) {
++ remove_proc_entry(DWC3_PROC_ROOT, NULL);
+ proc_dwc3_dir = NULL;
++ }
+
+ return 0;
+}
diff --git a/drivers/usb/dwc3/trace.h b/drivers/usb/dwc3/trace.h
-index d24cefd..b2153f2 100644
+index d24cefd..fcdf229 100644
--- a/drivers/usb/dwc3/trace.h
+++ b/drivers/usb/dwc3/trace.h
-@@ -37,47 +37,66 @@ DECLARE_EVENT_CLASS(dwc3_log_msg,
- TP_printk("%s", __get_str(msg))
- );
+@@ -27,57 +27,53 @@
+ #include "core.h"
+ #include "debug.h"
--DEFINE_EVENT(dwc3_log_msg, dwc3_readl,
-+DEFINE_EVENT(dwc3_log_msg, dwc3_gadget,
- TP_PROTO(struct va_format *vaf),
- TP_ARGS(vaf)
- );
-
--DEFINE_EVENT(dwc3_log_msg, dwc3_writel,
-+DEFINE_EVENT(dwc3_log_msg, dwc3_core,
- TP_PROTO(struct va_format *vaf),
- TP_ARGS(vaf)
- );
-
--DEFINE_EVENT(dwc3_log_msg, dwc3_gadget,
-+DEFINE_EVENT(dwc3_log_msg, dwc3_ep0,
- TP_PROTO(struct va_format *vaf),
- TP_ARGS(vaf)
- );
-
--DEFINE_EVENT(dwc3_log_msg, dwc3_core,
+-DECLARE_EVENT_CLASS(dwc3_log_msg,
- TP_PROTO(struct va_format *vaf),
-- TP_ARGS(vaf)
+- TP_ARGS(vaf),
+- TP_STRUCT__entry(__dynamic_array(char, msg, DWC3_MSG_MAX)),
+DECLARE_EVENT_CLASS(dwc3_log_io,
+ TP_PROTO(void *base, u32 offset, u32 value),
+ TP_ARGS(base, offset, value),
@@ -336979,23 +406956,43 @@ index d24cefd..b2153f2 100644
+ __field(u32, offset)
+ __field(u32, value)
+ ),
-+ TP_fast_assign(
+ TP_fast_assign(
+- vsnprintf(__get_str(msg), DWC3_MSG_MAX, vaf->fmt, *vaf->va);
+ __entry->base = base;
+ __entry->offset = offset;
+ __entry->value = value;
-+ ),
+ ),
+- TP_printk("%s", __get_str(msg))
+ TP_printk("addr %p value %08x", __entry->base + __entry->offset,
+ __entry->value)
);
--DEFINE_EVENT(dwc3_log_msg, dwc3_ep0,
+-DEFINE_EVENT(dwc3_log_msg, dwc3_readl,
- TP_PROTO(struct va_format *vaf),
- TP_ARGS(vaf)
+DEFINE_EVENT(dwc3_log_io, dwc3_readl,
+ TP_PROTO(void *base, u32 offset, u32 value),
+ TP_ARGS(base, offset, value)
-+);
-+
+ );
+
+-DEFINE_EVENT(dwc3_log_msg, dwc3_writel,
+- TP_PROTO(struct va_format *vaf),
+- TP_ARGS(vaf)
+-);
+-
+-DEFINE_EVENT(dwc3_log_msg, dwc3_gadget,
+- TP_PROTO(struct va_format *vaf),
+- TP_ARGS(vaf)
+-);
+-
+-DEFINE_EVENT(dwc3_log_msg, dwc3_core,
+- TP_PROTO(struct va_format *vaf),
+- TP_ARGS(vaf)
+-);
+-
+-DEFINE_EVENT(dwc3_log_msg, dwc3_ep0,
+- TP_PROTO(struct va_format *vaf),
+- TP_ARGS(vaf)
+DEFINE_EVENT(dwc3_log_io, dwc3_writel,
+ TP_PROTO(void *base, u32 offset, u32 value),
+ TP_ARGS(base, offset, value)
@@ -337009,6 +407006,7 @@ index d24cefd..b2153f2 100644
TP_STRUCT__entry(
__field(u32, event)
+ __field(u32, ep0state)
++ __dynamic_array(char, str, DWC3_MSG_MAX)
),
TP_fast_assign(
__entry->event = event;
@@ -337016,7 +407014,8 @@ index d24cefd..b2153f2 100644
),
TP_printk("event (%08x): %s", __entry->event,
- dwc3_decode_event(__entry->event))
-+ dwc3_decode_event(__entry->event, __entry->ep0state))
++ dwc3_decode_event(__get_str(str), DWC3_MSG_MAX,
++ __entry->event, __entry->ep0state))
);
DEFINE_EVENT(dwc3_log_event, dwc3_event,
@@ -337027,15 +407026,104 @@ index d24cefd..b2153f2 100644
);
DECLARE_EVENT_CLASS(dwc3_log_ctrl,
-@@ -237,6 +256,7 @@ DECLARE_EVENT_CLASS(dwc3_log_trb,
+@@ -89,6 +85,7 @@ DECLARE_EVENT_CLASS(dwc3_log_ctrl,
+ __field(__u16, wValue)
+ __field(__u16, wIndex)
+ __field(__u16, wLength)
++ __dynamic_array(char, str, DWC3_MSG_MAX)
+ ),
+ TP_fast_assign(
+ __entry->bRequestType = ctrl->bRequestType;
+@@ -97,10 +94,10 @@ DECLARE_EVENT_CLASS(dwc3_log_ctrl,
+ __entry->wIndex = le16_to_cpu(ctrl->wIndex);
+ __entry->wLength = le16_to_cpu(ctrl->wLength);
+ ),
+- TP_printk("bRequestType %02x bRequest %02x wValue %04x wIndex %04x wLength %d",
+- __entry->bRequestType, __entry->bRequest,
+- __entry->wValue, __entry->wIndex,
+- __entry->wLength
++ TP_printk("%s", dwc3_decode_ctrl(__get_str(str), DWC3_MSG_MAX,
++ __entry->bRequestType,
++ __entry->bRequest, __entry->wValue,
++ __entry->wIndex, __entry->wLength)
+ )
+ );
+
+@@ -113,7 +110,7 @@ DECLARE_EVENT_CLASS(dwc3_log_request,
+ TP_PROTO(struct dwc3_request *req),
+ TP_ARGS(req),
+ TP_STRUCT__entry(
+- __dynamic_array(char, name, DWC3_MSG_MAX)
++ __string(name, req->dep->name)
+ __field(struct dwc3_request *, req)
+ __field(unsigned, actual)
+ __field(unsigned, length)
+@@ -123,7 +120,7 @@ DECLARE_EVENT_CLASS(dwc3_log_request,
+ __field(int, no_interrupt)
+ ),
+ TP_fast_assign(
+- snprintf(__get_str(name), DWC3_MSG_MAX, "%s", req->dep->name);
++ __assign_str(name, req->dep->name);
+ __entry->req = req;
+ __entry->actual = req->request.actual;
+ __entry->length = req->request.length;
+@@ -179,7 +176,7 @@ DECLARE_EVENT_CLASS(dwc3_log_generic_cmd,
+ __entry->param = param;
+ __entry->status = status;
+ ),
+- TP_printk("cmd '%s' [%d] param %08x --> status: %s",
++ TP_printk("cmd '%s' [%x] param %08x --> status: %s",
+ dwc3_gadget_generic_cmd_string(__entry->cmd),
+ __entry->cmd, __entry->param,
+ dwc3_gadget_generic_cmd_status_string(__entry->status)
+@@ -196,7 +193,7 @@ DECLARE_EVENT_CLASS(dwc3_log_gadget_ep_cmd,
+ struct dwc3_gadget_ep_cmd_params *params, int cmd_status),
+ TP_ARGS(dep, cmd, params, cmd_status),
+ TP_STRUCT__entry(
+- __dynamic_array(char, name, DWC3_MSG_MAX)
++ __string(name, dep->name)
+ __field(unsigned int, cmd)
+ __field(u32, param0)
+ __field(u32, param1)
+@@ -204,14 +201,14 @@ DECLARE_EVENT_CLASS(dwc3_log_gadget_ep_cmd,
+ __field(int, cmd_status)
+ ),
+ TP_fast_assign(
+- snprintf(__get_str(name), DWC3_MSG_MAX, "%s", dep->name);
++ __assign_str(name, dep->name);
+ __entry->cmd = cmd;
+ __entry->param0 = params->param0;
+ __entry->param1 = params->param1;
+ __entry->param2 = params->param2;
+ __entry->cmd_status = cmd_status;
+ ),
+- TP_printk("%s: cmd '%s' [%d] params %08x %08x %08x --> status: %s",
++ TP_printk("%s: cmd '%s' [%x] params %08x %08x %08x --> status: %s",
+ __get_str(name), dwc3_gadget_ep_cmd_string(__entry->cmd),
+ __entry->cmd, __entry->param0,
+ __entry->param1, __entry->param2,
+@@ -229,7 +226,7 @@ DECLARE_EVENT_CLASS(dwc3_log_trb,
+ TP_PROTO(struct dwc3_ep *dep, struct dwc3_trb *trb),
+ TP_ARGS(dep, trb),
+ TP_STRUCT__entry(
+- __dynamic_array(char, name, DWC3_MSG_MAX)
++ __string(name, dep->name)
+ __field(struct dwc3_trb *, trb)
+ __field(u32, allocated)
+ __field(u32, queued)
+@@ -237,9 +234,10 @@ DECLARE_EVENT_CLASS(dwc3_log_trb,
__field(u32, bph)
__field(u32, size)
__field(u32, ctrl)
+ __field(u32, type)
),
TP_fast_assign(
- snprintf(__get_str(name), DWC3_MSG_MAX, "%s", dep->name);
-@@ -247,11 +267,31 @@ DECLARE_EVENT_CLASS(dwc3_log_trb,
+- snprintf(__get_str(name), DWC3_MSG_MAX, "%s", dep->name);
++ __assign_str(name, dep->name);
+ __entry->trb = trb;
+ __entry->allocated = dep->allocated_requests;
+ __entry->queued = dep->queued_requests;
+@@ -247,47 +245,40 @@ DECLARE_EVENT_CLASS(dwc3_log_trb,
__entry->bph = trb->bph;
__entry->size = trb->size;
__entry->ctrl = trb->ctrl;
@@ -337059,9 +407147,11 @@ index d24cefd..b2153f2 100644
+ s = "2x ";
+ break;
+ case 3:
++ default:
+ s = "3x ";
+ break;
+ }
++ break;
+ default:
+ s = "";
+ } s; }),
@@ -337069,6 +407159,100 @@ index d24cefd..b2153f2 100644
__entry->ctrl & DWC3_TRB_CTRL_HWO ? 'H' : 'h',
__entry->ctrl & DWC3_TRB_CTRL_LST ? 'L' : 'l',
__entry->ctrl & DWC3_TRB_CTRL_CHN ? 'C' : 'c',
+ __entry->ctrl & DWC3_TRB_CTRL_CSP ? 'S' : 's',
+ __entry->ctrl & DWC3_TRB_CTRL_ISP_IMI ? 'S' : 's',
+ __entry->ctrl & DWC3_TRB_CTRL_IOC ? 'C' : 'c',
+- ({char *s;
+- switch (__entry->ctrl & 0x3f0) {
+- case DWC3_TRBCTL_NORMAL:
+- s = "normal";
+- break;
+- case DWC3_TRBCTL_CONTROL_SETUP:
+- s = "setup";
+- break;
+- case DWC3_TRBCTL_CONTROL_STATUS2:
+- s = "status2";
+- break;
+- case DWC3_TRBCTL_CONTROL_STATUS3:
+- s = "status3";
+- break;
+- case DWC3_TRBCTL_CONTROL_DATA:
+- s = "data";
+- break;
+- case DWC3_TRBCTL_ISOCHRONOUS_FIRST:
+- s = "isoc-first";
+- break;
+- case DWC3_TRBCTL_ISOCHRONOUS:
+- s = "isoc";
+- break;
+- case DWC3_TRBCTL_LINK_TRB:
+- s = "link";
+- break;
+- default:
+- s = "UNKNOWN";
+- break;
+- } s; })
++ dwc3_trb_type_string(DWC3_TRBCTL_TYPE(__entry->ctrl))
+ )
+ );
+
+@@ -301,6 +292,56 @@ DEFINE_EVENT(dwc3_log_trb, dwc3_complete_trb,
+ TP_ARGS(dep, trb)
+ );
+
++DECLARE_EVENT_CLASS(dwc3_log_ep,
++ TP_PROTO(struct dwc3_ep *dep),
++ TP_ARGS(dep),
++ TP_STRUCT__entry(
++ __string(name, dep->name)
++ __field(unsigned, maxpacket)
++ __field(unsigned, maxpacket_limit)
++ __field(unsigned, max_streams)
++ __field(unsigned, maxburst)
++ __field(unsigned, flags)
++ __field(unsigned, direction)
++ __field(u8, trb_enqueue)
++ __field(u8, trb_dequeue)
++ ),
++ TP_fast_assign(
++ __assign_str(name, dep->name);
++ __entry->maxpacket = dep->endpoint.maxpacket;
++ __entry->maxpacket_limit = dep->endpoint.maxpacket_limit;
++ __entry->max_streams = dep->endpoint.max_streams;
++ __entry->maxburst = dep->endpoint.maxburst;
++ __entry->flags = dep->flags;
++ __entry->direction = dep->direction;
++ __entry->trb_enqueue = dep->trb_enqueue;
++ __entry->trb_dequeue = dep->trb_dequeue;
++ ),
++ TP_printk("%s: mps %d/%d streams %d burst %d ring %d/%d flags %c:%c%c%c%c%c:%c",
++ __get_str(name), __entry->maxpacket,
++ __entry->maxpacket_limit, __entry->max_streams,
++ __entry->maxburst, __entry->trb_enqueue,
++ __entry->trb_dequeue,
++ __entry->flags & DWC3_EP_ENABLED ? 'E' : 'e',
++ __entry->flags & DWC3_EP_STALL ? 'S' : 's',
++ __entry->flags & DWC3_EP_WEDGE ? 'W' : 'w',
++ __entry->flags & DWC3_EP_BUSY ? 'B' : 'b',
++ __entry->flags & DWC3_EP_PENDING_REQUEST ? 'P' : 'p',
++ __entry->flags & DWC3_EP_MISSED_ISOC ? 'M' : 'm',
++ __entry->direction ? '<' : '>'
++ )
++);
++
++DEFINE_EVENT(dwc3_log_ep, dwc3_gadget_ep_enable,
++ TP_PROTO(struct dwc3_ep *dep),
++ TP_ARGS(dep)
++);
++
++DEFINE_EVENT(dwc3_log_ep, dwc3_gadget_ep_disable,
++ TP_PROTO(struct dwc3_ep *dep),
++ TP_ARGS(dep)
++);
++
+ #endif /* __DWC3_TRACE_H */
+
+ /* this part has to be here */
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index f3ee80e..e98f894 100644
--- a/drivers/usb/gadget/Kconfig
@@ -337185,6 +407369,30 @@ index baa7cdc..4420df9 100644
usb_gadget_unregister_driver(&driver->gadget_driver);
}
EXPORT_SYMBOL_GPL(usb_composite_unregister);
+diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c
+index 3984787..3411586 100644
+--- a/drivers/usb/gadget/configfs.c
++++ b/drivers/usb/gadget/configfs.c
+@@ -1209,6 +1209,9 @@ static void purge_configs_funcs(struct gadget_info *gi)
+
+ list_for_each_entry_safe(f, tmp, &c->functions, list) {
+
++ if (f->disable)
++ f->disable(f);
++
+ list_move_tail(&f->list, &cfg->func_list);
+ if (f->unbind) {
+ dev_dbg(&gi->cdev.gadget->dev,
+@@ -1216,6 +1219,9 @@ static void purge_configs_funcs(struct gadget_info *gi)
+ f->name, f);
+ f->unbind(c, f);
+ }
++
++ if (f->bind_deactivated)
++ usb_function_activate(f);
+ }
+ c->next_interface_id = 0;
+ memset(c->interface, 0, sizeof(c->interface));
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 30fdab0..ae86e08 100644
--- a/drivers/usb/gadget/epautoconf.c
@@ -340911,7 +411119,7 @@ index 969cfe7..ff0f118 100644
DECLARE_USB_FUNCTION_INIT(uac2, afunc_alloc_inst, afunc_alloc);
diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c
-index c7689d0..7ddf42b 100644
+index c7689d0..804529f 100644
--- a/drivers/usb/gadget/function/f_uvc.c
+++ b/drivers/usb/gadget/function/f_uvc.c
@@ -594,6 +594,14 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f)
@@ -340929,22 +411137,15 @@ index c7689d0..7ddf42b 100644
/* Fill in the FS/HS/SS Video Streaming specific descriptors from the
* module parameters.
*
-@@ -619,12 +627,12 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f)
- cpu_to_le16(max_packet_size | ((max_packet_mult - 1) << 11));
- uvc_hs_streaming_ep.bInterval = opts->streaming_interval;
+@@ -621,7 +629,7 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f)
-- uvc_ss_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size);
-+ uvc_ss_streaming_ep.wMaxPacketSize = cpu_to_le16(min(opts->streaming_maxpacket, 1024U));
+ uvc_ss_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size);
uvc_ss_streaming_ep.bInterval = opts->streaming_interval;
- uvc_ss_streaming_comp.bmAttributes = max_packet_mult - 1;
-+ uvc_ss_streaming_comp.bmAttributes = 0;
++ uvc_ss_streaming_comp.bmAttributes = 1;
uvc_ss_streaming_comp.bMaxBurst = opts->streaming_maxburst;
uvc_ss_streaming_comp.wBytesPerInterval =
-- cpu_to_le16(max_packet_size * max_packet_mult *
-+ cpu_to_le16(uvc_ss_streaming_ep.wMaxPacketSize *
- (opts->streaming_maxburst + 1));
-
- /* Allocate endpoints. */
+ cpu_to_le16(max_packet_size * max_packet_mult *
@@ -720,7 +728,7 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f)
}
@@ -340999,7 +411200,7 @@ index c7689d0..7ddf42b 100644
opts->fs_control =
(const struct uvc_descriptor_header * const *)ctl_cls;
-@@ -832,13 +860,14 @@ static struct usb_function_instance *uvc_alloc_inst(void)
+@@ -832,13 +860,15 @@ static struct usb_function_instance *uvc_alloc_inst(void)
ctl_cls[0] = NULL; /* assigned elsewhere by configfs */
ctl_cls[1] = (struct uvc_descriptor_header *)cd;
ctl_cls[2] = (struct uvc_descriptor_header *)pd;
@@ -341014,6 +411215,7 @@ index c7689d0..7ddf42b 100644
opts->streaming_interval = 1;
- opts->streaming_maxpacket = 1024;
+ opts->streaming_maxpacket = 3072;
++ opts->streaming_maxburst = 15;
uvcg_attach_configfs(opts);
return &opts->func_inst;
@@ -342345,19 +412547,32 @@ index 4676b60..82c51b8 100644
/*
* Streaming descriptors for full-speed, high-speed and super-speed.
diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h
-index 7d3bb62..77ba30a 100644
+index 7d3bb62..afc14c8 100644
--- a/drivers/usb/gadget/function/uvc.h
+++ b/drivers/usb/gadget/function/uvc.h
-@@ -96,7 +96,7 @@ extern unsigned int uvc_gadget_trace_param;
+@@ -17,6 +17,7 @@
+ #include <linux/types.h>
+ #include <linux/usb/ch9.h>
+
++#define UVC_SG_REQ
+ #define UVC_EVENT_FIRST (V4L2_EVENT_PRIVATE_START + 0)
+ #define UVC_EVENT_CONNECT (V4L2_EVENT_PRIVATE_START + 0)
+ #define UVC_EVENT_DISCONNECT (V4L2_EVENT_PRIVATE_START + 1)
+@@ -95,8 +96,11 @@ extern unsigned int uvc_gadget_trace_param;
+ /* ------------------------------------------------------------------------
* Driver specific constants
*/
-
+-
-#define UVC_NUM_REQUESTS 4
-+#define UVC_NUM_REQUESTS 32
++#ifdef UVC_SG_REQ
++#define UVC_NUM_REQUESTS 1
++#else
++#define UVC_NUM_REQUESTS 32
++#endif
#define UVC_MAX_REQUEST_SIZE 64
#define UVC_MAX_EVENTS 4
-@@ -106,6 +106,7 @@ extern unsigned int uvc_gadget_trace_param;
+@@ -106,6 +110,7 @@ extern unsigned int uvc_gadget_trace_param;
struct uvc_video
{
@@ -342365,6 +412580,16 @@ index 7d3bb62..77ba30a 100644
struct usb_ep *ep;
/* Frame parameters */
+@@ -116,6 +121,9 @@ struct uvc_video
+ unsigned int imagesize;
+ struct mutex mutex; /* protects frame parameters */
+
++ unsigned int num_sgs; /* record base */
++ __u8 *sg_buf;
++
+ /* Requests */
+ unsigned int req_size;
+ struct usb_request *req[UVC_NUM_REQUESTS];
diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c
index 31125a4..37ce903 100644
--- a/drivers/usb/gadget/function/uvc_configfs.c
@@ -343210,28 +413435,91 @@ index 31125a4..37ce903 100644
&uvcg_streaming_grp.group);
configfs_add_default_group(&uvcg_streaming_class_grp.group,
diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c
-index f4ccbd5..ae0e123 100644
+index f4ccbd5..45e8393 100644
--- a/drivers/usb/gadget/function/uvc_v4l2.c
+++ b/drivers/usb/gadget/function/uvc_v4l2.c
@@ -60,8 +60,13 @@ struct uvc_format
};
static struct uvc_format uvc_formats[] = {
-+#ifndef CONFIG_HISI_MC
++#ifndef CONFIG_HISI_MC
{ 16, V4L2_PIX_FMT_YUYV },
+#else
-+ { 12, V4L2_PIX_FMT_YUV420 },
-+#endif
++ { 12, V4L2_PIX_FMT_NV21 },
++#endif
{ 0, V4L2_PIX_FMT_MJPEG },
+ { 0, V4L2_PIX_FMT_H264 },
};
static int
diff --git a/drivers/usb/gadget/function/uvc_video.c b/drivers/usb/gadget/function/uvc_video.c
-index 0f01c04..82b7607 100644
+index 0f01c04..9fd6dde 100644
--- a/drivers/usb/gadget/function/uvc_video.c
+++ b/drivers/usb/gadget/function/uvc_video.c
-@@ -129,6 +129,26 @@ uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video,
+@@ -23,6 +23,8 @@
+ #include "uvc_queue.h"
+ #include "uvc_video.h"
+
++#include <linux/scatterlist.h>
++#include <linux/io.h>
+ /* --------------------------------------------------------------------------
+ * Video codecs
+ */
+@@ -102,9 +104,45 @@ static void
+ uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video,
+ struct uvc_buffer *buf)
+ {
++ int ret;
++#ifdef UVC_SG_REQ
++ int len;
++ int ttllen = 0;
++ unsigned int sg_idx;
++ u8 *mem = NULL;
++
++ for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++) {
++ mem = sg_virt(&req->sg[sg_idx]);
++ len = video->req_size;
++
++ /* Add the header. */
++ ret = uvc_video_encode_header(video, buf, mem, len);
++ mem += ret;
++ len -= ret;
++
++ /* Process video data. */
++ ret = uvc_video_encode_data(video, buf, mem, len);
++ len -= ret;
++
++ /* Sync sg buffer len , default is 1024 or 3072 */
++ sg_set_buf(&req->sg[sg_idx], sg_virt(&req->sg[sg_idx]),
++ video->req_size - len);
++ ttllen += video->req_size - len;
++
++ if (buf->bytesused == video->queue.buf_used) {
++ video->queue.buf_used = 0;
++ buf->state = UVC_BUF_STATE_DONE;
++ uvcg_queue_next_buffer(&video->queue, buf);
++ video->fid ^= UVC_STREAM_FID;
++ break;
++ }
++ }
++ req->num_sgs = sg_idx + 1;
++ sg_mark_end(&req->sg[sg_idx]);
++ req->length = ttllen;
++#else
+ void *mem = req->buf;
+ int len = video->req_size;
+- int ret;
+
+ /* Add the header. */
+ ret = uvc_video_encode_header(video, buf, mem, len);
+@@ -123,12 +161,33 @@ uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video,
+ uvcg_queue_next_buffer(&video->queue, buf);
+ video->fid ^= UVC_STREAM_FID;
+ }
++#endif
+ }
+
+ /* --------------------------------------------------------------------------
* Request handling
*/
@@ -343258,8 +413546,14 @@ index 0f01c04..82b7607 100644
/*
* I somehow feel that synchronisation won't be easy to achieve here. We have
* three events that control USB requests submission:
-@@ -193,14 +213,13 @@ uvc_video_complete(struct usb_ep *ep, struct usb_request *req)
-
+@@ -190,22 +249,26 @@ uvc_video_complete(struct usb_ep *ep, struct usb_request *req)
+ spin_unlock_irqrestore(&video->queue.irqlock, flags);
+ goto requeue;
+ }
+-
++#ifdef UVC_SG_REQ
++ sg_unmark_end(&req->sg[req->num_sgs - 1]);
++#endif
video->encode(req, video, buf);
- if ((ret = usb_ep_queue(ep, req, GFP_ATOMIC)) < 0) {
@@ -343277,7 +413571,95 @@ index 0f01c04..82b7607 100644
return;
-@@ -320,15 +339,13 @@ int uvcg_video_pump(struct uvc_video *video)
+ requeue:
+ spin_lock_irqsave(&video->req_lock, flags);
++#ifdef UVC_SG_REQ
++ sg_unmark_end(&req->sg[req->num_sgs - 1]);
++#endif
+ list_add_tail(&req->list, &video->req_free);
+ spin_unlock_irqrestore(&video->req_lock, flags);
+ }
+@@ -214,9 +277,22 @@ static int
+ uvc_video_free_requests(struct uvc_video *video)
+ {
+ unsigned int i;
++#ifdef UVC_SG_REQ
++ unsigned int sg_idx;
++#endif
+
+ for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
+ if (video->req[i]) {
++#ifdef UVC_SG_REQ
++ for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++)
++ if (sg_page(&video->req[i]->sg[sg_idx]))
++ kfree(sg_virt(&video->req[i]->sg[sg_idx]));
++
++ if (video->req[i]->sg) {
++ kfree(video->req[i]->sg);
++ video->req[i]->sg = NULL;
++ }
++#endif
+ usb_ep_free_request(video->ep, video->req[i]);
+ video->req[i] = NULL;
+ }
+@@ -238,6 +314,11 @@ uvc_video_alloc_requests(struct uvc_video *video)
+ unsigned int req_size;
+ unsigned int i;
+ int ret = -ENOMEM;
++#ifdef UVC_SG_REQ
++ struct scatterlist *sg;
++ unsigned int num_sgs;
++ unsigned int sg_idx;
++#endif
+
+ BUG_ON(video->req_size);
+
+@@ -245,6 +326,35 @@ uvc_video_alloc_requests(struct uvc_video *video)
+ * max_t(unsigned int, video->ep->maxburst, 1)
+ * (video->ep->mult);
+
++#ifdef UVC_SG_REQ
++ num_sgs = ((video->imagesize / (req_size - 2)) + 1);
++ video->num_sgs = num_sgs;
++
++ for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
++ sg = kmalloc(num_sgs * sizeof(struct scatterlist), GFP_ATOMIC);
++ if (sg == NULL)
++ goto error;
++ sg_init_table(sg, num_sgs);
++
++ video->req[i] = usb_ep_alloc_request(video->ep, GFP_KERNEL);
++ if (video->req[i] == NULL)
++ goto error;
++
++ for (sg_idx = 0 ; sg_idx < num_sgs ; sg_idx++) {
++ video->sg_buf = kmalloc(req_size, GFP_KERNEL);
++ if (video->sg_buf == NULL)
++ goto error;
++ sg_set_buf(&sg[sg_idx], video->sg_buf, req_size);
++ }
++ video->req[i]->sg = sg;
++ video->req[i]->num_sgs = num_sgs;
++ video->req[i]->length = 0;
++ video->req[i]->complete = uvc_video_complete;
++ video->req[i]->context = video;
++
++ list_add_tail(&video->req[i]->list, &video->req_free);
++ }
++#else
+ for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
+ video->req_buffer[i] = kmalloc(req_size, GFP_KERNEL);
+ if (video->req_buffer[i] == NULL)
+@@ -261,7 +371,7 @@ uvc_video_alloc_requests(struct uvc_video *video)
+
+ list_add_tail(&video->req[i]->list, &video->req_free);
+ }
+-
++#endif
+ video->req_size = req_size;
+
+ return 0;
+@@ -320,15 +430,13 @@ int uvcg_video_pump(struct uvc_video *video)
video->encode(req, video, buf);
/* Queue the USB request */
@@ -343296,7 +413678,7 @@ index 0f01c04..82b7607 100644
}
spin_lock_irqsave(&video->req_lock, flags);
-@@ -379,16 +396,22 @@ int uvcg_video_enable(struct uvc_video *video, int enable)
+@@ -379,16 +487,22 @@ int uvcg_video_enable(struct uvc_video *video, int enable)
/*
* Initialize the UVC video stream.
*/
@@ -343311,7 +413693,7 @@ index 0f01c04..82b7607 100644
+ video->imagesize = 320 * 240 * 2;
video->bpp = 16;
+#else
-+ video->fcc = V4L2_PIX_FMT_YUV420;
++ video->fcc = V4L2_PIX_FMT_NV21;
+ video->imagesize = 320 * 240 * 3 / 2; /* YUV420: w*h*1.5 */
+ video->bpp = 12;
+#endif
@@ -343460,7 +413842,7 @@ index a70a406..4f6f0d1 100644
#ifdef USB_ETH_RNDIS
usb_put_function_instance(fi_rndis);
diff --git a/drivers/usb/gadget/legacy/webcam.c b/drivers/usb/gadget/legacy/webcam.c
-index f9661cd..6f56617 100644
+index f9661cd..cc21e05 100644
--- a/drivers/usb/gadget/legacy/webcam.c
+++ b/drivers/usb/gadget/legacy/webcam.c
@@ -26,11 +26,11 @@ static unsigned int streaming_interval = 1;
@@ -343596,8 +413978,8 @@ index f9661cd..6f56617 100644
.bDescriptorSubType = UVC_VS_FORMAT_UNCOMPRESSED,
.bFormatIndex = 1,
- .bNumFrameDescriptors = 2,
-+ .bNumFrameDescriptors = 1,
-+#ifndef CONFIG_HISI_MC
++ .bNumFrameDescriptors = 3,
++#ifndef CONFIG_HISI_MC
.guidFormat =
{ 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00,
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71},
@@ -343605,9 +413987,9 @@ index f9661cd..6f56617 100644
+#else
+ .guidFormat = {
+ 'N', 'V', '2', '1', 0x00, 0x00, 0x10, 0x00,
-+ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71},
++ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71},
+ .bBitsPerPixel = 12,
-+#endif
++#endif
.bDefaultFrameIndex = 1,
.bAspectRatioX = 0,
.bAspectRatioY = 0,
@@ -343628,7 +414010,7 @@ index f9661cd..6f56617 100644
- .dwMinBitRate = cpu_to_le32(18432000),
+ .dwMinBitRate = cpu_to_le32(55296000),
.dwMaxBitRate = cpu_to_le32(55296000),
-+#ifndef CONFIG_HISI_MC
++#ifndef CONFIG_HISI_MC
.dwMaxVideoFrameBufferSize = cpu_to_le32(460800),
- .dwDefaultFrameInterval = cpu_to_le32(666666),
- .bFrameIntervalType = 3,
@@ -343637,7 +414019,7 @@ index f9661cd..6f56617 100644
- .dwFrameInterval[2] = cpu_to_le32(5000000),
+#else
+ .dwMaxVideoFrameBufferSize = cpu_to_le32(345600),
-+#endif
++#endif
+ .dwDefaultFrameInterval = cpu_to_le32(333333),
+ .bFrameIntervalType = 1,
+ .dwFrameInterval[0] = cpu_to_le32(333333),
@@ -343648,11 +414030,12 @@ index f9661cd..6f56617 100644
.wHeight = cpu_to_le16(720),
.dwMinBitRate = cpu_to_le32(29491200),
.dwMaxBitRate = cpu_to_le32(29491200),
-+#ifndef CONFIG_HISI_MC
-+ .dwMaxVideoFrameBufferSize = cpu_to_le32(1843200),
++#ifndef CONFIG_HISI_MC
+ .dwMaxVideoFrameBufferSize = cpu_to_le32(1843200),
+- .dwDefaultFrameInterval = cpu_to_le32(5000000),
+#else
+ .dwMaxVideoFrameBufferSize = cpu_to_le32(1382400),
-+#endif
++#endif
+ .dwDefaultFrameInterval = cpu_to_le32(333333),
+ .bFrameIntervalType = 1,
+ .dwFrameInterval[0] = cpu_to_le32(333333),
@@ -343669,12 +414052,13 @@ index f9661cd..6f56617 100644
+ .dwMinBitRate = cpu_to_le32(29491200),
+ .dwMaxBitRate = cpu_to_le32(29491200),
+#ifndef CONFIG_HISI_MC
-+ .dwMaxVideoFrameBufferSize = cpu_to_le32(1843200),
++ .dwMaxVideoFrameBufferSize = cpu_to_le32(4147200),
+#else
+ .dwMaxVideoFrameBufferSize = cpu_to_le32(3110400),
+#endif
+ .dwDefaultFrameInterval = cpu_to_le32(333333),
-+ .bFrameIntervalType = 1,
+ .bFrameIntervalType = 1,
+- .dwFrameInterval[0] = cpu_to_le32(5000000),
+ .dwFrameInterval[0] = cpu_to_le32(333333),
+};
+
@@ -343688,15 +414072,13 @@ index f9661cd..6f56617 100644
+ .wHeight = cpu_to_le16(2160),
+ .dwMinBitRate = cpu_to_le32(29491200),
+ .dwMaxBitRate = cpu_to_le32(29491200),
-+#ifndef CONFIG_HISI_MC
- .dwMaxVideoFrameBufferSize = cpu_to_le32(1843200),
-- .dwDefaultFrameInterval = cpu_to_le32(5000000),
++#ifndef CONFIG_HISI_MC
++ .dwMaxVideoFrameBufferSize = cpu_to_le32(16588800),
+#else
+ .dwMaxVideoFrameBufferSize = cpu_to_le32(12441600),
-+#endif
++#endif
+ .dwDefaultFrameInterval = cpu_to_le32(333333),
- .bFrameIntervalType = 1,
-- .dwFrameInterval[0] = cpu_to_le32(5000000),
++ .bFrameIntervalType = 1,
+ .dwFrameInterval[0] = cpu_to_le32(333333),
};
@@ -343751,8 +414133,7 @@ index f9661cd..6f56617 100644
.dwMaxVideoFrameBufferSize = cpu_to_le32(1843200),
- .dwDefaultFrameInterval = cpu_to_le32(5000000),
+ .dwDefaultFrameInterval = cpu_to_le32(333333),
- .bFrameIntervalType = 1,
-- .dwFrameInterval[0] = cpu_to_le32(5000000),
++ .bFrameIntervalType = 1,
+ .dwFrameInterval[0] = cpu_to_le32(333333),
+};
+
@@ -343768,7 +414149,8 @@ index f9661cd..6f56617 100644
+ .dwMaxBitRate = cpu_to_le32(40960000),
+ .dwMaxVideoFrameBufferSize = cpu_to_le32(4147200),
+ .dwDefaultFrameInterval = cpu_to_le32(333333),
-+ .bFrameIntervalType = 1,
+ .bFrameIntervalType = 1,
+- .dwFrameInterval[0] = cpu_to_le32(5000000),
+ .dwFrameInterval[0] = cpu_to_le32(333333),
+};
+
@@ -343936,9 +414318,8 @@ index f9661cd..6f56617 100644
(const struct uvc_descriptor_header *) &uvc_input_header,
(const struct uvc_descriptor_header *) &uvc_format_yuv,
(const struct uvc_descriptor_header *) &uvc_frame_yuv_360p,
-- (const struct uvc_descriptor_header *) &uvc_frame_yuv_720p,
-+// (const struct uvc_descriptor_header *) &uvc_frame_yuv_720p,
-+// (const struct uvc_descriptor_header *) &uvc_frame_yuv_1080p,
+ (const struct uvc_descriptor_header *) &uvc_frame_yuv_720p,
++ (const struct uvc_descriptor_header *) &uvc_frame_yuv_1080p,
+// (const struct uvc_descriptor_header *) &uvc_frame_yuv_2160p,
(const struct uvc_descriptor_header *) &uvc_format_mjpg,
(const struct uvc_descriptor_header *) &uvc_frame_mjpg_360p,
@@ -390246,6 +460627,31 @@ index 0000000..357d6c7
+#endif
+
+#endif /* _USB_H_ */
+diff --git a/drivers/usb/gadget/udc/trace.h b/drivers/usb/gadget/udc/trace.h
+index da29874..a14e25d 100644
+--- a/drivers/usb/gadget/udc/trace.h
++++ b/drivers/usb/gadget/udc/trace.h
+@@ -236,6 +236,7 @@ DECLARE_EVENT_CLASS(udc_log_req,
+ __field(unsigned, short_not_ok)
+ __field(int, status)
+ __field(int, ret)
++ __field(struct usb_request *, req)
+ ),
+ TP_fast_assign(
+ snprintf(__get_str(name), UDC_TRACE_STR_MAX, "%s", ep->name);
+@@ -249,9 +250,10 @@ DECLARE_EVENT_CLASS(udc_log_req,
+ __entry->short_not_ok = req->short_not_ok;
+ __entry->status = req->status;
+ __entry->ret = ret;
++ __entry->req = req;
+ ),
+- TP_printk("%s: length %d/%d sgs %d/%d stream %d %s%s%s status %d --> %d",
+- __get_str(name), __entry->actual, __entry->length,
++ TP_printk("%s: req %p length %d/%d sgs %d/%d stream %d %s%s%s status %d --> %d",
++ __get_str(name),__entry->req, __entry->actual, __entry->length,
+ __entry->num_mapped_sgs, __entry->num_sgs, __entry->stream_id,
+ __entry->zero ? "Z" : "z",
+ __entry->short_not_ok ? "S" : "s",
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index ff544f2..68383cb 100644
--- a/drivers/usb/host/xhci-hub.c
@@ -391018,7 +461424,7 @@ index 3d04b12..34c5358 100644
up_write(&MSDOS_I(inode)->truncate_lock);
}
diff --git a/fs/fat/inode.c b/fs/fat/inode.c
-index a2c05f2..c2d0363 100644
+index a2c05f2..78106df 100644
--- a/fs/fat/inode.c
+++ b/fs/fat/inode.c
@@ -615,8 +615,9 @@ static void fat_free_eofblocks(struct inode *inode)
@@ -391052,7 +461458,8 @@ index a2c05f2..c2d0363 100644
+ struct msdos_dir_entry *raw_entry;
+ loff_t i_pos;
+ sector_t blocknr;
-+ int err, offset;
++ int err = 0;
++ int offset;
+
+ if (inode->i_ino == MSDOS_ROOT_INO)
+ return 0;
@@ -391106,7 +461513,6 @@ index a2c05f2..c2d0363 100644
+ }
+ spin_unlock(&sbi->inode_hash_lock);
+ mark_buffer_dirty(bh);
-+ err = 0;
+ if (wait) {
+ err = sync_dirty_buffer(bh);
+ }
@@ -408915,10 +479321,10 @@ index 0000000..c889d56
+#endif /* __DTS_HI3516A_CLOCK_H */
diff --git a/include/dt-bindings/clock/hi3516cv500-clock.h b/include/dt-bindings/clock/hi3516cv500-clock.h
new file mode 100644
-index 0000000..4294b90
+index 0000000..f937680
--- /dev/null
+++ b/include/dt-bindings/clock/hi3516cv500-clock.h
-@@ -0,0 +1,96 @@
+@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -409010,6 +479416,8 @@ index 0000000..4294b90
+#define HI3516CV500_I2C6_CLK 61
+#define HI3516CV500_I2C7_CLK 62
+#define HI3516CV500_DMAC_AXICLK 70
++#define HI3516CV500_PWM_CLK 71
++#define HI3516CV500_PWM_MUX 72
+
+#define HI3516CV500_NR_CLKS 256
+#define HI3516CV500_NR_RSTS 256
@@ -409115,10 +479523,10 @@ index 0000000..83b7ad7
+#endif /* __DTS_HI3516DV200_CLOCK_H */
diff --git a/include/dt-bindings/clock/hi3516dv300-clock.h b/include/dt-bindings/clock/hi3516dv300-clock.h
new file mode 100644
-index 0000000..38ebad3
+index 0000000..408c9b0
--- /dev/null
+++ b/include/dt-bindings/clock/hi3516dv300-clock.h
-@@ -0,0 +1,98 @@
+@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -409212,6 +479620,8 @@ index 0000000..38ebad3
+#define HI3516DV300_UART3_MUX 63
+#define HI3516DV300_UART3_CLK 64
+#define HI3516DV300_DMAC_AXICLK 70
++#define HI3516DV300_PWM_CLK 71
++#define HI3516DV300_PWM_MUX 72
+
+#define HI3516DV300_NR_CLKS 256
+#define HI3516DV300_NR_RSTS 256
@@ -410219,10 +480629,10 @@ index 0000000..ad21684
+#endif /* __DTS_HI3556AV100_CLOCK_H */
diff --git a/include/dt-bindings/clock/hi3556v200-clock.h b/include/dt-bindings/clock/hi3556v200-clock.h
new file mode 100644
-index 0000000..00006ea
+index 0000000..3249447
--- /dev/null
+++ b/include/dt-bindings/clock/hi3556v200-clock.h
-@@ -0,0 +1,97 @@
+@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -410316,6 +480726,7 @@ index 0000000..00006ea
+#define HI3556V200_UART3_MUX 63
+#define HI3556V200_UART3_CLK 64
+#define HI3556V200_DMAC_AXICLK 70
++#define HI3556V200_PWM_CLK 71
+
+#define HI3556V200_NR_CLKS 256
+#define HI3556V200_NR_RSTS 256
@@ -410504,10 +480915,10 @@ index 0000000..0608eee
+
diff --git a/include/dt-bindings/clock/hi3559v200-clock.h b/include/dt-bindings/clock/hi3559v200-clock.h
new file mode 100644
-index 0000000..912f2d9
+index 0000000..5313e5b
--- /dev/null
+++ b/include/dt-bindings/clock/hi3559v200-clock.h
-@@ -0,0 +1,97 @@
+@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
@@ -410601,6 +481012,7 @@ index 0000000..912f2d9
+#define HI3559V200_UART3_MUX 63
+#define HI3559V200_UART3_CLK 64
+#define HI3559V200_DMAC_AXICLK 70
++#define HI3559V200_PWM_CLK 71
+
+#define HI3559V200_NR_CLKS 256
+#define HI3559V200_NR_RSTS 256
@@ -410821,9 +481233,69 @@ index 2f63d44..dd88ded 100644
#endif
#define FL_POSIX 1
+diff --git a/include/linux/hi_cma.h b/include/linux/hi_cma.h
+new file mode 100644
+index 0000000..3a7fad2
+--- /dev/null
++++ b/include/linux/hi_cma.h
+@@ -0,0 +1,54 @@
++/*
++ * hi_cma.h
++ *
++ * Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++#ifndef __HI_CMA_H__
++#define __HI_CMA_H__
++
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/dma-contiguous.h>
++#include <linux/module.h>
++#include <linux/string.h>
++#include <linux/cma.h>
++#include <linux/memblock.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
++#include <linux/of_reserved_mem.h>
++
++#define NAME_LEN_MAX 64
++#define ZONE_MAX 64
++
++struct cma_zone {
++ struct device pdev;
++ char name[NAME_LEN_MAX];
++ gfp_t gfp;
++ phys_addr_t phys_start;
++ phys_addr_t nbytes;
++ u32 alloc_type;
++ u32 block_align;
++};
++
++#ifdef CONFIG_CMA
++int is_hicma_address(phys_addr_t phys, unsigned long size);
++phys_addr_t hisi_get_zones_start(void);
++struct cma_zone *hisi_get_cma_zone(const char *name);
++struct device *hisi_get_cma_device(const char *name);
++int __init hisi_declare_heap_memory(void);
++#endif /* CONFIG_CMA */
++
++#endif
diff --git a/include/linux/hidmac.h b/include/linux/hidmac.h
new file mode 100644
-index 0000000..2bb5809
+index 0000000..0558f49
--- /dev/null
+++ b/include/linux/hidmac.h
@@ -0,0 +1,179 @@
@@ -410847,168 +481319,168 @@ index 0000000..2bb5809
+extern int dmac_channel_allocate(void *pisr);
+
+extern int dmac_start_m2p(unsigned int channel, unsigned int pmemaddr,
-+ unsigned int uwperipheralid,
-+ unsigned int uwnumtransfers,
-+ unsigned int next_lli_addr);
++ unsigned int uwperipheralid,
++ unsigned int uwnumtransfers,
++ unsigned int next_lli_addr);
+extern int dmac_m2p_transfer(unsigned int memaddr,
-+ unsigned int uwperipheralid, unsigned int length);
++ unsigned int uwperipheralid, unsigned int length);
+extern int dmac_channel_free(unsigned int channel);
+extern int do_dma_m2p(unsigned int mem_addr, unsigned int peripheral_addr,
-+ unsigned int length);
++ unsigned int length);
+extern int do_dma_p2m(unsigned int mem_addr, unsigned int peripheral_addr,
-+ unsigned int length);
++ unsigned int length);
+extern int dmac_wait(int channel);
+extern int dmac_start_m2m(unsigned int channel, unsigned int psource,
-+ unsigned int pdest, unsigned int uwnumtransfers);
++ unsigned int pdest, unsigned int uwnumtransfers);
+extern int dmac_m2m_transfer(unsigned int source,
-+ unsigned int dest, unsigned int length);
++ unsigned int dest, unsigned int length);
+extern int dmac_register_isr(unsigned int channel, void *pisr);
+extern int free_dmalli_space(unsigned int *ppheadlli, unsigned int page_num);
+extern int dmac_start_llim2p(unsigned int channel, unsigned int *pfirst_lli,
-+ unsigned int uwperipheralid);
++ unsigned int uwperipheralid);
+extern int dmac_buildllim2m(unsigned int *ppheadlli, unsigned int pdest,
-+ unsigned int psource,
-+ unsigned int totaltransfersize,
-+ unsigned int uwnumtransfers);
++ unsigned int psource,
++ unsigned int totaltransfersize,
++ unsigned int uwnumtransfers);
+extern int dmac_start_llim2m(unsigned int channel, unsigned int *pfirst_lli);
+extern int allocate_dmalli_space(unsigned int *ppheadlli,
-+ unsigned int page_num);
++ unsigned int page_num);
+
+extern int do_dma_llim2m_isp(unsigned int *source,
-+ unsigned int *dest,
-+ unsigned int *length,
-+ unsigned int num);
++ unsigned int *dest,
++ unsigned int *length,
++ unsigned int num);
+
+#else /* !CONFIG_HI_DMAC */
+static inline int dma_driver_init(void)
+{
-+ return 0;
++ return 0;
+}
+static inline int dmac_channelclose(unsigned int channel)
+{
-+ return 0;
++ return 0;
+}
+static inline int dmac_channelstart(unsigned int u32channel)
+{
-+ return 0;
++ return 0;
+}
+static inline int dmac_channel_allocate(void *pisr)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_start_m2p(unsigned int channel, unsigned int pmemaddr,
-+ unsigned int uwperipheralid,
-+ unsigned int uwnumtransfers,
-+ unsigned int next_lli_addr)
++ unsigned int uwperipheralid,
++ unsigned int uwnumtransfers,
++ unsigned int next_lli_addr)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_m2p_transfer(unsigned int memaddr,
-+ unsigned int uwperipheralid, unsigned int length)
++ unsigned int uwperipheralid, unsigned int length)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_channel_free(unsigned int channel)
+{
-+ return 0;
++ return 0;
+}
+
+int do_dma_m2p(unsigned int mem_addr, unsigned int peripheral_addr,
-+ unsigned int length)
++ unsigned int length)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int do_dma_p2m(unsigned int mem_addr,
-+ unsigned int peripheral_addr,
-+ unsigned int length)
++ unsigned int peripheral_addr,
++ unsigned int length)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_wait(int channel)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_start_m2m(unsigned int channel, unsigned int psource,
-+ unsigned int pdest, unsigned int uwnumtransfers)
++ unsigned int pdest, unsigned int uwnumtransfers)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_m2m_transfer(unsigned int source,
-+ unsigned int dest, unsigned int length)
++ unsigned int dest, unsigned int length)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_register_isr(unsigned int channel, void *pisr)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int free_dmalli_space(unsigned int *ppheadlli,
-+ unsigned int page_num)
++ unsigned int page_num)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_start_llim2p(unsigned int channel,
-+ unsigned int *pfirst_lli,
-+ unsigned int uwperipheralid)
++ unsigned int *pfirst_lli,
++ unsigned int uwperipheralid)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_buildllim2m(unsigned int *ppheadlli, unsigned int pdest,
-+ unsigned int psource,
-+ unsigned int totaltransfersize,
-+ unsigned int uwnumtransfers)
++ unsigned int psource,
++ unsigned int totaltransfersize,
++ unsigned int uwnumtransfers)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int dmac_start_llim2m(unsigned int channel,
-+ unsigned int *pfirst_lli)
++ unsigned int *pfirst_lli)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int allocate_dmalli_space(unsigned int *ppheadlli,
-+ unsigned int page_num)
++ unsigned int page_num)
+{
-+ return 0;
++ return 0;
+}
+
+static inline int do_dma_llim2m_isp(unsigned int *source,
-+ unsigned int *dest,
-+ unsigned int *length,
-+ unsigned int num)
++ unsigned int *dest,
++ unsigned int *length,
++ unsigned int num)
+{
-+ return 0;
++ return 0;
+}
+#endif /* CONFIG_HI_DMAC */
+
+/*structure for LLI*/
+typedef struct dmac_lli {
-+ /*source address*/
-+ unsigned int src_addr;
-+ /*destination address*/
-+ unsigned int dst_addr;
-+ /*pointer to next LLI*/
-+ unsigned int next_lli;
-+ /*control word*/
-+ unsigned int lli_transfer_ctrl;
++ /*source address*/
++ unsigned int src_addr;
++ /*destination address*/
++ unsigned int dst_addr;
++ /*pointer to next LLI*/
++ unsigned int next_lli;
++ /*control word*/
++ unsigned int lli_transfer_ctrl;
+} dmac_lli;
+
+#endif
diff --git a/include/linux/hiedmac.h b/include/linux/hiedmac.h
new file mode 100644
-index 0000000..543fed3
+index 0000000..0bb72d3
--- /dev/null
+++ b/include/linux/hiedmac.h
@@ -0,0 +1,64 @@
@@ -411030,50 +481502,50 @@ index 0000000..543fed3
+extern int dmac_channel_allocate(void);
+
+extern int dmac_start_m2p(unsigned int channel, unsigned int pmemaddr,
-+ unsigned int uwperipheralid,
-+ unsigned int uwnumtransfers,
-+ unsigned int next_lli_addr);
++ unsigned int uwperipheralid,
++ unsigned int uwnumtransfers,
++ unsigned int next_lli_addr);
+extern int dmac_m2p_transfer(unsigned long long memaddr, unsigned int uwperipheralid,
-+ unsigned int length);
++ unsigned int length);
+extern int dmac_channel_free(unsigned int channel);
+
+extern int do_dma_m2p(unsigned long long memaddr, unsigned int peripheral_addr,
-+ unsigned int length);
++ unsigned int length);
+extern int do_dma_p2m(unsigned long mem_addr, unsigned int peripheral_addr,
-+ unsigned int length);
++ unsigned int length);
+extern int dmac_wait(int channel);
+
+extern int dmac_start_m2m(unsigned int channel, unsigned long psource,
-+ unsigned long pdest, unsigned int uwnumtransfers);
++ unsigned long pdest, unsigned int uwnumtransfers);
+extern int dmac_m2m_transfer(unsigned long source, unsigned long dest,
-+ unsigned int length);
++ unsigned int length);
+extern int dmac_register_isr(unsigned int channel, void *pisr);
+extern int free_dmalli_space(unsigned int *ppheadlli, unsigned int page_num);
+extern int dmac_start_llim2p(unsigned int channel, unsigned int *pfirst_lli,
-+ unsigned int uwperipheralid);
++ unsigned int uwperipheralid);
+extern int dmac_buildllim2m(unsigned long *ppheadlli,
-+ unsigned long psource,
-+ unsigned long pdest,
-+ unsigned int totaltransfersize,
-+ unsigned int uwnumtransfers);
++ unsigned long psource,
++ unsigned long pdest,
++ unsigned int totaltransfersize,
++ unsigned int uwnumtransfers);
+
+extern int dmac_start_llim2m(unsigned int channel, unsigned long *pfirst_lli);
+
+extern int allocate_dmalli_space(struct device *dev, unsigned long *ppheadlli,
-+ unsigned int page_num);
++ unsigned int page_num);
+#endif /* CONFIG_HIEDMAC*/
+
+
+/*structure for LLI*/
+typedef struct dmac_lli {
-+ //must be 64Byte aligned
-+ unsigned long next_lli;
-+ unsigned int reserved[5];
-+ unsigned int count;
-+ unsigned long src_addr;
-+ unsigned long dest_addr;
-+ unsigned int config;
-+ unsigned int pad[51];
++ //must be 64Byte aligned
++ unsigned long next_lli;
++ unsigned int reserved[5];
++ unsigned int count;
++ unsigned long src_addr;
++ unsigned long dest_addr;
++ unsigned int config;
++ unsigned int pad[51];
+} dmac_lli;
+#endif
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
@@ -411926,7 +482398,7 @@ index 0000000..4751acd
+#endif
diff --git a/include/linux/mfd/hisi_fmc.h b/include/linux/mfd/hisi_fmc.h
new file mode 100644
-index 0000000..fd0d8fd
+index 0000000..eba8e5f
--- /dev/null
+++ b/include/linux/mfd/hisi_fmc.h
@@ -0,0 +1,521 @@
@@ -412420,32 +482892,32 @@ index 0000000..fd0d8fd
+
+/*****************************************************************************/
+enum hifmc_iftype {
-+ IF_TYPE_STD,
-+ IF_TYPE_DUAL,
-+ IF_TYPE_DIO,
-+ IF_TYPE_QUAD,
-+ IF_TYPE_QIO,
++ IF_TYPE_STD,
++ IF_TYPE_DUAL,
++ IF_TYPE_DIO,
++ IF_TYPE_QUAD,
++ IF_TYPE_QIO,
+};
+
+struct hisi_fmc {
-+ void __iomem *regbase;
-+ void __iomem *iobase;
-+ struct clk *clk;
-+ struct mutex lock;
-+ void *buffer;
-+ dma_addr_t dma_buffer;
-+ unsigned int dma_len;
++ void __iomem *regbase;
++ void __iomem *iobase;
++ struct clk *clk;
++ struct mutex lock;
++ void *buffer;
++ dma_addr_t dma_buffer;
++ unsigned int dma_len;
+};
+
+struct hifmc_cmd_op {
-+ unsigned char cs;
-+ unsigned char cmd;
-+ unsigned char l_cmd;
-+ unsigned char addr_h;
-+ unsigned int addr_l;
-+ unsigned int data_no;
-+ unsigned short option;
-+ unsigned short op_cfg;
++ unsigned char cs;
++ unsigned char cmd;
++ unsigned char l_cmd;
++ unsigned char addr_h;
++ unsigned int addr_l;
++ unsigned int data_no;
++ unsigned short option;
++ unsigned short op_cfg;
+};
+
+extern struct mutex fmc_switch_mutex;
@@ -412876,7 +483348,7 @@ index d8905a2..c023fad 100644
/* The maximum expected count of bytes in the NAND ID sequence */
#define NAND_MAX_ID_LEN 8
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
-index c425c7b..d8c3db8 100644
+index c425c7b..0afe294 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -12,7 +12,6 @@
@@ -412887,7 +483359,7 @@ index c425c7b..d8c3db8 100644
/*
* Manufacturer IDs
-@@ -21,13 +20,51 @@
+@@ -21,13 +20,53 @@
* Sometimes these are the same as CFI IDs, but sometimes they aren't.
*/
#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
@@ -412903,6 +483375,8 @@ index c425c7b..d8c3db8 100644
+#define SNOR_MFR_ESMT 0x8c
+#define SNOR_MFR_GD 0xc8
+#define SNOR_MFR_XTX 0x0b
++#define SNOR_MFR_PUYA 0x85
++#define SNOR_MFR_ISSI 0x9d
+
+/* Flash set the RESET# from */
+#define SPI_NOR_SR_RST_MASK BIT(7)
@@ -412941,7 +483415,7 @@ index c425c7b..d8c3db8 100644
/*
* Note on opcode nomenclature: some opcodes have a format like
-@@ -40,27 +77,42 @@
+@@ -40,27 +79,42 @@
/* Flash opcodes. */
#define SPINOR_OP_WREN 0x06 /* Write enable */
#define SPINOR_OP_RDSR 0x05 /* Read status register */
@@ -412990,7 +483464,7 @@ index c425c7b..d8c3db8 100644
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
/* Used for SST flashes only. */
-@@ -73,12 +125,20 @@
+@@ -73,12 +127,20 @@
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
/* Used for Spansion flashes only. */
@@ -413011,7 +483485,7 @@ index c425c7b..d8c3db8 100644
/* Status Register bits. */
#define SR_WIP BIT(0) /* Write in progress */
#define SR_WEL BIT(1) /* Write enable latch */
-@@ -90,8 +150,9 @@
+@@ -90,8 +152,9 @@
#define SR_SRWD BIT(7) /* SR write protect */
#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
@@ -413022,15 +483496,11 @@ index c425c7b..d8c3db8 100644
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
/* Flag Status Register bits */
-@@ -100,11 +161,108 @@
+@@ -99,12 +162,109 @@
+
/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
-
--enum read_mode {
-- SPI_NOR_NORMAL = 0,
-- SPI_NOR_FAST,
-- SPI_NOR_DUAL,
-- SPI_NOR_QUAD,
++#define QUAD_EN_ISSI BIT(6)
+/* Status Register bits. */
+#define SR_QUAD_EN_XTX BIT(1)
+
@@ -413058,7 +483528,12 @@ index c425c7b..d8c3db8 100644
+ u32 rd_modes; /* supported SPI modes for (Fast) Read */
+ u32 wr_modes; /* supported SPI modes for Page Program */
+};
-+
+
+-enum read_mode {
+- SPI_NOR_NORMAL = 0,
+- SPI_NOR_FAST,
+- SPI_NOR_DUAL,
+- SPI_NOR_QUAD,
+struct spi_nor_read_op {
+ u8 num_mode_clocks;
+ u8 num_wait_states;
@@ -413136,7 +483611,7 @@ index c425c7b..d8c3db8 100644
};
#define SPI_NOR_MAX_CMD_SIZE 8
-@@ -121,20 +279,26 @@ enum spi_nor_option_flags {
+@@ -121,20 +281,26 @@ enum spi_nor_option_flags {
SNOR_F_HAS_SR_TB = BIT(1),
};
@@ -413164,7 +483639,7 @@ index c425c7b..d8c3db8 100644
* @cmd_buf: used by the write_reg
* @prepare: [OPTIONAL] do some preparations for the
* read/write/erase/lock/unlock operations
-@@ -157,13 +321,16 @@ struct spi_nor {
+@@ -157,13 +323,16 @@ struct spi_nor {
struct mtd_info mtd;
struct mutex lock;
struct device *dev;
@@ -413182,7 +483657,7 @@ index c425c7b..d8c3db8 100644
bool sst_write_second;
u32 flags;
u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
-@@ -183,6 +350,12 @@ struct spi_nor {
+@@ -183,6 +352,12 @@ struct spi_nor {
int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
@@ -413195,7 +483670,7 @@ index c425c7b..d8c3db8 100644
void *priv;
};
-@@ -201,7 +374,7 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
+@@ -201,7 +376,7 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
* spi_nor_scan() - scan the SPI NOR
* @nor: the spi_nor structure
* @name: the chip type name
@@ -413204,7 +483679,7 @@ index c425c7b..d8c3db8 100644
*
* The drivers can use this fuction to scan the SPI NOR.
* In the scanning, it will try to get all the necessary information to
-@@ -211,6 +384,12 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
+@@ -211,6 +386,12 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
*
* Return: 0 for success, others for failure.
*/
@@ -413220,7 +483695,7 @@ index c425c7b..d8c3db8 100644
#endif
diff --git a/include/linux/nospec.h b/include/linux/nospec.h
new file mode 100644
-index 0000000..eb3420a
+index 0000000..7a2c5be
--- /dev/null
+++ b/include/linux/nospec.h
@@ -0,0 +1,72 @@
@@ -413256,7 +483731,7 @@ index 0000000..eb3420a
+ * @index and @size are less than LONG_MAX.
+ */
+ if (WARN_ONCE(index > LONG_MAX || size > LONG_MAX,
-+ "array_index_nospec() limited to range of [0, LONG_MAX]\n"))
++ "array_index_nospec() limited to range of [0, LONG_MAX]\n"))
+ return 0;
+
+ /*
@@ -413755,7 +484230,7 @@ index 50144a3..8f348e8 100644
lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o
diff --git a/lib/lzma/LzFind.c b/lib/lzma/LzFind.c
new file mode 100644
-index 0000000..e3ecb05
+index 0000000..e0ff2ce
--- /dev/null
+++ b/lib/lzma/LzFind.c
@@ -0,0 +1,761 @@
@@ -414226,7 +484701,7 @@ index 0000000..e3ecb05
+static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }
+
+#define GET_MATCHES_HEADER2(minLen, ret_op) \
-+ UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \
++ UInt32 lenLimit; UInt32 hashValue = 0; const Byte *cur; UInt32 curMatch; \
+ lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \
+ cur = p->buffer;
+
@@ -414266,7 +484741,7 @@ index 0000000..e3ecb05
+
+static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+{
-+ UInt32 hash2Value, delta2, maxLen, offset;
++ UInt32 hash2Value = 0, delta2, maxLen, offset;
+ GET_MATCHES_HEADER(3)
+
+ HASH3_CALC;
@@ -414299,7 +484774,7 @@ index 0000000..e3ecb05
+
+static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+{
-+ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;
++ UInt32 hash2Value = 0, hash3Value = 0, delta2, delta3, maxLen, offset;
+ GET_MATCHES_HEADER(4)
+
+ HASH4_CALC;
@@ -414346,7 +484821,7 @@ index 0000000..e3ecb05
+
+static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+{
-+ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;
++ UInt32 hash2Value = 0, hash3Value = 0, delta2, delta3, maxLen, offset;
+ GET_MATCHES_HEADER(4)
+
+ HASH4_CALC;
@@ -414435,7 +484910,7 @@ index 0000000..e3ecb05
+{
+ do
+ {
-+ UInt32 hash2Value;
++ UInt32 hash2Value = 0;
+ SKIP_HEADER(3)
+ HASH3_CALC;
+ curMatch = p->hash[kFix3HashSize + hashValue];
@@ -414450,7 +484925,7 @@ index 0000000..e3ecb05
+{
+ do
+ {
-+ UInt32 hash2Value, hash3Value;
++ UInt32 hash2Value = 0, hash3Value = 0;
+ SKIP_HEADER(4)
+ HASH4_CALC;
+ curMatch = p->hash[kFix4HashSize + hashValue];
@@ -414466,7 +484941,7 @@ index 0000000..e3ecb05
+{
+ do
+ {
-+ UInt32 hash2Value, hash3Value;
++ UInt32 hash2Value = 0, hash3Value = 0;
+ SKIP_HEADER(4)
+ HASH4_CALC;
+ curMatch = p->hash[kFix4HashSize + hashValue];
@@ -414522,7 +484997,7 @@ index 0000000..e3ecb05
+}
diff --git a/lib/lzma/LzmaDec.c b/lib/lzma/LzmaDec.c
new file mode 100644
-index 0000000..2036761
+index 0000000..f9676a4
--- /dev/null
+++ b/lib/lzma/LzmaDec.c
@@ -0,0 +1,999 @@
@@ -414669,7 +485144,7 @@ index 0000000..2036761
+ Byte *dic = p->dic;
+ SizeT dicBufSize = p->dicBufSize;
+ SizeT dicPos = p->dicPos;
-+
++
+ UInt32 processedPos = p->processedPos;
+ UInt32 checkDicSize = p->checkDicSize;
+ unsigned len = 0;
@@ -414852,7 +485327,7 @@ index 0000000..2036761
+ {
+ NORMALIZE
+ range >>= 1;
-+
++
+ {
+ UInt32 t;
+ code -= range;
@@ -415250,7 +485725,7 @@ index 0000000..2036761
+ SizeT inSize = *srcLen;
+ (*srcLen) = 0;
+ LzmaDec_WriteRem(p, dicLimit);
-+
++
+ *status = LZMA_STATUS_NOT_SPECIFIED;
+
+ while (p->remainLen != kMatchSpecLenStart)
@@ -415296,11 +485771,11 @@ index 0000000..2036761
+
+ if (p->needInitState)
+ LzmaDec_InitStateReal(p);
-+
++
+ if (p->tempBufSize == 0)
+ {
+ SizeT processed;
-+ const Byte *bufLimit;
++ const Byte *bufLimit = NULL;
+ if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)
+ {
+ int dummyRes = LzmaDec_TryDummy(p, src, inSize);
@@ -415427,12 +485902,12 @@ index 0000000..2036761
+{
+ UInt32 dicSize;
+ Byte d;
-+
++
+ if (size < LZMA_PROPS_SIZE)
+ return SZ_ERROR_UNSUPPORTED;
+ else
+ dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);
-+
++
+ if (dicSize < LZMA_DIC_MIN)
+ dicSize = LZMA_DIC_MIN;
+ p->dicSize = dicSize;
@@ -415514,7 +485989,7 @@ index 0000000..2036761
+ p.dicBufSize = outSize;
+
+ LzmaDec_Init(&p);
-+
++
+ *srcLen = inSize;
+ res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status);
+
@@ -415527,7 +486002,7 @@ index 0000000..2036761
+}
diff --git a/lib/lzma/LzmaEnc.c b/lib/lzma/LzmaEnc.c
new file mode 100644
-index 0000000..6dadf00
+index 0000000..66842df
--- /dev/null
+++ b/lib/lzma/LzmaEnc.c
@@ -0,0 +1,2271 @@
@@ -415645,7 +486120,7 @@ index 0000000..6dadf00
+ int c = 2, slotFast;
+ g_FastPos[0] = 0;
+ g_FastPos[1] = 1;
-+
++
+ for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++)
+ {
+ UInt32 k = (1 << ((slotFast >> 1) - 1));
@@ -415782,7 +486257,7 @@ index 0000000..6dadf00
+ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];
+ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];
+ CLzmaProb posAlignEncoder[1 << kNumAlignBits];
-+
++
+ CLenPriceEnc lenEnc;
+ CLenPriceEnc repLenEnc;
+
@@ -415805,7 +486280,7 @@ index 0000000..6dadf00
+ #ifndef _7ZIP_ST
+ Byte pad[128];
+ #endif
-+
++
+ UInt32 optimumEndIndex;
+ UInt32 optimumCurrentIndex;
+
@@ -415813,7 +486288,7 @@ index 0000000..6dadf00
+ UInt32 numPairs;
+ UInt32 numAvail;
+ COptimal opt[kNumOpts];
-+
++
+ #ifndef LZMA_LOG_BSR
+ Byte g_FastPos[1 << kNumLogBits];
+ #endif
@@ -415847,14 +486322,14 @@ index 0000000..6dadf00
+ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];
+ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];
+ CLzmaProb posAlignEncoder[1 << kNumAlignBits];
-+
++
+ CLenPriceEnc lenEnc;
+ CLenPriceEnc repLenEnc;
+
+ unsigned lclp;
+
+ Bool fastMode;
-+
++
+ CRangeEnc rc;
+
+ Bool writeEndMark;
@@ -416445,10 +486920,10 @@ index 0000000..6dadf00
+ {
+ UInt32 posPrev = posMem;
+ UInt32 backCur = backMem;
-+
++
+ backMem = p->opt[posPrev].backPrev;
+ posMem = p->opt[posPrev].posPrev;
-+
++
+ p->opt[posPrev].backPrev = backCur;
+ p->opt[posPrev].posPrev = cur;
+ cur = posPrev;
@@ -416467,8 +486942,8 @@ index 0000000..6dadf00
+ UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur;
+ UInt32 matchPrice, repMatchPrice, normalMatchPrice;
+ UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS];
-+ UInt32 *matches;
-+ const Byte *data;
++ UInt32 *matches = NULL;
++ const Byte *data = NULL;
+ Byte curByte, matchByte;
+ if (p->optimumEndIndex != p->optimumCurrentIndex)
+ {
@@ -416479,7 +486954,7 @@ index 0000000..6dadf00
+ return lenRes;
+ }
+ p->optimumCurrentIndex = p->optimumEndIndex = 0;
-+
++
+ if (p->additionalOffset == 0)
+ mainLen = ReadMatchDistances(p, &numPairs);
+ else
@@ -416502,7 +486977,7 @@ index 0000000..6dadf00
+ for (i = 0; i < LZMA_NUM_REPS; i++)
+ {
+ UInt32 lenTest;
-+ const Byte *data2;
++ const Byte *data2 = NULL;
+ reps[i] = p->reps[i];
+ data2 = data - (reps[i] + 1);
+ if (data[0] != data2[0] || data[1] != data2[1])
@@ -416615,7 +487090,7 @@ index 0000000..6dadf00
+ offs += 2;
+ for (; ; len++)
+ {
-+ COptimal *opt;
++ COptimal *opt = NULL;
+ UInt32 distance = matches[offs + 1];
+
+ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN];
@@ -416663,9 +487138,9 @@ index 0000000..6dadf00
+ UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice;
+ Bool nextIsChar;
+ Byte curByte, matchByte;
-+ const Byte *data;
-+ COptimal *curOpt;
-+ COptimal *nextOpt;
++ const Byte *data = NULL;
++ COptimal *curOpt = NULL;
++ COptimal *nextOpt = NULL;
+
+ cur++;
+ if (cur == lenEnd)
@@ -416708,7 +487183,7 @@ index 0000000..6dadf00
+ else
+ {
+ UInt32 pos;
-+ const COptimal *prevOpt;
++ const COptimal *prevOpt = NULL;
+ if (curOpt->prev1IsChar && curOpt->prev2)
+ {
+ posPrev = curOpt->posPrev2;
@@ -416777,7 +487252,7 @@ index 0000000..6dadf00
+
+ matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]);
+ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]);
-+
++
+ if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0))
+ {
+ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState);
@@ -416839,7 +487314,7 @@ index 0000000..6dadf00
+ }
+ }
+ }
-+
++
+ startLen = 2; /* speed optimization */
+ {
+ UInt32 repIndex;
@@ -416870,10 +487345,10 @@ index 0000000..6dadf00
+ }
+ while (--lenTest >= 2);
+ lenTest = lenTestTemp;
-+
++
+ if (repIndex == 0)
+ startLen = lenTest + 1;
-+
++
+ /* if (_maxMode) */
+ {
+ UInt32 lenTest2 = lenTest + 1;
@@ -416897,7 +487372,7 @@ index 0000000..6dadf00
+ nextRepMatchPrice = curAndLenCharPrice +
+ GET_PRICE_1(p->isMatch[state2][posStateNext]) +
+ GET_PRICE_1(p->isRep[state2]);
-+
++
+ /* for (; lenTest2 >= 2; lenTest2--) */
+ {
+ UInt32 curAndLenPrice;
@@ -416947,12 +487422,12 @@ index 0000000..6dadf00
+ {
+ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN];
+ UInt32 lenToPosState = GetLenToPosState(lenTest);
-+ COptimal *opt;
++ COptimal *opt = NULL;
+ if (curBack < kNumFullDistances)
+ curAndLenPrice += p->distancesPrices[lenToPosState][curBack];
+ else
+ curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask];
-+
++
+ opt = &p->opt[cur + lenTest];
+ if (curAndLenPrice < opt->price)
+ {
@@ -416986,7 +487461,7 @@ index 0000000..6dadf00
+ nextRepMatchPrice = curAndLenCharPrice +
+ GET_PRICE_1(p->isMatch[state2][posStateNext]) +
+ GET_PRICE_1(p->isRep[state2]);
-+
++
+ /* for (; lenTest2 >= 2; lenTest2--) */
+ {
+ UInt32 offset = cur + lenTest + 1 + lenTest2;
@@ -417025,8 +487500,8 @@ index 0000000..6dadf00
+static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes)
+{
+ UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i;
-+ const Byte *data;
-+ const UInt32 *matches;
++ const Byte *data = NULL;
++ const UInt32 *matches = NULL;
+
+ if (p->additionalOffset == 0)
+ mainLen = ReadMatchDistances(p, &numPairs);
@@ -417098,7 +487573,7 @@ index 0000000..6dadf00
+ MovePos(p, repLen - 1);
+ return repLen;
+ }
-+
++
+ if (mainLen < 2 || numAvail <= 2)
+ return 1;
+
@@ -417112,7 +487587,7 @@ index 0000000..6dadf00
+ (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist)))
+ return 1;
+ }
-+
++
+ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;
+ for (i = 0; i < LZMA_NUM_REPS; i++)
+ {
@@ -417315,8 +487790,8 @@ index 0000000..6dadf00
+ if (len == 1 && pos == (UInt32)-1)
+ {
+ Byte curByte;
-+ CLzmaProb *probs;
-+ const Byte *data;
++ CLzmaProb *probs = NULL;
++ const Byte *data = NULL;
+
+ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0);
+ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;
@@ -417373,7 +487848,7 @@ index 0000000..6dadf00
+ pos -= LZMA_NUM_REPS;
+ GetPosSlot(pos, posSlot);
+ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot);
-+
++
+ if (posSlot >= kStartPosModelIndex)
+ {
+ UInt32 footerBits = ((posSlot >> 1) - 1);
@@ -417614,7 +488089,7 @@ index 0000000..6dadf00
+ if (p->mtMode)
+ MatchFinderMt_ReleaseStream(&p->matchFinderMt);
+ #else
-+ pp = pp;
++ (void)pp;
+ #endif
+}
+
@@ -417678,7 +488153,7 @@ index 0000000..6dadf00
+ p->rc.outStream = &outStream.funcTable;
+
+ res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize);
-+
++
+ *unpackSize = (UInt32)(p->nowPos64 - nowPos64);
+ *destLen -= outStream.rem;
+ if (outStream.overflow)
@@ -418111,3 +488586,46 @@ index 966dd39..5a4833a
# CONFIG_LOCALVERSION and LOCALVERSION (if set)
res="${res}${CONFIG_LOCALVERSION}${LOCALVERSION}"
+diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c
+index 4703cae..c3752dc 100644
+--- a/sound/usb/mixer.c
++++ b/sound/usb/mixer.c
+@@ -318,12 +318,15 @@ static int get_ctl_value_v1(struct usb_mixer_elem_info *cval, int request,
+
+ while (timeout-- > 0) {
+ idx = snd_usb_ctrl_intf(chip) | (cval->head.id << 8);
+- if (snd_usb_ctl_msg(chip->dev, usb_rcvctrlpipe(chip->dev, 0), request,
+- USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_IN,
+- validx, idx, buf, val_len) >= val_len) {
++ err = snd_usb_ctl_msg(chip->dev, usb_rcvctrlpipe(chip->dev, 0), request,
++ USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_IN,
++ validx, idx, buf, val_len);
++ if (err >= val_len) {
+ *value_ret = convert_signed_value(cval, snd_usb_combine_bytes(buf, val_len));
+ err = 0;
+ goto out;
++ } else if (err == -ETIMEDOUT) {
++ goto out;
+ }
+ }
+ usb_audio_dbg(chip,
+@@ -483,12 +486,15 @@ int snd_usb_mixer_set_ctl_value(struct usb_mixer_elem_info *cval,
+
+ while (timeout-- > 0) {
+ idx = snd_usb_ctrl_intf(chip) | (cval->head.id << 8);
+- if (snd_usb_ctl_msg(chip->dev,
+- usb_sndctrlpipe(chip->dev, 0), request,
+- USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_OUT,
+- validx, idx, buf, val_len) >= 0) {
++ err = snd_usb_ctl_msg(chip->dev,
++ usb_sndctrlpipe(chip->dev, 0), request,
++ USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_OUT,
++ validx, idx, buf, val_len);
++ if (err >= 0) {
+ err = 0;
+ goto out;
++ } else if (err == -ETIMEDOUT) {
++ goto out;
+ }
+ }
+ usb_audio_dbg(chip, "cannot set ctl value: req = %#x, wValue = %#x, wIndex = %#x, type = %d, data = %#x/%#x\n",