mirror of https://github.com/OpenIPC/firmware.git
				
				
				
			Fix different sensor configs (#301)
* Fix raw bitness for IMX415 in 60fps mode * Fix FullLinesStd for IMX335 sensorspull/302/head
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				|  | @ -65,4 +65,4 @@ Comp_mode    =0 ;Component mode (single-component or dual-component) | |||
| Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge) | ||||
|                 ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ | ||||
|                 ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ | ||||
| FullLinesStd=4500 | ||||
| FullLinesStd=1875 | ||||
|  |  | |||
|  | @ -65,7 +65,7 @@ Comp_mode    =0 ;Component mode (single-component or dual-component) | |||
| Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge) | ||||
|                 ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ | ||||
|                 ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ | ||||
| FullLinesStd=4500 | ||||
| FullLinesStd=1375 | ||||
| 
 | ||||
| [vi_chn] | ||||
| CapRect_Y=120 | ||||
|  |  | |||
|  | @ -65,4 +65,4 @@ Comp_mode    =0 ;Component mode (single-component or dual-component) | |||
| Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge) | ||||
|                 ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ | ||||
|                 ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ | ||||
| FullLinesStd=3300 | ||||
| FullLinesStd=1375 | ||||
|  |  | |||
|  | @ -3,25 +3,12 @@ Sensor_type   =stSnsImx415Obj           ;sensor name | |||
| Mode          = WDR_MODE_NONE | ||||
| DllFile   = /usr/lib/sensors/libsns_imx415.so            ;sensor lib path | ||||
| 
 | ||||
| 
 | ||||
| [mode] | ||||
| input_mode =0                           ;INPUT_MODE_MIPI = 0 | ||||
|                                         ;INPUT_MODE_SUBLVDS = 1 | ||||
|                                         ;INPUT_MODE_LVDS = 2 ...etc | ||||
| 
 | ||||
| raw_bitness = 10 | ||||
| input_mode = INPUT_MODE_MIPI | ||||
| 
 | ||||
| [mipi] | ||||
| ;----------only for mipi_dev--------- | ||||
| data_type = 1                        	;raw data type: 8/10/12/14 bit | ||||
|                                         ;DATA_TYPE_RAW_8BIT = 0, | ||||
|                                         ;DATA_TYPE_RAW_10BIT, | ||||
|                                         ;DATA_TYPE_RAW_12BIT, | ||||
|                                         ;DATA_TYPE_RAW_14BIT, | ||||
|                                         ;DATA_TYPE_RAW_16BIT, | ||||
|                                         ;DATA_TYPE_YUV420_8BIT_NORMAL, | ||||
|                                         ;DATA_TYPE_YUV420_8BIT_LEGACY, | ||||
|                                         ;DATA_TYPE_YUV422_8BIT, | ||||
| data_type = DATA_TYPE_RAW_12BIT | ||||
| lane_id = 0|1|2|3|-1|-1|-1|-1|          ;lane_id: -1 - disable | ||||
| 
 | ||||
| [isp_image] | ||||
|  | @ -109,6 +96,3 @@ CapSel       =2 ;Frame/field select. ONLY used in interlaced mode | |||
| PixFormat    =26;PIXEL_FORMAT_YVU_SEMIPLANAR_420 = 26 ...etc | ||||
| CompressMode =0 ;COMPRESS_MODE_NONE = 0 | ||||
|                 ;COMPRESS_MODE_SEG =1 ...etc | ||||
| 
 | ||||
| SrcFrameRate=-1 ;Source frame rate. -1: not controll | ||||
| FrameRate   =-1 ;Target frame rate. -1: not controll | ||||
|  |  | |||
|  | @ -64,4 +64,4 @@ Comp_mode    =0 ;Component mode (single-component or dual-component) | |||
| Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge) | ||||
|                 ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ | ||||
|                 ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ | ||||
| FullLinesStd=4500 | ||||
| FullLinesStd=1875 | ||||
|  |  | |||
|  | @ -64,7 +64,7 @@ Comp_mode    =0 ;Component mode (single-component or dual-component) | |||
| Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge) | ||||
|                 ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ | ||||
|                 ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ | ||||
| FullLinesStd=4500 | ||||
| FullLinesStd=1375 | ||||
| 
 | ||||
| [vi_chn] | ||||
| CapRect_Y=120 | ||||
|  |  | |||
|  | @ -64,4 +64,4 @@ Comp_mode    =0 ;Component mode (single-component or dual-component) | |||
| Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge) | ||||
|                 ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ | ||||
|                 ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ | ||||
| FullLinesStd=3300 | ||||
| FullLinesStd=1375 | ||||
|  |  | |||
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