diff --git a/.github/workflows/gk7205v200_images.yml b/.github/workflows/gk7205v200_images.yml index c8e80f93..cc4f88b5 100644 --- a/.github/workflows/gk7205v200_images.yml +++ b/.github/workflows/gk7205v200_images.yml @@ -1,6 +1,11 @@ name: OpenIPC for GK7205v200 on: + push: + branches: + - master + tags: + - "v*" workflow_dispatch: jobs: diff --git a/br-ext-chip-goke/board/gk7205v200/kernel/gk7205v200.generic.config b/br-ext-chip-goke/board/gk7205v200/kernel/gk7205v200.generic.config index b3d9867b..5219186e 100644 --- a/br-ext-chip-goke/board/gk7205v200/kernel/gk7205v200.generic.config +++ b/br-ext-chip-goke/board/gk7205v200/kernel/gk7205v200.generic.config @@ -990,9 +990,9 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 # # SCSI device support # -CONFIG_SCSI_MOD=y +CONFIG_SCSI_MOD=m # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y +CONFIG_SCSI=m CONFIG_SCSI_DMA=y CONFIG_SCSI_NETLINK=y # CONFIG_SCSI_MQ_DEFAULT is not set @@ -1001,10 +1001,10 @@ CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # -CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SD=m # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set @@ -1158,92 +1158,21 @@ CONFIG_INPUT=y # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVDEV=n # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_OMAP4 is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_CAP11XX is not set -# CONFIG_KEYBOARD_BCM is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_CYPRESS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_AD714X is not set -# CONFIG_INPUT_ATMEL_CAPTOUCH is not set -# CONFIG_INPUT_BMA150 is not set -# CONFIG_INPUT_E3X0_BUTTON is not set -# CONFIG_INPUT_MMA8450 is not set -# CONFIG_INPUT_MPU3050 is not set -# CONFIG_INPUT_GP2A is not set -# CONFIG_INPUT_GPIO_BEEPER is not set -# CONFIG_INPUT_GPIO_TILT_POLLED is not set -# CONFIG_INPUT_GPIO_DECODER is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_KXTJ9 is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_PCF8574 is not set -# CONFIG_INPUT_PWM_BEEPER is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_INPUT_ADXL34X is not set -# CONFIG_INPUT_CMA3000 is not set -# CONFIG_INPUT_DRV260X_HAPTICS is not set -# CONFIG_INPUT_DRV2665_HAPTICS is not set -# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_INPUT_UINPUT is not set # CONFIG_RMI4_CORE is not set # @@ -1650,33 +1579,33 @@ CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # -CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_CAMERA_SUPPORT is not set # CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set # CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set # CONFIG_MEDIA_RADIO_SUPPORT is not set # CONFIG_MEDIA_SDR_SUPPORT is not set # CONFIG_MEDIA_RC_SUPPORT is not set # CONFIG_MEDIA_CONTROLLER is not set -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_V4L2 is not set # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEOBUF2_CORE=y -CONFIG_VIDEOBUF2_MEMOPS=y -CONFIG_VIDEOBUF2_VMALLOC=y +# CONFIG_VIDEOBUF2_CORE is not set +# CONFIG_VIDEOBUF2_MEMOPS is not set +# CONFIG_VIDEOBUF2_VMALLOC is not set # CONFIG_TTPCI_EEPROM is not set # # Media drivers # -CONFIG_MEDIA_USB_SUPPORT=y +# CONFIG_MEDIA_USB_SUPPORT is not set # # Webcam devices # -CONFIG_USB_VIDEO_CLASS=y -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m +# CONFIG_USB_VIDEO_CLASS is not set +# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set +# CONFIG_USB_GSPCA is not set # CONFIG_USB_M5602 is not set # CONFIG_USB_STV06XX is not set # CONFIG_USB_GL860 is not set @@ -1748,7 +1677,7 @@ CONFIG_USB_GSPCA=m # # Media ancillary drivers (tuners, sensors, i2c, spi, frontends) # -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set # # Audio decoders, processors and mixers @@ -1812,10 +1741,10 @@ CONFIG_MEDIA_SUBDRV_AUTOSELECT=y # # Frame buffer Devices # -CONFIG_FB=y +# CONFIG_FB is not set # CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y +# CONFIG_FB_CMDLINE is not set +# CONFIG_FB_NOTIFY is not set # CONFIG_FB_DDC is not set # CONFIG_FB_BOOT_VESA_SUPPORT is not set # CONFIG_FB_CFB_FILLRECT is not set @@ -1903,7 +1832,7 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_LENOVO is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MAGICMOUSE is not set -CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_MULTITOUCH is not set # CONFIG_HID_NTRIG is not set @@ -1993,7 +1922,7 @@ CONFIG_USB_XHCI_PLATFORM=y # # also be needed; see USB_STORAGE Help for more info # -CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_REALTEK is not set # CONFIG_USB_STORAGE_DATAFAB is not set @@ -2100,14 +2029,14 @@ CONFIG_USB_F_RNDIS=m CONFIG_USB_F_MASS_STORAGE=m CONFIG_USB_CONFIGFS=m # CONFIG_USB_CONFIGFS_SERIAL is not set -CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_ACM=m # CONFIG_USB_CONFIGFS_OBEX is not set # CONFIG_USB_CONFIGFS_NCM is not set -CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM=m # CONFIG_USB_CONFIGFS_ECM_SUBSET is not set -CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_RNDIS=m # CONFIG_USB_CONFIGFS_EEM is not set -CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=m # CONFIG_USB_CONFIGFS_F_LB_SS is not set # CONFIG_USB_CONFIGFS_F_FS is not set # CONFIG_USB_CONFIGFS_F_HID is not set @@ -2412,8 +2341,8 @@ CONFIG_HAVE_ARM_SMCCC=y CONFIG_DCACHE_WORD_ACCESS=y # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -CONFIG_EXT4_FS=y -CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXT4_FS is not set +# CONFIG_EXT4_USE_FOR_EXT2 is not set # CONFIG_EXT4_FS_POSIX_ACL is not set # CONFIG_EXT4_FS_SECURITY is not set # CONFIG_EXT4_ENCRYPTION is not set @@ -2428,7 +2357,7 @@ CONFIG_FS_MBCACHE=y # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set -# CONFIG_F2FS_FS is not set +CONFIG_F2FS_FS=m CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -2443,7 +2372,7 @@ CONFIG_INOTIFY_USER=y # CONFIG_QUOTACTL is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# CONFIG_OVERLAY_FS is not set +CONFIG_OVERLAY_FS=y # # Caches @@ -2453,7 +2382,7 @@ CONFIG_INOTIFY_USER=y # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=y +# CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set # CONFIG_UDF_FS is not set @@ -2461,9 +2390,9 @@ CONFIG_ISO9660_FS=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y +CONFIG_FAT_FS=m +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set @@ -2493,19 +2422,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_YAFFS1=y -# CONFIG_YAFFS_9BYTE_TAGS is not set -# CONFIG_YAFFS_DOES_ECC is not set -CONFIG_YAFFS_YAFFS2=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set -# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set -# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set -# CONFIG_YAFFS_DISABLE_BACKGROUND is not set -# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set -CONFIG_YAFFS_XATTR=y +# CONFIG_YAFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y @@ -2518,14 +2435,11 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZMA is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set -CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_ATIME_SUPPORT is not set +# CONFIG_UBIFS_FS is not set +# # CONFIG_LOGFS is not set -CONFIG_CRAMFS=y -# CONFIG_SQUASHFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -2538,10 +2452,10 @@ CONFIG_CRAMFS=y # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y -CONFIG_NFS_V2=y +# CONFIG_NFS_V2 is not set CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4=y # CONFIG_NFS_SWAP is not set # CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y @@ -2562,44 +2476,44 @@ CONFIG_SUNRPC_GSS=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=y -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m +CONFIG_NLS_DEFAULT="utf8" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# # CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_MAC_ROMAN is not set # CONFIG_NLS_MAC_CELTIC is not set # CONFIG_NLS_MAC_CENTEURO is not set diff --git a/br-ext-chip-goke/board/gk7205v200/kernel/patches/00_gk7205v200_kernel-4.9.37_sdk-V100R001C00SPC020.patch b/br-ext-chip-goke/board/gk7205v200/kernel/patches/00_gk7205v200_kernel-4.9.37_sdk-V100R001C00SPC020.patch index 0f902adf..d10c6356 100644 --- a/br-ext-chip-goke/board/gk7205v200/kernel/patches/00_gk7205v200_kernel-4.9.37_sdk-V100R001C00SPC020.patch +++ b/br-ext-chip-goke/board/gk7205v200/kernel/patches/00_gk7205v200_kernel-4.9.37_sdk-V100R001C00SPC020.patch @@ -3250,326 +3250,6 @@ diff -urN linux-4.9.37/arch/arm/boot/dts/gk7605v100.dtsi linux-4.9.y/arch/arm/bo + }; + }; +}; -diff -urN linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h ---- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7202V300_CLOCK_H -+#define __DTS_GK7202V300_CLOCK_H -+ -+/* clk in GK7202V300 CRG */ -+/* fixed rate clocks */ -+#define GK7202V300_FIXED_100K 1 -+#define GK7202V300_FIXED_400K 2 -+#define GK7202V300_FIXED_3M 3 -+#define GK7202V300_FIXED_6M 4 -+#define GK7202V300_FIXED_12M 5 -+#define GK7202V300_FIXED_24M 6 -+#define GK7202V300_FIXED_25M 7 -+#define GK7202V300_FIXED_50M 8 -+#define GK7202V300_FIXED_83P3M 9 -+#define GK7202V300_FIXED_90M 10 -+#define GK7202V300_FIXED_100M 11 -+#define GK7202V300_FIXED_112M 12 -+#define GK7202V300_FIXED_125M 13 -+#define GK7202V300_FIXED_148P5M 14 -+#define GK7202V300_FIXED_150M 15 -+#define GK7202V300_FIXED_200M 16 -+#define GK7202V300_FIXED_250M 17 -+#define GK7202V300_FIXED_300M 18 -+#define GK7202V300_FIXED_324M 19 -+#define GK7202V300_FIXED_342M 20 -+#define GK7202V300_FIXED_375M 21 -+#define GK7202V300_FIXED_400M 22 -+#define GK7202V300_FIXED_448M 23 -+#define GK7202V300_FIXED_500M 24 -+#define GK7202V300_FIXED_540M 25 -+#define GK7202V300_FIXED_600M 26 -+#define GK7202V300_FIXED_750M 27 -+#define GK7202V300_FIXED_1000M 28 -+#define GK7202V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7202V300_SYSAXI_CLK 30 -+#define GK7202V300_SYSAPB_CLK 31 -+#define GK7202V300_FMC_MUX 32 -+#define GK7202V300_UART_MUX 33 -+#define GK7202V300_MMC0_MUX 34 -+#define GK7202V300_MMC1_MUX 35 -+#define GK7202V300_MMC2_MUX 36 -+#define GK7202V300_ETH_MUX 37 -+#define GK7202V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7202V300_UART0_CLK 40 -+#define GK7202V300_UART1_CLK 41 -+#define GK7202V300_UART2_CLK 42 -+#define GK7202V300_FMC_CLK 43 -+#define GK7202V300_ETH0_CLK 44 -+#define GK7202V300_EDMAC_AXICLK 45 -+#define GK7202V300_EDMAC_CLK 46 -+#define GK7202V300_SPI0_CLK 48 -+#define GK7202V300_SPI1_CLK 49 -+#define GK7202V300_MMC0_CLK 50 -+#define GK7202V300_MMC1_CLK 51 -+#define GK7202V300_MMC2_CLK 52 -+#define GK7202V300_I2C0_CLK 53 -+#define GK7202V300_I2C1_CLK 54 -+#define GK7202V300_I2C2_CLK 55 -+#define GK7202V300_USB2_BUS_CLK 81 -+#define GK7202V300_USB2_REF_CLK 82 -+#define GK7202V300_USB2_UTMI_CLK 83 -+#define GK7202V300_USB2_PHY_APB_CLK 84 -+#define GK7202V300_USB2_PHY_PLL_CLK 85 -+#define GK7202V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7202V300_NR_CLKS 256 -+#define GK7202V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7202V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h ---- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V200_CLOCK_H -+#define __DTS_GK7205V200_CLOCK_H -+ -+/* clk in GK7205V200 CRG */ -+/* fixed rate clocks */ -+#define GK7205V200_FIXED_100K 1 -+#define GK7205V200_FIXED_400K 2 -+#define GK7205V200_FIXED_3M 3 -+#define GK7205V200_FIXED_6M 4 -+#define GK7205V200_FIXED_12M 5 -+#define GK7205V200_FIXED_24M 6 -+#define GK7205V200_FIXED_25M 7 -+#define GK7205V200_FIXED_50M 8 -+#define GK7205V200_FIXED_83P3M 9 -+#define GK7205V200_FIXED_90M 10 -+#define GK7205V200_FIXED_100M 11 -+#define GK7205V200_FIXED_112M 12 -+#define GK7205V200_FIXED_125M 13 -+#define GK7205V200_FIXED_148P5M 14 -+#define GK7205V200_FIXED_150M 15 -+#define GK7205V200_FIXED_200M 16 -+#define GK7205V200_FIXED_250M 17 -+#define GK7205V200_FIXED_300M 18 -+#define GK7205V200_FIXED_324M 19 -+#define GK7205V200_FIXED_342M 20 -+#define GK7205V200_FIXED_375M 21 -+#define GK7205V200_FIXED_400M 22 -+#define GK7205V200_FIXED_448M 23 -+#define GK7205V200_FIXED_500M 24 -+#define GK7205V200_FIXED_540M 25 -+#define GK7205V200_FIXED_600M 26 -+#define GK7205V200_FIXED_750M 27 -+#define GK7205V200_FIXED_1000M 28 -+#define GK7205V200_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V200_SYSAXI_CLK 30 -+#define GK7205V200_SYSAPB_CLK 31 -+#define GK7205V200_FMC_MUX 32 -+#define GK7205V200_UART_MUX 33 -+#define GK7205V200_MMC0_MUX 34 -+#define GK7205V200_MMC1_MUX 35 -+#define GK7205V200_MMC2_MUX 36 -+#define GK7205V200_ETH_MUX 37 -+#define GK7205V200_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V200_UART0_CLK 40 -+#define GK7205V200_UART1_CLK 41 -+#define GK7205V200_UART2_CLK 42 -+#define GK7205V200_FMC_CLK 43 -+#define GK7205V200_ETH0_CLK 44 -+#define GK7205V200_EDMAC_AXICLK 45 -+#define GK7205V200_EDMAC_CLK 46 -+#define GK7205V200_SPI0_CLK 48 -+#define GK7205V200_SPI1_CLK 49 -+#define GK7205V200_MMC0_CLK 50 -+#define GK7205V200_MMC1_CLK 51 -+#define GK7205V200_MMC2_CLK 52 -+#define GK7205V200_I2C0_CLK 53 -+#define GK7205V200_I2C1_CLK 54 -+#define GK7205V200_I2C2_CLK 55 -+#define GK7205V200_USB2_BUS_CLK 81 -+#define GK7205V200_USB2_REF_CLK 82 -+#define GK7205V200_USB2_UTMI_CLK 83 -+#define GK7205V200_USB2_PHY_APB_CLK 84 -+#define GK7205V200_USB2_PHY_PLL_CLK 85 -+#define GK7205V200_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V200_NR_CLKS 256 -+#define GK7205V200_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V200_CLOCK_H */ -diff -urN linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h ---- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V300_CLOCK_H -+#define __DTS_GK7205V300_CLOCK_H -+ -+/* clk in GK7205V300 CRG */ -+/* fixed rate clocks */ -+#define GK7205V300_FIXED_100K 1 -+#define GK7205V300_FIXED_400K 2 -+#define GK7205V300_FIXED_3M 3 -+#define GK7205V300_FIXED_6M 4 -+#define GK7205V300_FIXED_12M 5 -+#define GK7205V300_FIXED_24M 6 -+#define GK7205V300_FIXED_25M 7 -+#define GK7205V300_FIXED_50M 8 -+#define GK7205V300_FIXED_83P3M 9 -+#define GK7205V300_FIXED_90M 10 -+#define GK7205V300_FIXED_100M 11 -+#define GK7205V300_FIXED_112M 12 -+#define GK7205V300_FIXED_125M 13 -+#define GK7205V300_FIXED_148P5M 14 -+#define GK7205V300_FIXED_150M 15 -+#define GK7205V300_FIXED_200M 16 -+#define GK7205V300_FIXED_250M 17 -+#define GK7205V300_FIXED_300M 18 -+#define GK7205V300_FIXED_324M 19 -+#define GK7205V300_FIXED_342M 20 -+#define GK7205V300_FIXED_375M 21 -+#define GK7205V300_FIXED_400M 22 -+#define GK7205V300_FIXED_448M 23 -+#define GK7205V300_FIXED_500M 24 -+#define GK7205V300_FIXED_540M 25 -+#define GK7205V300_FIXED_600M 26 -+#define GK7205V300_FIXED_750M 27 -+#define GK7205V300_FIXED_1000M 28 -+#define GK7205V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V300_SYSAXI_CLK 30 -+#define GK7205V300_SYSAPB_CLK 31 -+#define GK7205V300_FMC_MUX 32 -+#define GK7205V300_UART_MUX 33 -+#define GK7205V300_MMC0_MUX 34 -+#define GK7205V300_MMC1_MUX 35 -+#define GK7205V300_MMC2_MUX 36 -+#define GK7205V300_ETH_MUX 37 -+#define GK7205V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V300_UART0_CLK 40 -+#define GK7205V300_UART1_CLK 41 -+#define GK7205V300_UART2_CLK 42 -+#define GK7205V300_FMC_CLK 43 -+#define GK7205V300_ETH0_CLK 44 -+#define GK7205V300_EDMAC_AXICLK 45 -+#define GK7205V300_EDMAC_CLK 46 -+#define GK7205V300_SPI0_CLK 48 -+#define GK7205V300_SPI1_CLK 49 -+#define GK7205V300_MMC0_CLK 50 -+#define GK7205V300_MMC1_CLK 51 -+#define GK7205V300_MMC2_CLK 52 -+#define GK7205V300_I2C0_CLK 53 -+#define GK7205V300_I2C1_CLK 54 -+#define GK7205V300_I2C2_CLK 55 -+#define GK7205V300_USB2_BUS_CLK 81 -+#define GK7205V300_USB2_REF_CLK 82 -+#define GK7205V300_USB2_UTMI_CLK 83 -+#define GK7205V300_USB2_PHY_APB_CLK 84 -+#define GK7205V300_USB2_PHY_PLL_CLK 85 -+#define GK7205V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V300_NR_CLKS 256 -+#define GK7205V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h ---- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7605V100_CLOCK_H -+#define __DTS_GK7605V100_CLOCK_H -+ -+/* clk in GK7605V100 CRG */ -+/* fixed rate clocks */ -+#define GK7605V100_FIXED_100K 1 -+#define GK7605V100_FIXED_400K 2 -+#define GK7605V100_FIXED_3M 3 -+#define GK7605V100_FIXED_6M 4 -+#define GK7605V100_FIXED_12M 5 -+#define GK7605V100_FIXED_24M 6 -+#define GK7605V100_FIXED_25M 7 -+#define GK7605V100_FIXED_50M 8 -+#define GK7605V100_FIXED_83P3M 9 -+#define GK7605V100_FIXED_90M 10 -+#define GK7605V100_FIXED_100M 11 -+#define GK7605V100_FIXED_112M 12 -+#define GK7605V100_FIXED_125M 13 -+#define GK7605V100_FIXED_148P5M 14 -+#define GK7605V100_FIXED_150M 15 -+#define GK7605V100_FIXED_200M 16 -+#define GK7605V100_FIXED_250M 17 -+#define GK7605V100_FIXED_300M 18 -+#define GK7605V100_FIXED_324M 19 -+#define GK7605V100_FIXED_342M 20 -+#define GK7605V100_FIXED_375M 21 -+#define GK7605V100_FIXED_400M 22 -+#define GK7605V100_FIXED_448M 23 -+#define GK7605V100_FIXED_500M 24 -+#define GK7605V100_FIXED_540M 25 -+#define GK7605V100_FIXED_600M 26 -+#define GK7605V100_FIXED_750M 27 -+#define GK7605V100_FIXED_1000M 28 -+#define GK7605V100_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7605V100_SYSAXI_CLK 30 -+#define GK7605V100_SYSAPB_CLK 31 -+#define GK7605V100_FMC_MUX 32 -+#define GK7605V100_UART_MUX 33 -+#define GK7605V100_MMC0_MUX 34 -+#define GK7605V100_MMC1_MUX 35 -+#define GK7605V100_MMC2_MUX 36 -+#define GK7605V100_ETH_MUX 37 -+#define GK7605V100_USB2_MUX 80 -+/* gate clocks */ -+#define GK7605V100_UART0_CLK 40 -+#define GK7605V100_UART1_CLK 41 -+#define GK7605V100_UART2_CLK 42 -+#define GK7605V100_FMC_CLK 43 -+#define GK7605V100_ETH0_CLK 44 -+#define GK7605V100_EDMAC_AXICLK 45 -+#define GK7605V100_EDMAC_CLK 46 -+#define GK7605V100_SPI0_CLK 48 -+#define GK7605V100_SPI1_CLK 49 -+#define GK7605V100_MMC0_CLK 50 -+#define GK7605V100_MMC1_CLK 51 -+#define GK7605V100_MMC2_CLK 52 -+#define GK7605V100_I2C0_CLK 53 -+#define GK7605V100_I2C1_CLK 54 -+#define GK7605V100_I2C2_CLK 55 -+#define GK7605V100_USB2_BUS_CLK 81 -+#define GK7605V100_USB2_REF_CLK 82 -+#define GK7605V100_USB2_UTMI_CLK 83 -+#define GK7605V100_USB2_PHY_APB_CLK 84 -+#define GK7605V100_USB2_PHY_PLL_CLK 85 -+#define GK7605V100_USB2_PHY_XO_CLK 86 -+ -+#define GK7605V100_NR_CLKS 256 -+#define GK7605V100_NR_RSTS 256 -+ -+#endif /* __DTS_GK7605V100_CLOCK_H */ diff -urN linux-4.9.37/arch/arm/boot/dts/Makefile linux-4.9.y/arch/arm/boot/dts/Makefile --- linux-4.9.37/arch/arm/boot/dts/Makefile 2017-07-12 16:42:41.000000000 +0300 +++ linux-4.9.y/arch/arm/boot/dts/Makefile 2021-06-07 13:01:32.000000000 +0300 @@ -31664,326 +31344,6 @@ diff -urN linux-4.9.37/arch/arm64/boot/dts/.gitignore linux-4.9.y/arch/arm64/boo +++ linux-4.9.y/arch/arm64/boot/dts/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -1 +0,0 @@ -*.dtb -diff -urN linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h ---- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7202V300_CLOCK_H -+#define __DTS_GK7202V300_CLOCK_H -+ -+/* clk in GK7202V300 CRG */ -+/* fixed rate clocks */ -+#define GK7202V300_FIXED_100K 1 -+#define GK7202V300_FIXED_400K 2 -+#define GK7202V300_FIXED_3M 3 -+#define GK7202V300_FIXED_6M 4 -+#define GK7202V300_FIXED_12M 5 -+#define GK7202V300_FIXED_24M 6 -+#define GK7202V300_FIXED_25M 7 -+#define GK7202V300_FIXED_50M 8 -+#define GK7202V300_FIXED_83P3M 9 -+#define GK7202V300_FIXED_90M 10 -+#define GK7202V300_FIXED_100M 11 -+#define GK7202V300_FIXED_112M 12 -+#define GK7202V300_FIXED_125M 13 -+#define GK7202V300_FIXED_148P5M 14 -+#define GK7202V300_FIXED_150M 15 -+#define GK7202V300_FIXED_200M 16 -+#define GK7202V300_FIXED_250M 17 -+#define GK7202V300_FIXED_300M 18 -+#define GK7202V300_FIXED_324M 19 -+#define GK7202V300_FIXED_342M 20 -+#define GK7202V300_FIXED_375M 21 -+#define GK7202V300_FIXED_400M 22 -+#define GK7202V300_FIXED_448M 23 -+#define GK7202V300_FIXED_500M 24 -+#define GK7202V300_FIXED_540M 25 -+#define GK7202V300_FIXED_600M 26 -+#define GK7202V300_FIXED_750M 27 -+#define GK7202V300_FIXED_1000M 28 -+#define GK7202V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7202V300_SYSAXI_CLK 30 -+#define GK7202V300_SYSAPB_CLK 31 -+#define GK7202V300_FMC_MUX 32 -+#define GK7202V300_UART_MUX 33 -+#define GK7202V300_MMC0_MUX 34 -+#define GK7202V300_MMC1_MUX 35 -+#define GK7202V300_MMC2_MUX 36 -+#define GK7202V300_ETH_MUX 37 -+#define GK7202V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7202V300_UART0_CLK 40 -+#define GK7202V300_UART1_CLK 41 -+#define GK7202V300_UART2_CLK 42 -+#define GK7202V300_FMC_CLK 43 -+#define GK7202V300_ETH0_CLK 44 -+#define GK7202V300_EDMAC_AXICLK 45 -+#define GK7202V300_EDMAC_CLK 46 -+#define GK7202V300_SPI0_CLK 48 -+#define GK7202V300_SPI1_CLK 49 -+#define GK7202V300_MMC0_CLK 50 -+#define GK7202V300_MMC1_CLK 51 -+#define GK7202V300_MMC2_CLK 52 -+#define GK7202V300_I2C0_CLK 53 -+#define GK7202V300_I2C1_CLK 54 -+#define GK7202V300_I2C2_CLK 55 -+#define GK7202V300_USB2_BUS_CLK 81 -+#define GK7202V300_USB2_REF_CLK 82 -+#define GK7202V300_USB2_UTMI_CLK 83 -+#define GK7202V300_USB2_PHY_APB_CLK 84 -+#define GK7202V300_USB2_PHY_PLL_CLK 85 -+#define GK7202V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7202V300_NR_CLKS 256 -+#define GK7202V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7202V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h ---- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V200_CLOCK_H -+#define __DTS_GK7205V200_CLOCK_H -+ -+/* clk in GK7205V200 CRG */ -+/* fixed rate clocks */ -+#define GK7205V200_FIXED_100K 1 -+#define GK7205V200_FIXED_400K 2 -+#define GK7205V200_FIXED_3M 3 -+#define GK7205V200_FIXED_6M 4 -+#define GK7205V200_FIXED_12M 5 -+#define GK7205V200_FIXED_24M 6 -+#define GK7205V200_FIXED_25M 7 -+#define GK7205V200_FIXED_50M 8 -+#define GK7205V200_FIXED_83P3M 9 -+#define GK7205V200_FIXED_90M 10 -+#define GK7205V200_FIXED_100M 11 -+#define GK7205V200_FIXED_112M 12 -+#define GK7205V200_FIXED_125M 13 -+#define GK7205V200_FIXED_148P5M 14 -+#define GK7205V200_FIXED_150M 15 -+#define GK7205V200_FIXED_200M 16 -+#define GK7205V200_FIXED_250M 17 -+#define GK7205V200_FIXED_300M 18 -+#define GK7205V200_FIXED_324M 19 -+#define GK7205V200_FIXED_342M 20 -+#define GK7205V200_FIXED_375M 21 -+#define GK7205V200_FIXED_400M 22 -+#define GK7205V200_FIXED_448M 23 -+#define GK7205V200_FIXED_500M 24 -+#define GK7205V200_FIXED_540M 25 -+#define GK7205V200_FIXED_600M 26 -+#define GK7205V200_FIXED_750M 27 -+#define GK7205V200_FIXED_1000M 28 -+#define GK7205V200_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V200_SYSAXI_CLK 30 -+#define GK7205V200_SYSAPB_CLK 31 -+#define GK7205V200_FMC_MUX 32 -+#define GK7205V200_UART_MUX 33 -+#define GK7205V200_MMC0_MUX 34 -+#define GK7205V200_MMC1_MUX 35 -+#define GK7205V200_MMC2_MUX 36 -+#define GK7205V200_ETH_MUX 37 -+#define GK7205V200_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V200_UART0_CLK 40 -+#define GK7205V200_UART1_CLK 41 -+#define GK7205V200_UART2_CLK 42 -+#define GK7205V200_FMC_CLK 43 -+#define GK7205V200_ETH0_CLK 44 -+#define GK7205V200_EDMAC_AXICLK 45 -+#define GK7205V200_EDMAC_CLK 46 -+#define GK7205V200_SPI0_CLK 48 -+#define GK7205V200_SPI1_CLK 49 -+#define GK7205V200_MMC0_CLK 50 -+#define GK7205V200_MMC1_CLK 51 -+#define GK7205V200_MMC2_CLK 52 -+#define GK7205V200_I2C0_CLK 53 -+#define GK7205V200_I2C1_CLK 54 -+#define GK7205V200_I2C2_CLK 55 -+#define GK7205V200_USB2_BUS_CLK 81 -+#define GK7205V200_USB2_REF_CLK 82 -+#define GK7205V200_USB2_UTMI_CLK 83 -+#define GK7205V200_USB2_PHY_APB_CLK 84 -+#define GK7205V200_USB2_PHY_PLL_CLK 85 -+#define GK7205V200_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V200_NR_CLKS 256 -+#define GK7205V200_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V200_CLOCK_H */ -diff -urN linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h ---- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V300_CLOCK_H -+#define __DTS_GK7205V300_CLOCK_H -+ -+/* clk in GK7205V300 CRG */ -+/* fixed rate clocks */ -+#define GK7205V300_FIXED_100K 1 -+#define GK7205V300_FIXED_400K 2 -+#define GK7205V300_FIXED_3M 3 -+#define GK7205V300_FIXED_6M 4 -+#define GK7205V300_FIXED_12M 5 -+#define GK7205V300_FIXED_24M 6 -+#define GK7205V300_FIXED_25M 7 -+#define GK7205V300_FIXED_50M 8 -+#define GK7205V300_FIXED_83P3M 9 -+#define GK7205V300_FIXED_90M 10 -+#define GK7205V300_FIXED_100M 11 -+#define GK7205V300_FIXED_112M 12 -+#define GK7205V300_FIXED_125M 13 -+#define GK7205V300_FIXED_148P5M 14 -+#define GK7205V300_FIXED_150M 15 -+#define GK7205V300_FIXED_200M 16 -+#define GK7205V300_FIXED_250M 17 -+#define GK7205V300_FIXED_300M 18 -+#define GK7205V300_FIXED_324M 19 -+#define GK7205V300_FIXED_342M 20 -+#define GK7205V300_FIXED_375M 21 -+#define GK7205V300_FIXED_400M 22 -+#define GK7205V300_FIXED_448M 23 -+#define GK7205V300_FIXED_500M 24 -+#define GK7205V300_FIXED_540M 25 -+#define GK7205V300_FIXED_600M 26 -+#define GK7205V300_FIXED_750M 27 -+#define GK7205V300_FIXED_1000M 28 -+#define GK7205V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V300_SYSAXI_CLK 30 -+#define GK7205V300_SYSAPB_CLK 31 -+#define GK7205V300_FMC_MUX 32 -+#define GK7205V300_UART_MUX 33 -+#define GK7205V300_MMC0_MUX 34 -+#define GK7205V300_MMC1_MUX 35 -+#define GK7205V300_MMC2_MUX 36 -+#define GK7205V300_ETH_MUX 37 -+#define GK7205V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V300_UART0_CLK 40 -+#define GK7205V300_UART1_CLK 41 -+#define GK7205V300_UART2_CLK 42 -+#define GK7205V300_FMC_CLK 43 -+#define GK7205V300_ETH0_CLK 44 -+#define GK7205V300_EDMAC_AXICLK 45 -+#define GK7205V300_EDMAC_CLK 46 -+#define GK7205V300_SPI0_CLK 48 -+#define GK7205V300_SPI1_CLK 49 -+#define GK7205V300_MMC0_CLK 50 -+#define GK7205V300_MMC1_CLK 51 -+#define GK7205V300_MMC2_CLK 52 -+#define GK7205V300_I2C0_CLK 53 -+#define GK7205V300_I2C1_CLK 54 -+#define GK7205V300_I2C2_CLK 55 -+#define GK7205V300_USB2_BUS_CLK 81 -+#define GK7205V300_USB2_REF_CLK 82 -+#define GK7205V300_USB2_UTMI_CLK 83 -+#define GK7205V300_USB2_PHY_APB_CLK 84 -+#define GK7205V300_USB2_PHY_PLL_CLK 85 -+#define GK7205V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V300_NR_CLKS 256 -+#define GK7205V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h ---- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7605V100_CLOCK_H -+#define __DTS_GK7605V100_CLOCK_H -+ -+/* clk in GK7605V100 CRG */ -+/* fixed rate clocks */ -+#define GK7605V100_FIXED_100K 1 -+#define GK7605V100_FIXED_400K 2 -+#define GK7605V100_FIXED_3M 3 -+#define GK7605V100_FIXED_6M 4 -+#define GK7605V100_FIXED_12M 5 -+#define GK7605V100_FIXED_24M 6 -+#define GK7605V100_FIXED_25M 7 -+#define GK7605V100_FIXED_50M 8 -+#define GK7605V100_FIXED_83P3M 9 -+#define GK7605V100_FIXED_90M 10 -+#define GK7605V100_FIXED_100M 11 -+#define GK7605V100_FIXED_112M 12 -+#define GK7605V100_FIXED_125M 13 -+#define GK7605V100_FIXED_148P5M 14 -+#define GK7605V100_FIXED_150M 15 -+#define GK7605V100_FIXED_200M 16 -+#define GK7605V100_FIXED_250M 17 -+#define GK7605V100_FIXED_300M 18 -+#define GK7605V100_FIXED_324M 19 -+#define GK7605V100_FIXED_342M 20 -+#define GK7605V100_FIXED_375M 21 -+#define GK7605V100_FIXED_400M 22 -+#define GK7605V100_FIXED_448M 23 -+#define GK7605V100_FIXED_500M 24 -+#define GK7605V100_FIXED_540M 25 -+#define GK7605V100_FIXED_600M 26 -+#define GK7605V100_FIXED_750M 27 -+#define GK7605V100_FIXED_1000M 28 -+#define GK7605V100_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7605V100_SYSAXI_CLK 30 -+#define GK7605V100_SYSAPB_CLK 31 -+#define GK7605V100_FMC_MUX 32 -+#define GK7605V100_UART_MUX 33 -+#define GK7605V100_MMC0_MUX 34 -+#define GK7605V100_MMC1_MUX 35 -+#define GK7605V100_MMC2_MUX 36 -+#define GK7605V100_ETH_MUX 37 -+#define GK7605V100_USB2_MUX 80 -+/* gate clocks */ -+#define GK7605V100_UART0_CLK 40 -+#define GK7605V100_UART1_CLK 41 -+#define GK7605V100_UART2_CLK 42 -+#define GK7605V100_FMC_CLK 43 -+#define GK7605V100_ETH0_CLK 44 -+#define GK7605V100_EDMAC_AXICLK 45 -+#define GK7605V100_EDMAC_CLK 46 -+#define GK7605V100_SPI0_CLK 48 -+#define GK7605V100_SPI1_CLK 49 -+#define GK7605V100_MMC0_CLK 50 -+#define GK7605V100_MMC1_CLK 51 -+#define GK7605V100_MMC2_CLK 52 -+#define GK7605V100_I2C0_CLK 53 -+#define GK7605V100_I2C1_CLK 54 -+#define GK7605V100_I2C2_CLK 55 -+#define GK7605V100_USB2_BUS_CLK 81 -+#define GK7605V100_USB2_REF_CLK 82 -+#define GK7605V100_USB2_UTMI_CLK 83 -+#define GK7605V100_USB2_PHY_APB_CLK 84 -+#define GK7605V100_USB2_PHY_PLL_CLK 85 -+#define GK7605V100_USB2_PHY_XO_CLK 86 -+ -+#define GK7605V100_NR_CLKS 256 -+#define GK7605V100_NR_RSTS 256 -+ -+#endif /* __DTS_GK7605V100_CLOCK_H */ diff -urN linux-4.9.37/arch/arm64/boot/.gitignore linux-4.9.y/arch/arm64/boot/.gitignore --- linux-4.9.37/arch/arm64/boot/.gitignore 2017-07-12 16:42:41.000000000 +0300 +++ linux-4.9.y/arch/arm64/boot/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -32026,326 +31386,6 @@ diff -urN linux-4.9.37/arch/blackfin/kernel/.gitignore linux-4.9.y/arch/blackfin +++ linux-4.9.y/arch/blackfin/kernel/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -1 +0,0 @@ -vmlinux.lds -diff -urN linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h ---- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7202V300_CLOCK_H -+#define __DTS_GK7202V300_CLOCK_H -+ -+/* clk in GK7202V300 CRG */ -+/* fixed rate clocks */ -+#define GK7202V300_FIXED_100K 1 -+#define GK7202V300_FIXED_400K 2 -+#define GK7202V300_FIXED_3M 3 -+#define GK7202V300_FIXED_6M 4 -+#define GK7202V300_FIXED_12M 5 -+#define GK7202V300_FIXED_24M 6 -+#define GK7202V300_FIXED_25M 7 -+#define GK7202V300_FIXED_50M 8 -+#define GK7202V300_FIXED_83P3M 9 -+#define GK7202V300_FIXED_90M 10 -+#define GK7202V300_FIXED_100M 11 -+#define GK7202V300_FIXED_112M 12 -+#define GK7202V300_FIXED_125M 13 -+#define GK7202V300_FIXED_148P5M 14 -+#define GK7202V300_FIXED_150M 15 -+#define GK7202V300_FIXED_200M 16 -+#define GK7202V300_FIXED_250M 17 -+#define GK7202V300_FIXED_300M 18 -+#define GK7202V300_FIXED_324M 19 -+#define GK7202V300_FIXED_342M 20 -+#define GK7202V300_FIXED_375M 21 -+#define GK7202V300_FIXED_400M 22 -+#define GK7202V300_FIXED_448M 23 -+#define GK7202V300_FIXED_500M 24 -+#define GK7202V300_FIXED_540M 25 -+#define GK7202V300_FIXED_600M 26 -+#define GK7202V300_FIXED_750M 27 -+#define GK7202V300_FIXED_1000M 28 -+#define GK7202V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7202V300_SYSAXI_CLK 30 -+#define GK7202V300_SYSAPB_CLK 31 -+#define GK7202V300_FMC_MUX 32 -+#define GK7202V300_UART_MUX 33 -+#define GK7202V300_MMC0_MUX 34 -+#define GK7202V300_MMC1_MUX 35 -+#define GK7202V300_MMC2_MUX 36 -+#define GK7202V300_ETH_MUX 37 -+#define GK7202V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7202V300_UART0_CLK 40 -+#define GK7202V300_UART1_CLK 41 -+#define GK7202V300_UART2_CLK 42 -+#define GK7202V300_FMC_CLK 43 -+#define GK7202V300_ETH0_CLK 44 -+#define GK7202V300_EDMAC_AXICLK 45 -+#define GK7202V300_EDMAC_CLK 46 -+#define GK7202V300_SPI0_CLK 48 -+#define GK7202V300_SPI1_CLK 49 -+#define GK7202V300_MMC0_CLK 50 -+#define GK7202V300_MMC1_CLK 51 -+#define GK7202V300_MMC2_CLK 52 -+#define GK7202V300_I2C0_CLK 53 -+#define GK7202V300_I2C1_CLK 54 -+#define GK7202V300_I2C2_CLK 55 -+#define GK7202V300_USB2_BUS_CLK 81 -+#define GK7202V300_USB2_REF_CLK 82 -+#define GK7202V300_USB2_UTMI_CLK 83 -+#define GK7202V300_USB2_PHY_APB_CLK 84 -+#define GK7202V300_USB2_PHY_PLL_CLK 85 -+#define GK7202V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7202V300_NR_CLKS 256 -+#define GK7202V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7202V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h ---- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V200_CLOCK_H -+#define __DTS_GK7205V200_CLOCK_H -+ -+/* clk in GK7205V200 CRG */ -+/* fixed rate clocks */ -+#define GK7205V200_FIXED_100K 1 -+#define GK7205V200_FIXED_400K 2 -+#define GK7205V200_FIXED_3M 3 -+#define GK7205V200_FIXED_6M 4 -+#define GK7205V200_FIXED_12M 5 -+#define GK7205V200_FIXED_24M 6 -+#define GK7205V200_FIXED_25M 7 -+#define GK7205V200_FIXED_50M 8 -+#define GK7205V200_FIXED_83P3M 9 -+#define GK7205V200_FIXED_90M 10 -+#define GK7205V200_FIXED_100M 11 -+#define GK7205V200_FIXED_112M 12 -+#define GK7205V200_FIXED_125M 13 -+#define GK7205V200_FIXED_148P5M 14 -+#define GK7205V200_FIXED_150M 15 -+#define GK7205V200_FIXED_200M 16 -+#define GK7205V200_FIXED_250M 17 -+#define GK7205V200_FIXED_300M 18 -+#define GK7205V200_FIXED_324M 19 -+#define GK7205V200_FIXED_342M 20 -+#define GK7205V200_FIXED_375M 21 -+#define GK7205V200_FIXED_400M 22 -+#define GK7205V200_FIXED_448M 23 -+#define GK7205V200_FIXED_500M 24 -+#define GK7205V200_FIXED_540M 25 -+#define GK7205V200_FIXED_600M 26 -+#define GK7205V200_FIXED_750M 27 -+#define GK7205V200_FIXED_1000M 28 -+#define GK7205V200_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V200_SYSAXI_CLK 30 -+#define GK7205V200_SYSAPB_CLK 31 -+#define GK7205V200_FMC_MUX 32 -+#define GK7205V200_UART_MUX 33 -+#define GK7205V200_MMC0_MUX 34 -+#define GK7205V200_MMC1_MUX 35 -+#define GK7205V200_MMC2_MUX 36 -+#define GK7205V200_ETH_MUX 37 -+#define GK7205V200_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V200_UART0_CLK 40 -+#define GK7205V200_UART1_CLK 41 -+#define GK7205V200_UART2_CLK 42 -+#define GK7205V200_FMC_CLK 43 -+#define GK7205V200_ETH0_CLK 44 -+#define GK7205V200_EDMAC_AXICLK 45 -+#define GK7205V200_EDMAC_CLK 46 -+#define GK7205V200_SPI0_CLK 48 -+#define GK7205V200_SPI1_CLK 49 -+#define GK7205V200_MMC0_CLK 50 -+#define GK7205V200_MMC1_CLK 51 -+#define GK7205V200_MMC2_CLK 52 -+#define GK7205V200_I2C0_CLK 53 -+#define GK7205V200_I2C1_CLK 54 -+#define GK7205V200_I2C2_CLK 55 -+#define GK7205V200_USB2_BUS_CLK 81 -+#define GK7205V200_USB2_REF_CLK 82 -+#define GK7205V200_USB2_UTMI_CLK 83 -+#define GK7205V200_USB2_PHY_APB_CLK 84 -+#define GK7205V200_USB2_PHY_PLL_CLK 85 -+#define GK7205V200_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V200_NR_CLKS 256 -+#define GK7205V200_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V200_CLOCK_H */ -diff -urN linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h ---- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V300_CLOCK_H -+#define __DTS_GK7205V300_CLOCK_H -+ -+/* clk in GK7205V300 CRG */ -+/* fixed rate clocks */ -+#define GK7205V300_FIXED_100K 1 -+#define GK7205V300_FIXED_400K 2 -+#define GK7205V300_FIXED_3M 3 -+#define GK7205V300_FIXED_6M 4 -+#define GK7205V300_FIXED_12M 5 -+#define GK7205V300_FIXED_24M 6 -+#define GK7205V300_FIXED_25M 7 -+#define GK7205V300_FIXED_50M 8 -+#define GK7205V300_FIXED_83P3M 9 -+#define GK7205V300_FIXED_90M 10 -+#define GK7205V300_FIXED_100M 11 -+#define GK7205V300_FIXED_112M 12 -+#define GK7205V300_FIXED_125M 13 -+#define GK7205V300_FIXED_148P5M 14 -+#define GK7205V300_FIXED_150M 15 -+#define GK7205V300_FIXED_200M 16 -+#define GK7205V300_FIXED_250M 17 -+#define GK7205V300_FIXED_300M 18 -+#define GK7205V300_FIXED_324M 19 -+#define GK7205V300_FIXED_342M 20 -+#define GK7205V300_FIXED_375M 21 -+#define GK7205V300_FIXED_400M 22 -+#define GK7205V300_FIXED_448M 23 -+#define GK7205V300_FIXED_500M 24 -+#define GK7205V300_FIXED_540M 25 -+#define GK7205V300_FIXED_600M 26 -+#define GK7205V300_FIXED_750M 27 -+#define GK7205V300_FIXED_1000M 28 -+#define GK7205V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V300_SYSAXI_CLK 30 -+#define GK7205V300_SYSAPB_CLK 31 -+#define GK7205V300_FMC_MUX 32 -+#define GK7205V300_UART_MUX 33 -+#define GK7205V300_MMC0_MUX 34 -+#define GK7205V300_MMC1_MUX 35 -+#define GK7205V300_MMC2_MUX 36 -+#define GK7205V300_ETH_MUX 37 -+#define GK7205V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V300_UART0_CLK 40 -+#define GK7205V300_UART1_CLK 41 -+#define GK7205V300_UART2_CLK 42 -+#define GK7205V300_FMC_CLK 43 -+#define GK7205V300_ETH0_CLK 44 -+#define GK7205V300_EDMAC_AXICLK 45 -+#define GK7205V300_EDMAC_CLK 46 -+#define GK7205V300_SPI0_CLK 48 -+#define GK7205V300_SPI1_CLK 49 -+#define GK7205V300_MMC0_CLK 50 -+#define GK7205V300_MMC1_CLK 51 -+#define GK7205V300_MMC2_CLK 52 -+#define GK7205V300_I2C0_CLK 53 -+#define GK7205V300_I2C1_CLK 54 -+#define GK7205V300_I2C2_CLK 55 -+#define GK7205V300_USB2_BUS_CLK 81 -+#define GK7205V300_USB2_REF_CLK 82 -+#define GK7205V300_USB2_UTMI_CLK 83 -+#define GK7205V300_USB2_PHY_APB_CLK 84 -+#define GK7205V300_USB2_PHY_PLL_CLK 85 -+#define GK7205V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V300_NR_CLKS 256 -+#define GK7205V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h ---- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7605V100_CLOCK_H -+#define __DTS_GK7605V100_CLOCK_H -+ -+/* clk in GK7605V100 CRG */ -+/* fixed rate clocks */ -+#define GK7605V100_FIXED_100K 1 -+#define GK7605V100_FIXED_400K 2 -+#define GK7605V100_FIXED_3M 3 -+#define GK7605V100_FIXED_6M 4 -+#define GK7605V100_FIXED_12M 5 -+#define GK7605V100_FIXED_24M 6 -+#define GK7605V100_FIXED_25M 7 -+#define GK7605V100_FIXED_50M 8 -+#define GK7605V100_FIXED_83P3M 9 -+#define GK7605V100_FIXED_90M 10 -+#define GK7605V100_FIXED_100M 11 -+#define GK7605V100_FIXED_112M 12 -+#define GK7605V100_FIXED_125M 13 -+#define GK7605V100_FIXED_148P5M 14 -+#define GK7605V100_FIXED_150M 15 -+#define GK7605V100_FIXED_200M 16 -+#define GK7605V100_FIXED_250M 17 -+#define GK7605V100_FIXED_300M 18 -+#define GK7605V100_FIXED_324M 19 -+#define GK7605V100_FIXED_342M 20 -+#define GK7605V100_FIXED_375M 21 -+#define GK7605V100_FIXED_400M 22 -+#define GK7605V100_FIXED_448M 23 -+#define GK7605V100_FIXED_500M 24 -+#define GK7605V100_FIXED_540M 25 -+#define GK7605V100_FIXED_600M 26 -+#define GK7605V100_FIXED_750M 27 -+#define GK7605V100_FIXED_1000M 28 -+#define GK7605V100_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7605V100_SYSAXI_CLK 30 -+#define GK7605V100_SYSAPB_CLK 31 -+#define GK7605V100_FMC_MUX 32 -+#define GK7605V100_UART_MUX 33 -+#define GK7605V100_MMC0_MUX 34 -+#define GK7605V100_MMC1_MUX 35 -+#define GK7605V100_MMC2_MUX 36 -+#define GK7605V100_ETH_MUX 37 -+#define GK7605V100_USB2_MUX 80 -+/* gate clocks */ -+#define GK7605V100_UART0_CLK 40 -+#define GK7605V100_UART1_CLK 41 -+#define GK7605V100_UART2_CLK 42 -+#define GK7605V100_FMC_CLK 43 -+#define GK7605V100_ETH0_CLK 44 -+#define GK7605V100_EDMAC_AXICLK 45 -+#define GK7605V100_EDMAC_CLK 46 -+#define GK7605V100_SPI0_CLK 48 -+#define GK7605V100_SPI1_CLK 49 -+#define GK7605V100_MMC0_CLK 50 -+#define GK7605V100_MMC1_CLK 51 -+#define GK7605V100_MMC2_CLK 52 -+#define GK7605V100_I2C0_CLK 53 -+#define GK7605V100_I2C1_CLK 54 -+#define GK7605V100_I2C2_CLK 55 -+#define GK7605V100_USB2_BUS_CLK 81 -+#define GK7605V100_USB2_REF_CLK 82 -+#define GK7605V100_USB2_UTMI_CLK 83 -+#define GK7605V100_USB2_PHY_APB_CLK 84 -+#define GK7605V100_USB2_PHY_PLL_CLK 85 -+#define GK7605V100_USB2_PHY_XO_CLK 86 -+ -+#define GK7605V100_NR_CLKS 256 -+#define GK7605V100_NR_RSTS 256 -+ -+#endif /* __DTS_GK7605V100_CLOCK_H */ diff -urN linux-4.9.37/arch/cris/boot/.gitignore linux-4.9.y/arch/cris/boot/.gitignore --- linux-4.9.37/arch/cris/boot/.gitignore 2017-07-12 16:42:41.000000000 +0300 +++ linux-4.9.y/arch/cris/boot/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -32374,326 +31414,6 @@ diff -urN linux-4.9.37/arch/m68k/kernel/.gitignore linux-4.9.y/arch/m68k/kernel/ +++ linux-4.9.y/arch/m68k/kernel/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -1 +0,0 @@ -vmlinux.lds -diff -urN linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h ---- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7202V300_CLOCK_H -+#define __DTS_GK7202V300_CLOCK_H -+ -+/* clk in GK7202V300 CRG */ -+/* fixed rate clocks */ -+#define GK7202V300_FIXED_100K 1 -+#define GK7202V300_FIXED_400K 2 -+#define GK7202V300_FIXED_3M 3 -+#define GK7202V300_FIXED_6M 4 -+#define GK7202V300_FIXED_12M 5 -+#define GK7202V300_FIXED_24M 6 -+#define GK7202V300_FIXED_25M 7 -+#define GK7202V300_FIXED_50M 8 -+#define GK7202V300_FIXED_83P3M 9 -+#define GK7202V300_FIXED_90M 10 -+#define GK7202V300_FIXED_100M 11 -+#define GK7202V300_FIXED_112M 12 -+#define GK7202V300_FIXED_125M 13 -+#define GK7202V300_FIXED_148P5M 14 -+#define GK7202V300_FIXED_150M 15 -+#define GK7202V300_FIXED_200M 16 -+#define GK7202V300_FIXED_250M 17 -+#define GK7202V300_FIXED_300M 18 -+#define GK7202V300_FIXED_324M 19 -+#define GK7202V300_FIXED_342M 20 -+#define GK7202V300_FIXED_375M 21 -+#define GK7202V300_FIXED_400M 22 -+#define GK7202V300_FIXED_448M 23 -+#define GK7202V300_FIXED_500M 24 -+#define GK7202V300_FIXED_540M 25 -+#define GK7202V300_FIXED_600M 26 -+#define GK7202V300_FIXED_750M 27 -+#define GK7202V300_FIXED_1000M 28 -+#define GK7202V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7202V300_SYSAXI_CLK 30 -+#define GK7202V300_SYSAPB_CLK 31 -+#define GK7202V300_FMC_MUX 32 -+#define GK7202V300_UART_MUX 33 -+#define GK7202V300_MMC0_MUX 34 -+#define GK7202V300_MMC1_MUX 35 -+#define GK7202V300_MMC2_MUX 36 -+#define GK7202V300_ETH_MUX 37 -+#define GK7202V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7202V300_UART0_CLK 40 -+#define GK7202V300_UART1_CLK 41 -+#define GK7202V300_UART2_CLK 42 -+#define GK7202V300_FMC_CLK 43 -+#define GK7202V300_ETH0_CLK 44 -+#define GK7202V300_EDMAC_AXICLK 45 -+#define GK7202V300_EDMAC_CLK 46 -+#define GK7202V300_SPI0_CLK 48 -+#define GK7202V300_SPI1_CLK 49 -+#define GK7202V300_MMC0_CLK 50 -+#define GK7202V300_MMC1_CLK 51 -+#define GK7202V300_MMC2_CLK 52 -+#define GK7202V300_I2C0_CLK 53 -+#define GK7202V300_I2C1_CLK 54 -+#define GK7202V300_I2C2_CLK 55 -+#define GK7202V300_USB2_BUS_CLK 81 -+#define GK7202V300_USB2_REF_CLK 82 -+#define GK7202V300_USB2_UTMI_CLK 83 -+#define GK7202V300_USB2_PHY_APB_CLK 84 -+#define GK7202V300_USB2_PHY_PLL_CLK 85 -+#define GK7202V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7202V300_NR_CLKS 256 -+#define GK7202V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7202V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h ---- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V200_CLOCK_H -+#define __DTS_GK7205V200_CLOCK_H -+ -+/* clk in GK7205V200 CRG */ -+/* fixed rate clocks */ -+#define GK7205V200_FIXED_100K 1 -+#define GK7205V200_FIXED_400K 2 -+#define GK7205V200_FIXED_3M 3 -+#define GK7205V200_FIXED_6M 4 -+#define GK7205V200_FIXED_12M 5 -+#define GK7205V200_FIXED_24M 6 -+#define GK7205V200_FIXED_25M 7 -+#define GK7205V200_FIXED_50M 8 -+#define GK7205V200_FIXED_83P3M 9 -+#define GK7205V200_FIXED_90M 10 -+#define GK7205V200_FIXED_100M 11 -+#define GK7205V200_FIXED_112M 12 -+#define GK7205V200_FIXED_125M 13 -+#define GK7205V200_FIXED_148P5M 14 -+#define GK7205V200_FIXED_150M 15 -+#define GK7205V200_FIXED_200M 16 -+#define GK7205V200_FIXED_250M 17 -+#define GK7205V200_FIXED_300M 18 -+#define GK7205V200_FIXED_324M 19 -+#define GK7205V200_FIXED_342M 20 -+#define GK7205V200_FIXED_375M 21 -+#define GK7205V200_FIXED_400M 22 -+#define GK7205V200_FIXED_448M 23 -+#define GK7205V200_FIXED_500M 24 -+#define GK7205V200_FIXED_540M 25 -+#define GK7205V200_FIXED_600M 26 -+#define GK7205V200_FIXED_750M 27 -+#define GK7205V200_FIXED_1000M 28 -+#define GK7205V200_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V200_SYSAXI_CLK 30 -+#define GK7205V200_SYSAPB_CLK 31 -+#define GK7205V200_FMC_MUX 32 -+#define GK7205V200_UART_MUX 33 -+#define GK7205V200_MMC0_MUX 34 -+#define GK7205V200_MMC1_MUX 35 -+#define GK7205V200_MMC2_MUX 36 -+#define GK7205V200_ETH_MUX 37 -+#define GK7205V200_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V200_UART0_CLK 40 -+#define GK7205V200_UART1_CLK 41 -+#define GK7205V200_UART2_CLK 42 -+#define GK7205V200_FMC_CLK 43 -+#define GK7205V200_ETH0_CLK 44 -+#define GK7205V200_EDMAC_AXICLK 45 -+#define GK7205V200_EDMAC_CLK 46 -+#define GK7205V200_SPI0_CLK 48 -+#define GK7205V200_SPI1_CLK 49 -+#define GK7205V200_MMC0_CLK 50 -+#define GK7205V200_MMC1_CLK 51 -+#define GK7205V200_MMC2_CLK 52 -+#define GK7205V200_I2C0_CLK 53 -+#define GK7205V200_I2C1_CLK 54 -+#define GK7205V200_I2C2_CLK 55 -+#define GK7205V200_USB2_BUS_CLK 81 -+#define GK7205V200_USB2_REF_CLK 82 -+#define GK7205V200_USB2_UTMI_CLK 83 -+#define GK7205V200_USB2_PHY_APB_CLK 84 -+#define GK7205V200_USB2_PHY_PLL_CLK 85 -+#define GK7205V200_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V200_NR_CLKS 256 -+#define GK7205V200_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V200_CLOCK_H */ -diff -urN linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h ---- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V300_CLOCK_H -+#define __DTS_GK7205V300_CLOCK_H -+ -+/* clk in GK7205V300 CRG */ -+/* fixed rate clocks */ -+#define GK7205V300_FIXED_100K 1 -+#define GK7205V300_FIXED_400K 2 -+#define GK7205V300_FIXED_3M 3 -+#define GK7205V300_FIXED_6M 4 -+#define GK7205V300_FIXED_12M 5 -+#define GK7205V300_FIXED_24M 6 -+#define GK7205V300_FIXED_25M 7 -+#define GK7205V300_FIXED_50M 8 -+#define GK7205V300_FIXED_83P3M 9 -+#define GK7205V300_FIXED_90M 10 -+#define GK7205V300_FIXED_100M 11 -+#define GK7205V300_FIXED_112M 12 -+#define GK7205V300_FIXED_125M 13 -+#define GK7205V300_FIXED_148P5M 14 -+#define GK7205V300_FIXED_150M 15 -+#define GK7205V300_FIXED_200M 16 -+#define GK7205V300_FIXED_250M 17 -+#define GK7205V300_FIXED_300M 18 -+#define GK7205V300_FIXED_324M 19 -+#define GK7205V300_FIXED_342M 20 -+#define GK7205V300_FIXED_375M 21 -+#define GK7205V300_FIXED_400M 22 -+#define GK7205V300_FIXED_448M 23 -+#define GK7205V300_FIXED_500M 24 -+#define GK7205V300_FIXED_540M 25 -+#define GK7205V300_FIXED_600M 26 -+#define GK7205V300_FIXED_750M 27 -+#define GK7205V300_FIXED_1000M 28 -+#define GK7205V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V300_SYSAXI_CLK 30 -+#define GK7205V300_SYSAPB_CLK 31 -+#define GK7205V300_FMC_MUX 32 -+#define GK7205V300_UART_MUX 33 -+#define GK7205V300_MMC0_MUX 34 -+#define GK7205V300_MMC1_MUX 35 -+#define GK7205V300_MMC2_MUX 36 -+#define GK7205V300_ETH_MUX 37 -+#define GK7205V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V300_UART0_CLK 40 -+#define GK7205V300_UART1_CLK 41 -+#define GK7205V300_UART2_CLK 42 -+#define GK7205V300_FMC_CLK 43 -+#define GK7205V300_ETH0_CLK 44 -+#define GK7205V300_EDMAC_AXICLK 45 -+#define GK7205V300_EDMAC_CLK 46 -+#define GK7205V300_SPI0_CLK 48 -+#define GK7205V300_SPI1_CLK 49 -+#define GK7205V300_MMC0_CLK 50 -+#define GK7205V300_MMC1_CLK 51 -+#define GK7205V300_MMC2_CLK 52 -+#define GK7205V300_I2C0_CLK 53 -+#define GK7205V300_I2C1_CLK 54 -+#define GK7205V300_I2C2_CLK 55 -+#define GK7205V300_USB2_BUS_CLK 81 -+#define GK7205V300_USB2_REF_CLK 82 -+#define GK7205V300_USB2_UTMI_CLK 83 -+#define GK7205V300_USB2_PHY_APB_CLK 84 -+#define GK7205V300_USB2_PHY_PLL_CLK 85 -+#define GK7205V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V300_NR_CLKS 256 -+#define GK7205V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h ---- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7605V100_CLOCK_H -+#define __DTS_GK7605V100_CLOCK_H -+ -+/* clk in GK7605V100 CRG */ -+/* fixed rate clocks */ -+#define GK7605V100_FIXED_100K 1 -+#define GK7605V100_FIXED_400K 2 -+#define GK7605V100_FIXED_3M 3 -+#define GK7605V100_FIXED_6M 4 -+#define GK7605V100_FIXED_12M 5 -+#define GK7605V100_FIXED_24M 6 -+#define GK7605V100_FIXED_25M 7 -+#define GK7605V100_FIXED_50M 8 -+#define GK7605V100_FIXED_83P3M 9 -+#define GK7605V100_FIXED_90M 10 -+#define GK7605V100_FIXED_100M 11 -+#define GK7605V100_FIXED_112M 12 -+#define GK7605V100_FIXED_125M 13 -+#define GK7605V100_FIXED_148P5M 14 -+#define GK7605V100_FIXED_150M 15 -+#define GK7605V100_FIXED_200M 16 -+#define GK7605V100_FIXED_250M 17 -+#define GK7605V100_FIXED_300M 18 -+#define GK7605V100_FIXED_324M 19 -+#define GK7605V100_FIXED_342M 20 -+#define GK7605V100_FIXED_375M 21 -+#define GK7605V100_FIXED_400M 22 -+#define GK7605V100_FIXED_448M 23 -+#define GK7605V100_FIXED_500M 24 -+#define GK7605V100_FIXED_540M 25 -+#define GK7605V100_FIXED_600M 26 -+#define GK7605V100_FIXED_750M 27 -+#define GK7605V100_FIXED_1000M 28 -+#define GK7605V100_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7605V100_SYSAXI_CLK 30 -+#define GK7605V100_SYSAPB_CLK 31 -+#define GK7605V100_FMC_MUX 32 -+#define GK7605V100_UART_MUX 33 -+#define GK7605V100_MMC0_MUX 34 -+#define GK7605V100_MMC1_MUX 35 -+#define GK7605V100_MMC2_MUX 36 -+#define GK7605V100_ETH_MUX 37 -+#define GK7605V100_USB2_MUX 80 -+/* gate clocks */ -+#define GK7605V100_UART0_CLK 40 -+#define GK7605V100_UART1_CLK 41 -+#define GK7605V100_UART2_CLK 42 -+#define GK7605V100_FMC_CLK 43 -+#define GK7605V100_ETH0_CLK 44 -+#define GK7605V100_EDMAC_AXICLK 45 -+#define GK7605V100_EDMAC_CLK 46 -+#define GK7605V100_SPI0_CLK 48 -+#define GK7605V100_SPI1_CLK 49 -+#define GK7605V100_MMC0_CLK 50 -+#define GK7605V100_MMC1_CLK 51 -+#define GK7605V100_MMC2_CLK 52 -+#define GK7605V100_I2C0_CLK 53 -+#define GK7605V100_I2C1_CLK 54 -+#define GK7605V100_I2C2_CLK 55 -+#define GK7605V100_USB2_BUS_CLK 81 -+#define GK7605V100_USB2_REF_CLK 82 -+#define GK7605V100_USB2_UTMI_CLK 83 -+#define GK7605V100_USB2_PHY_APB_CLK 84 -+#define GK7605V100_USB2_PHY_PLL_CLK 85 -+#define GK7605V100_USB2_PHY_XO_CLK 86 -+ -+#define GK7605V100_NR_CLKS 256 -+#define GK7605V100_NR_RSTS 256 -+ -+#endif /* __DTS_GK7605V100_CLOCK_H */ diff -urN linux-4.9.37/arch/metag/boot/.gitignore linux-4.9.y/arch/metag/boot/.gitignore --- linux-4.9.37/arch/metag/boot/.gitignore 2017-07-12 16:42:41.000000000 +0300 +++ linux-4.9.y/arch/metag/boot/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -32719,326 +31439,6 @@ diff -urN linux-4.9.37/arch/microblaze/kernel/.gitignore linux-4.9.y/arch/microb +++ linux-4.9.y/arch/microblaze/kernel/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -1 +0,0 @@ -vmlinux.lds -diff -urN linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h ---- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7202V300_CLOCK_H -+#define __DTS_GK7202V300_CLOCK_H -+ -+/* clk in GK7202V300 CRG */ -+/* fixed rate clocks */ -+#define GK7202V300_FIXED_100K 1 -+#define GK7202V300_FIXED_400K 2 -+#define GK7202V300_FIXED_3M 3 -+#define GK7202V300_FIXED_6M 4 -+#define GK7202V300_FIXED_12M 5 -+#define GK7202V300_FIXED_24M 6 -+#define GK7202V300_FIXED_25M 7 -+#define GK7202V300_FIXED_50M 8 -+#define GK7202V300_FIXED_83P3M 9 -+#define GK7202V300_FIXED_90M 10 -+#define GK7202V300_FIXED_100M 11 -+#define GK7202V300_FIXED_112M 12 -+#define GK7202V300_FIXED_125M 13 -+#define GK7202V300_FIXED_148P5M 14 -+#define GK7202V300_FIXED_150M 15 -+#define GK7202V300_FIXED_200M 16 -+#define GK7202V300_FIXED_250M 17 -+#define GK7202V300_FIXED_300M 18 -+#define GK7202V300_FIXED_324M 19 -+#define GK7202V300_FIXED_342M 20 -+#define GK7202V300_FIXED_375M 21 -+#define GK7202V300_FIXED_400M 22 -+#define GK7202V300_FIXED_448M 23 -+#define GK7202V300_FIXED_500M 24 -+#define GK7202V300_FIXED_540M 25 -+#define GK7202V300_FIXED_600M 26 -+#define GK7202V300_FIXED_750M 27 -+#define GK7202V300_FIXED_1000M 28 -+#define GK7202V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7202V300_SYSAXI_CLK 30 -+#define GK7202V300_SYSAPB_CLK 31 -+#define GK7202V300_FMC_MUX 32 -+#define GK7202V300_UART_MUX 33 -+#define GK7202V300_MMC0_MUX 34 -+#define GK7202V300_MMC1_MUX 35 -+#define GK7202V300_MMC2_MUX 36 -+#define GK7202V300_ETH_MUX 37 -+#define GK7202V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7202V300_UART0_CLK 40 -+#define GK7202V300_UART1_CLK 41 -+#define GK7202V300_UART2_CLK 42 -+#define GK7202V300_FMC_CLK 43 -+#define GK7202V300_ETH0_CLK 44 -+#define GK7202V300_EDMAC_AXICLK 45 -+#define GK7202V300_EDMAC_CLK 46 -+#define GK7202V300_SPI0_CLK 48 -+#define GK7202V300_SPI1_CLK 49 -+#define GK7202V300_MMC0_CLK 50 -+#define GK7202V300_MMC1_CLK 51 -+#define GK7202V300_MMC2_CLK 52 -+#define GK7202V300_I2C0_CLK 53 -+#define GK7202V300_I2C1_CLK 54 -+#define GK7202V300_I2C2_CLK 55 -+#define GK7202V300_USB2_BUS_CLK 81 -+#define GK7202V300_USB2_REF_CLK 82 -+#define GK7202V300_USB2_UTMI_CLK 83 -+#define GK7202V300_USB2_PHY_APB_CLK 84 -+#define GK7202V300_USB2_PHY_PLL_CLK 85 -+#define GK7202V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7202V300_NR_CLKS 256 -+#define GK7202V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7202V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h ---- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V200_CLOCK_H -+#define __DTS_GK7205V200_CLOCK_H -+ -+/* clk in GK7205V200 CRG */ -+/* fixed rate clocks */ -+#define GK7205V200_FIXED_100K 1 -+#define GK7205V200_FIXED_400K 2 -+#define GK7205V200_FIXED_3M 3 -+#define GK7205V200_FIXED_6M 4 -+#define GK7205V200_FIXED_12M 5 -+#define GK7205V200_FIXED_24M 6 -+#define GK7205V200_FIXED_25M 7 -+#define GK7205V200_FIXED_50M 8 -+#define GK7205V200_FIXED_83P3M 9 -+#define GK7205V200_FIXED_90M 10 -+#define GK7205V200_FIXED_100M 11 -+#define GK7205V200_FIXED_112M 12 -+#define GK7205V200_FIXED_125M 13 -+#define GK7205V200_FIXED_148P5M 14 -+#define GK7205V200_FIXED_150M 15 -+#define GK7205V200_FIXED_200M 16 -+#define GK7205V200_FIXED_250M 17 -+#define GK7205V200_FIXED_300M 18 -+#define GK7205V200_FIXED_324M 19 -+#define GK7205V200_FIXED_342M 20 -+#define GK7205V200_FIXED_375M 21 -+#define GK7205V200_FIXED_400M 22 -+#define GK7205V200_FIXED_448M 23 -+#define GK7205V200_FIXED_500M 24 -+#define GK7205V200_FIXED_540M 25 -+#define GK7205V200_FIXED_600M 26 -+#define GK7205V200_FIXED_750M 27 -+#define GK7205V200_FIXED_1000M 28 -+#define GK7205V200_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V200_SYSAXI_CLK 30 -+#define GK7205V200_SYSAPB_CLK 31 -+#define GK7205V200_FMC_MUX 32 -+#define GK7205V200_UART_MUX 33 -+#define GK7205V200_MMC0_MUX 34 -+#define GK7205V200_MMC1_MUX 35 -+#define GK7205V200_MMC2_MUX 36 -+#define GK7205V200_ETH_MUX 37 -+#define GK7205V200_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V200_UART0_CLK 40 -+#define GK7205V200_UART1_CLK 41 -+#define GK7205V200_UART2_CLK 42 -+#define GK7205V200_FMC_CLK 43 -+#define GK7205V200_ETH0_CLK 44 -+#define GK7205V200_EDMAC_AXICLK 45 -+#define GK7205V200_EDMAC_CLK 46 -+#define GK7205V200_SPI0_CLK 48 -+#define GK7205V200_SPI1_CLK 49 -+#define GK7205V200_MMC0_CLK 50 -+#define GK7205V200_MMC1_CLK 51 -+#define GK7205V200_MMC2_CLK 52 -+#define GK7205V200_I2C0_CLK 53 -+#define GK7205V200_I2C1_CLK 54 -+#define GK7205V200_I2C2_CLK 55 -+#define GK7205V200_USB2_BUS_CLK 81 -+#define GK7205V200_USB2_REF_CLK 82 -+#define GK7205V200_USB2_UTMI_CLK 83 -+#define GK7205V200_USB2_PHY_APB_CLK 84 -+#define GK7205V200_USB2_PHY_PLL_CLK 85 -+#define GK7205V200_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V200_NR_CLKS 256 -+#define GK7205V200_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V200_CLOCK_H */ -diff -urN linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h ---- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V300_CLOCK_H -+#define __DTS_GK7205V300_CLOCK_H -+ -+/* clk in GK7205V300 CRG */ -+/* fixed rate clocks */ -+#define GK7205V300_FIXED_100K 1 -+#define GK7205V300_FIXED_400K 2 -+#define GK7205V300_FIXED_3M 3 -+#define GK7205V300_FIXED_6M 4 -+#define GK7205V300_FIXED_12M 5 -+#define GK7205V300_FIXED_24M 6 -+#define GK7205V300_FIXED_25M 7 -+#define GK7205V300_FIXED_50M 8 -+#define GK7205V300_FIXED_83P3M 9 -+#define GK7205V300_FIXED_90M 10 -+#define GK7205V300_FIXED_100M 11 -+#define GK7205V300_FIXED_112M 12 -+#define GK7205V300_FIXED_125M 13 -+#define GK7205V300_FIXED_148P5M 14 -+#define GK7205V300_FIXED_150M 15 -+#define GK7205V300_FIXED_200M 16 -+#define GK7205V300_FIXED_250M 17 -+#define GK7205V300_FIXED_300M 18 -+#define GK7205V300_FIXED_324M 19 -+#define GK7205V300_FIXED_342M 20 -+#define GK7205V300_FIXED_375M 21 -+#define GK7205V300_FIXED_400M 22 -+#define GK7205V300_FIXED_448M 23 -+#define GK7205V300_FIXED_500M 24 -+#define GK7205V300_FIXED_540M 25 -+#define GK7205V300_FIXED_600M 26 -+#define GK7205V300_FIXED_750M 27 -+#define GK7205V300_FIXED_1000M 28 -+#define GK7205V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V300_SYSAXI_CLK 30 -+#define GK7205V300_SYSAPB_CLK 31 -+#define GK7205V300_FMC_MUX 32 -+#define GK7205V300_UART_MUX 33 -+#define GK7205V300_MMC0_MUX 34 -+#define GK7205V300_MMC1_MUX 35 -+#define GK7205V300_MMC2_MUX 36 -+#define GK7205V300_ETH_MUX 37 -+#define GK7205V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V300_UART0_CLK 40 -+#define GK7205V300_UART1_CLK 41 -+#define GK7205V300_UART2_CLK 42 -+#define GK7205V300_FMC_CLK 43 -+#define GK7205V300_ETH0_CLK 44 -+#define GK7205V300_EDMAC_AXICLK 45 -+#define GK7205V300_EDMAC_CLK 46 -+#define GK7205V300_SPI0_CLK 48 -+#define GK7205V300_SPI1_CLK 49 -+#define GK7205V300_MMC0_CLK 50 -+#define GK7205V300_MMC1_CLK 51 -+#define GK7205V300_MMC2_CLK 52 -+#define GK7205V300_I2C0_CLK 53 -+#define GK7205V300_I2C1_CLK 54 -+#define GK7205V300_I2C2_CLK 55 -+#define GK7205V300_USB2_BUS_CLK 81 -+#define GK7205V300_USB2_REF_CLK 82 -+#define GK7205V300_USB2_UTMI_CLK 83 -+#define GK7205V300_USB2_PHY_APB_CLK 84 -+#define GK7205V300_USB2_PHY_PLL_CLK 85 -+#define GK7205V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V300_NR_CLKS 256 -+#define GK7205V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h ---- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7605V100_CLOCK_H -+#define __DTS_GK7605V100_CLOCK_H -+ -+/* clk in GK7605V100 CRG */ -+/* fixed rate clocks */ -+#define GK7605V100_FIXED_100K 1 -+#define GK7605V100_FIXED_400K 2 -+#define GK7605V100_FIXED_3M 3 -+#define GK7605V100_FIXED_6M 4 -+#define GK7605V100_FIXED_12M 5 -+#define GK7605V100_FIXED_24M 6 -+#define GK7605V100_FIXED_25M 7 -+#define GK7605V100_FIXED_50M 8 -+#define GK7605V100_FIXED_83P3M 9 -+#define GK7605V100_FIXED_90M 10 -+#define GK7605V100_FIXED_100M 11 -+#define GK7605V100_FIXED_112M 12 -+#define GK7605V100_FIXED_125M 13 -+#define GK7605V100_FIXED_148P5M 14 -+#define GK7605V100_FIXED_150M 15 -+#define GK7605V100_FIXED_200M 16 -+#define GK7605V100_FIXED_250M 17 -+#define GK7605V100_FIXED_300M 18 -+#define GK7605V100_FIXED_324M 19 -+#define GK7605V100_FIXED_342M 20 -+#define GK7605V100_FIXED_375M 21 -+#define GK7605V100_FIXED_400M 22 -+#define GK7605V100_FIXED_448M 23 -+#define GK7605V100_FIXED_500M 24 -+#define GK7605V100_FIXED_540M 25 -+#define GK7605V100_FIXED_600M 26 -+#define GK7605V100_FIXED_750M 27 -+#define GK7605V100_FIXED_1000M 28 -+#define GK7605V100_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7605V100_SYSAXI_CLK 30 -+#define GK7605V100_SYSAPB_CLK 31 -+#define GK7605V100_FMC_MUX 32 -+#define GK7605V100_UART_MUX 33 -+#define GK7605V100_MMC0_MUX 34 -+#define GK7605V100_MMC1_MUX 35 -+#define GK7605V100_MMC2_MUX 36 -+#define GK7605V100_ETH_MUX 37 -+#define GK7605V100_USB2_MUX 80 -+/* gate clocks */ -+#define GK7605V100_UART0_CLK 40 -+#define GK7605V100_UART1_CLK 41 -+#define GK7605V100_UART2_CLK 42 -+#define GK7605V100_FMC_CLK 43 -+#define GK7605V100_ETH0_CLK 44 -+#define GK7605V100_EDMAC_AXICLK 45 -+#define GK7605V100_EDMAC_CLK 46 -+#define GK7605V100_SPI0_CLK 48 -+#define GK7605V100_SPI1_CLK 49 -+#define GK7605V100_MMC0_CLK 50 -+#define GK7605V100_MMC1_CLK 51 -+#define GK7605V100_MMC2_CLK 52 -+#define GK7605V100_I2C0_CLK 53 -+#define GK7605V100_I2C1_CLK 54 -+#define GK7605V100_I2C2_CLK 55 -+#define GK7605V100_USB2_BUS_CLK 81 -+#define GK7605V100_USB2_REF_CLK 82 -+#define GK7605V100_USB2_UTMI_CLK 83 -+#define GK7605V100_USB2_PHY_APB_CLK 84 -+#define GK7605V100_USB2_PHY_PLL_CLK 85 -+#define GK7605V100_USB2_PHY_XO_CLK 86 -+ -+#define GK7605V100_NR_CLKS 256 -+#define GK7605V100_NR_RSTS 256 -+ -+#endif /* __DTS_GK7605V100_CLOCK_H */ diff -urN linux-4.9.37/arch/mips/boot/.gitignore linux-4.9.y/arch/mips/boot/.gitignore --- linux-4.9.37/arch/mips/boot/.gitignore 2017-07-12 16:42:41.000000000 +0300 +++ linux-4.9.y/arch/mips/boot/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -33079,326 +31479,6 @@ diff -urN linux-4.9.37/arch/parisc/kernel/.gitignore linux-4.9.y/arch/parisc/ker +++ linux-4.9.y/arch/parisc/kernel/.gitignore 1970-01-01 03:00:00.000000000 +0300 @@ -1 +0,0 @@ -vmlinux.lds -diff -urN linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h ---- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7202V300_CLOCK_H -+#define __DTS_GK7202V300_CLOCK_H -+ -+/* clk in GK7202V300 CRG */ -+/* fixed rate clocks */ -+#define GK7202V300_FIXED_100K 1 -+#define GK7202V300_FIXED_400K 2 -+#define GK7202V300_FIXED_3M 3 -+#define GK7202V300_FIXED_6M 4 -+#define GK7202V300_FIXED_12M 5 -+#define GK7202V300_FIXED_24M 6 -+#define GK7202V300_FIXED_25M 7 -+#define GK7202V300_FIXED_50M 8 -+#define GK7202V300_FIXED_83P3M 9 -+#define GK7202V300_FIXED_90M 10 -+#define GK7202V300_FIXED_100M 11 -+#define GK7202V300_FIXED_112M 12 -+#define GK7202V300_FIXED_125M 13 -+#define GK7202V300_FIXED_148P5M 14 -+#define GK7202V300_FIXED_150M 15 -+#define GK7202V300_FIXED_200M 16 -+#define GK7202V300_FIXED_250M 17 -+#define GK7202V300_FIXED_300M 18 -+#define GK7202V300_FIXED_324M 19 -+#define GK7202V300_FIXED_342M 20 -+#define GK7202V300_FIXED_375M 21 -+#define GK7202V300_FIXED_400M 22 -+#define GK7202V300_FIXED_448M 23 -+#define GK7202V300_FIXED_500M 24 -+#define GK7202V300_FIXED_540M 25 -+#define GK7202V300_FIXED_600M 26 -+#define GK7202V300_FIXED_750M 27 -+#define GK7202V300_FIXED_1000M 28 -+#define GK7202V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7202V300_SYSAXI_CLK 30 -+#define GK7202V300_SYSAPB_CLK 31 -+#define GK7202V300_FMC_MUX 32 -+#define GK7202V300_UART_MUX 33 -+#define GK7202V300_MMC0_MUX 34 -+#define GK7202V300_MMC1_MUX 35 -+#define GK7202V300_MMC2_MUX 36 -+#define GK7202V300_ETH_MUX 37 -+#define GK7202V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7202V300_UART0_CLK 40 -+#define GK7202V300_UART1_CLK 41 -+#define GK7202V300_UART2_CLK 42 -+#define GK7202V300_FMC_CLK 43 -+#define GK7202V300_ETH0_CLK 44 -+#define GK7202V300_EDMAC_AXICLK 45 -+#define GK7202V300_EDMAC_CLK 46 -+#define GK7202V300_SPI0_CLK 48 -+#define GK7202V300_SPI1_CLK 49 -+#define GK7202V300_MMC0_CLK 50 -+#define GK7202V300_MMC1_CLK 51 -+#define GK7202V300_MMC2_CLK 52 -+#define GK7202V300_I2C0_CLK 53 -+#define GK7202V300_I2C1_CLK 54 -+#define GK7202V300_I2C2_CLK 55 -+#define GK7202V300_USB2_BUS_CLK 81 -+#define GK7202V300_USB2_REF_CLK 82 -+#define GK7202V300_USB2_UTMI_CLK 83 -+#define GK7202V300_USB2_PHY_APB_CLK 84 -+#define GK7202V300_USB2_PHY_PLL_CLK 85 -+#define GK7202V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7202V300_NR_CLKS 256 -+#define GK7202V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7202V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h ---- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V200_CLOCK_H -+#define __DTS_GK7205V200_CLOCK_H -+ -+/* clk in GK7205V200 CRG */ -+/* fixed rate clocks */ -+#define GK7205V200_FIXED_100K 1 -+#define GK7205V200_FIXED_400K 2 -+#define GK7205V200_FIXED_3M 3 -+#define GK7205V200_FIXED_6M 4 -+#define GK7205V200_FIXED_12M 5 -+#define GK7205V200_FIXED_24M 6 -+#define GK7205V200_FIXED_25M 7 -+#define GK7205V200_FIXED_50M 8 -+#define GK7205V200_FIXED_83P3M 9 -+#define GK7205V200_FIXED_90M 10 -+#define GK7205V200_FIXED_100M 11 -+#define GK7205V200_FIXED_112M 12 -+#define GK7205V200_FIXED_125M 13 -+#define GK7205V200_FIXED_148P5M 14 -+#define GK7205V200_FIXED_150M 15 -+#define GK7205V200_FIXED_200M 16 -+#define GK7205V200_FIXED_250M 17 -+#define GK7205V200_FIXED_300M 18 -+#define GK7205V200_FIXED_324M 19 -+#define GK7205V200_FIXED_342M 20 -+#define GK7205V200_FIXED_375M 21 -+#define GK7205V200_FIXED_400M 22 -+#define GK7205V200_FIXED_448M 23 -+#define GK7205V200_FIXED_500M 24 -+#define GK7205V200_FIXED_540M 25 -+#define GK7205V200_FIXED_600M 26 -+#define GK7205V200_FIXED_750M 27 -+#define GK7205V200_FIXED_1000M 28 -+#define GK7205V200_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V200_SYSAXI_CLK 30 -+#define GK7205V200_SYSAPB_CLK 31 -+#define GK7205V200_FMC_MUX 32 -+#define GK7205V200_UART_MUX 33 -+#define GK7205V200_MMC0_MUX 34 -+#define GK7205V200_MMC1_MUX 35 -+#define GK7205V200_MMC2_MUX 36 -+#define GK7205V200_ETH_MUX 37 -+#define GK7205V200_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V200_UART0_CLK 40 -+#define GK7205V200_UART1_CLK 41 -+#define GK7205V200_UART2_CLK 42 -+#define GK7205V200_FMC_CLK 43 -+#define GK7205V200_ETH0_CLK 44 -+#define GK7205V200_EDMAC_AXICLK 45 -+#define GK7205V200_EDMAC_CLK 46 -+#define GK7205V200_SPI0_CLK 48 -+#define GK7205V200_SPI1_CLK 49 -+#define GK7205V200_MMC0_CLK 50 -+#define GK7205V200_MMC1_CLK 51 -+#define GK7205V200_MMC2_CLK 52 -+#define GK7205V200_I2C0_CLK 53 -+#define GK7205V200_I2C1_CLK 54 -+#define GK7205V200_I2C2_CLK 55 -+#define GK7205V200_USB2_BUS_CLK 81 -+#define GK7205V200_USB2_REF_CLK 82 -+#define GK7205V200_USB2_UTMI_CLK 83 -+#define GK7205V200_USB2_PHY_APB_CLK 84 -+#define GK7205V200_USB2_PHY_PLL_CLK 85 -+#define GK7205V200_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V200_NR_CLKS 256 -+#define GK7205V200_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V200_CLOCK_H */ -diff -urN linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h ---- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7205V300_CLOCK_H -+#define __DTS_GK7205V300_CLOCK_H -+ -+/* clk in GK7205V300 CRG */ -+/* fixed rate clocks */ -+#define GK7205V300_FIXED_100K 1 -+#define GK7205V300_FIXED_400K 2 -+#define GK7205V300_FIXED_3M 3 -+#define GK7205V300_FIXED_6M 4 -+#define GK7205V300_FIXED_12M 5 -+#define GK7205V300_FIXED_24M 6 -+#define GK7205V300_FIXED_25M 7 -+#define GK7205V300_FIXED_50M 8 -+#define GK7205V300_FIXED_83P3M 9 -+#define GK7205V300_FIXED_90M 10 -+#define GK7205V300_FIXED_100M 11 -+#define GK7205V300_FIXED_112M 12 -+#define GK7205V300_FIXED_125M 13 -+#define GK7205V300_FIXED_148P5M 14 -+#define GK7205V300_FIXED_150M 15 -+#define GK7205V300_FIXED_200M 16 -+#define GK7205V300_FIXED_250M 17 -+#define GK7205V300_FIXED_300M 18 -+#define GK7205V300_FIXED_324M 19 -+#define GK7205V300_FIXED_342M 20 -+#define GK7205V300_FIXED_375M 21 -+#define GK7205V300_FIXED_400M 22 -+#define GK7205V300_FIXED_448M 23 -+#define GK7205V300_FIXED_500M 24 -+#define GK7205V300_FIXED_540M 25 -+#define GK7205V300_FIXED_600M 26 -+#define GK7205V300_FIXED_750M 27 -+#define GK7205V300_FIXED_1000M 28 -+#define GK7205V300_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7205V300_SYSAXI_CLK 30 -+#define GK7205V300_SYSAPB_CLK 31 -+#define GK7205V300_FMC_MUX 32 -+#define GK7205V300_UART_MUX 33 -+#define GK7205V300_MMC0_MUX 34 -+#define GK7205V300_MMC1_MUX 35 -+#define GK7205V300_MMC2_MUX 36 -+#define GK7205V300_ETH_MUX 37 -+#define GK7205V300_USB2_MUX 80 -+/* gate clocks */ -+#define GK7205V300_UART0_CLK 40 -+#define GK7205V300_UART1_CLK 41 -+#define GK7205V300_UART2_CLK 42 -+#define GK7205V300_FMC_CLK 43 -+#define GK7205V300_ETH0_CLK 44 -+#define GK7205V300_EDMAC_AXICLK 45 -+#define GK7205V300_EDMAC_CLK 46 -+#define GK7205V300_SPI0_CLK 48 -+#define GK7205V300_SPI1_CLK 49 -+#define GK7205V300_MMC0_CLK 50 -+#define GK7205V300_MMC1_CLK 51 -+#define GK7205V300_MMC2_CLK 52 -+#define GK7205V300_I2C0_CLK 53 -+#define GK7205V300_I2C1_CLK 54 -+#define GK7205V300_I2C2_CLK 55 -+#define GK7205V300_USB2_BUS_CLK 81 -+#define GK7205V300_USB2_REF_CLK 82 -+#define GK7205V300_USB2_UTMI_CLK 83 -+#define GK7205V300_USB2_PHY_APB_CLK 84 -+#define GK7205V300_USB2_PHY_PLL_CLK 85 -+#define GK7205V300_USB2_PHY_XO_CLK 86 -+ -+#define GK7205V300_NR_CLKS 256 -+#define GK7205V300_NR_RSTS 256 -+ -+#endif /* __DTS_GK7205V300_CLOCK_H */ -diff -urN linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h ---- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300 -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved. -+ */ -+ -+#ifndef __DTS_GK7605V100_CLOCK_H -+#define __DTS_GK7605V100_CLOCK_H -+ -+/* clk in GK7605V100 CRG */ -+/* fixed rate clocks */ -+#define GK7605V100_FIXED_100K 1 -+#define GK7605V100_FIXED_400K 2 -+#define GK7605V100_FIXED_3M 3 -+#define GK7605V100_FIXED_6M 4 -+#define GK7605V100_FIXED_12M 5 -+#define GK7605V100_FIXED_24M 6 -+#define GK7605V100_FIXED_25M 7 -+#define GK7605V100_FIXED_50M 8 -+#define GK7605V100_FIXED_83P3M 9 -+#define GK7605V100_FIXED_90M 10 -+#define GK7605V100_FIXED_100M 11 -+#define GK7605V100_FIXED_112M 12 -+#define GK7605V100_FIXED_125M 13 -+#define GK7605V100_FIXED_148P5M 14 -+#define GK7605V100_FIXED_150M 15 -+#define GK7605V100_FIXED_200M 16 -+#define GK7605V100_FIXED_250M 17 -+#define GK7605V100_FIXED_300M 18 -+#define GK7605V100_FIXED_324M 19 -+#define GK7605V100_FIXED_342M 20 -+#define GK7605V100_FIXED_375M 21 -+#define GK7605V100_FIXED_400M 22 -+#define GK7605V100_FIXED_448M 23 -+#define GK7605V100_FIXED_500M 24 -+#define GK7605V100_FIXED_540M 25 -+#define GK7605V100_FIXED_600M 26 -+#define GK7605V100_FIXED_750M 27 -+#define GK7605V100_FIXED_1000M 28 -+#define GK7605V100_FIXED_1500M 29 -+ -+/* mux clocks */ -+#define GK7605V100_SYSAXI_CLK 30 -+#define GK7605V100_SYSAPB_CLK 31 -+#define GK7605V100_FMC_MUX 32 -+#define GK7605V100_UART_MUX 33 -+#define GK7605V100_MMC0_MUX 34 -+#define GK7605V100_MMC1_MUX 35 -+#define GK7605V100_MMC2_MUX 36 -+#define GK7605V100_ETH_MUX 37 -+#define GK7605V100_USB2_MUX 80 -+/* gate clocks */ -+#define GK7605V100_UART0_CLK 40 -+#define GK7605V100_UART1_CLK 41 -+#define GK7605V100_UART2_CLK 42 -+#define GK7605V100_FMC_CLK 43 -+#define GK7605V100_ETH0_CLK 44 -+#define GK7605V100_EDMAC_AXICLK 45 -+#define GK7605V100_EDMAC_CLK 46 -+#define GK7605V100_SPI0_CLK 48 -+#define GK7605V100_SPI1_CLK 49 -+#define GK7605V100_MMC0_CLK 50 -+#define GK7605V100_MMC1_CLK 51 -+#define GK7605V100_MMC2_CLK 52 -+#define GK7605V100_I2C0_CLK 53 -+#define GK7605V100_I2C1_CLK 54 -+#define GK7605V100_I2C2_CLK 55 -+#define GK7605V100_USB2_BUS_CLK 81 -+#define GK7605V100_USB2_REF_CLK 82 -+#define GK7605V100_USB2_UTMI_CLK 83 -+#define GK7605V100_USB2_PHY_APB_CLK 84 -+#define GK7605V100_USB2_PHY_PLL_CLK 85 -+#define GK7605V100_USB2_PHY_XO_CLK 86 -+ -+#define GK7605V100_NR_CLKS 256 -+#define GK7605V100_NR_RSTS 256 -+ -+#endif /* __DTS_GK7605V100_CLOCK_H */ diff -urN linux-4.9.37/arch/powerpc/boot/.gitignore linux-4.9.y/arch/powerpc/boot/.gitignore --- linux-4.9.37/arch/powerpc/boot/.gitignore 2017-07-12 16:42:41.000000000 +0300 +++ linux-4.9.y/arch/powerpc/boot/.gitignore 1970-01-01 03:00:00.000000000 +0300 diff --git a/br-ext-chip-goke/board/gk7205v200/kernel/patches/11_fix_yylloc_for_modern_computers.patch b/br-ext-chip-goke/board/gk7205v200/kernel/patches/11_fix_yylloc_for_modern_computers.patch new file mode 100644 index 00000000..2a670230 --- /dev/null +++ b/br-ext-chip-goke/board/gk7205v200/kernel/patches/11_fix_yylloc_for_modern_computers.patch @@ -0,0 +1,11 @@ +--- a/scripts/dtc/dtc-lexer.lex.c_shipped 2016-08-28 13:19:20.000000000 +0300 ++++ b/scripts/dtc/dtc-lexer.lex.c_shipped 2021-04-02 00:06:02.972781070 +0300 +@@ -637,7 +637,7 @@ + #include "srcpos.h" + #include "dtc-parser.tab.h" + +-YYLTYPE yylloc; ++extern YYLTYPE yylloc; + extern bool treesource_error; + + /* CAUTION: this will stop working if we ever use yyless() or yyunput() */