mirror of https://github.com/OpenIPC/firmware.git
Add new HiSilicon sensor modules and configs (#845)
Co-authored-by: Signor Pellegrino <68112357+FlyRouter@users.noreply.github.com>pull/848/head
Igor Zalatov
GitHub
parent
ce2612189b
commit
3d0693ff2f
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@ -0,0 +1,276 @@
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[sensor]
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Sensor_type =ov9750 ;sensor name
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Mode =0 ;WDR_MODE_NONE = 0
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;WDR_MODE_BUILT_IN = 1
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;WDR_MODE_2To1_LINE = 2
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;WDR_MODE_2To1_FRAME = 3
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;WDR_MODE_2To1_FRAME_FULL_RATE =4 ...etc
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DllFile =/usr/lib/sensors/libsns_ov9750_orig.so ;sensor lib path
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[mode]
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input_mode =4 ;INPUT_MODE_MIPI = 0
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;INPUT_MODE_SUBLVDS = 1
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;INPUT_MODE_LVDS = 2 ...etc
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dev_attr = 2 ;mipi_dev_attr_t = 0
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;lvds_dev_attr_t = 1
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;NULL =2
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[mipi]
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;----------only for mipi_dev---------
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data_type =-1 ;raw data type: 8/10/12/14 bit
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;RAW_DATA_8BIT = 1
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;RAW_DATA_10BIT = 2
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;RAW_DATA_12BIT = 3
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;RAW_DATA_14BIT = 4
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lane_id = -1|-1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable
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[lvds]
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;----------only for lvds_dev---------
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img_size_w = -1 ;oringnal sensor input image size W
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img_size_h = -1 ;oringnal sensor input image size H
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wdr_mode = -1 ;HI_WDR_MODE_NONE =0
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;HI_WDR_MODE_2F = 1
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;HI_WDR_MODE_3F = 2
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;HI_WDR_MODE_4F =3
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sync_mode = -1 ;LVDS_SYNC_MODE_SOL = 0
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;LVDS_SYNC_MODE_SAV = 1
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raw_data_type = -1 ;RAW_DATA_8BIT = 0
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;RAW_DATA_10BIT = 1
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;RAW_DATA_12BIT = 2
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;RAW_DATA_14BIT = 3
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data_endian = -1 ;LVDS_ENDIAN_LITTLE = 0
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;LVDS_ENDIAN_BIG = 1
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sync_code_endian =-1 ;LVDS_ENDIAN_LITTLE = 0
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;LVDS_ENDIAN_BIG = 1
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lane_id = -1|-1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable
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lvds_lane_num = -1 ;LVDS_LANE_NUM
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wdr_vc_num = -1 ;WDR_VC_NUM
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sync_code_num = -1 ;SYNC_CODE_NUM
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sync_code_0 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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sync_code_1 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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sync_code_2 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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sync_code_3 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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sync_code_4 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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sync_code_5 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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sync_code_6 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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sync_code_7 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
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[isp_image]
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Isp_x =0
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Isp_y =0
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Isp_W =1280
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Isp_H =960
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Isp_FrameRate=25
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Isp_Bayer =3 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3
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[vi_dev]
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Input_mod =2 ;VI_INPUT_MODE_BT656 = 0
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;VI_INPUT_MODE_BT601,
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;VI_INPUT_MODE_DIGITAL_CAMERA
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Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
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;VI_WORK_MODE_2Multiplex,
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;VI_WORK_MODE_4Multiplex
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Combine_mode =0 ;Y/C composite or separation mode
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;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
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;VI_COMBINE_SEPARATE, /*Separate mode */
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Comp_mode =0 ;Component mode (single-component or dual-component)
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;VI_COMP_MODE_SINGLE = 0, /*single component mode */
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;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
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Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
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;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
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;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
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Mask_num =2 ;Component mask
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Mask_0 =0xFFF0000
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Mask_1 =0x0
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Scan_mode = 1;VI_SCAN_INTERLACED = 0
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;VI_SCAN_PROGRESSIVE,
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Data_seq =2 ;data sequence (ONLY for YUV format)
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;----2th component U/V sequence in bt1120
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; VI_INPUT_DATA_VUVU = 0,
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; VI_INPUT_DATA_UVUV,
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;----input sequence for yuv
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; VI_INPUT_DATA_UYVY = 0,
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; VI_INPUT_DATA_VYUY,
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; VI_INPUT_DATA_YUYV,
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; VI_INPUT_DATA_YVYU
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Vsync =0 ; vertical synchronization signal
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;VI_VSYNC_FIELD = 0,
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;VI_VSYNC_PULSE,
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VsyncNeg=0 ;Polarity of the vertical synchronization signal
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;VI_VSYNC_NEG_HIGH = 0,
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;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
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Hsync =0 ;Attribute of the horizontal synchronization signal
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;VI_HSYNC_VALID_SINGNAL = 0,
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;VI_HSYNC_PULSE,
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HsyncNeg =0 ;Polarity of the horizontal synchronization signal
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;VI_HSYNC_NEG_HIGH = 0,
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;VI_HSYNC_NEG_LOW
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VsyncValid =1 ;Attribute of the valid vertical synchronization signal
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;VI_VSYNC_NORM_PULSE = 0,
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;VI_VSYNC_VALID_SINGAL,
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VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
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;VI_VSYNC_VALID_NEG_HIGH = 0,
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;VI_VSYNC_VALID_NEG_LOW
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Timingblank_HsyncHfb =408 ;Horizontal front blanking width
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Timingblank_HsyncAct =1280 ;Horizontal effetive width
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Timingblank_HsyncHbb =0 ;Horizontal back blanking width
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Timingblank_VsyncVfb =6 ;Vertical front blanking height
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Timingblank_VsyncVact =960 ;Vertical effetive width
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Timingblank_VsyncVbb=6 ;Vertical back blanking height
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Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
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Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
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Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
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;----- only for bt656 ----------
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FixCode =0 ;BT656_FIXCODE_1 = 0,
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;BT656_FIXCODE_0
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FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0
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;BT656_FIELD_POLAR_NSTD
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DataPath =1 ;ISP enable or bypass
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;VI_PATH_BYPASS = 0,/* ISP bypass */
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;VI_PATH_ISP = 1,/* ISP enable */
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;VI_PATH_RAW = 2,/* Capture raw data, for debug */
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InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
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DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
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DevRect_x=0 ;
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DevRect_y=0 ;
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DevRect_w=1280 ;
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DevRect_h=960 ;
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[vi_chn]
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CapRect_X =0
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CapRect_Y =0
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CapRect_Width=1280
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CapRect_Height=960
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DestSize_Width=1280
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DestSize_Height=960
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CapSel =2 ;Frame/field select. ONLY used in interlaced mode
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;VI_CAPSEL_TOP = 0, /* top field */
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;VI_CAPSEL_BOTTOM, /* bottom field */
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;VI_CAPSEL_BOTH, /* top and bottom field */
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PixFormat =23;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22
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;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc
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CompressMode =0 ;COMPRESS_MODE_NONE = 0
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;COMPRESS_MODE_SEG =1 ...etc
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SrcFrameRate=-1 ;Source frame rate. -1: not controll
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FrameRate =-1 ;Target frame rate. -1: not controll
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[vpss_group]
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Vpss_DciEn =FALSE
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Vpss_IeEn =FALSE
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Vpss_NrEn =TRUE
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Vpss_HistEn =FALSE
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Vpss_DieMode=1 ;Define de-interlace mode
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;VPSS_DIE_MODE_AUTO = 0,
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;VPSS_DIE_MODE_NODIE = 1,
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;VPSS_DIE_MODE_DIE = 2,
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[vpss_corp]
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Crop_enable =FALSE
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Coordinate =1 ;VPSS_CROP_RATIO_COOR = 0, /*Ratio coordinate*/
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;VPSS_CROP_ABS_COOR = 1 /*Absolute coordinate*/
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Crop_X =128
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Crop_Y =128
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Crop_W =1158
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Crop_H =562
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[vpss_chn]
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Vpss_W =1280
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Vpss_H =960
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CompressMode=0 ;COMPRESS_MODE_NONE = 0
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;COMPRESS_MODE_SEG =1 ...etc
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Mirror =FALSE;Whether to mirror
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Flip =FALSE;Whether to flip
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[vb_conf]
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VbCnt=10
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vbTimes=15 ;when raw=8bit vbTimes = 10
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;when raw=10/12 bit vbTimes = 15
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;when raw=14/16 bit vbTimes = 20
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[venc_comm]
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venc_chn =1 ;create venc chn number;(0,2]
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BufCnt = 1 ;network meida-trans bufcnt
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[venc_0]
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PicWidth =1280
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PicHeight =960
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Profile =2
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RcMode =VENC_RC_MODE_H264CBR
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Gop =50
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StatTime =2
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ViFrmRate =25
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TargetFrmRate=25
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;----- only for VENC_RC_MODE_H264CBR ----------
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BitRate=2048
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FluctuateLevel=0
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;----- only for VENC_RC_MODE_H264VBR ----------
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MaxBitRate =10000
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MaxQp=32
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MinQp=24
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;----- only for VENC_RC_MODE_H264FIXQP ----------
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IQp=45
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PQp=40
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;-------- for REF_EX IsliceEnable------
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IsliceEnable = FALSE ;IsliceEnable and ViEnable is mutual exclusion
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IsRefreshEnable = FALSE ;IsliceEnable and bRefreshEnable both TRUE is effective
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RefreshLineNum = 12 ;PicHeight/16/6 6 is empirical value,ask Fuyang
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ReqIQp = 30
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;-------- for REF_EX ViEnable------
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ViEnable = TRUE
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ViInterval = 50 ; 2s
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ViQpDelta = 2
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[venc_1]
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PicWidth =1280
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PicHeight =960
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Profile =2
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RcMode =VENC_RC_MODE_H264CBR
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Gop =50
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StatTime =2
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ViFrmRate =25
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TargetFrmRate=25
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;----- only for VENC_RC_MODE_H264CBR ----------
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BitRate=4096
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FluctuateLevel=0
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;----- only for VENC_RC_MODE_H264VBR ----------
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MaxBitRate =10000
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MaxQp=32
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MinQp=24
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;----- only for VENC_RC_MODE_H264FIXQP ----------
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IQp=40
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PQp=45
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;-------- for REF_EX IsliceEnable------
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IsliceEnable = FALSE ;IsliceEnable and ViEnable is mutual exclusion
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IsRefreshEnable = FALSE ;IsliceEnable and bRefreshEnable both TRUE is effective
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RefreshLineNum = 12 ;PicHeight/16/6 6 is empirical value,ask Fuyang
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ReqIQp = 30
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;-------- for REF_EX ViEnable------
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ViEnable = TRUE
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ViInterval = 50 ; 2s
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ViQpDelta = 2
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[bind]
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ViDev =0
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ViChn =0
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VpssGrp =0
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VpssChn = 0
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VoDev =0
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VoChn =0
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ViSnapChn =0
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VpssSnapGrp=0
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VpssSnapChn=1
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VencSnapGrp=1
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VencSnapChn=3
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@ -90,6 +90,7 @@ define HISILICON_OSDRV_HI3516CV200_INSTALL_TARGET_CMDS
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$(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(HISILICON_OSDRV_HI3516CV200_PKGDIR)/files/sensor/libsns_ov9732.so
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$(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(HISILICON_OSDRV_HI3516CV200_PKGDIR)/files/sensor/libsns_ov9750.so
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$(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(HISILICON_OSDRV_HI3516CV200_PKGDIR)/files/sensor/libsns_ov9752.so
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# $(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(HISILICON_OSDRV_HI3516CV200_PKGDIR)/files/sensor/libsns_ov9750_v2.so
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$(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(HISILICON_OSDRV_HI3516CV200_PKGDIR)/files/sensor/libsns_sc1135.so
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$(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(HISILICON_OSDRV_HI3516CV200_PKGDIR)/files/sensor/libsns_sc1145.so
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$(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(HISILICON_OSDRV_HI3516CV200_PKGDIR)/files/sensor/libsns_sc1235.so
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