From 2e76dc2ca95f02c8c456b796918ae28c73e1866f Mon Sep 17 00:00:00 2001
From: innd <oleg.kroupenko@gmail.com>
Date: Thu, 10 Nov 2022 03:57:45 +0700
Subject: [PATCH] 3516cv100+mt9p006 requires GPIO setup (#543)
---
.../files/script/load_hisilicon | 3 +
.../sensor/config/mt9p006_i2c_dc_720p.ini | 123 ++++++++++++++++++
2 files changed, 126 insertions(+)
create mode 100644 general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/mt9p006_i2c_dc_720p.ini
diff --git a/general/package/hisilicon-osdrv-hi3516cv100/files/script/load_hisilicon b/general/package/hisilicon-osdrv-hi3516cv100/files/script/load_hisilicon
index 089d226a..2761ebb7 100755
--- a/general/package/hisilicon-osdrv-hi3516cv100/files/script/load_hisilicon
+++ b/general/package/hisilicon-osdrv-hi3516cv100/files/script/load_hisilicon
@@ -118,6 +118,9 @@ insert_sns() {
mt9p006)
devmem 0x20030030 32 0x1 #Sensor clock 24 MHz
devmem 0x2003002c 32 0x6a #VI input associated clock phase reversed
+ devmem 0x200f0138 32 0 # pinmux [GPIO0_6] SVB_PWM TEMPER_DQ
+ devmem 0x20140400 32 0x60 # set GPIO 0_6 direction OUTPUT
+ devmem 0x201403FC 32 0xff # set GPIO 0_6 0
insmod ssp_ad9020.ko
;;
hm1375 | ar0330)
diff --git a/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/mt9p006_i2c_dc_720p.ini b/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/mt9p006_i2c_dc_720p.ini
new file mode 100644
index 00000000..979285ab
--- /dev/null
+++ b/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/mt9p006_i2c_dc_720p.ini
@@ -0,0 +1,123 @@
+[sensor]
+Sensor_type =mt9p006 ;sensor name
+Mode =0 ;WDR_MODE_NONE = 0
+ ;WDR_MODE_BUILT_IN = 1
+ ;WDR_MODE_2To1_LINE = 2
+ ;WDR_MODE_2To1_LINE = 3
+ ;WDR_MODE_2To1_FRAME_FULL_RATE =4 ...etc
+DllFile = /usr/lib/sensors/libsns_mt9p006.so ;sensor lib path
+
+
+[mode]
+input_mode =INPUT_MODE_CMOS_33V ;INPUT_MODE_MIPI = 0
+ ;INPUT_MODE_SUBLVDS = 1
+ ;INPUT_MODE_LVDS = 2 ...etc
+
+dev_attr = 2 ;mipi_dev_attr_t = 0
+ ;lvds_dev_attr_t = 1
+ ;NULL =2
+
+[isp_image]
+Isp_x =0
+Isp_y =0
+Isp_W =1280
+Isp_H =720
+Isp_FrameRate=30
+Isp_Bayer =BAYER_GRBG ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3
+
+
+[vi_dev]
+Input_mod =2 ;VI_INPUT_MODE_BT656 = 0
+ ;VI_INPUT_MODE_BT601,
+ ;VI_INPUT_MODE_DIGITAL_CAMERA
+Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
+ ;VI_WORK_MODE_2Multiplex,
+ ;VI_WORK_MODE_4Multiplex
+Combine_mode =0 ;Y/C composite or separation mode
+ ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
+ ;VI_COMBINE_SEPARATE, /*Separate mode */
+Comp_mode =0 ;Component mode (single-component or dual-component)
+ ;VI_COMP_MODE_SINGLE = 0, /*single component mode */
+ ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
+Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
+ ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
+ ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
+Mask_num =2 ;Component mask
+Mask_0 =0xfff00000
+Mask_1 =0x0
+Scan_mode = VI_SCAN_PROGRESSIVE ;VI_SCAN_INTERLACED = 0
+ ;VI_SCAN_PROGRESSIVE,
+Data_seq =VI_INPUT_DATA_YUYV ;data sequence (ONLY for YUV format)
+ ;----2th component U/V sequence in bt1120
+ ; VI_INPUT_DATA_VUVU = 0,
+ ; VI_INPUT_DATA_UVUV,
+ ;----input sequence for yuv
+ ; VI_INPUT_DATA_UYVY = 0,
+ ; VI_INPUT_DATA_VYUY,
+ ; VI_INPUT_DATA_YUYV,
+ ; VI_INPUT_DATA_YVYU
+
+Vsync =VI_VSYNC_FIELD ; vertical synchronization signal
+ ;VI_VSYNC_FIELD = 0,
+ ;VI_VSYNC_PULSE,
+VsyncNeg=VI_VSYNC_NEG_HIGH ;Polarity of the vertical synchronization signal
+ ;VI_VSYNC_NEG_HIGH = 0,
+ ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
+Hsync =VI_HSYNC_VALID_SINGNAL ;Attribute of the horizontal synchronization signal
+ ;VI_HSYNC_VALID_SINGNAL = 0,
+ ;VI_HSYNC_PULSE,
+HsyncNeg =VI_HSYNC_NEG_HIGH ;Polarity of the horizontal synchronization signal
+ ;VI_HSYNC_NEG_HIGH = 0,
+ ;VI_HSYNC_NEG_LOW
+VsyncValid =VI_VSYNC_VALID_SINGAL ;Attribute of the valid vertical synchronization signal
+ ;VI_VSYNC_NORM_PULSE = 0,
+ ;VI_VSYNC_VALID_SINGAL,
+VsyncValidNeg =VI_VSYNC_VALID_NEG_HIGH ;Polarity of the valid vertical synchronization signal
+ ;VI_VSYNC_VALID_NEG_HIGH = 0,
+ ;VI_VSYNC_VALID_NEG_LOW
+
+Timingblank_HsyncHfb =0 ;Horizontal front blanking width
+Timingblank_HsyncAct =1280 ;Horizontal effetive width
+Timingblank_HsyncHbb =0 ;Horizontal back blanking width
+Timingblank_VsyncVfb =0 ;Vertical front blanking height
+Timingblank_VsyncVact =720 ;Vertical effetive width
+Timingblank_VsyncVbb=0 ;Vertical back blanking height
+Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
+Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
+Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
+
+;----- only for bt656 ----------
+FixCode =0 ;BT656_FIXCODE_1 = 0,
+ ;BT656_FIXCODE_0
+FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0
+ ;BT656_FIELD_POLAR_NSTD
+DataPath =VI_PATH_ISP ;ISP enable or bypass
+ ;VI_PATH_BYPASS = 0,/* ISP bypass */
+ ;VI_PATH_ISP = 1,/* ISP enable */
+ ;VI_PATH_RAW = 2,/* Capture raw data, for debug */
+InputDataType=VI_DATA_TYPE_RGB ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
+DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
+DevRect_x=0 ;
+DevRect_y=0 ;
+DevRect_w=1280 ;
+DevRect_h=720 ;
+
+[vi_chn]
+CapRect_X =0
+CapRect_Y =0
+CapRect_Width=1280
+CapRect_Height=720
+;DestSize_Width=1920
+;DestSize_Height=1080
+CapSel =2 ;Frame/field select. ONLY used in interlaced mode
+ ;VI_CAPSEL_TOP = 0, /* top field */
+ ;VI_CAPSEL_BOTTOM, /* bottom field */
+ ;VI_CAPSEL_BOTH, /* top and bottom field */
+
+PixFormat =19;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22
+ ;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc
+CompressMode =0 ;COMPRESS_MODE_NONE = 0
+ ;COMPRESS_MODE_SEG =1 ...etc
+
+SrcFrameRate=-1 ;Source frame rate. -1: not controll
+FrameRate =-1 ;Target frame rate. -1: not controll