diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/CusEarlyInit_para.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/CusEarlyInit_para.h
new file mode 100644
index 00000000..d46dfc8a
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/CusEarlyInit_para.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _CUSEARLYINIT_PARA_H_
+#define _CUSEARLYINIT_PARA_H_
+
+enum {
+ EARLYINIT_PARAM_TYPE_MASTER,
+ EARLYINIT_PARAM_TYPE_CUST_ROSE
+};
+
+typedef struct
+{
+ unsigned short u16SnrEarlyFps;
+ unsigned short u16SnrEarlyFlicker;
+ unsigned long u32SnrEarlyShutter;
+ unsigned long u32SnrEarlyGainX1024;
+ unsigned long u32SnrEarlyDGain;
+ unsigned long u32SnrEarlyShutterShort;
+ unsigned long u32SnrEarlyGainX1024Short;
+ unsigned long u32SnrEarlyDGainShort;
+ unsigned short u16SnrEarlyAwbRGain;
+ unsigned short u16SnrEarlyAwbGGain;
+ unsigned short u16SnrEarlyAwbBGain;
+} __attribute__ ((packed)) MasterEarlyInitParam_t;
+
+typedef struct
+{
+ unsigned short u16SnrEarlyFps;
+ unsigned short u16SnrEarlyFlicker;
+ unsigned long u32SnrEarlyShutter;
+ unsigned long u32SnrEarlyGainX1024;
+ unsigned long u32SnrEarlyDGain;
+ unsigned long u32DeBugLevel_AWB_PERIOD;
+ unsigned long u32DeBugLevel_AeEarlyStageCnt;
+ unsigned short u16SnrEarlyAwbRGain;
+ unsigned short u16SnrEarlyAwbGGain;
+ unsigned short u16SnrEarlyAwbBGain;
+} __attribute__ ((packed)) CusEarlyInitParam_t;
+
+typedef struct
+{
+ unsigned long u32Revision;
+ unsigned long u32Size;
+
+ union
+ {
+ MasterEarlyInitParam_t tMasSnrEarlyInitParam;
+
+ // Add customize early-init parameter here, if any
+ CusEarlyInitParam_t tCusSnrEarlyInitParam;
+
+ unsigned char u8Data[64];
+ } u;
+
+} IspSensorEarlyInitParam_t;
+
+#endif // _CUSEARLYINIT_PARA_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/drv_ms_cus_sensor.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/drv_ms_cus_sensor.h
new file mode 100644
index 00000000..de6abeee
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/drv_ms_cus_sensor.h
@@ -0,0 +1,977 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*! @file drv_ms_cus_sensor.h
+ @brief This file contains Infinity ISP sensor driver interface.
+*/
+
+/** @defgroup group1 ISP Sensor Driver Interface
+* @{
+*/
+
+#ifndef DRV_MS_CUS_SENSOR_H_
+#define DRV_MS_CUS_SENSOR_H_
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <sensor_i2c_api.h>
+
+#define I2C_RETRYTIME (5)
+
+#ifndef SUCCESS
+#define FAIL (-1)
+#define SUCCESS 0
+#endif
+
+#ifdef __cplusplus
+#define EXPORT_CUS extern "C"
+#else
+#define EXPORT_CUS
+#endif
+
+#define CUS_MSTART_CAMSENSOR_CAP_VERSION 0x0001
+
+//#define usleep(usec) CamOsMsSleep(usec*1000);
+//#define usleep(usec) udelay(usec)
+//#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
+
+#define SENSOR_DRIVER_MODE_NOT_SUUPORT (0xFFFF)
+
+struct __ms_cus_sensor; /**< Sensor driver handle */
+//struct __ISensorAPI; /**< Sensor to ISP control interface */
+
+/*! @brief Resolution descriptor*/
+typedef struct _cus_camsensor_res{
+ u32 width; /**< Image crop width */
+ u32 height; /**< Image crop height */
+ u32 max_fps; /**< Max fps in this resolution */
+ u32 min_fps; /**< Min fps in this resolution*/
+ u32 crop_start_x;
+ u32 crop_start_y;
+ u32 nOutputWidth; /**< Sensor actual output width */
+ u32 nOutputHeight; /**< Sensor actual output height */
+ char strResDesc[32];
+} __attribute__((packed, aligned(4))) cus_camsensor_res;
+
+/*! @brief Resolution list*/
+typedef struct _cus_camsensor_res_list
+{
+ u32 num_res; /**< number of sensor resolution in list */
+ u32 ulcur_res; /**< current sensor resolution*/
+ cus_camsensor_res res[12]; /**< resolution list */
+} __attribute__((packed, aligned(4))) cus_camsensor_res_list;
+
+
+/*! @brief Select sensor type */
+typedef enum {
+ ISP_SOC, /**< Not support */
+ ISP_EXT /**< sensor without built-in ISP */
+} CUS_CAMSENSOR_ISPTYPE;
+
+/*! @brief Sensor bayer raw pixel order */
+typedef enum {
+ CUS_BAYER_RG = 0, /**< bayer data start with R channel */
+ CUS_BAYER_GR, /**< bayer data start with Gr channel */
+ CUS_BAYER_BG, /**< bayer data start with B channel */
+ CUS_BAYER_GB /**< bayer data start with Gb channel */
+} CUS_SEN_BAYER;
+
+typedef enum {
+ CUS_RGBIR_R0 = 0,
+ CUS_RGBIR_G0 = 1,
+ CUS_RGBIR_B0 = 2,
+ CUS_RGBIR_G1 = 3,
+ CUS_RGBIR_G2 = 4,
+ CUS_RGBIR_I0 = 5,
+ CUS_RGBIR_G3 = 6,
+ CUS_RGBIR_I1 = 7,
+ CUS_RGBIR_NONE = 8
+} CUS_SEN_RGBIR;
+
+/*! @brief Set sensor image mirror and flip.*/
+typedef enum {
+ CUS_ORIT_M0F0, /**< mirror, flip unchanged */
+ CUS_ORIT_M1F0, /**< mirror changed, flip unchanged */
+ CUS_ORIT_M0F1, /**< mirror unchanged, flip changed */
+ CUS_ORIT_M1F1, /**< mirror and flip changed */
+} CUS_CAMSENSOR_ORIT;
+
+
+/*! @brief Get input source type.*/
+typedef enum {
+ CUS_SNR_ANADEC_SRC_NO_READY, /**< input no ready */
+ CUS_SNR_ANADEC_SRC_PAL, /**< input type is PAL */
+ CUS_SNR_ANADEC_SRC_NTSC, /**< input type is NTSC */
+ CUS_SNR_ANADEC_SRC_HD, /**< input source type is HD */
+ CUS_SNR_ANADEC_SRC_FHD, /**< input source type is FHD */
+ CUS_SNR_ANADEC_SRC_DISCNT, /**< input disconnect */
+ CUS_SNR_ANADEC_SRC_MAX, /**< input num max */
+}CUS_SNR_ANADEC_SRC_TYPE;
+
+
+/*! @brief ISP AE event notifycation*/
+typedef enum {
+ CUS_FRAME_INACTIVE = 0, /**< Frame end */
+ CUS_FRAME_ACTIVE = 1,/**< Frame start */
+} CUS_CAMSENSOR_AE_STATUS_NOTIFY;
+
+/*! @brief Sensor bayer raw (8/10 bits) to 12bits mode control */
+typedef enum {
+ CUS_SEN_8TO12_7074, /**< Do not use*/
+ CUS_SEN_8TO12_7000, /**< Sensor bayer raw is 8 bits*/
+ CUS_SEN_8TO12_114118, /**< Do not use*/
+ CUS_SEN_8TO12_11400, /**< Do not use*/
+ CUS_SEN_10TO12_9098, /**< Do not use*/
+ CUS_SEN_10TO12_9000, /**< Sensor bayer raw is 10 bits*/
+ CUS_SEN_10TO12_1121110, /**< Do not use*/
+ CUS_SEN_10TO12_11200 /**< Do not use*/
+} CUS_SEN_FMT_CONV_MODE;
+
+/*! @brief Sensor input raw data precision */
+typedef enum {
+ CUS_DATAPRECISION_8 = 0, /**< raw data precision is 8bits */
+ CUS_DATAPRECISION_10 = 1, /**< raw data precision is 10bits */
+ CUS_DATAPRECISION_16 = 2, /**< raw data precision is 16bits */
+ CUS_DATAPRECISION_12 = 3, /**< raw data precision is 12bits */
+ CUS_DATAPRECISION_14 = 4, /**< raw data precision is 14bits */
+} CUS_DATAPRECISION;
+
+/*! @brief Select sensor data intarface */
+typedef enum {
+ CUS_SENIF_BUS_PARL = 0, /**< sensor data bus is parallel bus */
+ CUS_SENIF_BUS_MIPI = 1, /**< sensor data bus is mipi */
+ CUS_SENIF_BUS_BT601 = 2,
+ CUS_SENIF_BUS_BT656 = 3,
+ CUS_SENIF_BUS_BT1120 = 4,
+} CUS_SENIF_BUS;
+
+typedef enum {
+ CUS_SEN_INPUT_FORMAT_YUV422,
+ CUS_SEN_INPUT_FORMAT_RGB,
+} CUS_SEN_INPUT_FORMAT;
+
+/*! @brief Select pin polarity */
+typedef enum {
+ CUS_CLK_POL_POS = 0, /**< High active */
+ CUS_CLK_POL_NEG /**< Low active */
+} CUS_CLK_POL;
+
+typedef enum
+{
+ CUS_SENSOR_YUV_ORDER_CY = 0,
+ CUS_SENSOR_YUV_ORDER_YC = 1,
+}CUS_SENSOR_YUV_ORDER;
+
+/*! @brief Sensor master clock select */
+typedef enum {
+ CUS_CMU_CLK_27MHZ,
+ CUS_CMU_CLK_21P6MHZ,
+ CUS_CMU_CLK_12MHZ,
+ CUS_CMU_CLK_5P4MHZ,
+ CUS_CMU_CLK_36MHZ,
+ CUS_CMU_CLK_54MHZ,
+ CUS_CMU_CLK_43P2MHZ,
+ CUS_CMU_CLK_61P7MHZ,
+ CUS_CMU_CLK_72MHZ,
+ CUS_CMU_CLK_48MHZ,
+ CUS_CMU_CLK_24MHZ,
+ CUS_CMU_CLK_37P125MHZ,
+ CUS_CMU_CLK_LPLL_DIV1,
+ CUS_CMU_CLK_LPLL_DIV2,
+ CUS_CMU_CLK_LPLL_DIV4,
+ CUS_CMU_CLK_LPLL_DIV8,
+} CUS_MCLK_FREQ; //Depends on chip.
+
+//Depends on chip definition.
+typedef enum {
+ CUS_SR0_PAR_DISABLE,
+ CUS_SR0_PAR_MODE_1,
+ CUS_SR0_PAR_MODE_2,
+} CUS_SR0_PAR_MODE;
+
+//Depends on chip definition.
+typedef enum {
+ CUS_SR0_BT656_DISABLE,
+ CUS_SR0_BT656_MODE_1,
+ CUS_SR0_BT656_MODE_2,
+ CUS_SR0_BT656_MODE_3,
+ CUS_SR0_BT656_MODE_4,
+} CUS_SR0_BT656_MODE;
+
+//Depends on chip definition.
+typedef enum {
+ CUS_SR1_BT656_DISABLE,
+ CUS_SR1_BT656_MODE_1,
+} CUS_SR1_BT656_MODE;
+
+//Depends on chip definition.
+typedef enum {
+ CUS_SR0_BT601_DISABLE,
+ CUS_SR0_BT601_MODE_1,
+ CUS_SR0_BT601_MODE_2,
+ CUS_SR0_BT601_MODE_3,
+ CUS_SR0_BT601_MODE_4,
+} CUS_SR0_BT601_MODE;
+
+//Depends on chip definition.
+typedef enum {
+ CUS_SR0_MIPI_DISABLE,
+ CUS_SR0_MIPI_MODE_1,
+ CUS_SR0_MIPI_MODE_2,
+} CUS_SR0_MIPI_MODE;
+
+//Depends on chip definition.
+typedef enum {
+ CUS_SR1_MIPI_DISABLE,
+ CUS_SR1_MIPI_MODE_1,
+ CUS_SR1_MIPI_MODE_2,
+ CUS_SR1_MIPI_MODE_3,
+ CUS_SR1_MIPI_MODE_4,
+} CUS_SR1_MIPI_MODE;
+
+//Depends on chip definition.
+typedef enum
+{
+ CUS_VIF_BT656_EAV_DETECT = 0,
+ CUS_VIF_BT656_SAV_DETECT = 1,
+}CUS_VIF_BT656_CHANNEL_SELECT;
+
+//Depends on chip definition.
+typedef enum
+{
+ CUS_VIF_BT656_VSYNC_DELAY_1LINE = 0,
+ CUS_VIF_BT656_VSYNC_DELAY_2LINE = 1,
+ CUS_VIF_BT656_VSYNC_DELAY_0LINE = 2,
+ CUS_VIF_BT656_VSYNC_DELAY_AUTO = 3,
+}CUS_VIF_BT656_VSYNC_DELAY;
+
+typedef enum
+{
+ CUS_SENSOR_FUNC_DISABLE = 0,
+ CUS_SENSOR_FUNC_ENABLE = 1,
+}CUS_SENSOR_FUNC;
+
+typedef enum
+{
+ CUS_SENSOR_PAD_GROUP_A = 0,
+ CUS_SENSOR_PAD_GROUP_B = 1,
+}CUS_SENSOR_PAD_GROUP;
+
+typedef enum
+{
+ CUS_SENSOR_CHANNEL_MODE_REALTIME_NORMAL = 0,
+ CUS_SENSOR_CHANNEL_MODE_REALTIME_HDR = 1,
+ CUS_SENSOR_CHANNEL_MODE_RAW_STORE = 2,
+ CUS_SENSOR_CHANNEL_MODE_RAW_STORE_HDR = 3,
+}CUS_SENSOR_CHANNEL_MODE;
+
+typedef struct {
+ unsigned int gain;
+ unsigned int offset;
+} CUS_GAIN_GAP_ARRAY;
+
+//////////////////////////////////////
+// sensor functions
+//////////////////////////////////////
+
+typedef struct {
+ u32 length; //header length
+ u32 version; //version
+}CUS_CAMSENSOR_CAP;
+
+/////////////////// ISP for SENSOR API ///////////////////
+typedef enum {
+ CUS_INT_TASK_AE = (1<<0),
+ CUS_INT_TASK_AWB = (1<<1),
+ CUS_INT_TASK_AF = (1<<2),
+ CUS_INT_TASK_VS = (1<<3),
+ CUS_INT_TASK_VDOS = (1<<4),
+} CUS_INT_TASK_TYPE;
+
+#define MAX_RUN_ORDER 16
+typedef struct {
+ u8 RunLength;
+ u8 Orders[MAX_RUN_ORDER];
+ u8 CurTaskType;
+} CUS_INT_TASK_ORDER;
+
+/////////////////// Shutter Info ///////////////////////
+/*! @brief Report shutter information */
+typedef struct {
+ u32 length; /**< struct size */
+ u32 max; /**< maximun shutter in us*/
+ u32 min; /**< minimum shutter in us*/
+ u32 step; /**< shutter in step us*/
+} CUS_SHUTTER_INFO;
+
+////////////////// CSI CLOCK ////////////////////////
+/*! @brief Select MIPI clock*/
+typedef enum {
+ CUS_CSI_CLK_DISABLE = -1, /**< Disable MIPI clock*/
+ CUS_CSI_CLK_108M = 0, /**< MIPI pixel rate 864Mbps (1-lane)*/
+ CUS_CSI_CLK_86M = 1, /**< MIPI pixel rate 344Mbps(1-lane)*/
+ CUS_CSI_CLK_144M = 2, /**< MIPI pixel rate 1152Mbps(1-lane)*/
+ CUS_CSI_CLK_172M = 3,
+ CUS_CSI_CLK_216M = 4,
+ CUS_CSI_CLK_288M = 5,
+ CUS_CSI_CLK_40M = 6,
+ CUS_CSI_CLK_24M = 7,
+ CUS_CSI_CLK_12M = 8,
+ CUS_CSI_CLK_123M = 9
+}CUS_CSI_CLK;
+
+///////////////// SENSOR PIN CONFIG/////////////////
+/*! @brief Sensor pin assignment*/
+typedef enum {
+ CUS_SR_PAD_CFG_1 = 1, /**< Pin config for MIPI 1/2 lanes*/
+ CUS_SR_PAD_CFG_MIPI = 1, /**< Pin config for MIPI 1/2 lanes*/
+ CUS_SR_PAD_CFG_2 = 2, /**< Reserved */
+ CUS_SR_PAD_CFG_3 = 3, /**< Reserved */
+ CUS_SR_PAD_CFG_10BITS = 4, /**< Pin config for parallel interface 10 bits */
+ CUS_SR_PAD_CFG_4 = 4, /**< Pin config for parallel interface 12 bits */
+ CUS_SR_PAD_CFG_12BITS = 5, /**< Pin config for parallel interface 12 bits */
+ CUS_SR_PAD_CFG_5 = 5, /**< Pin config for parallel interface 12 bits */
+ CUS_SR_PAD_CFG_6 = 6 /**< Pin config for parallel interface 12 bits */
+ }CUS_SR_PAD_CFG;
+
+/*! @brief virtual channel0 hsync. mode */
+typedef enum
+{
+ PACKET_HEADER_EDGE1 = 0, /**< packet header edge */
+ PACKET_HEADER_EDGE2 = 1, /**< line end edge */
+ PACKET_HEADER_EDGE3 = 2, /**< line start edge */
+ PACKET_FOOTER_EDGE = 3, /**< packet footer edge */
+}CUS_CSI_VC_HS_MODE;
+
+typedef enum
+{
+ CUS_HDR_MODE_NONE = 0,
+ CUS_HDR_MODE_SONY_DOL = 1,
+ CUS_HDR_MODE_DCG = 2,
+ CUS_HDR_MODE_EMBEDDED_RAW8 = 3,
+ CUS_HDR_MODE_EMBEDDED_RAW10 = 4,
+ CUS_HDR_MODE_EMBEDDED_RAW12 = 5,
+ CUS_HDR_MODE_EMBEDDED_RAW16 = 6, //Only for OV2718?
+ CUS_HDR_MODE_LI = 7,
+ CUS_HDR_MODE_MULTI_VC = 8,
+}CUS_HDR_MODE;
+
+typedef enum
+{
+ // Index 0
+ SENSOR_DRIVER_MODE_VGA_30P_RESOLUTION, // 640*360 30P
+ SENSOR_DRIVER_MODE_VGA_50P_RESOLUTION, // 640*360 50P
+ SENSOR_DRIVER_MODE_VGA_60P_RESOLUTION, // 640*360 60P
+ SENSOR_DRIVER_MODE_VGA_100P_RESOLUTION, // 640*360 100P
+ SENSOR_DRIVER_MODE_VGA_120P_RESOLUTION, // 640*360 120P
+
+ // Index 5
+ SENSOR_DRIVER_MODE_HD_24P_RESOLUTION, // 1280*720 24P
+ SENSOR_DRIVER_MODE_HD_30P_RESOLUTION, // 1280*720 30P
+ SENSOR_DRIVER_MODE_HD_50P_RESOLUTION, // 1280*720 50P
+ SENSOR_DRIVER_MODE_HD_60P_RESOLUTION, // 1280*720 60P
+ SENSOR_DRIVER_MODE_HD_100P_RESOLUTION, // 1280*720 100P
+
+ // Index 10
+ SENSOR_DRIVER_MODE_HD_120P_RESOLUTION, // 1280*720 120P
+ SENSOR_DRIVER_MODE_1600x900_30P_RESOLUTION, // 1600*900 30P
+ SENSOR_DRIVER_MODE_FULL_HD_15P_RESOLUTION, // 1920*1080 15P
+ SENSOR_DRIVER_MODE_FULL_HD_24P_RESOLUTION, // 1920*1080 24P
+ SENSOR_DRIVER_MODE_FULL_HD_25P_RESOLUTION, // 1920*1080 25P
+
+ // Index 15
+ SENSOR_DRIVER_MODE_FULL_HD_30P_RESOLUTION, // 1920*1080 30P
+ SENSOR_DRIVER_MODE_FULL_HD_50P_RESOLUTION, // 1920*1080 50P
+ SENSOR_DRIVER_MODE_FULL_HD_60P_RESOLUTION, // 1920*1080 60P
+ SENSOR_DRIVER_MODE_SUPER_HD_30P_RESOLUTION, // 2304*1296 30P
+ SENSOR_DRIVER_MODE_SUPER_HD_25P_RESOLUTION, // 2304*1296 25P
+
+ // Index 20
+ SENSOR_DRIVER_MODE_SUPER_HD_24P_RESOLUTION, // 2304*1296 24P
+ SENSOR_DRIVER_MODE_1440_30P_RESOLUTION, // 2560*1440 30P
+ SENSOR_DRIVER_MODE_2D7K_15P_RESOLUTION, // 2704*1524 15P
+ SENSOR_DRIVER_MODE_2D7K_30P_RESOLUTION, // 2704*1524 30P
+ SENSOR_DRIVER_MODE_4K2K_15P_RESOLUTION, // 3840*2160 15P
+
+ // Index 25
+ SENSOR_DRIVER_MODE_4K2K_30P_RESOLUTION, // 3840*2160 30P
+ SENSOR_DRIVER_MODE_4TO3_VGA_30P_RESOLUTION, // 640*480 30P
+ SENSOR_DRIVER_MODE_4TO3_1D2M_30P_RESOLUTION, // 1280*960 30P
+ SENSOR_DRIVER_MODE_4TO3_1D5M_30P_RESOLUTION, // 1440*1080 30P
+ SENSOR_DRIVER_MODE_4TO3_3M_15P_RESOLUTION, // 2048*1536 15P
+
+ // Index 30
+ SENSOR_DRIVER_MODE_4TO3_3M_30P_RESOLUTION, // 2048*1536 30P
+ SENSOR_DRIVER_MODE_4TO3_5M_15P_RESOLUTION, // 2560*1920 15P
+ SENSOR_DRIVER_MODE_4TO3_5M_30P_RESOLUTION, // 2560*1920 30P
+ SENSOR_DRIVER_MODE_4TO3_8M_15P_RESOLUTION, // 3264*2448 15P
+ SENSOR_DRIVER_MODE_4TO3_8M_30P_RESOLUTION, // 3264*2448 30P
+
+ // Index 35
+ SENSOR_DRIVER_MODE_4TO3_10M_15P_RESOLUTION, // 3648*2736 15P
+ SENSOR_DRIVER_MODE_4TO3_10M_30P_RESOLUTION, // 3648*2736 30P
+ SENSOR_DRIVER_MODE_4TO3_12M_15P_RESOLUTION, // 4032*3024 15P
+ SENSOR_DRIVER_MODE_4TO3_12M_30P_RESOLUTION, // 4032*3024 30P
+ SENSOR_DRIVER_MODE_4TO3_14M_15P_RESOLUTION, // 4352*3264 15P
+
+ // Index 40
+ SENSOR_DRIVER_MODE_4TO3_14M_30P_RESOLUTION, // 4352*3264 30P
+ SENSOR_DRIVER_MODE_4K2K_24P_RESOLUTION,
+ SENSOR_DRIVER_MODE_PAL_25P_RESOLUTION,
+ SENSOR_DRIVER_MODE_NTSC_30P_RESOLUTION,
+
+ // For Camera Preview
+ SENSOR_DRIVER_MODE_BEST_CAMERA_PREVIEW_RESOLUTION,
+ SENSOR_DRIVER_MODE_BEST_CAMERA_CAPTURE_16TO9_RESOLUTION,
+ SENSOR_DRIVER_MODE_BEST_CAMERA_CAPTURE_4TO3_RESOLUTION,
+ SENSOR_DRIVER_MODE_FULL_HD_30P_RESOLUTION_HDR,
+} CUS_SNR_RESOLUTION;
+
+
+#ifdef __cplusplus
+extern "C"
+#endif
+/**@brief ISP sensor interface control API */
+typedef struct __ISensorIfAPI //isp sensor interface API
+{
+ /**@brief Reserved */
+ void* pdata;
+
+ /** @brief Set sensor power down pin.
+ @param[in] idx Sensor pad ID.
+ @param[in] pol pin polarity.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*PowerOff)(u32 idx, CUS_CLK_POL pol);
+
+ /** @brief Set sensor power reset pin.
+ @param[in] idx Sensor pad ID.
+ @param[in] pol pin polarity.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*Reset)(u32 idx, CUS_CLK_POL pol);
+
+ /** @brief Configure sensor master clock.
+ @param[in] idx Sensor pad ID.
+ @param[in] bONOFF Clock ON/OFF control.
+ @param[in] mclk Clock frequency Hz.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*MCLK)(u32 idx, u8 bONOFF, CUS_MCLK_FREQ mclk);
+
+ /** @brief Query sensor master clock.
+ @param[in] idx Sensor pad ID.
+ @param[in] mclk Query if clock frequency Hz is available.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*QueryMCLK)(u32 idx, CUS_MCLK_FREQ mclk);
+
+ /** @brief Query MIPI lane number.
+ @param[in] idx Sensor pad ID.
+ @param[in] lane_num Query max lane number.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*QueryLaneNum)(u32 idx, u8 *max_lane);
+#if 0
+ /** @brief Select pixel clock source
+ @remarks Parallel interface only
+ @param[in] handle Handle to sensor driver.
+ @param[in] pclk_source Clock source.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*PCLK)(CUS_PCLK_SOURCE pclk_source); //senect sensor
+
+ /** @brief Configure HSYNC pin polarity.
+ @remarks Parallel interface only
+ @param[in] handle Handle to sensor driver.
+ @param[in] pol pin polarity.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*HsyncPol)(CUS_CLK_POL pol);
+
+ /** @brief [parallel interface only] Configure VSYNC pin polarity.
+ @param[in] handle Handle to sensor driver.
+ @param[in] pol pin polarity.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*VsyncPol)(CUS_CLK_POL pol);
+
+ /** @brief Configure PCLK pin polarity.
+ @param[in] handle Handle to sensor driver.
+ @param[in] pol pin polarity.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*ClkPol)(CUS_CLK_POL pol);
+
+ /** @brief Configure sensor bayer raw pixel order
+ @param[in] handle Handle to sensor driver.
+ @param[in] bayer_id Select pixel order
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*BayerFmt)(CUS_SEN_BAYER bayer_id);
+
+ /** @brief Configure sensor RGBIR (8 or 10bits) convert to 12bit bits isp input, This config will be ignore for 12/16 bits sensor bayer raw input.
+ @param[in] handle Handle to sensor driver.
+ @param[in] mode Mode select
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*FmtConv)(CUS_SEN_FMT_CONV_MODE mode);
+
+ /** @brief Select sensor image data interface
+ @param[in] handle Handle to sensor driver.
+ @param[in] bus Sensor interface
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*DataBus)(CUS_SENIF_BUS bus);
+
+ /** @brief Configure sensor bayer raw pixel bits
+ @param[in] handle Handle to sensor driver.
+ @param[in] prec Select pixel bits
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*DataPrecision)(CUS_DATAPRECISION prec);
+
+ /** @brief Wait isp frame start event
+ @param[in] handle Handle to sensor driver.
+ @param[in] ms Max timeout in ms
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*WaitVStart)(int ms);
+
+ /** @brief Wait isp frame end event
+ @param[in] handle Handle to sensor driver.
+ @param[in] ms Max timeout in ms
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*WaitVEnd)(int ms);
+
+ /** @brief Configure 3A task order table
+ @param[in] handle Handle to sensor driver.
+ @param[in] tasks Task order table
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*Set3ATaskOrder)(CUS_INT_TASK_ORDER tasks);
+#endif
+ /** @brief Select sensor IO pin assignment
+ @param[in] idx Sensor pad ID.
+ @param[in] ulSnrType Interface type.
+ @param[in] ulSnrPadCfg Pin config.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetIOPad)(u32 idx, CUS_SENIF_BUS ulSnrType, u32 ulSnrPadCfg);
+
+ //FOR CSI
+
+ /** @brief Set maximum mipi data rate (amount of all lans)
+ @remarks MIPI interface only.
+ @param[in] idx Sensor pad ID.
+ @param[in] clk Max data rate.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetCSI_Clk)(u32 idx, CUS_CSI_CLK clk);
+
+ /** @brief Set number of MIPI lanes
+ @remarks MIPI interface only.
+ @param[in] idx Sensor pad ID.
+ @param[in] num_lan Number of lanes.
+ @param[in] bon_off Clock ON/OFF control.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetCSI_Lane)(u32 idx, u16 num_lan, u8 bon_off);
+
+ /** @brief Enable long packet type
+ @remarks MIPI interface only
+ @param[in] idx Sensor pad ID.
+ @param[in] ctl_cfg0_15 Control flag bit[0:15]
+ @param[in] ctl_cfg16_31 Control flag bit[16:31]
+ @param[in] ctl_cfg32_47 Control flag bit[32:47]
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetCSI_LongPacketType)(u32 idx, u16 ctl_cfg0_15, u16 ctl_cfg16_31, u16 ctl_cfg32_47);
+
+ /** @brief Virtual channel0 hsync mode
+ @remarks MIPI interface only
+ @param[in] idx Sensor pad ID.
+ @param[in] mode HSYNC mode.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetCSI_VC0HSmode)(CUS_CSI_VC_HS_MODE mode);
+
+ /** @brief Configure MIPI capture start timing
+ @remarks MIPI interface only
+ @param[in] idx Sensor pad ID.
+ @param[in] rx_clk_skip_ns
+ @param[in] rx_data_skip_ns
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetCSI_clk_data_skip)(u32 idx, u8 rx_clk_skip_ns,u8 rx_data_skip_ns);
+
+ /** @brief Configure MIPI hdr mode
+ @remarks MIPI interface only
+ @param[in] idx Sensor pad ID.
+ @param[in] hdr_mode HDR mode.
+ @param[in] bon_off Clock ON/OFF control.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetCSI_hdr_mode)(u32 idx, CUS_HDR_MODE hdr_mode, u8 bon_off);
+
+#if 0
+ /** @brief Configure sensor RGBIR raw pixel order
+ @param[in] handle Handle to sensor driver.
+ @param[in] bayer_id Select pixel order
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*RGBIRFmt)(CUS_SEN_RGBIR RGBIR_id);
+
+ /** @brief Skip input frame
+ @param[in] handle Handle to sensor driver.
+ @param[in] number of frames to skip
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*SetSkipFrame)(int cnt);
+#endif
+}ISensorIfAPI;
+
+typedef union {
+ //Parallel sensor
+ struct {
+ u32 parallel_reserved; //No additional attribute.
+ } attr_parallel;
+
+ //MIPI sensor
+ struct {
+ u32 mipi_lane_num;
+ u32 mipi_data_format; //0: YUV 422 format. 1: RGB pattern.
+ u32 mipi_yuv_order; //YUYV or UYVY
+ u32 mipi_hsync_mode;
+ u32 mipi_sampling_delay; /** < MIPI start sampling delay */ /*bit 0~7: clk_skip_ns. bit 8~15: data_skip_ns*/
+ CUS_HDR_MODE mipi_hdr_mode;
+ u32 mipi_hdr_virtual_channel_num;
+ } attr_mipi;
+
+ //BT656 sensor
+ struct {
+ u32 bt656_total_ch;
+ u32 bt656_cur_ch;
+ u32 bt656_ch_det_en;
+ CUS_VIF_BT656_CHANNEL_SELECT bt656_ch_det_sel;
+ u32 bt656_bit_swap;
+ u32 bt656_8bit_mode;
+ CUS_VIF_BT656_VSYNC_DELAY bt656_vsync_delay;
+ u32 bt656_hsync_inv;
+ u32 bt656_vsync_inv;
+ u32 bt656_clamp_en;
+ } attr_bt656;
+} InterfaceAttr_u;
+
+
+///////////////////////////////////////////////////////
+
+/** @brief Sensor driver interface \n
+The function here are implemented by sensor driver.
+*/
+typedef struct __ms_cus_sensor{
+ short lib_idx; /**< Reserved , Do not use */
+ char model_id[32]; /**< Please fill the sensor modle id string here then libcamera user can read model_id by using cameraGetSensorModelID() .*/
+ void *sen_handle; /**< Reserved , Do not use */
+ void *private_data;/**< sensor driver dependent variables should store in private_data and free when release */
+
+ app_i2c_cfg i2c_cfg; /**< Sensor i2c setting */
+ i2c_handle_t *i2c_bus; /**< Handle to sensor i2c API. */
+ ISensorIfAPI sensor_if_api; /**< sensor interface API */
+ // ae parameters
+ int ae_gain_delay; /**< How many frame delay from writing AE gain to take effect*/
+ int ae_shutter_delay;/**< How many frame delay from writing AE shutter to take effect*/
+
+ int ae_gain_ctrl_num;
+ int ae_shutter_ctrl_num;
+
+ // polarity
+ CUS_CLK_POL reset_POLARITY; /** < Sensor REST pin polarity */
+ CUS_CLK_POL pwdn_POLARITY; /** < Sensor Power Down pin polarity */
+ CUS_CLK_POL VSYNC_POLARITY; /** < Sensor VSYNC polarity */
+ CUS_CLK_POL HSYNC_POLARITY; /** < Sensor HSYNC pin polarity */
+ CUS_CLK_POL PCLK_POLARITY; //** < Sensor Plxel Clock pin polarity */
+
+ // sensor data
+ CUS_CAMSENSOR_ISPTYPE isp_type; /** < Always use ISP_EXT */
+ CUS_SEN_BAYER bayer_id; /** < Sensor bayer raw pixel order */
+ CUS_SEN_RGBIR RGBIR_id; /** < Sensor bayer raw pixel order */
+ CUS_SENIF_BUS sif_bus; /** < Select sensor interface */
+ CUS_DATAPRECISION data_prec; /** < Raw data bits */
+ CUS_SEN_FMT_CONV_MODE data_mode; /** < Data convert mode*/
+ CUS_CAMSENSOR_ORIT orient; /** < Sensor mirror/flip */
+ u32 mclk; /** < Sensor master clock frequency */
+
+ cus_camsensor_res_list video_res_supported; /** < Resolution list */
+ //sensor calibration
+ u32 sat_mingain; /**< Minimum AE gain */
+
+ CUS_SENSOR_PAD_GROUP snr_pad_group;
+ u32 channel_num; //Which VIF/ISP channel is occupied.
+ u32 channel_mode; //real-time, RAW store, HDR...
+
+ InterfaceAttr_u interface_attr;
+
+ ////////////////////////////////////////////////
+ // system functions
+ ////////////////////////////////////////////////
+
+ /** @brief Sensor power on sequence, I2C must be ready after calling this function
+ @param[in] handle Handle to sensor driver.
+ @remark Following configuration need to set up at this stage \n
+ @ref __ISensorIfAPI::Reset Reset sensor \n
+ @ref __ISensorIfAPI::PowerOff Sensor power down pin \n
+ @ref __ISensorIfAPI::MCLK Sensor master clock \n
+ @ref __ISensorIfAPI::SetIOPad ISP sensor IO \n
+ @ref __ISensorIfAPI::SetCSI_Clk [MIPI sensor only] MIPI clock\n
+ @ref __ISensorIfAPI::HsyncPol Hsync polarity\n
+ @ref __ISensorIfAPI::VsyncPol Vsync polarity\n
+ @ref __ISensorIfAPI::ClkPol [Parallel sensor only] Pixel clock polarity\n
+ @ref __ISensorIfAPI::BayerFmt Raw data format\n
+ @ref __ISensorIfAPI::DataPrecision Raw data pixel bits\n
+ @ref __ISensorIfAPI::FmtConv Raw data to ISP pixel convert\n
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_poweron)(struct __ms_cus_sensor* handle, u32 idx);
+
+ /** @brief Sensor power off
+ @param[in] handle Handle to sensor driver.
+ @retval SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_poweroff)(struct __ms_cus_sensor* handle, u32 idx);
+
+ /** @brief Sensor initialization
+ @param[in] handle Handle to sensor driver.
+ @retval SUCCESS or FAIL if error occurs.
+ @remark Fill sensor initial table here, Sensor beginning to output raw images after calling this function .
+ */
+ int (*pCus_sensor_init)(struct __ms_cus_sensor* handle);
+
+ /** @brief Release resources those allocated in cus_camsensor_init_handle()
+ @param[in] handle Handle to sensor driver.
+ @retval SUCCESS or FAIL if error occurs.
+ @remark Release resource allocated in \ref cus_camsensor_init_handle
+ */
+ int (*pCus_sensor_release)(struct __ms_cus_sensor* handle);
+
+ /** @brief Enter sensor suspend mode
+ @param[in] handle Handle to sensor driver.
+ @retval SUCCESS or FAIL if error occurs.
+ @remark ISP call this function before enter power saving mode
+ */
+ int (*pCus_sensor_suspend)(struct __ms_cus_sensor* handle);
+
+ /** @brief Sensor wakeup
+ @param[in] handle Handle to sensor driver.
+ @retval SUCCESS or FAIL if error occurs.
+ @remark ISP call this function after exit power saving mode
+ */
+ int (*pCus_sensor_resume)(struct __ms_cus_sensor* handle);
+
+ /** @brief Enable sensor pattern mode if sensor hardward supported
+ @param[in] handle Handle to sensor driver.
+ @param[in] mode Pattern select, if 0 disable pattern mode.
+ @retval SUCCESS or FAIL if error occurs.
+ @remark This function is optional
+ */
+ int (*pCus_sensor_SetPatternMode)(struct __ms_cus_sensor* handle,u32 mode);
+
+ // Normal
+
+ /** @brief Check sensor ID and report to ISP sensor match or not
+ @param[in] handle Handle to sensor driver.
+ @param[out] id Receive 4 bytes customer defined sensor ID.
+ @retval Return SUCCESS if sensor matched or Retuen FAIL if sensor mismatch.
+ @remark Read sensor ID through I2C
+ */
+ int (*pCus_sensor_GetSensorID)(struct __ms_cus_sensor* handle, u32 *id);
+
+ /** @brief Get resolution list
+ @param[in] handle Handle to sensor driver.
+ @param[out] id Receive supported resolution list
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_GetVideoRes)(struct __ms_cus_sensor* handle, u32 res_idx, cus_camsensor_res **res);
+
+ /** @brief Get resolution list
+ @param[in] handle Handle to sensor driver.
+ @param[out] id Receive supported resolution list
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_GetCurVideoRes)(struct __ms_cus_sensor* handle, u32 *cur_idx, cus_camsensor_res **res);
+
+ /** @brief Select a sensor output resolution sensor list
+ @param[in] handle Handle to sensor driver.
+ @param[in] res_id Resolution id
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_SetVideoRes)(struct __ms_cus_sensor* handle, u32 res_id);
+
+ /** @brief Get sensor current mirror flip setting
+ @param[in] handle Handle to sensor driver.
+ @param[out] ori Receive Mirror/Flip setting.
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_GetOrien)(struct __ms_cus_sensor* handle, CUS_CAMSENSOR_ORIT *ori);
+
+ /** @brief Select a sensor mirror flip
+ @param[in] handle Handle to sensor driver.
+ @param[in] ori Mirror/Flip configuration.
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_SetOrien)(struct __ms_cus_sensor* handle, CUS_CAMSENSOR_ORIT ori);
+
+ /** @brief Get sensor capability
+ @param[in] handle Handle to sensor driver.
+ @param[out] cap Receive sensor capability
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_GetSensorCap)(struct __ms_cus_sensor* handle, CUS_CAMSENSOR_CAP *cap);
+
+ ///////////////////////////////////////////////////////
+ // AE
+ ///////////////////////////////////////////////////////
+ // unit: micro seconds
+
+ /** @brief AE/Frame status change notification
+ @param[in] handle Handle to sensor driver.
+ @param[in] status Current status
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_AEStatusNotify)(struct __ms_cus_sensor* handle, CUS_CAMSENSOR_AE_STATUS_NOTIFY status);
+
+ /** @brief Get sensor shutter setting in us
+ @param[in] handle Handle to sensor driver.
+ @param[out] us Receive current shutter setting
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_GetAEUSecs)(struct __ms_cus_sensor* handle, u32 *us);
+
+ /** @brief Set sensor shutter in us
+ @param[in] handle Handle to sensor driver.
+ @param[in] us Shutter setting in us
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_SetAEUSecs)(struct __ms_cus_sensor* handle, u32 us);
+
+ // Gain: 1x = 1024
+ /** @brief Get sensor current AE gain
+ @param[in] handle Handle to sensor driver.
+ @param[out] gain Receive current AE gain
+ @retval Return SUCCESS or FAIL if error occurs.
+ @remark gain: 1x = 1024
+ */
+ int (*pCus_sensor_GetAEGain)(struct __ms_cus_sensor* handle, u32* gain);
+
+ /** @brief Set sensor AE gain
+ @param[in] handle Handle to sensor driver.
+ @param[in] gain AE gain
+ @retval Return SUCCESS or FAIL if error occurs.
+ @remark gain: 1x = 1024
+ */
+ int (*pCus_sensor_SetAEGain)(struct __ms_cus_sensor* handle, u32 gain);
+
+ /** @brief Get supported shutter range
+ @param[in] handle Handle to sensor driver.
+ @param[out] min Receive minimum shutter which sensor can supported
+ @param[out] min Receive maxiimum shutter which sensor can supported
+ @retval Return SUCCESS or FAIL if error occurs.
+ @remark gain: 1x = 1024
+ */
+ int (*pCus_sensor_GetAEMinMaxUSecs)(struct __ms_cus_sensor* handle, u32 *min, u32 *max);
+
+ /** @brief Get supported AE gain range
+ @param[in] handle Handle to sensor driver.
+ @param[out] min Receive minimum gain which sensor can supported
+ @param[out] min Receive maxiimum gain which sensor can supported
+ @retval Return SUCCESS or FAIL if error occurs.
+ @remark gain: 1x = 1024
+ */
+ int (*pCus_sensor_GetAEMinMaxGain)(struct __ms_cus_sensor* handle, u32 *min, u32 *max);
+
+ // frame rate control
+ /** @brief Get current fps
+ @param[in] handle Handle to sensor driver.
+ @retval Return current frame rate per second
+ */
+ int (*pCus_sensor_GetFPS)(struct __ms_cus_sensor* handle);
+
+ /** @brief Set sensor output fps
+ @param[in] handle Handle to sensor driver.
+ @param[in] fps
+ @retval Return SUCCESS or FAIL if fps is out of range.
+ */
+ int (*pCus_sensor_SetFPS)(struct __ms_cus_sensor* handle, u32 fps);
+
+ //[OPTIONAL] sensor calibration
+ /** @brief Optional function */
+ int (*pCus_sensor_SetAEGain_cal)(struct __ms_cus_sensor* handle, u32);
+
+ /** @brief Optional function */
+ int (*pCus_sensor_setCaliData_gain_linearity)(struct __ms_cus_sensor* handle, CUS_GAIN_GAP_ARRAY* pArray ,u32 num);
+
+ //Get shutter information
+ /** @brief Get shutter information
+ @param[in] handle Handle to sensor driver.
+ @param[out] info return shutter information.
+ @retval Return current frame rate per second
+ */
+ int (*pCus_sensor_GetShutterInfo)(struct __ms_cus_sensor* handle,CUS_SHUTTER_INFO *info);
+
+ /** @brief Get resolution list number
+ @param[in] handle Handle to sensor driver.
+ @param[out] ulres_num resolution list number
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_GetVideoResNum)(struct __ms_cus_sensor* handle, u32 *ulres_num);
+
+ //Get shutter information
+ /** @brief Sensor vendor command
+ @param[in] handle Handle to sensor driver.
+ @param[in] reserved
+ @param[in] param Command input
+ @param[out] out Command output
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_CustDefineFunction)(struct __ms_cus_sensor* handle,u32 cmd_id, void *param);
+
+ //Get Source Type
+ /** @brief Get Source Type
+ @param[in] handle Handle to sensor driver.
+ @param[out] psrc_type info
+ @retval Return SUCCESS or FAIL if error occurs.
+ */
+ int (*pCus_sensor_GetSrcType)(struct __ms_cus_sensor* handle, CUS_SNR_ANADEC_SRC_TYPE *psrc_type);
+
+} ms_cus_sensor;
+
+/** @brief Sensor driver entry. ISP call this function before start using sensor driver. \n
+ISP pass \ref ms_cus_sensor struct to obtain the driver information and function entries. \n
+And all allocated resources here should be released at \ref __ms_cus_sensor::pCus_sensor_release.
+Every sensor driver must implement this api.
+@param[in] drv_handle A uninitialized \ref ms_cus_sensor struct from ISP, Sensor driver fill the driver information and function entries to drv_handle.
+@retval SUCCESS or FAIL if error occurs.
+*/
+
+typedef int (*SensorInitHandle)(ms_cus_sensor* handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DRV_MS_CUS_SENSOR_H_ */
+/** @} */ // end of ISP Sensor Driver Interface
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/sensor_i2c_api.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/sensor_i2c_api.h
new file mode 100644
index 00000000..7463bddf
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/sensor_i2c_api.h
@@ -0,0 +1,161 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*! @file isp_i2c_api.h
+ @brief This file contains Infinity ISP I2C basic API.
+*/
+
+/** @defgroup group1 ISP I2C API
+* @{
+*/
+
+#ifndef ISP_I2C_API_H
+#define ISP_I2C_API_H
+
+#define SENSOR_I2C_SUCCESS (0)
+#define SENSOR_I2C_FAIL (-1)
+#define SENSOR_I2C_NOT_SUPPORT (-2)
+
+/*! @brief I2C API handle.*/
+struct __i2c_handle_t;
+
+/*! @brief I2C batch read/write data.*/
+typedef struct _I2C_ARRAY{
+ u16 reg; /**< Register address.*/
+ u16 data; /**< Data.*/
+} I2C_ARRAY;
+
+/*! @brief I2C burst read/write data.*/
+typedef struct _I2C_ARRAY_BURST{
+ u16 reg; /**< Register address.*/
+ u16 *data; /**< Data.*/
+} I2C_ARRAY_BURST;
+
+/*! @brief I2C data direction*/
+typedef enum {
+ I2C_RW_R, /**< Data direction read.*/
+ I2C_RW_W,/**< Data direction write.*/
+} I2C_RW;
+
+/*! @brief Use for i2c_array_rw only */
+typedef struct _I2C_CPX_ARRAY{
+ I2C_RW rw; /**< Data direction */
+ u16 reg; /**< Device register address */
+ u16 data; /**< Data write to device or read from device*/
+}__attribute__((packed, aligned(1))) I2C_CPX_ARRAY;
+
+/*! @brief Internal use for I2C API*/
+typedef enum {
+ I2C_FMT_A8D8, /**< 8 bits Address, 8 bits Data */
+ I2C_FMT_A16D8,/**< 16 bits Address 8 bits Data */
+ I2C_FMT_A8D16,/**< 8 bits Address 16 bits Data */
+ I2C_FMT_A16D16,/**< 16 bits Address 16 bits Data */
+ I2C_FMT_END/**< Reserved */
+} ISP_I2C_FMT;
+
+/*! @brief ISP_I2C_MODE Internal use for I2C API*/
+typedef enum {
+ I2C_LEGACY_MODE, /**< Do not use */
+ I2C_NORMAL_MODE /**< Sensor driver can only use I2C_NORMAL_MODE */
+} ISP_I2C_MODE;
+
+
+/*! @brief app_i2c_cfg I2C setting for sensor and bus.*/
+typedef struct _app_i2c_cfg{
+ ISP_I2C_MODE mode; //!< I2C_NORMAL_MODE only
+ ISP_I2C_FMT fmt; //!< I2C data format
+ u32 speed; //!< I2C clock in Hz
+ u16 address; //!< Sensor slave address , bit[7~1] are available, bit[0] user don't care
+ u16 reserved;
+}__attribute__((packed, aligned(1))) app_i2c_cfg;
+
+/*! @brief The interface of I2C APIs export to user*/
+typedef struct _i2c_handle_t {
+ int version;
+ void *pdata; //i2c_private_data
+
+ u32 nSensorID;
+ /** @brief Open isp i2c port. This function must be called before using isp I2C APIs.
+ Call i2c_close to close isp i2c port and allocated resource.
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C initial configuration.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_open)(struct _i2c_handle_t* handle, app_i2c_cfg *cfg);
+
+ /** @brief Close isp I2C port. Call this functon to release resource which allocated form i2c_open.
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C configuration mode and spped are necessary in this stage.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_close)(struct _i2c_handle_t* handle );
+
+ /** @brief Write single data to device.
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C config, fmd and address are necessary in this stage.
+ @param[in] reg Device register address address width depend on cfg->fmt.
+ @param[in] data Data to write, data width depend on cfg->fmt.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_tx)(struct _i2c_handle_t* handle , app_i2c_cfg cfg, short reg, short data);
+
+ /** @brief Read single data from device.
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C config, fmd and address are necessary in this stage.
+ @param[in] reg Device register address address width depend on cfg->fmt.
+ @param[out] data Data buffer for read, data width depend on cfg->fmt.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_rx)(struct _i2c_handle_t* handle, app_i2c_cfg cfg, short reg, volatile short *data);
+
+ /** @brief Batch write to device.
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C config, fmd and address are necessary in this stage.
+ @param[in] pdata Data array.
+ @param[in] len Array size.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_array_tx)(struct _i2c_handle_t* handle, app_i2c_cfg cfg, I2C_ARRAY *pdata, int len);
+
+ /** @brief Burst write to device.
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C config, fmd and address are necessary in this stage.
+ @param[in] pdata Data array.
+ @param[in] len Array size.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_burst_tx)(struct _i2c_handle_t* handle, app_i2c_cfg cfg, I2C_ARRAY_BURST *pdata, int len);
+
+ /** @brief Batch read from device.
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C config, fmd and address are necessary in this stage.
+ @param[out] pdata Data array.
+ @param[in] len Array size.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_array_rx)(struct _i2c_handle_t* handle, app_i2c_cfg cfg, I2C_ARRAY *pdata, int len);
+
+ /** @brief Composite batch read/write
+ @param[in] handle Handle to isp i2c api.
+ @param[in] cfg I2C config, fmd and address are necessary in this stage.
+ @param[in][out] pdata Data description array.
+ @param[in] len Array size.
+ @retval SENSOR_I2C_SUCCESS or SENSOR_I2C_FAIL if error occurs.
+ */
+ int (*i2c_array_rw)(struct _i2c_handle_t* handle, app_i2c_cfg cfg, I2C_CPX_ARRAY *pdata, int len);
+} i2c_handle_t;
+
+/** @} */ // end of ISP I2C API
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp.h
new file mode 100644
index 00000000..727da047
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp.h
@@ -0,0 +1,111 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_H_
+#define _MI_ISP_H_
+//#include <pthread.h>
+
+#include "mi_common.h"
+#include "mi_isp_datatype.h"
+#include "mi_vpe_datatype.h"
+#include "mi_isp_iq.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MI_ISP_OK (0)
+#define MI_ISP_NOT_SUPPORT (1)
+#define MI_ISP_FAILURE (-1)
+#define MI_ISP_API_MAX_PARM_NUMBRE (6)
+#define MI_ISP_API_ISPMID_NOT_SUPPORT (5)
+
+ /************************************* Customer 3A API ***********************************/
+ MI_S32 MI_ISP_AE_GetAeHwAvgStats(MI_U32 Channel, MI_ISP_AE_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AWB_GetAwbHwAvgStats(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AWB_GetAwbHwAvgStatsShort(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetHisto0HwStats(MI_U32 Channel, MI_ISP_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetHisto1HwStats(MI_U32 Channel, MI_ISP_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetRgbIrHistoHwStats(MI_U32 Channel, MI_ISP_RGBIR_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_CUS3A_Enable(MI_U32 Channel, Cus3AEnable_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAeInitStatus(MI_U32 Channel, CusAEInitParam_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAeStatus(MI_U32 Channel, CusAEInfo_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAeParam(MI_U32 Channel, CusAEResult_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAwbStatus(MI_U32 Channel, CusAWBInfo_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAwbParam(MI_U32 Channel, CusAWBResult_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAEWindowBlockNumber(MI_U32 Channel, MS_CUST_AE_WIN_BLOCK_NUM_TYPE_e *data);
+ MI_S32 MI_ISP_CUS3A_SetAEHistogramWindow(MI_U32 Channel, CusAEHistWin_t*data);
+ MI_S32 MI_ISP_CUS3A_SetAWBSampling(MI_U32 Channel, CusAWBSample_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAECropSize(MI_U32 Channel, CusAEAWBCropSize_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAWBCropSize(MI_U32 Channel, CusAEAWBCropSize_t *data);
+
+ MI_S32 MI_ISP_CUS3A_GetAFStats(MI_U32 Channel, CusAFStats_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFWindow(MI_U32 Channel, CusAFWin_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFWindow(MI_U32 Channel, CusAFWin_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFFilter(MI_U32 Channel, CusAFFilter_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFFilter(MI_U32 Channel, CusAFFilter_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFFilterSq(MI_U32 Channel, CusAFFilterSq_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFFilterSq(MI_U32 Channel, CusAFFilterSq_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFRoiMode(MI_U32 Channel, CusAFRoiMode_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFRoiMode(MI_U32 Channel, CusAFRoiMode_t *data);
+
+ MI_S32 MI_ISP_CUS3A_GetImageResolution(MI_U32 Channel, CusImageResolution_t *data);
+ MI_S32 MI_ISP_CUS3A_EnableISPOutImage(MI_U32 Channel, CusISPOutImage_t *data);
+ MI_S32 MI_ISP_CUS3A_GetISPOutImageCount(MI_U32 Channel, MI_U32 *data);
+ MI_S32 MI_ISP_CUS3A_CaptureHdrRawImage(MI_U32 Channel, CusHdrRawImage_t *data);
+ MI_S32 MI_ISP_GetFrameMetaInfo(MI_U32 Channel, IspFrameMetaInfo_t *data);
+ MI_S32 MI_ISP_ReadSensorData(MI_U32 Channel, CusSensorI2cParam_t *data);
+ MI_S32 MI_ISP_WriteSensorData(MI_U32 Channel, CusSensorI2cParam_t *data);
+ /************************************* Customer 3A API END********************************/
+ /************************************* Debug API ***********************************/
+ MI_S32 MI_ISP_SetDebugLevel_AE(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_GetDebugLevel_AE(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_SetDebugLevel_AWB(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_GetDebugLevel_AWB(MI_U32 Channel, MI_S32 *data);
+ /************************************* Debug API END********************************/
+
+ MI_S32 MI_ISP_SET_ALL(int Channel, MI_U16 ApiId, MI_U32 ApiLen, MI_U8* pApiBuf);
+ MI_S32 MI_ISP_GET_ALL(int Channel, MI_U16 ApiId, MI_U32* ApiLen, MI_U8* pApiBuf);
+
+ MI_S32 MI_ISP_API_CmdLoadBinFile(MI_U32 Channel, char* filepath, MI_U32 user_key);
+ MI_S32 MI_ISP_API_CmdLoadCaliData(MI_U32 Channel, MI_ISP_CALI_ITEM_e eCaliItem, char* filepath);
+
+ typedef MI_S32 (*MI_ISP_ApiAgent_fp)(MI_VPE_IspApiHeader_t *pstData, void* pData);
+
+ /*Api agent for SigmaStar user space 3A library*/
+ MI_S32 MI_ISP_RegisterIspApiAgent(MI_U32 Channel, MI_ISP_ApiAgent_fp fpApiSet, MI_ISP_ApiAgent_fp fpApiGet);
+#if !defined(DUAL_OS) && !defined(__RTOS__) //for pure linux
+ MI_S32 MI_ISP_EnableUserspace3A(MI_U32 Channel,MI_ISP_API_USERSPACE3A_ATTR_t *pAttr);
+ MI_S32 MI_ISP_DisableUserspace3A(MI_U32 Channel);
+#else //for DualOS-Linux , RTK
+ inline MI_S32 MI_ISP_EnableUserspace3A(MI_U32 Channel,MI_ISP_API_USERSPACE3A_ATTR_t *pAttr) {return 0;}
+ inline MI_S32 MI_ISP_DisableUserspace3A(MI_U32 Channel) {return 0;}
+#endif
+
+ /*Common API, get isp root path*/
+ MI_S32 MI_ISP_GetIspRoot(MI_U32 Channel, MI_ISP_ROOT_PATH_T *data);
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_3a_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_3a_datatype.h
new file mode 100644
index 00000000..0472f982
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_3a_datatype.h
@@ -0,0 +1,441 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_ISP_3A_DATATYPE_H_
+#define _MI_ISP_3A_DATATYPE_H_
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_FALSE = 0,
+ SS_TRUE = !SS_FALSE,
+ SS_BOOL_MAX
+} MI_ISP_BOOL_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_OP_TYP_AUTO = 0,
+ SS_OP_TYP_MANUAL = !SS_OP_TYP_AUTO,
+ SS_OP_TYP_MODE_MAX
+} MI_ISP_OP_TYPE_e;
+
+/************************************* AE - Define the structure declaration - START *************************************/
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_ISP_STATE_NORMAL = 0,
+ SS_ISP_STATE_PAUSE = 1,
+ SS_ISP_STATE_MAX
+} MI_ISP_SM_STATE_TYPE_e;
+
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_MODE_A, // auto
+ SS_AE_MODE_AV, // aperture priority
+ SS_AE_MODE_SV,
+ SS_AE_MODE_TV, // shutter priority
+ SS_AE_MODE_M, // manual mode
+ SS_AE_MODE_MAX
+} MI_ISP_AE_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_WEIGHT_AVERAGE = 0,
+ SS_AE_WEIGHT_CENTER,
+ SS_AE_WEIGHT_SPOT,
+ SS_AE_WEIGHT_MAX
+} MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_FLICKER_TYPE_DISABLE = 0,
+ SS_AE_FLICKER_TYPE_60HZ = 1,
+ SS_AE_FLICKER_TYPE_50HZ = 2,
+ SS_AE_FLICKER_TYPE_AUTO = 3,
+ //SS_AE_FLICKER_TYPE_DETECT_60HZ = 4,
+ //SS_AE_FLICKER_TYPE_DETECT_50HZ = 5,
+ SS_AE_FLICKER_TYPE_MAX
+} MI_ISP_AE_FLICKER_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_FLICKER_TYPE_DETECT_60HZ = 0,
+ SS_AE_FLICKER_TYPE_DETECT_50HZ = 1,
+ SS_AE_FLICKER_TYPE_DETECT_MAX
+} MI_ISP_AE_FLICKER_DETECT_TYPE_e;
+
+//typedef struct MI_ISP_AE_FLICKER_INFO_TYPE_s
+//{
+// MI_ISP_BOOL_e bIsEffective;
+// MI_ISP_AE_FLICKER_TYPE_e eFlickerType;
+// MI_U16 u16Score;
+//} MI_ISP_AE_FLICKER_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_FLICKER_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ MI_U8 u8AmpSensitivity; // 1 ~ 100
+ MI_U8 u8ScoreThd; // 1 ~ 100
+ MI_U8 uRefreshCycles; // 1 ~ 10
+ MI_U8 u8ValidTimesThd; // 1 ~ 10
+ MI_ISP_AE_FLICKER_DETECT_TYPE_e eFlickerType; // 60Hz = 0, 50Hz = 1
+} MI_ISP_AE_FLICKER_EX_TYPE_t;
+
+typedef struct MI_ISP_AE_FLICKER_EX_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsEffective;
+ MI_ISP_AE_FLICKER_DETECT_TYPE_e eFlickerType;
+ MI_U16 u16Score;
+} MI_ISP_AE_FLICKER_EX_INFO_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_BRIGHTTONE,
+ SS_AE_STRATEGY_DARKTONE,
+ SS_AE_STRATEGY_AUTO,
+ SS_AE_STRATEGY_MAX
+} MI_ISP_AE_STRATEGY_TYPE_e;
+
+typedef struct MI_ISP_AE_HIST_WEIGHT_Y_TYPE_s
+{
+ MI_U32 u32LumY;
+ MI_U32 u32AvgY;
+ MI_U32 u32Hits[128];
+} MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_VALUE_TYPE_s
+{
+ MI_U32 u32FNx10;
+ MI_U32 u32SensorGain;
+ MI_U32 u32ISPGain;
+ MI_U32 u32US;
+} MI_ISP_AE_EXPO_VALUE_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsStable;
+ MI_ISP_BOOL_e bIsReachBoundary;
+ MI_ISP_AE_EXPO_VALUE_TYPE_t stExpoValueLong;
+ MI_ISP_AE_EXPO_VALUE_TYPE_t stExpoValueShort;
+ MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t stHistWeightY;
+ MI_U32 u32LVx10;
+ MI_S32 s32BV;
+ MI_U32 u32SceneTarget;
+} MI_ISP_AE_EXPO_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_EV_COMP_TYPE_s
+{
+ MI_S32 s32EV;
+ MI_U32 u32Grad;
+} MI_ISP_AE_EV_COMP_TYPE_t;
+
+typedef struct MI_ISP_AE_INTP_LUT_TYPE_s
+{
+ MI_U16 u16NumOfPoints;
+ MI_U32 u32Y[16];
+ MI_U32 u32X[16];
+} MI_ISP_AE_INTP_LUT_TYPE_t;
+
+typedef struct CONV_SPEED_PARAM_s
+{
+ MI_U32 u32SpeedX[4];
+ MI_U32 u32SpeedY[4];
+} CONV_SPEED_PARAM_t;
+
+typedef struct CONV_THD_PARAM_s
+{
+ MI_U32 u32InThd;
+ MI_U32 u32OutThd;
+} CONV_THD_PARAM_t;
+
+typedef struct MI_ISP_AE_CONV_CONDITON_TYPE_s
+{
+ CONV_THD_PARAM_t stConvThrd;
+ CONV_SPEED_PARAM_t stConvSpeed;
+} MI_ISP_AE_CONV_CONDITON_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_LIMIT_TYPE_s
+{
+ MI_U32 u32MinShutterUS;
+ MI_U32 u32MaxShutterUS;
+ MI_U32 u32MinFNx10;
+ MI_U32 u32MaxFNx10;
+ MI_U32 u32MinSensorGain;
+ MI_U32 u32MinISPGain;
+ MI_U32 u32MaxSensorGain;
+ MI_U32 u32MaxISPGain;
+} MI_ISP_AE_EXPO_LIMIT_TYPE_t;
+
+typedef struct EXPO_POINT_PARAM_s
+{
+ MI_U32 u32FNumx10;
+ MI_U32 u32Shutter;
+ MI_U32 u32TotalGain;
+ MI_U32 u32SensorGain;
+} EXPO_POINT_PARAM_t;
+
+typedef struct MI_ISP_AE_EXPO_TABLE_TYPE_s
+{
+ MI_U32 u32NumPoints;
+ EXPO_POINT_PARAM_t stExpoTbl[16]; // LV from High to Low
+} MI_ISP_AE_EXPO_TABLE_TYPE_t;
+
+typedef struct WIN_WEIGHT_PARAM_s
+{
+ MI_U8 u8AverageTbl[32*32];
+ MI_U8 u8CenterTbl[32*32];
+ MI_U8 u8SpotTbl[32*32];
+} WIN_WEIGHT_PARAM_t;
+
+typedef struct MI_ISP_AE_WIN_WEIGHT_TYPE_s
+{
+ MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e eTypeID;
+ WIN_WEIGHT_PARAM_t stParaAPI;
+} MI_ISP_AE_WIN_WEIGHT_TYPE_t;
+
+typedef struct MI_ISP_AE_STRATEGY_TYPE_s
+{
+ MI_ISP_AE_STRATEGY_TYPE_e eAEStrategyMode;
+ MI_U32 u32Weighting;
+ MI_ISP_AE_INTP_LUT_TYPE_t stUpperOffset;
+ MI_ISP_AE_INTP_LUT_TYPE_t stLowerOffset;
+ MI_U32 u32BrightToneStrength;
+ MI_U32 u32BrightToneSensitivity;
+ MI_U32 u32DarkToneStrength;
+ MI_U32 u32DarkToneSensitivity;
+ MI_U32 u32AutoStrength;
+ MI_U32 u32AutoSensitivity;
+} MI_ISP_AE_STRATEGY_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_EX_BRIGHTTONE,
+ SS_AE_STRATEGY_EX_DARKTONE,
+} MI_ISP_AE_STRATEGY_EX_PRIORITY_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_EX_COUNT,
+ SS_AE_STRATEGY_EX_TARGET,
+} MI_ISP_AE_STRATEGY_EX_MODE_e;
+
+typedef struct MI_ISP_AE_STRATEGY_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_ISP_AE_STRATEGY_EX_MODE_e eMode;
+ MI_ISP_AE_STRATEGY_EX_PRIORITY_e ePriority;
+ MI_U16 u16BT_NodeNum;
+ MI_S32 u32BT_NodeBV[16];
+ MI_U32 u32BT_ThdY[16];
+ MI_U32 u32BT_Percentx10[16];
+ MI_U32 u32BT_TargetYx10[16];
+ MI_U32 u32BT_MaxOffsetDown[16];
+ MI_U16 u16DT_NodeNum;
+ MI_S32 u32DT_NodeBV[16];
+ MI_U32 u32DT_ThdY[16];
+ MI_U32 u32DT_Percentx10[16];
+ MI_U32 u32DT_TargetYx10[16];
+ MI_U32 u32DT_MaxOffsetUp[16];
+} MI_ISP_AE_STRATEGY_EX_TYPE_t;
+
+typedef struct MI_ISP_AE_STRATEGY_EX_INFO_TYPE_s
+{
+ MI_U16 u16GMBlendRatio;
+ MI_U16 u16UpperLimitTargetx10;
+ MI_U16 u16LowerLimitTargetx10;
+ MI_U16 u16BTCntPcntx10;
+ MI_U16 u16DTCntPcntx10;
+ MI_U16 u16BTYx10;
+ MI_U16 u16DTYx10;
+} MI_ISP_AE_STRATEGY_EX_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_RGBIR_AE_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16MaxYWithIR;
+ MI_U16 u16MinISPGainCompRatio;
+} MI_ISP_AE_RGBIR_AE_TYPE_t;
+
+typedef struct MI_ISP_AE_HDR_TYPE_s
+{
+ MI_ISP_AE_INTP_LUT_TYPE_t stAeHdrRatio;
+} MI_ISP_AE_HDR_TYPE_t;
+
+typedef struct MI_ISP_AE_STABILIZER_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16DiffThd;
+ MI_U16 u16Percent;
+} MI_ISP_AE_STABILIZER_TYPE_t;
+
+/************************************* AE - Define the structure declaration - END *************************************/
+
+/************************************* AWB - Define the structure declaration - START *************************************/
+
+#define MI_ISP_AWB_LV_CT_TBL_NUM (18)
+#define MI_ISP_AWB_CT_TBL_NUM (10)
+#define MI_ISP_AWB_WEIGHT_WIN_NUM (81)
+
+typedef struct MI_ISP_AWB_QUERY_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsStable;
+ MI_U16 u16Rgain;
+ MI_U16 u16Grgain;
+ MI_U16 u16Gbgain;
+ MI_U16 u16Bgain;
+ MI_U16 u16ColorTemp;
+ MI_U8 u8WPInd;
+ MI_ISP_BOOL_e bMultiLSDetected;
+ MI_U8 u8FirstLSInd;
+ MI_U8 u8SecondLSInd;
+} MI_ISP_AWB_QUERY_INFO_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_MODE_AUTO,
+ SS_AWB_MODE_MANUAL,
+ SS_AWB_MODE_CTMANUAL,
+ SS_AWB_MODE_MAX
+} MI_ISP_AWB_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_ALG_GRAYWORLD = 0,
+ SS_AWB_ALG_NORMAL = 1,
+ SS_AWB_ALG_BALANCE = 2,
+ SS_AWB_ALG_FOCUS = 3,
+ SS_AWB_ALG_MAX = 0xffffffff
+} MI_ISP_AWB_ALG_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_ADV_DEFAULT = 0,
+ SS_AWB_ADV_ADVANCE = 1,
+ SS_AWB_ADV_MAX = 0xffffffff
+} MI_ISP_AWB_ADV_TYPE_e;
+
+typedef struct CT_LIMIT_PARAM_s
+{
+ MI_U16 u16MaxRgain; //RW, Maximum RGain, Range: [0, 8191]
+ MI_U16 u16MinRgain; //RW, Miniimum RGain, Range: [0, 8191]
+ MI_U16 u16MaxBgain; //RW, Maximum BGain, Range: [0, 8191]
+ MI_U16 u16MinBgain; //RW, Miniimum BGain, Range: [0, 8191]
+} CT_LIMIT_PARAM_t;
+
+typedef struct CT_WEIGHT_PARAM_s
+{
+ MI_U16 u16Weight[MI_ISP_AWB_CT_TBL_NUM]; //RW, Light CT Weight, Range: [1, 255]
+} CT_WEIGHT_PARAM_t;
+
+typedef struct CT_RATIO_PARAM_s
+{
+ MI_U16 u16Ratio[MI_ISP_AWB_CT_TBL_NUM]; //RW, CT Prefer Ratio, Range: [1, 255]
+} CT_RATIO_PARAM_t;
+
+typedef struct AWB_ATTR_PARAM_s
+{
+ MI_U8 u8Speed; //RW, AWB converging speed, Range: [0x1, 0x64]
+ MI_U8 u8ConvInThd; //RW, AWB converging threshold, Range:[0, 255], Recommended: [32]
+ MI_U8 u8ConvOutThd; //RW, AWB converging threshold, Range:[0, 255], Recommended: [64]
+ MI_ISP_AWB_ALG_TYPE_e eAlgType; //RW, AWB 0:GrayWorld, 1:Normal, 2:Balance 3,Focus
+ MI_ISP_AWB_ADV_TYPE_e eAdvType; //RW, AWB advance mode type
+ MI_U8 u8RGStrength; //RW, AWB adjust RG ratio, Range:[0, 255]
+ MI_U8 u8BGStrength; //RW, AWB adjust BG ratio, Range:[0, 255]
+ CT_LIMIT_PARAM_t stCTLimit; //RW, AWB limitation when envirnoment ct is out of boundary
+ CT_WEIGHT_PARAM_t stLvWeight[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB Lv Ct Weight, Range: [0, 255]
+ CT_RATIO_PARAM_t stPreferRRatio[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB prefer R gain, Range: [0, 255]
+ CT_RATIO_PARAM_t stPreferBRatio[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB prefer B gain, Range: [0, 255]
+ MI_U16 u16WpWeight[MI_ISP_AWB_CT_TBL_NUM];
+ MI_U32 u32WeightWin[MI_ISP_AWB_WEIGHT_WIN_NUM]; //RW, AWB region gain, Range: [0, 16]
+} AWB_ATTR_PARAM_t;
+
+typedef struct MWB_ATTR_PARAM_s
+{
+ MI_U16 u16Rgain; //RW, Multiplier for R color channel, Range: [0, 0x2000]
+ MI_U16 u16Grgain; //RW, Multiplier for Gr color channel, Range: [0, 0x2000]
+ MI_U16 u16Gbgain; //RW, Multiplier for Gb color channel, Range: [0, 0x2000]
+ MI_U16 u16Bgain; //RW, Multiplier for B color channel, Range: [0, 0x2000]
+} MWB_ATTR_PARAM_t;
+
+typedef struct MI_ISP_AWB_ATTR_TYPE_s
+{
+ MI_ISP_SM_STATE_TYPE_e eState;
+ MI_ISP_AWB_MODE_TYPE_e eOpType;
+ MWB_ATTR_PARAM_t stManualParaAPI;
+ AWB_ATTR_PARAM_t stAutoParaAPI;
+} MI_ISP_AWB_ATTR_TYPE_t;
+
+typedef struct AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_s
+{
+ MI_U16 u16WhiteRgain; //RW, RGain of white Point Location , Range: [256, 4095]
+ MI_U16 u16WhiteBgain; //RW, RGain of white Point Location , Range: [256, 4095]
+ MI_U8 u8AreaSize; //RW, Light Area Size , Range: [1, 32]
+ MI_ISP_BOOL_e bExclude; //RW, Include or exclude Uaer light Area, 0: include, 1:exclude
+} AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_t;
+
+typedef struct MI_ISP_AWB_ATTR_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bExtraLightEn;
+ AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_t stLightInfo[4];
+} MI_ISP_AWB_ATTR_EX_TYPE_t;
+
+typedef struct MI_ISP_AWB_MULTILS_LS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U8 u8Sensitive;
+ MI_U8 u8CaliStrength;
+ MI_U16 u16CcmForLow[9];
+ MI_U16 u16CcmForHigh[9];
+} MI_ISP_AWB_MULTILS_LS_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_WEIGHT_TYPE_s
+{
+ MI_U16 u16LvIndex;
+ CT_WEIGHT_PARAM_t stParaAPI;
+} MI_ISP_AWB_CT_WEIGHT_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_CALI_TYPE_s
+{
+ MI_U16 u16StartIdx; //RW, Light area start index, Range: [0, u2EndIdx]
+ MI_U16 u16EndIdx; //RW, Light area end index, Range: [u2StartIdx, 9]
+ MI_U16 u16CtParams[40]; //RW, Color temperature of calibration paramters , Range: [1, 1000]
+} MI_ISP_AWB_CT_CALI_TYPE_t;
+
+typedef struct MI_ISP_AWB_CUR_CT_CALI_TYPE_s
+{
+ MI_U16 u16CtParams[40]; //RW, Color temperature of calibration paramters , Range: [1, 1000]
+} MI_ISP_AWB_CUR_CT_CALI_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_STATISTICS_TYPE_s
+{
+ MI_U16 u16Width; //RW, Effective range
+ MI_U16 u16Height; //RW, Effective range
+ MI_U16 u16StatisX[5760]; //RW, Color Temperature Curve Domain Statistics X, max is 64x90
+ MI_U16 u16StatisY[5760]; //RW, Color Temperature Curve Domain Statistics Y, max is 64x90
+} MI_ISP_AWB_CT_STATISTICS_TYPE_t;
+
+typedef struct MI_ISP_AWB_HW_STATISTICS_TYPE_s
+{
+ MI_U8 u8AwbBuffer[34560]; // 128 * 90 * 3
+} MI_ISP_AWB_HW_STATISTICS_TYPE_t;
+
+typedef struct MI_ISP_AWB_CTMWB_PARAM_s
+{
+ MI_U32 u32CT;
+} MI_ISP_AWB_CTMWB_PARAM_t;
+
+/************************************* AWB - Define the structure declaration - END *************************************/
+
+#endif //_MI_ISP_3A_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_api_id.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_api_id.h
new file mode 100644
index 00000000..c1c14c5b
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_api_id.h
@@ -0,0 +1,302 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp_api_id.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _TUNINGSERVER_API_ID_H_
+#define _TUNINGSERVER_API_ID_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#define ID_API_COMMON_BASE (0x0000)
+#define ID_API_COMMON_END (0x0FFF)
+
+#if 0
+#define ID_API_ISP_BASE (0x1000)
+#define ID_API_ISP_END (0x1FFF)
+
+#define ID_API_CALIBRATION_20_BASE (0x2000)
+#define ID_API_CALIBRATION_20_END (0x22FF)
+
+#define ID_API_MAINTOOL_BASE (0x2300)
+#define ID_API_MAINTOOL_END (0x25FF)
+
+#define ID_API_PLUGIN_BASE (0x2600)
+#define ID_API_PLUGIN_END (0x28FF)
+#else
+#define ID_API_ISP_IQ_BASE (0x1000)
+#define ID_API_ISP_IQ_END (0x13FF)
+
+#define ID_API_ISP_AE_BASE (0x1400)
+#define ID_API_ISP_AE_END (0x17FF)
+
+#define ID_API_ISP_AWB_BASE (0x1800)
+#define ID_API_ISP_AWB_END (0x1BFF)
+
+#define ID_API_ISP_AF_BASE (0x1C00)
+#define ID_API_ISP_AF_END (0x1FFF)
+
+#define ID_API_ISP_OTHER_BASE (0x2000)
+#define ID_API_ISP_OTHER_END (0x23FF)
+
+#define ID_API_CALIBRATION_20_BASE (0x2400)
+#define ID_API_CALIBRATION_20_END (0x27FF)
+
+#define ID_API_MAINTOOL_BASE (0x2800)
+#define ID_API_MAINTOOL_END (0x2BFF)
+
+#define ID_API_PLUGIN_BASE (0x2C00)
+#define ID_API_PLUGIN_END (0x2DFF)
+
+#define ID_API_CUS3A_BASE (0x2E00)
+#define ID_API_CUS3A_END (0x2FFF)
+
+#define ID_API_DEBUG_LEVEL_BASE (0x2FFF)
+#define ID_API_DEBUG_LEVEL_END (0x3100)
+
+#define ID_API_RESERVED_BASE (0x3101)
+#define ID_API_RESERVED_END (0x3FFF)
+
+#endif
+
+#define ID_CHIP_I1 (0x6d65031B)
+#define ID_CHIP_I3 (0x6d65031C)
+#define ID_CHIP_I2 (0x6d65031D)
+#define ID_CHIP_I5 (0x6d65031E)
+#define ID_CHIP_I6 (0x6d650320)
+#define ID_CHIP_I6E (0x6d650321)
+#define ID_CHIP_I6B0 (0x6d650322)
+#define ID_CHIP_M5 (0x6d65031F)
+
+//================================================================
+// ID Defined : Common API
+//================================================================
+#define ID_API_COMMON_I2C_ACCESS ( ID_API_COMMON_BASE + 32 ) //SET_API_ID_MI_ISP_WriteI2C
+//#define ID_API_COMMON_QuerySensorInfo ( ID_API_COMMON_BASE + 33 ) //GET_API_ID_MI_ISP_QuerySensorInfo
+#define ID_API_COMMON_MIRROR ( ID_API_COMMON_BASE + 34 )
+#define ID_API_COMMON_ROTATE ( ID_API_COMMON_BASE + 35 )
+#define ID_API_COMMON_SENSOR_ID ( ID_API_COMMON_BASE + 36 )
+
+#define ID_API_COMMON_FileID ( ID_API_COMMON_BASE + 100 ) //I1 or I3 or I2 or I5 ...
+#define ID_API_COMMON_CHANNEL_ID ( ID_API_COMMON_BASE + 101 )
+#define ID_API_COMMON_ISPROOT ( ID_API_COMMON_BASE + 102 )
+
+//================================================================
+// ID Defined : ISP API
+//================================================================
+#define ID_API_ISP_IQ_VERSION_INFO ( ID_API_ISP_IQ_BASE + 1 ) // 1. 4097
+#define ID_API_ISP_IQ_PARAM_INIT_STATUS ( ID_API_ISP_IQ_BASE + 2 ) // 2. 4098
+#define ID_API_ISP_IQ_FAST_MODE ( ID_API_ISP_IQ_BASE + 3 ) // 3. 4099
+#define ID_API_ISP_IQ_COLORTOGRAY ( ID_API_ISP_IQ_BASE + 4 ) // 4. 4100
+#define ID_API_ISP_IQ_CONTRAST ( ID_API_ISP_IQ_BASE + 5 ) // 5. 4101
+#define ID_API_ISP_IQ_BRIGHTNESS ( ID_API_ISP_IQ_BASE + 6 ) // 6. 4102
+#define ID_API_ISP_IQ_LIGHTNESS ( ID_API_ISP_IQ_BASE + 7 ) // 7. 4103
+#define ID_API_ISP_IQ_RGBGAMMA ( ID_API_ISP_IQ_BASE + 8 ) // 8. 4104
+#define ID_API_ISP_IQ_YUVGAMMA ( ID_API_ISP_IQ_BASE + 9 ) // 9. 4105
+#define ID_API_ISP_IQ_SATURATION ( ID_API_ISP_IQ_BASE + 10 ) // 10. 4106
+#define ID_API_ISP_IQ_DEFOG ( ID_API_ISP_IQ_BASE + 11 ) // 11. 4107
+#define ID_API_ISP_IQ_CCM ( ID_API_ISP_IQ_BASE + 12 ) // 12. 4108
+#define ID_API_ISP_IQ_ANTI_FALSE_COLOR ( ID_API_ISP_IQ_BASE + 13 ) // 13. 4109
+#define ID_API_ISP_IQ_NR3D ( ID_API_ISP_IQ_BASE + 14 ) // 14. 4110
+#define ID_API_ISP_IQ_NR2D_DESPIKE ( ID_API_ISP_IQ_BASE + 15 ) // 15. 4111
+#define ID_API_ISP_IQ_NR2D_LUMA ( ID_API_ISP_IQ_BASE + 16 ) // 16. 4112
+#define ID_API_ISP_IQ_NR2D_CHROMA ( ID_API_ISP_IQ_BASE + 17 ) // 17. 4113
+#define ID_API_ISP_IQ_SHARPNESS ( ID_API_ISP_IQ_BASE + 18 ) // 18. 4114
+#define ID_API_ISP_IQ_CROSSTALK ( ID_API_ISP_IQ_BASE + 19 ) // 19. 4115
+#define ID_API_ISP_IQ_BLACK_LEVEL ( ID_API_ISP_IQ_BASE + 20 ) // 20. 4116
+#define ID_API_ISP_IQ_BLACK_LEVEL_P1 ( ID_API_ISP_IQ_BASE + 21 ) // 21. 4117
+#define ID_API_ISP_IQ_WDR ( ID_API_ISP_IQ_BASE + 22 ) // 22. 4118
+#define ID_API_ISP_IQ_DEFECT_PIXEL ( ID_API_ISP_IQ_BASE + 23 ) // 23. 4119
+#define ID_API_ISP_IQ_HSV ( ID_API_ISP_IQ_BASE + 24 ) // 24. 4120
+#define ID_API_ISP_IQ_RGBIR ( ID_API_ISP_IQ_BASE + 25 ) // 25. 4121
+#define ID_API_ISP_IQ_FPN ( ID_API_ISP_IQ_BASE + 26 ) // 26. 4122
+#define ID_API_ISP_IQ_PFC ( ID_API_ISP_IQ_BASE + 27 ) // 27. 4123
+#define ID_API_ISP_IQ_DM ( ID_API_ISP_IQ_BASE + 28 ) // 28. 4124
+#define ID_API_ISP_IQ_COLOR_TRANSFORM ( ID_API_ISP_IQ_BASE + 29 ) // 29. 4125
+#define ID_API_ISP_IQ_HDR ( ID_API_ISP_IQ_BASE + 30 ) // 30. 4126
+#define ID_API_ISP_IQ_EFFECT ( ID_API_ISP_IQ_BASE + 31 ) // 31. 4127
+#define ID_API_ISP_IQ_SYS_MCNR_MEMORY ( ID_API_ISP_IQ_BASE + 32 ) // 32. 4128
+#define ID_API_ISP_IQ_LSC ( ID_API_ISP_IQ_BASE + 33 ) // 33. 4129
+#define ID_API_ISP_IQ_PARAM_MODE ( ID_API_ISP_IQ_BASE + 34 ) // 34. 4130
+#define ID_API_ISP_IQ_LinearityLUT ( ID_API_ISP_IQ_BASE + 35 ) // 35. 4131 //Get Gamma data for CCM calibration
+#define ID_API_ISP_IQ_OBCCALIB ( ID_API_ISP_IQ_BASE + 36 ) // 36. 4132 //Get OB data for Gamma or CCM calibration
+#define ID_API_ISP_IQ_NR3D_P1 ( ID_API_ISP_IQ_BASE + 37 ) // 37. 4133
+#define ID_API_ISP_IQ_WDR_FC_CURVE ( ID_API_ISP_IQ_BASE + 38 ) // 38. 4134
+#define ID_API_ISP_IQ_R2Y ( ID_API_ISP_IQ_BASE + 39 ) // 39. 4135
+#define ID_API_ISP_IQ_ALSC ( ID_API_ISP_IQ_BASE + 40 ) // 40. 4136
+#define ID_API_ISP_IQ_LSC_CTRL ( ID_API_ISP_IQ_BASE + 41 ) // 41. 4137
+#define ID_API_ISP_IQ_ALSC_CTRL ( ID_API_ISP_IQ_BASE + 42 ) // 42. 4138
+#define ID_API_ISP_IQ_DEFECT_PIXEL_CLUSTER ( ID_API_ISP_IQ_BASE + 43 ) // 43. 4139
+#define ID_API_ISP_IQ_QUERY_CCM_INFO ( ID_API_ISP_IQ_BASE + 44 ) // 44. 4140
+#define ID_API_ISP_IQ_NR2D_LUMA_ADV ( ID_API_ISP_IQ_BASE + 45 ) // 45. 4141
+#define ID_API_ISP_IQ_NR2D_CHROMA_ADV ( ID_API_ISP_IQ_BASE + 46 ) // 46. 4142
+#define ID_API_ISP_IQ_PFC_EX ( ID_API_ISP_IQ_BASE + 47 ) // 47. 4143
+#define ID_API_ISP_IQ_HDR_EX ( ID_API_ISP_IQ_BASE + 48 ) // 48. 4144
+#define ID_API_ISP_IQ_SHP_EX ( ID_API_ISP_IQ_BASE + 49 ) // 49. 4145
+#define ID_API_ISP_IQ_NR_3D_EX ( ID_API_ISP_IQ_BASE + 50 ) // 50. 4146
+#define ID_API_ISP_IQ_DUMMY ( ID_API_ISP_IQ_BASE + 51 ) // 51. 4147
+#define ID_API_ISP_IQ_DUMMY_EX ( ID_API_ISP_IQ_BASE + 52 ) // 52. 4148
+#define ID_API_ISP_IQ_WDR_FC_CURVE_FULL ( ID_API_ISP_IQ_BASE + 53 ) // 53. 4149
+#define ID_API_ISP_IQ_ADAPTIVE_GAMMA ( ID_API_ISP_IQ_BASE + 54 ) // 54. 4150
+#define ID_API_ISP_IQ_NR2D_CHROMA_PRE ( ID_API_ISP_IQ_BASE + 55 ) // 55. 4151
+#define ID_API_ISP_IQ_TEMP ( ID_API_ISP_IQ_BASE + 56 ) // 56. 4152
+#define ID_API_ISP_IQ_TEMP_INFO ( ID_API_ISP_IQ_BASE + 57 ) // 57. 4153
+
+#define ID_API_ISP_AE_HIST_WEIGHT_Y ( ID_API_ISP_AE_BASE + 1 ) // 1. 5121
+#define ID_API_ISP_AE_QUERY_EXPOSURE_INFO ( ID_API_ISP_AE_BASE + 2 ) // 2. 5122
+#define ID_API_ISP_AE_EV_COMP ( ID_API_ISP_AE_BASE + 3 ) // 3. 5123
+#define ID_API_ISP_AE_EXPO_MODE ( ID_API_ISP_AE_BASE + 4 ) // 4. 5124
+#define ID_API_ISP_AE_MANUAL_EXPO ( ID_API_ISP_AE_BASE + 5 ) // 5. 5125
+#define ID_API_ISP_AE_STATE ( ID_API_ISP_AE_BASE + 6 ) // 6. 5126
+#define ID_API_ISP_AE_TARGET ( ID_API_ISP_AE_BASE + 7 ) // 7. 5127
+#define ID_API_ISP_AE_CONVERGE ( ID_API_ISP_AE_BASE + 8 ) // 8. 5128
+#define ID_API_ISP_AE_EXPOSURE_LIMIT ( ID_API_ISP_AE_BASE + 9 ) // 9. 5129
+#define ID_API_ISP_AE_PLAIN_LONG_EXPO_TABLE ( ID_API_ISP_AE_BASE + 10 ) // 10. 5130
+#define ID_API_ISP_AE_PLAIN_SHORT_EXPO_TABLE ( ID_API_ISP_AE_BASE + 11 ) // 11. 5131
+#define ID_API_ISP_AE_WINDOW_WGT_MODE ( ID_API_ISP_AE_BASE + 12 ) // 12. 5132
+#define ID_API_ISP_AE_WINDOW_WGT ( ID_API_ISP_AE_BASE + 13 ) // 13. 5133
+#define ID_API_ISP_AE_FLICKER ( ID_API_ISP_AE_BASE + 14 ) // 14. 5134
+#define ID_API_ISP_AE_STRATEGY ( ID_API_ISP_AE_BASE + 15 ) // 15. 5135
+#define ID_API_ISP_AE_RGBIRExposureAttr ( ID_API_ISP_AE_BASE + 16 ) // 16. 5136
+#define ID_API_ISP_AE_HDR ( ID_API_ISP_AE_BASE + 17 ) // 17. 5137
+#define ID_API_ISP_AE_MANUAL_EXPO_SHORT ( ID_API_ISP_AE_BASE + 18 ) // 18. 5138
+#define ID_API_ISP_AE_FLICKER_EX ( ID_API_ISP_AE_BASE + 19 ) // 19. 5139
+#define ID_API_ISP_AE_QUERY_FLICKER_EX_INFO ( ID_API_ISP_AE_BASE + 20 ) // 20. 5140
+#define ID_API_ISP_AE_STABILIZER ( ID_API_ISP_AE_BASE + 21 ) // 21. 5141
+#define ID_API_ISP_AE_STRATEGY_EX ( ID_API_ISP_AE_BASE + 22 ) // 22. 5142
+#define ID_API_ISP_AE_QUERY_STRATEGY_EX_INFO ( ID_API_ISP_AE_BASE + 23 ) // 24. 5143
+
+#define ID_API_ISP_AWB_QUERY_WHITE_BALANCE_INFO ( ID_API_ISP_AWB_BASE + 1 ) // 1. 6145
+#define ID_API_ISP_AWB_ATTR ( ID_API_ISP_AWB_BASE + 2 ) // 2. 6146
+#define ID_API_ISP_AWB_ATTR_EX ( ID_API_ISP_AWB_BASE + 3 ) // 3. 6147
+#define ID_API_ISP_AWB_MULTI_LS_ATTR ( ID_API_ISP_AWB_BASE + 4 ) // 4. 6148
+#define ID_API_ISP_AWB_CT_WEIGHT ( ID_API_ISP_AWB_BASE + 5 ) // 5. 6149
+#define ID_API_ISP_AWB_CTMWB ( ID_API_ISP_AWB_BASE + 6 ) // 5. 6150
+
+//#define ID_API_ISP_AF_QUERY_FOCUS_INFO ( ID_API_ISP_AF_BASE + 1 ) // 1. 7169
+//#define ID_API_ISP_AF_WINDOW ( ID_API_ISP_AF_BASE + 2 ) // 2. 7170
+//#define ID_API_ISP_AF_FILTER ( ID_API_ISP_AF_BASE + 3 ) // 3. 7171
+
+
+//#define ID_API_VENC_RcParamEx ( ID_API_ISP_OTHER_BASE + 1 ) // 1. 8193 --> old ( ID_API_ISP_BASE + 35 ) //35. 4131
+//#define ID_API_VI_SensorFrameRate ( ID_API_ISP_OTHER_BASE + 2 ) // 2. 8194 --> old ( ID_API_ISP_BASE + 36 ) //36. 4132
+//#define ID_API_VENC_Resolution ( ID_API_ISP_OTHER_BASE + 3 ) // 3. 8195 --> old ( ID_API_ISP_BASE + 37 ) //37. 4133
+
+//================================================================
+// ID Defined : Calibration 2.0 API
+//================================================================
+#define ID_API_CALIBRATION_20_CaliBVAV ( ID_API_CALIBRATION_20_BASE + 1) // 1. 9217 //SET_API_ID_CALIBRATION_CaliBVAV = 61,
+#define ID_API_CALIBRATION_20_Apply ( ID_API_CALIBRATION_20_BASE + 2) // 2. 9218 //SET_API_ID_CALIBRATION_ApplyBVAV = 62,
+#define ID_API_CALIBRATION_20_CaliData ( ID_API_CALIBRATION_20_BASE + 3) // 3. 9219 //SET_API_ID_CALIBRATION_SetCaliData = 63,
+#define ID_API_CALIBRATION_20_CaliPath ( ID_API_CALIBRATION_20_BASE + 4) // 4. 9220 //SET_API_ID_CALIBRATION_SetCaliPath = 64,
+#define ID_API_CALIBRATION_20_CaliDBPath ( ID_API_CALIBRATION_20_BASE + 5) // 5. 9221 //SET_API_ID_CALIBRATION_SetCaliDBPath
+#define ID_API_CALIBRATION_20_CaliInfo ( ID_API_CALIBRATION_20_BASE + 6) // 6. 9222 //GET_API_ID_CALIBRATION_GetCaliInfo
+
+#define ID_API_CALIBRATION_20_CaliAWB ( ID_API_CALIBRATION_20_BASE + 7) // 7. 9223
+#define ID_API_CALIBRATION_20_CaliOB ( ID_API_CALIBRATION_20_BASE + 8) // 8. 9224
+#define ID_API_CALIBRATION_20_CaliMinGain ( ID_API_CALIBRATION_20_BASE + 9) // 9. 9225
+#define ID_API_CALIBRATION_20_CaliShutterLinearity ( ID_API_CALIBRATION_20_BASE + 10) // 10. 9226
+#define ID_API_CALIBRATION_20_CaliGainLinearity ( ID_API_CALIBRATION_20_BASE + 11) // 11 9227
+#define ID_API_CALIBRATION_20_CaliDPC ( ID_API_CALIBRATION_20_BASE + 12) // 12. 9228
+#define ID_API_CALIBRATION_20_CaliALSC ( ID_API_CALIBRATION_20_BASE + 13) // 13. 9229
+#define ID_API_CALIBRATION_20_CaliFPN ( ID_API_CALIBRATION_20_BASE + 14) // 14. 9230
+
+#define ID_API_CALIBRATION_30_ApplyAWB ( ID_API_CALIBRATION_20_BASE + 15) // 15. 9231
+#define ID_API_CALIBRATION_30_ApplyOBC ( ID_API_CALIBRATION_20_BASE + 16) // 16. 9232
+#define ID_API_CALIBRATION_30_ApplyMinGain ( ID_API_CALIBRATION_20_BASE + 17) // 17. 9233
+#define ID_API_CALIBRATION_30_ApplyShutterLinearity ( ID_API_CALIBRATION_20_BASE + 18) // 18. 9234
+#define ID_API_CALIBRATION_30_ApplyGainLinearity ( ID_API_CALIBRATION_20_BASE + 19) // 19 9235
+#define ID_API_CALIBRATION_30_ApplySDC ( ID_API_CALIBRATION_20_BASE + 20) // 20. 9236
+#define ID_API_CALIBRATION_30_ApplyALSC ( ID_API_CALIBRATION_20_BASE + 21) // 21. 9237
+#define ID_API_CALIBRATION_30_ApplyFPN ( ID_API_CALIBRATION_20_BASE + 22) // 22. 9238
+#define ID_API_CALIBRATION_30_ApplyLSC ( ID_API_CALIBRATION_20_BASE + 23) // 21. 9239
+
+//================================================================
+// ID Defined : MainTool API
+//================================================================
+#define ID_API_MAINTOOL_QUERY_SENSOR_INFO ( ID_API_MAINTOOL_BASE + 1 ) // 1. 10241
+#define ID_API_MAINTOOL_IQ_INDEX ( ID_API_MAINTOOL_BASE + 2 ) // 2. 10242
+#define ID_API_MAINTOOL_BYPASS ( ID_API_MAINTOOL_BASE + 3 ) // 3. 10243
+
+//================================================================
+// ID Defined : Plugin API
+//================================================================
+#define ID_API_PLUGIN_I2C_ACCESS ( ID_API_PLUGIN_BASE + 1 ) // 1. 11265 //SET_API_ID_MI_ISP_WriteI2C
+#define ID_API_PLUGIN_WBCT ( ID_API_PLUGIN_BASE + 3 ) // 3. 11267 //SetWBCTCaliAttr
+#define ID_API_PLUGIN_AWBCTStats ( ID_API_PLUGIN_BASE + 4 ) // 4. 11268
+#define ID_API_PLUGIN_AWBHWStats ( ID_API_PLUGIN_BASE + 5 ) // 5. 11269
+#define ID_API_PLUGIN_CUR_WBCT ( ID_API_PLUGIN_BASE + 6 ) // 6. 11270 //GetCurCTCaliAttr
+
+//================================================================
+// ID Defined : Cus3A API
+//================================================================
+#define ID_API_CUS_AE_HW_AVG_STATS ( ID_API_CUS3A_BASE + 1 ) // 1. 11777
+#define ID_API_CUS_AE_HW_HISTO_0_STATS ( ID_API_CUS3A_BASE + 2 ) // 2. 11778
+#define ID_API_CUS_AE_HW_HISTO_1_STATS ( ID_API_CUS3A_BASE + 3 ) // 3. 11779
+#define ID_API_CUS_AE_GET_INIT_STATUS ( ID_API_CUS3A_BASE + 4 ) // 4. 11780
+#define ID_API_CUS_AE_GET_CUR_STATUS ( ID_API_CUS3A_BASE + 5 ) // 5. 11781
+#define ID_API_CUS_AE_SET_PARAM ( ID_API_CUS3A_BASE + 6 ) // 6. 11782
+#define ID_API_CUS_AWB_HW_AVG_STATS ( ID_API_CUS3A_BASE + 7 ) // 7. 11783
+#define ID_API_CUS_3A_ENABLE ( ID_API_CUS3A_BASE + 8 ) // 8. 11784
+#define ID_API_CUS_AWB_GET_CUR_STATUS ( ID_API_CUS3A_BASE + 9 ) // 9. 11785
+#define ID_API_CUS_AWB_SET_PARAM ( ID_API_CUS3A_BASE + 10) //10. 11786
+#define ID_API_CUS_AE_WINDOW_BLOCK_NUMBER ( ID_API_CUS3A_BASE + 11 )//11. 11787
+#define ID_API_CUS_AWB_SAMPLING ( ID_API_CUS3A_BASE + 12 )//12. 11788
+#define ID_API_CUS_AF_STATS ( ID_API_CUS3A_BASE + 13 )//13. 11789
+#define ID_API_CUS_AF_WINDOW ( ID_API_CUS3A_BASE + 14 )//14. 11790
+#define ID_API_CUS_AF_FILTER ( ID_API_CUS3A_BASE + 15 )//15. 11791
+#define ID_API_CUS_AF_FILTER_SQUARE ( ID_API_CUS3A_BASE + 16 )//16. 11792
+#define ID_API_CUS_AF_MODE ( ID_API_CUS3A_BASE + 17 )//17. 11793
+#define ID_API_CUS_AE_HISTOGRAM_WINDOW ( ID_API_CUS3A_BASE + 18 )//18. 11794
+#define ID_API_CUS_GET_IMAGE_RESOLUTION ( ID_API_CUS3A_BASE + 19 )//19. 11795
+#define ID_API_CUS_ENABLE_ISP_OUT_IMAGE ( ID_API_CUS3A_BASE + 20 )//20. 11796
+#define ID_API_CUS_GET_ISP_OUT_IMAGE_COUNT ( ID_API_CUS3A_BASE + 21 )//21. 11797
+#define ID_API_CUS_CAPTURE_HDR_RAW_IMAGE ( ID_API_CUS3A_BASE + 22 )//22. 11798
+#define ID_API_CUS_FRAME_META_INFO ( ID_API_CUS3A_BASE + 23 )//23. 11799
+#define ID_API_CUS_I2C_ACCESS ( ID_API_CUS3A_BASE + 24 )//24. 11800
+#define ID_API_CUS_AWB_HW_AVG_STATS_SHORT ( ID_API_CUS3A_BASE + 25 ) // 25. 11801
+#define ID_API_CUS_CAPTURE_RAW_IMAGE ( ID_API_CUS3A_BASE + 26 )//26. 11802
+#define ID_API_CUS_CUSTOMER_AE_CTRL ( ID_API_CUS3A_BASE + 27 )//27. 11803 , Customer defined AE control only
+#define ID_API_CUS_CUSTOMER_AWB_CTRL ( ID_API_CUS3A_BASE + 28 )//28. 11804 , Customer defined AWB control only
+#define ID_API_CUS_CUSTOMER_AF_CTRL ( ID_API_CUS3A_BASE + 29 )//29. 11805 , Customer defined AF control only
+#define ID_API_CUS_AE_HW_RGBIR_HISTO_STATS ( ID_API_CUS3A_BASE + 30 ) // 30. 11806
+#ifdef ENABLE_EARLY_AE_DONE
+#define ID_API_CUS_AE_DONE_RATIO ( ID_API_CUS3A_BASE + 27 )//27. 11803
+#endif
+#define ID_API_CUS_AE_CROP_SIZE ( ID_API_CUS3A_BASE + 31 )//34. 11807
+#define ID_API_CUS_AWB_CROP_SIZE ( ID_API_CUS3A_BASE + 32 )//35. 11808
+
+//================================================================
+// ID Defined : Debug Level API
+//================================================================
+#define ID_API_ISP_DeBugLevel_AE ( ID_API_DEBUG_LEVEL_BASE + 1 ) // 1. 12288
+#define ID_API_ISP_DeBugLevel_AWB ( ID_API_DEBUG_LEVEL_BASE + 2 ) // 2. 12289
+#define ID_API_ISP_DeBugLevel_AWB_PERIOD ( ID_API_DEBUG_LEVEL_BASE + 3 ) // 3. 12290
+
+#define ID_API_REGISTER_API_SET_CB ( ID_API_RESERVED_BASE + 1) //1. register API_SET callback
+#define ID_API_REGISTER_API_GET_CB ( ID_API_RESERVED_BASE + 2) //2. register API_GET callback
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_TUNINGSERVER_API_ID_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_datatype.h
new file mode 100644
index 00000000..5926e888
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_datatype.h
@@ -0,0 +1,407 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp_datatype.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_DATATYPE_H_
+#define _MI_ISP_DATATYPE_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "mi_common.h"
+#include "mi_sys_datatype.h"
+#include "mi_isp_3a_datatype.h"
+#include "mi_isp_iq_datatype.h"
+
+/************************************* AF - Define the structure declaration - START *************************************/
+
+/************************************* AF - Define the structure declaration - END *************************************/
+
+/************************** Cus3A ***********************/
+
+typedef struct
+{
+ MI_U8 uAvgR;
+ MI_U8 uAvgG;
+ MI_U8 uAvgB;
+ MI_U8 uAvgY;
+} MI_ISP_AE_AVGS;
+
+typedef struct
+{
+ MI_U32 nBlkX;
+ MI_U32 nBlkY;
+ MI_ISP_AE_AVGS nAvg[128*90];
+}MI_ISP_AE_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U8 uAvgR;
+ MI_U8 uAvgG;
+ MI_U8 uAvgB;
+} MI_ISP_AWB_AVGS;
+
+typedef struct
+{
+ MI_U32 nBlkX;
+ MI_U32 nBlkY;
+ MI_ISP_AWB_AVGS nAvg[128*90];
+} MI_ISP_AWB_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U16 nHisto[128];
+} MI_ISP_HISTO_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U16 nHisto[256];
+} MI_ISP_RGBIR_HISTO_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_BOOL bAE;
+ MI_BOOL bAWB;
+ MI_BOOL bAF;
+}Cus3AEnable_t;
+
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ char sensor_id[32]; /**< sensor module id*/
+ MI_U32 shutter; /**< shutter Shutter in ns*/
+ MI_U32 shutter_step; /**< shutter Shutter step ns*/
+ MI_U32 shutter_min; /**< shutter Shutter min us*/
+ MI_U32 shutter_max; /**< shutter Shutter max us*/
+ MI_U32 sensor_gain; /**< sensor_gain Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gain_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gain_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ MI_U32 isp_gain; /**< isp_gain Isp digital gain , 1X = 1024 */
+ MI_U32 isp_gain_max; /**< isp_gain Maximum Isp digital gain , 1X = 1024 */
+ MI_U32 FNx10; /**< F number * 10*/
+ MI_U32 fps; /**< initial frame per second*/
+ MI_U32 shutterHDRShort_step; /**< shutter Shutter step ns*/
+ MI_U32 shutterHDRShort_min; /**< shutter Shutter min us*/
+ MI_U32 shutterHDRShort_max; /**< shutter Shutter max us*/
+ MI_U32 sensor_gainHDRShort_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gainHDRShort_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ /*CUS3A v1.1*/
+ MI_U32 AvgBlkX; /**< HW statistics average block number*/
+ MI_U32 AvgBlkY; /**< HW statistics average block number*/
+}CusAEInitParam_t,CusAeInitParam_t;
+
+/*! @brief ISP report to AE, hardware statistic */
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ void *hist1; /**< HW statistic histogram 1*/
+ void *hist2; /**< HW statistic histogram 2*/
+ MI_U32 AvgBlkX; /**< HW statistics average block number*/
+ MI_U32 AvgBlkY; /**< HW statistics average block number*/
+ void * avgs; /**< HW statistics average block data*/
+ MI_U32 Shutter; /**< Current shutter in ns*/
+ MI_U32 SensorGain; /**< Current Sensor gain, 1X = 1024 */
+ MI_U32 IspGain; /**< Current ISP gain, 1X = 1024*/
+ MI_U32 ShutterHDRShort; /**< Current shutter in ns*/
+ MI_U32 SensorGainHDRShort; /**< Current Sensor gain, 1X = 1024 */
+ MI_U32 IspGainHDRShort; /**< Current ISP gain, 1X = 1024*/
+ /*CUS3A V1.1*/
+ MI_U32 PreAvgY; /**< Previous frame brightness*/
+ MI_U8 HDRCtlMode; /**< 0 = HDR off; */
+ /**< 1 = Separate shutter & Separate sensor gain settings */
+ /**< 2 = Separate shutter & Share sensor gain settings */
+ /**< 3 = Share shutter & Separate sensor gain settings */
+ MI_U32 FNx10; /**< Aperture in FNx10*/
+ MI_U32 CurFPS; /**Current sensor FPS */
+ MI_U32 PreWeightY; /**< Previous frame brightness with ROI weight*/
+} __attribute__((packed, aligned(1))) CusAEInfo_t, CusAeInput_t;
+
+/*! @brief ISP ae algorithm result*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 Change; /**< if true, apply this result to hw register*/
+ MI_U32 Shutter; /**< Shutter in ns */
+ MI_U32 SensorGain; /**< Sensor gain, 1X = 1024 */
+ MI_U32 IspGain; /**< ISP gain, 1X = 1024 */
+ MI_U32 ShutterHdrShort; /**< Shutter in ns */
+ MI_U32 SensorGainHdrShort; /**< Sensor gain, 1X = 1024 */
+ MI_U32 IspGainHdrShort; /**< ISP gain, 1X = 1024 */
+ MI_U32 u4BVx16384; /**< Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ MI_U32 AvgY; /**< frame brightness */
+ MI_U32 HdrRatio; /**< hdr ratio, 1X = 1024 */
+ /*CUS3A V1.1*/
+ MI_U32 FNx10; /**< F number * 10*/
+ MI_U32 DebandFPS; /** Target fps when running auto debanding**/
+ MI_U32 WeightY; /**< frame brightness with ROI weight*/
+}__attribute__((packed, aligned(1))) CusAEResult_t, CusAeOutput_t;
+
+/*! @brief AWB HW statistics data*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 AvgBlkX;
+ MI_U32 AvgBlkY;
+ MI_U32 CurRGain;
+ MI_U32 CurGGain;
+ MI_U32 CurBGain;
+ void *avgs; //ISP_AWB_SAMPLE
+ /*CUS3A V1.1*/
+ MI_U8 HDRMode; /**< Noramal or HDR mode*/
+ void* *pAwbStatisShort; /**< Short Shutter AWB statistic data */
+ MI_U32 u4BVx16384; /**< From AE output, Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ MI_S32 WeightY; /**< frame brightness with ROI weight*/
+}__attribute__((packed, aligned(1))) CusAWBInfo_t, CusAWBInput_t;
+
+/*! @brief AWB algorithm result*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 Change; /**< if true, apply this result to hw register*/
+ MI_U32 R_gain; /**< AWB gain for R channel*/
+ MI_U32 G_gain; /**< AWB gain for G channel*/
+ MI_U32 B_gain; /**< AWB gain for B channel*/
+ MI_U32 ColorTmp; /**< Return color temperature*/
+}CusAWBResult_t, CusAwbOutput_t;;
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ SS_AE_16x24 = 0,
+ SS_AE_32x24,
+ SS_AE_64x48,
+ SS_AE_64x45,
+ SS_AE_128x80,
+ SS_AE_128x90,
+ SS_AE_32x32
+} MS_CUST_AE_WIN_BLOCK_NUM_TYPE_e;
+
+typedef struct {
+ MI_U16 u2Stawin_x_offset;
+ MI_U16 u2Stawin_x_size;
+ MI_U16 u2Stawin_y_offset;
+ MI_U16 u2Stawin_y_size;
+ MI_U16 u2WinIdx;
+} CusAEHistWin_t;
+
+typedef struct
+{
+ MI_U32 SizeX;
+ MI_U32 SizeY;
+ MI_U32 IncRatio;
+}CusAWBSample_t;
+
+typedef struct
+{
+ MI_U16 CropX; // 0~1023
+ MI_U16 CropY; // 0~1023
+ MI_U16 CropW; // 0~1023
+ MI_U16 CropH; // 0~1023
+}CusAEAWBCropSize_t;
+
+typedef struct
+{
+ MI_U8 iir_1[5*16]; //[5]: iir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 iir_2[5*16]; //[5]: iir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 luma[4*16]; //[4]: luma 32bit, use 4*u8 datatype, [16]: 16wins
+ MI_U8 fir_v[5*16]; //[5]: fir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 fir_h[5*16]; //[5]: fir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 ysat[3*16]; //[3]: ysat 22bit, use 3*u8 datatype, [16]: 16wins
+} AF_STATS_PARAM_t;
+
+typedef struct
+{
+ AF_STATS_PARAM_t stParaAPI[16];
+} CusAFStats_t;
+
+typedef struct AF_WINDOW_PARAM_s
+{
+ MI_U32 u32StartX; /*range : 0~1023*/
+ MI_U32 u32StartY; /*range : 0~1023*/
+ MI_U32 u32EndX; /*range : 0~1023*/
+ MI_U32 u32EndY; /*range : 0~1023*/
+} AF_WINDOW_PARAM_t;
+
+typedef struct
+{
+ MI_U8 u8WindowIndex;
+ AF_WINDOW_PARAM_t stParaAPI;
+} CusAFWin_t;
+
+typedef struct
+{
+ MI_U16 u16IIR1_a0;
+ MI_U16 u16IIR1_a1;
+ MI_U16 u16IIR1_a2;
+ MI_U16 u16IIR1_b1;
+ MI_U16 u16IIR1_b2;
+ MI_U16 u16IIR1_1st_low_clip;
+ MI_U16 u16IIR1_1st_high_clip;
+ MI_U16 u16IIR1_2nd_low_clip;
+ MI_U16 u16IIR1_2nd_high_clip;
+ MI_U16 u16IIR2_a0;
+ MI_U16 u16IIR2_a1;
+ MI_U16 u16IIR2_a2;
+ MI_U16 u16IIR2_b1;
+ MI_U16 u16IIR2_b2;
+ MI_U16 u16IIR2_1st_low_clip;
+ MI_U16 u16IIR2_1st_high_clip;
+ MI_U16 u16IIR2_2nd_low_clip;
+ MI_U16 u16IIR2_2nd_high_clip;
+
+ MI_U16 u16IIR1_e1_en;
+ MI_U16 u16IIR1_e1_a0;
+ MI_U16 u16IIR1_e1_a1;
+ MI_U16 u16IIR1_e1_a2;
+ MI_U16 u16IIR1_e1_b1;
+ MI_U16 u16IIR1_e1_b2;
+ MI_U16 u16IIR1_e2_en;
+ MI_U16 u16IIR1_e2_a0;
+ MI_U16 u16IIR1_e2_a1;
+ MI_U16 u16IIR1_e2_a2;
+ MI_U16 u16IIR1_e2_b1;
+ MI_U16 u16IIR1_e2_b2;
+
+ MI_U16 u16IIR2_e1_en;
+ MI_U16 u16IIR2_e1_a0;
+ MI_U16 u16IIR2_e1_a1;
+ MI_U16 u16IIR2_e1_a2;
+ MI_U16 u16IIR2_e1_b1;
+ MI_U16 u16IIR2_e1_b2;
+ MI_U16 u16IIR2_e2_en;
+ MI_U16 u16IIR2_e2_a0;
+ MI_U16 u16IIR2_e2_a1;
+ MI_U16 u16IIR2_e2_a2;
+ MI_U16 u16IIR2_e2_b1;
+ MI_U16 u16IIR2_e2_b2;
+} CusAFFilter_t;
+
+typedef struct
+{
+ MI_BOOL bSobelYSatEn;
+ MI_U16 u16SobelYThd;
+
+ MI_BOOL bIIRSquareAccEn;
+ MI_BOOL bSobelSquareAccEn;
+
+ MI_U16 u16IIR1Thd;
+ MI_U16 u16IIR2Thd;
+ MI_U16 u16SobelHThd;
+ MI_U16 u16SobelVThd;
+ MI_U8 u8AFTblX[12];
+ MI_U16 u16AFTblY[13];
+} CusAFFilterSq_t;
+
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ AF_ROI_MODE_NORMAL,
+ AF_ROI_MODE_MATRIX
+} ISP_AF_ROI_MODE_e;
+
+typedef struct
+{
+ ISP_AF_ROI_MODE_e mode;
+ MI_U32 u32_vertical_block_number;
+} CusAFRoiMode_t;
+
+/* Raw store control */
+typedef enum
+{
+ eRawStoreNode_P0HEAD = 0, /* Control by VIF, Do not use */
+ eRawStoreNode_P1HEAD = 1, /* Control by VIF, Do not use */
+ eRawStoreNode_P0TAIL = 2,
+ eRawStoreNode_P1TAIL = 3,
+ eRawStoreNode_ISPOUT = 4,
+ eRawStoreNode_VDOS = 5,
+ eRawStoreNode_ISPOUT_BEFORE_YEE = 6,
+ eRawStoreNode_RGBIR_IR_ONLY = 7
+}CameraRawStoreNode_e;
+
+typedef struct
+{
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32Node;
+ MI_U32 u32PixelDepth;
+} CusImageResolution_t;
+
+typedef struct
+{
+ MI_U32 u32enable;
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32physical_address;
+ MI_U32 u32Node;
+} CusISPOutImage_t;
+
+typedef struct
+{
+ MI_U32 u32enable;
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32physical_address;
+ MI_U32 u32Node;
+ MI_U32 u32PixelDepth;
+} CusHdrRawImage_t;
+
+typedef struct
+{
+ MI_U64 u64Pts; /** frame PTS */
+ MI_U32 u32Shutter; /**< Shutter in us */
+ MI_U32 u32SensorGain; /**< Sensor gain, 1X = 1024 */
+ MI_U32 u32ColorTmp; /**< Return color temperature*/
+} IspFrameMetaInfo_t;
+
+typedef struct
+{
+ MI_U32 u32SlaveAddr; //sensor slave address
+ MI_U32 u32RegLen; //sensor register length , 1 or 2 bytes
+ MI_U32 u32DataLen; //sensor register data length, 1 or 2 bytes
+ MI_U32 u32I2cSpeed; //i2c speed , 100/200/300/400 KHz
+ MI_U32 u32Reg; //sensor register address
+ MI_U32 u32Data; //sensor register data
+}CusSensorI2cParam_t;
+
+/***************************** end of Cus3A ****************************/
+
+// COMMON API
+typedef struct MI_ISP_API_CHANNEL_ID_TYPE_s
+{
+ MI_U32 u32ChannelID;
+} MI_ISP_API_CHANNEL_ID_TYPE_t;
+
+typedef struct MI_ISP_API_USERSPACE3A_ATTR_s
+{
+ MI_SYS_PixelFormat_e ePixelFmt;
+ MI_U32 eSensorBindId;
+} MI_ISP_API_USERSPACE3A_ATTR_t;
+
+typedef struct
+{
+ MI_S8 strIspRoot[64];
+} MI_ISP_ROOT_PATH_T;
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_general.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_general.h
new file mode 100644
index 00000000..abf87248
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_general.h
@@ -0,0 +1,187 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_GENERAL_H_
+#define _MI_ISP_GENERAL_H_
+
+#include "mi_syscall.h"
+#include "mi_vpe_datatype.h"
+#include "mi_common.h"
+#include "mi_isp.h"
+#include "mi_isp_datatype.h"
+
+#ifdef CAM_OS_LINUX_USER
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#ifdef LINUX_FLOW_ON_DUAL_OS
+#define DUAL_OS_RUN_ON_LINUX 1
+#define DUAL_OS_RUN_ON_RTOS 0
+#else
+#ifdef __RTOS__
+#define DUAL_OS_RUN_ON_LINUX 0
+#define DUAL_OS_RUN_ON_RTOS 1
+#else
+#define DUAL_OS_RUN_ON_LINUX 0
+#define DUAL_OS_RUN_ON_RTOS 0
+#endif
+#endif
+
+#define MI_ISP_MSG(args...) printf(args)
+#define MI_ISP_DMSG(args...) do{}while(0)
+#define MI_ISP_EMSG(args...) printf(args)
+#define MI_ISP_VMSG(args...) do{}while(0)
+
+#define MI_ISP_CALLOC calloc
+#define MI_ISP_FREE free
+
+extern MI_S32 MI_VPE_GetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+extern MI_S32 MI_VPE_SetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+
+MI_S32 _MI_ISP_SetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+MI_S32 _MI_ISP_GetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+
+#if (DUAL_OS_RUN_ON_LINUX)
+#define MI_GETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ PARAM_t *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(sizeof(PARAM_t), &pIspBuffer);\
+ memcpy(pIspBuffer, PtrData, sizeof(PARAM_t));\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, sizeof(PARAM_t));\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_GetIspApiData(&stIspApiHeader, pIspBuffer);\
+ memcpy(PtrData, pIspBuffer, sizeof(PARAM_t));\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+ return s32Ret;\
+
+#define MI_SETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ PARAM_t *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(sizeof(PARAM_t), &pIspBuffer);\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ memcpy(pIspBuffer, PtrData, sizeof(PARAM_t));\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, sizeof(PARAM_t));\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, pIspBuffer);\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+ return s32Ret;\
+
+#define MI_CALI_SETAPI(Channel, APIFuncID, PARAM_t, DataSize, PtrData)\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ char *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(DataSize, &pIspBuffer);\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = DataSize;\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ memcpy(pIspBuffer, PtrData, DataSize);\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, DataSize);\
+ stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, pIspBuffer);\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+
+#else
+#define MI_GETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ /*s32Ret = stIspApiHeader.s32Ret = MI_VPE_GetIspApiData(&stIspApiHeader, PtrData);*/\
+ s32Ret = stIspApiHeader.s32Ret = _MI_ISP_GetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader.u32Channel, stIspApiHeader.u32CtrlID, stIspApiHeader.u32DataLen, stIspApiHeader.u32HeadSize);\
+ return s32Ret;\
+
+#define MI_SETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ /*s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, PtrData);*/\
+ s32Ret = stIspApiHeader.s32Ret = _MI_ISP_SetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader.u32Channel, stIspApiHeader.u32CtrlID, stIspApiHeader.u32DataLen, stIspApiHeader.u32HeadSize);\
+ return s32Ret;\
+
+#define MI_CALI_SETAPI(Channel, APIFuncID, PARAM_t, DataSize, PtrData)\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = DataSize;\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader->u32Channel, stIspApiHeader->u32CtrlID, stIspApiHeader->u32DataLen, stIspApiHeader->u32HeadSize);\
+
+#endif
+
+#define MI_ISP_SET(APIFunc, PARAM_t) \
+ if(ApiLen != sizeof(PARAM_t)) \
+ { \
+ MI_ISP_MSG("[%s][%s] APIID:%d error param \n", __FILE__, __func__, ApiId); \
+ break; \
+ } \
+ ret = APIFunc(Channel, (PARAM_t*)pApiBuf); \
+
+#define MI_ISP_GET(APIFunc, PARAM_t) \
+ *ApiLen = sizeof(PARAM_t); \
+ ret = APIFunc(Channel, (PARAM_t*)pApiBuf); \
+
+#define MI_CALL_SETAPI(Channel, APIFunc, PARAM_t)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ PARAM_t *stParam = MI_ISP_CALLOC(1, sizeof(PARAM_t));\
+ memcpy(stParam, param_ary[0], sizeof(PARAM_t));\
+ s32Ret = APIFunc(Channel, stParam);\
+ MI_ISP_DMSG("[%s][%s] param_num = %d\n", __FILE__, __FUNCTION__, param_num);\
+ MI_ISP_FREE(stParam);\
+ return s32Ret;\
+
+#define MI_RESET_API(Channel, APIFunc, PARAM_t)\
+ PARAM_t *stParam = MI_ISP_CALLOC(1, sizeof(PARAM_t));\
+ memset(stParam, 0x00, sizeof(PARAM_t));\
+ s32Ret = APIFunc(Channel, stParam);\
+ MI_ISP_DMSG("[%s][%s] param_num = %d\n", __FILE__, __FUNCTION__, param_num);\
+ MI_ISP_FREE(stParam);\
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_GENERAL_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_iq.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_iq.h
new file mode 100644
index 00000000..ff097c7f
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_iq.h
@@ -0,0 +1,278 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_IQ_H_
+#define _MI_ISP_IQ_H_
+
+#include "mi_isp_3a_datatype.h"
+#include "mi_isp_iq_datatype.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if 1
+ /************************************* IQ API START *************************************/
+ MI_S32 MI_ISP_IQ_GetVersionInfo(MI_U32 Channel, MI_ISP_IQ_VERSION_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetVersionInfo(MI_U32 Channel, MI_ISP_IQ_VERSION_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetParaInitStatus(MI_U32 Channel, MI_ISP_IQ_PARAM_INIT_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetColorToGray(MI_U32 Channel, MI_ISP_IQ_COLORTOGRAY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetColorToGray(MI_U32 Channel, MI_ISP_IQ_COLORTOGRAY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetContrast(MI_U32 Channel, MI_ISP_IQ_CONTRAST_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetContrast(MI_U32 Channel, MI_ISP_IQ_CONTRAST_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetBrightness(MI_U32 Channel, MI_ISP_IQ_BRIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetBrightness(MI_U32 Channel, MI_ISP_IQ_BRIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLightness(MI_U32 Channel, MI_ISP_IQ_LIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLightness(MI_U32 Channel, MI_ISP_IQ_LIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBGamma(MI_U32 Channel, MI_ISP_IQ_RGBGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBGamma(MI_U32 Channel, MI_ISP_IQ_RGBGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetYUVGamma(MI_U32 Channel, MI_ISP_IQ_YUVGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetYUVGamma(MI_U32 Channel, MI_ISP_IQ_YUVGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetSaturation(MI_U32 Channel, MI_ISP_IQ_SATURATION_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetSaturation(MI_U32 Channel, MI_ISP_IQ_SATURATION_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDefog(MI_U32 Channel, MI_ISP_IQ_DEFOG_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDefog(MI_U32 Channel, MI_ISP_IQ_DEFOG_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBMatrix(MI_U32 Channel, MI_ISP_IQ_RGBMATRIX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBMatrix(MI_U32 Channel, MI_ISP_IQ_RGBMATRIX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetFalseColor(MI_U32 Channel, MI_ISP_IQ_FALSECOLOR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetFalseColor(MI_U32 Channel, MI_ISP_IQ_FALSECOLOR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNR3D(MI_U32 Channel, MI_ISP_IQ_NR3D_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNR3D(MI_U32 Channel, MI_ISP_IQ_NR3D_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNR3D_P1(MI_U32 Channel, MI_ISP_IQ_NR3D_P1_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_GetNR3D_P1(MI_U32 Channel, MI_ISP_IQ_NR3D_P1_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_SetNRDeSpike(MI_U32 Channel, MI_ISP_IQ_NRDESPIKE_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRDeSpike(MI_U32 Channel, MI_ISP_IQ_NRDESPIKE_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRLuma(MI_U32 Channel, MI_ISP_IQ_NRLUMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRLuma(MI_U32 Channel, MI_ISP_IQ_NRLUMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRChroma(MI_U32 Channel, MI_ISP_IQ_NRChroma_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRChroma(MI_U32 Channel, MI_ISP_IQ_NRChroma_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetSharpness(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetSharpness(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetCrossTalk(MI_U32 Channel, MI_ISP_IQ_CROSSTALK_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetCrossTalk(MI_U32 Channel, MI_ISP_IQ_CROSSTALK_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetOBC(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetOBC(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetOBC_P1(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetOBC_P1(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDR(MI_U32 Channel, MI_ISP_IQ_WDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDR(MI_U32 Channel, MI_ISP_IQ_WDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDRCurveAdv(MI_U32 Channel, MI_ISP_IQ_WDRCurveAdv_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDRCurveAdv(MI_U32 Channel, MI_ISP_IQ_WDRCurveAdv_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDRCurveFull(MI_U32 Channel, MI_ISP_IQ_WDRCurveFull_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDRCurveFull(MI_U32 Channel, MI_ISP_IQ_WDRCurveFull_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDynamicDP(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDynamicDP(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDynamicDP_CLUSTER(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDynamicDP_CLUSTER(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetHSV(MI_U32 Channel, MI_ISP_IQ_HSV_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetHSV(MI_U32 Channel, MI_ISP_IQ_HSV_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBIR(MI_U32 Channel, MI_ISP_IQ_RGBIR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBIR(MI_U32 Channel, MI_ISP_IQ_RGBIR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetFPN(MI_U32 Channel, MI_ISP_IQ_FPN_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_GetFPN(MI_U32 Channel, MI_ISP_IQ_FPN_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_SetPFC(MI_U32 Channel, MI_ISP_IQ_PFC_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetPFC(MI_U32 Channel, MI_ISP_IQ_PFC_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetDEMOSAIC(MI_U32 Channel, MI_ISP_IQ_DEMOSAIC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDEMOSAIC(MI_U32 Channel, MI_ISP_IQ_DEMOSAIC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetR2Y(MI_U32 Channel, MI_ISP_IQ_R2Y_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetR2Y(MI_U32 Channel, MI_ISP_IQ_R2Y_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetCOLORTRANS(MI_U32 Channel, MI_ISP_IQ_COLORTRANS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetCOLORTRANS(MI_U32 Channel, MI_ISP_IQ_COLORTRANS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetHDR(MI_U32 Channel, MI_ISP_IQ_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetHDR(MI_U32 Channel, MI_ISP_IQ_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLSC(MI_U32 Channel, MI_ISP_IQ_LSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLSC(MI_U32 Channel, MI_ISP_IQ_LSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLSC_CTRL(MI_U32 Channel, MI_ISP_IQ_LSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLSC_CTRL(MI_U32 Channel, MI_ISP_IQ_LSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetALSC(MI_U32 Channel, MI_ISP_IQ_ALSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetALSC(MI_U32 Channel, MI_ISP_IQ_ALSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetALSC_CTRL(MI_U32 Channel, MI_ISP_IQ_ALSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetALSC_CTRL(MI_U32 Channel, MI_ISP_IQ_ALSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRLuma_Adv(MI_U32 Channel, MI_ISP_IQ_NRLuma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNRLuma_Adv(MI_U32 Channel, MI_ISP_IQ_NRLuma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNRChroma_Adv(MI_U32 Channel, MI_ISP_IQ_NRChroma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNRChroma_Adv(MI_U32 Channel, MI_ISP_IQ_NRChroma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNRChroma_Pre(MI_U32 Channel, MI_ISP_IQ_NRChroma_Pre_TYPE_t *data); //[not support chip] macaron, pudding, ispahan
+ MI_S32 MI_ISP_IQ_GetNRChroma_Pre(MI_U32 Channel, MI_ISP_IQ_NRChroma_Pre_TYPE_t *data); //[not support chip] macaron, pudding, ispahan
+ MI_S32 MI_ISP_IQ_SetPFC_EX(MI_U32 Channel, MI_ISP_IQ_PFC_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetPFC_EX(MI_U32 Channel, MI_ISP_IQ_PFC_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetHDR_EX(MI_U32 Channel, MI_ISP_IQ_HDR_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetHDR_EX(MI_U32 Channel, MI_ISP_IQ_HDR_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetSHP_EX(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetSHP_EX(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNR3D_EX(MI_U32 Channel, MI_ISP_IQ_NR3D_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNR3D_EX(MI_U32 Channel, MI_ISP_IQ_NR3D_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetDUMMY(MI_U32 Channel, MI_ISP_IQ_DUMMY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDUMMY(MI_U32 Channel, MI_ISP_IQ_DUMMY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDUMMY_EX(MI_U32 Channel, MI_ISP_IQ_DUMMY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDUMMY_EX(MI_U32 Channel, MI_ISP_IQ_DUMMY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetIQMode(MI_U32 Channel, MI_ISP_IQ_PARAM_MODE_e *data);
+ MI_S32 MI_ISP_IQ_GetIQMode(MI_U32 Channel, MI_ISP_IQ_PARAM_MODE_e *data);
+ MI_S32 MI_ISP_IQ_GetIQind(MI_U32 Channel, MI_ISP_IQ_INDEX_e *data);
+ MI_S32 MI_ISP_IQ_SetAPIBypassMode(MI_U32 Channel, MI_ISP_API_BYPASS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetAPIBypassMode(MI_U32 Channel, MI_ISP_API_BYPASS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_QueryCCMInfo(MI_U32 Channel, MI_ISP_IQ_CCM_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetAdaptiveGamma(MI_U32 Channel, MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetAdaptiveGamma(MI_U32 Channel, MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetTEMP(MI_U32 Channel, MI_ISP_IQ_TEMP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetTEMP(MI_U32 Channel, MI_ISP_IQ_TEMP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetTEMP_INFO(MI_U32 Channel, MI_ISP_IQ_TEMP_INFO_TYPE_t *data);
+ /************************************* IQ API END *************************************/
+
+ /************************************* AE API START *************************************/
+ MI_S32 MI_ISP_AE_GetHistoWghtY(MI_U32 Channel, MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t *data);
+ MI_S32 MI_ISP_AE_QueryExposureInfo(MI_U32 Channel, MI_ISP_AE_EXPO_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetEVComp(MI_U32 Channel, MI_ISP_AE_EV_COMP_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetEVComp(MI_U32 Channel, MI_ISP_AE_EV_COMP_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetExpoMode(MI_U32 Channel, MI_ISP_AE_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetExpoMode(MI_U32 Channel, MI_ISP_AE_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetManualExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetManualExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetManualShortExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetManualShortExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetState(MI_U32 Channel, MI_ISP_SM_STATE_TYPE_e *data); // Pause, Resume
+ MI_S32 MI_ISP_AE_GetState(MI_U32 Channel, MI_ISP_SM_STATE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetTarget(MI_U32 Channel, MI_ISP_AE_INTP_LUT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetTarget(MI_U32 Channel, MI_ISP_AE_INTP_LUT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetConverge(MI_U32 Channel, MI_ISP_AE_CONV_CONDITON_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetConverge(MI_U32 Channel, MI_ISP_AE_CONV_CONDITON_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetExposureLimit(MI_U32 Channel, MI_ISP_AE_EXPO_LIMIT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetExposureLimit(MI_U32 Channel, MI_ISP_AE_EXPO_LIMIT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetPlainLongExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetPlainLongExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetPlainShortExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetPlainShortExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetWinWgtType(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetWinWgtType(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetWinWgt(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetWinWgt(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetFlicker(MI_U32 Channel, MI_ISP_AE_FLICKER_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetFlicker(MI_U32 Channel, MI_ISP_AE_FLICKER_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetFlickerEX(MI_U32 Channel, MI_ISP_AE_FLICKER_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetFlickerEX(MI_U32 Channel, MI_ISP_AE_FLICKER_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStrategy(MI_U32 Channel, MI_ISP_AE_STRATEGY_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStrategy(MI_U32 Channel, MI_ISP_AE_STRATEGY_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStrategyEX(MI_U32 Channel, MI_ISP_AE_STRATEGY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStrategyEX(MI_U32 Channel, MI_ISP_AE_STRATEGY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetRGBIRAE(MI_U32 Channel, MI_ISP_AE_RGBIR_AE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetRGBIRAE(MI_U32 Channel, MI_ISP_AE_RGBIR_AE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetHDR(MI_U32 Channel, MI_ISP_AE_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetHDR(MI_U32 Channel, MI_ISP_AE_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStabilizer(MI_U32 Channel, MI_ISP_AE_STABILIZER_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStabilizer(MI_U32 Channel, MI_ISP_AE_STABILIZER_TYPE_t *data);
+ /************************************* AE API END *************************************/
+
+ /************************************* AWB API START *************************************/
+ MI_S32 MI_ISP_AWB_QueryInfo(MI_U32 Channel, MI_ISP_AWB_QUERY_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetAttr(MI_U32 Channel, MI_ISP_AWB_ATTR_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetAttr(MI_U32 Channel, MI_ISP_AWB_ATTR_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetAttrEx(MI_U32 Channel, MI_ISP_AWB_ATTR_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetAttrEx(MI_U32 Channel, MI_ISP_AWB_ATTR_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetMultiLSAttr(MI_U32 Channel, MI_ISP_AWB_MULTILS_LS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetMultiLSAttr(MI_U32 Channel, MI_ISP_AWB_MULTILS_LS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetCTWeight(MI_U32 Channel, MI_ISP_AWB_CT_WEIGHT_TYPE_t *data); //Not works now, please use MI_ISP_AWB_SetAttr to set LvWeight indstead.
+ MI_S32 MI_ISP_AWB_GetCTWeight(MI_U32 Channel, MI_ISP_AWB_CT_WEIGHT_TYPE_t *data); //Not works now, please use MI_ISP_AWB_GetAttr to set LvWeight indstead.
+
+ MI_S32 MI_ISP_AWB_SetCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCurCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CUR_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCTStats(MI_U32 Channel, MI_ISP_AWB_CT_STATISTICS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetHWStats(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetCTMwbAttr(MI_U32 Channel, MI_ISP_AWB_CTMWB_PARAM_t *data);
+ MI_S32 MI_ISP_AWB_GetCTMwbAttr(MI_U32 Channel, MI_ISP_AWB_CTMWB_PARAM_t *data);
+
+ /************************************* AWB API END *************************************/
+
+ /************************************* AF API START *************************************/
+ /************************************* AF API END *************************************/
+
+ MI_S32 MI_ISP_ALGO_SET_ALL(int Channel, MI_U16 ApiId, MI_U32 ApiLen, MI_U8* pApiBuf);
+ MI_S32 MI_ISP_ALGO_GET_ALL(int Channel, MI_U16 ApiId, MI_U32* ApiLen, MI_U8* pApiBuf);
+
+#endif
+
+#if 1
+
+typedef struct MI_ISP_EXCUTE_CMD_ARRAY_s
+{
+ MI_U32 u32CmdType;
+ MI_U16 u16APIID;
+ MI_S32 (*callback)(MI_U32 Channel, MI_U8 *param_ary[], MI_U8 param_num);
+} MI_ISP_EXCUTE_CMD_ARRAY_t;
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ MI_ISP_CAMERA_CMD_SET = 0,
+ MI_ISP_CAMERA_CMD_GET,
+ MI_ISP_CAMERA_CMD_SET_MODE ,
+ MI_ISP_CAMERA_CMD_GET_MODE,
+ MI_ISP_CAMERA_CMD_GET_PIC,
+ MI_ISP_CAMERA_CMD_SET_API,
+ MI_ISP_CAMERA_CMD_GET_API,
+ MI_ISP_CAMERA_CMD_UPLOAD_FILE, /* client upload file to server */
+ MI_ISP_CAMERA_CMD_DOWNLOAD_FILE, /* client download file from server*/
+} MI_ISP_CAMERA_EXT_CMD_TYPE_e;
+
+typedef struct MI_ISP_CMD_HEADER_s
+{
+ MI_ISP_CAMERA_EXT_CMD_TYPE_e CmdType;
+ MI_S32 CmdLen;
+} MI_ISP_CMD_HEADER_t;
+
+typedef struct MI_ISP_API_PARAM_s
+{
+ MI_U32 u32MagicKey;
+ MI_ISP_CMD_HEADER_t sCmdheader;
+ MI_U16 u16APIID;
+ MI_U16 u16ParamNum;
+} MI_ISP_API_PARAM_t;
+
+typedef struct MI_ISP_API_BIN_FILE_s
+{
+ MI_U32 u32FileID;
+ MI_U32 u32ISPVer;
+ MI_U32 u32DataLen;
+ MI_U32 u32Checksum;
+ MI_U32 u32MagicKey;
+ MI_U32 u32Reserved[3];
+} MI_ISP_API_BIN_FILE_t;
+
+typedef struct MI_ISP_API_CALI_FILE_s
+{
+ MI_U32 u32CaliVer;
+ MI_U32 u32DataSize;
+ MI_U32 u32Checksum;
+ MI_U32 u32Reserved[2];
+} MI_ISP_API_CALI_FILE_t;
+
+ MI_S32 MI_ISP_ALGO_API_DisableAllApi(MI_U32 Channel);
+ MI_S32 MI_ISP_ALGO_API_CmdLoadBinFile(MI_U32 Channel, MI_U8 *bindata_buf, MI_U32 user_key);
+ MI_S32 MI_ISP_ALGO_API_CmdLoadCaliData(MI_U32 Channel, MI_U8 *bindata_buf, MI_U32 BIN_BUF_MAX_LEN, MI_ISP_CALI_ITEM_e eCaliItem);
+
+#endif
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_IQ_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_iq_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_iq_datatype.h
new file mode 100644
index 00000000..4d51ae64
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/mi_isp_iq_datatype.h
@@ -0,0 +1,1269 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+ * iq_apiset.h
+ *
+ * Created on: 2016/8/16
+ * Author: Elsa-cf.Lin
+ */
+
+#ifndef _MI_ISP_IQ_DATATYPE_H_
+#define _MI_ISP_IQ_DATATYPE_H_
+
+#include "mi_isp_3a_datatype.h"
+
+//put here temporarily, should add mi_isp_cali_datatype.h?
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ SS_CALI_ITEM_AWB = 0,
+ SS_CALI_ITEM_OBC = 1,
+ SS_CALI_ITEM_SDC = 2,
+ SS_CALI_ITEM_ALSC = 3,
+ SS_CALI_ITEM_LSC = 4,
+ SS_CALI_ITEM_MAX,
+} MI_ISP_CALI_ITEM_e;
+
+/************************************* IQ - Define the structure declaration - START *************************************/
+
+typedef struct
+{
+ MI_U16 u16NumOfPoints;
+ MI_S32 s32Y[16];
+ MI_S32 s32X[16];
+} MI_INTP_LUT_IQ;
+
+#if 1 //API20 struct
+
+#define MI_ISP_AUTO_NUM (16)
+#define ALSC_TBL_MAX 459
+#define ENABLE_CCM_COEFF_SUM_INFO 1
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ API20_AUTO = 0, //[00]
+ //API2.0
+ API20_FPN, //[01]
+ API20_CCM, //[02]
+ API20_SAT, //[03]
+ API20_OBC, //[04]
+ API20_OBC_P1, //[05]
+ API20_FCOLOR, //[06]
+ API20_CR, //[07]
+ API20_NR_DeSpike, //[08]
+ API20_SHP, //[09]
+ API20_NR_3D, //[10]
+ API20_BRI, //[11]
+ API20_LIG, //[12]
+ API20_CST, //[13]
+ API20_GMA, //[14]
+ API20_CTG, //[15]
+ API20_NR_NLM, //[16]
+ API20_DEFOG, //[17]
+ API20_DRC, //[18]
+ API20_DPC, //[19]
+ API20_HSV, //[20]
+ API20_WDR_LOC, //[21]
+ API20_RGBIR, //[22]
+ API20_YUVGMA, //[23]
+ API20_HDR16to12, //[24]
+ API20_COLORTRANS, //[25]
+ API20_HDR, //[26]
+ API20_EFFECT, //[27]
+ API20_PFC, //[28]
+ API20_SIIR, //[29]
+ API20_DM, //[30]
+ API20_NR_3D_P1, //[31]
+ API20_WDRCurveAdv, //[32]
+ API20_MXNR, //[33]
+ API20_R2Y, //[34]
+ API20_LSC, //[35]
+ API20_LSC_CTRL, //[36]
+ API20_ALSC, //[37]
+ API20_ALSC_CTRL, //[38]
+ API20_DPC_CLUSTER, //[39]
+ API20_PFC_EX, //[40]
+ API20_HDR_EX, //[41]
+ API20_SHP_EX, //[42]
+ API20_NR_3D_EX, //[43]
+ API20_GNR, //[44]
+ API20_DUMMY, //[45]
+ API20_DUMMY_EX, //[46]
+ API20_WDRCurveFull, //[47]
+ API20_ADAPTIVE_GMA, //[48]
+ API20_XNR, //[49]
+ API20_TEMP, //[50]
+ API20_TEMP_INFO, //[51]
+ API20_MAX, //for para reset
+} MI_ISP_API_ID_e;
+
+typedef struct MI_ISP_IQ_COLORTOGRAY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+} MI_ISP_IQ_COLORTOGRAY_TYPE_t;
+
+typedef struct LEVEL_BASE_PARAM_s
+{
+ MI_U32 u32Lev; //0 ~ 100
+} LEVEL_BASE_PARAM_t;
+
+typedef struct LIGHTNESS_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} LIGHTNESS_MANUAL_ATTR_t;
+
+typedef struct LIGHTNESS_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} LIGHTNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_LIGHTNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ LIGHTNESS_AUTO_ATTR_t stAuto;
+ LIGHTNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_LIGHTNESS_TYPE_t;
+
+typedef struct CONTRAST_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} CONTRAST_MANUAL_ATTR_t;
+
+typedef struct CONTRAST_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} CONTRAST_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_CONTRAST_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ CONTRAST_AUTO_ATTR_t stAuto;
+ CONTRAST_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_CONTRAST_TYPE_t;
+
+typedef struct BRIGHTNESS_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} BRIGHTNESS_MANUAL_ATTR_t;
+
+typedef struct BRIGHTNESS_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} BRIGHTNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_BRIGHTNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ BRIGHTNESS_AUTO_ATTR_t stAuto;
+ BRIGHTNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_BRIGHTNESS_TYPE_t;
+
+
+typedef struct RGBGAMMA_PARAM_s
+{
+ MI_U16 u16LutR[256]; //0 ~ 4095
+ MI_U16 u16LutG[256]; //0 ~ 4095
+ MI_U16 u16LutB[256]; //0 ~ 4095
+} RGBGAMMA_PARAM_t;
+
+typedef struct RGBGAMMA_MANUAL_ATTR_s
+{
+ RGBGAMMA_PARAM_t stParaAPI;
+} RGBGAMMA_MANUAL_ATTR_t;
+
+typedef struct RGBGAMMA_AUTO_ATTR_s
+{
+ RGBGAMMA_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBGAMMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBGAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBGAMMA_AUTO_ATTR_t stAuto;
+ RGBGAMMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBGAMMA_TYPE_t;
+
+typedef struct YUVGAMMA_PAMAR_s
+{
+ MI_U16 u16LutY[256]; //0 ~ 1023
+ MI_U16 u16LutU[128]; //0 ~ 511
+ MI_U16 u16LutV[128]; //0 ~ 511
+} YUVGAMMA_PAMAR_t;
+
+typedef struct YUVGAMMA_MANUAL_ATTR_s
+{
+ YUVGAMMA_PAMAR_t stParaAPI;
+} YUVGAMMA_MANUAL_ATTR_t;
+
+typedef struct YUVGAMMA_AUTO_ATTR_s
+{
+ YUVGAMMA_PAMAR_t stParaAPI[MI_ISP_AUTO_NUM];
+} YUVGAMMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_YUVGAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ YUVGAMMA_AUTO_ATTR_t stAuto;
+ YUVGAMMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_YUVGAMMA_TYPE_t;
+
+typedef struct SATURATION_PARAM_s
+{
+ MI_U8 u8SatAllStr; //0 ~ 127 (32 = 1X)
+ MI_U8 u8SatByYSFTAdv[5]; //0 ~ 8
+ MI_U8 u8SatByYLUTAdv[6]; //0 ~ 128
+ MI_U8 u8SatBySSFTAdv[5]; //0 ~ 8
+ MI_U8 u8SatBySLUTAdv[6]; //0 ~ 128
+ MI_U8 u8SatCoring;
+} SATURATION_PARAM_t;
+
+typedef struct SATURATION_MANUAL_ATTR_s
+{
+ SATURATION_PARAM_t stParaAPI;
+} SATURATION_MANUAL_ATTR_t;
+
+typedef struct SATURATION_AUTO_ATTR_s
+{
+ SATURATION_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} SATURATION_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_SATURATION_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ SATURATION_AUTO_ATTR_t stAuto;
+ SATURATION_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SATURATION_TYPE_t;
+
+typedef struct DEFOG_PARAM_s
+{
+ MI_U8 u8Strength;
+} DEFOG_PARAM_t;
+
+typedef struct DEFOG_MANUAL_ATTR_s
+{
+ DEFOG_PARAM_t stParaAPI;
+} DEFOG_MANUAL_ATTR_t;
+
+typedef struct DEFOG_AUTO_ATTR_s
+{
+ DEFOG_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} DEFOG_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DEFOG_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DEFOG_AUTO_ATTR_t stAuto;
+ DEFOG_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DEFOG_TYPE_t;
+
+typedef struct RGBMATRIX_PARAM_s
+{
+ MI_U16 u16CCTthr;
+#if ENABLE_CCM_COEFF_SUM_INFO
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+#else
+ MI_U16 u16CCM[9]; //0 ~ 8191(1024 = 1X)
+#endif
+ MI_U8 u8CCMSat; //0 ~ 100 0:Unit matrix, 100:User matrix
+} RGBMATRIX_PARAM_t;
+
+typedef struct RGBMATRIX_MANUAL_ATTR_s
+{
+#if ENABLE_CCM_COEFF_SUM_INFO
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+#else
+ MI_U16 u16CCM[9]; //0 ~ 8191(1024 = 1X)
+#endif
+ MI_U8 u8CCMSat; //0 ~ 100 0:Unit matrix, 100:User matrix
+} RGBMATRIX_MANUAL_ATTR_t;
+
+typedef struct RGBMATRIX_AUTO_ATTR_s
+{
+ MI_ISP_BOOL_e bISOActEn; //0 ~ 1
+ RGBMATRIX_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBMATRIX_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBMATRIX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBMATRIX_AUTO_ATTR_t stAuto;
+ RGBMATRIX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBMATRIX_TYPE_t;
+
+typedef struct MI_ISP_IQ_CCM_INFO_TYPE_s
+{
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+ MI_U16 u16CCT;
+} MI_ISP_IQ_CCM_INFO_TYPE_t;
+
+typedef struct FALSECOLOR_PARAM_s
+{
+ MI_U8 u8FreqThrd; //0~255 default:140
+ MI_U8 u8EdgeScoreThrd; //0~255 default:31
+ MI_U8 u8ChromaThrdOfStrengthMax; //0~127 default:10
+ MI_U8 u8ChromaThrdOfStrengthMid; //0~127 default:40
+ MI_U8 u8ChromaThrdOfStrengthMin; //0~127 default:80
+ MI_U8 u8StrengthMid; //0~7 default:7
+ MI_U8 u8StrengthMin; //0~7 default:7
+} FALSECOLOR_PARAM_t;
+
+typedef struct FALSECOLOR_MANUAL_ATTR_s
+{
+ FALSECOLOR_PARAM_t stParaAPI;
+} FALSECOLOR_MANUAL_ATTR_t;
+
+typedef struct FALSECOLOR_AUTO_ATTR_s
+{
+ FALSECOLOR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} FALSECOLOR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_FALSECOLOR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ FALSECOLOR_AUTO_ATTR_t stAuto;
+ FALSECOLOR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_FALSECOLOR_TYPE_t;
+
+typedef struct NR3D_PARAM_s
+{
+ MI_U8 u8MdThd; //0~255
+ MI_U16 u16MdGain; //0~1023
+ MI_U8 u8TfStr; //0~64
+ MI_U8 u8TfStrEx; //0~64
+ MI_U8 u8MdThdByY[16]; //0~255
+ MI_U8 u8MdGainByY[16]; //0~255
+ MI_U8 u8M2SLut[16]; //0~31
+ MI_U16 u16TfLut[16]; //0~4095
+ MI_U8 u8YSfBlendLut[16]; //0~16
+ MI_U8 u8YSfBlendOffset; //0~16
+} NR3D_PARAM_t;
+
+typedef struct NR3D_MANUAL_ATTR_s
+{
+ NR3D_PARAM_t stParaAPI;
+} NR3D_MANUAL_ATTR_t;
+
+typedef struct NR3D_AUTO_ATTR_s
+{
+ NR3D_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NR3D_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NR3D_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NR3D_AUTO_ATTR_t stAuto;
+ NR3D_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NR3D_TYPE_t;
+
+typedef struct NR3D_EX_PARAM_s
+{
+ MI_ISP_BOOL_e bAREn; //0~1
+ MI_U8 u8ARLumaTh[2]; //0~255
+ MI_U8 u8ARMotTh[2]; //0~255
+ MI_ISP_BOOL_e bPREn; //0~1
+ MI_U16 u16PRDiffTh; //0~4095
+ MI_U8 u8PRRatioConf[4]; //0~16
+ MI_U8 u8PRContrastTh[2]; //0~15
+ MI_U8 u8PRMotTh[2]; //0~255
+} NR3D_EX_PARAM_t;
+
+typedef struct NR3D_EX_MANUAL_ATTR_s
+{
+ NR3D_EX_PARAM_t stParaAPI;
+} NR3D_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_NR3D_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ NR3D_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NR3D_EX_TYPE_t;
+
+typedef struct MI_ISP_IQ_NR3D_P1_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NR3D_P1_TYPE_t;
+
+typedef struct NRDESPIKE_PARAM_s
+{
+ MI_U8 u8BlendRatio; //0 ~ 15
+ MI_U8 u8StrengthCenterNeighbor; //0 ~ 5
+ MI_U8 u8StrengthMeanStd; //0 ~ 5
+ MI_U8 u8StrengthCornerCross; //0 ~ 5
+ MI_U8 u8DiffGainMeanStd; //0 ~ 31
+ MI_U8 u8DiffGainCenterNeighbor; //0 ~ 255
+ MI_U8 u8DiffThdCornerCross; //0 ~ 255
+ MI_U16 u16BlendLut[5]; //0 ~ 2047
+ MI_U8 u8StrengthByY[15]; //0 ~ 127
+} NRDESPIKE_PARAM_t;
+
+typedef struct NRDESPIKE_MANUAL_ATTR_s
+{
+ NRDESPIKE_PARAM_t stParaAPI;
+} NRDESPIKE_MANUAL_ATTR_t;
+
+typedef struct NRDESPIKE_AUTO_ATTR_s
+{
+ NRDESPIKE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRDESPIKE_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRDESPIKE_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRDESPIKE_AUTO_ATTR_t stAuto;
+ NRDESPIKE_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRDESPIKE_TYPE_t;
+
+typedef struct NRLUMA_PARAM_s
+{
+ MI_U8 u8Strength;
+ MI_U8 u8GMaskSel;
+ MI_U16 u16SpfBlendLut[2];
+} NRLUMA_PARAM_t;
+
+typedef struct NRLUMA_MANUAL_ATTR_s
+{
+ NRLUMA_PARAM_t stParaAPI;
+} NRLUMA_MANUAL_ATTR_t;
+
+typedef struct NRLUMA_AUTO_ATTR_s
+{
+ NRLUMA_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRLUMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRLUMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRLUMA_AUTO_ATTR_t stAuto;
+ NRLUMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRLUMA_TYPE_t;
+
+typedef struct NRLUMA_Adv_PARAM_s
+{
+ MI_ISP_BOOL_e bDbgEn;
+ MI_U8 u8Strength;
+ MI_U8 u8StrengthByY[10];
+ MI_U8 u8StrengthByMot[16];
+ MI_U16 u16EdgeTh[8];
+ MI_U32 u32EdgeGain[8];
+ MI_U8 u8StrengthByType[2];
+} NRLUMA_Adv_PARAM_t;
+
+typedef struct NRLUMA_Adv_MANUAL_ATTR_s
+{
+ NRLUMA_Adv_PARAM_t stParaAPI;
+} NRLUMA_Adv_MANUAL_ATTR_t;
+
+typedef struct NRLUMA_Adv_AUTO_ATTR_s
+{
+ NRLUMA_Adv_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRLUMA_Adv_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRLuma_Adv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRLUMA_Adv_AUTO_ATTR_t stAuto;
+ NRLUMA_Adv_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRLuma_Adv_TYPE_t;
+
+typedef struct NRChroma_PARAM_s
+{
+ MI_U8 u8MatchRatio; //0 ~ 127
+ MI_U16 u16UvTh; //0 ~ 1023
+ MI_U16 u16StrengthByCEdge[6]; //0 ~ 1023
+} NRChroma_PARAM_t;
+
+typedef struct NRChroma_MANUAL_ATTR_s
+{
+ NRChroma_PARAM_t stParaAPI;
+} NRChroma_MANUAL_ATTR_t;
+
+typedef struct NRChroma_AUTO_ATTR_s
+{
+ NRChroma_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRChroma_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRChroma_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRChroma_AUTO_ATTR_t stAuto;
+ NRChroma_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRChroma_TYPE_t;
+
+typedef struct NRChroma_Adv_PARAM_s
+{
+ MI_U8 u8StrengthByY[8]; //0 ~ 255
+ MI_U8 u8StrengthByYEdge[8]; //0 ~ 63
+ MI_U8 u8StrengthByCEdge[8]; //0 ~ 255
+ MI_U8 u8MaxStrength; //0 ~ 255
+ MI_U8 u8StaticLimitRatio; //0 ~ 63
+ MI_U8 u8MotionClip; //0 ~ 255
+ MI_U8 u8MotionColorReduce; //0 ~ 255
+ MI_U8 u8MotionColorRecover; //0 ~ 255
+ MI_U8 u8PreStrength; //0 ~ 128
+} NRChroma_Adv_PARAM_t;
+
+typedef struct NRChroma_Adv_MANUAL_ATTR_s
+{
+ NRChroma_Adv_PARAM_t stParaAPI;
+} NRChroma_Adv_MANUAL_ATTR_t;
+
+typedef struct NRChroma_Adv_AUTO_ATTR_s
+{
+ NRChroma_Adv_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRChroma_Adv_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRChroma_Adv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRChroma_Adv_AUTO_ATTR_t stAuto;
+ NRChroma_Adv_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRChroma_Adv_TYPE_t;
+
+typedef struct MI_ISP_IQ_NRChroma_Pre_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NRChroma_Pre_TYPE_t;
+
+typedef struct SHARPNESS_PARAM_s
+{
+ MI_U8 u8OverShootGain; //0 ~ 255
+ MI_U8 u8UnderShootGain; //0 ~ 255
+ MI_U8 u8CorLUT[6]; //0 ~ 255
+ MI_U8 u8SclLUT[6]; //0 ~ 255
+ MI_U16 u16EdgeKillLUT[6]; //0 ~ 1023
+ MI_U8 u8CornerReduce; //0 ~ 32
+ MI_U8 u8DirTh; //0 ~ 255
+ MI_U16 u16SharpnessUD[2]; //0 ~ 1023
+ MI_U16 u16SharpnessD[2]; //0 ~ 1023
+ MI_U8 u8PreCorUD[2]; //0 ~ 63
+ MI_U8 u8PreCorD[2]; //0 ~ 63
+ MI_U8 u8PreCorMotGain; //0 ~ 255
+ MI_U8 u8LpfEdgeGainUD; //0 ~ 255
+ MI_U8 u8LpfEdgeGainD; //0 ~ 255
+ MI_U8 u8WeakDetailEnhance; //0 ~ 15
+ MI_U16 u16DetailTh; //0 ~ 4095
+ MI_U8 u8DetailMotOffset; //0 ~ 255
+ MI_U8 u8DetailByY[6]; //0 ~ 255
+ MI_U16 u16OverShootLimit; //0 ~ 1023
+ MI_U16 u16UnderShootLimit; //0 ~ 1023
+ MI_U8 u8MotGain[16]; //0 ~ 255
+} SHARPNESS_PARAM_t;
+
+typedef struct SHARPNESS_MANUAL_ATTR_s
+{
+ SHARPNESS_PARAM_t stParaAPI;
+} SHARPNESS_MANUAL_ATTR_t;
+
+typedef struct SHARPNESS_AUTO_ATTR_s
+{
+ SHARPNESS_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} SHARPNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_SHARPNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ SHARPNESS_AUTO_ATTR_t stAuto;
+ SHARPNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SHARPNESS_TYPE_t;
+
+typedef struct SHARPNESS_EX_PARAM_s
+{
+ MI_ISP_BOOL_e bDbgEn; //0 ~ 1
+ MI_U8 u8DirSel; //0 ~ 1
+ MI_U8 u8DirOffA; //0 ~ 255
+ MI_U8 u8MaxRatio; //0 ~ 255
+ MI_U8 u8LpfY; //0 ~ 1
+ MI_U8 u8SblLutY[6]; //0 ~ 255
+ MI_U8 u8Sbl2LutY[6]; //0 ~ 255
+ MI_U8 u8StrengthByHue[24]; //0 ~ 255
+} SHARPNESS_EX_PARAM_t;
+
+typedef struct SHARPNESS_EX_MANUAL_ATTR_s
+{
+ SHARPNESS_EX_PARAM_t stParaAPI;
+} SHARPNESS_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_SHARPNESS_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ SHARPNESS_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SHARPNESS_EX_TYPE_t;
+
+typedef struct CROSSTALK_PARAM_s
+{
+ MI_U8 u8Strength; //0 ~ 31
+ MI_U8 u8StrengthByY[15]; //0 ~ 127
+ MI_U8 u8Threshold; //0 ~ 255
+ MI_U16 u16Offset; //0 ~ 4095
+} CROSSTALK_PARAM_t;
+
+typedef struct CROSSTALK_MANUAL_ATTR_s
+{
+ CROSSTALK_PARAM_t stParaAPI;
+} CROSSTALK_MANUAL_ATTR_t;
+
+typedef struct CROSSTALK_AUTO_ATTR_s
+{
+ CROSSTALK_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} CROSSTALK_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_CROSSTALK_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ CROSSTALK_AUTO_ATTR_t stAuto;
+ CROSSTALK_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_CROSSTALK_TYPE_t;
+
+typedef struct OBC_PARAM_s
+{
+ MI_U16 u16ValR; //0 ~ 255
+ MI_U16 u16ValGr; //0 ~ 255
+ MI_U16 u16ValGb; //0 ~ 255
+ MI_U16 u16ValB; //0 ~ 255
+} OBC_PARAM_t;
+
+typedef struct OBC_MANUAL_ATTR_s
+{
+ OBC_PARAM_t stParaAPI;
+} OBC_MANUAL_ATTR_t;
+
+typedef struct OBC_AUTO_ATTR_s
+{
+ OBC_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} OBC_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_OBC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ OBC_AUTO_ATTR_t stAuto;
+ OBC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_OBC_TYPE_t;
+
+typedef struct WDR_PARAM_s
+{
+ MI_U8 u8BoxNum; //1 ~ 4
+ MI_U8 u8PreEnhance; //0 ~ 6
+ MI_ISP_BOOL_e bAutoDetailEnhance; //0 ~ 1
+ MI_U8 u8ManualDetailEnhance; //0~255; default:128
+ MI_U8 u8GlobalDarkToneEnhance; //0 ~ 15
+ MI_U8 u8WDRStrByY[33]; //0 ~ 255
+ MI_U8 u8Strength; //0 ~ 255
+ MI_U8 u8DarkLimit; //0 ~ 255
+ MI_U8 u8BrightLimit; //0 ~ 255
+ MI_ISP_BOOL_e bGammaSyncEn; //0 ~ 1
+} WDR_PARAM_t;
+
+typedef struct WDR_MANUAL_ATTR_s
+{
+ WDR_PARAM_t stParaAPI;
+} WDR_MANUAL_ATTR_t;
+
+typedef struct WDR_AUTO_ATTR_s
+{
+ WDR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDR_AUTO_ATTR_t stAuto;
+ WDR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDR_TYPE_t;
+
+typedef struct WDRCurveFull_PARAM_s
+{
+ MI_U16 u16FCurve[256];
+} WDRCurveFull_PARAM_t;
+
+typedef struct WDRCurveFull_MANUAL_ATTR_s
+{
+ WDRCurveFull_PARAM_t stParaAPI;
+} WDRCurveFull_MANUAL_ATTR_t;
+
+typedef struct WDRCurveFull_AUTO_ATTR_s
+{
+ WDRCurveFull_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDRCurveFull_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDRCurveFull_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDRCurveFull_AUTO_ATTR_t stAuto;
+ WDRCurveFull_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDRCurveFull_TYPE_t;
+
+typedef struct WDRCurveAdv_PARAM_s
+{
+ MI_U16 u16Slope; //1024~16384
+ MI_U8 u8TransitionPoint0; //0~255
+ MI_U8 u8TransitionPoint1; //0~255
+ MI_U8 u8SaturatedPoint; //0~255
+ MI_U8 u8CurveModeSel; //0~5
+} WDRCurveAdv_PARAM_t;
+
+typedef struct WDRCurveAdv_MANUAL_ATTR_s
+{
+ WDRCurveAdv_PARAM_t stParaAPI;
+} WDRCurveAdv_MANUAL_ATTR_t;
+
+typedef struct WDRCurveAdv_AUTO_ATTR_s
+{
+ WDRCurveAdv_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDRCurveAdv_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDRCurveAdv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDRCurveAdv_AUTO_ATTR_t stAuto;
+ WDRCurveAdv_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDRCurveAdv_TYPE_t;
+
+typedef struct DYNAMIC_DP_PARAM_s
+{
+ MI_ISP_BOOL_e bHotPixEn; //0 ~ 1
+ MI_U16 u16HotPixCompSlpoe;
+ MI_ISP_BOOL_e bDarkPixEn; //0 ~ 1
+ MI_U16 u16DarkPixCompSlpoe;
+ MI_U16 u16DPCTH;
+ MI_ISP_BOOL_e bBlendEn;
+ MI_U16 u16DiffLut[6];
+ MI_U16 u16YLut[6];
+} DYNAMIC_DP_PARAM_t;
+
+typedef struct DYNAMIC_DP_MANUAL_ATTR_s
+{
+ DYNAMIC_DP_PARAM_t stParaAPI;
+} DYNAMIC_DP_MANUAL_ATTR_t;
+
+typedef struct DYNAMIC_DP_AUTO_ATTR_s
+{
+ DYNAMIC_DP_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} DYNAMIC_DP_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DYNAMIC_DP_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DYNAMIC_DP_AUTO_ATTR_t stAuto;
+ DYNAMIC_DP_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DYNAMIC_DP_TYPE_t;
+
+typedef struct DYNAMIC_DP_CLUSTER_ATTR_S
+{
+ MI_ISP_BOOL_e bEdgeMode;
+ MI_U16 u16NeiDeltaTh;
+ MI_U8 u8NeiSmooth;
+ MI_ISP_BOOL_e bSortEn;
+ MI_ISP_BOOL_e bSortRGGBEn[4];
+ MI_ISP_BOOL_e bSort1x3ModeEn;
+ MI_U16 u16SortLumTblL[6];
+ MI_U16 u16SortLumTblD[6];
+ MI_U16 u16SortLumTblS[6];
+} DYNAMIC_DP_CLUSTER_ATTR_S;
+
+typedef struct
+{
+ DYNAMIC_DP_CLUSTER_ATTR_S stParaAPI;
+} DYNAMIC_DP_CLUSTER_MANUAL_ATTR_S;
+
+typedef struct
+{
+ DYNAMIC_DP_CLUSTER_ATTR_S stParaAPI[MI_ISP_AUTO_NUM];
+} DYNAMIC_DP_CLUSTER_AUTO_ATTR_S;
+
+typedef struct MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DYNAMIC_DP_CLUSTER_AUTO_ATTR_S stAuto;
+ DYNAMIC_DP_CLUSTER_MANUAL_ATTR_S stManual;
+} MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t;
+
+typedef struct HSV_PARAM_s
+{
+ MI_S16 s16HueLut[24]; //-64 ~ 64
+ MI_U16 u16SatLut[24]; // 0 ~ 255 (64->1X)
+ MI_S16 s16HueLut_ForUnitCCM[24]; //-64 ~ 64
+ MI_U16 u16SatLut_ForUnitCCM[24]; // 0 ~ 255 (64->1X)
+ MI_U8 u8GlobalSat; // 0 ~ 255 (64->1x)
+} HSV_PARAM_t;
+
+typedef struct HSV_MANUAL_ATTR_s
+{
+ HSV_PARAM_t stParaAPI;
+} HSV_MANUAL_ATTR_t;
+
+typedef struct HSV_AUTO_ATTR_s
+{
+ HSV_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} HSV_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_HSV_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ HSV_AUTO_ATTR_t stAuto;
+ HSV_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HSV_TYPE_t;
+
+typedef struct RGBIR_PARAM_s
+{
+ MI_U8 u8IrPosType; //0 ~ 7, def : 0
+ MI_ISP_BOOL_e bRemovelEn; //0 ~ 1, def : 1
+ MI_U16 u16Ratio_R[6];
+ MI_U16 u16Ratio_G[6];
+ MI_U16 u16Ratio_B[6];
+} RGBIR_PARAM_t;
+
+typedef struct RGBIR_MANUAL_ATTR_s
+{
+ RGBIR_PARAM_t stParaAPI;
+} RGBIR_MANUAL_ATTR_t;
+
+typedef struct RGBIR_AUTO_ATTR_s
+{
+ RGBIR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBIR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBIR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBIR_AUTO_ATTR_t stAuto;
+ RGBIR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBIR_TYPE_t;
+
+typedef struct MI_ISP_IQ_FPN_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_FPN_TYPE_t;
+
+typedef struct PFC_PARAM_s
+{
+ MI_U8 u8Strength; //0 ~ 255
+ MI_U8 u8UStrength; //0 ~ 63
+ MI_U8 u8VStrength; //0 ~ 63
+ MI_U8 u8StrengthByY[8]; //0 ~ 255
+ MI_U8 u8FlatProtect; //0 ~ 127
+ MI_U8 u8SatByY[2]; //0 ~ 25
+ MI_U8 u8SatSrcSel; //0 ~ 1
+ MI_U8 u8StrengthByContrast[8]; //0 ~ 127
+} PFC_PARAM_t;
+
+typedef struct PFC_MANUAL_ATTR_s
+{
+ PFC_PARAM_t stParaAPI;
+} PFC_MANUAL_ATTR_t;
+
+typedef struct PFC_AUTO_ATTR_s
+{
+ PFC_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} PFC_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_PFC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ PFC_AUTO_ATTR_t stAuto;
+ PFC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_PFC_TYPE_t;
+
+typedef struct PFC_EX_PARAM_s
+{
+ MI_ISP_BOOL_e bDbgEn; //0 ~ 1
+ MI_ISP_BOOL_e bGSkipEn; //0 ~ 1
+ MI_U8 u8SatMaskSel; //0 ~ 1
+ MI_ISP_BOOL_e bSatAmpEn; //0 ~ 1
+ MI_U8 u8StrengthByHue[12]; //0 ~ 255
+} PFC_EX_PARAM_t;
+
+typedef struct PFC_EX_MANUAL_ATTR_s
+{
+ PFC_EX_PARAM_t stParaAPI;
+} PFC_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_PFC_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ PFC_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_PFC_EX_TYPE_t;
+
+typedef struct DEMOSAIC_PARAM_s
+{
+ MI_U8 u8DirThrd; //0~63 def:35
+ MI_U8 u8EdgeSmoothThrdY; //0~255 def:230
+ MI_U8 u8EdgeSmoothThrdC; //0~127 def:20
+} DEMOSAIC_PARAM_t;
+
+typedef struct DEMOSAIC_MANUAL_ATTR_s
+{
+ DEMOSAIC_PARAM_t stParaAPI;
+} DEMOSAIC_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_DEMOSAIC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ DEMOSAIC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DEMOSAIC_TYPE_t;
+
+typedef struct COLORTRANS_PARAM_s
+{
+ MI_U16 u16Y_OFST; //0 ~ 2047
+ MI_U16 u16U_OFST; //0 ~ 2047
+ MI_U16 u16V_OFST; //0 ~ 2047
+ MI_U16 u16Matrix[9]; //0 ~ 1023
+} COLORTRANS_PARAM_t;
+
+typedef struct COLORTRANS_MANUAL_ATTR_s
+{
+ COLORTRANS_PARAM_t stParaAPI;
+} COLORTRANS_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_COLORTRANS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ COLORTRANS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_COLORTRANS_TYPE_t;
+
+typedef struct HDR_PARAM_s
+{
+ MI_ISP_BOOL_e bNrEn;
+ MI_U16 u16YwtTh1;
+ MI_U16 u16YwtTh2;
+ MI_U16 u16NoiseLevel[16];
+ MI_U16 u16MotionTh;
+ MI_U16 u16MotionAdjLut[7];
+} HDR_PARAM_t;
+
+typedef struct HDR_MANUAL_ATTR_s
+{
+ HDR_PARAM_t stParaAPI;
+} HDR_MANUAL_ATTR_t;
+
+typedef struct HDR_AUTO_ATTR_s
+{
+ HDR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} HDR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_HDR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ HDR_AUTO_ATTR_t stAuto;
+ HDR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HDR_TYPE_t;
+
+typedef struct HDR_EX_PARAM_s
+{
+ MI_U16 u16SensorExpRatio;
+ MI_ISP_BOOL_e bDynRatioEn;
+ MI_U8 u8DynRatioSrcSel;
+ MI_U8 u8YSrcSel;
+ MI_U8 u8NoiseLevelSrcSel;
+ MI_U8 u8MotionMaxVal;
+ MI_U16 u16MotionLumaTh;
+ MI_U8 u8MotionAdjSft[6];
+} HDR_EX_PARAM_t;
+
+typedef struct HDR_EX_MANUAL_ATTR_s
+{
+ HDR_EX_PARAM_t stParaAPI;
+} HDR_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_HDR_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ HDR_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HDR_EX_TYPE_t;
+
+typedef struct MI_ISP_IQ_EFFECT_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_EFFECT_TYPE_t;
+
+typedef struct MI_ISP_IQ_SYS_MCNR_MEMORY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_SYS_MCNR_MEMORY_TYPE_t;
+
+typedef struct MI_ISP_IQ_LSC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U16 u16CenterX;
+ MI_U16 u16CenterY;
+ MI_U8 u8Shift;
+ MI_U16 u16RGainTable[32*3];
+ MI_U16 u16GGainTable[32*3];
+ MI_U16 u16BGainTable[32*3];
+} MI_ISP_IQ_LSC_TYPE_t;
+
+typedef struct MI_ISP_IQ_LSC_CTRL_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8RRatioByCct[3];
+ MI_U8 u8GRatioByCct[3];
+ MI_U8 u8BRatioByCct[3];
+ MI_INTP_LUT_IQ RatioByBv;
+} MI_ISP_IQ_LSC_CTRL_TYPE_t;
+
+typedef struct MI_ISP_IQ_ALSC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8GridX;
+ MI_U8 u8GridY;
+ MI_U16 u16CCTthr[3];
+ MI_U8 u8DeltaMode;
+ MI_ISP_BOOL_e bDeltaModeAdvEn;
+ MI_U8 u8DeltaLutX[26];
+ MI_U8 u8DeltaLutY[26];
+ MI_U16 u16TableR[3][ALSC_TBL_MAX];
+ MI_U16 u16TableG[3][ALSC_TBL_MAX];
+ MI_U16 u16TableB[3][ALSC_TBL_MAX];
+} MI_ISP_IQ_ALSC_TYPE_t;
+
+typedef struct MI_ISP_IQ_ALSC_CTRL_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8RRatioByCct[3];
+ MI_U8 u8GRatioByCct[3];
+ MI_U8 u8BRatioByCct[3];
+ MI_INTP_LUT_IQ RatioByBv;
+} MI_ISP_IQ_ALSC_CTRL_TYPE_t;
+
+typedef struct R2Y_PARAM_s
+{
+ MI_U16 u16Matrix[9];
+ MI_U8 u8AddY16;
+} R2Y_PARAM_t;
+
+typedef struct R2Y_MANUAL_ATTR_s
+{
+ R2Y_PARAM_t stParaAPI;
+} R2Y_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_R2Y_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ R2Y_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_R2Y_TYPE_t;
+
+typedef struct DUMMY_ATTR_s
+{
+ MI_S16 s16Dummy0[256];
+ MI_S16 s16Dummy1[256];
+ MI_S16 s16Dummy2[256];
+ MI_S16 s16Dummy3;
+ MI_S16 s16Dummy4;
+} DUMMY_ATTR_t;
+
+typedef struct DUMMY_MANUAL_ATTR_s
+{
+ DUMMY_ATTR_t stParaAPI;
+} DUMMY_MANUAL_ATTR_t;
+
+typedef struct DUMMY_AUTO_ATTR_s
+{
+ DUMMY_ATTR_t stParaAPI[MI_ISP_AUTO_NUM];
+} DUMMY_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DUMMY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ DUMMY_AUTO_ATTR_t stAuto;
+ DUMMY_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DUMMY_TYPE_t;
+
+typedef struct DUMMY_EX_ATTR_s
+{
+ MI_S16 s16DummyEx0[256];
+ MI_S16 s16DummyEx1[256];
+ MI_S16 s16DummyEx2[256];
+ MI_S16 s16DummyEx3;
+ MI_S16 s16DummyEx4;
+} DUMMY_EX_ATTR_t;
+
+typedef struct
+{
+ DUMMY_EX_ATTR_t stParaAPI;
+} DUMMY_EX_MANUAL_ATTR_S;
+
+typedef struct MI_ISP_IQ_DUMMY_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ DUMMY_EX_MANUAL_ATTR_S stManual;
+} MI_ISP_IQ_DUMMY_EX_TYPE_t;
+
+#endif
+
+#if 1 // ISP IQ API
+typedef struct IQ_VERSION_INFO_PARAM_s
+{
+ MI_U32 u32Vendor;
+ MI_U32 u32Major;
+ MI_U32 u32Minor;
+} IQ_VERSION_INFO_PARAM_t;
+
+typedef struct MI_ISP_IQ_VERSION_INFO_TYPE_s
+{
+ IQ_VERSION_INFO_PARAM_t stParaAPI;
+} MI_ISP_IQ_VERSION_INFO_TYPE_t;
+
+typedef struct IQ_PARAM_INIT_INFO_PARAM_s
+{
+ MI_ISP_BOOL_e bFlag;
+} IQ_PARAM_INIT_INFO_PARAM_t;
+
+typedef struct MI_ISP_IQ_PARAM_INIT_INFO_TYPE_s
+{
+ IQ_PARAM_INIT_INFO_PARAM_t stParaAPI;
+} MI_ISP_IQ_PARAM_INIT_INFO_TYPE_t;
+
+typedef struct FAST_MODE_PARAM_s
+{
+ MI_ISP_BOOL_e bFastMode;
+} FAST_MODE_PARAM_t;
+
+typedef struct MI_ISP_IQ_FAST_MODE_TYPE_s
+{
+ FAST_MODE_PARAM_t stParaAPI;
+} MI_ISP_IQ_FAST_MODE_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_IQ_PARAM_MODE_NORMAL = 0,
+ SS_IQ_PARAM_MODE_NIGHT = 1, //Night Mode
+ SS_IQ_PARAM_MODE_MAX
+} MI_ISP_IQ_PARAM_MODE_e;
+
+typedef struct MI_ISP_IQ_GAMMA_LUT_TYPE_s
+{
+ MI_U16 u16LutR[256];
+ MI_U16 u16LutG[256];
+ MI_U16 u16LutB[256];
+} MI_ISP_IQ_GAMMA_LUT_TYPE_t;
+
+typedef struct MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16BTGamma[256];
+ MI_U16 u16DTGamma[256];
+} MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_t;
+
+typedef struct MI_ISP_IQ_OBC4Ch_TYPE_s
+{
+ MI_U16 u16OBC4Ch[4];
+} MI_ISP_IQ_OBC4Ch_TYPE_t;
+#endif
+
+typedef struct TEMP_PARAM_s
+{
+ MI_S16 s16ObcOffset;
+ MI_U8 u8DynamicDPRatio;
+ MI_U8 u8CrosstalkRatio;
+ MI_U8 u8NRDeSpikeRatio;
+ MI_U8 u8NR3DRatio[2];
+ MI_U8 u8NRLumaRatio;
+ MI_U8 u8SharpnessRatio[2];
+ MI_U8 u8SaturationRatio;
+ MI_U8 u8ColorToneRatio[3];
+} TEMP_PARAM_t;
+
+typedef struct TEMP_MANUAL_ATTR_s
+{
+ TEMP_PARAM_t stParaAPI;
+} TEMP_MANUAL_ATTR_t;
+
+typedef struct TEMP_AUTO_ATTR_s
+{
+ TEMP_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} TEMP_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_TEMP_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8TemperatureLut[16];
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ TEMP_AUTO_ATTR_t stAuto;
+ TEMP_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_TEMP_TYPE_t;
+
+typedef struct MI_ISP_IQ_TEMP_INFO_TYPE_s
+{
+ MI_U8 u8Temperature;
+} MI_ISP_IQ_TEMP_INFO_TYPE_t;
+
+#if 1 // MAINTOOL API
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_IQ_INDEX_0 = 0,
+ SS_IQ_INDEX_1,
+ SS_IQ_INDEX_2,
+ SS_IQ_INDEX_3,
+ SS_IQ_INDEX_4,
+ SS_IQ_INDEX_5,
+ SS_IQ_INDEX_6,
+ SS_IQ_INDEX_7,
+ SS_IQ_INDEX_8,
+ SS_IQ_INDEX_9,
+ SS_IQ_INDEX_10,
+ SS_IQ_INDEX_11,
+ SS_IQ_INDEX_12,
+ SS_IQ_INDEX_13,
+ SS_IQ_INDEX_14,
+ SS_IQ_INDEX_15,
+ SS_IQ_INDEX_MAX
+} MI_ISP_IQ_INDEX_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_BYPASS_OFF = 0,
+ SS_BYPASS_ON,
+ SS_BYPASS_MAX
+} MI_ISP_BYPASS_MODE_e;
+
+typedef struct MI_ISP_API_BYPASS_TYPE_s
+{
+ MI_ISP_BYPASS_MODE_e bEnable; //0 ~ 1
+ MI_ISP_API_ID_e eAPIIndex;
+} MI_ISP_API_BYPASS_TYPE_t;
+#endif
+
+
+/************************************* IQ - Define the structure declaration - END *************************************/
+
+
+#endif /* _MI_ISP_IQ_DATATYPE_H_ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp.h
new file mode 100644
index 00000000..f2168e54
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp.h
@@ -0,0 +1,109 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_H_
+#define _MI_ISP_H_
+//#include <pthread.h>
+
+#include "mi_common.h"
+#include "mi_isp_datatype.h"
+#include "mi_vpe_datatype.h"
+#include "mi_isp_iq.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MI_ISP_OK (0)
+#define MI_ISP_NOT_SUPPORT (1)
+#define MI_ISP_FAILURE (-1)
+#define MI_ISP_API_MAX_PARM_NUMBRE (6)
+#define MI_ISP_API_ISPMID_NOT_SUPPORT (5)
+
+ /************************************* Customer 3A API ***********************************/
+ MI_S32 MI_ISP_AE_GetAeHwAvgStats(MI_U32 Channel, MI_ISP_AE_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AWB_GetAwbHwAvgStats(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AWB_GetAwbHwAvgStatsShort(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetHisto0HwStats(MI_U32 Channel, MI_ISP_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetHisto1HwStats(MI_U32 Channel, MI_ISP_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetRgbIrHistoHwStats(MI_U32 Channel, MI_ISP_RGBIR_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_CUS3A_Enable(MI_U32 Channel, Cus3AEnable_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAeInitStatus(MI_U32 Channel, CusAEInitParam_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAeStatus(MI_U32 Channel, CusAEInfo_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAeParam(MI_U32 Channel, CusAEResult_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAwbStatus(MI_U32 Channel, CusAWBInfo_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAwbParam(MI_U32 Channel, CusAWBResult_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAEWindowBlockNumber(MI_U32 Channel, MS_CUST_AE_WIN_BLOCK_NUM_TYPE_e *data);
+ MI_S32 MI_ISP_CUS3A_SetAEHistogramWindow(MI_U32 Channel, CusAEHistWin_t*data);
+ MI_S32 MI_ISP_CUS3A_SetAWBSampling(MI_U32 Channel, CusAWBSample_t *data);
+
+ MI_S32 MI_ISP_CUS3A_GetAFStats(MI_U32 Channel, CusAFStats_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFWindow(MI_U32 Channel, CusAFWin_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFWindow(MI_U32 Channel, CusAFWin_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFFilter(MI_U32 Channel, CusAFFilter_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFFilter(MI_U32 Channel, CusAFFilter_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFFilterSq(MI_U32 Channel, CusAFFilterSq_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFFilterSq(MI_U32 Channel, CusAFFilterSq_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFRoiMode(MI_U32 Channel, CusAFRoiMode_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFRoiMode(MI_U32 Channel, CusAFRoiMode_t *data);
+
+ MI_S32 MI_ISP_CUS3A_GetImageResolution(MI_U32 Channel, CusImageResolution_t *data);
+ MI_S32 MI_ISP_CUS3A_EnableISPOutImage(MI_U32 Channel, CusISPOutImage_t *data);
+ MI_S32 MI_ISP_CUS3A_GetISPOutImageCount(MI_U32 Channel, MI_U32 *data);
+ MI_S32 MI_ISP_CUS3A_CaptureHdrRawImage(MI_U32 Channel, CusHdrRawImage_t *data);
+ MI_S32 MI_ISP_GetFrameMetaInfo(MI_U32 Channel, IspFrameMetaInfo_t *data);
+ MI_S32 MI_ISP_ReadSensorData(MI_U32 Channel, CusSensorI2cParam_t *data);
+ MI_S32 MI_ISP_WriteSensorData(MI_U32 Channel, CusSensorI2cParam_t *data);
+ /************************************* Customer 3A API END********************************/
+ /************************************* Debug API ***********************************/
+ MI_S32 MI_ISP_SetDebugLevel_AE(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_GetDebugLevel_AE(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_SetDebugLevel_AWB(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_GetDebugLevel_AWB(MI_U32 Channel, MI_S32 *data);
+ /************************************* Debug API END********************************/
+
+ MI_S32 MI_ISP_SET_ALL(int Channel, MI_U16 ApiId, MI_U32 ApiLen, MI_U8* pApiBuf);
+ MI_S32 MI_ISP_GET_ALL(int Channel, MI_U16 ApiId, MI_U32* ApiLen, MI_U8* pApiBuf);
+
+ MI_S32 MI_ISP_API_CmdLoadBinFile(MI_U32 Channel, char* filepath, MI_U32 user_key);
+ MI_S32 MI_ISP_API_CmdLoadCaliData(MI_U32 Channel, MI_ISP_CALI_ITEM_e eCaliItem, char* filepath);
+
+ typedef MI_S32 (*MI_ISP_ApiAgent_fp)(MI_VPE_IspApiHeader_t *pstData, void* pData);
+
+ /*Api agent for SigmaStar user space 3A library*/
+ MI_S32 MI_ISP_RegisterIspApiAgent(MI_U32 Channel, MI_ISP_ApiAgent_fp fpApiSet, MI_ISP_ApiAgent_fp fpApiGet);
+#if !defined(DUAL_OS) && !defined(__RTOS__) //for pure linux
+ MI_S32 MI_ISP_EnableUserspace3A(MI_U32 Channel,MI_ISP_API_USERSPACE3A_ATTR_t *pAttr);
+ MI_S32 MI_ISP_DisableUserspace3A(MI_U32 Channel);
+#else //for DualOS-Linux , RTK
+ inline MI_S32 MI_ISP_EnableUserspace3A(MI_U32 Channel,MI_ISP_API_USERSPACE3A_ATTR_t *pAttr) {return 0;}
+ inline MI_S32 MI_ISP_DisableUserspace3A(MI_U32 Channel) {return 0;}
+#endif
+
+ /*Common API, get isp root path*/
+ MI_S32 MI_ISP_GetIspRoot(MI_U32 Channel, MI_ISP_ROOT_PATH_T *data);
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_3a_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_3a_datatype.h
new file mode 100644
index 00000000..0472f982
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_3a_datatype.h
@@ -0,0 +1,441 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_ISP_3A_DATATYPE_H_
+#define _MI_ISP_3A_DATATYPE_H_
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_FALSE = 0,
+ SS_TRUE = !SS_FALSE,
+ SS_BOOL_MAX
+} MI_ISP_BOOL_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_OP_TYP_AUTO = 0,
+ SS_OP_TYP_MANUAL = !SS_OP_TYP_AUTO,
+ SS_OP_TYP_MODE_MAX
+} MI_ISP_OP_TYPE_e;
+
+/************************************* AE - Define the structure declaration - START *************************************/
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_ISP_STATE_NORMAL = 0,
+ SS_ISP_STATE_PAUSE = 1,
+ SS_ISP_STATE_MAX
+} MI_ISP_SM_STATE_TYPE_e;
+
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_MODE_A, // auto
+ SS_AE_MODE_AV, // aperture priority
+ SS_AE_MODE_SV,
+ SS_AE_MODE_TV, // shutter priority
+ SS_AE_MODE_M, // manual mode
+ SS_AE_MODE_MAX
+} MI_ISP_AE_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_WEIGHT_AVERAGE = 0,
+ SS_AE_WEIGHT_CENTER,
+ SS_AE_WEIGHT_SPOT,
+ SS_AE_WEIGHT_MAX
+} MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_FLICKER_TYPE_DISABLE = 0,
+ SS_AE_FLICKER_TYPE_60HZ = 1,
+ SS_AE_FLICKER_TYPE_50HZ = 2,
+ SS_AE_FLICKER_TYPE_AUTO = 3,
+ //SS_AE_FLICKER_TYPE_DETECT_60HZ = 4,
+ //SS_AE_FLICKER_TYPE_DETECT_50HZ = 5,
+ SS_AE_FLICKER_TYPE_MAX
+} MI_ISP_AE_FLICKER_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_FLICKER_TYPE_DETECT_60HZ = 0,
+ SS_AE_FLICKER_TYPE_DETECT_50HZ = 1,
+ SS_AE_FLICKER_TYPE_DETECT_MAX
+} MI_ISP_AE_FLICKER_DETECT_TYPE_e;
+
+//typedef struct MI_ISP_AE_FLICKER_INFO_TYPE_s
+//{
+// MI_ISP_BOOL_e bIsEffective;
+// MI_ISP_AE_FLICKER_TYPE_e eFlickerType;
+// MI_U16 u16Score;
+//} MI_ISP_AE_FLICKER_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_FLICKER_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ MI_U8 u8AmpSensitivity; // 1 ~ 100
+ MI_U8 u8ScoreThd; // 1 ~ 100
+ MI_U8 uRefreshCycles; // 1 ~ 10
+ MI_U8 u8ValidTimesThd; // 1 ~ 10
+ MI_ISP_AE_FLICKER_DETECT_TYPE_e eFlickerType; // 60Hz = 0, 50Hz = 1
+} MI_ISP_AE_FLICKER_EX_TYPE_t;
+
+typedef struct MI_ISP_AE_FLICKER_EX_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsEffective;
+ MI_ISP_AE_FLICKER_DETECT_TYPE_e eFlickerType;
+ MI_U16 u16Score;
+} MI_ISP_AE_FLICKER_EX_INFO_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_BRIGHTTONE,
+ SS_AE_STRATEGY_DARKTONE,
+ SS_AE_STRATEGY_AUTO,
+ SS_AE_STRATEGY_MAX
+} MI_ISP_AE_STRATEGY_TYPE_e;
+
+typedef struct MI_ISP_AE_HIST_WEIGHT_Y_TYPE_s
+{
+ MI_U32 u32LumY;
+ MI_U32 u32AvgY;
+ MI_U32 u32Hits[128];
+} MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_VALUE_TYPE_s
+{
+ MI_U32 u32FNx10;
+ MI_U32 u32SensorGain;
+ MI_U32 u32ISPGain;
+ MI_U32 u32US;
+} MI_ISP_AE_EXPO_VALUE_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsStable;
+ MI_ISP_BOOL_e bIsReachBoundary;
+ MI_ISP_AE_EXPO_VALUE_TYPE_t stExpoValueLong;
+ MI_ISP_AE_EXPO_VALUE_TYPE_t stExpoValueShort;
+ MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t stHistWeightY;
+ MI_U32 u32LVx10;
+ MI_S32 s32BV;
+ MI_U32 u32SceneTarget;
+} MI_ISP_AE_EXPO_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_EV_COMP_TYPE_s
+{
+ MI_S32 s32EV;
+ MI_U32 u32Grad;
+} MI_ISP_AE_EV_COMP_TYPE_t;
+
+typedef struct MI_ISP_AE_INTP_LUT_TYPE_s
+{
+ MI_U16 u16NumOfPoints;
+ MI_U32 u32Y[16];
+ MI_U32 u32X[16];
+} MI_ISP_AE_INTP_LUT_TYPE_t;
+
+typedef struct CONV_SPEED_PARAM_s
+{
+ MI_U32 u32SpeedX[4];
+ MI_U32 u32SpeedY[4];
+} CONV_SPEED_PARAM_t;
+
+typedef struct CONV_THD_PARAM_s
+{
+ MI_U32 u32InThd;
+ MI_U32 u32OutThd;
+} CONV_THD_PARAM_t;
+
+typedef struct MI_ISP_AE_CONV_CONDITON_TYPE_s
+{
+ CONV_THD_PARAM_t stConvThrd;
+ CONV_SPEED_PARAM_t stConvSpeed;
+} MI_ISP_AE_CONV_CONDITON_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_LIMIT_TYPE_s
+{
+ MI_U32 u32MinShutterUS;
+ MI_U32 u32MaxShutterUS;
+ MI_U32 u32MinFNx10;
+ MI_U32 u32MaxFNx10;
+ MI_U32 u32MinSensorGain;
+ MI_U32 u32MinISPGain;
+ MI_U32 u32MaxSensorGain;
+ MI_U32 u32MaxISPGain;
+} MI_ISP_AE_EXPO_LIMIT_TYPE_t;
+
+typedef struct EXPO_POINT_PARAM_s
+{
+ MI_U32 u32FNumx10;
+ MI_U32 u32Shutter;
+ MI_U32 u32TotalGain;
+ MI_U32 u32SensorGain;
+} EXPO_POINT_PARAM_t;
+
+typedef struct MI_ISP_AE_EXPO_TABLE_TYPE_s
+{
+ MI_U32 u32NumPoints;
+ EXPO_POINT_PARAM_t stExpoTbl[16]; // LV from High to Low
+} MI_ISP_AE_EXPO_TABLE_TYPE_t;
+
+typedef struct WIN_WEIGHT_PARAM_s
+{
+ MI_U8 u8AverageTbl[32*32];
+ MI_U8 u8CenterTbl[32*32];
+ MI_U8 u8SpotTbl[32*32];
+} WIN_WEIGHT_PARAM_t;
+
+typedef struct MI_ISP_AE_WIN_WEIGHT_TYPE_s
+{
+ MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e eTypeID;
+ WIN_WEIGHT_PARAM_t stParaAPI;
+} MI_ISP_AE_WIN_WEIGHT_TYPE_t;
+
+typedef struct MI_ISP_AE_STRATEGY_TYPE_s
+{
+ MI_ISP_AE_STRATEGY_TYPE_e eAEStrategyMode;
+ MI_U32 u32Weighting;
+ MI_ISP_AE_INTP_LUT_TYPE_t stUpperOffset;
+ MI_ISP_AE_INTP_LUT_TYPE_t stLowerOffset;
+ MI_U32 u32BrightToneStrength;
+ MI_U32 u32BrightToneSensitivity;
+ MI_U32 u32DarkToneStrength;
+ MI_U32 u32DarkToneSensitivity;
+ MI_U32 u32AutoStrength;
+ MI_U32 u32AutoSensitivity;
+} MI_ISP_AE_STRATEGY_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_EX_BRIGHTTONE,
+ SS_AE_STRATEGY_EX_DARKTONE,
+} MI_ISP_AE_STRATEGY_EX_PRIORITY_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_EX_COUNT,
+ SS_AE_STRATEGY_EX_TARGET,
+} MI_ISP_AE_STRATEGY_EX_MODE_e;
+
+typedef struct MI_ISP_AE_STRATEGY_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_ISP_AE_STRATEGY_EX_MODE_e eMode;
+ MI_ISP_AE_STRATEGY_EX_PRIORITY_e ePriority;
+ MI_U16 u16BT_NodeNum;
+ MI_S32 u32BT_NodeBV[16];
+ MI_U32 u32BT_ThdY[16];
+ MI_U32 u32BT_Percentx10[16];
+ MI_U32 u32BT_TargetYx10[16];
+ MI_U32 u32BT_MaxOffsetDown[16];
+ MI_U16 u16DT_NodeNum;
+ MI_S32 u32DT_NodeBV[16];
+ MI_U32 u32DT_ThdY[16];
+ MI_U32 u32DT_Percentx10[16];
+ MI_U32 u32DT_TargetYx10[16];
+ MI_U32 u32DT_MaxOffsetUp[16];
+} MI_ISP_AE_STRATEGY_EX_TYPE_t;
+
+typedef struct MI_ISP_AE_STRATEGY_EX_INFO_TYPE_s
+{
+ MI_U16 u16GMBlendRatio;
+ MI_U16 u16UpperLimitTargetx10;
+ MI_U16 u16LowerLimitTargetx10;
+ MI_U16 u16BTCntPcntx10;
+ MI_U16 u16DTCntPcntx10;
+ MI_U16 u16BTYx10;
+ MI_U16 u16DTYx10;
+} MI_ISP_AE_STRATEGY_EX_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_RGBIR_AE_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16MaxYWithIR;
+ MI_U16 u16MinISPGainCompRatio;
+} MI_ISP_AE_RGBIR_AE_TYPE_t;
+
+typedef struct MI_ISP_AE_HDR_TYPE_s
+{
+ MI_ISP_AE_INTP_LUT_TYPE_t stAeHdrRatio;
+} MI_ISP_AE_HDR_TYPE_t;
+
+typedef struct MI_ISP_AE_STABILIZER_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16DiffThd;
+ MI_U16 u16Percent;
+} MI_ISP_AE_STABILIZER_TYPE_t;
+
+/************************************* AE - Define the structure declaration - END *************************************/
+
+/************************************* AWB - Define the structure declaration - START *************************************/
+
+#define MI_ISP_AWB_LV_CT_TBL_NUM (18)
+#define MI_ISP_AWB_CT_TBL_NUM (10)
+#define MI_ISP_AWB_WEIGHT_WIN_NUM (81)
+
+typedef struct MI_ISP_AWB_QUERY_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsStable;
+ MI_U16 u16Rgain;
+ MI_U16 u16Grgain;
+ MI_U16 u16Gbgain;
+ MI_U16 u16Bgain;
+ MI_U16 u16ColorTemp;
+ MI_U8 u8WPInd;
+ MI_ISP_BOOL_e bMultiLSDetected;
+ MI_U8 u8FirstLSInd;
+ MI_U8 u8SecondLSInd;
+} MI_ISP_AWB_QUERY_INFO_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_MODE_AUTO,
+ SS_AWB_MODE_MANUAL,
+ SS_AWB_MODE_CTMANUAL,
+ SS_AWB_MODE_MAX
+} MI_ISP_AWB_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_ALG_GRAYWORLD = 0,
+ SS_AWB_ALG_NORMAL = 1,
+ SS_AWB_ALG_BALANCE = 2,
+ SS_AWB_ALG_FOCUS = 3,
+ SS_AWB_ALG_MAX = 0xffffffff
+} MI_ISP_AWB_ALG_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_ADV_DEFAULT = 0,
+ SS_AWB_ADV_ADVANCE = 1,
+ SS_AWB_ADV_MAX = 0xffffffff
+} MI_ISP_AWB_ADV_TYPE_e;
+
+typedef struct CT_LIMIT_PARAM_s
+{
+ MI_U16 u16MaxRgain; //RW, Maximum RGain, Range: [0, 8191]
+ MI_U16 u16MinRgain; //RW, Miniimum RGain, Range: [0, 8191]
+ MI_U16 u16MaxBgain; //RW, Maximum BGain, Range: [0, 8191]
+ MI_U16 u16MinBgain; //RW, Miniimum BGain, Range: [0, 8191]
+} CT_LIMIT_PARAM_t;
+
+typedef struct CT_WEIGHT_PARAM_s
+{
+ MI_U16 u16Weight[MI_ISP_AWB_CT_TBL_NUM]; //RW, Light CT Weight, Range: [1, 255]
+} CT_WEIGHT_PARAM_t;
+
+typedef struct CT_RATIO_PARAM_s
+{
+ MI_U16 u16Ratio[MI_ISP_AWB_CT_TBL_NUM]; //RW, CT Prefer Ratio, Range: [1, 255]
+} CT_RATIO_PARAM_t;
+
+typedef struct AWB_ATTR_PARAM_s
+{
+ MI_U8 u8Speed; //RW, AWB converging speed, Range: [0x1, 0x64]
+ MI_U8 u8ConvInThd; //RW, AWB converging threshold, Range:[0, 255], Recommended: [32]
+ MI_U8 u8ConvOutThd; //RW, AWB converging threshold, Range:[0, 255], Recommended: [64]
+ MI_ISP_AWB_ALG_TYPE_e eAlgType; //RW, AWB 0:GrayWorld, 1:Normal, 2:Balance 3,Focus
+ MI_ISP_AWB_ADV_TYPE_e eAdvType; //RW, AWB advance mode type
+ MI_U8 u8RGStrength; //RW, AWB adjust RG ratio, Range:[0, 255]
+ MI_U8 u8BGStrength; //RW, AWB adjust BG ratio, Range:[0, 255]
+ CT_LIMIT_PARAM_t stCTLimit; //RW, AWB limitation when envirnoment ct is out of boundary
+ CT_WEIGHT_PARAM_t stLvWeight[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB Lv Ct Weight, Range: [0, 255]
+ CT_RATIO_PARAM_t stPreferRRatio[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB prefer R gain, Range: [0, 255]
+ CT_RATIO_PARAM_t stPreferBRatio[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB prefer B gain, Range: [0, 255]
+ MI_U16 u16WpWeight[MI_ISP_AWB_CT_TBL_NUM];
+ MI_U32 u32WeightWin[MI_ISP_AWB_WEIGHT_WIN_NUM]; //RW, AWB region gain, Range: [0, 16]
+} AWB_ATTR_PARAM_t;
+
+typedef struct MWB_ATTR_PARAM_s
+{
+ MI_U16 u16Rgain; //RW, Multiplier for R color channel, Range: [0, 0x2000]
+ MI_U16 u16Grgain; //RW, Multiplier for Gr color channel, Range: [0, 0x2000]
+ MI_U16 u16Gbgain; //RW, Multiplier for Gb color channel, Range: [0, 0x2000]
+ MI_U16 u16Bgain; //RW, Multiplier for B color channel, Range: [0, 0x2000]
+} MWB_ATTR_PARAM_t;
+
+typedef struct MI_ISP_AWB_ATTR_TYPE_s
+{
+ MI_ISP_SM_STATE_TYPE_e eState;
+ MI_ISP_AWB_MODE_TYPE_e eOpType;
+ MWB_ATTR_PARAM_t stManualParaAPI;
+ AWB_ATTR_PARAM_t stAutoParaAPI;
+} MI_ISP_AWB_ATTR_TYPE_t;
+
+typedef struct AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_s
+{
+ MI_U16 u16WhiteRgain; //RW, RGain of white Point Location , Range: [256, 4095]
+ MI_U16 u16WhiteBgain; //RW, RGain of white Point Location , Range: [256, 4095]
+ MI_U8 u8AreaSize; //RW, Light Area Size , Range: [1, 32]
+ MI_ISP_BOOL_e bExclude; //RW, Include or exclude Uaer light Area, 0: include, 1:exclude
+} AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_t;
+
+typedef struct MI_ISP_AWB_ATTR_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bExtraLightEn;
+ AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_t stLightInfo[4];
+} MI_ISP_AWB_ATTR_EX_TYPE_t;
+
+typedef struct MI_ISP_AWB_MULTILS_LS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U8 u8Sensitive;
+ MI_U8 u8CaliStrength;
+ MI_U16 u16CcmForLow[9];
+ MI_U16 u16CcmForHigh[9];
+} MI_ISP_AWB_MULTILS_LS_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_WEIGHT_TYPE_s
+{
+ MI_U16 u16LvIndex;
+ CT_WEIGHT_PARAM_t stParaAPI;
+} MI_ISP_AWB_CT_WEIGHT_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_CALI_TYPE_s
+{
+ MI_U16 u16StartIdx; //RW, Light area start index, Range: [0, u2EndIdx]
+ MI_U16 u16EndIdx; //RW, Light area end index, Range: [u2StartIdx, 9]
+ MI_U16 u16CtParams[40]; //RW, Color temperature of calibration paramters , Range: [1, 1000]
+} MI_ISP_AWB_CT_CALI_TYPE_t;
+
+typedef struct MI_ISP_AWB_CUR_CT_CALI_TYPE_s
+{
+ MI_U16 u16CtParams[40]; //RW, Color temperature of calibration paramters , Range: [1, 1000]
+} MI_ISP_AWB_CUR_CT_CALI_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_STATISTICS_TYPE_s
+{
+ MI_U16 u16Width; //RW, Effective range
+ MI_U16 u16Height; //RW, Effective range
+ MI_U16 u16StatisX[5760]; //RW, Color Temperature Curve Domain Statistics X, max is 64x90
+ MI_U16 u16StatisY[5760]; //RW, Color Temperature Curve Domain Statistics Y, max is 64x90
+} MI_ISP_AWB_CT_STATISTICS_TYPE_t;
+
+typedef struct MI_ISP_AWB_HW_STATISTICS_TYPE_s
+{
+ MI_U8 u8AwbBuffer[34560]; // 128 * 90 * 3
+} MI_ISP_AWB_HW_STATISTICS_TYPE_t;
+
+typedef struct MI_ISP_AWB_CTMWB_PARAM_s
+{
+ MI_U32 u32CT;
+} MI_ISP_AWB_CTMWB_PARAM_t;
+
+/************************************* AWB - Define the structure declaration - END *************************************/
+
+#endif //_MI_ISP_3A_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_api_id.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_api_id.h
new file mode 100644
index 00000000..b4c3a257
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_api_id.h
@@ -0,0 +1,296 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp_api_id.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _TUNINGSERVER_API_ID_H_
+#define _TUNINGSERVER_API_ID_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#define ID_API_COMMON_BASE (0x0000)
+#define ID_API_COMMON_END (0x0FFF)
+
+#if 0
+#define ID_API_ISP_BASE (0x1000)
+#define ID_API_ISP_END (0x1FFF)
+
+#define ID_API_CALIBRATION_20_BASE (0x2000)
+#define ID_API_CALIBRATION_20_END (0x22FF)
+
+#define ID_API_MAINTOOL_BASE (0x2300)
+#define ID_API_MAINTOOL_END (0x25FF)
+
+#define ID_API_PLUGIN_BASE (0x2600)
+#define ID_API_PLUGIN_END (0x28FF)
+#else
+#define ID_API_ISP_IQ_BASE (0x1000)
+#define ID_API_ISP_IQ_END (0x13FF)
+
+#define ID_API_ISP_AE_BASE (0x1400)
+#define ID_API_ISP_AE_END (0x17FF)
+
+#define ID_API_ISP_AWB_BASE (0x1800)
+#define ID_API_ISP_AWB_END (0x1BFF)
+
+#define ID_API_ISP_AF_BASE (0x1C00)
+#define ID_API_ISP_AF_END (0x1FFF)
+
+#define ID_API_ISP_OTHER_BASE (0x2000)
+#define ID_API_ISP_OTHER_END (0x23FF)
+
+#define ID_API_CALIBRATION_20_BASE (0x2400)
+#define ID_API_CALIBRATION_20_END (0x27FF)
+
+#define ID_API_MAINTOOL_BASE (0x2800)
+#define ID_API_MAINTOOL_END (0x2BFF)
+
+#define ID_API_PLUGIN_BASE (0x2C00)
+#define ID_API_PLUGIN_END (0x2DFF)
+
+#define ID_API_CUS3A_BASE (0x2E00)
+#define ID_API_CUS3A_END (0x2FFF)
+
+#define ID_API_DEBUG_LEVEL_BASE (0x2FFF)
+#define ID_API_DEBUG_LEVEL_END (0x3100)
+
+#define ID_API_RESERVED_BASE (0x3101)
+#define ID_API_RESERVED_END (0x3FFF)
+
+#endif
+
+#define ID_CHIP_I1 (0x6d65031B)
+#define ID_CHIP_I3 (0x6d65031C)
+#define ID_CHIP_I2 (0x6d65031D)
+#define ID_CHIP_I5 (0x6d65031E)
+#define ID_CHIP_I6 (0x6d650320)
+#define ID_CHIP_I6E (0x6d650321)
+#define ID_CHIP_I6B0 (0x6d650322)
+#define ID_CHIP_M5 (0x6d65031F)
+
+//================================================================
+// ID Defined : Common API
+//================================================================
+#define ID_API_COMMON_I2C_ACCESS ( ID_API_COMMON_BASE + 32 ) //SET_API_ID_MI_ISP_WriteI2C
+//#define ID_API_COMMON_QuerySensorInfo ( ID_API_COMMON_BASE + 33 ) //GET_API_ID_MI_ISP_QuerySensorInfo
+#define ID_API_COMMON_MIRROR ( ID_API_COMMON_BASE + 34 )
+#define ID_API_COMMON_ROTATE ( ID_API_COMMON_BASE + 35 )
+#define ID_API_COMMON_SENSOR_ID ( ID_API_COMMON_BASE + 36 )
+
+#define ID_API_COMMON_FileID ( ID_API_COMMON_BASE + 100 ) //I1 or I3 or I2 or I5 ...
+#define ID_API_COMMON_CHANNEL_ID ( ID_API_COMMON_BASE + 101 )
+#define ID_API_COMMON_ISPROOT ( ID_API_COMMON_BASE + 102 )
+
+//================================================================
+// ID Defined : ISP API
+//================================================================
+#define ID_API_ISP_IQ_VERSION_INFO ( ID_API_ISP_IQ_BASE + 1 ) // 1. 4097
+#define ID_API_ISP_IQ_PARAM_INIT_STATUS ( ID_API_ISP_IQ_BASE + 2 ) // 2. 4098
+#define ID_API_ISP_IQ_FAST_MODE ( ID_API_ISP_IQ_BASE + 3 ) // 3. 4099
+#define ID_API_ISP_IQ_COLORTOGRAY ( ID_API_ISP_IQ_BASE + 4 ) // 4. 4100
+#define ID_API_ISP_IQ_CONTRAST ( ID_API_ISP_IQ_BASE + 5 ) // 5. 4101
+#define ID_API_ISP_IQ_BRIGHTNESS ( ID_API_ISP_IQ_BASE + 6 ) // 6. 4102
+#define ID_API_ISP_IQ_LIGHTNESS ( ID_API_ISP_IQ_BASE + 7 ) // 7. 4103
+#define ID_API_ISP_IQ_RGBGAMMA ( ID_API_ISP_IQ_BASE + 8 ) // 8. 4104
+#define ID_API_ISP_IQ_YUVGAMMA ( ID_API_ISP_IQ_BASE + 9 ) // 9. 4105
+#define ID_API_ISP_IQ_SATURATION ( ID_API_ISP_IQ_BASE + 10 ) // 10. 4106
+#define ID_API_ISP_IQ_DEFOG ( ID_API_ISP_IQ_BASE + 11 ) // 11. 4107
+#define ID_API_ISP_IQ_CCM ( ID_API_ISP_IQ_BASE + 12 ) // 12. 4108
+#define ID_API_ISP_IQ_ANTI_FALSE_COLOR ( ID_API_ISP_IQ_BASE + 13 ) // 13. 4109
+#define ID_API_ISP_IQ_NR3D ( ID_API_ISP_IQ_BASE + 14 ) // 14. 4110
+#define ID_API_ISP_IQ_NR2D_DESPIKE ( ID_API_ISP_IQ_BASE + 15 ) // 15. 4111
+#define ID_API_ISP_IQ_NR2D_LUMA ( ID_API_ISP_IQ_BASE + 16 ) // 16. 4112
+#define ID_API_ISP_IQ_NR2D_CHROMA ( ID_API_ISP_IQ_BASE + 17 ) // 17. 4113
+#define ID_API_ISP_IQ_SHARPNESS ( ID_API_ISP_IQ_BASE + 18 ) // 18. 4114
+#define ID_API_ISP_IQ_CROSSTALK ( ID_API_ISP_IQ_BASE + 19 ) // 19. 4115
+#define ID_API_ISP_IQ_BLACK_LEVEL ( ID_API_ISP_IQ_BASE + 20 ) // 20. 4116
+#define ID_API_ISP_IQ_BLACK_LEVEL_P1 ( ID_API_ISP_IQ_BASE + 21 ) // 21. 4117
+#define ID_API_ISP_IQ_WDR ( ID_API_ISP_IQ_BASE + 22 ) // 22. 4118
+#define ID_API_ISP_IQ_DEFECT_PIXEL ( ID_API_ISP_IQ_BASE + 23 ) // 23. 4119
+#define ID_API_ISP_IQ_HSV ( ID_API_ISP_IQ_BASE + 24 ) // 24. 4120
+#define ID_API_ISP_IQ_RGBIR ( ID_API_ISP_IQ_BASE + 25 ) // 25. 4121
+#define ID_API_ISP_IQ_FPN ( ID_API_ISP_IQ_BASE + 26 ) // 26. 4122
+#define ID_API_ISP_IQ_PFC ( ID_API_ISP_IQ_BASE + 27 ) // 27. 4123
+#define ID_API_ISP_IQ_DM ( ID_API_ISP_IQ_BASE + 28 ) // 28. 4124
+#define ID_API_ISP_IQ_COLOR_TRANSFORM ( ID_API_ISP_IQ_BASE + 29 ) // 29. 4125
+#define ID_API_ISP_IQ_HDR ( ID_API_ISP_IQ_BASE + 30 ) // 30. 4126
+#define ID_API_ISP_IQ_EFFECT ( ID_API_ISP_IQ_BASE + 31 ) // 31. 4127
+#define ID_API_ISP_IQ_SYS_MCNR_MEMORY ( ID_API_ISP_IQ_BASE + 32 ) // 32. 4128
+#define ID_API_ISP_IQ_LSC ( ID_API_ISP_IQ_BASE + 33 ) // 33. 4129
+#define ID_API_ISP_IQ_PARAM_MODE ( ID_API_ISP_IQ_BASE + 34 ) // 34. 4130
+#define ID_API_ISP_IQ_LinearityLUT ( ID_API_ISP_IQ_BASE + 35 ) // 35. 4131 //Get Gamma data for CCM calibration
+#define ID_API_ISP_IQ_OBCCALIB ( ID_API_ISP_IQ_BASE + 36 ) // 36. 4132 //Get OB data for Gamma or CCM calibration
+#define ID_API_ISP_IQ_NR3D_P1 ( ID_API_ISP_IQ_BASE + 37 ) // 37. 4133
+#define ID_API_ISP_IQ_WDR_FC_CURVE ( ID_API_ISP_IQ_BASE + 38 ) // 38. 4134
+#define ID_API_ISP_IQ_R2Y ( ID_API_ISP_IQ_BASE + 39 ) // 39. 4135
+#define ID_API_ISP_IQ_ALSC ( ID_API_ISP_IQ_BASE + 40 ) // 40. 4136
+#define ID_API_ISP_IQ_LSC_CTRL ( ID_API_ISP_IQ_BASE + 41 ) // 41. 4137
+#define ID_API_ISP_IQ_ALSC_CTRL ( ID_API_ISP_IQ_BASE + 42 ) // 42. 4138
+#define ID_API_ISP_IQ_DEFECT_PIXEL_CLUSTER ( ID_API_ISP_IQ_BASE + 43 ) // 43. 4139
+#define ID_API_ISP_IQ_QUERY_CCM_INFO ( ID_API_ISP_IQ_BASE + 44 ) // 44. 4140
+#define ID_API_ISP_IQ_NR2D_LUMA_ADV ( ID_API_ISP_IQ_BASE + 45 ) // 45. 4141
+#define ID_API_ISP_IQ_NR2D_CHROMA_ADV ( ID_API_ISP_IQ_BASE + 46 ) // 46. 4142
+#define ID_API_ISP_IQ_PFC_EX ( ID_API_ISP_IQ_BASE + 47 ) // 47. 4143
+#define ID_API_ISP_IQ_HDR_EX ( ID_API_ISP_IQ_BASE + 48 ) // 48. 4144
+#define ID_API_ISP_IQ_SHP_EX ( ID_API_ISP_IQ_BASE + 49 ) // 49. 4145
+#define ID_API_ISP_IQ_NR_3D_EX ( ID_API_ISP_IQ_BASE + 50 ) // 50. 4146
+#define ID_API_ISP_IQ_DUMMY ( ID_API_ISP_IQ_BASE + 51 ) // 51. 4147
+#define ID_API_ISP_IQ_DUMMY_EX ( ID_API_ISP_IQ_BASE + 52 ) // 52. 4148
+#define ID_API_ISP_IQ_WDR_FC_CURVE_FULL ( ID_API_ISP_IQ_BASE + 53 ) // 53. 4149
+#define ID_API_ISP_IQ_ADAPTIVE_GAMMA ( ID_API_ISP_IQ_BASE + 54 ) // 54. 4150
+
+#define ID_API_ISP_AE_HIST_WEIGHT_Y ( ID_API_ISP_AE_BASE + 1 ) // 1. 5121
+#define ID_API_ISP_AE_QUERY_EXPOSURE_INFO ( ID_API_ISP_AE_BASE + 2 ) // 2. 5122
+#define ID_API_ISP_AE_EV_COMP ( ID_API_ISP_AE_BASE + 3 ) // 3. 5123
+#define ID_API_ISP_AE_EXPO_MODE ( ID_API_ISP_AE_BASE + 4 ) // 4. 5124
+#define ID_API_ISP_AE_MANUAL_EXPO ( ID_API_ISP_AE_BASE + 5 ) // 5. 5125
+#define ID_API_ISP_AE_STATE ( ID_API_ISP_AE_BASE + 6 ) // 6. 5126
+#define ID_API_ISP_AE_TARGET ( ID_API_ISP_AE_BASE + 7 ) // 7. 5127
+#define ID_API_ISP_AE_CONVERGE ( ID_API_ISP_AE_BASE + 8 ) // 8. 5128
+#define ID_API_ISP_AE_EXPOSURE_LIMIT ( ID_API_ISP_AE_BASE + 9 ) // 9. 5129
+#define ID_API_ISP_AE_PLAIN_LONG_EXPO_TABLE ( ID_API_ISP_AE_BASE + 10 ) // 10. 5130
+#define ID_API_ISP_AE_PLAIN_SHORT_EXPO_TABLE ( ID_API_ISP_AE_BASE + 11 ) // 11. 5131
+#define ID_API_ISP_AE_WINDOW_WGT_MODE ( ID_API_ISP_AE_BASE + 12 ) // 12. 5132
+#define ID_API_ISP_AE_WINDOW_WGT ( ID_API_ISP_AE_BASE + 13 ) // 13. 5133
+#define ID_API_ISP_AE_FLICKER ( ID_API_ISP_AE_BASE + 14 ) // 14. 5134
+#define ID_API_ISP_AE_STRATEGY ( ID_API_ISP_AE_BASE + 15 ) // 15. 5135
+#define ID_API_ISP_AE_RGBIRExposureAttr ( ID_API_ISP_AE_BASE + 16 ) // 16. 5136
+#define ID_API_ISP_AE_HDR ( ID_API_ISP_AE_BASE + 17 ) // 17. 5137
+#define ID_API_ISP_AE_MANUAL_EXPO_SHORT ( ID_API_ISP_AE_BASE + 18 ) // 18. 5138
+#define ID_API_ISP_AE_FLICKER_EX ( ID_API_ISP_AE_BASE + 19 ) // 19. 5139
+#define ID_API_ISP_AE_QUERY_FLICKER_EX_INFO ( ID_API_ISP_AE_BASE + 20 ) // 20. 5140
+#define ID_API_ISP_AE_STABILIZER ( ID_API_ISP_AE_BASE + 21 ) // 21. 5141
+#define ID_API_ISP_AE_STRATEGY_EX ( ID_API_ISP_AE_BASE + 22 ) // 22. 5142
+#define ID_API_ISP_AE_QUERY_STRATEGY_EX_INFO ( ID_API_ISP_AE_BASE + 23 ) // 24. 5143
+
+#define ID_API_ISP_AWB_QUERY_WHITE_BALANCE_INFO ( ID_API_ISP_AWB_BASE + 1 ) // 1. 6145
+#define ID_API_ISP_AWB_ATTR ( ID_API_ISP_AWB_BASE + 2 ) // 2. 6146
+#define ID_API_ISP_AWB_ATTR_EX ( ID_API_ISP_AWB_BASE + 3 ) // 3. 6147
+#define ID_API_ISP_AWB_MULTI_LS_ATTR ( ID_API_ISP_AWB_BASE + 4 ) // 4. 6148
+#define ID_API_ISP_AWB_CT_WEIGHT ( ID_API_ISP_AWB_BASE + 5 ) // 5. 6149
+#define ID_API_ISP_AWB_CTMWB ( ID_API_ISP_AWB_BASE + 6 ) // 5. 6150
+
+//#define ID_API_ISP_AF_QUERY_FOCUS_INFO ( ID_API_ISP_AF_BASE + 1 ) // 1. 7169
+//#define ID_API_ISP_AF_WINDOW ( ID_API_ISP_AF_BASE + 2 ) // 2. 7170
+//#define ID_API_ISP_AF_FILTER ( ID_API_ISP_AF_BASE + 3 ) // 3. 7171
+
+
+//#define ID_API_VENC_RcParamEx ( ID_API_ISP_OTHER_BASE + 1 ) // 1. 8193 --> old ( ID_API_ISP_BASE + 35 ) //35. 4131
+//#define ID_API_VI_SensorFrameRate ( ID_API_ISP_OTHER_BASE + 2 ) // 2. 8194 --> old ( ID_API_ISP_BASE + 36 ) //36. 4132
+//#define ID_API_VENC_Resolution ( ID_API_ISP_OTHER_BASE + 3 ) // 3. 8195 --> old ( ID_API_ISP_BASE + 37 ) //37. 4133
+
+//================================================================
+// ID Defined : Calibration 2.0 API
+//================================================================
+#define ID_API_CALIBRATION_20_CaliBVAV ( ID_API_CALIBRATION_20_BASE + 1) // 1. 9217 //SET_API_ID_CALIBRATION_CaliBVAV = 61,
+#define ID_API_CALIBRATION_20_Apply ( ID_API_CALIBRATION_20_BASE + 2) // 2. 9218 //SET_API_ID_CALIBRATION_ApplyBVAV = 62,
+#define ID_API_CALIBRATION_20_CaliData ( ID_API_CALIBRATION_20_BASE + 3) // 3. 9219 //SET_API_ID_CALIBRATION_SetCaliData = 63,
+#define ID_API_CALIBRATION_20_CaliPath ( ID_API_CALIBRATION_20_BASE + 4) // 4. 9220 //SET_API_ID_CALIBRATION_SetCaliPath = 64,
+#define ID_API_CALIBRATION_20_CaliDBPath ( ID_API_CALIBRATION_20_BASE + 5) // 5. 9221 //SET_API_ID_CALIBRATION_SetCaliDBPath
+#define ID_API_CALIBRATION_20_CaliInfo ( ID_API_CALIBRATION_20_BASE + 6) // 6. 9222 //GET_API_ID_CALIBRATION_GetCaliInfo
+
+#define ID_API_CALIBRATION_20_CaliAWB ( ID_API_CALIBRATION_20_BASE + 7) // 7. 9223
+#define ID_API_CALIBRATION_20_CaliOB ( ID_API_CALIBRATION_20_BASE + 8) // 8. 9224
+#define ID_API_CALIBRATION_20_CaliMinGain ( ID_API_CALIBRATION_20_BASE + 9) // 9. 9225
+#define ID_API_CALIBRATION_20_CaliShutterLinearity ( ID_API_CALIBRATION_20_BASE + 10) // 10. 9226
+#define ID_API_CALIBRATION_20_CaliGainLinearity ( ID_API_CALIBRATION_20_BASE + 11) // 11 9227
+#define ID_API_CALIBRATION_20_CaliDPC ( ID_API_CALIBRATION_20_BASE + 12) // 12. 9228
+#define ID_API_CALIBRATION_20_CaliALSC ( ID_API_CALIBRATION_20_BASE + 13) // 13. 9229
+#define ID_API_CALIBRATION_20_CaliFPN ( ID_API_CALIBRATION_20_BASE + 14) // 14. 9230
+
+#define ID_API_CALIBRATION_30_ApplyAWB ( ID_API_CALIBRATION_20_BASE + 15) // 15. 9231
+#define ID_API_CALIBRATION_30_ApplyOBC ( ID_API_CALIBRATION_20_BASE + 16) // 16. 9232
+#define ID_API_CALIBRATION_30_ApplyMinGain ( ID_API_CALIBRATION_20_BASE + 17) // 17. 9233
+#define ID_API_CALIBRATION_30_ApplyShutterLinearity ( ID_API_CALIBRATION_20_BASE + 18) // 18. 9234
+#define ID_API_CALIBRATION_30_ApplyGainLinearity ( ID_API_CALIBRATION_20_BASE + 19) // 19 9235
+#define ID_API_CALIBRATION_30_ApplySDC ( ID_API_CALIBRATION_20_BASE + 20) // 20. 9236
+#define ID_API_CALIBRATION_30_ApplyALSC ( ID_API_CALIBRATION_20_BASE + 21) // 21. 9237
+#define ID_API_CALIBRATION_30_ApplyFPN ( ID_API_CALIBRATION_20_BASE + 22) // 22. 9238
+#define ID_API_CALIBRATION_30_ApplyLSC ( ID_API_CALIBRATION_20_BASE + 23) // 21. 9239
+
+//================================================================
+// ID Defined : MainTool API
+//================================================================
+#define ID_API_MAINTOOL_QUERY_SENSOR_INFO ( ID_API_MAINTOOL_BASE + 1 ) // 1. 10241
+#define ID_API_MAINTOOL_IQ_INDEX ( ID_API_MAINTOOL_BASE + 2 ) // 2. 10242
+#define ID_API_MAINTOOL_BYPASS ( ID_API_MAINTOOL_BASE + 3 ) // 3. 10243
+
+//================================================================
+// ID Defined : Plugin API
+//================================================================
+#define ID_API_PLUGIN_I2C_ACCESS ( ID_API_PLUGIN_BASE + 1 ) // 1. 11265 //SET_API_ID_MI_ISP_WriteI2C
+#define ID_API_PLUGIN_WBCT ( ID_API_PLUGIN_BASE + 3 ) // 3. 11267 //SetWBCTCaliAttr
+#define ID_API_PLUGIN_AWBCTStats ( ID_API_PLUGIN_BASE + 4 ) // 4. 11268
+#define ID_API_PLUGIN_AWBHWStats ( ID_API_PLUGIN_BASE + 5 ) // 5. 11269
+#define ID_API_PLUGIN_CUR_WBCT ( ID_API_PLUGIN_BASE + 6 ) // 6. 11270 //GetCurCTCaliAttr
+
+//================================================================
+// ID Defined : Cus3A API
+//================================================================
+#define ID_API_CUS_AE_HW_AVG_STATS ( ID_API_CUS3A_BASE + 1 ) // 1. 11777
+#define ID_API_CUS_AE_HW_HISTO_0_STATS ( ID_API_CUS3A_BASE + 2 ) // 2. 11778
+#define ID_API_CUS_AE_HW_HISTO_1_STATS ( ID_API_CUS3A_BASE + 3 ) // 3. 11779
+#define ID_API_CUS_AE_GET_INIT_STATUS ( ID_API_CUS3A_BASE + 4 ) // 4. 11780
+#define ID_API_CUS_AE_GET_CUR_STATUS ( ID_API_CUS3A_BASE + 5 ) // 5. 11781
+#define ID_API_CUS_AE_SET_PARAM ( ID_API_CUS3A_BASE + 6 ) // 6. 11782
+#define ID_API_CUS_AWB_HW_AVG_STATS ( ID_API_CUS3A_BASE + 7 ) // 7. 11783
+#define ID_API_CUS_3A_ENABLE ( ID_API_CUS3A_BASE + 8 ) // 8. 11784
+#define ID_API_CUS_AWB_GET_CUR_STATUS ( ID_API_CUS3A_BASE + 9 ) // 9. 11785
+#define ID_API_CUS_AWB_SET_PARAM ( ID_API_CUS3A_BASE + 10) //10. 11786
+#define ID_API_CUS_AE_WINDOW_BLOCK_NUMBER ( ID_API_CUS3A_BASE + 11 )//11. 11787
+#define ID_API_CUS_AWB_SAMPLING ( ID_API_CUS3A_BASE + 12 )//12. 11788
+#define ID_API_CUS_AF_STATS ( ID_API_CUS3A_BASE + 13 )//13. 11789
+#define ID_API_CUS_AF_WINDOW ( ID_API_CUS3A_BASE + 14 )//14. 11790
+#define ID_API_CUS_AF_FILTER ( ID_API_CUS3A_BASE + 15 )//15. 11791
+#define ID_API_CUS_AF_FILTER_SQUARE ( ID_API_CUS3A_BASE + 16 )//16. 11792
+#define ID_API_CUS_AF_MODE ( ID_API_CUS3A_BASE + 17 )//17. 11793
+#define ID_API_CUS_AE_HISTOGRAM_WINDOW ( ID_API_CUS3A_BASE + 18 )//18. 11794
+#define ID_API_CUS_GET_IMAGE_RESOLUTION ( ID_API_CUS3A_BASE + 19 )//19. 11795
+#define ID_API_CUS_ENABLE_ISP_OUT_IMAGE ( ID_API_CUS3A_BASE + 20 )//20. 11796
+#define ID_API_CUS_GET_ISP_OUT_IMAGE_COUNT ( ID_API_CUS3A_BASE + 21 )//21. 11797
+#define ID_API_CUS_CAPTURE_HDR_RAW_IMAGE ( ID_API_CUS3A_BASE + 22 )//22. 11798
+#define ID_API_CUS_FRAME_META_INFO ( ID_API_CUS3A_BASE + 23 )//23. 11799
+#define ID_API_CUS_I2C_ACCESS ( ID_API_CUS3A_BASE + 24 )//24. 11800
+#define ID_API_CUS_AWB_HW_AVG_STATS_SHORT ( ID_API_CUS3A_BASE + 25 ) // 25. 11801
+#define ID_API_CUS_CAPTURE_RAW_IMAGE ( ID_API_CUS3A_BASE + 26 )//26. 11802
+#define ID_API_CUS_CUSTOMER_AE_CTRL ( ID_API_CUS3A_BASE + 27 )//27. 11803 , Customer defined AE control only
+#define ID_API_CUS_CUSTOMER_AWB_CTRL ( ID_API_CUS3A_BASE + 28 )//28. 11804 , Customer defined AWB control only
+#define ID_API_CUS_CUSTOMER_AF_CTRL ( ID_API_CUS3A_BASE + 29 )//29. 11805 , Customer defined AF control only
+#define ID_API_CUS_AE_HW_RGBIR_HISTO_STATS ( ID_API_CUS3A_BASE + 30 ) // 30. 11806
+#ifdef ENABLE_EARLY_AE_DONE
+#define ID_API_CUS_AE_DONE_RATIO ( ID_API_CUS3A_BASE + 27 )//27. 11803
+#endif
+//================================================================
+// ID Defined : Debug Level API
+//================================================================
+#define ID_API_ISP_DeBugLevel_AE ( ID_API_DEBUG_LEVEL_BASE + 1 ) // 1. 12288
+#define ID_API_ISP_DeBugLevel_AWB ( ID_API_DEBUG_LEVEL_BASE + 2 ) // 2. 12289
+#define ID_API_ISP_DeBugLevel_AWB_PERIOD ( ID_API_DEBUG_LEVEL_BASE + 3 ) // 3. 12290
+
+#define ID_API_REGISTER_API_SET_CB ( ID_API_RESERVED_BASE + 1) //1. register API_SET callback
+#define ID_API_REGISTER_API_GET_CB ( ID_API_RESERVED_BASE + 2) //2. register API_GET callback
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_TUNINGSERVER_API_ID_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_datatype.h
new file mode 100644
index 00000000..28952f69
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_datatype.h
@@ -0,0 +1,373 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp_datatype.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_DATATYPE_H_
+#define _MI_ISP_DATATYPE_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "mi_common.h"
+#include "mi_sys_datatype.h"
+#include "mi_isp_3a_datatype.h"
+#include "mi_isp_iq_datatype.h"
+
+/************************************* AF - Define the structure declaration - START *************************************/
+
+/************************************* AF - Define the structure declaration - END *************************************/
+
+/************************** Cus3A ***********************/
+
+typedef struct
+{
+ MI_U8 uAvgR;
+ MI_U8 uAvgG;
+ MI_U8 uAvgB;
+ MI_U8 uAvgY;
+} MI_ISP_AE_AVGS;
+
+typedef struct
+{
+ MI_U32 nBlkX;
+ MI_U32 nBlkY;
+ MI_ISP_AE_AVGS nAvg[128*90];
+}MI_ISP_AE_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U8 uAvgR;
+ MI_U8 uAvgG;
+ MI_U8 uAvgB;
+} MI_ISP_AWB_AVGS;
+
+typedef struct
+{
+ MI_U32 nBlkX;
+ MI_U32 nBlkY;
+ MI_ISP_AWB_AVGS nAvg[128*90];
+} MI_ISP_AWB_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U16 nHisto[128];
+} MI_ISP_HISTO_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U16 nHisto[256];
+} MI_ISP_RGBIR_HISTO_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_BOOL bAE;
+ MI_BOOL bAWB;
+ MI_BOOL bAF;
+}Cus3AEnable_t;
+
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ char sensor_id[32]; /**< sensor module id*/
+ MI_U32 shutter; /**< shutter Shutter in ns*/
+ MI_U32 shutter_step; /**< shutter Shutter step ns*/
+ MI_U32 shutter_min; /**< shutter Shutter min us*/
+ MI_U32 shutter_max; /**< shutter Shutter max us*/
+ MI_U32 sensor_gain; /**< sensor_gain Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gain_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gain_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ MI_U32 isp_gain; /**< isp_gain Isp digital gain , 1X = 1024 */
+ MI_U32 isp_gain_max; /**< isp_gain Maximum Isp digital gain , 1X = 1024 */
+ MI_U32 FNx10; /**< F number * 10*/
+ MI_U32 fps; /**< initial frame per second*/
+ MI_U32 shutterHDRShort_step; /**< shutter Shutter step ns*/
+ MI_U32 shutterHDRShort_min; /**< shutter Shutter min us*/
+ MI_U32 shutterHDRShort_max; /**< shutter Shutter max us*/
+ MI_U32 sensor_gainHDRShort_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gainHDRShort_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ /*CUS3A v1.1*/
+ MI_U32 AvgBlkX; /**< HW statistics average block number*/
+ MI_U32 AvgBlkY; /**< HW statistics average block number*/
+}CusAEInitParam_t,CusAeInitParam_t;
+
+/*! @brief ISP report to AE, hardware statistic */
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ void *hist1; /**< HW statistic histogram 1*/
+ void *hist2; /**< HW statistic histogram 2*/
+ MI_U32 AvgBlkX; /**< HW statistics average block number*/
+ MI_U32 AvgBlkY; /**< HW statistics average block number*/
+ void * avgs; /**< HW statistics average block data*/
+ MI_U32 Shutter; /**< Current shutter in ns*/
+ MI_U32 SensorGain; /**< Current Sensor gain, 1X = 1024 */
+ MI_U32 IspGain; /**< Current ISP gain, 1X = 1024*/
+ MI_U32 ShutterHDRShort; /**< Current shutter in ns*/
+ MI_U32 SensorGainHDRShort; /**< Current Sensor gain, 1X = 1024 */
+ MI_U32 IspGainHDRShort; /**< Current ISP gain, 1X = 1024*/
+ /*CUS3A V1.1*/
+ MI_U32 PreAvgY; /**< Previous frame brightness*/
+ MI_U8 HDRCtlMode; /**< 0 = HDR off; */
+ /**< 1 = Separate shutter & Separate sensor gain settings */
+ /**< 2 = Separate shutter & Share sensor gain settings */
+ /**< 3 = Share shutter & Separate sensor gain settings */
+ MI_U32 FNx10; /**< Aperture in FNx10*/
+ MI_U32 CurFPS; /**Current sensor FPS */
+ MI_U32 PreWeightY; /**< Previous frame brightness with ROI weight*/
+} __attribute__((packed, aligned(1))) CusAEInfo_t, CusAeInput_t;
+
+/*! @brief ISP ae algorithm result*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 Change; /**< if true, apply this result to hw register*/
+ MI_U32 Shutter; /**< Shutter in ns */
+ MI_U32 SensorGain; /**< Sensor gain, 1X = 1024 */
+ MI_U32 IspGain; /**< ISP gain, 1X = 1024 */
+ MI_U32 ShutterHdrShort; /**< Shutter in ns */
+ MI_U32 SensorGainHdrShort; /**< Sensor gain, 1X = 1024 */
+ MI_U32 IspGainHdrShort; /**< ISP gain, 1X = 1024 */
+ MI_U32 u4BVx16384; /**< Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ MI_U32 AvgY; /**< frame brightness */
+ MI_U32 HdrRatio; /**< hdr ratio, 1X = 1024 */
+ /*CUS3A V1.1*/
+ MI_U32 FNx10; /**< F number * 10*/
+ MI_U32 DebandFPS; /** Target fps when running auto debanding**/
+ MI_U32 WeightY; /**< frame brightness with ROI weight*/
+}__attribute__((packed, aligned(1))) CusAEResult_t, CusAeOutput_t;
+
+/*! @brief AWB HW statistics data*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 AvgBlkX;
+ MI_U32 AvgBlkY;
+ MI_U32 CurRGain;
+ MI_U32 CurGGain;
+ MI_U32 CurBGain;
+ void *avgs; //ISP_AWB_SAMPLE
+ /*CUS3A V1.1*/
+ MI_U8 HDRMode; /**< Noramal or HDR mode*/
+ void* *pAwbStatisShort; /**< Short Shutter AWB statistic data */
+ MI_U32 u4BVx16384; /**< From AE output, Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ MI_S32 WeightY; /**< frame brightness with ROI weight*/
+}__attribute__((packed, aligned(1))) CusAWBInfo_t, CusAWBInput_t;
+
+/*! @brief AWB algorithm result*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 Change; /**< if true, apply this result to hw register*/
+ MI_U32 R_gain; /**< AWB gain for R channel*/
+ MI_U32 G_gain; /**< AWB gain for G channel*/
+ MI_U32 B_gain; /**< AWB gain for B channel*/
+ MI_U32 ColorTmp; /**< Return color temperature*/
+}CusAWBResult_t, CusAwbOutput_t;;
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ SS_AE_16x24 = 0,
+ SS_AE_32x24,
+ SS_AE_64x48,
+ SS_AE_64x45,
+ SS_AE_128x80,
+ SS_AE_128x90,
+ SS_AE_32x32
+} MS_CUST_AE_WIN_BLOCK_NUM_TYPE_e;
+
+typedef struct {
+ MI_U16 u2Stawin_x_offset;
+ MI_U16 u2Stawin_x_size;
+ MI_U16 u2Stawin_y_offset;
+ MI_U16 u2Stawin_y_size;
+ MI_U16 u2WinIdx;
+} CusAEHistWin_t;
+
+typedef struct
+{
+ MI_U32 SizeX;
+ MI_U32 SizeY;
+ MI_U32 IncRatio;
+}CusAWBSample_t;
+
+typedef struct
+{
+ MI_U8 iir_1[5*16]; //[5]: iir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 iir_2[5*16]; //[5]: iir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 luma[4*16]; //[4]: luma 32bit, use 4*u8 datatype, [16]: 16wins
+ MI_U8 fir_v[5*16]; //[5]: fir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 fir_h[5*16]; //[5]: fir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 ysat[3*16]; //[3]: ysat 22bit, use 3*u8 datatype, [16]: 16wins
+} AF_STATS_PARAM_t;
+
+typedef struct
+{
+ AF_STATS_PARAM_t stParaAPI[16];
+} CusAFStats_t;
+
+typedef struct AF_WINDOW_PARAM_s
+{
+ MI_U32 u32StartX; /*range : 0~1023*/
+ MI_U32 u32StartY; /*range : 0~1023*/
+ MI_U32 u32EndX; /*range : 0~1023*/
+ MI_U32 u32EndY; /*range : 0~1023*/
+} AF_WINDOW_PARAM_t;
+
+typedef struct
+{
+ MI_U8 u8WindowIndex;
+ AF_WINDOW_PARAM_t stParaAPI;
+} CusAFWin_t;
+
+typedef struct
+{
+ MI_U16 u16IIR1_a0;
+ MI_U16 u16IIR1_a1;
+ MI_U16 u16IIR1_a2;
+ MI_U16 u16IIR1_b1;
+ MI_U16 u16IIR1_b2;
+ MI_U16 u16IIR1_1st_low_clip;
+ MI_U16 u16IIR1_1st_high_clip;
+ MI_U16 u16IIR1_2nd_low_clip;
+ MI_U16 u16IIR1_2nd_high_clip;
+ MI_U16 u16IIR2_a0;
+ MI_U16 u16IIR2_a1;
+ MI_U16 u16IIR2_a2;
+ MI_U16 u16IIR2_b1;
+ MI_U16 u16IIR2_b2;
+ MI_U16 u16IIR2_1st_low_clip;
+ MI_U16 u16IIR2_1st_high_clip;
+ MI_U16 u16IIR2_2nd_low_clip;
+ MI_U16 u16IIR2_2nd_high_clip;
+} CusAFFilter_t;
+
+typedef struct
+{
+ MI_BOOL bSobelYSatEn;
+ MI_U16 u16SobelYThd;
+
+ MI_BOOL bIIRSquareAccEn;
+ MI_BOOL bSobelSquareAccEn;
+
+ MI_U16 u16IIR1Thd;
+ MI_U16 u16IIR2Thd;
+ MI_U16 u16SobelHThd;
+ MI_U16 u16SobelVThd;
+ MI_U8 u8AFTblX[12];
+ MI_U16 u16AFTblY[13];
+} CusAFFilterSq_t;
+
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ AF_ROI_MODE_NORMAL,
+ AF_ROI_MODE_MATRIX
+} ISP_AF_ROI_MODE_e;
+
+typedef struct
+{
+ ISP_AF_ROI_MODE_e mode;
+ MI_U32 u32_vertical_block_number;
+} CusAFRoiMode_t;
+
+/* Raw store control */
+typedef enum
+{
+ eRawStoreNode_P0HEAD = 0, /* Control by VIF, Do not use */
+ eRawStoreNode_P1HEAD = 1, /* Control by VIF, Do not use */
+ eRawStoreNode_P0TAIL = 2,
+ eRawStoreNode_P1TAIL = 3,
+ eRawStoreNode_ISPOUT = 4,
+ eRawStoreNode_VDOS = 5,
+ eRawStoreNode_ISPOUT_BEFORE_YEE = 6,
+ eRawStoreNode_RGBIR_IR_ONLY = 7
+}CameraRawStoreNode_e;
+
+typedef struct
+{
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32Node;
+ MI_U32 u32PixelDepth;
+} CusImageResolution_t;
+
+typedef struct
+{
+ MI_U32 u32enable;
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32physical_address;
+ MI_U32 u32Node;
+} CusISPOutImage_t;
+
+typedef struct
+{
+ MI_U32 u32enable;
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32physical_address;
+ MI_U32 u32Node;
+ MI_U32 u32PixelDepth;
+} CusHdrRawImage_t;
+
+typedef struct
+{
+ MI_U64 u64Pts; /** frame PTS */
+ MI_U32 u32Shutter; /**< Shutter in us */
+ MI_U32 u32SensorGain; /**< Sensor gain, 1X = 1024 */
+ MI_U32 u32ColorTmp; /**< Return color temperature*/
+} IspFrameMetaInfo_t;
+
+typedef struct
+{
+ MI_U32 u32SlaveAddr; //sensor slave address
+ MI_U32 u32RegLen; //sensor register length , 1 or 2 bytes
+ MI_U32 u32DataLen; //sensor register data length, 1 or 2 bytes
+ MI_U32 u32I2cSpeed; //i2c speed , 100/200/300/400 KHz
+ MI_U32 u32Reg; //sensor register address
+ MI_U32 u32Data; //sensor register data
+}CusSensorI2cParam_t;
+
+/***************************** end of Cus3A ****************************/
+
+// COMMON API
+typedef struct MI_ISP_API_CHANNEL_ID_TYPE_s
+{
+ MI_U32 u32ChannelID;
+} MI_ISP_API_CHANNEL_ID_TYPE_t;
+
+typedef struct MI_ISP_API_USERSPACE3A_ATTR_s
+{
+ MI_SYS_PixelFormat_e ePixelFmt;
+ MI_U32 eSensorBindId;
+} MI_ISP_API_USERSPACE3A_ATTR_t;
+
+typedef struct
+{
+ MI_S8 strIspRoot[64];
+} MI_ISP_ROOT_PATH_T;
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_general.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_general.h
new file mode 100644
index 00000000..abf87248
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_general.h
@@ -0,0 +1,187 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_GENERAL_H_
+#define _MI_ISP_GENERAL_H_
+
+#include "mi_syscall.h"
+#include "mi_vpe_datatype.h"
+#include "mi_common.h"
+#include "mi_isp.h"
+#include "mi_isp_datatype.h"
+
+#ifdef CAM_OS_LINUX_USER
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#ifdef LINUX_FLOW_ON_DUAL_OS
+#define DUAL_OS_RUN_ON_LINUX 1
+#define DUAL_OS_RUN_ON_RTOS 0
+#else
+#ifdef __RTOS__
+#define DUAL_OS_RUN_ON_LINUX 0
+#define DUAL_OS_RUN_ON_RTOS 1
+#else
+#define DUAL_OS_RUN_ON_LINUX 0
+#define DUAL_OS_RUN_ON_RTOS 0
+#endif
+#endif
+
+#define MI_ISP_MSG(args...) printf(args)
+#define MI_ISP_DMSG(args...) do{}while(0)
+#define MI_ISP_EMSG(args...) printf(args)
+#define MI_ISP_VMSG(args...) do{}while(0)
+
+#define MI_ISP_CALLOC calloc
+#define MI_ISP_FREE free
+
+extern MI_S32 MI_VPE_GetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+extern MI_S32 MI_VPE_SetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+
+MI_S32 _MI_ISP_SetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+MI_S32 _MI_ISP_GetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+
+#if (DUAL_OS_RUN_ON_LINUX)
+#define MI_GETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ PARAM_t *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(sizeof(PARAM_t), &pIspBuffer);\
+ memcpy(pIspBuffer, PtrData, sizeof(PARAM_t));\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, sizeof(PARAM_t));\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_GetIspApiData(&stIspApiHeader, pIspBuffer);\
+ memcpy(PtrData, pIspBuffer, sizeof(PARAM_t));\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+ return s32Ret;\
+
+#define MI_SETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ PARAM_t *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(sizeof(PARAM_t), &pIspBuffer);\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ memcpy(pIspBuffer, PtrData, sizeof(PARAM_t));\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, sizeof(PARAM_t));\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, pIspBuffer);\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+ return s32Ret;\
+
+#define MI_CALI_SETAPI(Channel, APIFuncID, PARAM_t, DataSize, PtrData)\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ char *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(DataSize, &pIspBuffer);\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = DataSize;\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ memcpy(pIspBuffer, PtrData, DataSize);\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, DataSize);\
+ stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, pIspBuffer);\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+
+#else
+#define MI_GETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ /*s32Ret = stIspApiHeader.s32Ret = MI_VPE_GetIspApiData(&stIspApiHeader, PtrData);*/\
+ s32Ret = stIspApiHeader.s32Ret = _MI_ISP_GetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader.u32Channel, stIspApiHeader.u32CtrlID, stIspApiHeader.u32DataLen, stIspApiHeader.u32HeadSize);\
+ return s32Ret;\
+
+#define MI_SETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ /*s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, PtrData);*/\
+ s32Ret = stIspApiHeader.s32Ret = _MI_ISP_SetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader.u32Channel, stIspApiHeader.u32CtrlID, stIspApiHeader.u32DataLen, stIspApiHeader.u32HeadSize);\
+ return s32Ret;\
+
+#define MI_CALI_SETAPI(Channel, APIFuncID, PARAM_t, DataSize, PtrData)\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = DataSize;\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader->u32Channel, stIspApiHeader->u32CtrlID, stIspApiHeader->u32DataLen, stIspApiHeader->u32HeadSize);\
+
+#endif
+
+#define MI_ISP_SET(APIFunc, PARAM_t) \
+ if(ApiLen != sizeof(PARAM_t)) \
+ { \
+ MI_ISP_MSG("[%s][%s] APIID:%d error param \n", __FILE__, __func__, ApiId); \
+ break; \
+ } \
+ ret = APIFunc(Channel, (PARAM_t*)pApiBuf); \
+
+#define MI_ISP_GET(APIFunc, PARAM_t) \
+ *ApiLen = sizeof(PARAM_t); \
+ ret = APIFunc(Channel, (PARAM_t*)pApiBuf); \
+
+#define MI_CALL_SETAPI(Channel, APIFunc, PARAM_t)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ PARAM_t *stParam = MI_ISP_CALLOC(1, sizeof(PARAM_t));\
+ memcpy(stParam, param_ary[0], sizeof(PARAM_t));\
+ s32Ret = APIFunc(Channel, stParam);\
+ MI_ISP_DMSG("[%s][%s] param_num = %d\n", __FILE__, __FUNCTION__, param_num);\
+ MI_ISP_FREE(stParam);\
+ return s32Ret;\
+
+#define MI_RESET_API(Channel, APIFunc, PARAM_t)\
+ PARAM_t *stParam = MI_ISP_CALLOC(1, sizeof(PARAM_t));\
+ memset(stParam, 0x00, sizeof(PARAM_t));\
+ s32Ret = APIFunc(Channel, stParam);\
+ MI_ISP_DMSG("[%s][%s] param_num = %d\n", __FILE__, __FUNCTION__, param_num);\
+ MI_ISP_FREE(stParam);\
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_GENERAL_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_iq.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_iq.h
new file mode 100644
index 00000000..9b30af20
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_iq.h
@@ -0,0 +1,271 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_IQ_H_
+#define _MI_ISP_IQ_H_
+
+#include "mi_isp_3a_datatype.h"
+#include "mi_isp_iq_datatype.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if 1
+ /************************************* IQ API START *************************************/
+ MI_S32 MI_ISP_IQ_GetVersionInfo(MI_U32 Channel, MI_ISP_IQ_VERSION_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetVersionInfo(MI_U32 Channel, MI_ISP_IQ_VERSION_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetParaInitStatus(MI_U32 Channel, MI_ISP_IQ_PARAM_INIT_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetColorToGray(MI_U32 Channel, MI_ISP_IQ_COLORTOGRAY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetColorToGray(MI_U32 Channel, MI_ISP_IQ_COLORTOGRAY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetContrast(MI_U32 Channel, MI_ISP_IQ_CONTRAST_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetContrast(MI_U32 Channel, MI_ISP_IQ_CONTRAST_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetBrightness(MI_U32 Channel, MI_ISP_IQ_BRIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetBrightness(MI_U32 Channel, MI_ISP_IQ_BRIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLightness(MI_U32 Channel, MI_ISP_IQ_LIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLightness(MI_U32 Channel, MI_ISP_IQ_LIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBGamma(MI_U32 Channel, MI_ISP_IQ_RGBGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBGamma(MI_U32 Channel, MI_ISP_IQ_RGBGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetYUVGamma(MI_U32 Channel, MI_ISP_IQ_YUVGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetYUVGamma(MI_U32 Channel, MI_ISP_IQ_YUVGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetSaturation(MI_U32 Channel, MI_ISP_IQ_SATURATION_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetSaturation(MI_U32 Channel, MI_ISP_IQ_SATURATION_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDefog(MI_U32 Channel, MI_ISP_IQ_DEFOG_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_GetDefog(MI_U32 Channel, MI_ISP_IQ_DEFOG_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_SetRGBMatrix(MI_U32 Channel, MI_ISP_IQ_RGBMATRIX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBMatrix(MI_U32 Channel, MI_ISP_IQ_RGBMATRIX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetFalseColor(MI_U32 Channel, MI_ISP_IQ_FALSECOLOR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetFalseColor(MI_U32 Channel, MI_ISP_IQ_FALSECOLOR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNR3D(MI_U32 Channel, MI_ISP_IQ_NR3D_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNR3D(MI_U32 Channel, MI_ISP_IQ_NR3D_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNR3D_P1(MI_U32 Channel, MI_ISP_IQ_NR3D_P1_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_GetNR3D_P1(MI_U32 Channel, MI_ISP_IQ_NR3D_P1_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_SetNRDeSpike(MI_U32 Channel, MI_ISP_IQ_NRDESPIKE_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRDeSpike(MI_U32 Channel, MI_ISP_IQ_NRDESPIKE_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRLuma(MI_U32 Channel, MI_ISP_IQ_NRLUMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRLuma(MI_U32 Channel, MI_ISP_IQ_NRLUMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRChroma(MI_U32 Channel, MI_ISP_IQ_NRChroma_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRChroma(MI_U32 Channel, MI_ISP_IQ_NRChroma_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetSharpness(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetSharpness(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetCrossTalk(MI_U32 Channel, MI_ISP_IQ_CROSSTALK_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetCrossTalk(MI_U32 Channel, MI_ISP_IQ_CROSSTALK_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetOBC(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetOBC(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetOBC_P1(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetOBC_P1(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDR(MI_U32 Channel, MI_ISP_IQ_WDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDR(MI_U32 Channel, MI_ISP_IQ_WDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDRCurveAdv(MI_U32 Channel, MI_ISP_IQ_WDRCurveAdv_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDRCurveAdv(MI_U32 Channel, MI_ISP_IQ_WDRCurveAdv_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDRCurveFull(MI_U32 Channel, MI_ISP_IQ_WDRCurveFull_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDRCurveFull(MI_U32 Channel, MI_ISP_IQ_WDRCurveFull_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDynamicDP(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDynamicDP(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDynamicDP_CLUSTER(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDynamicDP_CLUSTER(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetHSV(MI_U32 Channel, MI_ISP_IQ_HSV_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetHSV(MI_U32 Channel, MI_ISP_IQ_HSV_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBIR(MI_U32 Channel, MI_ISP_IQ_RGBIR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBIR(MI_U32 Channel, MI_ISP_IQ_RGBIR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetFPN(MI_U32 Channel, MI_ISP_IQ_FPN_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_GetFPN(MI_U32 Channel, MI_ISP_IQ_FPN_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_SetPFC(MI_U32 Channel, MI_ISP_IQ_PFC_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetPFC(MI_U32 Channel, MI_ISP_IQ_PFC_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetDEMOSAIC(MI_U32 Channel, MI_ISP_IQ_DEMOSAIC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDEMOSAIC(MI_U32 Channel, MI_ISP_IQ_DEMOSAIC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetR2Y(MI_U32 Channel, MI_ISP_IQ_R2Y_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetR2Y(MI_U32 Channel, MI_ISP_IQ_R2Y_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetCOLORTRANS(MI_U32 Channel, MI_ISP_IQ_COLORTRANS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetCOLORTRANS(MI_U32 Channel, MI_ISP_IQ_COLORTRANS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetHDR(MI_U32 Channel, MI_ISP_IQ_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetHDR(MI_U32 Channel, MI_ISP_IQ_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLSC(MI_U32 Channel, MI_ISP_IQ_LSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLSC(MI_U32 Channel, MI_ISP_IQ_LSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLSC_CTRL(MI_U32 Channel, MI_ISP_IQ_LSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLSC_CTRL(MI_U32 Channel, MI_ISP_IQ_LSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetALSC(MI_U32 Channel, MI_ISP_IQ_ALSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetALSC(MI_U32 Channel, MI_ISP_IQ_ALSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetALSC_CTRL(MI_U32 Channel, MI_ISP_IQ_ALSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetALSC_CTRL(MI_U32 Channel, MI_ISP_IQ_ALSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRLuma_Adv(MI_U32 Channel, MI_ISP_IQ_NRLuma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNRLuma_Adv(MI_U32 Channel, MI_ISP_IQ_NRLuma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNRChroma_Adv(MI_U32 Channel, MI_ISP_IQ_NRChroma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNRChroma_Adv(MI_U32 Channel, MI_ISP_IQ_NRChroma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetPFC_EX(MI_U32 Channel, MI_ISP_IQ_PFC_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetPFC_EX(MI_U32 Channel, MI_ISP_IQ_PFC_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetHDR_EX(MI_U32 Channel, MI_ISP_IQ_HDR_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetHDR_EX(MI_U32 Channel, MI_ISP_IQ_HDR_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetSHP_EX(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetSHP_EX(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNR3D_EX(MI_U32 Channel, MI_ISP_IQ_NR3D_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNR3D_EX(MI_U32 Channel, MI_ISP_IQ_NR3D_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetDUMMY(MI_U32 Channel, MI_ISP_IQ_DUMMY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDUMMY(MI_U32 Channel, MI_ISP_IQ_DUMMY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDUMMY_EX(MI_U32 Channel, MI_ISP_IQ_DUMMY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDUMMY_EX(MI_U32 Channel, MI_ISP_IQ_DUMMY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetIQMode(MI_U32 Channel, MI_ISP_IQ_PARAM_MODE_e *data);
+ MI_S32 MI_ISP_IQ_GetIQMode(MI_U32 Channel, MI_ISP_IQ_PARAM_MODE_e *data);
+ MI_S32 MI_ISP_IQ_GetIQind(MI_U32 Channel, MI_ISP_IQ_INDEX_e *data);
+ MI_S32 MI_ISP_IQ_SetAPIBypassMode(MI_U32 Channel, MI_ISP_API_BYPASS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetAPIBypassMode(MI_U32 Channel, MI_ISP_API_BYPASS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_QueryCCMInfo(MI_U32 Channel, MI_ISP_IQ_CCM_INFO_TYPE_t *data);
+ /************************************* IQ API END *************************************/
+
+ /************************************* AE API START *************************************/
+ MI_S32 MI_ISP_AE_GetHistoWghtY(MI_U32 Channel, MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t *data);
+ MI_S32 MI_ISP_AE_QueryExposureInfo(MI_U32 Channel, MI_ISP_AE_EXPO_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetEVComp(MI_U32 Channel, MI_ISP_AE_EV_COMP_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetEVComp(MI_U32 Channel, MI_ISP_AE_EV_COMP_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetExpoMode(MI_U32 Channel, MI_ISP_AE_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetExpoMode(MI_U32 Channel, MI_ISP_AE_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetManualExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetManualExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetManualShortExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetManualShortExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetState(MI_U32 Channel, MI_ISP_SM_STATE_TYPE_e *data); // Pause, Resume
+ MI_S32 MI_ISP_AE_GetState(MI_U32 Channel, MI_ISP_SM_STATE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetTarget(MI_U32 Channel, MI_ISP_AE_INTP_LUT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetTarget(MI_U32 Channel, MI_ISP_AE_INTP_LUT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetConverge(MI_U32 Channel, MI_ISP_AE_CONV_CONDITON_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetConverge(MI_U32 Channel, MI_ISP_AE_CONV_CONDITON_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetExposureLimit(MI_U32 Channel, MI_ISP_AE_EXPO_LIMIT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetExposureLimit(MI_U32 Channel, MI_ISP_AE_EXPO_LIMIT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetPlainLongExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetPlainLongExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetPlainShortExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetPlainShortExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetWinWgtType(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetWinWgtType(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetWinWgt(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetWinWgt(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetFlicker(MI_U32 Channel, MI_ISP_AE_FLICKER_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetFlicker(MI_U32 Channel, MI_ISP_AE_FLICKER_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetFlickerEX(MI_U32 Channel, MI_ISP_AE_FLICKER_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetFlickerEX(MI_U32 Channel, MI_ISP_AE_FLICKER_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStrategy(MI_U32 Channel, MI_ISP_AE_STRATEGY_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStrategy(MI_U32 Channel, MI_ISP_AE_STRATEGY_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStrategyEX(MI_U32 Channel, MI_ISP_AE_STRATEGY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStrategyEX(MI_U32 Channel, MI_ISP_AE_STRATEGY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetRGBIRAE(MI_U32 Channel, MI_ISP_AE_RGBIR_AE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetRGBIRAE(MI_U32 Channel, MI_ISP_AE_RGBIR_AE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetHDR(MI_U32 Channel, MI_ISP_AE_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetHDR(MI_U32 Channel, MI_ISP_AE_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStabilizer(MI_U32 Channel, MI_ISP_AE_STABILIZER_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStabilizer(MI_U32 Channel, MI_ISP_AE_STABILIZER_TYPE_t *data);
+ /************************************* AE API END *************************************/
+
+ /************************************* AWB API START *************************************/
+ MI_S32 MI_ISP_AWB_QueryInfo(MI_U32 Channel, MI_ISP_AWB_QUERY_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetAttr(MI_U32 Channel, MI_ISP_AWB_ATTR_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetAttr(MI_U32 Channel, MI_ISP_AWB_ATTR_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetAttrEx(MI_U32 Channel, MI_ISP_AWB_ATTR_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetAttrEx(MI_U32 Channel, MI_ISP_AWB_ATTR_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetMultiLSAttr(MI_U32 Channel, MI_ISP_AWB_MULTILS_LS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetMultiLSAttr(MI_U32 Channel, MI_ISP_AWB_MULTILS_LS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetCTWeight(MI_U32 Channel, MI_ISP_AWB_CT_WEIGHT_TYPE_t *data); //Not works now, please use MI_ISP_AWB_SetAttr to set LvWeight indstead.
+ MI_S32 MI_ISP_AWB_GetCTWeight(MI_U32 Channel, MI_ISP_AWB_CT_WEIGHT_TYPE_t *data); //Not works now, please use MI_ISP_AWB_GetAttr to set LvWeight indstead.
+
+ MI_S32 MI_ISP_AWB_SetCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCurCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CUR_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCTStats(MI_U32 Channel, MI_ISP_AWB_CT_STATISTICS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetHWStats(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetCTMwbAttr(MI_U32 Channel, MI_ISP_AWB_CTMWB_PARAM_t *data);
+ MI_S32 MI_ISP_AWB_GetCTMwbAttr(MI_U32 Channel, MI_ISP_AWB_CTMWB_PARAM_t *data);
+
+ /************************************* AWB API END *************************************/
+
+ /************************************* AF API START *************************************/
+ /************************************* AF API END *************************************/
+
+ MI_S32 MI_ISP_ALGO_SET_ALL(int Channel, MI_U16 ApiId, MI_U32 ApiLen, MI_U8* pApiBuf);
+ MI_S32 MI_ISP_ALGO_GET_ALL(int Channel, MI_U16 ApiId, MI_U32* ApiLen, MI_U8* pApiBuf);
+
+#endif
+
+#if 1
+
+typedef struct MI_ISP_EXCUTE_CMD_ARRAY_s
+{
+ MI_U32 u32CmdType;
+ MI_U16 u16APIID;
+ MI_S32 (*callback)(MI_U32 Channel, MI_U8 *param_ary[], MI_U8 param_num);
+} MI_ISP_EXCUTE_CMD_ARRAY_t;
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ MI_ISP_CAMERA_CMD_SET = 0,
+ MI_ISP_CAMERA_CMD_GET,
+ MI_ISP_CAMERA_CMD_SET_MODE ,
+ MI_ISP_CAMERA_CMD_GET_MODE,
+ MI_ISP_CAMERA_CMD_GET_PIC,
+ MI_ISP_CAMERA_CMD_SET_API,
+ MI_ISP_CAMERA_CMD_GET_API,
+ MI_ISP_CAMERA_CMD_UPLOAD_FILE, /* client upload file to server */
+ MI_ISP_CAMERA_CMD_DOWNLOAD_FILE, /* client download file from server*/
+} MI_ISP_CAMERA_EXT_CMD_TYPE_e;
+
+typedef struct MI_ISP_CMD_HEADER_s
+{
+ MI_ISP_CAMERA_EXT_CMD_TYPE_e CmdType;
+ MI_S32 CmdLen;
+} MI_ISP_CMD_HEADER_t;
+
+typedef struct MI_ISP_API_PARAM_s
+{
+ MI_U32 u32MagicKey;
+ MI_ISP_CMD_HEADER_t sCmdheader;
+ MI_U16 u16APIID;
+ MI_U16 u16ParamNum;
+} MI_ISP_API_PARAM_t;
+
+typedef struct MI_ISP_API_BIN_FILE_s
+{
+ MI_U32 u32FileID;
+ MI_U32 u32ISPVer;
+ MI_U32 u32DataLen;
+ MI_U32 u32Checksum;
+ MI_U32 u32MagicKey;
+ MI_U32 u32Reserved[3];
+} MI_ISP_API_BIN_FILE_t;
+
+typedef struct MI_ISP_API_CALI_FILE_s
+{
+ MI_U32 u32CaliVer;
+ MI_U32 u32DataSize;
+ MI_U32 u32Checksum;
+ MI_U32 u32Reserved[2];
+} MI_ISP_API_CALI_FILE_t;
+
+ MI_S32 MI_ISP_ALGO_API_DisableAllApi(MI_U32 Channel);
+ MI_S32 MI_ISP_ALGO_API_CmdLoadBinFile(MI_U32 Channel, MI_U8 *bindata_buf, MI_U32 user_key);
+ MI_S32 MI_ISP_ALGO_API_CmdLoadCaliData(MI_U32 Channel, MI_U8 *bindata_buf, MI_U32 BIN_BUF_MAX_LEN, MI_ISP_CALI_ITEM_e eCaliItem);
+
+#endif
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_IQ_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_iq_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_iq_datatype.h
new file mode 100644
index 00000000..3d1e46d6
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/mi_isp_iq_datatype.h
@@ -0,0 +1,1051 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+ * iq_apiset.h
+ *
+ * Created on: 2016/8/16
+ * Author: Elsa-cf.Lin
+ */
+
+#ifndef _MI_ISP_IQ_DATATYPE_H_
+#define _MI_ISP_IQ_DATATYPE_H_
+
+#include "mi_isp_3a_datatype.h"
+
+//put here temporarily, should add mi_isp_cali_datatype.h?
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ SS_CALI_ITEM_AWB = 0,
+ SS_CALI_ITEM_OBC = 1,
+ SS_CALI_ITEM_SDC = 2,
+ SS_CALI_ITEM_ALSC = 3,
+ SS_CALI_ITEM_LSC = 4,
+ SS_CALI_ITEM_MAX,
+} MI_ISP_CALI_ITEM_e;
+
+/************************************* IQ - Define the structure declaration - START *************************************/
+
+typedef struct
+{
+ MI_U16 u16NumOfPoints;
+ MI_S32 s32Y[16];
+ MI_S32 s32X[16];
+} MI_INTP_LUT_IQ;
+
+#if 1 //API20 struct
+
+#define MI_ISP_AUTO_NUM (16)
+#define ALSC_TBL_MAX 255
+#define ENABLE_CCM_COEFF_SUM_INFO 0
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ API20_AUTO = 0, //[00]
+ //API2.0
+ API20_FPN, //[01]
+ API20_CCM, //[02]
+ API20_SAT, //[03]
+ API20_OBC, //[04]
+ API20_OBC_P1, //[05]
+ API20_FCOLOR, //[06]
+ API20_CR, //[07]
+ API20_NR_DeSpike, //[08]
+ API20_SHP, //[09]
+ API20_NR_3D, //[10]
+ API20_BRI, //[11]
+ API20_LIG, //[12]
+ API20_CST, //[13]
+ API20_GMA, //[14]
+ API20_CTG, //[15]
+ API20_NR_NLM, //[16]
+ API20_DEFOG, //[17]
+ API20_DRC, //[18]
+ API20_DPC, //[19]
+ API20_HSV, //[20]
+ API20_WDR_LOC, //[21]
+ API20_RGBIR, //[22]
+ API20_YUVGMA, //[23]
+ API20_HDR16to12, //[24]
+ API20_COLORTRANS, //[25]
+ API20_HDR, //[26]
+ API20_EFFECT, //[27]
+ API20_PFC, //[28]
+ API20_SIIR, //[29]
+ API20_DM, //[30]
+ API20_NR_3D_P1, //[31]
+ API20_WDRCurveAdv, //[32]
+ API20_MXNR, //[33]
+ API20_R2Y, //[34]
+ API20_LSC, //[35]
+ API20_LSC_CTRL, //[36]
+ API20_ALSC, //[37]
+ API20_ALSC_CTRL, //[38]
+ API20_DPC_CLUSTER, //[39]
+ API20_PFC_EX, //[40]
+ API20_HDR_EX, //[41]
+ API20_SHP_EX, //[42]
+ API20_NR_3D_EX, //[43]
+ API20_GNR, //[44]
+ API20_DUMMY, //[45]
+ API20_DUMMY_EX, //[46]
+ API20_WDRCurveFull, //[47]
+ API20_ADAPTIVE_GMA, //[48]
+ API20_MAX, //for para reset
+} MI_ISP_API_ID_e;
+
+typedef struct MI_ISP_IQ_COLORTOGRAY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+} MI_ISP_IQ_COLORTOGRAY_TYPE_t;
+
+typedef struct LEVEL_BASE_PARAM_s
+{
+ MI_U32 u32Lev; //0 ~ 100
+} LEVEL_BASE_PARAM_t;
+
+typedef struct LIGHTNESS_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} LIGHTNESS_MANUAL_ATTR_t;
+
+typedef struct LIGHTNESS_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} LIGHTNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_LIGHTNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ LIGHTNESS_AUTO_ATTR_t stAuto;
+ LIGHTNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_LIGHTNESS_TYPE_t;
+
+typedef struct CONTRAST_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} CONTRAST_MANUAL_ATTR_t;
+
+typedef struct CONTRAST_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} CONTRAST_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_CONTRAST_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ CONTRAST_AUTO_ATTR_t stAuto;
+ CONTRAST_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_CONTRAST_TYPE_t;
+
+typedef struct BRIGHTNESS_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} BRIGHTNESS_MANUAL_ATTR_t;
+
+typedef struct BRIGHTNESS_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} BRIGHTNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_BRIGHTNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ BRIGHTNESS_AUTO_ATTR_t stAuto;
+ BRIGHTNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_BRIGHTNESS_TYPE_t;
+
+
+typedef struct RGBGAMMA_PARAM_s
+{
+ MI_U16 u16LutR[256]; //0 ~ 4095
+ MI_U16 u16LutG[256]; //0 ~ 4095
+ MI_U16 u16LutB[256]; //0 ~ 4095
+} RGBGAMMA_PARAM_t;
+
+typedef struct RGBGAMMA_MANUAL_ATTR_s
+{
+ RGBGAMMA_PARAM_t stParaAPI;
+} RGBGAMMA_MANUAL_ATTR_t;
+
+typedef struct RGBGAMMA_AUTO_ATTR_s
+{
+ RGBGAMMA_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBGAMMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBGAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBGAMMA_AUTO_ATTR_t stAuto;
+ RGBGAMMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBGAMMA_TYPE_t;
+
+typedef struct YUVGAMMA_PAMAR_s
+{
+ MI_U16 u16LutY[256]; //0 ~ 1023
+ MI_U16 u16LutU[128]; //0 ~ 511
+ MI_U16 u16LutV[128]; //0 ~ 511
+} YUVGAMMA_PAMAR_t;
+
+typedef struct YUVGAMMA_MANUAL_ATTR_s
+{
+ YUVGAMMA_PAMAR_t stParaAPI;
+} YUVGAMMA_MANUAL_ATTR_t;
+
+typedef struct YUVGAMMA_AUTO_ATTR_s
+{
+ YUVGAMMA_PAMAR_t stParaAPI[MI_ISP_AUTO_NUM];
+} YUVGAMMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_YUVGAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ YUVGAMMA_AUTO_ATTR_t stAuto;
+ YUVGAMMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_YUVGAMMA_TYPE_t;
+
+typedef struct SATURATION_PARAM_s
+{
+ MI_U8 u8SatAllStr; //0 ~ 127 (32 = 1X)
+ MI_U8 u8SatByYSFTAdv[5]; //0 ~ 8
+ MI_U8 u8SatByYLUTAdv[6]; //0 ~ 128
+ MI_U8 u8SatBySSFTAdv[5]; //0 ~ 8
+ MI_U8 u8SatBySLUTAdv[6]; //0 ~ 128
+ MI_U8 u8SatCoring;
+} SATURATION_PARAM_t;
+
+typedef struct SATURATION_MANUAL_ATTR_s
+{
+ SATURATION_PARAM_t stParaAPI;
+} SATURATION_MANUAL_ATTR_t;
+
+typedef struct SATURATION_AUTO_ATTR_s
+{
+ SATURATION_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} SATURATION_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_SATURATION_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ SATURATION_AUTO_ATTR_t stAuto;
+ SATURATION_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SATURATION_TYPE_t;
+
+typedef struct MI_ISP_IQ_DEFOG_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_DEFOG_TYPE_t;
+
+typedef struct RGBMATRIX_PARAM_s
+{
+ MI_U16 u16CCTthr;
+#if ENABLE_CCM_COEFF_SUM_INFO
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+#else
+ MI_U16 u16CCM[9]; //0 ~ 8191(1024 = 1X)
+#endif
+ MI_U8 u8CCMSat; //0 ~ 100 0:Unit matrix, 100:User matrix
+} RGBMATRIX_PARAM_t;
+
+typedef struct RGBMATRIX_MANUAL_ATTR_s
+{
+#if ENABLE_CCM_COEFF_SUM_INFO
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+#else
+ MI_U16 u16CCM[9]; //0 ~ 8191(1024 = 1X)
+#endif
+ MI_U8 u8CCMSat; //0 ~ 100 0:Unit matrix, 100:User matrix
+} RGBMATRIX_MANUAL_ATTR_t;
+
+typedef struct RGBMATRIX_AUTO_ATTR_s
+{
+ MI_ISP_BOOL_e bISOActEn; //0 ~ 1
+ RGBMATRIX_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBMATRIX_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBMATRIX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBMATRIX_AUTO_ATTR_t stAuto;
+ RGBMATRIX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBMATRIX_TYPE_t;
+
+typedef struct MI_ISP_IQ_CCM_INFO_TYPE_s
+{
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+ MI_U16 u16CCT;
+} MI_ISP_IQ_CCM_INFO_TYPE_t;
+
+typedef struct FALSECOLOR_PARAM_s
+{
+ MI_U8 u8FreqThrd; //0~255 default:140
+ MI_U8 u8EdgeScoreThrd; //0~255 default:31
+ MI_U8 u8ChromaThrdOfStrengthMax; //0~127 default:10
+ MI_U8 u8ChromaThrdOfStrengthMid; //0~127 default:40
+ MI_U8 u8ChromaThrdOfStrengthMin; //0~127 default:80
+ MI_U8 u8StrengthMid; //0~7 default:7
+ MI_U8 u8StrengthMin; //0~7 default:7
+} FALSECOLOR_PARAM_t;
+
+typedef struct FALSECOLOR_MANUAL_ATTR_s
+{
+ FALSECOLOR_PARAM_t stParaAPI;
+} FALSECOLOR_MANUAL_ATTR_t;
+
+typedef struct FALSECOLOR_AUTO_ATTR_s
+{
+ FALSECOLOR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} FALSECOLOR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_FALSECOLOR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ FALSECOLOR_AUTO_ATTR_t stAuto;
+ FALSECOLOR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_FALSECOLOR_TYPE_t;
+
+typedef struct NR3D_PARAM_s
+{
+ //TF
+ MI_U16 u16MdThd; //0~2048
+ MI_U16 u16MdGain; //0~2048
+ MI_U8 u8TfStr; //0~64
+ MI_U8 u8TfStrEx; //0~64
+ MI_U8 u8MdThdByY[16]; //0~255
+ MI_U8 u8MdGainByY[16]; //0~255
+ MI_U8 u8M2SLut[16]; //0~31
+ MI_U8 u8TfLut[16]; //0~63
+
+ //Y SF (BNR)
+ MI_U8 u8YSfStr; //0~31
+ MI_U8 u8YSfBlendLut[16]; //0~16
+} NR3D_PARAM_t;
+
+typedef struct NR3D_MANUAL_ATTR_s
+{
+ NR3D_PARAM_t stParaAPI;
+} NR3D_MANUAL_ATTR_t;
+
+typedef struct NR3D_AUTO_ATTR_s
+{
+ NR3D_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NR3D_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NR3D_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NR3D_AUTO_ATTR_t stAuto;
+ NR3D_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NR3D_TYPE_t;
+
+typedef struct MI_ISP_IQ_NR3D_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NR3D_EX_TYPE_t;
+
+typedef struct MI_ISP_IQ_NR3D_P1_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NR3D_P1_TYPE_t;
+
+typedef struct NRDESPIKE_PARAM_s
+{
+ MI_U8 u8BlendRatio; //0 ~ 15
+ MI_U8 u8StrengthCenterNeighbor; //0 ~ 5
+ MI_U8 u8StrengthMeanStd; //0 ~ 5
+ MI_U8 u8StrengthCornerCross; //0 ~ 5
+ MI_U8 u8DiffGainMeanStd; //0 ~ 31
+ MI_U16 u16DiffGainCenterNeighbor; //0 ~ 255
+ MI_U16 u16DiffThdCornerCross; //0 ~ 255
+} NRDESPIKE_PARAM_t;
+
+typedef struct NRDESPIKE_MANUAL_ATTR_s
+{
+ NRDESPIKE_PARAM_t stParaAPI;
+} NRDESPIKE_MANUAL_ATTR_t;
+
+typedef struct NRDESPIKE_AUTO_ATTR_s
+{
+ NRDESPIKE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRDESPIKE_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRDESPIKE_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRDESPIKE_AUTO_ATTR_t stAuto;
+ NRDESPIKE_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRDESPIKE_TYPE_t;
+
+typedef struct NRLUMA_PARAM_s
+{
+ MI_ISP_BOOL_e bLumaAdjEn;
+ MI_U8 u8LumaX[9];
+ MI_U16 u16LumaStrByY[10];
+ MI_U8 u8Wei[20];
+} NRLUMA_PARAM_t;
+
+typedef struct NRLUMA_MANUAL_ATTR_s
+{
+ NRLUMA_PARAM_t stParaAPI;
+} NRLUMA_MANUAL_ATTR_t;
+
+typedef struct NRLUMA_AUTO_ATTR_s
+{
+ NRLUMA_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRLUMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRLUMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRLUMA_AUTO_ATTR_t stAuto;
+ NRLUMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRLUMA_TYPE_t;
+
+typedef struct MI_ISP_IQ_NRLuma_Adv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NRLuma_Adv_TYPE_t;
+
+typedef struct NRChroma_PARAM_s
+{
+ MI_U8 u8MatchRatio; //0 ~ 127
+ MI_U16 u16UvTh; //0 ~ 1023
+ MI_U16 u16StrengthByCEdge[6]; //0 ~ 1023
+} NRChroma_PARAM_t;
+
+typedef struct NRChroma_MANUAL_ATTR_s
+{
+ NRChroma_PARAM_t stParaAPI;
+} NRChroma_MANUAL_ATTR_t;
+
+typedef struct NRChroma_AUTO_ATTR_s
+{
+ NRChroma_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRChroma_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRChroma_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRChroma_AUTO_ATTR_t stAuto;
+ NRChroma_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRChroma_TYPE_t;
+
+typedef struct MI_ISP_IQ_NRChroma_Adv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NRChroma_Adv_TYPE_t;
+
+typedef struct SHARPNESS_LOCAL_PARAM_s
+{
+ MI_U8 u8OverShootGain; //0 ~ 255, def: 128
+ MI_U8 u8UnderShootGain; //0 ~ 255, def: 128
+ MI_U8 u8CorLUT[6]; //0 ~ 255, def: 0
+ MI_U8 u8SclLUT[6]; //0 ~ 255, def: 0
+} SHARPNESS_LOCAL_PARAM_t;
+
+typedef struct SHARPNESS_PARAM_s
+{
+ SHARPNESS_LOCAL_PARAM_t stEdgeCtrl;
+ SHARPNESS_LOCAL_PARAM_t stTextureCtrl;
+ MI_U8 u8EdgeKillLUT[6]; //0 ~ 255, def: 0
+ MI_U8 u8CornerReduce; //0 ~ 32, def: 32
+ MI_ISP_BOOL_e bDirEn; //0 ~ 1, def: 1
+ MI_U16 u16SharpnessUD; //0 ~ 1023
+ MI_U16 u16SharpnessD; //0 ~ 1023
+ MI_U16 u16DetailTh; //0 ~ 4095
+ MI_U8 u8DetailByY[6]; //0 ~ 255
+ MI_U16 u16OverShootLimit; //0 ~ 1023
+ MI_U16 u16UnderShootLimit; //0 ~ 1023
+} SHARPNESS_PARAM_t;
+
+typedef struct SHARPNESS_MANUAL_ATTR_s
+{
+ SHARPNESS_PARAM_t stParaAPI;
+} SHARPNESS_MANUAL_ATTR_t;
+
+typedef struct SHARPNESS_AUTO_ATTR_s
+{
+ SHARPNESS_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} SHARPNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_SHARPNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ SHARPNESS_AUTO_ATTR_t stAuto;
+ SHARPNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SHARPNESS_TYPE_t;
+
+typedef struct MI_ISP_IQ_SHARPNESS_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_SHARPNESS_EX_TYPE_t;
+
+typedef struct CROSSTALK_PARAM_s
+{
+ MI_U8 u8StrengthV2; //0 ~ 31
+ MI_U16 u16ThresholdV2; //0 ~ 255
+ MI_U16 u16ThresholdOffsetV2; //0 ~ 4095
+} CROSSTALK_PARAM_t;
+
+typedef struct CROSSTALK_MANUAL_ATTR_s
+{
+ CROSSTALK_PARAM_t stParaAPI;
+} CROSSTALK_MANUAL_ATTR_t;
+
+typedef struct CROSSTALK_AUTO_ATTR_s
+{
+ CROSSTALK_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} CROSSTALK_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_CROSSTALK_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ CROSSTALK_AUTO_ATTR_t stAuto;
+ CROSSTALK_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_CROSSTALK_TYPE_t;
+
+typedef struct OBC_PARAM_s
+{
+ MI_U16 u16ValR; //0 ~ 255
+ MI_U16 u16ValGr; //0 ~ 255
+ MI_U16 u16ValGb; //0 ~ 255
+ MI_U16 u16ValB; //0 ~ 255
+} OBC_PARAM_t;
+
+typedef struct OBC_MANUAL_ATTR_s
+{
+ OBC_PARAM_t stParaAPI;
+} OBC_MANUAL_ATTR_t;
+
+typedef struct OBC_AUTO_ATTR_s
+{
+ OBC_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} OBC_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_OBC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ OBC_AUTO_ATTR_t stAuto;
+ OBC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_OBC_TYPE_t;
+
+typedef struct WDR_PARAM_s
+{
+ MI_U8 u8BoxNum; //1 ~ 4
+ MI_U8 u8PreEnhance; //0 ~ 6
+ MI_ISP_BOOL_e bAutoDetailEnhance; //0 ~ 1
+ MI_U8 u8ManualDetailEnhance; //0~255; default:128
+ MI_U8 u8GlobalDarkToneEnhance; //0 ~ 15
+ MI_U8 u8WDRStrByY[33]; //0 ~ 255
+ MI_U8 u8Strength; //0 ~ 255
+ MI_U8 u8DarkLimit; //0 ~ 255
+ MI_U8 u8BrightLimit; //0 ~ 255
+ MI_ISP_BOOL_e bGammaSyncEn; //0 ~ 1
+} WDR_PARAM_t;
+
+typedef struct WDR_MANUAL_ATTR_s
+{
+ WDR_PARAM_t stParaAPI;
+} WDR_MANUAL_ATTR_t;
+
+typedef struct WDR_AUTO_ATTR_s
+{
+ WDR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDR_AUTO_ATTR_t stAuto;
+ WDR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDR_TYPE_t;
+
+typedef struct WDRCurveFull_PARAM_s
+{
+ MI_U16 u16FCurve[256];
+} WDRCurveFull_PARAM_t;
+
+typedef struct WDRCurveFull_MANUAL_ATTR_s
+{
+ WDRCurveFull_PARAM_t stParaAPI;
+} WDRCurveFull_MANUAL_ATTR_t;
+
+typedef struct WDRCurveFull_AUTO_ATTR_s
+{
+ WDRCurveFull_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDRCurveFull_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDRCurveFull_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDRCurveFull_AUTO_ATTR_t stAuto;
+ WDRCurveFull_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDRCurveFull_TYPE_t;
+
+typedef struct WDRCurveAdv_PARAM_s
+{
+ MI_U16 u16Slope; //1024~16384
+ MI_U8 u8TransitionPoint0; //0~255
+ MI_U8 u8TransitionPoint1; //0~255
+ MI_U8 u8SaturatedPoint; //0~255
+ MI_U8 u8CurveModeSel; //0~5
+} WDRCurveAdv_PARAM_t;
+
+typedef struct WDRCurveAdv_MANUAL_ATTR_s
+{
+ WDRCurveAdv_PARAM_t stParaAPI;
+} WDRCurveAdv_MANUAL_ATTR_t;
+
+typedef struct WDRCurveAdv_AUTO_ATTR_s
+{
+ WDRCurveAdv_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDRCurveAdv_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDRCurveAdv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDRCurveAdv_AUTO_ATTR_t stAuto;
+ WDRCurveAdv_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDRCurveAdv_TYPE_t;
+
+typedef struct DYNAMIC_DP_PARAM_s
+{
+ MI_ISP_BOOL_e bHotPixEn; //0 ~ 1
+ MI_U16 u16HotPixCompSlpoe;
+ MI_ISP_BOOL_e bDarkPixEn; //0 ~ 1
+ MI_U16 u16DarkPixCompSlpoe;
+ MI_U16 u16DPCTH;
+ MI_ISP_BOOL_e bBlendEn;
+ MI_U16 u16DiffLut[6];
+ MI_U16 u16YLut[6];
+} DYNAMIC_DP_PARAM_t;
+
+typedef struct DYNAMIC_DP_MANUAL_ATTR_s
+{
+ DYNAMIC_DP_PARAM_t stParaAPI;
+} DYNAMIC_DP_MANUAL_ATTR_t;
+
+typedef struct DYNAMIC_DP_AUTO_ATTR_s
+{
+ DYNAMIC_DP_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} DYNAMIC_DP_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DYNAMIC_DP_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DYNAMIC_DP_AUTO_ATTR_t stAuto;
+ DYNAMIC_DP_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DYNAMIC_DP_TYPE_t;
+
+typedef struct DYNAMIC_DP_CLUSTER_ATTR_S
+{
+ MI_ISP_BOOL_e bEdgeMode;
+ MI_U16 u16NeiDeltaTh;
+ MI_U8 u8NeiSmooth;
+ MI_ISP_BOOL_e bSortEn;
+ MI_ISP_BOOL_e bSortRGGBEn[4];
+ MI_ISP_BOOL_e bSort1x3ModeEn;
+ MI_U16 u16SortLumTblL[6];
+ MI_U16 u16SortLumTblD[6];
+ MI_U16 u16SortLumTblS[6];
+} DYNAMIC_DP_CLUSTER_ATTR_S;
+
+typedef struct
+{
+ DYNAMIC_DP_CLUSTER_ATTR_S stParaAPI;
+} DYNAMIC_DP_CLUSTER_MANUAL_ATTR_S;
+
+typedef struct
+{
+ DYNAMIC_DP_CLUSTER_ATTR_S stParaAPI[MI_ISP_AUTO_NUM];
+} DYNAMIC_DP_CLUSTER_AUTO_ATTR_S;
+
+typedef struct MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DYNAMIC_DP_CLUSTER_AUTO_ATTR_S stAuto;
+ DYNAMIC_DP_CLUSTER_MANUAL_ATTR_S stManual;
+} MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t;
+
+typedef struct HSV_PARAM_s
+{
+ MI_S16 s16HueLut[24]; //-64 ~ 64
+ MI_U16 u16SatLut[24]; // 0 ~ 255 (64->1X)
+ MI_S16 s16HueLut_ForUnitCCM[24]; //-64 ~ 64
+ MI_U16 u16SatLut_ForUnitCCM[24]; // 0 ~ 255 (64->1X)
+ MI_U8 u8GlobalSat; // 0 ~ 255 (64->1x)
+} HSV_PARAM_t;
+
+typedef struct HSV_MANUAL_ATTR_s
+{
+ HSV_PARAM_t stParaAPI;
+} HSV_MANUAL_ATTR_t;
+
+typedef struct HSV_AUTO_ATTR_s
+{
+ HSV_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} HSV_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_HSV_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ HSV_AUTO_ATTR_t stAuto;
+ HSV_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HSV_TYPE_t;
+
+typedef struct RGBIR_PARAM_s
+{
+ MI_U8 u8IrPosType; //0 ~ 7, def : 0
+ MI_ISP_BOOL_e bRemovelEn; //0 ~ 1, def : 1
+ MI_U16 u16Ratio_R[6];
+ MI_U16 u16Ratio_G[6];
+ MI_U16 u16Ratio_B[6];
+} RGBIR_PARAM_t;
+
+typedef struct RGBIR_MANUAL_ATTR_s
+{
+ RGBIR_PARAM_t stParaAPI;
+} RGBIR_MANUAL_ATTR_t;
+
+typedef struct RGBIR_AUTO_ATTR_s
+{
+ RGBIR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBIR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBIR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBIR_AUTO_ATTR_t stAuto;
+ RGBIR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBIR_TYPE_t;
+
+typedef struct MI_ISP_IQ_FPN_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_FPN_TYPE_t;
+
+typedef struct MI_ISP_IQ_PFC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_PFC_TYPE_t;
+
+typedef struct MI_ISP_IQ_PFC_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_PFC_EX_TYPE_t;
+
+typedef struct DEMOSAIC_PARAM_s
+{
+ MI_U8 u8DirThrd; //0~63 def:35
+ MI_U8 u8EdgeSmoothThrdY; //0~255 def:230
+ MI_U8 u8EdgeSmoothThrdC; //0~127 def:20
+} DEMOSAIC_PARAM_t;
+
+typedef struct DEMOSAIC_MANUAL_ATTR_s
+{
+ DEMOSAIC_PARAM_t stParaAPI;
+} DEMOSAIC_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_DEMOSAIC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ DEMOSAIC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DEMOSAIC_TYPE_t;
+
+typedef struct COLORTRANS_PARAM_s
+{
+ MI_U16 u16Y_OFST; //0 ~ 2047
+ MI_U16 u16U_OFST; //0 ~ 2047
+ MI_U16 u16V_OFST; //0 ~ 2047
+ MI_U16 u16Matrix[9]; //0 ~ 1023
+} COLORTRANS_PARAM_t;
+
+typedef struct COLORTRANS_MANUAL_ATTR_s
+{
+ COLORTRANS_PARAM_t stParaAPI;
+} COLORTRANS_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_COLORTRANS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ COLORTRANS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_COLORTRANS_TYPE_t;
+
+typedef struct HDR_PARAM_s
+{
+ MI_U16 u16SensorExpRatio;
+ MI_ISP_BOOL_e bNrEn;
+ MI_ISP_BOOL_e bDynRatioEn;
+ MI_U8 u8CRefSel;
+ MI_U16 u16YwtTh1;
+ MI_U16 u16YwtTh2;
+} HDR_PARAM_t;
+
+typedef struct HDR_MANUAL_ATTR_s
+{
+ HDR_PARAM_t stParaAPI;
+} HDR_MANUAL_ATTR_t;
+
+typedef struct HDR_AUTO_ATTR_s
+{
+ HDR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} HDR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_HDR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ HDR_AUTO_ATTR_t stAuto;
+ HDR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HDR_TYPE_t;
+
+typedef struct MI_ISP_IQ_HDR_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_HDR_EX_TYPE_t;
+
+typedef struct MI_ISP_IQ_EFFECT_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_EFFECT_TYPE_t;
+
+typedef struct MI_ISP_IQ_SYS_MCNR_MEMORY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_SYS_MCNR_MEMORY_TYPE_t;
+
+typedef struct MI_ISP_IQ_LSC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8RGainTable[32*3];
+ MI_U8 u8GGainTable[32*3];
+ MI_U8 u8BGainTable[32*3];
+} MI_ISP_IQ_LSC_TYPE_t;
+
+typedef struct MI_ISP_IQ_LSC_CTRL_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8RRatioByCct[3];
+ MI_U8 u8GRatioByCct[3];
+ MI_U8 u8BRatioByCct[3];
+ MI_INTP_LUT_IQ RatioByBv;
+} MI_ISP_IQ_LSC_CTRL_TYPE_t;
+
+typedef struct MI_ISP_IQ_ALSC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U16 u16TableR[3][ALSC_TBL_MAX];
+ MI_U16 u16TableG[3][ALSC_TBL_MAX];
+ MI_U16 u16TableB[3][ALSC_TBL_MAX];
+} MI_ISP_IQ_ALSC_TYPE_t;
+
+typedef struct MI_ISP_IQ_ALSC_CTRL_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8RRatioByCct[3];
+ MI_U8 u8GRatioByCct[3];
+ MI_U8 u8BRatioByCct[3];
+ MI_INTP_LUT_IQ RatioByBv;
+} MI_ISP_IQ_ALSC_CTRL_TYPE_t;
+
+typedef struct R2Y_PARAM_s
+{
+ MI_U16 u16Matrix[9];
+ MI_U8 u8AddY16;
+} R2Y_PARAM_t;
+
+typedef struct R2Y_MANUAL_ATTR_s
+{
+ R2Y_PARAM_t stParaAPI;
+} R2Y_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_R2Y_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ R2Y_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_R2Y_TYPE_t;
+
+typedef struct DUMMY_ATTR_s
+{
+ MI_S16 s16Dummy0[256];
+ MI_S16 s16Dummy1[256];
+ MI_S16 s16Dummy2[256];
+ MI_S16 s16Dummy3;
+ MI_S16 s16Dummy4;
+} DUMMY_ATTR_t;
+
+typedef struct DUMMY_MANUAL_ATTR_s
+{
+ DUMMY_ATTR_t stParaAPI;
+} DUMMY_MANUAL_ATTR_t;
+
+typedef struct DUMMY_AUTO_ATTR_s
+{
+ DUMMY_ATTR_t stParaAPI[MI_ISP_AUTO_NUM];
+} DUMMY_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DUMMY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ DUMMY_AUTO_ATTR_t stAuto;
+ DUMMY_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DUMMY_TYPE_t;
+
+typedef struct DUMMY_EX_ATTR_s
+{
+ MI_S16 s16DummyEx0[256];
+ MI_S16 s16DummyEx1[256];
+ MI_S16 s16DummyEx2[256];
+ MI_S16 s16DummyEx3;
+ MI_S16 s16DummyEx4;
+} DUMMY_EX_ATTR_t;
+
+typedef struct
+{
+ DUMMY_EX_ATTR_t stParaAPI;
+} DUMMY_EX_MANUAL_ATTR_S;
+
+typedef struct MI_ISP_IQ_DUMMY_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ DUMMY_EX_MANUAL_ATTR_S stManual;
+} MI_ISP_IQ_DUMMY_EX_TYPE_t;
+
+#endif
+
+#if 1 // ISP IQ API
+typedef struct IQ_VERSION_INFO_PARAM_s
+{
+ MI_U32 u32Vendor;
+ MI_U32 u32Major;
+ MI_U32 u32Minor;
+} IQ_VERSION_INFO_PARAM_t;
+
+typedef struct MI_ISP_IQ_VERSION_INFO_TYPE_s
+{
+ IQ_VERSION_INFO_PARAM_t stParaAPI;
+} MI_ISP_IQ_VERSION_INFO_TYPE_t;
+
+typedef struct IQ_PARAM_INIT_INFO_PARAM_s
+{
+ MI_ISP_BOOL_e bFlag;
+} IQ_PARAM_INIT_INFO_PARAM_t;
+
+typedef struct MI_ISP_IQ_PARAM_INIT_INFO_TYPE_s
+{
+ IQ_PARAM_INIT_INFO_PARAM_t stParaAPI;
+} MI_ISP_IQ_PARAM_INIT_INFO_TYPE_t;
+
+typedef struct FAST_MODE_PARAM_s
+{
+ MI_ISP_BOOL_e bFastMode;
+} FAST_MODE_PARAM_t;
+
+typedef struct MI_ISP_IQ_FAST_MODE_TYPE_s
+{
+ FAST_MODE_PARAM_t stParaAPI;
+} MI_ISP_IQ_FAST_MODE_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_IQ_PARAM_MODE_NORMAL = 0,
+ SS_IQ_PARAM_MODE_NIGHT = 1, //Night Mode
+ SS_IQ_PARAM_MODE_MAX
+} MI_ISP_IQ_PARAM_MODE_e;
+
+typedef struct MI_ISP_IQ_GAMMA_LUT_TYPE_s
+{
+ MI_U16 u16LutR[256];
+ MI_U16 u16LutG[256];
+ MI_U16 u16LutB[256];
+} MI_ISP_IQ_GAMMA_LUT_TYPE_t;
+
+typedef struct MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16BTGamma[256];
+ MI_U16 u16DTGamma[256];
+} MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_t;
+
+typedef struct MI_ISP_IQ_OBC4Ch_TYPE_s
+{
+ MI_U16 u16OBC4Ch[4];
+} MI_ISP_IQ_OBC4Ch_TYPE_t;
+#endif
+
+#if 1 // MAINTOOL API
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_IQ_INDEX_0 = 0,
+ SS_IQ_INDEX_1,
+ SS_IQ_INDEX_2,
+ SS_IQ_INDEX_3,
+ SS_IQ_INDEX_4,
+ SS_IQ_INDEX_5,
+ SS_IQ_INDEX_6,
+ SS_IQ_INDEX_7,
+ SS_IQ_INDEX_8,
+ SS_IQ_INDEX_9,
+ SS_IQ_INDEX_10,
+ SS_IQ_INDEX_11,
+ SS_IQ_INDEX_12,
+ SS_IQ_INDEX_13,
+ SS_IQ_INDEX_14,
+ SS_IQ_INDEX_15,
+ SS_IQ_INDEX_MAX
+} MI_ISP_IQ_INDEX_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_BYPASS_OFF = 0,
+ SS_BYPASS_ON,
+ SS_BYPASS_MAX
+} MI_ISP_BYPASS_MODE_e;
+
+typedef struct MI_ISP_API_BYPASS_TYPE_s
+{
+ MI_ISP_BYPASS_MODE_e bEnable; //0 ~ 1
+ MI_ISP_API_ID_e eAPIIndex;
+} MI_ISP_API_BYPASS_TYPE_t;
+#endif
+
+
+/************************************* IQ - Define the structure declaration - END *************************************/
+
+
+#endif /* _MI_ISP_IQ_DATATYPE_H_ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp.h
new file mode 100644
index 00000000..727da047
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp.h
@@ -0,0 +1,111 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_H_
+#define _MI_ISP_H_
+//#include <pthread.h>
+
+#include "mi_common.h"
+#include "mi_isp_datatype.h"
+#include "mi_vpe_datatype.h"
+#include "mi_isp_iq.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MI_ISP_OK (0)
+#define MI_ISP_NOT_SUPPORT (1)
+#define MI_ISP_FAILURE (-1)
+#define MI_ISP_API_MAX_PARM_NUMBRE (6)
+#define MI_ISP_API_ISPMID_NOT_SUPPORT (5)
+
+ /************************************* Customer 3A API ***********************************/
+ MI_S32 MI_ISP_AE_GetAeHwAvgStats(MI_U32 Channel, MI_ISP_AE_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AWB_GetAwbHwAvgStats(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AWB_GetAwbHwAvgStatsShort(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetHisto0HwStats(MI_U32 Channel, MI_ISP_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetHisto1HwStats(MI_U32 Channel, MI_ISP_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_AE_GetRgbIrHistoHwStats(MI_U32 Channel, MI_ISP_RGBIR_HISTO_HW_STATISTICS_t *data);
+ MI_S32 MI_ISP_CUS3A_Enable(MI_U32 Channel, Cus3AEnable_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAeInitStatus(MI_U32 Channel, CusAEInitParam_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAeStatus(MI_U32 Channel, CusAEInfo_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAeParam(MI_U32 Channel, CusAEResult_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAwbStatus(MI_U32 Channel, CusAWBInfo_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAwbParam(MI_U32 Channel, CusAWBResult_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAEWindowBlockNumber(MI_U32 Channel, MS_CUST_AE_WIN_BLOCK_NUM_TYPE_e *data);
+ MI_S32 MI_ISP_CUS3A_SetAEHistogramWindow(MI_U32 Channel, CusAEHistWin_t*data);
+ MI_S32 MI_ISP_CUS3A_SetAWBSampling(MI_U32 Channel, CusAWBSample_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAECropSize(MI_U32 Channel, CusAEAWBCropSize_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAWBCropSize(MI_U32 Channel, CusAEAWBCropSize_t *data);
+
+ MI_S32 MI_ISP_CUS3A_GetAFStats(MI_U32 Channel, CusAFStats_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFWindow(MI_U32 Channel, CusAFWin_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFWindow(MI_U32 Channel, CusAFWin_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFFilter(MI_U32 Channel, CusAFFilter_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFFilter(MI_U32 Channel, CusAFFilter_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFFilterSq(MI_U32 Channel, CusAFFilterSq_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFFilterSq(MI_U32 Channel, CusAFFilterSq_t *data);
+ MI_S32 MI_ISP_CUS3A_SetAFRoiMode(MI_U32 Channel, CusAFRoiMode_t *data);
+ MI_S32 MI_ISP_CUS3A_GetAFRoiMode(MI_U32 Channel, CusAFRoiMode_t *data);
+
+ MI_S32 MI_ISP_CUS3A_GetImageResolution(MI_U32 Channel, CusImageResolution_t *data);
+ MI_S32 MI_ISP_CUS3A_EnableISPOutImage(MI_U32 Channel, CusISPOutImage_t *data);
+ MI_S32 MI_ISP_CUS3A_GetISPOutImageCount(MI_U32 Channel, MI_U32 *data);
+ MI_S32 MI_ISP_CUS3A_CaptureHdrRawImage(MI_U32 Channel, CusHdrRawImage_t *data);
+ MI_S32 MI_ISP_GetFrameMetaInfo(MI_U32 Channel, IspFrameMetaInfo_t *data);
+ MI_S32 MI_ISP_ReadSensorData(MI_U32 Channel, CusSensorI2cParam_t *data);
+ MI_S32 MI_ISP_WriteSensorData(MI_U32 Channel, CusSensorI2cParam_t *data);
+ /************************************* Customer 3A API END********************************/
+ /************************************* Debug API ***********************************/
+ MI_S32 MI_ISP_SetDebugLevel_AE(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_GetDebugLevel_AE(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_SetDebugLevel_AWB(MI_U32 Channel, MI_S32 *data);
+ MI_S32 MI_ISP_GetDebugLevel_AWB(MI_U32 Channel, MI_S32 *data);
+ /************************************* Debug API END********************************/
+
+ MI_S32 MI_ISP_SET_ALL(int Channel, MI_U16 ApiId, MI_U32 ApiLen, MI_U8* pApiBuf);
+ MI_S32 MI_ISP_GET_ALL(int Channel, MI_U16 ApiId, MI_U32* ApiLen, MI_U8* pApiBuf);
+
+ MI_S32 MI_ISP_API_CmdLoadBinFile(MI_U32 Channel, char* filepath, MI_U32 user_key);
+ MI_S32 MI_ISP_API_CmdLoadCaliData(MI_U32 Channel, MI_ISP_CALI_ITEM_e eCaliItem, char* filepath);
+
+ typedef MI_S32 (*MI_ISP_ApiAgent_fp)(MI_VPE_IspApiHeader_t *pstData, void* pData);
+
+ /*Api agent for SigmaStar user space 3A library*/
+ MI_S32 MI_ISP_RegisterIspApiAgent(MI_U32 Channel, MI_ISP_ApiAgent_fp fpApiSet, MI_ISP_ApiAgent_fp fpApiGet);
+#if !defined(DUAL_OS) && !defined(__RTOS__) //for pure linux
+ MI_S32 MI_ISP_EnableUserspace3A(MI_U32 Channel,MI_ISP_API_USERSPACE3A_ATTR_t *pAttr);
+ MI_S32 MI_ISP_DisableUserspace3A(MI_U32 Channel);
+#else //for DualOS-Linux , RTK
+ inline MI_S32 MI_ISP_EnableUserspace3A(MI_U32 Channel,MI_ISP_API_USERSPACE3A_ATTR_t *pAttr) {return 0;}
+ inline MI_S32 MI_ISP_DisableUserspace3A(MI_U32 Channel) {return 0;}
+#endif
+
+ /*Common API, get isp root path*/
+ MI_S32 MI_ISP_GetIspRoot(MI_U32 Channel, MI_ISP_ROOT_PATH_T *data);
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_3a_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_3a_datatype.h
new file mode 100644
index 00000000..0472f982
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_3a_datatype.h
@@ -0,0 +1,441 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_ISP_3A_DATATYPE_H_
+#define _MI_ISP_3A_DATATYPE_H_
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_FALSE = 0,
+ SS_TRUE = !SS_FALSE,
+ SS_BOOL_MAX
+} MI_ISP_BOOL_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_OP_TYP_AUTO = 0,
+ SS_OP_TYP_MANUAL = !SS_OP_TYP_AUTO,
+ SS_OP_TYP_MODE_MAX
+} MI_ISP_OP_TYPE_e;
+
+/************************************* AE - Define the structure declaration - START *************************************/
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_ISP_STATE_NORMAL = 0,
+ SS_ISP_STATE_PAUSE = 1,
+ SS_ISP_STATE_MAX
+} MI_ISP_SM_STATE_TYPE_e;
+
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_MODE_A, // auto
+ SS_AE_MODE_AV, // aperture priority
+ SS_AE_MODE_SV,
+ SS_AE_MODE_TV, // shutter priority
+ SS_AE_MODE_M, // manual mode
+ SS_AE_MODE_MAX
+} MI_ISP_AE_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_WEIGHT_AVERAGE = 0,
+ SS_AE_WEIGHT_CENTER,
+ SS_AE_WEIGHT_SPOT,
+ SS_AE_WEIGHT_MAX
+} MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_FLICKER_TYPE_DISABLE = 0,
+ SS_AE_FLICKER_TYPE_60HZ = 1,
+ SS_AE_FLICKER_TYPE_50HZ = 2,
+ SS_AE_FLICKER_TYPE_AUTO = 3,
+ //SS_AE_FLICKER_TYPE_DETECT_60HZ = 4,
+ //SS_AE_FLICKER_TYPE_DETECT_50HZ = 5,
+ SS_AE_FLICKER_TYPE_MAX
+} MI_ISP_AE_FLICKER_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_FLICKER_TYPE_DETECT_60HZ = 0,
+ SS_AE_FLICKER_TYPE_DETECT_50HZ = 1,
+ SS_AE_FLICKER_TYPE_DETECT_MAX
+} MI_ISP_AE_FLICKER_DETECT_TYPE_e;
+
+//typedef struct MI_ISP_AE_FLICKER_INFO_TYPE_s
+//{
+// MI_ISP_BOOL_e bIsEffective;
+// MI_ISP_AE_FLICKER_TYPE_e eFlickerType;
+// MI_U16 u16Score;
+//} MI_ISP_AE_FLICKER_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_FLICKER_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ MI_U8 u8AmpSensitivity; // 1 ~ 100
+ MI_U8 u8ScoreThd; // 1 ~ 100
+ MI_U8 uRefreshCycles; // 1 ~ 10
+ MI_U8 u8ValidTimesThd; // 1 ~ 10
+ MI_ISP_AE_FLICKER_DETECT_TYPE_e eFlickerType; // 60Hz = 0, 50Hz = 1
+} MI_ISP_AE_FLICKER_EX_TYPE_t;
+
+typedef struct MI_ISP_AE_FLICKER_EX_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsEffective;
+ MI_ISP_AE_FLICKER_DETECT_TYPE_e eFlickerType;
+ MI_U16 u16Score;
+} MI_ISP_AE_FLICKER_EX_INFO_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_BRIGHTTONE,
+ SS_AE_STRATEGY_DARKTONE,
+ SS_AE_STRATEGY_AUTO,
+ SS_AE_STRATEGY_MAX
+} MI_ISP_AE_STRATEGY_TYPE_e;
+
+typedef struct MI_ISP_AE_HIST_WEIGHT_Y_TYPE_s
+{
+ MI_U32 u32LumY;
+ MI_U32 u32AvgY;
+ MI_U32 u32Hits[128];
+} MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_VALUE_TYPE_s
+{
+ MI_U32 u32FNx10;
+ MI_U32 u32SensorGain;
+ MI_U32 u32ISPGain;
+ MI_U32 u32US;
+} MI_ISP_AE_EXPO_VALUE_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsStable;
+ MI_ISP_BOOL_e bIsReachBoundary;
+ MI_ISP_AE_EXPO_VALUE_TYPE_t stExpoValueLong;
+ MI_ISP_AE_EXPO_VALUE_TYPE_t stExpoValueShort;
+ MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t stHistWeightY;
+ MI_U32 u32LVx10;
+ MI_S32 s32BV;
+ MI_U32 u32SceneTarget;
+} MI_ISP_AE_EXPO_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_EV_COMP_TYPE_s
+{
+ MI_S32 s32EV;
+ MI_U32 u32Grad;
+} MI_ISP_AE_EV_COMP_TYPE_t;
+
+typedef struct MI_ISP_AE_INTP_LUT_TYPE_s
+{
+ MI_U16 u16NumOfPoints;
+ MI_U32 u32Y[16];
+ MI_U32 u32X[16];
+} MI_ISP_AE_INTP_LUT_TYPE_t;
+
+typedef struct CONV_SPEED_PARAM_s
+{
+ MI_U32 u32SpeedX[4];
+ MI_U32 u32SpeedY[4];
+} CONV_SPEED_PARAM_t;
+
+typedef struct CONV_THD_PARAM_s
+{
+ MI_U32 u32InThd;
+ MI_U32 u32OutThd;
+} CONV_THD_PARAM_t;
+
+typedef struct MI_ISP_AE_CONV_CONDITON_TYPE_s
+{
+ CONV_THD_PARAM_t stConvThrd;
+ CONV_SPEED_PARAM_t stConvSpeed;
+} MI_ISP_AE_CONV_CONDITON_TYPE_t;
+
+typedef struct MI_ISP_AE_EXPO_LIMIT_TYPE_s
+{
+ MI_U32 u32MinShutterUS;
+ MI_U32 u32MaxShutterUS;
+ MI_U32 u32MinFNx10;
+ MI_U32 u32MaxFNx10;
+ MI_U32 u32MinSensorGain;
+ MI_U32 u32MinISPGain;
+ MI_U32 u32MaxSensorGain;
+ MI_U32 u32MaxISPGain;
+} MI_ISP_AE_EXPO_LIMIT_TYPE_t;
+
+typedef struct EXPO_POINT_PARAM_s
+{
+ MI_U32 u32FNumx10;
+ MI_U32 u32Shutter;
+ MI_U32 u32TotalGain;
+ MI_U32 u32SensorGain;
+} EXPO_POINT_PARAM_t;
+
+typedef struct MI_ISP_AE_EXPO_TABLE_TYPE_s
+{
+ MI_U32 u32NumPoints;
+ EXPO_POINT_PARAM_t stExpoTbl[16]; // LV from High to Low
+} MI_ISP_AE_EXPO_TABLE_TYPE_t;
+
+typedef struct WIN_WEIGHT_PARAM_s
+{
+ MI_U8 u8AverageTbl[32*32];
+ MI_U8 u8CenterTbl[32*32];
+ MI_U8 u8SpotTbl[32*32];
+} WIN_WEIGHT_PARAM_t;
+
+typedef struct MI_ISP_AE_WIN_WEIGHT_TYPE_s
+{
+ MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e eTypeID;
+ WIN_WEIGHT_PARAM_t stParaAPI;
+} MI_ISP_AE_WIN_WEIGHT_TYPE_t;
+
+typedef struct MI_ISP_AE_STRATEGY_TYPE_s
+{
+ MI_ISP_AE_STRATEGY_TYPE_e eAEStrategyMode;
+ MI_U32 u32Weighting;
+ MI_ISP_AE_INTP_LUT_TYPE_t stUpperOffset;
+ MI_ISP_AE_INTP_LUT_TYPE_t stLowerOffset;
+ MI_U32 u32BrightToneStrength;
+ MI_U32 u32BrightToneSensitivity;
+ MI_U32 u32DarkToneStrength;
+ MI_U32 u32DarkToneSensitivity;
+ MI_U32 u32AutoStrength;
+ MI_U32 u32AutoSensitivity;
+} MI_ISP_AE_STRATEGY_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_EX_BRIGHTTONE,
+ SS_AE_STRATEGY_EX_DARKTONE,
+} MI_ISP_AE_STRATEGY_EX_PRIORITY_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AE_STRATEGY_EX_COUNT,
+ SS_AE_STRATEGY_EX_TARGET,
+} MI_ISP_AE_STRATEGY_EX_MODE_e;
+
+typedef struct MI_ISP_AE_STRATEGY_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_ISP_AE_STRATEGY_EX_MODE_e eMode;
+ MI_ISP_AE_STRATEGY_EX_PRIORITY_e ePriority;
+ MI_U16 u16BT_NodeNum;
+ MI_S32 u32BT_NodeBV[16];
+ MI_U32 u32BT_ThdY[16];
+ MI_U32 u32BT_Percentx10[16];
+ MI_U32 u32BT_TargetYx10[16];
+ MI_U32 u32BT_MaxOffsetDown[16];
+ MI_U16 u16DT_NodeNum;
+ MI_S32 u32DT_NodeBV[16];
+ MI_U32 u32DT_ThdY[16];
+ MI_U32 u32DT_Percentx10[16];
+ MI_U32 u32DT_TargetYx10[16];
+ MI_U32 u32DT_MaxOffsetUp[16];
+} MI_ISP_AE_STRATEGY_EX_TYPE_t;
+
+typedef struct MI_ISP_AE_STRATEGY_EX_INFO_TYPE_s
+{
+ MI_U16 u16GMBlendRatio;
+ MI_U16 u16UpperLimitTargetx10;
+ MI_U16 u16LowerLimitTargetx10;
+ MI_U16 u16BTCntPcntx10;
+ MI_U16 u16DTCntPcntx10;
+ MI_U16 u16BTYx10;
+ MI_U16 u16DTYx10;
+} MI_ISP_AE_STRATEGY_EX_INFO_TYPE_t;
+
+typedef struct MI_ISP_AE_RGBIR_AE_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16MaxYWithIR;
+ MI_U16 u16MinISPGainCompRatio;
+} MI_ISP_AE_RGBIR_AE_TYPE_t;
+
+typedef struct MI_ISP_AE_HDR_TYPE_s
+{
+ MI_ISP_AE_INTP_LUT_TYPE_t stAeHdrRatio;
+} MI_ISP_AE_HDR_TYPE_t;
+
+typedef struct MI_ISP_AE_STABILIZER_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16DiffThd;
+ MI_U16 u16Percent;
+} MI_ISP_AE_STABILIZER_TYPE_t;
+
+/************************************* AE - Define the structure declaration - END *************************************/
+
+/************************************* AWB - Define the structure declaration - START *************************************/
+
+#define MI_ISP_AWB_LV_CT_TBL_NUM (18)
+#define MI_ISP_AWB_CT_TBL_NUM (10)
+#define MI_ISP_AWB_WEIGHT_WIN_NUM (81)
+
+typedef struct MI_ISP_AWB_QUERY_INFO_TYPE_s
+{
+ MI_ISP_BOOL_e bIsStable;
+ MI_U16 u16Rgain;
+ MI_U16 u16Grgain;
+ MI_U16 u16Gbgain;
+ MI_U16 u16Bgain;
+ MI_U16 u16ColorTemp;
+ MI_U8 u8WPInd;
+ MI_ISP_BOOL_e bMultiLSDetected;
+ MI_U8 u8FirstLSInd;
+ MI_U8 u8SecondLSInd;
+} MI_ISP_AWB_QUERY_INFO_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_MODE_AUTO,
+ SS_AWB_MODE_MANUAL,
+ SS_AWB_MODE_CTMANUAL,
+ SS_AWB_MODE_MAX
+} MI_ISP_AWB_MODE_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_ALG_GRAYWORLD = 0,
+ SS_AWB_ALG_NORMAL = 1,
+ SS_AWB_ALG_BALANCE = 2,
+ SS_AWB_ALG_FOCUS = 3,
+ SS_AWB_ALG_MAX = 0xffffffff
+} MI_ISP_AWB_ALG_TYPE_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_AWB_ADV_DEFAULT = 0,
+ SS_AWB_ADV_ADVANCE = 1,
+ SS_AWB_ADV_MAX = 0xffffffff
+} MI_ISP_AWB_ADV_TYPE_e;
+
+typedef struct CT_LIMIT_PARAM_s
+{
+ MI_U16 u16MaxRgain; //RW, Maximum RGain, Range: [0, 8191]
+ MI_U16 u16MinRgain; //RW, Miniimum RGain, Range: [0, 8191]
+ MI_U16 u16MaxBgain; //RW, Maximum BGain, Range: [0, 8191]
+ MI_U16 u16MinBgain; //RW, Miniimum BGain, Range: [0, 8191]
+} CT_LIMIT_PARAM_t;
+
+typedef struct CT_WEIGHT_PARAM_s
+{
+ MI_U16 u16Weight[MI_ISP_AWB_CT_TBL_NUM]; //RW, Light CT Weight, Range: [1, 255]
+} CT_WEIGHT_PARAM_t;
+
+typedef struct CT_RATIO_PARAM_s
+{
+ MI_U16 u16Ratio[MI_ISP_AWB_CT_TBL_NUM]; //RW, CT Prefer Ratio, Range: [1, 255]
+} CT_RATIO_PARAM_t;
+
+typedef struct AWB_ATTR_PARAM_s
+{
+ MI_U8 u8Speed; //RW, AWB converging speed, Range: [0x1, 0x64]
+ MI_U8 u8ConvInThd; //RW, AWB converging threshold, Range:[0, 255], Recommended: [32]
+ MI_U8 u8ConvOutThd; //RW, AWB converging threshold, Range:[0, 255], Recommended: [64]
+ MI_ISP_AWB_ALG_TYPE_e eAlgType; //RW, AWB 0:GrayWorld, 1:Normal, 2:Balance 3,Focus
+ MI_ISP_AWB_ADV_TYPE_e eAdvType; //RW, AWB advance mode type
+ MI_U8 u8RGStrength; //RW, AWB adjust RG ratio, Range:[0, 255]
+ MI_U8 u8BGStrength; //RW, AWB adjust BG ratio, Range:[0, 255]
+ CT_LIMIT_PARAM_t stCTLimit; //RW, AWB limitation when envirnoment ct is out of boundary
+ CT_WEIGHT_PARAM_t stLvWeight[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB Lv Ct Weight, Range: [0, 255]
+ CT_RATIO_PARAM_t stPreferRRatio[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB prefer R gain, Range: [0, 255]
+ CT_RATIO_PARAM_t stPreferBRatio[MI_ISP_AWB_LV_CT_TBL_NUM]; //RW, AWB prefer B gain, Range: [0, 255]
+ MI_U16 u16WpWeight[MI_ISP_AWB_CT_TBL_NUM];
+ MI_U32 u32WeightWin[MI_ISP_AWB_WEIGHT_WIN_NUM]; //RW, AWB region gain, Range: [0, 16]
+} AWB_ATTR_PARAM_t;
+
+typedef struct MWB_ATTR_PARAM_s
+{
+ MI_U16 u16Rgain; //RW, Multiplier for R color channel, Range: [0, 0x2000]
+ MI_U16 u16Grgain; //RW, Multiplier for Gr color channel, Range: [0, 0x2000]
+ MI_U16 u16Gbgain; //RW, Multiplier for Gb color channel, Range: [0, 0x2000]
+ MI_U16 u16Bgain; //RW, Multiplier for B color channel, Range: [0, 0x2000]
+} MWB_ATTR_PARAM_t;
+
+typedef struct MI_ISP_AWB_ATTR_TYPE_s
+{
+ MI_ISP_SM_STATE_TYPE_e eState;
+ MI_ISP_AWB_MODE_TYPE_e eOpType;
+ MWB_ATTR_PARAM_t stManualParaAPI;
+ AWB_ATTR_PARAM_t stAutoParaAPI;
+} MI_ISP_AWB_ATTR_TYPE_t;
+
+typedef struct AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_s
+{
+ MI_U16 u16WhiteRgain; //RW, RGain of white Point Location , Range: [256, 4095]
+ MI_U16 u16WhiteBgain; //RW, RGain of white Point Location , Range: [256, 4095]
+ MI_U8 u8AreaSize; //RW, Light Area Size , Range: [1, 32]
+ MI_ISP_BOOL_e bExclude; //RW, Include or exclude Uaer light Area, 0: include, 1:exclude
+} AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_t;
+
+typedef struct MI_ISP_AWB_ATTR_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bExtraLightEn;
+ AWB_ATTR_EXTRA_LIGHTSOURCE_PARAM_t stLightInfo[4];
+} MI_ISP_AWB_ATTR_EX_TYPE_t;
+
+typedef struct MI_ISP_AWB_MULTILS_LS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U8 u8Sensitive;
+ MI_U8 u8CaliStrength;
+ MI_U16 u16CcmForLow[9];
+ MI_U16 u16CcmForHigh[9];
+} MI_ISP_AWB_MULTILS_LS_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_WEIGHT_TYPE_s
+{
+ MI_U16 u16LvIndex;
+ CT_WEIGHT_PARAM_t stParaAPI;
+} MI_ISP_AWB_CT_WEIGHT_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_CALI_TYPE_s
+{
+ MI_U16 u16StartIdx; //RW, Light area start index, Range: [0, u2EndIdx]
+ MI_U16 u16EndIdx; //RW, Light area end index, Range: [u2StartIdx, 9]
+ MI_U16 u16CtParams[40]; //RW, Color temperature of calibration paramters , Range: [1, 1000]
+} MI_ISP_AWB_CT_CALI_TYPE_t;
+
+typedef struct MI_ISP_AWB_CUR_CT_CALI_TYPE_s
+{
+ MI_U16 u16CtParams[40]; //RW, Color temperature of calibration paramters , Range: [1, 1000]
+} MI_ISP_AWB_CUR_CT_CALI_TYPE_t;
+
+typedef struct MI_ISP_AWB_CT_STATISTICS_TYPE_s
+{
+ MI_U16 u16Width; //RW, Effective range
+ MI_U16 u16Height; //RW, Effective range
+ MI_U16 u16StatisX[5760]; //RW, Color Temperature Curve Domain Statistics X, max is 64x90
+ MI_U16 u16StatisY[5760]; //RW, Color Temperature Curve Domain Statistics Y, max is 64x90
+} MI_ISP_AWB_CT_STATISTICS_TYPE_t;
+
+typedef struct MI_ISP_AWB_HW_STATISTICS_TYPE_s
+{
+ MI_U8 u8AwbBuffer[34560]; // 128 * 90 * 3
+} MI_ISP_AWB_HW_STATISTICS_TYPE_t;
+
+typedef struct MI_ISP_AWB_CTMWB_PARAM_s
+{
+ MI_U32 u32CT;
+} MI_ISP_AWB_CTMWB_PARAM_t;
+
+/************************************* AWB - Define the structure declaration - END *************************************/
+
+#endif //_MI_ISP_3A_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_api_id.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_api_id.h
new file mode 100644
index 00000000..c1c14c5b
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_api_id.h
@@ -0,0 +1,302 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp_api_id.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _TUNINGSERVER_API_ID_H_
+#define _TUNINGSERVER_API_ID_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#define ID_API_COMMON_BASE (0x0000)
+#define ID_API_COMMON_END (0x0FFF)
+
+#if 0
+#define ID_API_ISP_BASE (0x1000)
+#define ID_API_ISP_END (0x1FFF)
+
+#define ID_API_CALIBRATION_20_BASE (0x2000)
+#define ID_API_CALIBRATION_20_END (0x22FF)
+
+#define ID_API_MAINTOOL_BASE (0x2300)
+#define ID_API_MAINTOOL_END (0x25FF)
+
+#define ID_API_PLUGIN_BASE (0x2600)
+#define ID_API_PLUGIN_END (0x28FF)
+#else
+#define ID_API_ISP_IQ_BASE (0x1000)
+#define ID_API_ISP_IQ_END (0x13FF)
+
+#define ID_API_ISP_AE_BASE (0x1400)
+#define ID_API_ISP_AE_END (0x17FF)
+
+#define ID_API_ISP_AWB_BASE (0x1800)
+#define ID_API_ISP_AWB_END (0x1BFF)
+
+#define ID_API_ISP_AF_BASE (0x1C00)
+#define ID_API_ISP_AF_END (0x1FFF)
+
+#define ID_API_ISP_OTHER_BASE (0x2000)
+#define ID_API_ISP_OTHER_END (0x23FF)
+
+#define ID_API_CALIBRATION_20_BASE (0x2400)
+#define ID_API_CALIBRATION_20_END (0x27FF)
+
+#define ID_API_MAINTOOL_BASE (0x2800)
+#define ID_API_MAINTOOL_END (0x2BFF)
+
+#define ID_API_PLUGIN_BASE (0x2C00)
+#define ID_API_PLUGIN_END (0x2DFF)
+
+#define ID_API_CUS3A_BASE (0x2E00)
+#define ID_API_CUS3A_END (0x2FFF)
+
+#define ID_API_DEBUG_LEVEL_BASE (0x2FFF)
+#define ID_API_DEBUG_LEVEL_END (0x3100)
+
+#define ID_API_RESERVED_BASE (0x3101)
+#define ID_API_RESERVED_END (0x3FFF)
+
+#endif
+
+#define ID_CHIP_I1 (0x6d65031B)
+#define ID_CHIP_I3 (0x6d65031C)
+#define ID_CHIP_I2 (0x6d65031D)
+#define ID_CHIP_I5 (0x6d65031E)
+#define ID_CHIP_I6 (0x6d650320)
+#define ID_CHIP_I6E (0x6d650321)
+#define ID_CHIP_I6B0 (0x6d650322)
+#define ID_CHIP_M5 (0x6d65031F)
+
+//================================================================
+// ID Defined : Common API
+//================================================================
+#define ID_API_COMMON_I2C_ACCESS ( ID_API_COMMON_BASE + 32 ) //SET_API_ID_MI_ISP_WriteI2C
+//#define ID_API_COMMON_QuerySensorInfo ( ID_API_COMMON_BASE + 33 ) //GET_API_ID_MI_ISP_QuerySensorInfo
+#define ID_API_COMMON_MIRROR ( ID_API_COMMON_BASE + 34 )
+#define ID_API_COMMON_ROTATE ( ID_API_COMMON_BASE + 35 )
+#define ID_API_COMMON_SENSOR_ID ( ID_API_COMMON_BASE + 36 )
+
+#define ID_API_COMMON_FileID ( ID_API_COMMON_BASE + 100 ) //I1 or I3 or I2 or I5 ...
+#define ID_API_COMMON_CHANNEL_ID ( ID_API_COMMON_BASE + 101 )
+#define ID_API_COMMON_ISPROOT ( ID_API_COMMON_BASE + 102 )
+
+//================================================================
+// ID Defined : ISP API
+//================================================================
+#define ID_API_ISP_IQ_VERSION_INFO ( ID_API_ISP_IQ_BASE + 1 ) // 1. 4097
+#define ID_API_ISP_IQ_PARAM_INIT_STATUS ( ID_API_ISP_IQ_BASE + 2 ) // 2. 4098
+#define ID_API_ISP_IQ_FAST_MODE ( ID_API_ISP_IQ_BASE + 3 ) // 3. 4099
+#define ID_API_ISP_IQ_COLORTOGRAY ( ID_API_ISP_IQ_BASE + 4 ) // 4. 4100
+#define ID_API_ISP_IQ_CONTRAST ( ID_API_ISP_IQ_BASE + 5 ) // 5. 4101
+#define ID_API_ISP_IQ_BRIGHTNESS ( ID_API_ISP_IQ_BASE + 6 ) // 6. 4102
+#define ID_API_ISP_IQ_LIGHTNESS ( ID_API_ISP_IQ_BASE + 7 ) // 7. 4103
+#define ID_API_ISP_IQ_RGBGAMMA ( ID_API_ISP_IQ_BASE + 8 ) // 8. 4104
+#define ID_API_ISP_IQ_YUVGAMMA ( ID_API_ISP_IQ_BASE + 9 ) // 9. 4105
+#define ID_API_ISP_IQ_SATURATION ( ID_API_ISP_IQ_BASE + 10 ) // 10. 4106
+#define ID_API_ISP_IQ_DEFOG ( ID_API_ISP_IQ_BASE + 11 ) // 11. 4107
+#define ID_API_ISP_IQ_CCM ( ID_API_ISP_IQ_BASE + 12 ) // 12. 4108
+#define ID_API_ISP_IQ_ANTI_FALSE_COLOR ( ID_API_ISP_IQ_BASE + 13 ) // 13. 4109
+#define ID_API_ISP_IQ_NR3D ( ID_API_ISP_IQ_BASE + 14 ) // 14. 4110
+#define ID_API_ISP_IQ_NR2D_DESPIKE ( ID_API_ISP_IQ_BASE + 15 ) // 15. 4111
+#define ID_API_ISP_IQ_NR2D_LUMA ( ID_API_ISP_IQ_BASE + 16 ) // 16. 4112
+#define ID_API_ISP_IQ_NR2D_CHROMA ( ID_API_ISP_IQ_BASE + 17 ) // 17. 4113
+#define ID_API_ISP_IQ_SHARPNESS ( ID_API_ISP_IQ_BASE + 18 ) // 18. 4114
+#define ID_API_ISP_IQ_CROSSTALK ( ID_API_ISP_IQ_BASE + 19 ) // 19. 4115
+#define ID_API_ISP_IQ_BLACK_LEVEL ( ID_API_ISP_IQ_BASE + 20 ) // 20. 4116
+#define ID_API_ISP_IQ_BLACK_LEVEL_P1 ( ID_API_ISP_IQ_BASE + 21 ) // 21. 4117
+#define ID_API_ISP_IQ_WDR ( ID_API_ISP_IQ_BASE + 22 ) // 22. 4118
+#define ID_API_ISP_IQ_DEFECT_PIXEL ( ID_API_ISP_IQ_BASE + 23 ) // 23. 4119
+#define ID_API_ISP_IQ_HSV ( ID_API_ISP_IQ_BASE + 24 ) // 24. 4120
+#define ID_API_ISP_IQ_RGBIR ( ID_API_ISP_IQ_BASE + 25 ) // 25. 4121
+#define ID_API_ISP_IQ_FPN ( ID_API_ISP_IQ_BASE + 26 ) // 26. 4122
+#define ID_API_ISP_IQ_PFC ( ID_API_ISP_IQ_BASE + 27 ) // 27. 4123
+#define ID_API_ISP_IQ_DM ( ID_API_ISP_IQ_BASE + 28 ) // 28. 4124
+#define ID_API_ISP_IQ_COLOR_TRANSFORM ( ID_API_ISP_IQ_BASE + 29 ) // 29. 4125
+#define ID_API_ISP_IQ_HDR ( ID_API_ISP_IQ_BASE + 30 ) // 30. 4126
+#define ID_API_ISP_IQ_EFFECT ( ID_API_ISP_IQ_BASE + 31 ) // 31. 4127
+#define ID_API_ISP_IQ_SYS_MCNR_MEMORY ( ID_API_ISP_IQ_BASE + 32 ) // 32. 4128
+#define ID_API_ISP_IQ_LSC ( ID_API_ISP_IQ_BASE + 33 ) // 33. 4129
+#define ID_API_ISP_IQ_PARAM_MODE ( ID_API_ISP_IQ_BASE + 34 ) // 34. 4130
+#define ID_API_ISP_IQ_LinearityLUT ( ID_API_ISP_IQ_BASE + 35 ) // 35. 4131 //Get Gamma data for CCM calibration
+#define ID_API_ISP_IQ_OBCCALIB ( ID_API_ISP_IQ_BASE + 36 ) // 36. 4132 //Get OB data for Gamma or CCM calibration
+#define ID_API_ISP_IQ_NR3D_P1 ( ID_API_ISP_IQ_BASE + 37 ) // 37. 4133
+#define ID_API_ISP_IQ_WDR_FC_CURVE ( ID_API_ISP_IQ_BASE + 38 ) // 38. 4134
+#define ID_API_ISP_IQ_R2Y ( ID_API_ISP_IQ_BASE + 39 ) // 39. 4135
+#define ID_API_ISP_IQ_ALSC ( ID_API_ISP_IQ_BASE + 40 ) // 40. 4136
+#define ID_API_ISP_IQ_LSC_CTRL ( ID_API_ISP_IQ_BASE + 41 ) // 41. 4137
+#define ID_API_ISP_IQ_ALSC_CTRL ( ID_API_ISP_IQ_BASE + 42 ) // 42. 4138
+#define ID_API_ISP_IQ_DEFECT_PIXEL_CLUSTER ( ID_API_ISP_IQ_BASE + 43 ) // 43. 4139
+#define ID_API_ISP_IQ_QUERY_CCM_INFO ( ID_API_ISP_IQ_BASE + 44 ) // 44. 4140
+#define ID_API_ISP_IQ_NR2D_LUMA_ADV ( ID_API_ISP_IQ_BASE + 45 ) // 45. 4141
+#define ID_API_ISP_IQ_NR2D_CHROMA_ADV ( ID_API_ISP_IQ_BASE + 46 ) // 46. 4142
+#define ID_API_ISP_IQ_PFC_EX ( ID_API_ISP_IQ_BASE + 47 ) // 47. 4143
+#define ID_API_ISP_IQ_HDR_EX ( ID_API_ISP_IQ_BASE + 48 ) // 48. 4144
+#define ID_API_ISP_IQ_SHP_EX ( ID_API_ISP_IQ_BASE + 49 ) // 49. 4145
+#define ID_API_ISP_IQ_NR_3D_EX ( ID_API_ISP_IQ_BASE + 50 ) // 50. 4146
+#define ID_API_ISP_IQ_DUMMY ( ID_API_ISP_IQ_BASE + 51 ) // 51. 4147
+#define ID_API_ISP_IQ_DUMMY_EX ( ID_API_ISP_IQ_BASE + 52 ) // 52. 4148
+#define ID_API_ISP_IQ_WDR_FC_CURVE_FULL ( ID_API_ISP_IQ_BASE + 53 ) // 53. 4149
+#define ID_API_ISP_IQ_ADAPTIVE_GAMMA ( ID_API_ISP_IQ_BASE + 54 ) // 54. 4150
+#define ID_API_ISP_IQ_NR2D_CHROMA_PRE ( ID_API_ISP_IQ_BASE + 55 ) // 55. 4151
+#define ID_API_ISP_IQ_TEMP ( ID_API_ISP_IQ_BASE + 56 ) // 56. 4152
+#define ID_API_ISP_IQ_TEMP_INFO ( ID_API_ISP_IQ_BASE + 57 ) // 57. 4153
+
+#define ID_API_ISP_AE_HIST_WEIGHT_Y ( ID_API_ISP_AE_BASE + 1 ) // 1. 5121
+#define ID_API_ISP_AE_QUERY_EXPOSURE_INFO ( ID_API_ISP_AE_BASE + 2 ) // 2. 5122
+#define ID_API_ISP_AE_EV_COMP ( ID_API_ISP_AE_BASE + 3 ) // 3. 5123
+#define ID_API_ISP_AE_EXPO_MODE ( ID_API_ISP_AE_BASE + 4 ) // 4. 5124
+#define ID_API_ISP_AE_MANUAL_EXPO ( ID_API_ISP_AE_BASE + 5 ) // 5. 5125
+#define ID_API_ISP_AE_STATE ( ID_API_ISP_AE_BASE + 6 ) // 6. 5126
+#define ID_API_ISP_AE_TARGET ( ID_API_ISP_AE_BASE + 7 ) // 7. 5127
+#define ID_API_ISP_AE_CONVERGE ( ID_API_ISP_AE_BASE + 8 ) // 8. 5128
+#define ID_API_ISP_AE_EXPOSURE_LIMIT ( ID_API_ISP_AE_BASE + 9 ) // 9. 5129
+#define ID_API_ISP_AE_PLAIN_LONG_EXPO_TABLE ( ID_API_ISP_AE_BASE + 10 ) // 10. 5130
+#define ID_API_ISP_AE_PLAIN_SHORT_EXPO_TABLE ( ID_API_ISP_AE_BASE + 11 ) // 11. 5131
+#define ID_API_ISP_AE_WINDOW_WGT_MODE ( ID_API_ISP_AE_BASE + 12 ) // 12. 5132
+#define ID_API_ISP_AE_WINDOW_WGT ( ID_API_ISP_AE_BASE + 13 ) // 13. 5133
+#define ID_API_ISP_AE_FLICKER ( ID_API_ISP_AE_BASE + 14 ) // 14. 5134
+#define ID_API_ISP_AE_STRATEGY ( ID_API_ISP_AE_BASE + 15 ) // 15. 5135
+#define ID_API_ISP_AE_RGBIRExposureAttr ( ID_API_ISP_AE_BASE + 16 ) // 16. 5136
+#define ID_API_ISP_AE_HDR ( ID_API_ISP_AE_BASE + 17 ) // 17. 5137
+#define ID_API_ISP_AE_MANUAL_EXPO_SHORT ( ID_API_ISP_AE_BASE + 18 ) // 18. 5138
+#define ID_API_ISP_AE_FLICKER_EX ( ID_API_ISP_AE_BASE + 19 ) // 19. 5139
+#define ID_API_ISP_AE_QUERY_FLICKER_EX_INFO ( ID_API_ISP_AE_BASE + 20 ) // 20. 5140
+#define ID_API_ISP_AE_STABILIZER ( ID_API_ISP_AE_BASE + 21 ) // 21. 5141
+#define ID_API_ISP_AE_STRATEGY_EX ( ID_API_ISP_AE_BASE + 22 ) // 22. 5142
+#define ID_API_ISP_AE_QUERY_STRATEGY_EX_INFO ( ID_API_ISP_AE_BASE + 23 ) // 24. 5143
+
+#define ID_API_ISP_AWB_QUERY_WHITE_BALANCE_INFO ( ID_API_ISP_AWB_BASE + 1 ) // 1. 6145
+#define ID_API_ISP_AWB_ATTR ( ID_API_ISP_AWB_BASE + 2 ) // 2. 6146
+#define ID_API_ISP_AWB_ATTR_EX ( ID_API_ISP_AWB_BASE + 3 ) // 3. 6147
+#define ID_API_ISP_AWB_MULTI_LS_ATTR ( ID_API_ISP_AWB_BASE + 4 ) // 4. 6148
+#define ID_API_ISP_AWB_CT_WEIGHT ( ID_API_ISP_AWB_BASE + 5 ) // 5. 6149
+#define ID_API_ISP_AWB_CTMWB ( ID_API_ISP_AWB_BASE + 6 ) // 5. 6150
+
+//#define ID_API_ISP_AF_QUERY_FOCUS_INFO ( ID_API_ISP_AF_BASE + 1 ) // 1. 7169
+//#define ID_API_ISP_AF_WINDOW ( ID_API_ISP_AF_BASE + 2 ) // 2. 7170
+//#define ID_API_ISP_AF_FILTER ( ID_API_ISP_AF_BASE + 3 ) // 3. 7171
+
+
+//#define ID_API_VENC_RcParamEx ( ID_API_ISP_OTHER_BASE + 1 ) // 1. 8193 --> old ( ID_API_ISP_BASE + 35 ) //35. 4131
+//#define ID_API_VI_SensorFrameRate ( ID_API_ISP_OTHER_BASE + 2 ) // 2. 8194 --> old ( ID_API_ISP_BASE + 36 ) //36. 4132
+//#define ID_API_VENC_Resolution ( ID_API_ISP_OTHER_BASE + 3 ) // 3. 8195 --> old ( ID_API_ISP_BASE + 37 ) //37. 4133
+
+//================================================================
+// ID Defined : Calibration 2.0 API
+//================================================================
+#define ID_API_CALIBRATION_20_CaliBVAV ( ID_API_CALIBRATION_20_BASE + 1) // 1. 9217 //SET_API_ID_CALIBRATION_CaliBVAV = 61,
+#define ID_API_CALIBRATION_20_Apply ( ID_API_CALIBRATION_20_BASE + 2) // 2. 9218 //SET_API_ID_CALIBRATION_ApplyBVAV = 62,
+#define ID_API_CALIBRATION_20_CaliData ( ID_API_CALIBRATION_20_BASE + 3) // 3. 9219 //SET_API_ID_CALIBRATION_SetCaliData = 63,
+#define ID_API_CALIBRATION_20_CaliPath ( ID_API_CALIBRATION_20_BASE + 4) // 4. 9220 //SET_API_ID_CALIBRATION_SetCaliPath = 64,
+#define ID_API_CALIBRATION_20_CaliDBPath ( ID_API_CALIBRATION_20_BASE + 5) // 5. 9221 //SET_API_ID_CALIBRATION_SetCaliDBPath
+#define ID_API_CALIBRATION_20_CaliInfo ( ID_API_CALIBRATION_20_BASE + 6) // 6. 9222 //GET_API_ID_CALIBRATION_GetCaliInfo
+
+#define ID_API_CALIBRATION_20_CaliAWB ( ID_API_CALIBRATION_20_BASE + 7) // 7. 9223
+#define ID_API_CALIBRATION_20_CaliOB ( ID_API_CALIBRATION_20_BASE + 8) // 8. 9224
+#define ID_API_CALIBRATION_20_CaliMinGain ( ID_API_CALIBRATION_20_BASE + 9) // 9. 9225
+#define ID_API_CALIBRATION_20_CaliShutterLinearity ( ID_API_CALIBRATION_20_BASE + 10) // 10. 9226
+#define ID_API_CALIBRATION_20_CaliGainLinearity ( ID_API_CALIBRATION_20_BASE + 11) // 11 9227
+#define ID_API_CALIBRATION_20_CaliDPC ( ID_API_CALIBRATION_20_BASE + 12) // 12. 9228
+#define ID_API_CALIBRATION_20_CaliALSC ( ID_API_CALIBRATION_20_BASE + 13) // 13. 9229
+#define ID_API_CALIBRATION_20_CaliFPN ( ID_API_CALIBRATION_20_BASE + 14) // 14. 9230
+
+#define ID_API_CALIBRATION_30_ApplyAWB ( ID_API_CALIBRATION_20_BASE + 15) // 15. 9231
+#define ID_API_CALIBRATION_30_ApplyOBC ( ID_API_CALIBRATION_20_BASE + 16) // 16. 9232
+#define ID_API_CALIBRATION_30_ApplyMinGain ( ID_API_CALIBRATION_20_BASE + 17) // 17. 9233
+#define ID_API_CALIBRATION_30_ApplyShutterLinearity ( ID_API_CALIBRATION_20_BASE + 18) // 18. 9234
+#define ID_API_CALIBRATION_30_ApplyGainLinearity ( ID_API_CALIBRATION_20_BASE + 19) // 19 9235
+#define ID_API_CALIBRATION_30_ApplySDC ( ID_API_CALIBRATION_20_BASE + 20) // 20. 9236
+#define ID_API_CALIBRATION_30_ApplyALSC ( ID_API_CALIBRATION_20_BASE + 21) // 21. 9237
+#define ID_API_CALIBRATION_30_ApplyFPN ( ID_API_CALIBRATION_20_BASE + 22) // 22. 9238
+#define ID_API_CALIBRATION_30_ApplyLSC ( ID_API_CALIBRATION_20_BASE + 23) // 21. 9239
+
+//================================================================
+// ID Defined : MainTool API
+//================================================================
+#define ID_API_MAINTOOL_QUERY_SENSOR_INFO ( ID_API_MAINTOOL_BASE + 1 ) // 1. 10241
+#define ID_API_MAINTOOL_IQ_INDEX ( ID_API_MAINTOOL_BASE + 2 ) // 2. 10242
+#define ID_API_MAINTOOL_BYPASS ( ID_API_MAINTOOL_BASE + 3 ) // 3. 10243
+
+//================================================================
+// ID Defined : Plugin API
+//================================================================
+#define ID_API_PLUGIN_I2C_ACCESS ( ID_API_PLUGIN_BASE + 1 ) // 1. 11265 //SET_API_ID_MI_ISP_WriteI2C
+#define ID_API_PLUGIN_WBCT ( ID_API_PLUGIN_BASE + 3 ) // 3. 11267 //SetWBCTCaliAttr
+#define ID_API_PLUGIN_AWBCTStats ( ID_API_PLUGIN_BASE + 4 ) // 4. 11268
+#define ID_API_PLUGIN_AWBHWStats ( ID_API_PLUGIN_BASE + 5 ) // 5. 11269
+#define ID_API_PLUGIN_CUR_WBCT ( ID_API_PLUGIN_BASE + 6 ) // 6. 11270 //GetCurCTCaliAttr
+
+//================================================================
+// ID Defined : Cus3A API
+//================================================================
+#define ID_API_CUS_AE_HW_AVG_STATS ( ID_API_CUS3A_BASE + 1 ) // 1. 11777
+#define ID_API_CUS_AE_HW_HISTO_0_STATS ( ID_API_CUS3A_BASE + 2 ) // 2. 11778
+#define ID_API_CUS_AE_HW_HISTO_1_STATS ( ID_API_CUS3A_BASE + 3 ) // 3. 11779
+#define ID_API_CUS_AE_GET_INIT_STATUS ( ID_API_CUS3A_BASE + 4 ) // 4. 11780
+#define ID_API_CUS_AE_GET_CUR_STATUS ( ID_API_CUS3A_BASE + 5 ) // 5. 11781
+#define ID_API_CUS_AE_SET_PARAM ( ID_API_CUS3A_BASE + 6 ) // 6. 11782
+#define ID_API_CUS_AWB_HW_AVG_STATS ( ID_API_CUS3A_BASE + 7 ) // 7. 11783
+#define ID_API_CUS_3A_ENABLE ( ID_API_CUS3A_BASE + 8 ) // 8. 11784
+#define ID_API_CUS_AWB_GET_CUR_STATUS ( ID_API_CUS3A_BASE + 9 ) // 9. 11785
+#define ID_API_CUS_AWB_SET_PARAM ( ID_API_CUS3A_BASE + 10) //10. 11786
+#define ID_API_CUS_AE_WINDOW_BLOCK_NUMBER ( ID_API_CUS3A_BASE + 11 )//11. 11787
+#define ID_API_CUS_AWB_SAMPLING ( ID_API_CUS3A_BASE + 12 )//12. 11788
+#define ID_API_CUS_AF_STATS ( ID_API_CUS3A_BASE + 13 )//13. 11789
+#define ID_API_CUS_AF_WINDOW ( ID_API_CUS3A_BASE + 14 )//14. 11790
+#define ID_API_CUS_AF_FILTER ( ID_API_CUS3A_BASE + 15 )//15. 11791
+#define ID_API_CUS_AF_FILTER_SQUARE ( ID_API_CUS3A_BASE + 16 )//16. 11792
+#define ID_API_CUS_AF_MODE ( ID_API_CUS3A_BASE + 17 )//17. 11793
+#define ID_API_CUS_AE_HISTOGRAM_WINDOW ( ID_API_CUS3A_BASE + 18 )//18. 11794
+#define ID_API_CUS_GET_IMAGE_RESOLUTION ( ID_API_CUS3A_BASE + 19 )//19. 11795
+#define ID_API_CUS_ENABLE_ISP_OUT_IMAGE ( ID_API_CUS3A_BASE + 20 )//20. 11796
+#define ID_API_CUS_GET_ISP_OUT_IMAGE_COUNT ( ID_API_CUS3A_BASE + 21 )//21. 11797
+#define ID_API_CUS_CAPTURE_HDR_RAW_IMAGE ( ID_API_CUS3A_BASE + 22 )//22. 11798
+#define ID_API_CUS_FRAME_META_INFO ( ID_API_CUS3A_BASE + 23 )//23. 11799
+#define ID_API_CUS_I2C_ACCESS ( ID_API_CUS3A_BASE + 24 )//24. 11800
+#define ID_API_CUS_AWB_HW_AVG_STATS_SHORT ( ID_API_CUS3A_BASE + 25 ) // 25. 11801
+#define ID_API_CUS_CAPTURE_RAW_IMAGE ( ID_API_CUS3A_BASE + 26 )//26. 11802
+#define ID_API_CUS_CUSTOMER_AE_CTRL ( ID_API_CUS3A_BASE + 27 )//27. 11803 , Customer defined AE control only
+#define ID_API_CUS_CUSTOMER_AWB_CTRL ( ID_API_CUS3A_BASE + 28 )//28. 11804 , Customer defined AWB control only
+#define ID_API_CUS_CUSTOMER_AF_CTRL ( ID_API_CUS3A_BASE + 29 )//29. 11805 , Customer defined AF control only
+#define ID_API_CUS_AE_HW_RGBIR_HISTO_STATS ( ID_API_CUS3A_BASE + 30 ) // 30. 11806
+#ifdef ENABLE_EARLY_AE_DONE
+#define ID_API_CUS_AE_DONE_RATIO ( ID_API_CUS3A_BASE + 27 )//27. 11803
+#endif
+#define ID_API_CUS_AE_CROP_SIZE ( ID_API_CUS3A_BASE + 31 )//34. 11807
+#define ID_API_CUS_AWB_CROP_SIZE ( ID_API_CUS3A_BASE + 32 )//35. 11808
+
+//================================================================
+// ID Defined : Debug Level API
+//================================================================
+#define ID_API_ISP_DeBugLevel_AE ( ID_API_DEBUG_LEVEL_BASE + 1 ) // 1. 12288
+#define ID_API_ISP_DeBugLevel_AWB ( ID_API_DEBUG_LEVEL_BASE + 2 ) // 2. 12289
+#define ID_API_ISP_DeBugLevel_AWB_PERIOD ( ID_API_DEBUG_LEVEL_BASE + 3 ) // 3. 12290
+
+#define ID_API_REGISTER_API_SET_CB ( ID_API_RESERVED_BASE + 1) //1. register API_SET callback
+#define ID_API_REGISTER_API_GET_CB ( ID_API_RESERVED_BASE + 2) //2. register API_GET callback
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_TUNINGSERVER_API_ID_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_datatype.h
new file mode 100644
index 00000000..5926e888
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_datatype.h
@@ -0,0 +1,407 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp_datatype.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_DATATYPE_H_
+#define _MI_ISP_DATATYPE_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "mi_common.h"
+#include "mi_sys_datatype.h"
+#include "mi_isp_3a_datatype.h"
+#include "mi_isp_iq_datatype.h"
+
+/************************************* AF - Define the structure declaration - START *************************************/
+
+/************************************* AF - Define the structure declaration - END *************************************/
+
+/************************** Cus3A ***********************/
+
+typedef struct
+{
+ MI_U8 uAvgR;
+ MI_U8 uAvgG;
+ MI_U8 uAvgB;
+ MI_U8 uAvgY;
+} MI_ISP_AE_AVGS;
+
+typedef struct
+{
+ MI_U32 nBlkX;
+ MI_U32 nBlkY;
+ MI_ISP_AE_AVGS nAvg[128*90];
+}MI_ISP_AE_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U8 uAvgR;
+ MI_U8 uAvgG;
+ MI_U8 uAvgB;
+} MI_ISP_AWB_AVGS;
+
+typedef struct
+{
+ MI_U32 nBlkX;
+ MI_U32 nBlkY;
+ MI_ISP_AWB_AVGS nAvg[128*90];
+} MI_ISP_AWB_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U16 nHisto[128];
+} MI_ISP_HISTO_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_U16 nHisto[256];
+} MI_ISP_RGBIR_HISTO_HW_STATISTICS_t;
+
+typedef struct
+{
+ MI_BOOL bAE;
+ MI_BOOL bAWB;
+ MI_BOOL bAF;
+}Cus3AEnable_t;
+
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ char sensor_id[32]; /**< sensor module id*/
+ MI_U32 shutter; /**< shutter Shutter in ns*/
+ MI_U32 shutter_step; /**< shutter Shutter step ns*/
+ MI_U32 shutter_min; /**< shutter Shutter min us*/
+ MI_U32 shutter_max; /**< shutter Shutter max us*/
+ MI_U32 sensor_gain; /**< sensor_gain Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gain_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gain_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ MI_U32 isp_gain; /**< isp_gain Isp digital gain , 1X = 1024 */
+ MI_U32 isp_gain_max; /**< isp_gain Maximum Isp digital gain , 1X = 1024 */
+ MI_U32 FNx10; /**< F number * 10*/
+ MI_U32 fps; /**< initial frame per second*/
+ MI_U32 shutterHDRShort_step; /**< shutter Shutter step ns*/
+ MI_U32 shutterHDRShort_min; /**< shutter Shutter min us*/
+ MI_U32 shutterHDRShort_max; /**< shutter Shutter max us*/
+ MI_U32 sensor_gainHDRShort_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MI_U32 sensor_gainHDRShort_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ /*CUS3A v1.1*/
+ MI_U32 AvgBlkX; /**< HW statistics average block number*/
+ MI_U32 AvgBlkY; /**< HW statistics average block number*/
+}CusAEInitParam_t,CusAeInitParam_t;
+
+/*! @brief ISP report to AE, hardware statistic */
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ void *hist1; /**< HW statistic histogram 1*/
+ void *hist2; /**< HW statistic histogram 2*/
+ MI_U32 AvgBlkX; /**< HW statistics average block number*/
+ MI_U32 AvgBlkY; /**< HW statistics average block number*/
+ void * avgs; /**< HW statistics average block data*/
+ MI_U32 Shutter; /**< Current shutter in ns*/
+ MI_U32 SensorGain; /**< Current Sensor gain, 1X = 1024 */
+ MI_U32 IspGain; /**< Current ISP gain, 1X = 1024*/
+ MI_U32 ShutterHDRShort; /**< Current shutter in ns*/
+ MI_U32 SensorGainHDRShort; /**< Current Sensor gain, 1X = 1024 */
+ MI_U32 IspGainHDRShort; /**< Current ISP gain, 1X = 1024*/
+ /*CUS3A V1.1*/
+ MI_U32 PreAvgY; /**< Previous frame brightness*/
+ MI_U8 HDRCtlMode; /**< 0 = HDR off; */
+ /**< 1 = Separate shutter & Separate sensor gain settings */
+ /**< 2 = Separate shutter & Share sensor gain settings */
+ /**< 3 = Share shutter & Separate sensor gain settings */
+ MI_U32 FNx10; /**< Aperture in FNx10*/
+ MI_U32 CurFPS; /**Current sensor FPS */
+ MI_U32 PreWeightY; /**< Previous frame brightness with ROI weight*/
+} __attribute__((packed, aligned(1))) CusAEInfo_t, CusAeInput_t;
+
+/*! @brief ISP ae algorithm result*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 Change; /**< if true, apply this result to hw register*/
+ MI_U32 Shutter; /**< Shutter in ns */
+ MI_U32 SensorGain; /**< Sensor gain, 1X = 1024 */
+ MI_U32 IspGain; /**< ISP gain, 1X = 1024 */
+ MI_U32 ShutterHdrShort; /**< Shutter in ns */
+ MI_U32 SensorGainHdrShort; /**< Sensor gain, 1X = 1024 */
+ MI_U32 IspGainHdrShort; /**< ISP gain, 1X = 1024 */
+ MI_U32 u4BVx16384; /**< Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ MI_U32 AvgY; /**< frame brightness */
+ MI_U32 HdrRatio; /**< hdr ratio, 1X = 1024 */
+ /*CUS3A V1.1*/
+ MI_U32 FNx10; /**< F number * 10*/
+ MI_U32 DebandFPS; /** Target fps when running auto debanding**/
+ MI_U32 WeightY; /**< frame brightness with ROI weight*/
+}__attribute__((packed, aligned(1))) CusAEResult_t, CusAeOutput_t;
+
+/*! @brief AWB HW statistics data*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 AvgBlkX;
+ MI_U32 AvgBlkY;
+ MI_U32 CurRGain;
+ MI_U32 CurGGain;
+ MI_U32 CurBGain;
+ void *avgs; //ISP_AWB_SAMPLE
+ /*CUS3A V1.1*/
+ MI_U8 HDRMode; /**< Noramal or HDR mode*/
+ void* *pAwbStatisShort; /**< Short Shutter AWB statistic data */
+ MI_U32 u4BVx16384; /**< From AE output, Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ MI_S32 WeightY; /**< frame brightness with ROI weight*/
+}__attribute__((packed, aligned(1))) CusAWBInfo_t, CusAWBInput_t;
+
+/*! @brief AWB algorithm result*/
+typedef struct
+{
+ MI_U32 Size; /**< struct size*/
+ MI_U32 Change; /**< if true, apply this result to hw register*/
+ MI_U32 R_gain; /**< AWB gain for R channel*/
+ MI_U32 G_gain; /**< AWB gain for G channel*/
+ MI_U32 B_gain; /**< AWB gain for B channel*/
+ MI_U32 ColorTmp; /**< Return color temperature*/
+}CusAWBResult_t, CusAwbOutput_t;;
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ SS_AE_16x24 = 0,
+ SS_AE_32x24,
+ SS_AE_64x48,
+ SS_AE_64x45,
+ SS_AE_128x80,
+ SS_AE_128x90,
+ SS_AE_32x32
+} MS_CUST_AE_WIN_BLOCK_NUM_TYPE_e;
+
+typedef struct {
+ MI_U16 u2Stawin_x_offset;
+ MI_U16 u2Stawin_x_size;
+ MI_U16 u2Stawin_y_offset;
+ MI_U16 u2Stawin_y_size;
+ MI_U16 u2WinIdx;
+} CusAEHistWin_t;
+
+typedef struct
+{
+ MI_U32 SizeX;
+ MI_U32 SizeY;
+ MI_U32 IncRatio;
+}CusAWBSample_t;
+
+typedef struct
+{
+ MI_U16 CropX; // 0~1023
+ MI_U16 CropY; // 0~1023
+ MI_U16 CropW; // 0~1023
+ MI_U16 CropH; // 0~1023
+}CusAEAWBCropSize_t;
+
+typedef struct
+{
+ MI_U8 iir_1[5*16]; //[5]: iir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 iir_2[5*16]; //[5]: iir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 luma[4*16]; //[4]: luma 32bit, use 4*u8 datatype, [16]: 16wins
+ MI_U8 fir_v[5*16]; //[5]: fir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 fir_h[5*16]; //[5]: fir 35bit, use 5*u8 datatype, [16]: 16wins
+ MI_U8 ysat[3*16]; //[3]: ysat 22bit, use 3*u8 datatype, [16]: 16wins
+} AF_STATS_PARAM_t;
+
+typedef struct
+{
+ AF_STATS_PARAM_t stParaAPI[16];
+} CusAFStats_t;
+
+typedef struct AF_WINDOW_PARAM_s
+{
+ MI_U32 u32StartX; /*range : 0~1023*/
+ MI_U32 u32StartY; /*range : 0~1023*/
+ MI_U32 u32EndX; /*range : 0~1023*/
+ MI_U32 u32EndY; /*range : 0~1023*/
+} AF_WINDOW_PARAM_t;
+
+typedef struct
+{
+ MI_U8 u8WindowIndex;
+ AF_WINDOW_PARAM_t stParaAPI;
+} CusAFWin_t;
+
+typedef struct
+{
+ MI_U16 u16IIR1_a0;
+ MI_U16 u16IIR1_a1;
+ MI_U16 u16IIR1_a2;
+ MI_U16 u16IIR1_b1;
+ MI_U16 u16IIR1_b2;
+ MI_U16 u16IIR1_1st_low_clip;
+ MI_U16 u16IIR1_1st_high_clip;
+ MI_U16 u16IIR1_2nd_low_clip;
+ MI_U16 u16IIR1_2nd_high_clip;
+ MI_U16 u16IIR2_a0;
+ MI_U16 u16IIR2_a1;
+ MI_U16 u16IIR2_a2;
+ MI_U16 u16IIR2_b1;
+ MI_U16 u16IIR2_b2;
+ MI_U16 u16IIR2_1st_low_clip;
+ MI_U16 u16IIR2_1st_high_clip;
+ MI_U16 u16IIR2_2nd_low_clip;
+ MI_U16 u16IIR2_2nd_high_clip;
+
+ MI_U16 u16IIR1_e1_en;
+ MI_U16 u16IIR1_e1_a0;
+ MI_U16 u16IIR1_e1_a1;
+ MI_U16 u16IIR1_e1_a2;
+ MI_U16 u16IIR1_e1_b1;
+ MI_U16 u16IIR1_e1_b2;
+ MI_U16 u16IIR1_e2_en;
+ MI_U16 u16IIR1_e2_a0;
+ MI_U16 u16IIR1_e2_a1;
+ MI_U16 u16IIR1_e2_a2;
+ MI_U16 u16IIR1_e2_b1;
+ MI_U16 u16IIR1_e2_b2;
+
+ MI_U16 u16IIR2_e1_en;
+ MI_U16 u16IIR2_e1_a0;
+ MI_U16 u16IIR2_e1_a1;
+ MI_U16 u16IIR2_e1_a2;
+ MI_U16 u16IIR2_e1_b1;
+ MI_U16 u16IIR2_e1_b2;
+ MI_U16 u16IIR2_e2_en;
+ MI_U16 u16IIR2_e2_a0;
+ MI_U16 u16IIR2_e2_a1;
+ MI_U16 u16IIR2_e2_a2;
+ MI_U16 u16IIR2_e2_b1;
+ MI_U16 u16IIR2_e2_b2;
+} CusAFFilter_t;
+
+typedef struct
+{
+ MI_BOOL bSobelYSatEn;
+ MI_U16 u16SobelYThd;
+
+ MI_BOOL bIIRSquareAccEn;
+ MI_BOOL bSobelSquareAccEn;
+
+ MI_U16 u16IIR1Thd;
+ MI_U16 u16IIR2Thd;
+ MI_U16 u16SobelHThd;
+ MI_U16 u16SobelVThd;
+ MI_U8 u8AFTblX[12];
+ MI_U16 u16AFTblY[13];
+} CusAFFilterSq_t;
+
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ AF_ROI_MODE_NORMAL,
+ AF_ROI_MODE_MATRIX
+} ISP_AF_ROI_MODE_e;
+
+typedef struct
+{
+ ISP_AF_ROI_MODE_e mode;
+ MI_U32 u32_vertical_block_number;
+} CusAFRoiMode_t;
+
+/* Raw store control */
+typedef enum
+{
+ eRawStoreNode_P0HEAD = 0, /* Control by VIF, Do not use */
+ eRawStoreNode_P1HEAD = 1, /* Control by VIF, Do not use */
+ eRawStoreNode_P0TAIL = 2,
+ eRawStoreNode_P1TAIL = 3,
+ eRawStoreNode_ISPOUT = 4,
+ eRawStoreNode_VDOS = 5,
+ eRawStoreNode_ISPOUT_BEFORE_YEE = 6,
+ eRawStoreNode_RGBIR_IR_ONLY = 7
+}CameraRawStoreNode_e;
+
+typedef struct
+{
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32Node;
+ MI_U32 u32PixelDepth;
+} CusImageResolution_t;
+
+typedef struct
+{
+ MI_U32 u32enable;
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32physical_address;
+ MI_U32 u32Node;
+} CusISPOutImage_t;
+
+typedef struct
+{
+ MI_U32 u32enable;
+ MI_U32 u32image_width;
+ MI_U32 u32image_height;
+ MI_U32 u32physical_address;
+ MI_U32 u32Node;
+ MI_U32 u32PixelDepth;
+} CusHdrRawImage_t;
+
+typedef struct
+{
+ MI_U64 u64Pts; /** frame PTS */
+ MI_U32 u32Shutter; /**< Shutter in us */
+ MI_U32 u32SensorGain; /**< Sensor gain, 1X = 1024 */
+ MI_U32 u32ColorTmp; /**< Return color temperature*/
+} IspFrameMetaInfo_t;
+
+typedef struct
+{
+ MI_U32 u32SlaveAddr; //sensor slave address
+ MI_U32 u32RegLen; //sensor register length , 1 or 2 bytes
+ MI_U32 u32DataLen; //sensor register data length, 1 or 2 bytes
+ MI_U32 u32I2cSpeed; //i2c speed , 100/200/300/400 KHz
+ MI_U32 u32Reg; //sensor register address
+ MI_U32 u32Data; //sensor register data
+}CusSensorI2cParam_t;
+
+/***************************** end of Cus3A ****************************/
+
+// COMMON API
+typedef struct MI_ISP_API_CHANNEL_ID_TYPE_s
+{
+ MI_U32 u32ChannelID;
+} MI_ISP_API_CHANNEL_ID_TYPE_t;
+
+typedef struct MI_ISP_API_USERSPACE3A_ATTR_s
+{
+ MI_SYS_PixelFormat_e ePixelFmt;
+ MI_U32 eSensorBindId;
+} MI_ISP_API_USERSPACE3A_ATTR_t;
+
+typedef struct
+{
+ MI_S8 strIspRoot[64];
+} MI_ISP_ROOT_PATH_T;
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_general.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_general.h
new file mode 100644
index 00000000..abf87248
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_general.h
@@ -0,0 +1,187 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_GENERAL_H_
+#define _MI_ISP_GENERAL_H_
+
+#include "mi_syscall.h"
+#include "mi_vpe_datatype.h"
+#include "mi_common.h"
+#include "mi_isp.h"
+#include "mi_isp_datatype.h"
+
+#ifdef CAM_OS_LINUX_USER
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#ifdef LINUX_FLOW_ON_DUAL_OS
+#define DUAL_OS_RUN_ON_LINUX 1
+#define DUAL_OS_RUN_ON_RTOS 0
+#else
+#ifdef __RTOS__
+#define DUAL_OS_RUN_ON_LINUX 0
+#define DUAL_OS_RUN_ON_RTOS 1
+#else
+#define DUAL_OS_RUN_ON_LINUX 0
+#define DUAL_OS_RUN_ON_RTOS 0
+#endif
+#endif
+
+#define MI_ISP_MSG(args...) printf(args)
+#define MI_ISP_DMSG(args...) do{}while(0)
+#define MI_ISP_EMSG(args...) printf(args)
+#define MI_ISP_VMSG(args...) do{}while(0)
+
+#define MI_ISP_CALLOC calloc
+#define MI_ISP_FREE free
+
+extern MI_S32 MI_VPE_GetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+extern MI_S32 MI_VPE_SetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+
+MI_S32 _MI_ISP_SetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+MI_S32 _MI_ISP_GetIspApiData(MI_VPE_IspApiHeader_t *pstIspDataHeader, void *pVirData);
+
+#if (DUAL_OS_RUN_ON_LINUX)
+#define MI_GETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ PARAM_t *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(sizeof(PARAM_t), &pIspBuffer);\
+ memcpy(pIspBuffer, PtrData, sizeof(PARAM_t));\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, sizeof(PARAM_t));\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_GetIspApiData(&stIspApiHeader, pIspBuffer);\
+ memcpy(PtrData, pIspBuffer, sizeof(PARAM_t));\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+ return s32Ret;\
+
+#define MI_SETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ PARAM_t *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(sizeof(PARAM_t), &pIspBuffer);\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ memcpy(pIspBuffer, PtrData, sizeof(PARAM_t));\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, sizeof(PARAM_t));\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, pIspBuffer);\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+ return s32Ret;\
+
+#define MI_CALI_SETAPI(Channel, APIFuncID, PARAM_t, DataSize, PtrData)\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ char *pIspBuffer = NULL;\
+ MI_VPE_Alloc_IspDataBuf(DataSize, &pIspBuffer);\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = DataSize;\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ memcpy(pIspBuffer, PtrData, DataSize);\
+ MI_SYS_FlushInvCache((void *)pIspBuffer, DataSize);\
+ stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, pIspBuffer);\
+ MI_VPE_Free_IspDataBuf(pIspBuffer);\
+
+#else
+#define MI_GETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ /*s32Ret = stIspApiHeader.s32Ret = MI_VPE_GetIspApiData(&stIspApiHeader, PtrData);*/\
+ s32Ret = stIspApiHeader.s32Ret = _MI_ISP_GetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader.u32Channel, stIspApiHeader.u32CtrlID, stIspApiHeader.u32DataLen, stIspApiHeader.u32HeadSize);\
+ return s32Ret;\
+
+#define MI_SETAPI(Channel, APIFuncID, PARAM_t, PtrData)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = sizeof(PARAM_t);\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ /*s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, PtrData);*/\
+ s32Ret = stIspApiHeader.s32Ret = _MI_ISP_SetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader.u32Channel, stIspApiHeader.u32CtrlID, stIspApiHeader.u32DataLen, stIspApiHeader.u32HeadSize);\
+ return s32Ret;\
+
+#define MI_CALI_SETAPI(Channel, APIFuncID, PARAM_t, DataSize, PtrData)\
+ MI_VPE_IspApiHeader_t stIspApiHeader;\
+ stIspApiHeader.u32HeadSize = sizeof(MI_VPE_IspApiHeader_t);\
+ stIspApiHeader.u32DataLen = DataSize;\
+ stIspApiHeader.u32CtrlID = APIFuncID;\
+ stIspApiHeader.u32Channel = Channel;\
+ stIspApiHeader.s32Ret = 0;\
+ s32Ret = stIspApiHeader.s32Ret = MI_VPE_SetIspApiData(&stIspApiHeader, PtrData);\
+ MI_ISP_DMSG("[%s] - (Channel,CtrlID, DataLenght, HeadSize) = (%d,%d,%d,%d)\n", __FUNCTION__, stIspApiHeader->u32Channel, stIspApiHeader->u32CtrlID, stIspApiHeader->u32DataLen, stIspApiHeader->u32HeadSize);\
+
+#endif
+
+#define MI_ISP_SET(APIFunc, PARAM_t) \
+ if(ApiLen != sizeof(PARAM_t)) \
+ { \
+ MI_ISP_MSG("[%s][%s] APIID:%d error param \n", __FILE__, __func__, ApiId); \
+ break; \
+ } \
+ ret = APIFunc(Channel, (PARAM_t*)pApiBuf); \
+
+#define MI_ISP_GET(APIFunc, PARAM_t) \
+ *ApiLen = sizeof(PARAM_t); \
+ ret = APIFunc(Channel, (PARAM_t*)pApiBuf); \
+
+#define MI_CALL_SETAPI(Channel, APIFunc, PARAM_t)\
+ MI_S32 s32Ret = MI_ISP_OK;\
+ PARAM_t *stParam = MI_ISP_CALLOC(1, sizeof(PARAM_t));\
+ memcpy(stParam, param_ary[0], sizeof(PARAM_t));\
+ s32Ret = APIFunc(Channel, stParam);\
+ MI_ISP_DMSG("[%s][%s] param_num = %d\n", __FILE__, __FUNCTION__, param_num);\
+ MI_ISP_FREE(stParam);\
+ return s32Ret;\
+
+#define MI_RESET_API(Channel, APIFunc, PARAM_t)\
+ PARAM_t *stParam = MI_ISP_CALLOC(1, sizeof(PARAM_t));\
+ memset(stParam, 0x00, sizeof(PARAM_t));\
+ s32Ret = APIFunc(Channel, stParam);\
+ MI_ISP_DMSG("[%s][%s] param_num = %d\n", __FILE__, __FUNCTION__, param_num);\
+ MI_ISP_FREE(stParam);\
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_GENERAL_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_iq.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_iq.h
new file mode 100644
index 00000000..ff097c7f
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_iq.h
@@ -0,0 +1,278 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_isp.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_ISP_IQ_H_
+#define _MI_ISP_IQ_H_
+
+#include "mi_isp_3a_datatype.h"
+#include "mi_isp_iq_datatype.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if 1
+ /************************************* IQ API START *************************************/
+ MI_S32 MI_ISP_IQ_GetVersionInfo(MI_U32 Channel, MI_ISP_IQ_VERSION_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetVersionInfo(MI_U32 Channel, MI_ISP_IQ_VERSION_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetParaInitStatus(MI_U32 Channel, MI_ISP_IQ_PARAM_INIT_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetColorToGray(MI_U32 Channel, MI_ISP_IQ_COLORTOGRAY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetColorToGray(MI_U32 Channel, MI_ISP_IQ_COLORTOGRAY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetContrast(MI_U32 Channel, MI_ISP_IQ_CONTRAST_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetContrast(MI_U32 Channel, MI_ISP_IQ_CONTRAST_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetBrightness(MI_U32 Channel, MI_ISP_IQ_BRIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetBrightness(MI_U32 Channel, MI_ISP_IQ_BRIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLightness(MI_U32 Channel, MI_ISP_IQ_LIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLightness(MI_U32 Channel, MI_ISP_IQ_LIGHTNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBGamma(MI_U32 Channel, MI_ISP_IQ_RGBGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBGamma(MI_U32 Channel, MI_ISP_IQ_RGBGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetYUVGamma(MI_U32 Channel, MI_ISP_IQ_YUVGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetYUVGamma(MI_U32 Channel, MI_ISP_IQ_YUVGAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetSaturation(MI_U32 Channel, MI_ISP_IQ_SATURATION_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetSaturation(MI_U32 Channel, MI_ISP_IQ_SATURATION_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDefog(MI_U32 Channel, MI_ISP_IQ_DEFOG_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDefog(MI_U32 Channel, MI_ISP_IQ_DEFOG_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBMatrix(MI_U32 Channel, MI_ISP_IQ_RGBMATRIX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBMatrix(MI_U32 Channel, MI_ISP_IQ_RGBMATRIX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetFalseColor(MI_U32 Channel, MI_ISP_IQ_FALSECOLOR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetFalseColor(MI_U32 Channel, MI_ISP_IQ_FALSECOLOR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNR3D(MI_U32 Channel, MI_ISP_IQ_NR3D_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNR3D(MI_U32 Channel, MI_ISP_IQ_NR3D_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNR3D_P1(MI_U32 Channel, MI_ISP_IQ_NR3D_P1_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_GetNR3D_P1(MI_U32 Channel, MI_ISP_IQ_NR3D_P1_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_SetNRDeSpike(MI_U32 Channel, MI_ISP_IQ_NRDESPIKE_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRDeSpike(MI_U32 Channel, MI_ISP_IQ_NRDESPIKE_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRLuma(MI_U32 Channel, MI_ISP_IQ_NRLUMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRLuma(MI_U32 Channel, MI_ISP_IQ_NRLUMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRChroma(MI_U32 Channel, MI_ISP_IQ_NRChroma_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetNRChroma(MI_U32 Channel, MI_ISP_IQ_NRChroma_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetSharpness(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetSharpness(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetCrossTalk(MI_U32 Channel, MI_ISP_IQ_CROSSTALK_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetCrossTalk(MI_U32 Channel, MI_ISP_IQ_CROSSTALK_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetOBC(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetOBC(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetOBC_P1(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetOBC_P1(MI_U32 Channel, MI_ISP_IQ_OBC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDR(MI_U32 Channel, MI_ISP_IQ_WDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDR(MI_U32 Channel, MI_ISP_IQ_WDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDRCurveAdv(MI_U32 Channel, MI_ISP_IQ_WDRCurveAdv_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDRCurveAdv(MI_U32 Channel, MI_ISP_IQ_WDRCurveAdv_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetWDRCurveFull(MI_U32 Channel, MI_ISP_IQ_WDRCurveFull_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetWDRCurveFull(MI_U32 Channel, MI_ISP_IQ_WDRCurveFull_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDynamicDP(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDynamicDP(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDynamicDP_CLUSTER(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDynamicDP_CLUSTER(MI_U32 Channel, MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetHSV(MI_U32 Channel, MI_ISP_IQ_HSV_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetHSV(MI_U32 Channel, MI_ISP_IQ_HSV_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetRGBIR(MI_U32 Channel, MI_ISP_IQ_RGBIR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetRGBIR(MI_U32 Channel, MI_ISP_IQ_RGBIR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetFPN(MI_U32 Channel, MI_ISP_IQ_FPN_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_GetFPN(MI_U32 Channel, MI_ISP_IQ_FPN_TYPE_t *data); //[not support chip] macaron, pudding
+ MI_S32 MI_ISP_IQ_SetPFC(MI_U32 Channel, MI_ISP_IQ_PFC_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetPFC(MI_U32 Channel, MI_ISP_IQ_PFC_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetDEMOSAIC(MI_U32 Channel, MI_ISP_IQ_DEMOSAIC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDEMOSAIC(MI_U32 Channel, MI_ISP_IQ_DEMOSAIC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetR2Y(MI_U32 Channel, MI_ISP_IQ_R2Y_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetR2Y(MI_U32 Channel, MI_ISP_IQ_R2Y_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetCOLORTRANS(MI_U32 Channel, MI_ISP_IQ_COLORTRANS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetCOLORTRANS(MI_U32 Channel, MI_ISP_IQ_COLORTRANS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetHDR(MI_U32 Channel, MI_ISP_IQ_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetHDR(MI_U32 Channel, MI_ISP_IQ_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLSC(MI_U32 Channel, MI_ISP_IQ_LSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLSC(MI_U32 Channel, MI_ISP_IQ_LSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetLSC_CTRL(MI_U32 Channel, MI_ISP_IQ_LSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetLSC_CTRL(MI_U32 Channel, MI_ISP_IQ_LSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetALSC(MI_U32 Channel, MI_ISP_IQ_ALSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetALSC(MI_U32 Channel, MI_ISP_IQ_ALSC_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetALSC_CTRL(MI_U32 Channel, MI_ISP_IQ_ALSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetALSC_CTRL(MI_U32 Channel, MI_ISP_IQ_ALSC_CTRL_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetNRLuma_Adv(MI_U32 Channel, MI_ISP_IQ_NRLuma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNRLuma_Adv(MI_U32 Channel, MI_ISP_IQ_NRLuma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNRChroma_Adv(MI_U32 Channel, MI_ISP_IQ_NRChroma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNRChroma_Adv(MI_U32 Channel, MI_ISP_IQ_NRChroma_Adv_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNRChroma_Pre(MI_U32 Channel, MI_ISP_IQ_NRChroma_Pre_TYPE_t *data); //[not support chip] macaron, pudding, ispahan
+ MI_S32 MI_ISP_IQ_GetNRChroma_Pre(MI_U32 Channel, MI_ISP_IQ_NRChroma_Pre_TYPE_t *data); //[not support chip] macaron, pudding, ispahan
+ MI_S32 MI_ISP_IQ_SetPFC_EX(MI_U32 Channel, MI_ISP_IQ_PFC_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetPFC_EX(MI_U32 Channel, MI_ISP_IQ_PFC_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetHDR_EX(MI_U32 Channel, MI_ISP_IQ_HDR_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetHDR_EX(MI_U32 Channel, MI_ISP_IQ_HDR_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetSHP_EX(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetSHP_EX(MI_U32 Channel, MI_ISP_IQ_SHARPNESS_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetNR3D_EX(MI_U32 Channel, MI_ISP_IQ_NR3D_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_GetNR3D_EX(MI_U32 Channel, MI_ISP_IQ_NR3D_EX_TYPE_t *data); //[not support chip] macaron
+ MI_S32 MI_ISP_IQ_SetDUMMY(MI_U32 Channel, MI_ISP_IQ_DUMMY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDUMMY(MI_U32 Channel, MI_ISP_IQ_DUMMY_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetDUMMY_EX(MI_U32 Channel, MI_ISP_IQ_DUMMY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetDUMMY_EX(MI_U32 Channel, MI_ISP_IQ_DUMMY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetIQMode(MI_U32 Channel, MI_ISP_IQ_PARAM_MODE_e *data);
+ MI_S32 MI_ISP_IQ_GetIQMode(MI_U32 Channel, MI_ISP_IQ_PARAM_MODE_e *data);
+ MI_S32 MI_ISP_IQ_GetIQind(MI_U32 Channel, MI_ISP_IQ_INDEX_e *data);
+ MI_S32 MI_ISP_IQ_SetAPIBypassMode(MI_U32 Channel, MI_ISP_API_BYPASS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetAPIBypassMode(MI_U32 Channel, MI_ISP_API_BYPASS_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_QueryCCMInfo(MI_U32 Channel, MI_ISP_IQ_CCM_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetAdaptiveGamma(MI_U32 Channel, MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetAdaptiveGamma(MI_U32 Channel, MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_SetTEMP(MI_U32 Channel, MI_ISP_IQ_TEMP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetTEMP(MI_U32 Channel, MI_ISP_IQ_TEMP_TYPE_t *data);
+ MI_S32 MI_ISP_IQ_GetTEMP_INFO(MI_U32 Channel, MI_ISP_IQ_TEMP_INFO_TYPE_t *data);
+ /************************************* IQ API END *************************************/
+
+ /************************************* AE API START *************************************/
+ MI_S32 MI_ISP_AE_GetHistoWghtY(MI_U32 Channel, MI_ISP_AE_HIST_WEIGHT_Y_TYPE_t *data);
+ MI_S32 MI_ISP_AE_QueryExposureInfo(MI_U32 Channel, MI_ISP_AE_EXPO_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetEVComp(MI_U32 Channel, MI_ISP_AE_EV_COMP_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetEVComp(MI_U32 Channel, MI_ISP_AE_EV_COMP_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetExpoMode(MI_U32 Channel, MI_ISP_AE_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetExpoMode(MI_U32 Channel, MI_ISP_AE_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetManualExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetManualExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetManualShortExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetManualShortExpo(MI_U32 Channel, MI_ISP_AE_EXPO_VALUE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetState(MI_U32 Channel, MI_ISP_SM_STATE_TYPE_e *data); // Pause, Resume
+ MI_S32 MI_ISP_AE_GetState(MI_U32 Channel, MI_ISP_SM_STATE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetTarget(MI_U32 Channel, MI_ISP_AE_INTP_LUT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetTarget(MI_U32 Channel, MI_ISP_AE_INTP_LUT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetConverge(MI_U32 Channel, MI_ISP_AE_CONV_CONDITON_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetConverge(MI_U32 Channel, MI_ISP_AE_CONV_CONDITON_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetExposureLimit(MI_U32 Channel, MI_ISP_AE_EXPO_LIMIT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetExposureLimit(MI_U32 Channel, MI_ISP_AE_EXPO_LIMIT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetPlainLongExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetPlainLongExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetPlainShortExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetPlainShortExpoTable(MI_U32 Channel, MI_ISP_AE_EXPO_TABLE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetWinWgtType(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetWinWgtType(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_MODE_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetWinWgt(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetWinWgt(MI_U32 Channel, MI_ISP_AE_WIN_WEIGHT_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetFlicker(MI_U32 Channel, MI_ISP_AE_FLICKER_TYPE_e *data);
+ MI_S32 MI_ISP_AE_GetFlicker(MI_U32 Channel, MI_ISP_AE_FLICKER_TYPE_e *data);
+ MI_S32 MI_ISP_AE_SetFlickerEX(MI_U32 Channel, MI_ISP_AE_FLICKER_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetFlickerEX(MI_U32 Channel, MI_ISP_AE_FLICKER_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStrategy(MI_U32 Channel, MI_ISP_AE_STRATEGY_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStrategy(MI_U32 Channel, MI_ISP_AE_STRATEGY_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStrategyEX(MI_U32 Channel, MI_ISP_AE_STRATEGY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStrategyEX(MI_U32 Channel, MI_ISP_AE_STRATEGY_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetRGBIRAE(MI_U32 Channel, MI_ISP_AE_RGBIR_AE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetRGBIRAE(MI_U32 Channel, MI_ISP_AE_RGBIR_AE_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetHDR(MI_U32 Channel, MI_ISP_AE_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetHDR(MI_U32 Channel, MI_ISP_AE_HDR_TYPE_t *data);
+ MI_S32 MI_ISP_AE_SetStabilizer(MI_U32 Channel, MI_ISP_AE_STABILIZER_TYPE_t *data);
+ MI_S32 MI_ISP_AE_GetStabilizer(MI_U32 Channel, MI_ISP_AE_STABILIZER_TYPE_t *data);
+ /************************************* AE API END *************************************/
+
+ /************************************* AWB API START *************************************/
+ MI_S32 MI_ISP_AWB_QueryInfo(MI_U32 Channel, MI_ISP_AWB_QUERY_INFO_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetAttr(MI_U32 Channel, MI_ISP_AWB_ATTR_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetAttr(MI_U32 Channel, MI_ISP_AWB_ATTR_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetAttrEx(MI_U32 Channel, MI_ISP_AWB_ATTR_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetAttrEx(MI_U32 Channel, MI_ISP_AWB_ATTR_EX_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetMultiLSAttr(MI_U32 Channel, MI_ISP_AWB_MULTILS_LS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetMultiLSAttr(MI_U32 Channel, MI_ISP_AWB_MULTILS_LS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetCTWeight(MI_U32 Channel, MI_ISP_AWB_CT_WEIGHT_TYPE_t *data); //Not works now, please use MI_ISP_AWB_SetAttr to set LvWeight indstead.
+ MI_S32 MI_ISP_AWB_GetCTWeight(MI_U32 Channel, MI_ISP_AWB_CT_WEIGHT_TYPE_t *data); //Not works now, please use MI_ISP_AWB_GetAttr to set LvWeight indstead.
+
+ MI_S32 MI_ISP_AWB_SetCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCurCTCaliAttr(MI_U32 Channel, MI_ISP_AWB_CUR_CT_CALI_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetCTStats(MI_U32 Channel, MI_ISP_AWB_CT_STATISTICS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_GetHWStats(MI_U32 Channel, MI_ISP_AWB_HW_STATISTICS_TYPE_t *data);
+ MI_S32 MI_ISP_AWB_SetCTMwbAttr(MI_U32 Channel, MI_ISP_AWB_CTMWB_PARAM_t *data);
+ MI_S32 MI_ISP_AWB_GetCTMwbAttr(MI_U32 Channel, MI_ISP_AWB_CTMWB_PARAM_t *data);
+
+ /************************************* AWB API END *************************************/
+
+ /************************************* AF API START *************************************/
+ /************************************* AF API END *************************************/
+
+ MI_S32 MI_ISP_ALGO_SET_ALL(int Channel, MI_U16 ApiId, MI_U32 ApiLen, MI_U8* pApiBuf);
+ MI_S32 MI_ISP_ALGO_GET_ALL(int Channel, MI_U16 ApiId, MI_U32* ApiLen, MI_U8* pApiBuf);
+
+#endif
+
+#if 1
+
+typedef struct MI_ISP_EXCUTE_CMD_ARRAY_s
+{
+ MI_U32 u32CmdType;
+ MI_U16 u16APIID;
+ MI_S32 (*callback)(MI_U32 Channel, MI_U8 *param_ary[], MI_U8 param_num);
+} MI_ISP_EXCUTE_CMD_ARRAY_t;
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ MI_ISP_CAMERA_CMD_SET = 0,
+ MI_ISP_CAMERA_CMD_GET,
+ MI_ISP_CAMERA_CMD_SET_MODE ,
+ MI_ISP_CAMERA_CMD_GET_MODE,
+ MI_ISP_CAMERA_CMD_GET_PIC,
+ MI_ISP_CAMERA_CMD_SET_API,
+ MI_ISP_CAMERA_CMD_GET_API,
+ MI_ISP_CAMERA_CMD_UPLOAD_FILE, /* client upload file to server */
+ MI_ISP_CAMERA_CMD_DOWNLOAD_FILE, /* client download file from server*/
+} MI_ISP_CAMERA_EXT_CMD_TYPE_e;
+
+typedef struct MI_ISP_CMD_HEADER_s
+{
+ MI_ISP_CAMERA_EXT_CMD_TYPE_e CmdType;
+ MI_S32 CmdLen;
+} MI_ISP_CMD_HEADER_t;
+
+typedef struct MI_ISP_API_PARAM_s
+{
+ MI_U32 u32MagicKey;
+ MI_ISP_CMD_HEADER_t sCmdheader;
+ MI_U16 u16APIID;
+ MI_U16 u16ParamNum;
+} MI_ISP_API_PARAM_t;
+
+typedef struct MI_ISP_API_BIN_FILE_s
+{
+ MI_U32 u32FileID;
+ MI_U32 u32ISPVer;
+ MI_U32 u32DataLen;
+ MI_U32 u32Checksum;
+ MI_U32 u32MagicKey;
+ MI_U32 u32Reserved[3];
+} MI_ISP_API_BIN_FILE_t;
+
+typedef struct MI_ISP_API_CALI_FILE_s
+{
+ MI_U32 u32CaliVer;
+ MI_U32 u32DataSize;
+ MI_U32 u32Checksum;
+ MI_U32 u32Reserved[2];
+} MI_ISP_API_CALI_FILE_t;
+
+ MI_S32 MI_ISP_ALGO_API_DisableAllApi(MI_U32 Channel);
+ MI_S32 MI_ISP_ALGO_API_CmdLoadBinFile(MI_U32 Channel, MI_U8 *bindata_buf, MI_U32 user_key);
+ MI_S32 MI_ISP_ALGO_API_CmdLoadCaliData(MI_U32 Channel, MI_U8 *bindata_buf, MI_U32 BIN_BUF_MAX_LEN, MI_ISP_CALI_ITEM_e eCaliItem);
+
+#endif
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
+
+#endif //_MI_ISP_IQ_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_iq_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_iq_datatype.h
new file mode 100644
index 00000000..4d51ae64
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/mi_isp_iq_datatype.h
@@ -0,0 +1,1269 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+ * iq_apiset.h
+ *
+ * Created on: 2016/8/16
+ * Author: Elsa-cf.Lin
+ */
+
+#ifndef _MI_ISP_IQ_DATATYPE_H_
+#define _MI_ISP_IQ_DATATYPE_H_
+
+#include "mi_isp_3a_datatype.h"
+
+//put here temporarily, should add mi_isp_cali_datatype.h?
+
+typedef enum __attribute__ ((aligned (1)))
+{
+ SS_CALI_ITEM_AWB = 0,
+ SS_CALI_ITEM_OBC = 1,
+ SS_CALI_ITEM_SDC = 2,
+ SS_CALI_ITEM_ALSC = 3,
+ SS_CALI_ITEM_LSC = 4,
+ SS_CALI_ITEM_MAX,
+} MI_ISP_CALI_ITEM_e;
+
+/************************************* IQ - Define the structure declaration - START *************************************/
+
+typedef struct
+{
+ MI_U16 u16NumOfPoints;
+ MI_S32 s32Y[16];
+ MI_S32 s32X[16];
+} MI_INTP_LUT_IQ;
+
+#if 1 //API20 struct
+
+#define MI_ISP_AUTO_NUM (16)
+#define ALSC_TBL_MAX 459
+#define ENABLE_CCM_COEFF_SUM_INFO 1
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ API20_AUTO = 0, //[00]
+ //API2.0
+ API20_FPN, //[01]
+ API20_CCM, //[02]
+ API20_SAT, //[03]
+ API20_OBC, //[04]
+ API20_OBC_P1, //[05]
+ API20_FCOLOR, //[06]
+ API20_CR, //[07]
+ API20_NR_DeSpike, //[08]
+ API20_SHP, //[09]
+ API20_NR_3D, //[10]
+ API20_BRI, //[11]
+ API20_LIG, //[12]
+ API20_CST, //[13]
+ API20_GMA, //[14]
+ API20_CTG, //[15]
+ API20_NR_NLM, //[16]
+ API20_DEFOG, //[17]
+ API20_DRC, //[18]
+ API20_DPC, //[19]
+ API20_HSV, //[20]
+ API20_WDR_LOC, //[21]
+ API20_RGBIR, //[22]
+ API20_YUVGMA, //[23]
+ API20_HDR16to12, //[24]
+ API20_COLORTRANS, //[25]
+ API20_HDR, //[26]
+ API20_EFFECT, //[27]
+ API20_PFC, //[28]
+ API20_SIIR, //[29]
+ API20_DM, //[30]
+ API20_NR_3D_P1, //[31]
+ API20_WDRCurveAdv, //[32]
+ API20_MXNR, //[33]
+ API20_R2Y, //[34]
+ API20_LSC, //[35]
+ API20_LSC_CTRL, //[36]
+ API20_ALSC, //[37]
+ API20_ALSC_CTRL, //[38]
+ API20_DPC_CLUSTER, //[39]
+ API20_PFC_EX, //[40]
+ API20_HDR_EX, //[41]
+ API20_SHP_EX, //[42]
+ API20_NR_3D_EX, //[43]
+ API20_GNR, //[44]
+ API20_DUMMY, //[45]
+ API20_DUMMY_EX, //[46]
+ API20_WDRCurveFull, //[47]
+ API20_ADAPTIVE_GMA, //[48]
+ API20_XNR, //[49]
+ API20_TEMP, //[50]
+ API20_TEMP_INFO, //[51]
+ API20_MAX, //for para reset
+} MI_ISP_API_ID_e;
+
+typedef struct MI_ISP_IQ_COLORTOGRAY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+} MI_ISP_IQ_COLORTOGRAY_TYPE_t;
+
+typedef struct LEVEL_BASE_PARAM_s
+{
+ MI_U32 u32Lev; //0 ~ 100
+} LEVEL_BASE_PARAM_t;
+
+typedef struct LIGHTNESS_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} LIGHTNESS_MANUAL_ATTR_t;
+
+typedef struct LIGHTNESS_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} LIGHTNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_LIGHTNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ LIGHTNESS_AUTO_ATTR_t stAuto;
+ LIGHTNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_LIGHTNESS_TYPE_t;
+
+typedef struct CONTRAST_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} CONTRAST_MANUAL_ATTR_t;
+
+typedef struct CONTRAST_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} CONTRAST_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_CONTRAST_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ CONTRAST_AUTO_ATTR_t stAuto;
+ CONTRAST_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_CONTRAST_TYPE_t;
+
+typedef struct BRIGHTNESS_MANUAL_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI;
+} BRIGHTNESS_MANUAL_ATTR_t;
+
+typedef struct BRIGHTNESS_AUTO_ATTR_s
+{
+ LEVEL_BASE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} BRIGHTNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_BRIGHTNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; // 0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; // M_AUTO ~ (M_MODMAX-1)
+ BRIGHTNESS_AUTO_ATTR_t stAuto;
+ BRIGHTNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_BRIGHTNESS_TYPE_t;
+
+
+typedef struct RGBGAMMA_PARAM_s
+{
+ MI_U16 u16LutR[256]; //0 ~ 4095
+ MI_U16 u16LutG[256]; //0 ~ 4095
+ MI_U16 u16LutB[256]; //0 ~ 4095
+} RGBGAMMA_PARAM_t;
+
+typedef struct RGBGAMMA_MANUAL_ATTR_s
+{
+ RGBGAMMA_PARAM_t stParaAPI;
+} RGBGAMMA_MANUAL_ATTR_t;
+
+typedef struct RGBGAMMA_AUTO_ATTR_s
+{
+ RGBGAMMA_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBGAMMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBGAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBGAMMA_AUTO_ATTR_t stAuto;
+ RGBGAMMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBGAMMA_TYPE_t;
+
+typedef struct YUVGAMMA_PAMAR_s
+{
+ MI_U16 u16LutY[256]; //0 ~ 1023
+ MI_U16 u16LutU[128]; //0 ~ 511
+ MI_U16 u16LutV[128]; //0 ~ 511
+} YUVGAMMA_PAMAR_t;
+
+typedef struct YUVGAMMA_MANUAL_ATTR_s
+{
+ YUVGAMMA_PAMAR_t stParaAPI;
+} YUVGAMMA_MANUAL_ATTR_t;
+
+typedef struct YUVGAMMA_AUTO_ATTR_s
+{
+ YUVGAMMA_PAMAR_t stParaAPI[MI_ISP_AUTO_NUM];
+} YUVGAMMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_YUVGAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ YUVGAMMA_AUTO_ATTR_t stAuto;
+ YUVGAMMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_YUVGAMMA_TYPE_t;
+
+typedef struct SATURATION_PARAM_s
+{
+ MI_U8 u8SatAllStr; //0 ~ 127 (32 = 1X)
+ MI_U8 u8SatByYSFTAdv[5]; //0 ~ 8
+ MI_U8 u8SatByYLUTAdv[6]; //0 ~ 128
+ MI_U8 u8SatBySSFTAdv[5]; //0 ~ 8
+ MI_U8 u8SatBySLUTAdv[6]; //0 ~ 128
+ MI_U8 u8SatCoring;
+} SATURATION_PARAM_t;
+
+typedef struct SATURATION_MANUAL_ATTR_s
+{
+ SATURATION_PARAM_t stParaAPI;
+} SATURATION_MANUAL_ATTR_t;
+
+typedef struct SATURATION_AUTO_ATTR_s
+{
+ SATURATION_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} SATURATION_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_SATURATION_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ SATURATION_AUTO_ATTR_t stAuto;
+ SATURATION_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SATURATION_TYPE_t;
+
+typedef struct DEFOG_PARAM_s
+{
+ MI_U8 u8Strength;
+} DEFOG_PARAM_t;
+
+typedef struct DEFOG_MANUAL_ATTR_s
+{
+ DEFOG_PARAM_t stParaAPI;
+} DEFOG_MANUAL_ATTR_t;
+
+typedef struct DEFOG_AUTO_ATTR_s
+{
+ DEFOG_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} DEFOG_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DEFOG_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DEFOG_AUTO_ATTR_t stAuto;
+ DEFOG_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DEFOG_TYPE_t;
+
+typedef struct RGBMATRIX_PARAM_s
+{
+ MI_U16 u16CCTthr;
+#if ENABLE_CCM_COEFF_SUM_INFO
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+#else
+ MI_U16 u16CCM[9]; //0 ~ 8191(1024 = 1X)
+#endif
+ MI_U8 u8CCMSat; //0 ~ 100 0:Unit matrix, 100:User matrix
+} RGBMATRIX_PARAM_t;
+
+typedef struct RGBMATRIX_MANUAL_ATTR_s
+{
+#if ENABLE_CCM_COEFF_SUM_INFO
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+#else
+ MI_U16 u16CCM[9]; //0 ~ 8191(1024 = 1X)
+#endif
+ MI_U8 u8CCMSat; //0 ~ 100 0:Unit matrix, 100:User matrix
+} RGBMATRIX_MANUAL_ATTR_t;
+
+typedef struct RGBMATRIX_AUTO_ATTR_s
+{
+ MI_ISP_BOOL_e bISOActEn; //0 ~ 1
+ RGBMATRIX_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBMATRIX_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBMATRIX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBMATRIX_AUTO_ATTR_t stAuto;
+ RGBMATRIX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBMATRIX_TYPE_t;
+
+typedef struct MI_ISP_IQ_CCM_INFO_TYPE_s
+{
+ MI_U16 u16CCM[12]; //0 ~ 8191(1024 = 1X)
+ MI_U16 u16CCT;
+} MI_ISP_IQ_CCM_INFO_TYPE_t;
+
+typedef struct FALSECOLOR_PARAM_s
+{
+ MI_U8 u8FreqThrd; //0~255 default:140
+ MI_U8 u8EdgeScoreThrd; //0~255 default:31
+ MI_U8 u8ChromaThrdOfStrengthMax; //0~127 default:10
+ MI_U8 u8ChromaThrdOfStrengthMid; //0~127 default:40
+ MI_U8 u8ChromaThrdOfStrengthMin; //0~127 default:80
+ MI_U8 u8StrengthMid; //0~7 default:7
+ MI_U8 u8StrengthMin; //0~7 default:7
+} FALSECOLOR_PARAM_t;
+
+typedef struct FALSECOLOR_MANUAL_ATTR_s
+{
+ FALSECOLOR_PARAM_t stParaAPI;
+} FALSECOLOR_MANUAL_ATTR_t;
+
+typedef struct FALSECOLOR_AUTO_ATTR_s
+{
+ FALSECOLOR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} FALSECOLOR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_FALSECOLOR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ FALSECOLOR_AUTO_ATTR_t stAuto;
+ FALSECOLOR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_FALSECOLOR_TYPE_t;
+
+typedef struct NR3D_PARAM_s
+{
+ MI_U8 u8MdThd; //0~255
+ MI_U16 u16MdGain; //0~1023
+ MI_U8 u8TfStr; //0~64
+ MI_U8 u8TfStrEx; //0~64
+ MI_U8 u8MdThdByY[16]; //0~255
+ MI_U8 u8MdGainByY[16]; //0~255
+ MI_U8 u8M2SLut[16]; //0~31
+ MI_U16 u16TfLut[16]; //0~4095
+ MI_U8 u8YSfBlendLut[16]; //0~16
+ MI_U8 u8YSfBlendOffset; //0~16
+} NR3D_PARAM_t;
+
+typedef struct NR3D_MANUAL_ATTR_s
+{
+ NR3D_PARAM_t stParaAPI;
+} NR3D_MANUAL_ATTR_t;
+
+typedef struct NR3D_AUTO_ATTR_s
+{
+ NR3D_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NR3D_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NR3D_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NR3D_AUTO_ATTR_t stAuto;
+ NR3D_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NR3D_TYPE_t;
+
+typedef struct NR3D_EX_PARAM_s
+{
+ MI_ISP_BOOL_e bAREn; //0~1
+ MI_U8 u8ARLumaTh[2]; //0~255
+ MI_U8 u8ARMotTh[2]; //0~255
+ MI_ISP_BOOL_e bPREn; //0~1
+ MI_U16 u16PRDiffTh; //0~4095
+ MI_U8 u8PRRatioConf[4]; //0~16
+ MI_U8 u8PRContrastTh[2]; //0~15
+ MI_U8 u8PRMotTh[2]; //0~255
+} NR3D_EX_PARAM_t;
+
+typedef struct NR3D_EX_MANUAL_ATTR_s
+{
+ NR3D_EX_PARAM_t stParaAPI;
+} NR3D_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_NR3D_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ NR3D_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NR3D_EX_TYPE_t;
+
+typedef struct MI_ISP_IQ_NR3D_P1_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NR3D_P1_TYPE_t;
+
+typedef struct NRDESPIKE_PARAM_s
+{
+ MI_U8 u8BlendRatio; //0 ~ 15
+ MI_U8 u8StrengthCenterNeighbor; //0 ~ 5
+ MI_U8 u8StrengthMeanStd; //0 ~ 5
+ MI_U8 u8StrengthCornerCross; //0 ~ 5
+ MI_U8 u8DiffGainMeanStd; //0 ~ 31
+ MI_U8 u8DiffGainCenterNeighbor; //0 ~ 255
+ MI_U8 u8DiffThdCornerCross; //0 ~ 255
+ MI_U16 u16BlendLut[5]; //0 ~ 2047
+ MI_U8 u8StrengthByY[15]; //0 ~ 127
+} NRDESPIKE_PARAM_t;
+
+typedef struct NRDESPIKE_MANUAL_ATTR_s
+{
+ NRDESPIKE_PARAM_t stParaAPI;
+} NRDESPIKE_MANUAL_ATTR_t;
+
+typedef struct NRDESPIKE_AUTO_ATTR_s
+{
+ NRDESPIKE_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRDESPIKE_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRDESPIKE_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRDESPIKE_AUTO_ATTR_t stAuto;
+ NRDESPIKE_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRDESPIKE_TYPE_t;
+
+typedef struct NRLUMA_PARAM_s
+{
+ MI_U8 u8Strength;
+ MI_U8 u8GMaskSel;
+ MI_U16 u16SpfBlendLut[2];
+} NRLUMA_PARAM_t;
+
+typedef struct NRLUMA_MANUAL_ATTR_s
+{
+ NRLUMA_PARAM_t stParaAPI;
+} NRLUMA_MANUAL_ATTR_t;
+
+typedef struct NRLUMA_AUTO_ATTR_s
+{
+ NRLUMA_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRLUMA_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRLUMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRLUMA_AUTO_ATTR_t stAuto;
+ NRLUMA_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRLUMA_TYPE_t;
+
+typedef struct NRLUMA_Adv_PARAM_s
+{
+ MI_ISP_BOOL_e bDbgEn;
+ MI_U8 u8Strength;
+ MI_U8 u8StrengthByY[10];
+ MI_U8 u8StrengthByMot[16];
+ MI_U16 u16EdgeTh[8];
+ MI_U32 u32EdgeGain[8];
+ MI_U8 u8StrengthByType[2];
+} NRLUMA_Adv_PARAM_t;
+
+typedef struct NRLUMA_Adv_MANUAL_ATTR_s
+{
+ NRLUMA_Adv_PARAM_t stParaAPI;
+} NRLUMA_Adv_MANUAL_ATTR_t;
+
+typedef struct NRLUMA_Adv_AUTO_ATTR_s
+{
+ NRLUMA_Adv_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRLUMA_Adv_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRLuma_Adv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRLUMA_Adv_AUTO_ATTR_t stAuto;
+ NRLUMA_Adv_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRLuma_Adv_TYPE_t;
+
+typedef struct NRChroma_PARAM_s
+{
+ MI_U8 u8MatchRatio; //0 ~ 127
+ MI_U16 u16UvTh; //0 ~ 1023
+ MI_U16 u16StrengthByCEdge[6]; //0 ~ 1023
+} NRChroma_PARAM_t;
+
+typedef struct NRChroma_MANUAL_ATTR_s
+{
+ NRChroma_PARAM_t stParaAPI;
+} NRChroma_MANUAL_ATTR_t;
+
+typedef struct NRChroma_AUTO_ATTR_s
+{
+ NRChroma_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRChroma_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRChroma_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRChroma_AUTO_ATTR_t stAuto;
+ NRChroma_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRChroma_TYPE_t;
+
+typedef struct NRChroma_Adv_PARAM_s
+{
+ MI_U8 u8StrengthByY[8]; //0 ~ 255
+ MI_U8 u8StrengthByYEdge[8]; //0 ~ 63
+ MI_U8 u8StrengthByCEdge[8]; //0 ~ 255
+ MI_U8 u8MaxStrength; //0 ~ 255
+ MI_U8 u8StaticLimitRatio; //0 ~ 63
+ MI_U8 u8MotionClip; //0 ~ 255
+ MI_U8 u8MotionColorReduce; //0 ~ 255
+ MI_U8 u8MotionColorRecover; //0 ~ 255
+ MI_U8 u8PreStrength; //0 ~ 128
+} NRChroma_Adv_PARAM_t;
+
+typedef struct NRChroma_Adv_MANUAL_ATTR_s
+{
+ NRChroma_Adv_PARAM_t stParaAPI;
+} NRChroma_Adv_MANUAL_ATTR_t;
+
+typedef struct NRChroma_Adv_AUTO_ATTR_s
+{
+ NRChroma_Adv_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} NRChroma_Adv_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_NRChroma_Adv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ NRChroma_Adv_AUTO_ATTR_t stAuto;
+ NRChroma_Adv_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_NRChroma_Adv_TYPE_t;
+
+typedef struct MI_ISP_IQ_NRChroma_Pre_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_NRChroma_Pre_TYPE_t;
+
+typedef struct SHARPNESS_PARAM_s
+{
+ MI_U8 u8OverShootGain; //0 ~ 255
+ MI_U8 u8UnderShootGain; //0 ~ 255
+ MI_U8 u8CorLUT[6]; //0 ~ 255
+ MI_U8 u8SclLUT[6]; //0 ~ 255
+ MI_U16 u16EdgeKillLUT[6]; //0 ~ 1023
+ MI_U8 u8CornerReduce; //0 ~ 32
+ MI_U8 u8DirTh; //0 ~ 255
+ MI_U16 u16SharpnessUD[2]; //0 ~ 1023
+ MI_U16 u16SharpnessD[2]; //0 ~ 1023
+ MI_U8 u8PreCorUD[2]; //0 ~ 63
+ MI_U8 u8PreCorD[2]; //0 ~ 63
+ MI_U8 u8PreCorMotGain; //0 ~ 255
+ MI_U8 u8LpfEdgeGainUD; //0 ~ 255
+ MI_U8 u8LpfEdgeGainD; //0 ~ 255
+ MI_U8 u8WeakDetailEnhance; //0 ~ 15
+ MI_U16 u16DetailTh; //0 ~ 4095
+ MI_U8 u8DetailMotOffset; //0 ~ 255
+ MI_U8 u8DetailByY[6]; //0 ~ 255
+ MI_U16 u16OverShootLimit; //0 ~ 1023
+ MI_U16 u16UnderShootLimit; //0 ~ 1023
+ MI_U8 u8MotGain[16]; //0 ~ 255
+} SHARPNESS_PARAM_t;
+
+typedef struct SHARPNESS_MANUAL_ATTR_s
+{
+ SHARPNESS_PARAM_t stParaAPI;
+} SHARPNESS_MANUAL_ATTR_t;
+
+typedef struct SHARPNESS_AUTO_ATTR_s
+{
+ SHARPNESS_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} SHARPNESS_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_SHARPNESS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ SHARPNESS_AUTO_ATTR_t stAuto;
+ SHARPNESS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SHARPNESS_TYPE_t;
+
+typedef struct SHARPNESS_EX_PARAM_s
+{
+ MI_ISP_BOOL_e bDbgEn; //0 ~ 1
+ MI_U8 u8DirSel; //0 ~ 1
+ MI_U8 u8DirOffA; //0 ~ 255
+ MI_U8 u8MaxRatio; //0 ~ 255
+ MI_U8 u8LpfY; //0 ~ 1
+ MI_U8 u8SblLutY[6]; //0 ~ 255
+ MI_U8 u8Sbl2LutY[6]; //0 ~ 255
+ MI_U8 u8StrengthByHue[24]; //0 ~ 255
+} SHARPNESS_EX_PARAM_t;
+
+typedef struct SHARPNESS_EX_MANUAL_ATTR_s
+{
+ SHARPNESS_EX_PARAM_t stParaAPI;
+} SHARPNESS_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_SHARPNESS_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ SHARPNESS_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_SHARPNESS_EX_TYPE_t;
+
+typedef struct CROSSTALK_PARAM_s
+{
+ MI_U8 u8Strength; //0 ~ 31
+ MI_U8 u8StrengthByY[15]; //0 ~ 127
+ MI_U8 u8Threshold; //0 ~ 255
+ MI_U16 u16Offset; //0 ~ 4095
+} CROSSTALK_PARAM_t;
+
+typedef struct CROSSTALK_MANUAL_ATTR_s
+{
+ CROSSTALK_PARAM_t stParaAPI;
+} CROSSTALK_MANUAL_ATTR_t;
+
+typedef struct CROSSTALK_AUTO_ATTR_s
+{
+ CROSSTALK_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} CROSSTALK_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_CROSSTALK_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ CROSSTALK_AUTO_ATTR_t stAuto;
+ CROSSTALK_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_CROSSTALK_TYPE_t;
+
+typedef struct OBC_PARAM_s
+{
+ MI_U16 u16ValR; //0 ~ 255
+ MI_U16 u16ValGr; //0 ~ 255
+ MI_U16 u16ValGb; //0 ~ 255
+ MI_U16 u16ValB; //0 ~ 255
+} OBC_PARAM_t;
+
+typedef struct OBC_MANUAL_ATTR_s
+{
+ OBC_PARAM_t stParaAPI;
+} OBC_MANUAL_ATTR_t;
+
+typedef struct OBC_AUTO_ATTR_s
+{
+ OBC_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} OBC_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_OBC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ OBC_AUTO_ATTR_t stAuto;
+ OBC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_OBC_TYPE_t;
+
+typedef struct WDR_PARAM_s
+{
+ MI_U8 u8BoxNum; //1 ~ 4
+ MI_U8 u8PreEnhance; //0 ~ 6
+ MI_ISP_BOOL_e bAutoDetailEnhance; //0 ~ 1
+ MI_U8 u8ManualDetailEnhance; //0~255; default:128
+ MI_U8 u8GlobalDarkToneEnhance; //0 ~ 15
+ MI_U8 u8WDRStrByY[33]; //0 ~ 255
+ MI_U8 u8Strength; //0 ~ 255
+ MI_U8 u8DarkLimit; //0 ~ 255
+ MI_U8 u8BrightLimit; //0 ~ 255
+ MI_ISP_BOOL_e bGammaSyncEn; //0 ~ 1
+} WDR_PARAM_t;
+
+typedef struct WDR_MANUAL_ATTR_s
+{
+ WDR_PARAM_t stParaAPI;
+} WDR_MANUAL_ATTR_t;
+
+typedef struct WDR_AUTO_ATTR_s
+{
+ WDR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDR_AUTO_ATTR_t stAuto;
+ WDR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDR_TYPE_t;
+
+typedef struct WDRCurveFull_PARAM_s
+{
+ MI_U16 u16FCurve[256];
+} WDRCurveFull_PARAM_t;
+
+typedef struct WDRCurveFull_MANUAL_ATTR_s
+{
+ WDRCurveFull_PARAM_t stParaAPI;
+} WDRCurveFull_MANUAL_ATTR_t;
+
+typedef struct WDRCurveFull_AUTO_ATTR_s
+{
+ WDRCurveFull_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDRCurveFull_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDRCurveFull_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDRCurveFull_AUTO_ATTR_t stAuto;
+ WDRCurveFull_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDRCurveFull_TYPE_t;
+
+typedef struct WDRCurveAdv_PARAM_s
+{
+ MI_U16 u16Slope; //1024~16384
+ MI_U8 u8TransitionPoint0; //0~255
+ MI_U8 u8TransitionPoint1; //0~255
+ MI_U8 u8SaturatedPoint; //0~255
+ MI_U8 u8CurveModeSel; //0~5
+} WDRCurveAdv_PARAM_t;
+
+typedef struct WDRCurveAdv_MANUAL_ATTR_s
+{
+ WDRCurveAdv_PARAM_t stParaAPI;
+} WDRCurveAdv_MANUAL_ATTR_t;
+
+typedef struct WDRCurveAdv_AUTO_ATTR_s
+{
+ WDRCurveAdv_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} WDRCurveAdv_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_WDRCurveAdv_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ WDRCurveAdv_AUTO_ATTR_t stAuto;
+ WDRCurveAdv_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_WDRCurveAdv_TYPE_t;
+
+typedef struct DYNAMIC_DP_PARAM_s
+{
+ MI_ISP_BOOL_e bHotPixEn; //0 ~ 1
+ MI_U16 u16HotPixCompSlpoe;
+ MI_ISP_BOOL_e bDarkPixEn; //0 ~ 1
+ MI_U16 u16DarkPixCompSlpoe;
+ MI_U16 u16DPCTH;
+ MI_ISP_BOOL_e bBlendEn;
+ MI_U16 u16DiffLut[6];
+ MI_U16 u16YLut[6];
+} DYNAMIC_DP_PARAM_t;
+
+typedef struct DYNAMIC_DP_MANUAL_ATTR_s
+{
+ DYNAMIC_DP_PARAM_t stParaAPI;
+} DYNAMIC_DP_MANUAL_ATTR_t;
+
+typedef struct DYNAMIC_DP_AUTO_ATTR_s
+{
+ DYNAMIC_DP_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} DYNAMIC_DP_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DYNAMIC_DP_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DYNAMIC_DP_AUTO_ATTR_t stAuto;
+ DYNAMIC_DP_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DYNAMIC_DP_TYPE_t;
+
+typedef struct DYNAMIC_DP_CLUSTER_ATTR_S
+{
+ MI_ISP_BOOL_e bEdgeMode;
+ MI_U16 u16NeiDeltaTh;
+ MI_U8 u8NeiSmooth;
+ MI_ISP_BOOL_e bSortEn;
+ MI_ISP_BOOL_e bSortRGGBEn[4];
+ MI_ISP_BOOL_e bSort1x3ModeEn;
+ MI_U16 u16SortLumTblL[6];
+ MI_U16 u16SortLumTblD[6];
+ MI_U16 u16SortLumTblS[6];
+} DYNAMIC_DP_CLUSTER_ATTR_S;
+
+typedef struct
+{
+ DYNAMIC_DP_CLUSTER_ATTR_S stParaAPI;
+} DYNAMIC_DP_CLUSTER_MANUAL_ATTR_S;
+
+typedef struct
+{
+ DYNAMIC_DP_CLUSTER_ATTR_S stParaAPI[MI_ISP_AUTO_NUM];
+} DYNAMIC_DP_CLUSTER_AUTO_ATTR_S;
+
+typedef struct MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ DYNAMIC_DP_CLUSTER_AUTO_ATTR_S stAuto;
+ DYNAMIC_DP_CLUSTER_MANUAL_ATTR_S stManual;
+} MI_ISP_IQ_DYNAMIC_DP_CLUSTER_TYPE_t;
+
+typedef struct HSV_PARAM_s
+{
+ MI_S16 s16HueLut[24]; //-64 ~ 64
+ MI_U16 u16SatLut[24]; // 0 ~ 255 (64->1X)
+ MI_S16 s16HueLut_ForUnitCCM[24]; //-64 ~ 64
+ MI_U16 u16SatLut_ForUnitCCM[24]; // 0 ~ 255 (64->1X)
+ MI_U8 u8GlobalSat; // 0 ~ 255 (64->1x)
+} HSV_PARAM_t;
+
+typedef struct HSV_MANUAL_ATTR_s
+{
+ HSV_PARAM_t stParaAPI;
+} HSV_MANUAL_ATTR_t;
+
+typedef struct HSV_AUTO_ATTR_s
+{
+ HSV_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} HSV_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_HSV_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ HSV_AUTO_ATTR_t stAuto;
+ HSV_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HSV_TYPE_t;
+
+typedef struct RGBIR_PARAM_s
+{
+ MI_U8 u8IrPosType; //0 ~ 7, def : 0
+ MI_ISP_BOOL_e bRemovelEn; //0 ~ 1, def : 1
+ MI_U16 u16Ratio_R[6];
+ MI_U16 u16Ratio_G[6];
+ MI_U16 u16Ratio_B[6];
+} RGBIR_PARAM_t;
+
+typedef struct RGBIR_MANUAL_ATTR_s
+{
+ RGBIR_PARAM_t stParaAPI;
+} RGBIR_MANUAL_ATTR_t;
+
+typedef struct RGBIR_AUTO_ATTR_s
+{
+ RGBIR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} RGBIR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_RGBIR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ RGBIR_AUTO_ATTR_t stAuto;
+ RGBIR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_RGBIR_TYPE_t;
+
+typedef struct MI_ISP_IQ_FPN_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_FPN_TYPE_t;
+
+typedef struct PFC_PARAM_s
+{
+ MI_U8 u8Strength; //0 ~ 255
+ MI_U8 u8UStrength; //0 ~ 63
+ MI_U8 u8VStrength; //0 ~ 63
+ MI_U8 u8StrengthByY[8]; //0 ~ 255
+ MI_U8 u8FlatProtect; //0 ~ 127
+ MI_U8 u8SatByY[2]; //0 ~ 25
+ MI_U8 u8SatSrcSel; //0 ~ 1
+ MI_U8 u8StrengthByContrast[8]; //0 ~ 127
+} PFC_PARAM_t;
+
+typedef struct PFC_MANUAL_ATTR_s
+{
+ PFC_PARAM_t stParaAPI;
+} PFC_MANUAL_ATTR_t;
+
+typedef struct PFC_AUTO_ATTR_s
+{
+ PFC_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} PFC_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_PFC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ PFC_AUTO_ATTR_t stAuto;
+ PFC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_PFC_TYPE_t;
+
+typedef struct PFC_EX_PARAM_s
+{
+ MI_ISP_BOOL_e bDbgEn; //0 ~ 1
+ MI_ISP_BOOL_e bGSkipEn; //0 ~ 1
+ MI_U8 u8SatMaskSel; //0 ~ 1
+ MI_ISP_BOOL_e bSatAmpEn; //0 ~ 1
+ MI_U8 u8StrengthByHue[12]; //0 ~ 255
+} PFC_EX_PARAM_t;
+
+typedef struct PFC_EX_MANUAL_ATTR_s
+{
+ PFC_EX_PARAM_t stParaAPI;
+} PFC_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_PFC_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ PFC_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_PFC_EX_TYPE_t;
+
+typedef struct DEMOSAIC_PARAM_s
+{
+ MI_U8 u8DirThrd; //0~63 def:35
+ MI_U8 u8EdgeSmoothThrdY; //0~255 def:230
+ MI_U8 u8EdgeSmoothThrdC; //0~127 def:20
+} DEMOSAIC_PARAM_t;
+
+typedef struct DEMOSAIC_MANUAL_ATTR_s
+{
+ DEMOSAIC_PARAM_t stParaAPI;
+} DEMOSAIC_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_DEMOSAIC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ DEMOSAIC_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DEMOSAIC_TYPE_t;
+
+typedef struct COLORTRANS_PARAM_s
+{
+ MI_U16 u16Y_OFST; //0 ~ 2047
+ MI_U16 u16U_OFST; //0 ~ 2047
+ MI_U16 u16V_OFST; //0 ~ 2047
+ MI_U16 u16Matrix[9]; //0 ~ 1023
+} COLORTRANS_PARAM_t;
+
+typedef struct COLORTRANS_MANUAL_ATTR_s
+{
+ COLORTRANS_PARAM_t stParaAPI;
+} COLORTRANS_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_COLORTRANS_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ COLORTRANS_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_COLORTRANS_TYPE_t;
+
+typedef struct HDR_PARAM_s
+{
+ MI_ISP_BOOL_e bNrEn;
+ MI_U16 u16YwtTh1;
+ MI_U16 u16YwtTh2;
+ MI_U16 u16NoiseLevel[16];
+ MI_U16 u16MotionTh;
+ MI_U16 u16MotionAdjLut[7];
+} HDR_PARAM_t;
+
+typedef struct HDR_MANUAL_ATTR_s
+{
+ HDR_PARAM_t stParaAPI;
+} HDR_MANUAL_ATTR_t;
+
+typedef struct HDR_AUTO_ATTR_s
+{
+ HDR_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} HDR_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_HDR_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ HDR_AUTO_ATTR_t stAuto;
+ HDR_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HDR_TYPE_t;
+
+typedef struct HDR_EX_PARAM_s
+{
+ MI_U16 u16SensorExpRatio;
+ MI_ISP_BOOL_e bDynRatioEn;
+ MI_U8 u8DynRatioSrcSel;
+ MI_U8 u8YSrcSel;
+ MI_U8 u8NoiseLevelSrcSel;
+ MI_U8 u8MotionMaxVal;
+ MI_U16 u16MotionLumaTh;
+ MI_U8 u8MotionAdjSft[6];
+} HDR_EX_PARAM_t;
+
+typedef struct HDR_EX_MANUAL_ATTR_s
+{
+ HDR_EX_PARAM_t stParaAPI;
+} HDR_EX_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_HDR_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ HDR_EX_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_HDR_EX_TYPE_t;
+
+typedef struct MI_ISP_IQ_EFFECT_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_EFFECT_TYPE_t;
+
+typedef struct MI_ISP_IQ_SYS_MCNR_MEMORY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+} MI_ISP_IQ_SYS_MCNR_MEMORY_TYPE_t;
+
+typedef struct MI_ISP_IQ_LSC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U16 u16CenterX;
+ MI_U16 u16CenterY;
+ MI_U8 u8Shift;
+ MI_U16 u16RGainTable[32*3];
+ MI_U16 u16GGainTable[32*3];
+ MI_U16 u16BGainTable[32*3];
+} MI_ISP_IQ_LSC_TYPE_t;
+
+typedef struct MI_ISP_IQ_LSC_CTRL_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8RRatioByCct[3];
+ MI_U8 u8GRatioByCct[3];
+ MI_U8 u8BRatioByCct[3];
+ MI_INTP_LUT_IQ RatioByBv;
+} MI_ISP_IQ_LSC_CTRL_TYPE_t;
+
+typedef struct MI_ISP_IQ_ALSC_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8GridX;
+ MI_U8 u8GridY;
+ MI_U16 u16CCTthr[3];
+ MI_U8 u8DeltaMode;
+ MI_ISP_BOOL_e bDeltaModeAdvEn;
+ MI_U8 u8DeltaLutX[26];
+ MI_U8 u8DeltaLutY[26];
+ MI_U16 u16TableR[3][ALSC_TBL_MAX];
+ MI_U16 u16TableG[3][ALSC_TBL_MAX];
+ MI_U16 u16TableB[3][ALSC_TBL_MAX];
+} MI_ISP_IQ_ALSC_TYPE_t;
+
+typedef struct MI_ISP_IQ_ALSC_CTRL_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8RRatioByCct[3];
+ MI_U8 u8GRatioByCct[3];
+ MI_U8 u8BRatioByCct[3];
+ MI_INTP_LUT_IQ RatioByBv;
+} MI_ISP_IQ_ALSC_CTRL_TYPE_t;
+
+typedef struct R2Y_PARAM_s
+{
+ MI_U16 u16Matrix[9];
+ MI_U8 u8AddY16;
+} R2Y_PARAM_t;
+
+typedef struct R2Y_MANUAL_ATTR_s
+{
+ R2Y_PARAM_t stParaAPI;
+} R2Y_MANUAL_ATTR_t;
+
+typedef struct MI_ISP_IQ_R2Y_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ R2Y_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_R2Y_TYPE_t;
+
+typedef struct DUMMY_ATTR_s
+{
+ MI_S16 s16Dummy0[256];
+ MI_S16 s16Dummy1[256];
+ MI_S16 s16Dummy2[256];
+ MI_S16 s16Dummy3;
+ MI_S16 s16Dummy4;
+} DUMMY_ATTR_t;
+
+typedef struct DUMMY_MANUAL_ATTR_s
+{
+ DUMMY_ATTR_t stParaAPI;
+} DUMMY_MANUAL_ATTR_t;
+
+typedef struct DUMMY_AUTO_ATTR_s
+{
+ DUMMY_ATTR_t stParaAPI[MI_ISP_AUTO_NUM];
+} DUMMY_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_DUMMY_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_ISP_OP_TYPE_e enOpType; //OP_TYP_AUTO ~ (OP_TPY_MODMAX-1)
+ DUMMY_AUTO_ATTR_t stAuto;
+ DUMMY_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_DUMMY_TYPE_t;
+
+typedef struct DUMMY_EX_ATTR_s
+{
+ MI_S16 s16DummyEx0[256];
+ MI_S16 s16DummyEx1[256];
+ MI_S16 s16DummyEx2[256];
+ MI_S16 s16DummyEx3;
+ MI_S16 s16DummyEx4;
+} DUMMY_EX_ATTR_t;
+
+typedef struct
+{
+ DUMMY_EX_ATTR_t stParaAPI;
+} DUMMY_EX_MANUAL_ATTR_S;
+
+typedef struct MI_ISP_IQ_DUMMY_EX_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ DUMMY_EX_MANUAL_ATTR_S stManual;
+} MI_ISP_IQ_DUMMY_EX_TYPE_t;
+
+#endif
+
+#if 1 // ISP IQ API
+typedef struct IQ_VERSION_INFO_PARAM_s
+{
+ MI_U32 u32Vendor;
+ MI_U32 u32Major;
+ MI_U32 u32Minor;
+} IQ_VERSION_INFO_PARAM_t;
+
+typedef struct MI_ISP_IQ_VERSION_INFO_TYPE_s
+{
+ IQ_VERSION_INFO_PARAM_t stParaAPI;
+} MI_ISP_IQ_VERSION_INFO_TYPE_t;
+
+typedef struct IQ_PARAM_INIT_INFO_PARAM_s
+{
+ MI_ISP_BOOL_e bFlag;
+} IQ_PARAM_INIT_INFO_PARAM_t;
+
+typedef struct MI_ISP_IQ_PARAM_INIT_INFO_TYPE_s
+{
+ IQ_PARAM_INIT_INFO_PARAM_t stParaAPI;
+} MI_ISP_IQ_PARAM_INIT_INFO_TYPE_t;
+
+typedef struct FAST_MODE_PARAM_s
+{
+ MI_ISP_BOOL_e bFastMode;
+} FAST_MODE_PARAM_t;
+
+typedef struct MI_ISP_IQ_FAST_MODE_TYPE_s
+{
+ FAST_MODE_PARAM_t stParaAPI;
+} MI_ISP_IQ_FAST_MODE_TYPE_t;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_IQ_PARAM_MODE_NORMAL = 0,
+ SS_IQ_PARAM_MODE_NIGHT = 1, //Night Mode
+ SS_IQ_PARAM_MODE_MAX
+} MI_ISP_IQ_PARAM_MODE_e;
+
+typedef struct MI_ISP_IQ_GAMMA_LUT_TYPE_s
+{
+ MI_U16 u16LutR[256];
+ MI_U16 u16LutG[256];
+ MI_U16 u16LutB[256];
+} MI_ISP_IQ_GAMMA_LUT_TYPE_t;
+
+typedef struct MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable;
+ MI_U16 u16BTGamma[256];
+ MI_U16 u16DTGamma[256];
+} MI_ISP_IQ_ADAPTIVE_GAMMA_TYPE_t;
+
+typedef struct MI_ISP_IQ_OBC4Ch_TYPE_s
+{
+ MI_U16 u16OBC4Ch[4];
+} MI_ISP_IQ_OBC4Ch_TYPE_t;
+#endif
+
+typedef struct TEMP_PARAM_s
+{
+ MI_S16 s16ObcOffset;
+ MI_U8 u8DynamicDPRatio;
+ MI_U8 u8CrosstalkRatio;
+ MI_U8 u8NRDeSpikeRatio;
+ MI_U8 u8NR3DRatio[2];
+ MI_U8 u8NRLumaRatio;
+ MI_U8 u8SharpnessRatio[2];
+ MI_U8 u8SaturationRatio;
+ MI_U8 u8ColorToneRatio[3];
+} TEMP_PARAM_t;
+
+typedef struct TEMP_MANUAL_ATTR_s
+{
+ TEMP_PARAM_t stParaAPI;
+} TEMP_MANUAL_ATTR_t;
+
+typedef struct TEMP_AUTO_ATTR_s
+{
+ TEMP_PARAM_t stParaAPI[MI_ISP_AUTO_NUM];
+} TEMP_AUTO_ATTR_t;
+
+typedef struct MI_ISP_IQ_TEMP_TYPE_s
+{
+ MI_ISP_BOOL_e bEnable; //0 ~ 1
+ MI_U8 u8TemperatureLut[16];
+ MI_ISP_OP_TYPE_e enOpType; //M_AUTO ~ (M_MODMAX-1)
+ TEMP_AUTO_ATTR_t stAuto;
+ TEMP_MANUAL_ATTR_t stManual;
+} MI_ISP_IQ_TEMP_TYPE_t;
+
+typedef struct MI_ISP_IQ_TEMP_INFO_TYPE_s
+{
+ MI_U8 u8Temperature;
+} MI_ISP_IQ_TEMP_INFO_TYPE_t;
+
+#if 1 // MAINTOOL API
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_IQ_INDEX_0 = 0,
+ SS_IQ_INDEX_1,
+ SS_IQ_INDEX_2,
+ SS_IQ_INDEX_3,
+ SS_IQ_INDEX_4,
+ SS_IQ_INDEX_5,
+ SS_IQ_INDEX_6,
+ SS_IQ_INDEX_7,
+ SS_IQ_INDEX_8,
+ SS_IQ_INDEX_9,
+ SS_IQ_INDEX_10,
+ SS_IQ_INDEX_11,
+ SS_IQ_INDEX_12,
+ SS_IQ_INDEX_13,
+ SS_IQ_INDEX_14,
+ SS_IQ_INDEX_15,
+ SS_IQ_INDEX_MAX
+} MI_ISP_IQ_INDEX_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_BYPASS_OFF = 0,
+ SS_BYPASS_ON,
+ SS_BYPASS_MAX
+} MI_ISP_BYPASS_MODE_e;
+
+typedef struct MI_ISP_API_BYPASS_TYPE_s
+{
+ MI_ISP_BYPASS_MODE_e bEnable; //0 ~ 1
+ MI_ISP_API_ID_e eAPIIndex;
+} MI_ISP_API_BYPASS_TYPE_t;
+#endif
+
+
+/************************************* IQ - Define the structure declaration - END *************************************/
+
+
+#endif /* _MI_ISP_IQ_DATATYPE_H_ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_3a_if.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_3a_if.h
new file mode 100644
index 00000000..72d0f60d
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_3a_if.h
@@ -0,0 +1,594 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef ISP_3A_IF_H
+#define ISP_3A_IF_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//#include <linux/kernel.h>
+#ifdef __USE_USERSPACE_3A__
+#include "ispalgo_types.h"
+#include "sigma_isp_general.h"
+#else
+#include <drv_ms_isp_general.h>
+#include <drv_ms_rwcfg.h>
+#include <hal_isp_shadow.h>
+#include <drv_isp_shadow.h>
+#include <cam_os_wrapper.h>
+#include "libcamera_iq_struct.h"
+#include "libcamera_error_code.h"
+#include "iq_apiset.h"
+#endif
+
+#include "mi_isp_3a_datatype.h"
+
+//#define ENABLE_DOUBLE_OPT (0)
+
+#define ENABLE_GET_PARAM_FORM_CFG (1)
+
+typedef void* IqCfgHandle; //debug buffer handle
+typedef void* AeHandle;
+typedef void* AwbHandle;
+typedef void* AfHandle;
+
+/******************* IQ_DEBUG_Mode ********************/
+typedef enum
+{
+ DEBUG_ENABLE_IQ, /**< Stop IQ update */
+ DEBUG_LEVEL, /**< enable show log of iq.debug.blkid */
+ DEBUG_BLKID, /**< show log for each IP */
+ DEBUG_PARALEV, /**< parameter level: SUB(0)/DBG(1)/HAL(2) */
+ DEBUG_INDSHOW, /**< show GainCheck result */
+ DEBUG_TBLSCAL, /**< set table scale for debug show (def: 16, only work for 8, 4, 2, 1)*/
+ DEBUG_SETPROPEN, /**< replace function by setprop (works by follow mark with $$) */
+ DEBUG_ISOFIX, /**< ($$)fix iso to present index */
+ DEBUG_ISOIND, /**< ($$)assign isoind under fix iso mode */
+ DEBUG_IQ_TRIGGER, /**< ($$)Force Trigger IQ by mod and blkid */
+ DEBUG_IQ_TRIGMOD, /**< ($$)Force Trigger IQ by mod and blkid */
+ DEBUG_AUTOIQ, /**< on/off autoiq (def:on) */
+ DEBUG_SKIPCFGVC, /**< skip cfg major version check */
+
+ DEBUG_APISHOW, /**< show debug message of API */
+ DEBUG_APIRESET, /**< reset all API setting of OFF */
+
+ DEBUG_SKIPML,
+
+ //---[WDR_GBL, WDR_LOC]
+ DEBUG_FEATURE_LEVEL,
+ DEBUG_DEFOG_ENABLE,
+ DEBUG_DEFOG_MODE,
+ DEBUG_DEFOG_AUTO_LEVEL,
+ DEBUG_DEFOG_MANUAL_LEVEL,
+ DEBUG_DRC_ENABLE,
+ DEBUG_DRC_WHITE_LEVEL,
+ DEBUG_DRC_BLACK_LEVEL,
+ DEBUG_DRC_ASYMMETRY,
+ DEBUG_DRC_BRIGNT_ENHANCE,
+ DEBUG_DRC_EMODE,
+ DEBUG_DRC_MANUAL_LEVEL,
+ DEBUG_DRC_AUTO_LEVEL,
+ DEBUG_LOCWDR_TblShow,
+ DEBUG_LOCWDR_TblSmooth,
+
+
+ //---[RGBIR]
+ DEBUG_IRIDX_THRD_0,
+ DEBUG_IRIDX_THRD_1,
+ DEBUG_IRIDX_THRD_2,
+ DEBUG_IRIDX_THRD_3,
+ DEBUG_IRIDX_THRD_4,
+
+ //---[MEMALLOC]
+ DEBUG_NLM_MEMALLOC_EN,
+ DEBUG_HIST_MEMALLOC_EN,
+
+ DBG_PROP_MAX,
+} DBG_PROP;
+
+typedef struct
+{
+ //---[Enable IQ]
+ MS_S32 IQ_DEBUG_ENABLE_IQ; /**< Stop IQ update */
+ MS_S32 IQ_DEBUG_LEVEL; /**< enable show log of iq.debug.blkid */
+ MS_S32 IQ_DEBUG_BLKID; /**< show log for each IP */
+ MS_S32 IQ_DEBUG_PARALEV; /**< parameter level: SUB(0)/DBG(1)/HAL(2) */
+ MS_S32 IQ_DEBUG_INDSHOW; /**< show GainCheck result */
+ MS_S32 IQ_DEBUG_TBLSCAL; /**< set table scale for debug show (def: 16, only work for 8, 4, 2, 1)*/
+ MS_S32 IQ_DEBUG_SETPROPEN; /**< replace function by setprop (works by follow mark with $$) */
+ MS_S32 IQ_DEBUG_ISOFIX; /**< ($$)fix iso to present index */
+ MS_S32 IQ_DEBUG_ISOIND; /**< ($$)assign isoind under fix iso mode */
+ MS_S32 IQ_DEBUG_IQ_TRIGGER; /**< ($$)Force Trigger IQ by mod and blkid */
+ MS_S32 IQ_DEBUG_IQ_TRIGMOD; /**< ($$)Force Trigger IQ by mod and blkid */
+ MS_S32 IQ_DEBUG_AUTOIQ; /**< on/off autoiq (def:on) */
+ MS_S32 IQ_DEBUG_SKIPCFGVC; /**< skip cfg major version check */
+ //---[API]
+ MS_S32 IQ_DEBUG_APISHOW; /**< show debug message of API */
+ MS_S32 IQ_DEBUG_APIRESET; /**< reset all API setting of OFF */
+ //---[MLoad]
+ MS_S32 IQ_DEBUG_SKIPML;
+ //---[WDR_GBL, WDR_LOC]
+ MS_S32 IQ_DEBUG_FEATURE_LEVEL;
+ MS_S32 IQ_DEBUG_DEFOG_ENABLE;
+ MS_S32 IQ_DEBUG_DEFOG_MODE;
+ MS_S32 IQ_DEBUG_DEFOG_AUTO_LEVEL;
+ MS_S32 IQ_DEBUG_DEFOG_MANUAL_LEVEL;
+ MS_S32 IQ_DEBUG_DRC_ENABLE;
+ MS_S32 IQ_DEBUG_DRC_WHITE_LEVEL;
+ MS_S32 IQ_DEBUG_DRC_BLACK_LEVEL;
+ MS_S32 IQ_DEBUG_DRC_ASYMMETRY;
+ MS_S32 IQ_DEBUG_DRC_BRIGNT_ENHANCE;
+ MS_S32 IQ_DEBUG_DRC_EMODE;
+ MS_S32 IQ_DEBUG_DRC_MANUAL_LEVEL;
+ MS_S32 IQ_DEBUG_DRC_AUTO_LEVEL;
+ MS_S32 IQ_DEBUG_LOCWDR_TblShow;
+ MS_U16 IQ_DEBUG_LOCWDR_TblSmooth;
+ //---[RGBIR]
+ MS_S32 IQ_DEBUG_IRIDX_THRD_0;
+ MS_S32 IQ_DEBUG_IRIDX_THRD_1;
+ MS_S32 IQ_DEBUG_IRIDX_THRD_2;
+ MS_S32 IQ_DEBUG_IRIDX_THRD_3;
+ MS_S32 IQ_DEBUG_IRIDX_THRD_4;
+ //---[Memalloc]
+ MS_S32 IQ_DEBUG_NLM_MEMALLOC_EN;
+ MS_S32 IQ_DEBUG_HIST_MEMALLOC_EN;
+
+} IQDEBUG_t;
+
+typedef struct
+{
+ //---[Enable AE]
+ MS_S32 AE_DEBUG_ENABLE_AE; /**< Enable/Disable AE */
+ MS_S32 AE_DEBUG_LEVEL; /**< 0: disable, 1: Exposure 2: Algo parameters 4: Algo statistics 32: API debug */
+
+} AEDEBUG_t;
+
+typedef struct
+{
+ //---[Enable AWB]
+ MS_S32 AWB_DEBUG_AWB_ENABLE; /**< Enable/Disable AWB */
+ MS_S32 AWB_DEBUG_MWB_ENABLE; /**< Enable/Disable MWB */
+ MS_S32 AWB_DEBUG_MWB_RGAIN; /**< MWB Rgain */
+ MS_S32 AWB_DEBUG_MWB_BGAIN; /**< MWB Bgain */
+ MS_S32 AWB_DEBUG_LEVEL; /**< AWB Debug Mode: 1:show simple algo paramaters 2:always show detail algo parameters 3:show detail algo parameters 7:User Paramters*/
+
+} AWBDEBUG_t;
+
+/******************* AE *********************/
+#define isp_3A_ROW 128 /**< number of 3A statistic blocks in a row */
+#define isp_3A_COL 90 /**< number of 3A statistic blocks in a column */
+#define isp_3A_HIST_BIN0 40 /**< histogram type0 resolution*/
+#define isp_3A_HIST_BINX 128 /**< histogram type1 resolution*/
+#define isp_3A_IR_HIST_BIN 256 /**< histogram type2 resolution*/
+#define isp_DLC_HISTOGRAM_REPORT_NUM 8 /**< histogram type1 resolution(DRC)*/
+
+typedef struct
+{
+ MS_U8 r;
+ MS_U8 g;
+ MS_U8 b;
+ MS_U8 y;
+} __attribute__((packed, aligned(1))) ISPAESample_t;
+
+typedef struct
+{
+ MS_U16 u2HistY[isp_3A_HIST_BINX];
+} __attribute__((packed, aligned(1))) ISPHistX_t;
+
+typedef struct {
+ MS_U16 u2IRHist[isp_3A_IR_HIST_BIN];
+} __attribute__((packed, aligned(1)))ISPHistIR_t;
+
+typedef enum
+{
+ AE_HDR_DISABLE = 0,
+ AE_HDR_SEPARATE_GAIN_SHUTTER,
+ AE_HDR_SHARE_GAIN_SEPARATE_SHUTTER,
+ AE_HDR_SHARE_SHUTTER_SEPARATE_GAIN,
+ AE_HDR_MODE_MAX
+} AE_HDR_MODE;
+
+typedef struct
+{
+ char sensor_id[32]; /**< sensor module id*/
+ MS_U16 FNx10; /**< F number * 10*/
+ MS_U16 shutter_min; /**< shutter Shutter min us*/
+ MS_U16 sensor_gain_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MS_U16 shutterHDRShort_min; /**< shutter Shutter min us*/
+ MS_U16 sensor_gainHDRShort_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ MS_U32 Size; /**< struct size*/
+ MS_U32 fps; /**< initial frame per second*/
+ MS_U32 shutter; /**< shutter Shutter in ns*/
+ MS_U32 shutter_step; /**< shutter Shutter step ns*/
+ MS_U32 shutterHDRShort_step; /**< shutter Shutter step ns*/
+ MS_U32 sensor_gain; /**< sensor_gain Sensor gain, 1X = 1024*/
+ MS_U32 isp_gain; /**< isp_gain Isp digital gain , 1X = 1024 */
+ MS_U32 isp_gain_max; /**< isp_gain Maximum Isp digital gain , 1X = 1024 */
+ MS_U32 shutter_max; /**< shutter Shutter max us*/
+ MS_U32 sensor_gain_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ MS_U32 shutterHDRShort_max; /**< shutter Shutter max us*/
+ MS_U32 sensor_gainHDRShort_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+}ISPAEInitParam_t,AeInitParam_t;
+
+/*! @brief ISP report to AE, hardware statistic */
+typedef struct
+{
+ MS_U32 Size; /**< struct size*/
+ ISPHistX_t *hist1; /**< HW statistic histogram 1*/
+ ISPHistX_t *hist2; /**< HW statistic histogram 2*/
+ ISPHistIR_t *histIR; /**< HW statistic histogram IR*/
+ MS_U32 AvgBlkX; /**< HW statistics average block number*/
+ MS_U32 AvgBlkY; /**< HW statistics average block number*/
+ ISPAESample_t *avgs; /**< HW statistics average block data*/
+ ISPAESample_t *avgs1; /**< HW statistics average block data*/
+ MS_U16 FNx10; /**< Current Aperture in FNx10*/
+ MS_U32 Shutter; /**< Current shutter in ns*/
+ MS_U32 SensorGain; /**< Current Sensor gain, 1X = 1024 */
+ MS_U32 IspGain; /**< Current ISP gain, 1X = 1024*/
+ MS_U32 ShutterHDR; /**< Shutter in ns */
+ MS_U32 SensorGainHDR; /**< Sensor gain, 1X = 1024 */
+ MS_U32 IspGainHDR; /**< ISP gain, 1X = 1024 */
+ MS_U32 PreCurYx10;
+ MS_U32 PreAvgYx10;
+ MS_U32 PreCurY1x10;
+ MS_U32 PreAvgY1x10;
+ MS_U8 HDRMode; /**< 0 = Separate shutter/sensor gain settings; */
+ /**< 1 = Separate shutter & Share sensor gain settings */
+ AEDEBUG_t *tAEDebug; /**< AE debug -> unit test*/
+ MS_U32 CurFPS;
+} ISPAEInfo_t, AeInput_t;
+
+/*! @brief ISP ae algorithm result*/
+typedef struct
+{
+ MS_U32 Size; /**< struct size*/
+ MS_U32 Change; /**< if true, apply this result to hw register*/
+ MS_U32 Shutter; /**< Shutter in ns */
+ MS_U32 SensorGain; /**< Sensor gain, 1X = 1024 */
+ MS_U32 IspGain; /**< ISP gain, 1X = 1024 */
+ MS_U32 ShutterHDR; /**< Shutter in ns */
+ MS_U32 SensorGainHDR; /**< Sensor gain, 1X = 1024 */
+ MS_U32 IspGainHDR; /**< ISP gain, 1X = 1024 */
+ MS_S32 i4BVx16384; /**< Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ MS_U32 CurYx10; /**< frame brightness with weighting*/
+ MS_U32 AvgYx10; /**< frame brightness */
+ MS_U32 CurY1x10; /**< frame brightness with weighting*/
+ MS_U32 AvgY1x10; /**< frame brightness */
+ MS_U32 SceneTargetx10; /**< Current AE target for CurY */
+ MS_CAM_BOOL IsStable;
+ MS_CAM_BOOL IsReachBoundary;
+ MS_U32 AeHdr_Num_BV[17];
+ MS_U32 DebandFPS;
+ MS_U16 FNx10; /**< Aperture in FNx10*/
+ MS_U8 HistMaxY; /**< HistMaxY*/
+ MS_U8 Reserved; /**< Reserved*/
+ MS_U16 GMBlendRatio; /**< Adaptive Gamma Blending Ratio from AE**/
+}__attribute__((packed, aligned(4))) ISPAEResult_t, AeOutput_t;
+
+/*! @brief AE library initialization
+ @param[in] CfgHandle IQ data handle
+ @retval SUCCESS or FAIL if error occurs.
+*/
+AeHandle AeInit(ISP_DBGBUF_HANDLE CfgHandle, AeInitParam_t *init_param, AeInput_t *pInput, AeOutput_t *pOutput);
+
+/*! @brief Release resources that allocated at AeInit
+ @param[in] IQ data handle
+ @retval SUCCESS or FAIL if error occurs.
+*/
+MS_S32 AeRelease(AeHandle Handle);
+
+/*! @brief AE algorithm entry
+ @param[in] handle AE Algorithm private data
+ @param[in] pInput AE algorithm input.
+@param[in] pDbgBuf Debug buffer handle.
+ @param[out] pOutput AE algorithm result.
+ @retval SUCCESS or FAIL if error occurs.
+*/
+MS_S32 DoAe(AeHandle Handle, AeInput_t *pInput, AeOutput_t *pOutput);
+
+MS_S32 AeInitParamConversion(AeHandle Handle, AeInitParam_t *init_param);
+
+/******************* AWB ********************/
+typedef enum
+{
+ AWB_MODE_NORMAL,
+ AWB_MODE_HDR,
+ AWB_MODE_MAX
+} AWBMode_e;
+
+/*! @brief Input parameters of function DoAWB()*/
+typedef struct
+{
+ MS_U32 nSize; /**< Size of DoAwbInput_t */
+ MS_U32 nFrameCount; /**< Frame counts */
+ MS_S32 nBV; /**< Bright value from DoAE() result */
+ MS_S32 CurYx10;
+ MS_U8 nColorToGrayFlag; /**< ColorToGray Flag From IQ for AWB->MWB(x1 gain) */
+ MS_U8 nGrayToColorFlag; /**< GrayToColor Flag From IQ for MWB->AWB */
+ MS_U8 HDRMode; /**< Noramal or HDR mode*/
+ MS_U16 InitRgain; /**< Init Rgain from Wifi */
+ MS_U16 InitGgain; /**< Init Ggain from Wifi */
+ MS_U16 InitBgain; /**< Init Bgain from Wifi */
+ IspCropWin_t tCrop; /**< AWB statistic windows parameter */
+ IspAwbWin_t tBlock; /**< AWB statistic block parameter */
+ IspAwbStatis_t *pAwbStatis; /**< AWB statistic data */
+ IspAwbStatis_t *pAwbStatisShort; /**< Short Shutter AWB statistic data */
+ AWBDEBUG_t *tAWBDebug; /**< AWB debug -> unit test*/
+}AwbInput_t;
+
+/*! @brief Output of function DoAWB()*/
+typedef struct
+{
+ MS_U32 nSize; /** Size of DoAwbOutput_t */
+ IspCropWin_t tCrop; /**< New AWB statistic windows settings for next frame */
+ IspAwbWin_t tBlock; /**< New AWB statistic block settings for next frame */
+ IspAwbGain_t tGain; /**< AWB gain */
+ MS_U16 nColorTmp; /**< Color temperature */
+ MS_CAM_BOOL nMultiLS_CaliCCMUpdate; /**< Color calibration CCM update flag for multi-lightsource*/
+ MS_U16 nMultiLS_CaliCCM[9]; /**< Color calibration CCM for multi-lightsource*/
+}AwbOutput_t;
+
+
+/*! @brief AWB algorithm entry
+ @param[in] handle AWB Algorithm private data
+ @param[in] AWB HW statistics
+ @param[out] pOutput AWB algorithm result.
+ @retval SUCCESS or FAIL if error occurs.
+*/
+MS_S32 DoAwb(AwbHandle Handle, AwbInput_t *pInput, AwbOutput_t *pOutput);
+
+/*! @brief AWB library initialization
+ @param[in] CfgHandle IQ data handle
+ @retval SUCCESS or FAIL if error occurs.
+*/
+AwbHandle AwbInit(ISP_DBGBUF_HANDLE CfgHandle, AwbInput_t *pInput, AwbOutput_t *pOutput);
+
+/*! @brief Release resources that allocated at AwbInit
+ @param[in] IQ data handle
+ @retval SUCCESS or FAIL if error occurs.
+*/
+MS_S32 AwbRelease(AwbHandle Handle);
+
+
+/******************* IQ ********************/
+/*! @brief Calculate IQ for current condition then output the ISP setting to shadow register buffer
+ @param[in] pHandle IQ handle
+ @param[out] pRegShd register shadow buffer
+ @retval SUCCESS or FAIL if error occurs.
+*/
+/*! @brief Input of function DoIQ()*/
+#ifndef __USE_USERSPACE_3A__
+
+//
+
+typedef struct
+{
+ MS_U16 dummy0;
+ MS_U16 dummy1;
+ MS_U16 dummy2;
+ MS_U16 dummy3;
+} IQNoiseEst_t;
+
+typedef struct
+{
+ MS_U32 acc;
+ MS_U16 n;
+ MS_U32 rstracc;
+ MS_U16 rstrn;
+} IQWDRDefog_t;
+
+typedef struct
+{
+ MS_U16 nalignGain[16];
+} IQHDREst_t;
+
+typedef enum
+{
+ IQ_MODE_NORMAL,
+ IQ_MODE_HDR,
+ IQ_MODE_HDR_EMBED,
+ IQ_MODE_RGBIR,
+ IQ_MODE_MAX
+} IQMode_e;
+
+typedef enum __attribute__ ((aligned (4))) //IQ Trigger:
+{
+ IQ_PA_KEEP,
+ IQ_PA_ALL, //all blocks update
+ IQ_PA_ISO, //blocks change by ISO
+ IQ_PA_CCT, //blocks change by CCT
+ IQ_PA_SEL, //single block update
+ IQ_PA_API, //blocks change by API
+ IQ_PA_INIT,//init blocks update
+ IQ_PA_MISS,//CFG parse fail make IND missing
+ IQ_PA_SKIP,
+ IQ_PA_MAX,
+} IQ_PARA_CODE;
+
+typedef struct
+{
+ MS_U32 nSize; /** Size of IqInput_t **/
+ MS_U32 nFrameCount; /**< frame count*/
+ MS_S32 nBV; /**< Bright value from DoAE() result */
+ MS_U32 nIspGain; /** ISP gain **/
+ MS_U32 nIspGainHDR; /** ISP gain P1 **/
+ MS_U32 nTotalGain; /** TotalGain = ISP gain + Sensor gain **/
+ MS_S32 nChipTemp; /** Chip temperature **/
+ MS_S32 nSensorTemp; /** Sensor temperature **/
+ MS_U32 nColorTemp; /** Color temperature **/
+ MS_U32 nAwbRx1024; /** Awb R gain 1024 base **/
+ MS_U32 nAwbGx1024; /** Awb G gain 1024 base **/
+ MS_U32 nAwbBx1024; /** Awb B gain 1024 base **/
+ MS_U32 nWdrRatiox1024; /** Wdr ratio 1024 base **/
+ MS_U32 nIrindex; /** RGBIR index **/
+ MS_U32 nCropSizeW; /** Image width after crop **/
+ MS_U32 nCropSizeH; /** Image height after crop **/
+ MS_U32 nAvgBlkX; /**< HW statistics average block number*/
+ MS_U32 nAvgBlkY; /**< HW statistics average block number*/
+ MS_U16 nDegree; /**< Sensor degree **/
+ MS_U16 nGMBlendRatio; /**< Adaptive Gamma Blending Ratio from AE**/
+ IQMode_e nMode; /**< IQ Mode **/
+ ISPAESample_t *tAvgs; /**< HW statistics average block data*/
+ IQDEBUG_t *tIQDebug; /**< IQ debug -> unit test*/
+ ISP_HDR_STATS *pHdrStats; /**< HDR statistic */
+ MS_CAM_BOOL nMultiLS_CaliCCMUpdate; /**< Color calibration CCM update flag for multi-lightsource*/
+ MS_U16 nMultiLS_CaliCCM[9]; /**< Color calibration CCM for multi-lightsource*/
+ IQNoiseEst_t *pNE0; /**< Noise Est*/
+ IQWDRDefog_t *pDefog;
+ IQHDREst_t *pHDRDyn; /**< HDR Dynamic Ratio*/
+}IqInput_t;
+
+typedef struct
+{
+ DrvIspShd_t tIsp;
+ DrvSclShd_t tScl;
+ DrvMloadShd_t tMload;
+ MS_U8 nColorToGrayFlag; /**< ColorToGray Flag for AWB->MWB **/
+ MS_U8 nGrayToColorFlag; /**< ColorToGray Flag for MWB->AWB **/
+ MS_U16 u16HDRExpRatio;
+}IqOutput_t;
+
+/*! @brief IQ algorithm entry
+ @param[in] handle IQ Algorithm private data
+ @param[in] IQ HW statistics
+ @param[out] pOutput IQ algorithm result.
+ @retval SUCCESS or FAIL if error occurs.
+*/
+MS_S32 DoIq(IqCfgHandle pHandle, IqInput_t *input_param, IqOutput_t *output_param);
+MS_S32 DoIqPerFrame(IqCfgHandle pHandle, IqInput_t *input_param, IqOutput_t *output_param);
+
+/*! @brief IQ library initialization
+ @param[in] CfgHandle IQ data handle
+ @retval SUCCESS or FAIL if error occurs.
+*/
+IqCfgHandle IqInit(ISP_DBGBUF_HANDLE pIqDbgBuf, IqInput_t *input_param, IqOutput_t *output_param);
+
+/*! @brief IQ resources that allocated at IQInit
+ @param[in] IQ data handle
+ @retval SUCCESS or FAIL if error occurs.
+*/
+MS_S32 IqRelease(IqCfgHandle Handle);
+
+int IspAlgoReadIqBinH(void* pIqBuf, int nIqSize);
+
+typedef struct
+{
+ AeInput_t ae;
+ AwbInput_t awb;
+ IqInput_t iq;
+}IspAlgoInputHandle;
+
+#endif
+/************************************* IQ API STRUCT START *************************************/
+
+#if 1 //unused struct
+
+typedef struct
+{
+ MS_U16 u2BlkSize_x;
+ MS_U16 u2BlkSize_y;
+ MS_U16 u2BlkNum_x;
+ MS_U16 u2BlkNum_y;
+} MS_AE_WIN;
+
+typedef struct
+{
+ MS_U16 u2BlkSize_x;
+ MS_U16 u2BlkSize_y;
+ MS_U16 u2BlkNum_x;
+ MS_U16 u2BlkNum_y;
+} MS_AWB_WIN;
+
+typedef struct
+{
+ MS_U8 r;
+ MS_U8 g;
+ MS_U8 b;
+ MS_U8 y;
+} __attribute__((packed, aligned(1))) AE_SAMPLE;
+
+typedef struct
+{
+ AE_SAMPLE ae_data[128 * 90];
+} __attribute__((packed, aligned(1))) MS_CAM_AE_STATIS;
+
+typedef enum
+{
+ MS_ExposureControlOff = 0,
+ MS_ExposureControlAuto,
+ MS_ExposureControlNight,
+ MS_ExposureControlBackLight,
+ MS_ExposureControlSpotLight,
+ MS_ExposureControlSports,
+ MS_ExposureControlSnow,
+ MS_ExposureControlBeach,
+ MS_ExposureControlLargeAperture,
+ MS_ExposureControlSmallApperture,
+ MS_ExposureControlKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */
+ MS_ExposureControlVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */
+ MS_ExposureControlMax = 0x7FFFFFFF
+} MS_CAM_AE_EXPOSURECONTROLTYPE;
+
+typedef struct
+{
+ MS_U8 u8DebugLevel;
+} MS_CAM_AE_DEBUG_LEVEL;
+
+typedef enum __attribute__ ((aligned (1))) //MS_AWB_CONTROL_MODE_
+{
+ MS_AWB_CONTROL_OFF = 0,
+ MS_AWB_CONTROL_AUTO,
+ MS_AWB_CONTROL_SUNLIGHT, // Referenced in JSR-234
+ MS_AWB_CONTROL_CLOUDY,
+ MS_AWB_CONTROL_SHADE,
+ MS_AWB_CONTROL_TUNGSTEN,
+ MS_AWB_CONTROL_FLUORESCENT,
+ MS_AWB_CONTROL_INCANDESCENT,
+ MS_AWB_CONTROL_FLASH, // Optimal for device's integrated flash
+ MS_AWB_CONTROL_HORIZON,
+ MS_AWB_CONTROL_NUM
+} MS_WHITEBALCONTROLTYPE;
+
+typedef struct MS_CAM_WHITEBALCONTROLTYPE
+{
+ MS_WHITEBALCONTROLTYPE eWhiteBalControl;
+ //AWB_SCENE eWhiteBalControl;
+} MS_CAM_WHITEBALCONTROLTYPE;
+
+#endif
+
+#if 1 //export api
+#ifndef __USE_USERSPACE_3A__
+MS_S32 DrvAlgo_IF_IQ_SetMirrorFlip(IqCfgHandle hIq, MS_CAM_MIRRORFLIPTYPE *MirrorFlip);
+MS_S32 DrvAlgo_IF_IQ_ForceTrigIQ(IqCfgHandle hIq, IQ_PARA_CODE mode, int block);
+#endif //#ifdef __USE_KERNEL_3A__
+MS_S32 DrvAlgo_IF_AE_SetFlicker(AeHandle hAe, MI_ISP_AE_FLICKER_TYPE_e *eFlicker);
+
+MS_S32 DrvAlgo_IF_ApiSet(MS_U32 nCtlID, AeHandle pAEHandle, AwbHandle pAWBHandle, AfHandle pAFHandle, IqCfgHandle pIQHandle, MS_U32 size, const void* pData);
+MS_S32 DrvAlgo_IF_ApiGet(MS_U32 nCtlID, AeHandle pAEHandle, AwbHandle pAWBHandle, AfHandle pAFHandle, IqCfgHandle pIQHandle, MS_U32 size, const void* pData);
+#endif
+
+#ifdef __USE_USERSPACE_3A__
+int IspLoadIqCfg(ISP_DBGBUF_HANDLE *pHandle, void *pCfg, unsigned int Len);
+void IspFreeIqCfg(ISP_DBGBUF_HANDLE *pHandle);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_cus3a_if.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_cus3a_if.h
new file mode 100644
index 00000000..f504af60
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_cus3a_if.h
@@ -0,0 +1,385 @@
+#ifndef _ISP_CUS3A_IF_H_
+#define _ISP_CUS3A_IF_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define CUS3A_VER_STR "CUS3A_V1.1"
+#define CUS3A_VER_MAJOR 1
+#define CUS3A_VER_MINOR 1
+
+#include "cam_os_wrapper.h"
+
+#if 0
+typedef unsigned char u8;
+//typedef signed char s8;
+typedef unsigned short u16;
+//typedef signed short s16;
+typedef unsigned int u32;
+//typedef signed int s32;
+typedef unsigned long long u64;
+//typedef signed long long s64;
+#endif
+
+#define MV_WIN_NUM 25
+#define CAM20_AUTO_NUM 16
+#define CAM20_SDC_CTRL_ITEM_NUMBER 2
+#define AWB_LV_CT_TBL_NUM 18
+#define AWB_CT_TBL_NUM 10
+
+#define MS_GAMMA_TBL 256
+#define MS_ALSC_TBL_W 61
+#define MS_ALSC_TBL_H 69
+#define MS_ALSC_TBL 4209
+#define MS_SDC_TBL 1024
+#define MS_FPN_TBL 4000 //infinity5
+#define MS_YUVGAMA_Y_TBL 256
+#define MS_YUVGAMA_VU_TBL 128
+#define MS_WDR_LOC_TBL 88
+
+#define MS_CAM_AF_MAX_WIN_NUM 16 //
+#define MAX_CUST_3A_CHINFO_NUM (16)
+
+/*------AE/AWB interface--------*/
+/*! @brief API error code*/
+typedef enum CUS_3A_ERR_CODE
+{
+ CUS_3A_SUCCESS = 0, /**< operation successful */
+ CUS_3A_ERROR = -1, /**< unspecified failure */
+}CUS3A_ERR_CODE;
+
+#define _3A_ROW (128) /**< number of 3A statistic blocks in a row */
+#define _3A_COL (90) /**< number of 3A statistic blocks in a column */
+#define _3A_HIST_BIN0 (40) /**< histogram type0 resolution*/
+#define _3A_HIST_BINX (128) /**< histogram type1 resolution*/
+#define _3A_IR_HIST_BIN (256) /**< histogram type2 resolution*/
+
+// AWB statistic , one sample
+typedef struct
+{
+ u8 r;
+ u8 g;
+ u8 b;
+} __attribute__((packed, aligned(1))) ISP_AWB_SAMPLE;
+
+#if 0
+/*! @brief AWB HW statistics data*/
+typedef struct
+{
+ //ISP_AWB_SAMPLE data[_3A_ROW*_3A_COL];
+ u32 AvgBlkX;
+ u32 AvgBlkY;
+ ISP_AWB_SAMPLE *avgs;
+} __attribute__((packed, aligned(1))) ISP_AWB_INFO;
+#else
+/*! @brief AWB HW statistics data*/
+typedef struct
+{
+ u32 Size; /**< struct size*/
+ u32 AvgBlkX;
+ u32 AvgBlkY;
+ u32 CurRGain;
+ u32 CurGGain;
+ u32 CurBGain;
+ ISP_AWB_SAMPLE *avgs; /*awb statis for linear frame or HDR long frame*/
+ /*CUS3A V1.1*/
+ u8 HDRMode; /**< Noramal or HDR mode*/
+ ISP_AWB_SAMPLE* pAwbStatisShort; /**<awb statis for HDR short Shutter AWB statistic data */
+ u32 u4BVx16384; /**< From AE output, Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ u32 WeightY; /**< frame brightness with ROI weight*/
+} __attribute__((packed, aligned(1))) ISP_AWB_INFO;
+#endif
+
+
+/*! @brief AWB algorithm result*/
+typedef struct isp_awb_result
+{
+ u32 Size; /**< struct size*/
+ u32 Change; /**< if true, apply this result to hw register*/
+ u32 R_gain; /**< AWB gain for R channel*/
+ u32 G_gain; /**< AWB gain for G channel*/
+ u32 B_gain; /**< AWB gain for B channel*/
+ u32 ColorTmp; /**< Return color temperature*/
+} ISP_AWB_RESULT;
+
+// AE statistics data
+typedef struct
+{
+ u8 r;
+ u8 g;
+ u8 b;
+ u8 y;
+} __attribute__((packed, aligned(1))) ISP_AE_SAMPLE;
+
+typedef struct
+{
+ u16 u2HistY[_3A_HIST_BINX];
+} __attribute__((packed, aligned(1))) ISP_HISTX;
+
+typedef struct
+{
+ u16 u2IRHist[_3A_IR_HIST_BIN];
+} __attribute__((packed, aligned(1))) ISP_IR_HISTX;
+
+/*! @brief ISP report to AE, hardware statistic */
+typedef struct
+{
+ u32 Size; /**< struct size*/
+ ISP_HISTX *hist1; /**< HW statistic histogram 1*/
+ ISP_HISTX *hist2; /**< HW statistic histogram 2*/
+ u32 AvgBlkX; /**< HW statistics average block number*/
+ u32 AvgBlkY; /**< HW statistics average block number*/
+ ISP_AE_SAMPLE * avgs; /**< HW statistics average block data*/
+ u32 Shutter; /**< Current shutter in us*/
+ u32 SensorGain; /**< Current Sensor gain, 1X = 1024 */
+ u32 IspGain; /**< Current ISP gain, 1X = 1024*/
+ u32 ShutterHDRShort; /**< Current shutter in us*/
+ u32 SensorGainHDRShort; /**< Current Sensor gain, 1X = 1024 */
+ u32 IspGainHDRShort; /**< Current ISP gain, 1X = 1024*/
+
+ /*CUS3A V1.1*/
+ u32 PreAvgY; /**< Previous frame brightness*/
+ u8 HDRCtlMode; /**< 0 = Separate shutter/sensor gain settings; */
+ /**< 1 = Separate shutter & Share sensor gain settings */
+ u32 FNx10; /**< Aperture in FNx10*/
+ u32 CurFPS; /**Current sensor FPS */
+ u32 PreWeightY; /**< Previous frame brightness with ROI weight*/
+ ISP_IR_HISTX *histIR; /**< HW statistic histogram IR*/
+} __attribute__((packed, aligned(1))) ISP_AE_INFO;
+
+//AE algorithm result
+/*! @brief ISP ae algorithm result*/
+typedef struct
+{
+ u32 Size; /**< struct size*/
+ u32 Change; /**< if true, apply this result to hw register*/
+ u32 Shutter; /**< Shutter in us */
+ u32 SensorGain; /**< Sensor gain, 1X = 1024 */
+ u32 IspGain; /**< ISP gain, 1X = 1024 */
+ u32 ShutterHdrShort; /**< Shutter in us */
+ u32 SensorGainHdrShort; /**< Sensor gain, 1X = 1024 */
+ u32 IspGainHdrShort; /**< ISP gain, 1X = 1024 */
+ u32 u4BVx16384; /**< Bv * 16384 in APEX system, EV = Av + Tv = Sv + Bv */
+ u32 AvgY; /**< frame brightness */
+ u32 HdrRatio; /**< hdr ratio, 1X = 1024 */
+ /*CUS3A V1.1*/
+ u32 FNx10; /**< F number * 10*/
+ u32 DebandFPS; /** Target fps when running auto debanding**/
+ u32 WeightY; /**< frame brightness with ROI weight*/
+} __attribute__((packed, aligned(1))) ISP_AE_RESULT;
+
+/*! @brief ISP initial status*/
+typedef struct _isp_ae_init_param
+{
+ u32 Size; /**< struct size*/
+ char sensor_id[32]; /**< sensor module id*/
+ u32 shutter; /**< shutter Shutter in us*/
+ u32 shutter_step; /**< shutter Shutter step ns*/
+ u32 shutter_min; /**< shutter Shutter min us*/
+ u32 shutter_max; /**< shutter Shutter max us*/
+ u32 sensor_gain; /**< sensor_gain Sensor gain, 1X = 1024*/
+ u32 sensor_gain_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ u32 sensor_gain_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ u32 isp_gain; /**< isp_gain Isp digital gain , 1X = 1024 */
+ u32 isp_gain_max; /**< isp_gain Maximum Isp digital gain , 1X = 1024 */
+ u32 FNx10; /**< F number * 10*/
+ u32 fps; /**< initial frame per second*/
+ u32 shutterHDRShort_step; /**< shutter Shutter step ns*/
+ u32 shutterHDRShort_min; /**< shutter Shutter min us*/
+ u32 shutterHDRShort_max; /**< shutter Shutter max us*/
+ u32 sensor_gainHDRShort_min; /**< sensor_gain_min Minimum Sensor gain, 1X = 1024*/
+ u32 sensor_gainHDRShort_max; /**< sensor_gain_max Maximum Sensor gain, 1X = 1024*/
+ u32 AvgBlkX; /**< HW statistics average block number*/
+ u32 AvgBlkY; /**< HW statistics average block number*/
+} ISP_AE_INIT_PARAM;
+
+typedef enum
+{
+ ISP_AE_FPS_SET, /**< ISP notify AE sensor FPS has changed*/
+} ISP_AE_CTRL_CMD;
+
+typedef struct
+{
+ u32 start_x; /*range : 0~1023*/
+ u32 start_y; /*range : 0~1023*/
+ u32 end_x; /*range : 0~1023*/
+ u32 end_y; /*range : 0~1023*/
+} ISP_AF_RECT;
+
+/*! @brief ISP initial status*/
+typedef struct _isp_af_init_param
+{
+ u32 Size; /**< struct size*/
+ ISP_AF_RECT af_stats_win[16];
+
+} ISP_AF_INIT_PARAM;
+
+typedef enum
+{
+ ISP_AF_CMD_MAX,
+} ISP_AF_CTRL_CMD;
+
+typedef struct
+{
+ u8 high_iir[5*16];
+ u8 low_iir[5*16];
+ u8 luma[4*16];
+ u8 sobel_v[5*16];
+ u8 sobel_h[5*16];
+ u8 ysat[3*16];
+} ISP_AF_INFO_STATS_PARAM_t;
+//Infinity5. Sync with ISP_AF_STATS
+
+typedef struct
+{
+ ISP_AF_INFO_STATS_PARAM_t stParaAPI[MS_CAM_AF_MAX_WIN_NUM];
+} ISP_AF_INFO_STATS;
+
+/*! @brief ISP report to AF, hardware statistic */
+typedef struct
+{
+ u32 Size; /**< struct size*/
+ ISP_AF_INFO_STATS af_stats; /**< AF statistic*/
+} __attribute__((packed, aligned(1))) ISP_AF_INFO;
+
+typedef struct
+{
+ u32 Change; /**< if true, apply this result to hw*/
+ u32 Focal_pos; /**< Focal position*/
+} __attribute__((packed, aligned(1))) ISP_AF_RESULT;
+
+/**@brief ISP AE interface*/
+typedef struct isp_ae_interface
+{
+ void *pdata; /**< Private data for AE algorithm.*/
+
+ /** @brief AE algorithm init callback
+ @param[in] pdata AE algorithm private data
+ @param[in] init_state ISP initial status.
+ @retval CUS_3A_SUCCESS or CUS_3A_ERROR if error occurs.
+ @remark ISP call this function when AE algorithm initialize.
+ */
+ int (*init)(void* pdata, ISP_AE_INIT_PARAM *init_state);
+
+ /** @brief AE algorithm close
+ @param[in] pdata AE algorithm private data
+ @remark ISP call this function when AE close.
+ */
+ void (*release)(void* pdata);
+
+ /** @brief AE algorithm run
+ @param[in] pdata AE algorithm private data
+ @param[in] info ISP HW statistics
+ @param[out] result AE algorithm return calculated result.
+ @remark ISP call this function when AE close.
+ */
+ void (*run)(void* pdata, const ISP_AE_INFO *info, ISP_AE_RESULT *result);
+
+ /** @brief AE algorithm control
+ @param[in] pdata AE algorithm private data
+ @param[in] cmd Control ID
+ @param[in out] param Control parameter.
+ @retval CUS_3A_SUCCESS or CUS_3A_ERROR if error occurs.
+ @remark ISP call this function to change parameter
+ */
+ int (*ctrl)(void* pdata, ISP_AE_CTRL_CMD cmd, void* param);
+} ISP_AE_INTERFACE;
+
+typedef enum
+{
+ ISP_AWB_MODE_SET,
+} ISP_AWB_CTRL_CMD;
+/**@brief ISP AWB interface*/
+
+typedef struct isp_awb_interface
+{
+ void *pdata; /**< Private data for AE algorithm.*/
+
+ /** @brief AWB algorithm init callback
+ @param[in] pdata Algorithm private data
+ @retval CUS_3A_SUCCESS or CUS_3A_ERROR if error occurs.
+ @remark ISP call this function when AE algorithm initialize.
+ */
+ int (*init)(void *pdata);
+
+ /** @brief AWB algorithm close
+ @param[in] pdata Algorithm private data
+ @remark ISP call this function when AE close.
+ */
+ void (*release)(void *pdata);
+
+ /** @brief AWB algorithm run
+ @param[in] pdata Algorithm private data
+ @param[in] info ISP HW statistics
+ @param[out] result AWB algorithm return calculated result.
+ @remark ISP call this function when AE close.
+ */
+ void (*run)(void *pdata, const ISP_AWB_INFO *awb_info, ISP_AWB_RESULT *result);
+
+ /** @brief AWB algorithm control
+ @param[in] pdata Algorithm private data
+ @param[in] cmd Control ID
+ @param[in out] param Control parameter.
+ @retval CUS_3A_SUCCESS or CUS_3A_ERROR if error occurs.
+ @remark ISP call this function to change parameter
+ */
+ int (*ctrl)(void *pdata, ISP_AWB_CTRL_CMD cmd, void* param);
+} ISP_AWB_INTERFACE;
+
+/**@brief ISP AF interface*/
+typedef struct isp_af_interface
+{
+ void *pdata; /**< Private data for AF algorithm.*/
+
+ /** @brief AF algorithm init callback
+ @param[in] pdata Algorithm private data
+ @retval CUS_3A_SUCCESS or CUS_3A_ERROR if error occurs.
+ @remark ISP call this function when AF algorithm initialize.
+ */
+ int (*init)(void *pdata, ISP_AF_INIT_PARAM *param);
+
+ /** @brief AF algorithm close
+ @param[in] pdata Algorithm private data
+ @remark ISP call this function when AF close.
+ */
+ void (*release)(void *pdata);
+
+ /** @brief AF algorithm run
+ @param[in] pdata Algorithm private data
+ @param[in] info ISP HW statistics
+ @param[out] result AF algorithm return calculated result.
+ @remark ISP call this function when AF close.
+ */
+ void (*run)(void *pdata, const ISP_AF_INFO *af_info, ISP_AF_RESULT *result);
+
+ /** @brief AF algorithm control
+ @param[in] pdata Algorithm private data
+ @param[in] cmd Control ID
+ @param[in out] param Control parameter.
+ @retval CUS_3A_SUCCESS or CUS_3A_ERROR if error occurs.
+ @remark ISP call this function to change parameter
+ */
+ int (*ctrl)(void *pdata, ISP_AF_CTRL_CMD cmd, void* param);
+} ISP_AF_INTERFACE;
+
+
+unsigned int CUS3A_GetVersion(char* pVerStr);
+int CUS3A_Init(void);
+void CUS3A_Release(void);
+int CUS3A_RegInterface(u32 nCh,ISP_AE_INTERFACE *pAE,ISP_AWB_INTERFACE *pAWB,ISP_AF_INTERFACE *pAF);
+int CUS3A_AERegInterface(u32 nCh,ISP_AE_INTERFACE *pAE);
+int CUS3A_AWBRegInterface(u32 nCh,ISP_AWB_INTERFACE *pAWB);
+int CUS3A_AFRegInterface(u32 nCh,ISP_AF_INTERFACE *pAF);
+void* pAllocDmaBuffer(const char* pName, u32 nReqSize, u32 *pPhysAddr, u32 *pMiuAddr, u8 bCache);
+int FreeDmaBuffer(const char* pName, u32 u32MiuAddr, void *pVirtAddr, u32 u32FreeSize);
+int Cus3AOpenIspFrameSync(int *fd0, int *fd1);
+int Cus3ACloseIspFrameSync(int fd0, int fd1);
+unsigned int Cus3AWaitIspFrameSync(int fd0, int fd1, int timeout);
+int CUS3A_AeAvgDownSample(const ISP_AE_SAMPLE *pInBuf, ISP_AE_SAMPLE *pOutBuf, unsigned int nInBlkX, unsigned int nInBlkY, unsigned int nOutBlkX, unsigned int nOutBlkY);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_sigma3a_ext.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_sigma3a_ext.h
new file mode 100644
index 00000000..9771b741
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/isp_sigma3a_ext.h
@@ -0,0 +1,43 @@
+/* SigmaStar 3A extension api */
+#ifndef ISP_SIGMA3A_EXT_H
+#define ISP_SIGMA3A_EXT_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "mi_vpe_datatype.h"
+
+typedef struct
+{
+ MI_U32 u32HeadSize; //Size of MIIspApiHeader_t
+ MI_U32 u32DataLen; //Data length;
+ MI_U32 u32CtrlID; //Function ID
+ MI_U32 u32Channel; //Isp channel number
+ MI_U32 u32Dir; //Command direction, 1: Set, 2: Get
+ MI_S32 s32Ret; //Isp api retuen value
+} MI_CUS3A_IspApiHeader_t;
+
+typedef struct
+{
+ MI_CUS3A_IspApiHeader_t stHeader;
+ MI_U8 u8Data[0];
+}MI_CUS3A_IspApiCmd_t;
+
+typedef struct
+{
+ MI_U32 u32Dir; // 0: Set, 1: Get
+ //MI_VPE_IspApiData_t stApiData;
+ MI_VPE_IspApiHeader_t stApiHeader;
+ void* pData;
+}MI_CUS3A_CtrlCmd_t;
+
+MI_S32 Cus3A_GetIspApiData(MI_VPE_IspApiHeader_t *pCmd, void *pstData);
+MI_S32 Cus3A_SetIspApiData(MI_VPE_IspApiHeader_t *pCmd, void *pstData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/ispalgo_types.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/ispalgo_types.h
new file mode 100644
index 00000000..2922ac1c
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/ispalgo_types.h
@@ -0,0 +1,117 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+ * ispalgo_type.h
+ *
+ * Created on:
+ * Author:
+ */
+
+/// data type unsigned char, data length 1 byte
+typedef unsigned char MS_U8; // 1 byte
+/// data type unsigned short, data length 2 byte
+typedef unsigned short MS_U16; // 2 bytes
+/// data type unsigned int, data length 4 byte
+typedef unsigned int MS_U32; // 4 bytes
+/// data type unsigned int, data length 8 byte
+typedef unsigned long long MS_U64; // 8 bytes
+/// data type signed char, data length 1 byte
+typedef signed char MS_S8; // 1 byte
+/// data type signed short, data length 2 byte
+typedef signed short MS_S16; // 2 bytes
+/// data type signed int, data length 4 byte
+typedef signed int MS_S32; // 4 bytes
+/// data type signed int, data length 8 byte
+typedef signed long long MS_S64; // 8 bytes
+/// data type float, data length 4 byte
+typedef float MS_FLOAT; // 4 bytes
+/// data type hardware physical address
+typedef unsigned long long MS_PHYADDR; // 32bit physical address
+/// definition for MS_BOOL
+typedef unsigned char MS_BOOL;
+
+#ifdef SUCCESS
+#undef SUCCESS
+#endif
+#define SUCCESS (0)
+#ifdef FAIL
+#undef FAIL
+#endif
+#define FAIL (-1)
+
+#ifdef TRUE
+#undef TRUE
+#endif
+#define TRUE (1)
+
+#ifdef FALSE
+#undef FALSE
+#endif
+#define FALSE (0)
+
+#ifdef NULL
+#undef NULL
+#endif
+#define NULL (0)
+
+#ifdef sign
+#undef sign
+#endif
+#define sign(a) (((a) > 0) ? (1) : (-1))
+
+#ifdef LIMIT
+#undef LIMIT
+#endif
+#define LIMIT(x, low, high) (((x) > (high)) ? (high) : (((x) < (low)) ? (low) : (x)))
+
+#ifdef MIN
+#undef MIN
+#endif
+#define MIN(a,b) (((a) >= (b))?(b):(a))
+
+#ifdef MIN3
+#undef MIN3
+#endif
+#define MIN3(a, b, c) (((a) < (b)) ? (MIN(a, c)) : (MIN(b, c)))
+
+#ifdef MAX
+#undef MAX
+#endif
+#define MAX(a, b) (((a)>(b)) ? (a) : (b))
+
+#ifdef MAX3
+#undef MAX3
+#endif
+#define MAX3(a, b, c) (((a) > (b)) ? (MAX(a, c)) : (MAX(b, c)))
+
+#ifdef MINMAX
+#undef MINMAX
+#endif
+#define MINMAX(v,a,b) (((v)<(a))? (a) : ((v)>(b)) ? (b) : (v))
+
+#ifdef ABS
+#undef ABS
+#endif
+#define ABS(x) (((x) < 0) ? (-(x)) : (x))
+
+#ifdef DIFF
+#undef DIFF
+#endif
+#define DIFF(a, b) (((a) > (b)) ? (a-b) : (b-a))
+
+#define lInterp(T, m, n, a, b) (a + (b - a)*(T - m)/(n - m)) //Linear interpolation
+
+
+
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ai.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ai.h
new file mode 100644
index 00000000..f5f1e523
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ai.h
@@ -0,0 +1,115 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_AI_H__
+#define __MI_AI_H__
+
+#include "mi_aio_datatype.h"
+#include "mi_ai_datatype.h"
+
+
+#define AI_MAJOR_VERSION 2
+#define AI_SUB_VERSION 13
+#define MACRO_TO_STR(macro) #macro
+#define AI_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_ai_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_ai_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_ai_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_AI_API_VERSION AI_VERSION_STR(AI_MAJOR_VERSION,AI_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//=============================================================================
+// Include files
+//=============================================================================
+
+
+//=============================================================================
+// Extern definition
+//=============================================================================
+
+//=============================================================================
+// Macro definition
+//=============================================================================
+
+
+//=============================================================================
+// Data type definition
+//=============================================================================
+
+
+//=============================================================================
+// Variable definition
+//=============================================================================
+
+
+//=============================================================================
+// Global function definition
+//=============================================================================
+MI_S32 MI_AI_SetPubAttr(MI_AUDIO_DEV AiDevId, MI_AUDIO_Attr_t *pstAttr);
+MI_S32 MI_AI_GetPubAttr(MI_AUDIO_DEV AiDevId, MI_AUDIO_Attr_t*pstAttr);
+MI_S32 MI_AI_Enable(MI_AUDIO_DEV AiDevId);
+MI_S32 MI_AI_Disable(MI_AUDIO_DEV AiDevId);
+MI_S32 MI_AI_EnableChn(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_DisableChn(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_GetFrame(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AUDIO_Frame_t*pstFrm, MI_AUDIO_AecFrame_t *pstAecFrm , MI_S32 s32MilliSec);
+MI_S32 MI_AI_ReleaseFrame(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AUDIO_Frame_t *pstFrm, MI_AUDIO_AecFrame_t *pstAecFrm);
+MI_S32 MI_AI_SetChnParam(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_ChnParam_t *pstChnParam);
+MI_S32 MI_AI_GetChnParam(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_ChnParam_t *pstChnParam);
+MI_S32 MI_AI_EnableReSmp(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AUDIO_SampleRate_e eOutSampleRate);
+MI_S32 MI_AI_DisableReSmp(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_SetVqeAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AI_VqeConfig_t *pstVqeConfig);
+MI_S32 MI_AI_GetVqeAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_VqeConfig_t *pstVqeConfig);
+MI_S32 MI_AI_EnableVqe(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_DisableVqe(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_ClrPubAttr(MI_AUDIO_DEV AiDevId);
+MI_S32 MI_AI_SaveFile(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn,MI_AUDIO_SaveFileInfo_t *pstSaveFileInfo);
+MI_S32 MI_AI_SetVqeVolume(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_S32 s32VolumeDb);
+MI_S32 MI_AI_GetVqeVolume(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_S32 *ps32VolumeDb);
+MI_S32 MI_AI_SetAencAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_AencConfig_t * pstAencConfig);
+MI_S32 MI_AI_GetAencAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_AencConfig_t * pstAencConfig);
+MI_S32 MI_AI_EnableAenc(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_DisableAenc(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_DupChn(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_SetAedAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_AedConfig_t *pstAedConfig);
+MI_S32 MI_AI_GetAedAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_AedConfig_t *pstAedConfig);
+MI_S32 MI_AI_EnableAed(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_DisableAed(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_GetAedResult(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_AedResult_t *pstAedResult);
+MI_S32 MI_AI_SetExtAecChn(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_CHN AiAECSndChn);
+MI_S32 MI_AI_SetSslInitAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_SslInitAttr_t* pstSslInitAttr);
+MI_S32 MI_AI_GetSslInitAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_SslInitAttr_t* pstSslInitAttr);
+MI_S32 MI_AI_SetSslConfigAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_SslConfigAttr_t* pstSslConfigAttr);
+MI_S32 MI_AI_GetSslConfigAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_SslConfigAttr_t* pstSslConfigAttr);
+MI_S32 MI_AI_EnableSsl(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_DisableSsl(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_GetSslDoa(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_S32 *ps32SslDoa);
+MI_S32 MI_AI_SetBfInitAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_BfInitAttr_t* pstBfInitAttr);
+MI_S32 MI_AI_GetBfInitAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_BfInitAttr_t* pstBfInitAttr);
+MI_S32 MI_AI_SetBfConfigAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_BfConfigAttr_t* pstBfConfigAttr);
+MI_S32 MI_AI_GetBfConfigAttr(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_AI_BfConfigAttr_t* pstBfConfigAttr);
+MI_S32 MI_AI_EnableBf(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_DisableBf(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn);
+MI_S32 MI_AI_SetBfAngle(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_S32 s32BfAngle);
+MI_S32 MI_AI_SetMute(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_BOOL bMute);
+MI_S32 MI_AI_GetMute(MI_AUDIO_DEV AiDevId, MI_AI_CHN AiChn, MI_BOOL *pbMute);
+MI_S32 MI_AI_InitDev(MI_AI_InitParam_t *pstInitParam);
+MI_S32 MI_AI_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif ///__MI_AI_H__
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ai_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ai_datatype.h
new file mode 100644
index 00000000..20f9ea39
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ai_datatype.h
@@ -0,0 +1,210 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_AI_DATATYPE_H__
+#define __MI_AI_DATATYPE_H__
+
+#include "mi_common_datatype.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//=============================================================================
+// Include files
+//=============================================================================
+
+
+//=============================================================================
+// Extern definition
+//=============================================================================
+
+//=============================================================================
+// Macro definition
+//=============================================================================
+#define MI_AI_DEV_NUM_MAX 4
+#define MI_AI_CHAN_NUM_MAX 4
+
+#define MI_AI_ERR_INVALID_DEVID (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID))
+#define MI_AI_ERR_ILLEGAL_PARAM (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM))
+#define MI_AI_ERR_NOT_ENABLED (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_ENABLE))
+#define MI_AI_ERR_NULL_PTR (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR))
+#define MI_AI_ERR_INVALID_CHNID (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID))
+#define MI_AI_ERR_NOT_CONFIG (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG))
+#define MI_AI_ERR_NOT_SUPPORT (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT))
+#define MI_AI_ERR_NOT_PERM (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM))
+#define MI_AI_ERR_NOMEM (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM))
+#define MI_AI_ERR_NOBUF (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOBUF))
+#define MI_AI_ERR_BUF_EMPTY (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY))
+#define MI_AI_ERR_BUF_FULL (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL))
+#define MI_AI_ERR_SYS_NOTREADY (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY))
+#define MI_AI_ERR_BUSY (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY))
+#define MI_AI_ERR_VQE_ERR (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_AI_VQE_ERR))
+#define MI_AI_ERR_AENC_ERR (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_AI_AENC_ERR))
+#define MI_AI_ERR_AED_ERR (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_AI_AED_ERR))
+#define MI_AI_ERR_SSL_ERR (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_AI_SSL_ERR))
+#define MI_AI_ERR_BF_ERR (MI_DEF_ERR( E_MI_MODULE_ID_AI, E_MI_ERR_LEVEL_ERROR, E_MI_AI_BF_ERR))
+
+//=============================================================================
+// Data type definition
+//=============================================================================
+typedef enum
+{
+ E_MI_AI_VQE_ERR = MI_AI_INITIAL_ERROR_CODE, /* VQE of AI error */
+ E_MI_AI_AENC_ERR,
+ E_MI_AI_AED_ERR,
+ E_MI_AI_SSL_ERR,
+ E_MI_AI_BF_ERR,
+} MI_AI_ErrCode_e;
+
+typedef struct MI_AI_ChnGainConfig_s
+{
+ MI_BOOL bEnableGainSet;
+ MI_S16 s16FrontGain;
+ MI_S16 s16RearGain;
+} MI_AI_ChnGainConfig_t;
+
+typedef struct MI_AI_ChnParam_s
+{
+ MI_AI_ChnGainConfig_t stChnGain;
+ MI_U32 u32Reserved;
+} MI_AI_ChnParam_t;
+
+typedef struct MI_AI_AecConfig_s
+{
+ MI_BOOL bComfortNoiseEnable;
+ MI_S16 s16DelaySample;
+ MI_U32 u32AecSupfreq[6];
+ MI_U32 u32AecSupIntensity[7];
+ MI_S32 s32Reserved;
+} MI_AI_AecConfig_t;
+
+typedef struct MI_AI_VqeConfig_s
+{
+ MI_BOOL bHpfOpen;
+ MI_BOOL bAecOpen;
+ MI_BOOL bAnrOpen;
+ MI_BOOL bAgcOpen;
+ MI_BOOL bEqOpen;
+ MI_U32 u32ChnNum;
+ MI_S32 s32WorkSampleRate;
+ MI_S32 s32FrameSample;
+ MI_AUDIO_HpfConfig_t stHpfCfg;
+ MI_AI_AecConfig_t stAecCfg;
+ MI_AUDIO_AnrConfig_t stAnrCfg;
+ MI_AUDIO_AgcConfig_t stAgcCfg;
+ MI_AUDIO_EqConfig_t stEqCfg;
+} MI_AI_VqeConfig_t;
+
+
+typedef enum{
+ E_MI_AUDIO_AENC_TYPE_G711A = 0,
+ E_MI_AUDIO_AENC_TYPE_G711U,
+ E_MI_AUDIO_AENC_TYPE_G726,
+ E_MI_AUDIO_AENC_TYPE_INVALID,
+} MI_AUDIO_AencType_e;
+
+
+typedef struct MI_AUDIO_AencG711Config_s{
+ MI_AUDIO_SampleRate_e eSamplerate;
+ MI_AUDIO_SoundMode_e eSoundmode;
+} MI_AUDIO_AencG711Config_t;
+
+typedef struct MI_AUDIO_AencG726Config_s{
+ MI_AUDIO_SampleRate_e eSamplerate;
+ MI_AUDIO_SoundMode_e eSoundmode;
+ MI_AUDIO_G726Mode_e eG726Mode;
+} MI_AUDIO_AencG726Config_t;
+
+typedef struct MI_AI_AencConfig_s{
+ MI_AUDIO_AencType_e eAencType;
+ union
+ {
+ MI_AUDIO_AencG711Config_t stAencG711Cfg;
+ MI_AUDIO_AencG726Config_t stAencG726Cfg;
+ };
+} MI_AI_AencConfig_t;
+
+typedef enum
+{
+ E_MI_AUDIO_AED_SEN_LOW,
+ E_MI_AUDIO_AED_SEN_MID,
+ E_MI_AUDIO_AED_SEN_HIGH,
+ E_MI_AUDIO_AED_SEN_INVALID,
+} MI_AUDIO_AedSensitivity_e;
+
+typedef struct MI_AI_AedConfig_s
+{
+ MI_BOOL bEnableNr;
+ MI_AUDIO_AedSensitivity_e eSensitivity;
+ MI_S32 s32OperatingPoint;
+ MI_S32 s32VadThresholdDb;
+ MI_S32 s32LsdThresholdDb;
+} MI_AI_AedConfig_t;
+
+typedef struct MI_AI_AedResult_s
+{
+ MI_BOOL bAcousticEventDetected;
+ MI_BOOL bLoudSoundDetected;
+} MI_AI_AedResult_t;
+
+typedef struct MI_AI_SslInitAttr_s
+{
+ MI_U32 u32MicDistance;
+ MI_BOOL bBfMode;
+} MI_AI_SslInitAttr_t;
+
+typedef struct MI_AI_SslConfigAttr_s
+{
+ MI_S32 s32Temperature;
+ MI_S32 s32NoiseGateDbfs;
+ MI_S32 s32DirectionFrameNum;
+
+} MI_AI_SslConfigAttr_t;
+
+typedef struct MI_AI_BfInitAttr_s
+{
+ MI_U32 u32MicDistance;
+ MI_U32 u32ChanCnt;
+} MI_AI_BfInitAttr_t;
+
+typedef struct MI_AI_BfConfigAttr_s
+{
+ MI_S32 s32Temperature;
+ MI_S32 s32NoiseGateDbfs;
+ MI_S32 s32NoiseSupressionMode;
+ MI_S32 s32NoiseEstimation;
+ MI_FLOAT outputGain;
+} MI_AI_BfConfigAttr_t;
+
+typedef struct MI_AI_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_AI_InitParam_t;
+
+//=============================================================================
+// Variable definition
+//=============================================================================
+
+
+//=============================================================================
+// Global function definition
+//=============================================================================
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__MI_AI_DATATYPE_H__
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_aio.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_aio.h
new file mode 100644
index 00000000..3e963bc1
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_aio.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_AIO_DEP_H_
+#define _MI_AIO_DEP_H_
+
+
+//=============================================================================
+// Include files
+//=============================================================================
+
+
+//=============================================================================
+// Extern definition
+//=============================================================================
+
+//=============================================================================
+// Macro definition
+//=============================================================================
+
+
+//=============================================================================
+// Data type definition
+//=============================================================================
+
+
+
+
+//=============================================================================
+// Variable definition
+//=============================================================================
+
+
+//=============================================================================
+// Global function definition
+//=============================================================================
+
+
+#endif // _MI_AIO_DEP_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_aio_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_aio_datatype.h
new file mode 100644
index 00000000..cb82e312
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_aio_datatype.h
@@ -0,0 +1,224 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_AIO_DEP_DATATYPE_H_
+#define _MI_AIO_DEP_DATATYPE_H_
+
+#include "mi_sys_datatype.h"
+
+//=============================================================================
+// Include files
+//=============================================================================
+
+
+//=============================================================================
+// Extern definition
+//=============================================================================
+
+//=============================================================================
+// Macro definition
+//=============================================================================
+#define MI_AUDIO_MAX_CHN_NUM (16)
+
+
+
+//=============================================================================
+// Data type definition
+//=============================================================================
+typedef enum
+{
+ E_MI_AUDIO_ALGORITHM_MODE_DEFAULT,
+ E_MI_AUDIO_ALGORITHM_MODE_USER,
+ E_MI_AUDIO_ALGORITHM_MODE_MUSIC,
+ E_MI_AUDIO_ALGORITHM_MODE_INVALID,
+}MI_AUDIO_AlgorithmMode_e;
+
+typedef enum
+{
+ E_MI_AUDIO_SAMPLE_RATE_8000 = 8000, /* 8kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_11025 = 11025, /* 11.025kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_12000 = 12000, /* 12kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_16000 = 16000, /* 16kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_22050 = 22050, /* 22.05kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_24000 = 24000, /* 24kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_32000 = 32000, /* 32kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_44100 = 44100, /* 44.1kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_48000 = 48000, /* 48kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_96000 = 96000, /* 96kHz sampling rate */
+ E_MI_AUDIO_SAMPLE_RATE_INVALID,
+}MI_AUDIO_SampleRate_e;
+
+typedef enum
+{
+ E_MI_AUDIO_BIT_WIDTH_16 =0, /* 16bit width */
+ E_MI_AUDIO_BIT_WIDTH_24 =1, /* 24bit width */
+ E_MI_AUDIO_BIT_WIDTH_MAX,
+}MI_AUDIO_BitWidth_e;
+
+typedef enum
+{
+ E_MI_AUDIO_MODE_I2S_MASTER, /* I2S master mode */
+ E_MI_AUDIO_MODE_I2S_SLAVE, /* I2S slave mode */
+ E_MI_AUDIO_MODE_TDM_MASTER, /* TDM master mode */
+ E_MI_AUDIO_MODE_TDM_SLAVE, /* TDM slave mode */
+ E_MI_AUDIO_MODE_MAX,
+}MI_AUDIO_Mode_e;
+
+typedef enum
+{
+ E_MI_AUDIO_SOUND_MODE_MONO = 0, /* mono */
+ E_MI_AUDIO_SOUND_MODE_STEREO = 1, /* stereo */
+ E_MI_AUDIO_SOUND_MODE_QUEUE = 2, /* all data in One chn */
+ E_MI_AUDIO_SOUND_MODE_MAX,
+}MI_AUDIO_SoundMode_e;
+
+typedef enum
+{
+ E_MI_AUDIO_HPF_FREQ_80 = 80, /* 80Hz */
+ E_MI_AUDIO_HPF_FREQ_120 = 120, /* 120Hz */
+ E_MI_AUDIO_HPF_FREQ_150 = 150, /* 150Hz */
+ E_MI_AUDIO_HPF_FREQ_INVALID,
+}MI_AUDIO_HpfFreq_e;
+
+typedef enum {
+ E_MI_AUDIO_NR_SPEED_LOW,
+ E_MI_AUDIO_NR_SPEED_MID,
+ E_MI_AUDIO_NR_SPEED_HIGH
+}MI_AUDIO_NrSpeed_e;
+
+typedef enum
+{
+ E_MI_AUDIO_I2S_FMT_I2S_MSB,
+ E_MI_AUDIO_I2S_FMT_LEFT_JUSTIFY_MSB,
+}MI_AUDIO_I2sFmt_e;
+
+typedef enum{
+ E_MI_AUDIO_I2S_MCLK_0, //not enable
+ E_MI_AUDIO_I2S_MCLK_12_288M, //12.288M
+ E_MI_AUDIO_I2S_MCLK_16_384M, //16.384M
+ E_MI_AUDIO_I2S_MCLK_18_432M, //18.432M
+ E_MI_AUDIO_I2S_MCLK_24_576M, //24.576M
+ E_MI_AUDIO_I2S_MCLK_24M, // 24MHz
+ E_MI_AUDIO_I2S_MCLK_48M, // 48MHz
+}MI_AUDIO_I2sMclk_e;
+
+typedef struct MI_AUDIO_I2sConfig_s
+{
+ MI_AUDIO_I2sFmt_e eFmt;
+ MI_AUDIO_I2sMclk_e eMclk;
+ MI_BOOL bSyncClock; //I2s Tx BCLK, Rx BCLK use the same clock source
+}MI_AUDIO_I2sConfig_t;
+
+typedef struct MI_AUDIO_Attr_s
+{
+ MI_AUDIO_SampleRate_e eSamplerate; /* sample rate */
+ MI_AUDIO_BitWidth_e eBitwidth; /* bitwidth */
+ MI_AUDIO_Mode_e eWorkmode; /* I2s master or slave mode */
+ MI_AUDIO_SoundMode_e eSoundmode; /* mono or stereo */
+ MI_U32 u32FrmNum; /* frame num in buffer */
+ MI_U32 u32PtNumPerFrm; /* number of samples */
+ MI_U32 u32CodecChnCnt; /* channel number on Codec */
+ MI_U32 u32ChnCnt;
+ union{
+ MI_AUDIO_I2sConfig_t stI2sConfig;
+ }WorkModeSetting;
+
+}MI_AUDIO_Attr_t;
+
+typedef struct MI_AUDIO_Frame_s
+{
+ MI_AUDIO_BitWidth_e eBitwidth; /* audio frame bitwidth */
+ MI_AUDIO_SoundMode_e eSoundmode; /* audio frame momo or stereo mode */
+ void *apVirAddr[MI_AUDIO_MAX_CHN_NUM];
+ MI_U64 u64TimeStamp; /* audio frame timestamp */
+ MI_U32 u32Seq; /* audio frame seq */
+ MI_U32 u32Len; /* data lenth per channel in frame */
+ MI_U32 au32PoolId[2];
+ /* Only use for Ai */
+ void *apSrcPcmVirAddr[MI_AUDIO_MAX_CHN_NUM]; /* Ai original pcm data from ai channel */
+ MI_U32 u32SrcPcmLen; /* length of Ai original pcm data */
+
+}MI_AUDIO_Frame_t;
+
+typedef struct MI_AUDIO_AecFrame_s
+{
+ MI_AUDIO_Frame_t stRefFrame; /* aec reference audio frame */
+ MI_BOOL bValid; /* whether frame is valid */
+}MI_AUDIO_AecFrame_t;
+
+typedef struct MI_AUDIO_SaveFileInfo_s
+{
+ MI_BOOL bCfg;
+ MI_U8 szFilePath[256];
+ MI_U32 u32FileSize; /*in KB*/
+}MI_AUDIO_SaveFileInfo_t;
+
+typedef struct MI_AUDIO_HpfConfig_s
+{
+ MI_AUDIO_AlgorithmMode_e eMode;
+ MI_AUDIO_HpfFreq_e eHpfFreq; /*freq to be processed*/
+}MI_AUDIO_HpfConfig_t;
+
+typedef struct MI_AUDIO_AnrConfig_s
+{
+ MI_AUDIO_AlgorithmMode_e eMode;
+ MI_U32 u32NrIntensity;
+ MI_U32 u32NrSmoothLevel;
+ MI_AUDIO_NrSpeed_e eNrSpeed;
+}MI_AUDIO_AnrConfig_t;
+
+typedef struct AgcGainInfo_s{
+ MI_S32 s32GainMax;
+ MI_S32 s32GainMin;
+ MI_S32 s32GainInit;
+}AgcGainInfo_t;
+
+typedef struct MI_AUDIO_AgcConfig_s
+{
+ MI_AUDIO_AlgorithmMode_e eMode;
+ AgcGainInfo_t stAgcGainInfo;
+ MI_U32 u32DropGainMax;
+ MI_U32 u32AttackTime;
+ MI_U32 u32ReleaseTime;
+ MI_S16 s16Compression_ratio_input[5];
+ MI_S16 s16Compression_ratio_output[5];
+ MI_S32 s32TargetLevelDb;
+ MI_S32 s32NoiseGateDb;
+ MI_U32 u32NoiseGateAttenuationDb;
+}MI_AUDIO_AgcConfig_t;
+
+typedef struct MI_AUDIO_EqConfig_s
+{
+ MI_AUDIO_AlgorithmMode_e eMode;
+ MI_S16 s16EqGainDb[129];
+}MI_AUDIO_EqConfig_t;
+
+typedef enum{
+ E_MI_AUDIO_G726_MODE_16 = 0,
+ E_MI_AUDIO_G726_MODE_24,
+ E_MI_AUDIO_G726_MODE_32,
+ E_MI_AUDIO_G726_MODE_40,
+ E_MI_AUDIO_G726_MODE_INVALID,
+}MI_AUDIO_G726Mode_e;
+
+//=============================================================================
+// Variable definition
+//=============================================================================
+
+
+//=============================================================================
+// Global function definition
+//=============================================================================
+
+
+#endif // _MI_AIO_DEP_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ao.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ao.h
new file mode 100644
index 00000000..2df26c94
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ao.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_AO_H__
+#define __MI_AO_H__
+
+#include "mi_aio_datatype.h"
+#include "mi_ao_datatype.h"
+
+#define AO_MAJOR_VERSION 2
+#define AO_SUB_VERSION 11
+#define MACRO_TO_STR(macro) #macro
+#define AO_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_ao_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_ao_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_ao_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_AO_API_VERSION AO_VERSION_STR(AO_MAJOR_VERSION,AO_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//=============================================================================
+// Include files
+//=============================================================================
+
+
+//=============================================================================
+// Extern definition
+//=============================================================================
+
+//=============================================================================
+// Macro definition
+//=============================================================================
+
+
+//=============================================================================
+// Data type definition
+//=============================================================================
+
+
+//=============================================================================
+// Variable definition
+//=============================================================================
+
+
+//=============================================================================
+// Global function definition
+//=============================================================================
+MI_S32 MI_AO_SetPubAttr(MI_AUDIO_DEV AoDevId, MI_AUDIO_Attr_t *pstAttr);
+MI_S32 MI_AO_GetPubAttr(MI_AUDIO_DEV AoDevId, MI_AUDIO_Attr_t *pstAttr);
+MI_S32 MI_AO_Enable(MI_AUDIO_DEV AoDevId);
+MI_S32 MI_AO_Disable(MI_AUDIO_DEV AoDevId);
+MI_S32 MI_AO_EnableChn(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_DisableChn(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_SendFrame(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AUDIO_Frame_t *pstData, MI_S32 s32MilliSec);
+MI_S32 MI_AO_EnableReSmp(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AUDIO_SampleRate_e eInSampleRate);
+MI_S32 MI_AO_DisableReSmp(MI_AUDIO_DEV AiDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_PauseChn(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_ResumeChn(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_ClearChnBuf(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_QueryChnStat(MI_AUDIO_DEV AoDevId , MI_AO_CHN AoChn, MI_AO_ChnState_t *pstStatus);
+MI_S32 MI_AO_SetVolume(MI_AUDIO_DEV AoDevId, MI_S32 s32VolumeDb);
+MI_S32 MI_AO_GetVolume(MI_AUDIO_DEV AoDevId, MI_S32 *ps32VolumeDb);
+MI_S32 MI_AO_SetMute(MI_AUDIO_DEV AoDevId, MI_BOOL bEnable);
+MI_S32 MI_AO_GetMute(MI_AUDIO_DEV AoDevId, MI_BOOL *pbEnable);
+MI_S32 MI_AO_ClrPubAttr(MI_AUDIO_DEV AoDevId);
+MI_S32 MI_AO_SetVqeAttr(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AO_VqeConfig_t *pstVqeConfig);
+MI_S32 MI_AO_GetVqeAttr(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AO_VqeConfig_t *pstVqeConfig);
+MI_S32 MI_AO_EnableVqe(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_DisableVqe(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_SetAdecAttr(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AO_AdecConfig_t *pstAdecConfig);
+MI_S32 MI_AO_GetAdecAttr(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AO_AdecConfig_t *pstAdecConfig);
+MI_S32 MI_AO_EnableAdec(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_DisableAdec(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn);
+MI_S32 MI_AO_SetChnParam(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AO_ChnParam_t *pstChnParam);
+MI_S32 MI_AO_GetChnParam(MI_AUDIO_DEV AoDevId, MI_AO_CHN AoChn, MI_AO_ChnParam_t *pstChnParam);
+MI_S32 MI_AO_SetSrcGain(MI_AUDIO_DEV AoDevId, MI_S32 s32VolumeDb);
+MI_S32 MI_AO_InitDev(MI_AO_InitParam_t *pstInitParam);
+MI_S32 MI_AO_DeInitDev(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif///__MI_AO_H__
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ao_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ao_datatype.h
new file mode 100644
index 00000000..c3799a42
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ao_datatype.h
@@ -0,0 +1,145 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_AO_DATATYPE_H__
+#define __MI_AO_DATATYPE_H__
+
+#include "mi_common_datatype.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//=============================================================================
+// Include files
+//=============================================================================
+
+
+//=============================================================================
+// Extern definition
+//=============================================================================
+
+//=============================================================================
+// Macro definition
+//=============================================================================
+#define MI_AO_DEV_NUM_MAX 4
+#define MI_AO_CHAN_NUM_MAX 1
+
+#define MI_AO_ERR_INVALID_DEVID (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID))
+#define MI_AO_ERR_ILLEGAL_PARAM (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM))
+#define MI_AO_ERR_NOT_ENABLED (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_ENABLE))
+#define MI_AO_ERR_NULL_PTR (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR))
+#define MI_AO_ERR_INVALID_CHNID (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID))
+#define MI_AO_ERR_NOT_CONFIG (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG))
+#define MI_AO_ERR_NOT_SUPPORT (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT))
+#define MI_AO_ERR_NOT_PERM (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM))
+#define MI_AO_ERR_NOMEM (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM))
+#define MI_AO_ERR_NOBUF (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOBUF))
+#define MI_AO_ERR_BUF_EMPTY (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY))
+#define MI_AO_ERR_BUF_FULL (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL))
+#define MI_AO_ERR_SYS_NOTREADY (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY))
+#define MI_AO_ERR_BUSY (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY))
+#define MI_AO_ERR_VQE_ERR (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_AO_VQE_ERR))
+#define MI_AO_ERR_ADEC_ERR (MI_DEF_ERR( E_MI_MODULE_ID_AO, E_MI_ERR_LEVEL_ERROR, E_MI_AO_ADEC_ERR))
+//=============================================================================
+// Data type definition
+//=============================================================================
+typedef enum
+{
+ E_MI_AO_VQE_ERR = MI_AO_INITIAL_ERROR_CODE, /* VQE of AO error */
+ E_MI_AO_ADEC_ERR, //ADEC of AO error
+}MI_AO_ErrCode_e;
+
+
+typedef struct MI_AO_ChnState_s
+{
+ MI_U32 u32ChnTotalNum;
+ MI_U32 u32ChnFreeNum;
+ MI_U32 u32ChnBusyNum;
+} MI_AO_ChnState_t;
+
+typedef struct MI_AO_VqeConfig_s
+{
+ MI_BOOL bHpfOpen;
+ MI_BOOL bAnrOpen;
+ MI_BOOL bAgcOpen;
+ MI_BOOL bEqOpen;
+ MI_S32 s32WorkSampleRate;
+ MI_S32 s32FrameSample;
+ MI_AUDIO_HpfConfig_t stHpfCfg;
+ MI_AUDIO_AnrConfig_t stAnrCfg;
+ MI_AUDIO_AgcConfig_t stAgcCfg;
+ MI_AUDIO_EqConfig_t stEqCfg;
+}MI_AO_VqeConfig_t;
+
+typedef enum{
+ E_MI_AUDIO_ADEC_TYPE_G711A = 0,
+ E_MI_AUDIO_ADEC_TYPE_G711U,
+ E_MI_AUDIO_ADEC_TYPE_G726,
+ E_MI_AUDIO_ADEC_TYPE_INVALID,
+}MI_AUDIO_AdecType_e;
+
+
+typedef struct MI_AUDIO_AdecG711Config_s{
+ MI_AUDIO_SampleRate_e eSamplerate;
+ MI_AUDIO_SoundMode_e eSoundmode;
+}MI_AUDIO_AdecG711Config_t;
+
+typedef struct MI_AUDIO_AdecG726Config_s{
+ MI_AUDIO_SampleRate_e eSamplerate;
+ MI_AUDIO_SoundMode_e eSoundmode;
+ MI_AUDIO_G726Mode_e eG726Mode;
+}MI_AUDIO_AdecG726Config_t;
+
+typedef struct MI_AO_AdecConfig_s{
+ MI_AUDIO_AdecType_e eAdecType;
+ union
+ {
+ MI_AUDIO_AdecG711Config_t stAdecG711Cfg;
+ MI_AUDIO_AdecG726Config_t stAdecG726Cfg;
+ };
+}MI_AO_AdecConfig_t;
+
+typedef struct MI_AO_ChnGainConfig_s
+{
+ MI_BOOL bEnableGainSet;
+ MI_S16 s16Gain;
+}MI_AO_ChnGainConfig_t;
+
+typedef struct MI_AO_ChnParam_s
+{
+ MI_AO_ChnGainConfig_t stChnGain;
+ MI_U32 u32Reserved;
+} MI_AO_ChnParam_t;
+
+typedef struct MI_AO_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_AO_InitParam_t;
+
+//=============================================================================
+// Variable definition
+//=============================================================================
+
+
+//=============================================================================
+// Global function definition
+//=============================================================================
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__MI_AO_DATATYPE_H__
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_cipher.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_cipher.h
new file mode 100644
index 00000000..48796f05
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_cipher.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_CIPHER_H_
+#define _MI_CIPHER_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+#include "mi_cipher_datatype.h"
+
+#define CIPHER_MAJOR_VERSION 2
+#define CIPHER_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define CIPHER_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_cipher_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_cipher_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_cipher_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_CIPHER_API_VERSION CIPHER_VERSION_STR(CIPHER_MAJOR_VERSION,CIPHER_SUB_VERSION)
+
+MI_S32 MI_CIPHER_Init(void);
+MI_S32 MI_CIPHER_Uninit (void);
+MI_S32 MI_CIPHER_CreateHandle(MI_HANDLE *phandle);
+MI_S32 MI_CIPHER_DestroyHandle(MI_HANDLE handle);
+MI_S32 MI_CIPHER_ConfigHandle(MI_HANDLE handle, MI_CIPHER_Config_t *pconfig);
+MI_S32 MI_CIPHER_Encrypt(MI_HANDLE handle, void* srcAddr, void* dstAddr , MI_U32 u32ByteLen, MI_U32 *pu32dstByteLen);
+MI_S32 MI_CIPHER_Decrypt(MI_HANDLE handle, void* srcAddr, void* dstAddr, MI_U32 u32ByteLen, MI_U32 *pu32dstByteLen);
+MI_S32 MI_CIPHER_HashInit(MI_CIPHER_HASH_ALGO_e eHashAlgoType, MI_HANDLE *pHashHandle);
+MI_S32 MI_CIPHER_HashUnInit(MI_HANDLE hHashHandle);
+MI_S32 MI_CIPHER_HashUpdate(MI_HANDLE hHashHandle , MI_U8 *pu8InputData, MI_U32 u32IDataLen);
+MI_S32 MI_CIPHER_HashFinal(MI_HANDLE hHashHandle, MI_U8 *pu8OutputHash, MI_U32 *pu32OutputHashLen);
+MI_S32 MI_CIPHER_RsaPublicEncrypt(MI_CIPHER_RSA_PUB_ENC_t *pstRsa, MI_U8 *pu8Input, MI_U32 u32InLen, MI_U8 *pu8Output, MI_U32 *pu32OutLen);
+MI_S32 MI_CIPHER_RsaPrivateDecrypt(MI_CIPHER_RSA_PRI_ENC_t *pstRsa, MI_U8 *pu8Input, MI_U32 u32InLen, MI_U8 *pu8Output, MI_U32 *pu32OutLen);
+MI_S32 MI_CIPHER_RsaPrivateEncrypt(MI_CIPHER_RSA_PRI_ENC_t *pstRsa, MI_U8 *pu8Input, MI_U32 u32InLen, MI_U8 *pu8Output, MI_U32 *pu32OutLen);
+MI_S32 MI_CIPHER_RsaPublicDecrypt(MI_CIPHER_RSA_PUB_ENC_t *pstRsa, MI_U8 *pu8Input, MI_U32 u32InLen, MI_U8 *pu8Output, MI_U32 *pu32OutLen);
+MI_S32 MI_CIPHER_RsaSign(MI_CIPHER_RSA_SIGN_t *pstRsaSign, MI_U8 *pu8InHashData, MI_U32 u32HashDataLen, MI_U8 *pu8OutSign, MI_U32 *pu32OutSignLen);
+MI_S32 MI_CIPHER_RsaVerify(MI_CIPHER_RSA_VERIFY_t *pstRsaVerify, MI_U8 *pu8InHashData, MI_U32 u32HashDataLen, MI_U8 *pu8InSign, MI_U32 u32InSignLen);
+MI_S32 MI_CIPHER_InitDev(MI_CIPHER_InitParam_t *pstInitParam);
+MI_S32 MI_CIPHER_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif ///_MI_CIPHER_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_cipher_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_cipher_datatype.h
new file mode 100644
index 00000000..b2a684a9
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_cipher_datatype.h
@@ -0,0 +1,164 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_CIPHER_DATATYPE_H_
+#define _MI_CIPHER_DATATYPE_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+#include "mi_common_datatype.h"
+
+/* min length of encrypt, unit: byte*/
+#define MI_CIPHER_MIN_CRYPT_LEN 8
+
+/*max length of encrypt, unit: byte*/
+#define MI_CIPHER_MAX_CRYPT_LEN 0xfffff
+
+#define MI_CIPHER_KEY_SIZE_MAX 32
+#define MI_CIPHER_AES_BLOCK_SIZE 16
+#define MI_CIPHER_MAX_DEVICE_NUM 1
+#define CIPHER_MAX_RSA_KEY_LEN (512)
+#define DRV_MAX_RSA_KEY_LEN (128)
+
+
+/*-------------------------------------------------------------------------------------------------
+ * Enum
+ ------------------------------------------------------------------------------------------------*/
+ /*cipher work mode*/
+typedef enum
+{
+ MI_CIPHER_ALG_AES_ECB = 0,
+ MI_CIPHER_ALG_AES_CBC,
+ MI_CIPHER_ALG_AES_CTR,
+} MI_CIPHER_ALG_e;
+
+typedef enum
+{
+ MI_CIPHER_HASH_ALG_SHA1,
+ MI_CIPHER_HASH_ALG_SHA256,
+ MI_CIPHER_HASH_TYPE_BUTT,
+} MI_CIPHER_HASH_ALGO_e;
+
+typedef enum
+{
+ MI_CIPHER_RSA_ENC_SCHEME_NO_PADDING, /**< without padding */
+ MI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA1, /**< PKCS#1 RSAES-OAEP-SHA1 padding*/
+ MI_CIPHER_RSA_ENC_SCHEME_RSAES_OAEP_SHA256, /**< PKCS#1 RSAES-OAEP-SHA256 padding*/
+ MI_CIPHER_RSA_ENC_SCHEME_RSAES_PKCS1_V1_5, /**< PKCS#1 RSAES-PKCS1_V1_5 padding*/
+ MI_CIPHER_RSA_ENC_SCHEME_BUTT,
+}MI_CIPHER_RSA_ENC_SCHEME_E;
+
+typedef enum
+{
+ MI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA1 = 0x100, /**< PKCS#1 RSASSA_PKCS1_V15_SHA1 signature*/
+ MI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_V15_SHA256, /**< PKCS#1 RSASSA_PKCS1_V15_SHA256 signature*/
+ MI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA1, /**< PKCS#1 RSASSA_PKCS1_PSS_SHA1 signature*/
+ MI_CIPHER_RSA_SIGN_SCHEME_RSASSA_PKCS1_PSS_SHA256, /**< PKCS#1 RSASSA_PKCS1_PSS_SHA256 signature*/
+ MI_CIPHER_RSA_SIGN_SCHEME_BUTT,
+}MI_CIPHER_RSA_SIGN_SCHEME_E;
+
+/*-------------------------------------------------------------------------------------------------
+ * Defines
+ ------------------------------------------------------------------------------------------------*/
+
+/* CIPHER Module ErrorCode */
+#define MI_CIPHER_ERR_INVALID_DEVID (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID))
+#define MI_CIPHER_ERR_ILLEGAL_PARAM (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM))
+#define MI_CIPHER_ERR_NOT_ENABLED (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_ENABLE))
+#define MI_CIPHER_ERR_NOT_DISABLED (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_DISABLE))
+#define MI_CIPHER_ERR_NULL_PTR (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR))
+#define MI_CIPHER_ERR_INVALID_CHNID (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID))
+#define MI_CIPHER_ERR_NOT_CONFIG (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG))
+#define MI_CIPHER_ERR_NOT_SUPPORT (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT))
+#define MI_CIPHER_ERR_NOT_PERM (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM))
+#define MI_CIPHER_ERR_NOMEM (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM))
+#define MI_CIPHER_ERR_NOBUF (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOBUF))
+#define MI_CIPHER_ERR_BUF_EMPTY (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY))
+#define MI_CIPHER_ERR_BUF_FULL (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL))
+#define MI_CIPHER_ERR_SYS_NOTREADY (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY))
+#define MI_CIPHER_ERR_BUSY (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY))
+#define MI_CIPHER_ERR_MOD_NOTINIT (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_INIT))
+#define MI_CIPHER_ERR_MOD_INITED (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INITED))
+#define MI_CIPHER_ERR_FAILED (MI_DEF_ERR( E_MI_MODULE_ID_CIPHER, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED))
+
+
+/*-------------------------------------------------------------------------------------------------
+ * Structures
+ ------------------------------------------------------------------------------------------------*/
+// bits
+typedef enum {
+ E_MI_CIPHER_KEY_SIZE_128 = 0,
+ E_MI_CIPHER_KEY_SIZE_192,
+ E_MI_CIPHER_KEY_SIZE_256,
+} MI_CIPHER_KeySize_e;
+
+typedef struct MI_CIPHER_Config_s
+{
+ MI_CIPHER_KeySize_e eKeySize;
+ MI_U8 key[MI_CIPHER_KEY_SIZE_MAX];
+ MI_U8 iv[MI_CIPHER_AES_BLOCK_SIZE];
+ MI_CIPHER_ALG_e eAlg;
+} MI_CIPHER_Config_t;
+
+typedef struct MI_CIPHER_RSA_PUB_Key_s
+{
+ MI_U8* pu8ExpE;
+ MI_U8* pu8ModN;
+ MI_U32 expSize;
+ MI_U32 modSize;
+} MI_CIPHER_RSA_PUB_Key_t;
+
+typedef struct MI_CIPHER_RSA_PRI_Key_s
+{
+ MI_U8* pu8ExpD;
+ MI_U8* pu8ModN;
+ MI_U32 expSize;
+ MI_U32 modSize;
+} MI_CIPHER_RSA_PRI_Key_t;
+
+typedef struct MI_CIPHER_RSA_PUB_ENC_s
+{
+ MI_CIPHER_RSA_ENC_SCHEME_E eRsaAlgoType;
+ MI_CIPHER_RSA_PUB_Key_t stPubKey;
+} MI_CIPHER_RSA_PUB_ENC_t;
+
+typedef struct MI_CIPHER_RSA_PRI_ENC_s
+{
+ MI_CIPHER_RSA_ENC_SCHEME_E eRsaAlgoType;
+ MI_CIPHER_RSA_PRI_Key_t stPriKey;
+} MI_CIPHER_RSA_PRI_ENC_t;
+
+typedef struct MI_CIPHER_RSA_SIGN_s
+{
+ MI_CIPHER_RSA_SIGN_SCHEME_E eRsaAlgoType;
+ MI_CIPHER_RSA_PRI_Key_t stPriKey;
+} MI_CIPHER_RSA_SIGN_t;
+
+typedef struct MI_CIPHER_RSA_VERIFY_s
+{
+ MI_CIPHER_RSA_SIGN_SCHEME_E eRsaAlgoType;
+ MI_CIPHER_RSA_PUB_Key_t stPubKey;
+} MI_CIPHER_RSA_VERIFY_t;
+
+typedef struct MI_CIPHER_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_CIPHER_InitParam_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif //_MI_CIPHER_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_common.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_common.h
new file mode 100644
index 00000000..05662267
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_common.h
@@ -0,0 +1,28 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_COMMON_H_
+#define _MI_COMMON_H_
+
+#include "mi_common_datatype.h"
+
+#define COMMON_MAJOR_VERSION 2
+#define COMMON_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define COMMON_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_common_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_common_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_common_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_COMMON_API_VERSION COMMON_VERSION_STR(COMMON_MAJOR_VERSION,COMMON_SUB_VERSION)
+
+#endif///_MI_COMMON_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_common_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_common_datatype.h
new file mode 100644
index 00000000..eb2c8bfb
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_common_datatype.h
@@ -0,0 +1,266 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_COMMON_DATATYPE_H_
+#define _MI_COMMON_DATATYPE_H_
+
+//-------------------------------------------------------------------------------------------------
+// System Data Type
+//-------------------------------------------------------------------------------------------------
+/// data type unsigned char, data length 1 byte
+typedef unsigned char MI_U8; // 1 byte
+/// data type unsigned short, data length 2 byte
+typedef unsigned short MI_U16; // 2 bytes
+/// data type unsigned int, data length 4 byte
+typedef unsigned int MI_U32; // 4 bytes
+/// data type unsigned int, data length 8 byte
+typedef unsigned long long MI_U64; // 8 bytes
+/// data type signed char, data length 1 byte
+typedef signed char MI_S8; // 1 byte
+/// data type signed short, data length 2 byte
+typedef signed short MI_S16; // 2 bytes
+/// data type signed int, data length 4 byte
+typedef signed int MI_S32; // 4 bytes
+/// data type signed int, data length 8 byte
+typedef signed long long MI_S64; // 8 bytes
+/// data type float, data length 4 byte
+typedef float MI_FLOAT; // 4 bytes
+/// data type 64bit physical address
+typedef unsigned long long MI_PHY; // 8 bytes
+/// data type pointer content
+typedef unsigned long MI_VIRT; // 4 bytes when 32bit toolchain, 8 bytes when 64bit toolchain.
+
+typedef unsigned char MI_BOOL;
+
+//-------------------------------------------------------------------------------------------------
+// Moudle common type
+//-------------------------------------------------------------------------------------------------
+typedef MI_S32 MI_AI_CHN;
+typedef MI_S32 MI_AO_CHN;
+typedef MI_S32 MI_AUDIO_DEV;
+typedef MI_S32 MI_VIF_DEV;
+typedef MI_S32 MI_DISP_DEV;
+typedef MI_S32 MI_DISP_LAYER;
+typedef MI_S32 MI_DISP_CHN;
+typedef MI_S32 MI_VENC_CHN;
+typedef MI_S32 MI_VDEC_CHN;
+typedef MI_S32 MI_IVE_HANDLE;
+typedef MI_S32 MI_VPE_DEV;
+typedef MI_S32 MI_DIVP_CHN;
+typedef MI_U32 MI_RGN_HANDLE;
+typedef MI_U32 MI_SED_CHN;
+typedef MI_S32 MI_HANDLE;
+//-------------------------------------------------------------------------------------------------
+// Macros
+//-------------------------------------------------------------------------------------------------
+#define INIT_ST(st) do { \
+ memset(&st, 0, sizeof(st));\
+ st.u16SizeofStructure = sizeof(st);\
+}while(0)
+
+
+
+//-------------------------------------------------------------------------------------------------
+// Defines
+//-------------------------------------------------------------------------------------------------
+#define MI_HANDLE_NULL (0)
+#define MI_SUCCESS (0)
+#define MI_BIT(_bit_) (1 << (_bit_))
+#define MI_ERR_ID (0x80000000L + 0x20000000L)
+#define MI_IVE_INITIAL_ERROR_CODE (0x80)
+#define MI_VDF_INITIAL_ERROR_CODE (0xA0)
+#define MI_VENC_INITIAL_ERROR_CODE (0xC0)
+#define MI_RGN_INITIAL_ERROR_CODE (0xE0)
+#define MI_AI_INITIAL_ERROR_CODE (0x100)
+#define MI_AO_INITIAL_ERROR_CODE (0x120)
+#define MI_VIF_INITIAL_ERROR_CODE (0x140)
+#define MI_VPE_INITIAL_ERROR_CODE (0x160)
+#define MI_VDEC_INITIAL_ERROR_CODE (0x180)
+#define MI_SYS_INITIAL_ERROR_CODE (0x1A0)
+#define MI_FB_INITIAL_ERROR_CODE (0x1C0)
+#define MI_HDMI_INITIAL_ERROR_CODE (0x1E0)
+#define MI_DIVP_INITIAL_ERROR_CODE (0x200)
+#define MI_GFX_INITIAL_ERROR_CODE (0x220)
+#define MI_VDISP_INITIAL_ERROR_CODE (0x240)
+#define MI_DISP_INITIAL_ERROR_CODE (0x260)
+#define MI_WARP_INITIAL_ERROR_CODE (0x280)
+#define MI_CV_INITIAL_ERROR_CODE (0x2A0)
+#define MI_CEVA_INITIAL_ERROR_CODE (0x2C0)
+#define MI_UAC_INITIAL_ERROR_CODE (0x2E0)
+#define MI_LDC_INITIAL_ERROR_CODE (0x300)
+
+#ifndef UNUSED
+#define UNUSED(var) (void)((var) = (var))
+#endif
+
+/******************************************************************************
+|----------------------------------------------------------------|
+| 1 | APP_ID | MOD_ID | ERR_LEVEL | ERR_ID |
+|----------------------------------------------------------------|
+|<--><--7bits----><----8bits---><--4bits---><------12bits------->|
+******************************************************************************/
+
+#define MI_DEF_ERR( module, level, errid) \
+ ((MI_S32)( (MI_ERR_ID) | ((module) << 16 ) | ((level)<<12) | (errid) ))
+
+
+#ifndef __KERNEL__
+/// data type null pointer
+#ifdef NULL
+#undef NULL
+#endif
+#define NULL 0
+
+
+#if !defined(__cplusplus)
+#ifndef true
+/// definition for true
+#define true 1
+/// definition for false
+#define false 0
+#endif
+#endif
+
+#if !defined(TRUE) && !defined(FALSE)
+/// definition for TRUE
+#define TRUE 1
+/// definition for FALSE
+#define FALSE 0
+#endif
+#endif
+
+#define TO_STR_NATIVE(e) #e
+#define TO_STR_PROXY(m, e) m(e)
+#define MACRO_TO_STRING(e) TO_STR_PROXY(TO_STR_NATIVE, e)
+#define COMPILE_DATE_TIME() __DATE__ __TIME__
+
+///ASCII color code
+#define ASCII_COLOR_RED "\033[1;31m"
+#define ASCII_COLOR_WHITE "\033[1;37m"
+#define ASCII_COLOR_YELLOW "\033[1;33m"
+#define ASCII_COLOR_BLUE "\033[1;36m"
+#define ASCII_COLOR_GREEN "\033[1;32m"
+#define ASCII_COLOR_END "\033[0m"
+
+//-------------------------------------------------------------------------------------------------
+// Structures
+//-------------------------------------------------------------------------------------------------
+
+
+
+//-------------------------------------------------------------------------------------------------
+// Enum
+//-------------------------------------------------------------------------------------------------
+typedef enum
+{
+ E_MI_MODULE_ID_IVE = 0,
+ E_MI_MODULE_ID_VDF = 1,
+ E_MI_MODULE_ID_VENC = 2,
+ E_MI_MODULE_ID_RGN = 3,
+ E_MI_MODULE_ID_AI = 4,
+ E_MI_MODULE_ID_AO = 5,
+ E_MI_MODULE_ID_VIF = 6,
+ E_MI_MODULE_ID_VPE = 7,
+ E_MI_MODULE_ID_VDEC = 8,
+ E_MI_MODULE_ID_SYS = 9,
+ E_MI_MODULE_ID_FB = 10,
+ E_MI_MODULE_ID_HDMI = 11,
+ E_MI_MODULE_ID_DIVP = 12,
+ E_MI_MODULE_ID_GFX = 13,
+ E_MI_MODULE_ID_VDISP = 14,
+ E_MI_MODULE_ID_DISP = 15,
+ E_MI_MODULE_ID_OS = 16,
+ E_MI_MODULE_ID_IAE = 17,
+ E_MI_MODULE_ID_MD = 18,
+ E_MI_MODULE_ID_OD = 19,
+ E_MI_MODULE_ID_SHADOW = 20,
+ E_MI_MODULE_ID_WARP = 21,
+ E_MI_MODULE_ID_UAC = 22,
+ E_MI_MODULE_ID_LDC = 23,
+ E_MI_MODULE_ID_SD = 24,
+ E_MI_MODULE_ID_PANEL = 25,
+ E_MI_MODULE_ID_CIPHER = 26,
+ E_MI_MODULE_ID_SNR = 27,
+ E_MI_MODULE_ID_WLAN =28,
+ E_MI_MODULE_ID_IPU = 29,
+ E_MI_MODULE_ID_MIPITX = 30,
+ E_MI_MODULE_ID_GYRO = 31,
+ //E_MI_MODULE_ID_SED = 29,
+ E_MI_MODULE_ID_MAX,
+} MI_ModuleId_e;
+
+typedef enum
+{
+ E_MI_ERR_LEVEL_INFO, /* informational */
+ E_MI_ERR_LEVEL_WARNING, /* warning conditions */
+ E_MI_ERR_LEVEL_ERROR, /* error conditions */
+ E_MI_ERR_LEVEL_BUTT
+} MI_ErrLevel_e;
+
+typedef enum
+{
+ E_MI_ERR_INVALID_DEVID = 1, /* invlalid device ID */
+ E_MI_ERR_INVALID_CHNID = 2, /* invlalid channel ID */
+ E_MI_ERR_ILLEGAL_PARAM = 3, /* at lease one parameter is illagal
+ ** eg, an illegal enumeration value */
+ E_MI_ERR_EXIST = 4, /* resource exists */
+ E_MI_ERR_UNEXIST = 5,/* resource unexists */
+ E_MI_ERR_NULL_PTR = 6, /* using a NULL point */
+ E_MI_ERR_NOT_CONFIG = 7, /* try to enable or initialize system, device
+ ** or channel, before configing attribute */
+ E_MI_ERR_NOT_SUPPORT = 8, /* operation or type is not supported by NOW */
+ E_MI_ERR_NOT_PERM = 9, /* operation is not permitted
+ ** eg, try to change static attribute */
+ E_MI_ERR_NOMEM = 12,/* failure caused by malloc memory */
+ E_MI_ERR_NOBUF = 13,/* failure caused by malloc buffer */
+ E_MI_ERR_BUF_EMPTY = 14,/* no data in buffer */
+ E_MI_ERR_BUF_FULL = 15,/* no buffer for new data */
+ E_MI_ERR_SYS_NOTREADY = 16,/* System is not ready,maybe not initialed or
+ ** loaded. Returning the error code when opening
+ ** a device file failed. */
+ E_MI_ERR_BADADDR = 17,/* bad address,
+ ** eg. used for copy_from_user & copy_to_user */
+ E_MI_ERR_BUSY = 18,/* resource is busy,
+ ** eg. destroy a venc chn without unregister it */
+ E_MI_ERR_CHN_NOT_STARTED = 19,/* channel not start*/
+ E_MI_ERR_CHN_NOT_STOPED = 20,/* channel not stop*/
+ E_MI_ERR_NOT_INIT = 21,/* module not init before use it*/
+ E_MI_ERR_INITED = 22,/* module already init*/
+ E_MI_ERR_NOT_ENABLE = 23,/* device channel or port not enable*/
+ E_MI_ERR_NOT_DISABLE = 24,/* device channel or port not disable*/
+ E_MI_ERR_SYS_TIMEOUT = 25,/* sys timeout*/
+ E_MI_ERR_DEV_NOT_STARTED = 26,/* device not started*/
+ E_MI_ERR_DEV_NOT_STOPED = 27,/* device not stoped*/
+ E_MI_ERR_CHN_NO_CONTENT = 28,/* there is no content in the channel.*/
+ E_MI_ERR_NOVASPACE = 29,/* failure caused by va mmap */
+ E_MI_ERR_NOITEM = 30,/* no item record in ringpool */
+ E_MI_ERR_FAILED ,/* unexpected error */
+
+ E_MI_ERR_MAX = 127,/* maxium code, private error code of all modules
+ ** must be greater than it */
+}MI_ErrCode_e;
+
+typedef enum
+{
+ MI_DBG_NONE = 0,
+ MI_DBG_ERR,
+ MI_DBG_WRN,
+ MI_DBG_API,
+ MI_DBG_KMSG,
+ MI_DBG_INFO,
+ MI_DBG_DEBUG,
+ MI_DBG_TRACE,
+ MI_DBG_ALL
+}MI_DBG_LEVEL_e;
+
+#endif///_MI_COMMON_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_disp.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_disp.h
new file mode 100644
index 00000000..89091473
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_disp.h
@@ -0,0 +1,85 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_DISP_H_
+#define _MI_DISP_H_
+
+#include "mi_disp_datatype.h"
+
+#define DISP_MAJOR_VERSION 2
+#define DISP_SUB_VERSION 9
+#define MACRO_TO_STR(macro) #macro
+#define DISP_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_disp_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_disp_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_disp_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_DISP_API_VERSION DISP_VERSION_STR(DISP_MAJOR_VERSION,DISP_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_DISP_Enable(MI_DISP_DEV DispDev);
+MI_S32 MI_DISP_Disable(MI_DISP_DEV DispDev);
+MI_S32 MI_DISP_SetPubAttr(MI_DISP_DEV DispDev, const MI_DISP_PubAttr_t *pstPubAttr);
+MI_S32 MI_DISP_GetPubAttr(MI_DISP_DEV DispDev, MI_DISP_PubAttr_t *pstPubAttr);
+MI_S32 MI_DISP_DeviceAttach(MI_DISP_DEV DispSrcDev, MI_DISP_DEV DispDstDev);
+MI_S32 MI_DISP_DeviceDetach(MI_DISP_DEV DispSrcDev, MI_DISP_DEV DispDstDev);
+MI_S32 MI_DISP_EnableVideoLayer(MI_DISP_LAYER DispLayer);
+MI_S32 MI_DISP_DisableVideoLayer(MI_DISP_LAYER DispLayer);
+MI_S32 MI_DISP_SetVideoLayerAttr(MI_DISP_LAYER DispLayer, const MI_DISP_VideoLayerAttr_t *pstLayerAttr);
+MI_S32 MI_DISP_GetVideoLayerAttr(MI_DISP_LAYER DispLayer, MI_DISP_VideoLayerAttr_t *pstLayerAttr);
+MI_S32 MI_DISP_BindVideoLayer(MI_DISP_LAYER DispLayer, MI_DISP_DEV DispDev);
+MI_S32 MI_DISP_UnBindVideoLayer(MI_DISP_LAYER DispLayer, MI_DISP_DEV DispDev);
+MI_S32 MI_DISP_SetPlayToleration(MI_DISP_LAYER DispLayer, MI_U32 u32Toleration);
+MI_S32 MI_DISP_GetPlayToleration(MI_DISP_LAYER DispLayer, MI_U32 *pu32Toleration);
+MI_S32 MI_DISP_GetScreenFrame(MI_DISP_LAYER DispLayer, MI_DISP_VideoFrame_t *pstVFrame);
+MI_S32 MI_DISP_ReleaseScreenFrame(MI_DISP_LAYER DispLayer, MI_DISP_VideoFrame_t *pstVFrame);
+MI_S32 MI_DISP_SetVideoLayerAttrBegin(MI_DISP_LAYER DispLayer);
+MI_S32 MI_DISP_SetVideoLayerAttrEnd(MI_DISP_LAYER DispLayer);
+MI_S32 MI_DISP_SetInputPortAttr(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, const MI_DISP_InputPortAttr_t *pstInputPortAttr);
+MI_S32 MI_DISP_GetInputPortAttr(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, MI_DISP_InputPortAttr_t *pstInputPortAttr);
+MI_S32 MI_DISP_EnableInputPort (MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort);
+MI_S32 MI_DISP_DisableInputPort(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort);
+MI_S32 MI_DISP_SetInputPortDispPos(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, const MI_DISP_Position_t *pstDispPos);
+MI_S32 MI_DISP_GetInputPortDispPos(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, MI_DISP_Position_t *pstDispPos);
+MI_S32 MI_DISP_PauseInputPort (MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort);
+MI_S32 MI_DISP_ResumeInputPort (MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort);
+MI_S32 MI_DISP_StepInputPort(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort);
+MI_S32 MI_DISP_ShowInputPort(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort);
+MI_S32 MI_DISP_HideInputPort(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort);
+MI_S32 MI_DISP_SetInputPortSyncMode (MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, MI_DISP_SyncMode_e eMode);
+MI_S32 MI_DISP_QueryInputPortStat(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, MI_DISP_QueryChannelStatus_t *pstStatus);
+MI_S32 MI_DISP_SetZoomInWindow(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, MI_DISP_VidWinRect_t* pstZoomRect);
+MI_S32 MI_DISP_GetVgaParam(MI_DISP_DEV DispDev, MI_DISP_VgaParam_t *pstVgaParam);
+MI_S32 MI_DISP_SetVgaParam(MI_DISP_DEV DispDev, MI_DISP_VgaParam_t *pstVgaParam);
+MI_S32 MI_DISP_GetHdmiParam(MI_DISP_DEV DispDev, MI_DISP_HdmiParam_t *pstHdmiParam);
+MI_S32 MI_DISP_SetHdmiParam(MI_DISP_DEV DispDev, MI_DISP_HdmiParam_t *pstHdmiParam);
+MI_S32 MI_DISP_GetLcdParam(MI_DISP_DEV DispDev, MI_DISP_LcdParam_t *pstLcdParam);
+MI_S32 MI_DISP_SetLcdParam(MI_DISP_DEV DispDev, MI_DISP_LcdParam_t *pstLcdParam);
+MI_S32 MI_DISP_GetCvbsParam(MI_DISP_DEV DispDev, MI_DISP_CvbsParam_t *pstCvbsParam);
+MI_S32 MI_DISP_SetCvbsParam(MI_DISP_DEV DispDev, MI_DISP_CvbsParam_t *pstCvbsParam);
+MI_S32 MI_DISP_DeviceSetColorTempeture(MI_DISP_DEV DispDev, MI_DISP_ColorTemperature_t *pstColorTempInfo);
+MI_S32 MI_DISP_DeviceGetColorTempeture(MI_DISP_DEV DispDev, MI_DISP_ColorTemperature_t *pstColorTempInfo);
+MI_S32 MI_DISP_DeviceSetGammaParam(MI_DISP_DEV DispDev, MI_DISP_GammaParam_t * pstGammaParam);
+MI_S32 MI_DISP_ClearInputPortBuffer(MI_DISP_LAYER DispLayer, MI_DISP_INPUTPORT LayerInputPort, MI_BOOL bClrAll);
+MI_S32 MI_DISP_SetVideoLayerRotateMode(MI_DISP_LAYER DispLayer, MI_DISP_RotateConfig_t *pstRotateConfig);
+MI_S32 MI_DISP_InitDev(MI_DISP_InitParam_t *pstInitParam);
+MI_S32 MI_DISP_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_DISP_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_disp_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_disp_datatype.h
new file mode 100644
index 00000000..4f6b8b19
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_disp_datatype.h
@@ -0,0 +1,336 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_DISP_DATATYPE_H_
+#define _MI_DISP_DATATYPE_H_
+#include "mi_sys_datatype.h"
+
+#define MI_DISP_SUCCESS (0)
+#define MI_DISP_FAIL (1)
+#define MI_ERR_DISP_INVALID_DEVID (0xA00F8001) //The device ID does not fall within the value range.
+#define MI_ERR_DISP_INVALID_CHNID (0xA00F8002) //The channel ID does not fall within the value range.
+#define MI_ERR_DISP_ILLEGAL_PARAM (0xA00F8003) //The parameter value does not fall within the value range.
+#define MI_ERR_DISP_NULL_PTR (0xA00F8006) //The pointer is null.
+#define MI_ERR_DISP_NOT_SUPPORT (0xA00F8008) //The operation is not supported.
+#define MI_ERR_DISP_NOT_PERMIT (0xA00F8009) //The operation is forbidden.
+#define MI_ERR_DISP_NO_MEM (0xA00F800C) //The memory is insufficient.
+#define MI_ERR_DISP_SYS_NOTREADY (0xA00F8010) //The system is not initialized.
+#define MI_ERR_DISP_BUSY (0xA00F8012) //The resources are unavailable.
+#define MI_ERR_DISP_DEV_NOT_CONFIG (0xA00F8040) //The MI_DISP device is not configured.
+#define MI_ERR_DISP_DEV_NOT_ENABLE (0xA00F8041) //The MI_DISP device is not enabled.
+#define MI_ERR_DISP_DEV_HAS_ENABLED (0xA00F8042) //The MI_DISP device has been enabled.
+#define MI_ERR_DISP_DEV_HAS_BINDED (0xA00F8043) //The device has been bound.
+#define MI_ERR_DISP_DEV_NOT_BINDED (0xA00F8044) //The device is not bound.
+#define MI_ERR_DISP_VIDEO_NOT_ENABLE (0xA00F8045) //The video layer is not enabled.
+#define MI_ERR_DISP_VIDEO_NOT_DISABLE (0xA00F8046) //The video layer is not disabled.
+#define MI_ERR_DISP_VIDEO_NOT_CONFIG (0xA00F8047) //The video layer is not configured.
+#define MI_ERR_DISP_CHN_NOT_DISABLE (0xA00F8048) //The MI_DISP input port is not disabled.
+#define MI_ERR_DISP_CHN_NOT_ENABLE (0xA00F8049) //No MI_DISP input port is enabled.
+#define MI_ERR_DISP_CHN_NOT_CONFIG (0xA00F804A) //The MI_DISP input port is not configured.
+#define MI_ERR_DISP_CHN_NOT_ALLOC (0xA00F804B) //No MI_DISP input port is allocated.
+#define MI_ERR_DISP_INVALID_PATTERN (0xA00F804C) //The pattern is invalid.
+#define MI_ERR_DISP_INVALID_POSITION (0xA00F804D) //The cascade position is invalid.
+#define MI_ERR_DISP_WAIT_TIMEOUT (0xA00F804E) //Waiting times out.
+#define MI_ERR_DISP_INVALID_VFRAME (0xA00F804F) //The video frame is invalid.
+#define MI_ERR_DISP_INVALID_RECT_PARA (0xA00F8050) //The rectangle parameter is invalid.
+#define MI_ERR_DISP_GFX_NOT_DISABLE (0xA00F8065) //The graphics layer is not disabled.
+#define MI_ERR_DISP_GFX_NOT_BIND (0xA00F8066) //The graphics layer is not bound.
+#define MI_ERR_DISP_GFX_NOT_UNBIND (0xA00F8067) //The graphics layer is not unbound.
+#define MI_ERR_DISP_GFX_INVALID_ID (0xA00F8068) //The graphics layer ID does not fall within the value range.
+#define MI_ERR_DISP_CHN_AREA_OVERLAP (0xA00F806b) //The MI_DISP input port areas overlap.
+#define MI_ERR_DISP_INVALID_LAYERID (0xA00F806d) //The video layer ID does not fall within the value range.
+#define MI_ERR_DISP_VIDEO_HAS_BINDED (0xA00F806e) //The video layer has been bound.
+#define MI_ERR_DISP_VIDEO_NOT_BINDED (0xA00F806f) //The video layer is not bound
+
+#define MI_DISP_DEV_MAX 1
+#define MI_DISP_LAYER_MAX 2
+#define MI_DISP_INPUTPORT_MAX 16
+
+//typedef MI_U32 MI_DISP_DEV;
+//typedef MI_U32 MI_DISP_LAYER;
+typedef MI_U32 MI_DISP_INPUTPORT;
+
+typedef enum
+{
+ E_MI_DISP_INTF_CVBS = 0,
+ E_MI_DISP_INTF_YPBPR,
+ E_MI_DISP_INTF_VGA,
+ E_MI_DISP_INTF_BT656,
+ E_MI_DISP_INTF_BT1120,
+ E_MI_DISP_INTF_HDMI,
+ E_MI_DISP_INTF_LCD,
+ E_MI_DISP_INTF_BT656_H,
+ E_MI_DISP_INTF_BT656_L,
+ E_MI_DISP_INTF_TTL,
+ E_MI_DISP_INTF_MIPIDSI,
+ E_MI_DISP_INTF_TTL_SPI_IF,
+ E_MI_DISP_INTF_MAX,
+}MI_DISP_Interface_e;
+
+typedef enum
+{
+ E_MI_DISP_OUTPUT_PAL = 0,
+ E_MI_DISP_OUTPUT_NTSC,
+ E_MI_DISP_OUTPUT_960H_PAL, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced)*/
+ E_MI_DISP_OUTPUT_960H_NTSC, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced)*/
+
+ E_MI_DISP_OUTPUT_480i60,
+ E_MI_DISP_OUTPUT_576i50,
+ E_MI_DISP_OUTPUT_480P60,
+ E_MI_DISP_OUTPUT_576P50,
+ E_MI_DISP_OUTPUT_720P50,
+ E_MI_DISP_OUTPUT_720P60,
+ E_MI_DISP_OUTPUT_1080P24,
+ E_MI_DISP_OUTPUT_1080P25,
+ E_MI_DISP_OUTPUT_1080P30,
+ E_MI_DISP_OUTPUT_1080I50,
+ E_MI_DISP_OUTPUT_1080I60,
+ E_MI_DISP_OUTPUT_1080P50,
+ E_MI_DISP_OUTPUT_1080P60,
+
+ E_MI_DISP_OUTPUT_640x480_60, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */
+ E_MI_DISP_OUTPUT_800x600_60, /* VESA 800 x 600 at 60 Hz (non-interlaced) */
+ E_MI_DISP_OUTPUT_1024x768_60, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */
+ E_MI_DISP_OUTPUT_1280x1024_60, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */
+ E_MI_DISP_OUTPUT_1366x768_60, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */
+ E_MI_DISP_OUTPUT_1440x900_60, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */
+ E_MI_DISP_OUTPUT_1280x800_60, /* 1280*800@60Hz VGA@60Hz*/
+ E_MI_DISP_OUTPUT_1680x1050_60, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */
+ E_MI_DISP_OUTPUT_1920x2160_30, /* 1920x2160_30 */
+ E_MI_DISP_OUTPUT_1600x1200_60, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */
+ E_MI_DISP_OUTPUT_1920x1200_60, /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking)*/
+
+ E_MI_DISP_OUTPUT_2560x1440_30, /* 2560x1440_30 */
+ E_MI_DISP_OUTPUT_2560x1600_60, /* 2560x1600_60 */
+ E_MI_DISP_OUTPUT_3840x2160_30, /* 3840x2160_30 */
+ E_MI_DISP_OUTPUT_3840x2160_60, /* 3840x2160_60 */
+ E_MI_DISP_OUTPUT_USER,
+ E_MI_DISP_OUTPUT_MAX,
+} MI_DISP_OutputTiming_e;
+
+typedef enum
+{
+ E_MI_DISP_ROTATE_NONE,
+ E_MI_DISP_ROTATE_90,
+ E_MI_DISP_ROTATE_180,
+ E_MI_DISP_ROTATE_270,
+ E_MI_DISP_ROTATE_NUM,
+}MI_DISP_RotateMode_e;
+
+typedef enum
+{
+ E_MI_DISP_CSC_MATRIX_BYPASS = 0, /* do not change color space */
+
+ E_MI_DISP_CSC_MATRIX_BT601_TO_BT709, /* change color space from BT.601 to BT.709 */
+ E_MI_DISP_CSC_MATRIX_BT709_TO_BT601, /* change color space from BT.709 to BT.601 */
+
+ E_MI_DISP_CSC_MATRIX_BT601_TO_RGB_PC, /* change color space from BT.601 to RGB */
+ E_MI_DISP_CSC_MATRIX_BT709_TO_RGB_PC, /* change color space from BT.709 to RGB */
+
+ E_MI_DISP_CSC_MATRIX_RGB_TO_BT601_PC, /* change color space from RGB to BT.601 */
+ E_MI_DISP_CSC_MATRIX_RGB_TO_BT709_PC, /* change color space from RGB to BT.709 */
+
+ E_MI_DISP_CSC_MATRIX_NUM
+} MI_DISP_CscMattrix_e;
+
+typedef enum
+{
+ E_MI_DISP_SYNC_MODE_INVALID = 0,
+ E_MI_DISP_SYNC_MODE_CHECK_PTS,
+ E_MI_DISP_SYNC_MODE_FREE_RUN,
+ E_MI_DISP_SYNC_MODE_NUM,
+} MI_DISP_SyncMode_e;
+
+typedef enum
+{
+ E_MI_LAYER_INPUTPORT_STATUS_INVALID = 0,
+ E_MI_LAYER_INPUTPORT_STATUS_PAUSE,
+ E_MI_LAYER_INPUTPORT_STATUS_RESUME,
+ E_MI_LAYER_INPUTPORT_STATUS_STEP,
+ E_MI_LAYER_INPUTPORT_STATUS_REFRESH,
+ E_MI_LAYER_INPUTPORT_STATUS_SHOW,
+ E_MI_LAYER_INPUTPORT_STATUS_HIDE,
+ E_MI_LAYER_INPUTPORT_STATUS_NUM,
+} MI_DISP_InputPortStatus_e;
+
+typedef struct MI_DISP_SyncInfo_s
+{
+ MI_BOOL bSynm; /* sync mode(0:timing,as BT.656; 1:signal,as LCD) */
+ MI_BOOL bIop; /* interlaced or progressive display(0:i; 1:p) */
+ MI_U8 u8Intfb; /* interlace bit width while output */
+
+ MI_U16 u16Vact ; /* vertical active area */
+ MI_U16 u16Vbb; /* vertical back blank porch */
+ MI_U16 u16Vfb; /* vertical front blank porch */
+
+ MI_U16 u16Hact; /* herizontal active area */
+ MI_U16 u16Hbb; /* herizontal back blank porch */
+ MI_U16 u16Hfb; /* herizontal front blank porch */
+ MI_U16 u16Hmid; /* bottom herizontal active area */
+
+ MI_U16 u16Bvact; /* bottom vertical active area */
+ MI_U16 u16Bvbb; /* bottom vertical back blank porch */
+ MI_U16 u16Bvfb; /* bottom vertical front blank porch */
+
+ MI_U16 u16Hpw; /* horizontal pulse width */
+ MI_U16 u16Vpw; /* vertical pulse width */
+
+ MI_BOOL bIdv; /* inverse data valid of output */
+ MI_BOOL bIhs; /* inverse horizontal synch signal */
+ MI_BOOL bIvs; /* inverse vertical synch signal */
+ MI_U32 u32FrameRate;
+} MI_DISP_SyncInfo_t;
+
+
+typedef struct MI_DISP_PubAttr_s
+{
+ MI_U32 u32BgColor; /* Background color of a device, in RGB format. */
+ MI_DISP_Interface_e eIntfType; /* Type of a VO interface */
+ MI_DISP_OutputTiming_e eIntfSync; /* Type of a VO interface timing */
+ MI_DISP_SyncInfo_t stSyncInfo; /* Information about VO interface timings */
+} MI_DISP_PubAttr_t;
+
+typedef struct MI_DISP_CompressAttr_s
+{
+ MI_BOOL bSupportCompress; /* Whether to support compress */
+} MI_DISP_CompressAttr_t;
+
+typedef struct MI_DISP_VidWin_Rect_s
+{
+ MI_U16 u16X;
+ MI_U16 u16Y;
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+} MI_DISP_VidWinRect_t;
+
+typedef struct MI_DISP_VideoLayerSize_s
+{
+ MI_U32 u16Width;
+ MI_U32 u16Height;
+} MI_DISP_VideoLayerSize_t;
+
+typedef struct MI_DISP_VideoLayerAttr_s
+{
+ MI_DISP_VidWinRect_t stVidLayerDispWin; /* Display resolution */
+// TODO: dev
+ MI_DISP_VideoLayerSize_t stVidLayerSize; /* Canvas size of the video layer */
+ // TODO: Tommy delete pixel format & doc
+ MI_SYS_PixelFormat_e ePixFormat; /* Pixel format of the video layer */
+} MI_DISP_VideoLayerAttr_t;
+
+typedef struct MI_DISP_Csc_s
+{
+ MI_DISP_CscMattrix_e eCscMatrix;
+ MI_U32 u32Luma; /* luminance: 0 ~ 100 default: 50 */
+ MI_U32 u32Contrast; /* contrast : 0 ~ 100 default: 50 */
+ MI_U32 u32Hue; /* hue : 0 ~ 100 default: 50 */
+ MI_U32 u32Saturation; /* saturation: 0 ~ 100 default: 40 */
+} MI_DISP_Csc_t;
+
+typedef struct MI_DISP_VideoFrame_s
+{
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+ MI_SYS_PixelFormat_e ePixelFormat;
+ MI_PHY aphyAddr;
+ void * pavirAddr;
+ MI_U64 u64pts;
+ MI_U32 u32PrivateData;
+ MI_U32 u32Size;
+ MI_U32 u32Stride;
+} MI_DISP_VideoFrame_t;
+/* General Operation of InputPort */
+typedef struct MI_DISP_InputPortAttr_s
+{
+ MI_DISP_VidWinRect_t stDispWin; /* rect of video out chn */
+ MI_U16 u16SrcWidth;
+ MI_U16 u16SrcHeight;
+} MI_DISP_InputPortAttr_t;
+typedef struct MI_DISP_Position_s
+{
+ MI_U16 u16X;
+ MI_U16 u16Y;
+} MI_DISP_Position_t;
+
+typedef struct MI_DISP_QueryChannelStatus_s
+{
+ MI_BOOL bEnable;
+ MI_DISP_InputPortStatus_e eStatus;
+} MI_DISP_QueryChannelStatus_t;
+
+typedef struct MI_DISP_VgaParam_s
+{
+ MI_DISP_Csc_t stCsc; /* color space */
+ MI_U32 u32Gain; /* current gain of VGA signals. [0, 64). default:0x30 */
+ MI_U32 u32Sharpness;
+} MI_DISP_VgaParam_t;
+
+typedef struct MI_DISP_HdmiParam_s
+{
+ MI_DISP_Csc_t stCsc; /* color space */
+ MI_U32 u32Gain; /* current gain of HDMI signals. [0, 64). default:0x30 */
+ MI_U32 u32Sharpness;
+} MI_DISP_HdmiParam_t;
+
+typedef struct MI_DISP_LcdParam_s
+{
+ MI_DISP_Csc_t stCsc; /* color space */
+ MI_U32 u32Sharpness;
+} MI_DISP_LcdParam_t;
+
+typedef struct MI_DISP_CvbsParam_s
+{
+ MI_BOOL bEnable;
+} MI_DISP_CvbsParam_t;
+
+
+typedef struct MI_DISP_RotateConfig_s
+{
+ MI_DISP_RotateMode_e eRotateMode;
+}MI_DISP_RotateConfig_t;
+
+typedef struct
+{
+ MI_U16 u16RedOffset;
+ MI_U16 u16GreenOffset;
+ MI_U16 u16BlueOffset;
+
+ MI_U16 u16RedColor; // 00~FF, 0x80 is no change
+ MI_U16 u16GreenColor;// 00~FF, 0x80 is no change
+ MI_U16 u16BlueColor; // 00~FF, 0x80 is no change
+}MI_DISP_ColorTemperature_t;
+
+typedef struct
+{
+ MI_BOOL bEn;
+ MI_U16 u16EntryNum;
+ MI_U8 *pu8ColorR;
+ MI_U8 *pu8ColorG;
+ MI_U8 *pu8ColorB;
+}MI_DISP_GammaParam_t;
+
+typedef struct MI_DISP_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_DISP_InitParam_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_DISP_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_divp.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_divp.h
new file mode 100644
index 00000000..ca1222cd
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_divp.h
@@ -0,0 +1,157 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_DIVP_H_
+#define _MI_DIVP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_divp_datatype.h"
+
+#define DIVP_MAJOR_VERSION 2
+#define DIVP_SUB_VERSION 4
+#define MACRO_TO_STR(macro) #macro
+#define DIVP_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_divp_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_divp_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_divp_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_DIVP_API_VERSION DIVP_VERSION_STR(DIVP_MAJOR_VERSION,DIVP_SUB_VERSION)
+
+//------------------------------------------------------------------------------
+/// @brief create a DIVP channel.
+/// @param[out] pDivpChn: DIVP channel ID.
+/// @param[in] pstAttr: Attribute of DIVP channel.
+/// @return MI_SUCCESS: succeed in creating a channel.
+/// MI_DIVP_ERR_INVALID_PARAM: invalid input patamter.
+/// MI_DIVP_ERR_NULL_PTR: NULL poiter error.
+/// MI_DIVP_ERR_FAILED: Fail to create a channel.
+/// MI_DIVP_ERR_NO_RESOUCE: there is no resource.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_CreateChn (MI_DIVP_CHN DivpChn, MI_DIVP_ChnAttr_t* pstAttr);
+
+//------------------------------------------------------------------------------
+/// @brief deatroy a DIVP channel.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @return MI_SUCCESS: succeed in deatroying a DIVP channel.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_FAILED: Fail to deatroy a DIVP channel.
+/// MI_DIVP_ERR_CHN_BUSY:channel is busy.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_DestroyChn(MI_DIVP_CHN DivpChn);
+
+//------------------------------------------------------------------------------
+/// @brief set attribute of DIVP channel.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @param[in] pstAttr: Attribute of DIVP channel.
+/// @return MI_SUCCESS: succeed in setting attribute of DIVP channel.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_INVALID_PARAM: Invalid input patamter.
+/// MI_DIVP_ERR_NULL_PTR: NULL poiter error.
+/// MI_DIVP_ERR_CHN_NOT_SUPPORT: not support.
+/// MI_DIVP_ERR_FAILED: Fail to set attribute of DIVP channel.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_SetChnAttr(MI_DIVP_CHN DivpChn, MI_DIVP_ChnAttr_t* pstAttr);
+
+//------------------------------------------------------------------------------
+/// @brief get attribute of DIVP channel.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @param[in] pstAttr: Attribute of DIVP channel.
+/// @return MI_SUCCESS: succeed in getting attribute of DIVP channel.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_NULL_PTR: NULL poiter error.
+/// MI_DIVP_ERR_FAILED: Fail to get attribute of DIVP channel.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_GetChnAttr(MI_DIVP_CHN DivpChn, MI_DIVP_ChnAttr_t* pstAttr);
+
+//------------------------------------------------------------------------------
+/// @brief start a DIVP channel.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @return MI_SUCCESS: succeed in starting a DIVP channel.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_FAILED: Fail to start a DIVP channel.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_StartChn(MI_DIVP_CHN DivpChn);
+
+//------------------------------------------------------------------------------
+/// @brief stop a DIVP channel.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @return MI_SUCCESS: succeed in stopping a DIVP channel.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_FAILED: Fail to stop a DIVP channel.
+/// MI_DIVP_ERR_CHN_BUSY:channel is busy.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_StopChn(MI_DIVP_CHN DivpChn);
+
+//------------------------------------------------------------------------------
+/// @brief set attribute of DIVP channel output port.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @param[in] pstOutputPortAttr: DIVP channel output port attribute.
+/// @return MI_SUCCESS: succeed in setting attribute of DIVP channel output port.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_INVALID_PARAM: Invalid input patamter.
+/// MI_DIVP_ERR_NULL_PTR: NULL poiter error.
+/// MI_DIVP_ERR_FAILED: Fail to set attribute of DIVP channel output port.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_SetOutputPortAttr (MI_DIVP_CHN DivpChn, MI_DIVP_OutputPortAttr_t * pstOutputPortAttr);
+
+//------------------------------------------------------------------------------
+/// @brief get attribute of DIVP channel output port.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @param[out] pstOutputPortAttr: DIVP channel output port attribute.
+/// @return MI_SUCCESS: succeed in getting attribute of DIVP channel output port.
+/// MI_DIVP_ERR_FAILED: Fail to get attribute of DIVP channel output port.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_NULL_PTR: NULL poiter error.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_GetOutputPortAttr (MI_DIVP_CHN DivpChn, MI_DIVP_OutputPortAttr_t * pstOutputPortAttr);
+
+//------------------------------------------------------------------------------
+/// @brief refresh a DIVP channel.
+/// @param[in] DivpChn: DIVP channel ID.
+/// @return MI_SUCCESS: succeed in refreshing a DIVP channel.
+/// MI_DIVP_ERR_INVALID_CHNID: Invalid channel ID.
+/// MI_DIVP_ERR_FAILED: Fail to refresh a DIVP channel.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_RefreshChn(MI_DIVP_CHN DivpChn);
+
+//------------------------------------------------------------------------------
+/// @brief stretch or crop image in specified memory to target memory
+/// @param[in] pstSrcBuf: source buff info pointer
+/// @param[in] pstSrcCrop: crop info pointer
+/// @param[in] pstDstBuf: dest buff info pointer
+/// @return MI_SUCCESS: succeed in stretching image
+/// MI_DIVP_ERR_FAILED: Fail to stretch image
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_StretchBuf(MI_DIVP_DirectBuf_t *pstSrcBuf, MI_SYS_WindowRect_t *pstSrcCrop, MI_DIVP_DirectBuf_t *pstDstBuf);
+
+//------------------------------------------------------------------------------
+/// @brief Init DIVP module.
+/// @return MI_SUCCESS: succeed in Init DIVP module.
+/// MI_DIVP_ERR_FAILED: Fail to Init DIVP module.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_InitDev(MI_DIVP_InitParam_t *pstInitParam);
+
+//------------------------------------------------------------------------------
+/// @brief DeInit DIVP module.
+/// @return MI_SUCCESS: succeed in DeInit DIVP module.
+/// MI_DIVP_ERR_FAILED: Fail to DeInit DIVP module.
+//------------------------------------------------------------------------------
+MI_S32 MI_DIVP_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_divp_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_divp_datatype.h
new file mode 100644
index 00000000..6137575a
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_divp_datatype.h
@@ -0,0 +1,85 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_DIVP_DATATYPE_H_
+#define _MI_DIVP_DATATYPE_H_
+#pragma pack(push)
+#pragma pack(4)
+
+#define MI_DIVP_ERR_INVALID_DEVID (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID))
+#define MI_DIVP_ERR_INVALID_CHNID (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID))
+#define MI_DIVP_ERR_INVALID_PARAM (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM))
+#define MI_DIVP_ERR_NULL_PTR (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR))
+#define MI_DIVP_ERR_FAILED (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED))
+#define MI_DIVP_ERR_CHN_NOT_STARTED (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NOT_STARTED))
+#define MI_DIVP_ERR_CHN_NOT_STOPED (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NOT_STOPED))
+#define MI_DIVP_ERR_CHN_NOT_SUPPORT (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT))
+#define MI_DIVP_ERR_NO_RESOUCE (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_UNEXIST))
+#define MI_DIVP_ERR_CHN_BUSY (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY))
+#define MI_DIVP_ERR_HAS_CREATED (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_EXIST))
+#define MI_DIVP_ERR_NO_CONTENT (MI_DEF_ERR( E_MI_MODULE_ID_DIVP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NO_CONTENT))
+
+typedef enum
+{
+ E_MI_DIVP_DI_TYPE_OFF,//off
+ E_MI_DIVP_DI_TYPE_2D,///2.5D DI
+ E_MI_DIVP_DI_TYPE_3D,///3D DI
+ E_MI_DIVP_DI_TYPE_NUM,
+} MI_DIVP_DiType_e;
+
+typedef enum
+{
+ E_MI_DIVP_TNR_LEVEL_OFF,
+ E_MI_DIVP_TNR_LEVEL_LOW,
+ E_MI_DIVP_TNR_LEVEL_MIDDLE,
+ E_MI_DIVP_TNR_LEVEL_HIGH,
+ E_MI_DIVP_TNR_LEVEL_NUM,
+} MI_DIVP_TnrLevel_e;
+
+typedef struct MI_DIVP_OutputPortAttr_s
+{
+ MI_U32 u32Width;//output width
+ MI_U32 u32Height;//output height
+ MI_SYS_PixelFormat_e ePixelFormat;//output pixel format
+ MI_SYS_CompressMode_e eCompMode;//compress mode
+}MI_DIVP_OutputPortAttr_t;
+
+typedef struct MI_DIVP_ChnAttr_s
+{
+ MI_U32 u32MaxWidth;//support max input width
+ MI_U32 u32MaxHeight;//support max input height
+ MI_DIVP_TnrLevel_e eTnrLevel;//TNR level
+ MI_DIVP_DiType_e eDiType;//DI type
+ MI_SYS_Rotate_e eRotateType;//rotate angle
+ MI_SYS_WindowRect_t stCropRect;//crop information
+ MI_BOOL bHorMirror;//horizontal mirror
+ MI_BOOL bVerMirror;//vertical mirror
+}MI_DIVP_ChnAttr_t;
+
+typedef struct MI_DIVP_DirectBuf_s
+{
+ MI_SYS_PixelFormat_e ePixelFormat; //YUV420SP or ARGB888 only
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+ MI_U32 u32Stride[3];
+ MI_PHY phyAddr[3];
+}MI_DIVP_DirectBuf_t;
+
+typedef struct MI_DIVP_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_DIVP_InitParam_t;
+
+#pragma pack(pop)
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gfx.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gfx.h
new file mode 100644
index 00000000..dedcc408
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gfx.h
@@ -0,0 +1,76 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_GFX_H_
+#define _MI_GFX_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+#include "mi_gfx_datatype.h"
+
+#define GFX_MAJOR_VERSION 2
+#define GFX_SUB_VERSION 5
+#define MACRO_TO_STR(macro) #macro
+#define GFX_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_gfx_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_gfx_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_gfx_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_GFX_API_VERSION GFX_VERSION_STR(GFX_MAJOR_VERSION,GFX_SUB_VERSION)
+
+/*-------------------------------------------------------------------------------------------
+ * Global Functions
+-------------------------------------------------------------------------------------------*/
+
+MI_S32 MI_GFX_Open(void);
+MI_S32 MI_GFX_Close(void);
+MI_S32 MI_GFX_WaitAllDone(MI_BOOL bWaitAllDone, MI_U16 u16TargetFence);
+
+//-------------------------------------------------------------------------------------------------
+/// Fill Rect
+/// @param pstDst \b IN: Target Surface info
+/// @param pstDstRect \b IN: Target Rect info
+/// @param u32ColorVal \b IN: Color to fill
+/// For all RGB color, the color set as the ARGB8888 format.\n
+/// Each color component need to shift to high bit.\n
+/// Use ARGB1555 as the example, the source color key as the following:\n
+/// ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n
+/// For I8 format, the index set to b component\n
+/// @param pu16Fence \b OUT: wait fence
+/// @return MI_SUCCESS - Success
+/// @return OTHER - Failure
+//------------------------------------------------------------------------------------------------
+MI_S32 MI_GFX_QuickFill(MI_GFX_Surface_t *pstDst, MI_GFX_Rect_t *pstDstRect,
+ MI_U32 u32ColorVal, MI_U16 *pu16Fence);
+MI_S32 MI_GFX_GetAlphaThresholdValue(MI_U8 *pu8ThresholdValue);
+MI_S32 MI_GFX_SetAlphaThresholdValue(MI_U8 u8ThresholdValue);
+MI_S32 MI_GFX_BitBlit(MI_GFX_Surface_t *pstSrc, MI_GFX_Rect_t *pstSrcRect,
+ MI_GFX_Surface_t *pstDst, MI_GFX_Rect_t *pstDstRect, MI_GFX_Opt_t *pstOpt, MI_U16 *pu16Fence);
+//-------------------------------------------------------------------------------------------------
+/// Set Palette for Index Color format(I2/I4/I8)
+/// @param eColorFmt \b IN: Index Color format(I2/I4/I8)
+/// @param pstPalette \b IN: RGB color data array for corresponding Index Color
+/// @return MI_SUCCESS - Success
+/// @return OTHER - Failure,refer to error code
+//------------------------------------------------------------------------------------------------
+MI_S32 MI_GFX_SetPalette(MI_GFX_ColorFmt_e eColorFmt, MI_GFX_Palette_t* pstPalette);
+
+MI_S32 MI_GFX_InitDev(MI_GFX_InitParam_t *pstInitParam);
+MI_S32 MI_GFX_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_MI_GFX_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gfx_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gfx_datatype.h
new file mode 100644
index 00000000..9dd311ea
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gfx_datatype.h
@@ -0,0 +1,229 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_GFX_DATATYPE_H_
+#define _MI_GFX_DATATYPE_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "mi_common.h"
+#include "mi_gfx_datatype.h"
+
+typedef enum
+{
+ E_MI_GFX_FMT_I1 = 0, /* MS_ColorFormat */
+ E_MI_GFX_FMT_I2,
+ E_MI_GFX_FMT_I4,
+ E_MI_GFX_FMT_I8,
+ E_MI_GFX_FMT_FABAFGBG2266,
+ E_MI_GFX_FMT_1ABFGBG12355,
+ E_MI_GFX_FMT_RGB565,
+ E_MI_GFX_FMT_ARGB1555,
+ E_MI_GFX_FMT_ARGB4444,
+ E_MI_GFX_FMT_ARGB1555_DST,
+ E_MI_GFX_FMT_YUV422,
+ E_MI_GFX_FMT_ARGB8888,
+ E_MI_GFX_FMT_RGBA5551,
+ E_MI_GFX_FMT_RGBA4444,
+ E_MI_GFX_FMT_ABGR8888,
+ E_MI_GFX_FMT_BGRA5551,
+ E_MI_GFX_FMT_ABGR1555,
+ E_MI_GFX_FMT_ABGR4444,
+ E_MI_GFX_FMT_BGRA4444,
+ E_MI_GFX_FMT_BGR565,
+ E_MI_GFX_FMT_RGBA8888,
+ E_MI_GFX_FMT_BGRA8888,
+ E_MI_GFX_FMT_MAX
+} MI_GFX_ColorFmt_e;
+
+typedef enum
+{
+ E_MI_GFX_RGB_OP_EQUAL = 0,
+ E_MI_GFX_RGB_OP_NOT_EQUAL,
+ E_MI_GFX_ALPHA_OP_EQUAL,
+ E_MI_GFX_ALPHA_OP_NOT_EQUAL,
+ E_MI_GFX_ARGB_OP_EQUAL,
+ E_MI_GFX_ARGB_OP_NOT_EQUAL,
+ E_MI_GFX_CKEY_OP_MAX,
+} MI_GFX_ColorKeyOp_e;
+
+typedef enum
+{
+ E_MI_GFX_DFB_BLD_ZERO = 0,
+ E_MI_GFX_DFB_BLD_ONE,
+ E_MI_GFX_DFB_BLD_SRCCOLOR,
+ E_MI_GFX_DFB_BLD_INVSRCCOLOR,
+ E_MI_GFX_DFB_BLD_SRCALPHA,
+ E_MI_GFX_DFB_BLD_INVSRCALPHA,
+ E_MI_GFX_DFB_BLD_DESTALPHA,
+ E_MI_GFX_DFB_BLD_INVDESTALPHA,
+ E_MI_GFX_DFB_BLD_DESTCOLOR,
+ E_MI_GFX_DFB_BLD_INVDESTCOLOR,
+ E_MI_GFX_DFB_BLD_SRCALPHASAT,
+ E_MI_GFX_DFB_BLD_MAX,
+} MI_GFX_DfbBldOp_e;
+
+typedef enum
+{
+ E_MI_GFX_MIRROR_NONE = 0,
+ E_MI_GFX_MIRROR_HORIZONTAL,
+ E_MI_GFX_MIRROR_VERTICAL,
+ E_MI_GFX_MIRROR_BOTH,
+ E_MI_GFX_MIRROR_MAX
+} MI_GFX_Mirror_e;
+
+typedef enum
+{
+ E_MI_GFX_ROTATE_0 = 0,
+ E_MI_GFX_ROTATE_90,
+ E_MI_GFX_ROTATE_180,
+ E_MI_GFX_ROTATE_270,
+ E_MI_GFX_ROTATE_MAX
+} MI_GFX_Rotate_e;
+
+typedef enum
+{
+ E_MI_GFX_ERR_NOT_INIT = MI_GFX_INITIAL_ERROR_CODE,
+ E_MI_GFX_ERR_GFX_DRV_NOT_SUPPORT,
+ E_MI_GFX_ERR_GFX_DRV_FAIL_FORMAT,
+ E_MI_GFX_ERR_GFX_NON_ALIGN_ADDRESS,
+ E_MI_GFX_ERR_GFX_NON_ALIGN_PITCH,
+ E_MI_GFX_ERR_GFX_DRV_FAIL_OVERLAP,
+ E_MI_GFX_ERR_GFX_DRV_FAIL_STRETCH,
+ E_MI_GFX_ERR_GFX_DRV_FAIL_ITALIC,
+ E_MI_GFX_ERR_GFX_DRV_FAIL_LOCKED,
+ E_MI_GFX_ERR_GFX_DRV_FAIL_BLTADDR,
+ E_MI_GFX_ERR_MAX
+} MI_GFX_ErrCode_e;
+
+
+/* GFX Module ErrorCode */
+#define MI_ERR_GFX_INVALID_PARAM MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+#define MI_ERR_GFX_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+#define MI_ERR_GFX_DEV_BUSY MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY)
+
+#define MI_ERR_GFX_NOT_INIT MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_NOT_INIT)
+#define MI_ERR_GFX_DRV_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_DRV_NOT_SUPPORT)
+#define MI_ERR_GFX_DRV_FAIL_FORMAT MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_DRV_FAIL_FORMAT)
+#define MI_ERR_GFX_NON_ALIGN_ADDRESS MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_NON_ALIGN_ADDRESS)
+#define MI_ERR_GFX_NON_ALIGN_PITCH MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_NON_ALIGN_PITCH)
+#define MI_ERR_GFX_DRV_FAIL_OVERLAP MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_DRV_FAIL_OVERLAP)
+#define MI_ERR_GFX_DRV_FAIL_STRETCH MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_DRV_FAIL_STRETCH)
+#define MI_ERR_GFX_DRV_FAIL_ITALIC MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_DRV_FAIL_ITALIC)
+#define MI_ERR_GFX_DRV_FAIL_LOCKED MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_DRV_FAIL_LOCKED)
+#define MI_ERR_GFX_DRV_FAIL_BLTADDR MI_DEF_ERR(E_MI_MODULE_ID_GFX, E_MI_ERR_LEVEL_ERROR, E_MI_GFX_ERR_GFX_DRV_FAIL_BLTADDR)
+
+typedef struct MI_GFX_Rect_s
+{
+ MI_S32 s32Xpos;
+ MI_S32 s32Ypos;
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+} MI_GFX_Rect_t;
+
+//=============================================================================
+// GFX palette information
+//=============================================================================
+
+typedef union
+{
+ /// ARGB8888 byte order
+ struct
+ {
+ MI_U8 u8A;
+ MI_U8 u8R;
+ MI_U8 u8G;
+ MI_U8 u8B;
+ } RGB;
+ // u8Data[0] = u8A
+ // u8Data[1] = u8R
+ // u8Data[2] = u8G
+ // u8Data[3] = u8B
+ MI_U8 u8Data[4];
+} MI_GFX_PaletteEntry_t;
+
+typedef struct MI_GFX_Palette_s
+{
+ /// array subscripts are indentical to value of Index Color
+ MI_GFX_PaletteEntry_t aunPalette[256];
+ /// Starting Index in palette to config
+ MI_U16 u16PalStart;
+ /// Ending Index in palette to config
+ MI_U16 u16PalEnd;
+}MI_GFX_Palette_t;
+
+typedef struct MI_GFX_ColorKey_s
+{
+ MI_U32 u32ColorStart;
+ MI_U32 u32ColorEnd;
+} MI_GFX_ColorKeyValue_t;
+
+typedef struct MI_GFX_ColorKeyInfo_s
+{
+ MI_BOOL bEnColorKey;
+ MI_GFX_ColorKeyOp_e eCKeyOp;
+ MI_GFX_ColorFmt_e eCKeyFmt;
+ MI_GFX_ColorKeyValue_t stCKeyVal;
+} MI_GFX_ColorKeyInfo_t;
+
+typedef struct MI_GFX_Surface_s
+{
+ MI_PHY phyAddr;
+ MI_GFX_ColorFmt_e eColorFmt;
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+ MI_U32 u32Stride;
+} MI_GFX_Surface_t;
+
+typedef enum
+{
+ E_MI_GFX_DFB_BLEND_NOFX = 0x00000000,
+ E_MI_GFX_DFB_BLEND_COLORALPHA = 0x00000001,
+ E_MI_GFX_DFB_BLEND_ALPHACHANNEL = 0x00000002,
+ E_MI_GFX_DFB_BLEND_COLORIZE = 0x00000004,
+ E_MI_GFX_DFB_BLEND_SRC_PREMULTIPLY = 0x00000008,
+ E_MI_GFX_DFB_BLEND_SRC_PREMULTCOLOR = 0x00000010,
+ E_MI_GFX_DFB_BLEND_DST_PREMULTIPLY = 0x00000020,
+ E_MI_GFX_DFB_BLEND_XOR = 0x00000040,
+ E_MI_GFX_DFB_BLEND_DEMULTIPLY = 0x00000080,
+ E_MI_GFX_DFB_BLEND_SRC_COLORKEY = 0x00000100,
+ E_MI_GFX_DFB_BLEND_DST_COLORKEY = 0x00000200,
+ E_MI_GFX_DFB_BLEND_MAX = 0x3FF
+} MI_Gfx_DfbBlendFlags_e;
+
+typedef struct MI_GFX_Opt_s
+{
+ MI_GFX_Rect_t stClipRect;
+ MI_GFX_ColorKeyInfo_t stSrcColorKeyInfo;
+ MI_GFX_ColorKeyInfo_t stDstColorKeyInfo;
+ MI_GFX_DfbBldOp_e eSrcDfbBldOp;
+ MI_GFX_DfbBldOp_e eDstDfbBldOp;
+ MI_GFX_Mirror_e eMirror;
+ MI_GFX_Rotate_e eRotate;
+ MI_Gfx_DfbBlendFlags_e eDFBBlendFlag;
+ MI_U32 u32GlobalSrcConstColor;
+ MI_U32 u32GlobalDstConstColor;
+} MI_GFX_Opt_t;
+
+typedef struct MI_GFX_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_GFX_InitParam_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_GFX_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gyro.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gyro.h
new file mode 100644
index 00000000..3ef98792
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gyro.h
@@ -0,0 +1,37 @@
+#ifndef _MI_GYRO_H_
+#define _MI_GYRO_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "mi_gyro_datatype.h"
+
+int GyroSensor_SetSampleRateDiv(MI_U8 u8DevId, MI_U8 u8Div);
+
+int GyroSensor_SetGyroRange(MI_U8 u8DevId, GyroSensorGyroRange_e eFullScaleRange);
+int GyroSensor_GetGyroRange(MI_U8 u8DevId, GyroSensorGyroRange_e *peFullScaleRange);
+int GyroSensor_GetGyroSensitivity(MI_U8 u8DevId, MI_U16 *pu16SensitivityDen, MI_U16 *pu16SensitivityMol);
+//pu16SensitivityDen+pu16SensitivityMol/1000
+int GyroSensor_ReadGyro_XYZ(MI_U8 u8DevId, MI_S16 *ps16X, MI_S16 *ps16Y, MI_S16 *ps16Z);
+
+int GyroSensor_SetAccelRange(MI_U8 u8DevId, GyroSensorAccelRange_e eFullScaleRange);
+int GyroSensor_GetAccelRange(MI_U8 u8DevId, GyroSensorAccelRange_e *peFullScaleRange);
+int GyroSensor_GetAccelSensitivity(MI_U8 u8DevId, MI_U16 *pu16SensitivityDen, MI_U16 *pu16SensitivityMol);
+//pu16SensitivityDen+pu16SensitivityMol/1000
+int GyroSensor_ReadAccel_XYZ(MI_U8 u8DevId, MI_S16 *ps16X, MI_S16 *ps16Y, MI_S16 *ps16Z);
+
+int GyroSensor_ReadTemp(MI_U8 u8DevId, MI_S16 *s16Temp);
+
+int GyroSensor_EnableDev(MI_U8 u8DevId, MI_BOOL bEnFifoMode, MI_U8 u8FifoModeType);
+int GyroSensor_ReadFifoData(MI_U8 u8DevId, MI_U16 *pu16FifoCnt, MI_U8 *pu8Data);
+
+MI_S32 MI_Gyro_InitDev(MI_Gyro_InitParam_t *pstInitParam);
+MI_S32 MI_Gyro_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gyro_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gyro_datatype.h
new file mode 100644
index 00000000..f5bb6c26
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_gyro_datatype.h
@@ -0,0 +1,48 @@
+#ifndef _MI_GYRO_DATATYPE_H_
+#define _MI_GYRO_DATATYPE_H_
+
+#include <cam_os_wrapper.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define FIFO_MAX_CNT (512)
+
+typedef enum
+{
+ E_GYROSENSOR_ALL_ACCEL_FIFO_EN = 0x08,
+ E_GYROSENSOR_ZG_FIFO_EN = 0x10,
+ E_GYROSENSOR_YG_FIFO_EN = 0x20,
+ E_GYROSENSOR_XG_FIFO_EN = 0x40,
+ E_GYROSENSOR_TEMP_FIFO_EN = 0x80,
+ E_GYROSENSOR_FIFO_MAX_EN = 0xFF,
+}GyroSensorEnFifoMode_e;
+
+typedef enum
+{
+ E_GYROSENSOR_GYRO_RANGE_125 =0x00,
+ E_GYROSENSOR_GYRO_RANGE_250 =0x08,
+ E_GYROSENSOR_GYRO_RANGE_500 =0x10,
+ E_GYROSENSOR_GYRO_RANGE_MASK =0x18,
+}GyroSensorGyroRange_e;
+
+typedef enum
+{
+ E_GYROSENSOR_ACCEL_RANGE_2G =0x00,
+ E_GYROSENSOR_ACCEL_RANGE_4G =0x08,
+ E_GYROSENSOR_ACCEL_RANGE_8G =0x10,
+ E_GYROSENSOR_ACCEL_RANGE_16G =0x18,
+}GyroSensorAccelRange_e;
+
+typedef struct MI_Gyro_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_Gyro_InitParam_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_hdmi.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_hdmi.h
new file mode 100644
index 00000000..e9b015b1
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_hdmi.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_HDMI_H_
+#define _MI_HDMI_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+#include "mi_hdmi_datatype.h"
+
+#define HDMI_MAJOR_VERSION 2
+#define HDMI_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define HDMI_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_hdmi_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_hdmi_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_hdmi_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_HDMI_API_VERSION HDMI_VERSION_STR(HDMI_MAJOR_VERSION,HDMI_SUB_VERSION)
+
+MI_S32 MI_HDMI_Init(MI_HDMI_InitParam_t *pstInitParam);
+MI_S32 MI_HDMI_DeInit(void);
+MI_S32 MI_HDMI_Open(MI_HDMI_DeviceId_e eHdmi);
+MI_S32 MI_HDMI_Close(MI_HDMI_DeviceId_e eHdmi);
+MI_S32 MI_HDMI_SetAttr(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_Attr_t *pstAttr);
+MI_S32 MI_HDMI_GetAttr(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_Attr_t *pstAttr);
+MI_S32 MI_HDMI_Start(MI_HDMI_DeviceId_e eHdmi);
+MI_S32 MI_HDMI_Stop(MI_HDMI_DeviceId_e eHdmi);
+MI_S32 MI_HDMI_GetSinkInfo(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_SinkInfo_t *pstSinkInfo);
+MI_S32 MI_HDMI_SetAvMute(MI_HDMI_DeviceId_e eHdmi, MI_BOOL bAvMute);
+MI_S32 MI_HDMI_ForceGetEdid(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_Edid_t *pstEdidData);
+MI_S32 MI_HDMI_SetDeepColor(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_DeepColor_e eDeepColor);
+MI_S32 MI_HDMI_GetDeepColor(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_DeepColor_e *peDeepColor);
+MI_S32 MI_HDMI_SetInfoFrame(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_InfoFrame_t *pstInfoFrame);
+MI_S32 MI_HDMI_GetInfoFrame(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_InfoFrameType_e eInfoFrameType,
+ MI_HDMI_InfoFrame_t *pstInfoFrame);
+MI_S32 MI_HDMI_SetAnalogDrvCurrent(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_AnalogDrvCurrent_t *pstAnalogDrvCurrent);
+MI_S32 MI_HDMI_InitDev(MI_HDMI_InitParam_t *pstInitParam);
+MI_S32 MI_HDMI_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif ///_MI_HDMI_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_hdmi_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_hdmi_datatype.h
new file mode 100644
index 00000000..51a2ad41
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_hdmi_datatype.h
@@ -0,0 +1,412 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_HDMI_DATATYPE_H_
+#define _MI_HDMI_DATATYPE_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+
+/*-------------------------------------------------------------------------------------------------
+ * Enum
+ ------------------------------------------------------------------------------------------------*/
+typedef enum
+{
+ E_MI_HDMI_ID_0 = 0,
+ E_MI_HDMI_ID_MAX
+} MI_HDMI_DeviceId_e;
+
+typedef enum
+{
+ E_MI_HDMI_EVENT_HOTPLUG = 0,
+ E_MI_HDMI_EVENT_NO_PLUG,
+ E_MI_HDMI_EVENT_MAX
+} MI_HDMI_EventType_e;
+
+typedef enum
+{
+ E_MI_HDMI_TIMING_480_60I = 0,
+ E_MI_HDMI_TIMING_480_60P = 1,
+ E_MI_HDMI_TIMING_576_50I = 2,
+ E_MI_HDMI_TIMING_576_50P = 3,
+ E_MI_HDMI_TIMING_720_50P = 4,
+ E_MI_HDMI_TIMING_720_60P = 5,
+ E_MI_HDMI_TIMING_1080_50I = 6,
+ E_MI_HDMI_TIMING_1080_50P = 7,
+ E_MI_HDMI_TIMING_1080_60I = 8,
+ E_MI_HDMI_TIMING_1080_60P = 9,
+ E_MI_HDMI_TIMING_1080_30P = 10,
+ E_MI_HDMI_TIMING_1080_25P = 11,
+ E_MI_HDMI_TIMING_1080_24P = 12,
+ E_MI_HDMI_TIMING_4K2K_30P = 13,
+ E_MI_HDMI_TIMING_1440_50P = 14,
+ E_MI_HDMI_TIMING_1440_60P = 15,
+ E_MI_HDMI_TIMING_1440_24P = 16,
+ E_MI_HDMI_TIMING_1440_30P = 17,
+ E_MI_HDMI_TIMING_1470_50P = 18,
+ E_MI_HDMI_TIMING_1470_60P = 19,
+ E_MI_HDMI_TIMING_1470_24P = 20,
+ E_MI_HDMI_TIMING_1470_30P = 21,
+ E_MI_HDMI_TIMING_1920x2205_24P = 22,
+ E_MI_HDMI_TIMING_1920x2205_30P = 23,
+ E_MI_HDMI_TIMING_4K2K_25P = 24,
+ E_MI_HDMI_TIMING_4K1K_60P = 25,
+ E_MI_HDMI_TIMING_4K2K_60P = 26,
+ E_MI_HDMI_TIMING_4K2K_24P = 27,
+ E_MI_HDMI_TIMING_4K2K_50P = 28,
+ E_MI_HDMI_TIMING_2205_24P = 29,
+ E_MI_HDMI_TIMING_4K1K_120P = 30,
+ E_MI_HDMI_TIMING_4096x2160_24P = 31,
+ E_MI_HDMI_TIMING_4096x2160_25P = 32,
+ E_MI_HDMI_TIMING_4096x2160_30P = 33,
+ E_MI_HDMI_TIMING_4096x2160_50P = 34,
+ E_MI_HDMI_TIMING_4096x2160_60P = 35,
+ E_MI_HDMI_TIMING_1024x768_60P = 36,
+ E_MI_HDMI_TIMING_1280x1024_60P = 37,
+ E_MI_HDMI_TIMING_1440x900_60P = 38,
+ E_MI_HDMI_TIMING_1600x1200_60P = 39,
+ E_MI_HDMI_TIMING_1280x800_60P = 40,
+ E_MI_HDMI_TIMING_1366x768_60P = 41,
+ E_MI_HDMI_TIMING_1680x1050_60P = 42,
+ E_MI_HDMI_TIMING_MAX,
+} MI_HDMI_TimingType_e;
+
+typedef enum
+{
+ E_MI_HDMI_COLOR_TYPE_RGB444 = 0,
+ E_MI_HDMI_COLOR_TYPE_YCBCR422,
+ E_MI_HDMI_COLOR_TYPE_YCBCR444,
+ E_MI_HDMI_COLOR_TYPE_YCBCR420,
+ E_MI_HDMI_COLOR_TYPE_MAX
+} MI_HDMI_ColorType_e;
+
+typedef enum
+{
+ E_MI_HDMI_OUTPUT_MODE_HDMI = 0,
+ E_MI_HDMI_OUTPUT_MODE_HDMI_HDCP,
+ E_MI_HDMI_OUTPUT_MODE_DVI,
+ E_MI_HDMI_OUTPUT_MODE_DVI_HDCP,
+ E_MI_HDMI_OUTPUT_MODE_MAX,
+} MI_HDMI_OutputMode_e;
+
+typedef enum
+{
+ E_MI_HDMI_DEEP_COLOR_24BIT = 0,
+ E_MI_HDMI_DEEP_COLOR_30BIT,
+ E_MI_HDMI_DEEP_COLOR_36BIT,
+ E_MI_HDMI_DEEP_COLOR_48BIT,
+ E_MI_HDMI_DEEP_COLOR_MAX,
+} MI_HDMI_DeepColor_e;
+
+typedef enum
+{
+ E_MI_HDMI_AUDIO_SAMPLERATE_UNKNOWN = 0,
+ E_MI_HDMI_AUDIO_SAMPLERATE_32K = 1,
+ E_MI_HDMI_AUDIO_SAMPLERATE_44K = 2,
+ E_MI_HDMI_AUDIO_SAMPLERATE_48K = 3,
+ E_MI_HDMI_AUDIO_SAMPLERATE_88K = 4,
+ E_MI_HDMI_AUDIO_SAMPLERATE_96K = 5,
+ E_MI_HDMI_AUDIO_SAMPLERATE_176K = 6,
+ E_MI_HDMI_AUDIO_SAMPLERATE_192K = 7,
+ E_MI_HDMI_AUDIO_SAMPLERATE_MAX,
+} MI_HDMI_SampleRate_e;
+
+typedef enum
+{
+ E_MI_HDMI_BIT_DEPTH_8 = 8,
+ E_MI_HDMI_BIT_DEPTH_16 = 16,
+ E_MI_HDMI_BIT_DEPTH_18 = 18,
+ E_MI_HDMI_BIT_DEPTH_20 = 20,
+ E_MI_HDMI_BIT_DEPTH_24 = 24,
+ E_MI_HDMI_BIT_DEPTH_32 = 32,
+ E_MI_HDMI_BIT_DEPTH_MAX
+} MI_HDMI_BitDepth_e;
+
+typedef enum
+{
+ E_MI_HDMI_ACODE_PCM = 0,
+ E_MI_HDMI_ACODE_NON_PCM,
+ E_MI_HDMI_ACODE_MAX
+} MI_HDMI_AudioCodeType_e;
+
+typedef enum
+{
+ E_MI_HDMI_INFOFRAME_TYPE_AVI = 0,
+ E_MI_HDMI_INFOFRAME_TYPE_SPD,
+ E_MI_HDMI_INFOFRAME_TYPE_AUDIO,
+ E_MI_HDMI_INFOFRAME_TYPE_MAX
+} MI_HDMI_InfoFrameType_e;
+
+typedef enum
+{
+ E_MI_HDMI_VIDEO_AFD_SameAsPictureAR = 8, // 1000
+ E_MI_HDMI_VIDEO_AFD_4_3_Center = 9, // 1001
+ E_MI_HDMI_VIDEO_AFD_16_9_Center = 10, // 1010
+ E_MI_HDMI_VIDEO_AFD_14_9_Center = 11, // 1011
+ E_MI_HDMI_VIDEO_AFD_Others = 15, // 0000~ 0111, 1100 ~ 1111
+} MI_HDMI_VideoAfdRatio_e;
+
+typedef enum
+{
+ E_MI_HDMI_AUDIO_CODING_REFER_STREAM_HEAD = 0,
+ E_MI_HDMI_AUDIO_CODING_PCM,
+ E_MI_HDMI_AUDIO_CODING_AC3,
+ E_MI_HDMI_AUDIO_CODING_MPEG1,
+ E_MI_HDMI_AUDIO_CODING_MP3,
+ E_MI_HDMI_AUDIO_CODING_MPEG2,
+ E_MI_HDMI_AUDIO_CODING_AAC,
+ E_MI_HDMI_AUDIO_CODING_DTS,
+ E_MI_HDMI_AUDIO_CODING_DDPLUS,
+ E_MI_HDMI_AUDIO_CODING_MLP,
+ E_MI_HDMI_AUDIO_CODING_WMA,
+ E_MI_HDMI_AUDIO_CODING_MAX
+} MI_HDMI_AudioCodingType_e;
+
+typedef enum
+{
+ E_MI_HDMI_SCAN_INFO_NO_DATA = 0, /**< No Scan information*/
+ E_MI_HDMI_SCAN_INFO_OVERSCANNED, /**< Scan information, Overscanned (for television) */
+ E_MI_HDMI_SCAN_INFO_UNDERSCANNED, /**< Scan information, Underscanned (for computer) */
+ E_MI_HDMI_SCAN_INFO_FUTURE,
+ E_MI_HDMI_SCAN_INFO_MAX
+} MI_HDMI_ScanInfo_e;
+
+typedef enum
+{
+ E_MI_HDMI_COLORIMETRY_NO_DATA = 0,
+ E_MI_HDMI_COLORIMETRY_SMPTE170M,
+ E_MI_HDMI_COLORIMETRY_ITUR709,
+ E_MI_HDMI_COLORIMETRY_EXTEND,
+ E_MI_HDMI_COLORIMETRY_MAX,
+} MI_HDMI_Colorimetry_e;
+
+typedef enum
+{
+ E_MI_HDMI_EXT_COLORIMETRY_XVYCC601 = 0,
+ E_MI_HDMI_EXT_COLORIMETRY_XVYCC709,
+ E_MI_HDMI_EXT_COLORIMETRY_SYCC601,
+ E_MI_HDMI_EXT_COLORIMETRY_ADOBEYCC601,
+ E_MI_HDMI_EXT_COLORIMETRY_ADOBERGB,
+ E_MI_HDMI_EXT_COLORIMETRY_BT2020CYCC, //mapping to ext. colorimetry format BT2020Y'cC'bcC'rc
+ E_MI_HDMI_EXT_COLORIMETRY_BT2020YCC, //mapping to ext. colorimetry format BT2020 RGB or YCbCr
+ E_MI_HDMI_EXT_COLORIMETRY_BT2020RGB, //mapping to ext. colorimetry format BT2020 RGB or YCbCr
+ E_MI_HDMI_EXT_COLORIMETRY_MAX,
+} MI_HDMI_ExtColorimetry_e;
+
+typedef enum
+{
+ E_MI_HDMI_ASPECT_RATIO_INVALID = 0, /**< unknown aspect ratio */
+ E_MI_HDMI_ASPECT_RATIO_4TO3, /**< 4:3 */
+ E_MI_HDMI_ASPECT_RATIO_16TO9, /**< 16:9 */
+ E_MI_HDMI_ASPECT_RATIO_21TO9, /**< 21:9 */
+ E_MI_HDMI_ASPECT_RATIO_MAX
+} MI_HDMI_AspectRatio_e;
+
+typedef enum
+{
+ E_MI_HDMI_YCC_QUANTIZATION_LIMITED_RANGE = 0, /**< Limited quantization range of 220 levels when receiving a CE video format*/
+ E_MI_HDMI_YCC_QUANTIZATION_FULL_RANGE, /**< Full quantization range of 256 levels when receiving an IT video format*/
+ E_MI_HDMI_YCC_QUANTIZATION_MAX
+} MI_HDMI_YccQuantRange_e;
+
+typedef enum
+{
+ E_MI_HDMI_ERR_UNSUPPORT_TIMING = MI_HDMI_INITIAL_ERROR_CODE,
+ E_MI_HDMI_ERR_UNSUPPORT_COLORTYPE,
+ E_MI_HDMI_ERR_UNSUPPORT_COLORDEPTH,
+ E_MI_HDMI_ERR_UNSUPPORT_OUTPUTMODE,
+ E_MI_HDMI_ERR_UNSUPPORT_ACODETYPE,
+ E_MI_HDMI_ERR_UNSUPPORT_AFREQ,
+ E_MI_HDMI_ERR_EDID_HEADER_ERR,
+ E_MI_HDMI_ERR_EDID_DATA_ERR,
+ E_MI_HDMI_ERR_EDID_PRASE_ERR,
+ E_MI_HDMI_ERR_MAX
+} MI_HDMI_ErrCode_e;
+
+/*-------------------------------------------------------------------------------------------------
+ * Defines
+ ------------------------------------------------------------------------------------------------*/
+#define MI_HDMI_MAX_ACAP_CNT 8
+#define MI_HDMI_MAX_AUDIO_SAMPLE_RATE_CNT 10
+
+/* HDMI Module ErrorCode */
+#define MI_ERR_HDMI_INVALID_PARAM MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+#define MI_ERR_HDMI_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+#define MI_ERR_HDMI_DRV_FAILED MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED)
+#define MI_ERR_HDMI_NOT_INIT MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_INIT)
+#define MI_ERR_HDMI_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT)
+#define MI_ERR_HDMI_UNSUPPORT_TIMING MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_HDMI_ERR_UNSUPPORT_TIMING)
+#define MI_ERR_HDMI_UNSUPPORT_COLORTYPE MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_HDMI_ERR_UNSUPPORT_COLORTYPE)
+#define MI_ERR_HDMI_UNSUPPORT_ACODETYPE MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_HDMI_ERR_UNSUPPORT_ACODETYPE)
+#define MI_ERR_HDMI_UNSUPPORT_AFREQ MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_HDMI_ERR_UNSUPPORT_AFREQ)
+#define MI_ERR_HDMI_EDID_HEADER_ERR MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_HDMI_ERR_EDID_HEADER_ERR)
+#define MI_ERR_HDMI_EDID_DATA_ERR MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_HDMI_ERR_EDID_DATA_ERR)
+#define MI_ERR_HDMI_EDID_PRASE_ERR MI_DEF_ERR(E_MI_MODULE_ID_HDMI, E_MI_ERR_LEVEL_ERROR, E_MI_HDMI_ERR_EDID_PRASE_ERR)
+
+/*-------------------------------------------------------------------------------------------------
+ * Callback
+ ------------------------------------------------------------------------------------------------*/
+typedef MI_S32 (* MI_HDMI_EventCallBack)(MI_HDMI_DeviceId_e eHdmi, MI_HDMI_EventType_e event, void *pEventParam, void *pUsrParam);
+
+/*-------------------------------------------------------------------------------------------------
+ * Structures
+ ------------------------------------------------------------------------------------------------*/
+typedef struct MI_HDMI_InitParam_s
+{
+ MI_HDMI_EventCallBack pfnHdmiEventCallback;
+ void *pCallBackArgs;
+} MI_HDMI_InitParam_t;
+
+typedef struct MI_HDMI_VideoAttr_s
+{
+ MI_BOOL bEnableVideo;
+ MI_HDMI_TimingType_e eTimingType;
+ MI_HDMI_OutputMode_e eOutputMode;
+ MI_HDMI_ColorType_e eColorType;
+ MI_HDMI_DeepColor_e eDeepColorMode;
+} MI_HDMI_VideoAttr_t;
+
+typedef struct MI_HDMI_AudioAttr_s
+{
+ MI_BOOL bEnableAudio;
+ MI_BOOL bIsMultiChannel;// 0->2channel 1->8channel
+ MI_HDMI_SampleRate_e eSampleRate;
+ MI_HDMI_BitDepth_e eBitDepth;
+ MI_HDMI_AudioCodeType_e eCodeType;
+} MI_HDMI_AudioAttr_t;
+
+typedef struct MI_HDMI_EnInfoFrame_s
+{
+ MI_BOOL bEnableAviInfoFrame;
+ MI_BOOL bEnableAudInfoFrame;
+ MI_BOOL bEnableSpdInfoFrame;
+} MI_HDMI_EnInfoFrame_t;
+
+typedef struct MI_HDMI_Attr_s
+{
+ MI_BOOL bConnect;
+ MI_HDMI_VideoAttr_t stVideoAttr;
+ MI_HDMI_AudioAttr_t stAudioAttr;
+ MI_HDMI_EnInfoFrame_t stEnInfoFrame;
+} MI_HDMI_Attr_t;
+
+typedef struct MI_HDMI_Edid_s
+{
+ MI_BOOL bEdidValid;
+ MI_U32 u32Edidlength;
+ MI_U8 au8Edid[512]; /* EDID buffer */
+} MI_HDMI_Edid_t;
+
+typedef struct MI_HDMI_Sink_Info_s
+{
+ MI_BOOL bConnected;
+ MI_BOOL bSupportHdmi;
+ MI_HDMI_TimingType_e eNativeTimingType;
+ MI_BOOL abVideoFmtSupported[E_MI_HDMI_TIMING_MAX];
+ MI_BOOL bSupportYCbCr444;
+ MI_BOOL bSupportYCbCr422;
+ MI_BOOL bSupportYCbCr;
+ MI_BOOL bSupportxvYcc601;
+ MI_BOOL bSupportxvYcc709;
+ MI_U8 u8MdBit;
+ MI_BOOL abAudioFmtSupported[MI_HDMI_MAX_ACAP_CNT];
+ MI_U32 au32AudioSampleRateSupported[MI_HDMI_MAX_AUDIO_SAMPLE_RATE_CNT];
+ MI_U32 u32MaxPcmChannels;
+ MI_U8 u8Speaker;
+ MI_U8 au8IdManufactureName[4];
+ MI_U32 u32IdProductCode;
+ MI_U32 u32IdSerialNumber;
+ MI_U32 u32WeekOfManufacture;
+ MI_U32 u32YearOfManufacture;
+ MI_U8 u8Version;
+ MI_U8 u8Revision;
+ MI_U8 u8EdidExternBlockNum;
+ MI_U8 au8IeeRegId[3];//IEEE registeration identifier
+ MI_U8 u8PhyAddr_A;
+ MI_U8 u8PhyAddr_B;
+ MI_U8 u8PhyAddr_C;
+ MI_U8 u8PhyAddr_D;
+ MI_BOOL bSupportDviDual;
+ MI_BOOL bSupportDeepColorYcbcr444;
+ MI_BOOL bSupportDeepColor30Bit;
+ MI_BOOL bSupportDeepColor36Bit;
+ MI_BOOL bSupportDeepColor48Bit;
+ MI_BOOL bSupportAi;
+ MI_U32 u8MaxTmdsClock;
+ MI_BOOL bILatencyFieldsPresent;
+ MI_BOOL bLatencyFieldsPresent;
+ MI_BOOL bHdmiVideoPresent;
+ MI_U8 u8VideoLatency;
+ MI_U8 u8AudioLatency;
+ MI_U8 u8InterlacedVideoLatency;
+ MI_U8 u8InterlacedAudioLatency;
+} MI_HDMI_SinkInfo_t;
+
+typedef struct MI_HDMIAviInforFrameVer_s
+{
+ MI_BOOL bEnableAfdOverWrite;
+ MI_U8 A0Value;
+ MI_HDMI_ColorType_e eColorType;
+ MI_HDMI_Colorimetry_e eColorimetry;
+ MI_HDMI_ExtColorimetry_e eExtColorimetry;
+ MI_HDMI_YccQuantRange_e eYccQuantRange;
+ MI_HDMI_TimingType_e eTimingType; //trans to MS_VIDEO_TIMING in impl
+ MI_HDMI_VideoAfdRatio_e eAfdRatio;
+ MI_HDMI_ScanInfo_e eScanInfo;
+ MI_HDMI_AspectRatio_e eAspectRatio;
+} MI_HDMI_AviInfoFrameVer_t;
+
+typedef struct MI_HDMI_AudInfoFrameVer_s
+{
+ MI_U32 u32ChannelCount; //2 4 6 8 channels
+ MI_HDMI_AudioCodeType_e eAudioCodeType;//PCM NON-PCM
+ MI_HDMI_SampleRate_e eSampleRate;
+} MI_HDMI_AudInfoFrameVer_t;
+
+typedef struct MI_HDMI_SpdInfoFrame_s
+{
+ MI_U8 au8VendorName[8];
+ MI_U8 au8ProductDescription[16];
+} MI_HDMI_SpdInfoFrame_t;
+
+typedef union
+{
+ MI_HDMI_AviInfoFrameVer_t stAviInfoFrame;
+ MI_HDMI_AudInfoFrameVer_t stAudInfoFrame;
+ MI_HDMI_SpdInfoFrame_t stSpdInfoFrame;
+} MI_HDMI_InfoFrameUnit_u;
+
+typedef struct MI_HDMI_InfoFrame_s
+{
+ MI_HDMI_InfoFrameType_e eInfoFrameType; /* InfoFrame type */
+ MI_HDMI_InfoFrameUnit_u unInforUnit; /* InfoFrame date */
+} MI_HDMI_InfoFrame_t;
+
+typedef struct MI_HDMI_AnalogDrvCurrent_s
+{
+ MI_U8 u8DrvCurTap1Ch0;
+ MI_U8 u8DrvCurTap1Ch1;
+ MI_U8 u8DrvCurTap1Ch2;
+ MI_U8 u8DrvCurTap1Ch3;
+ MI_U8 u8DrvCurTap2Ch0;
+ MI_U8 u8DrvCurTap2Ch1;
+ MI_U8 u8DrvCurTap2Ch2;
+ MI_U8 u8DrvCurTap2Ch3;
+} MI_HDMI_AnalogDrvCurrent_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif //_MI_HDMI_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ipu.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ipu.h
new file mode 100644
index 00000000..ced63548
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ipu.h
@@ -0,0 +1,65 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_IPU_H_
+#define _MI_IPU_H_
+
+#include "mi_common.h"
+#include "mi_common_datatype.h"
+#include "mi_sys_datatype.h"
+#include "cam_os_wrapper.h"
+#include "mi_ipu_datatype.h"
+
+//#define PERFORMANCE_DEBUG
+//#define IPU_DEBUG
+#define ipu_err(fmt, args...) CamOsPrintf(fmt, ##args)
+
+#ifdef IPU_DEBUG
+#define ipu_info(fmt, args...) CamOsPrintf(fmt,##args)
+#else
+#define ipu_info(fmt, args...)
+#endif
+
+
+#define IPU_MAJOR_VERSION 1
+#define IPU_SUB_VERSION 0
+#define MACRO_TO_STR(macro) #macro
+#define IPU_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_ipu_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_ipu_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_ipu_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_IPU_API_VERSION IPU_VERSION_STR(IPU_MAJOR_VERSION,IPU_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_IPU_CreateDevice(MI_IPU_DevAttr_t *pstIPUDevAttr, SerializedReadFunc pReadFunc, char *pReadCtx, MI_U32 FWSize);
+MI_S32 MI_IPU_DestroyDevice(void);
+MI_S32 MI_IPU_CreateCHN(MI_IPU_CHN *ptChnId, MI_IPUChnAttr_t *pstIPUChnAttr,SerializedReadFunc pReadFunc, char *pReadCtx);
+MI_S32 MI_IPU_DestroyCHN(MI_IPU_CHN u32ChnId);
+MI_S32 MI_IPU_GetInOutTensorDesc(MI_IPU_CHN u32ChnId, MI_IPU_SubNet_InputOutputDesc_t *pstDesc);
+MI_S32 MI_IPU_GetInputTensors(MI_IPU_CHN u32ChnId, MI_IPU_TensorVector_t *pstInputTensorVector);
+MI_S32 MI_IPU_PutInputTensors(MI_IPU_CHN u32ChnId, MI_IPU_TensorVector_t *pstInputTensorVector);
+MI_S32 MI_IPU_GetOutputTensors(MI_IPU_CHN u32ChnId, MI_IPU_TensorVector_t *pstInputTensorVector);
+MI_S32 MI_IPU_PutOutputTensors(MI_IPU_CHN u32ChnId, MI_IPU_TensorVector_t *pstInputTensorVector);
+MI_S32 MI_IPU_Invoke(MI_IPU_CHN u32ChnId, MI_IPU_TensorVector_t *pstInputTensorVector, MI_IPU_TensorVector_t *pstOuputTensorVector);
+MI_S32 MI_IPU_GetOfflineModeStaticInfo(SerializedReadFunc pReadFunc, char *pReadCtx, MI_IPU_OfflineModelStaticInfo_t *pStaticInfo);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ipu_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ipu_datatype.h
new file mode 100644
index 00000000..c222174a
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ipu_datatype.h
@@ -0,0 +1,134 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_IPU_DATATYPE_H_
+#define _MI_IPU_DATATYPE_H_
+
+
+#define MI_IPU_MAX_TENSOR_DIM 8
+#define MI_IPU_CHN_MAX 16
+#define MI_IPU_MAX_INPUT_TENSOR_CNT 61
+#define MI_IPU_MAX_OUTPUT_TENSOR_CNT 61
+#define MI_IPU_MAX_TENSOR_CNT \
+ ((MI_IPU_MAX_INPUT_TENSOR_CNT>MI_IPU_MAX_OUTPUT_TENSOR_CNT)? \
+ MI_IPU_MAX_INPUT_TENSOR_CNT:MI_IPU_MAX_OUTPUT_TENSOR_CNT)
+
+#define MAX_TENSOR_NAME_LEN 256
+#define MAX_IPU_INPUT_OUTPUT_BUF_DEPTH 3
+#define MI_IPU_MAX_TIMEOUT (20*1000) //20 seconds
+#define MI_IPU_BOOT_MAX_TIMEOUT (5*1000) //5 seconds
+
+#define YUV420_W_PITCH_ALIGNMENT 16
+#define YUV420_H_PITCH_ALIGNMENT 2
+#define XRGB_W_PITCH_ALIGNMENT 16
+
+
+typedef MI_U32 MI_IPU_CHN;
+typedef int (*SerializedReadFunc)(void *dst_buf,int offset, int size, char *ctx);
+
+typedef enum
+{
+ MI_IPU_FORMAT_U8,
+ MI_IPU_FORMAT_NV12,
+ MI_IPU_FORMAT_INT16,
+ MI_IPU_FORMAT_INT32,
+ MI_IPU_FORMAT_INT8,
+ MI_IPU_FORMAT_FP32,
+ MI_IPU_FORMAT_UNKNOWN,
+ MI_IPU_FORMAT_ARGB8888,
+ MI_IPU_FORMAT_ABGR8888,
+} MI_IPU_ELEMENT_FORMAT;
+
+typedef enum
+{
+ E_IPU_ERR_INVALID_CHNID = 1, /* invalid channel ID */
+ E_IPU_ERR_CHNID_EXIST, /* channel exists */
+ E_IPU_ERR_CHNID_UNEXIST, /* channel unexists */
+ E_IPU_ERR_NOMEM, /* failure caused by malloc memory */
+ E_IPU_ERR_NOBUF, /* failure caused by malloc buffer */
+ E_IPU_ERR_BADADDR, /* bad address, buffer address doesn't get from IPU buffer allocator */
+ E_IPU_ERR_SYS_TIMEOUT, /* system timeout*/
+ E_IPU_ERR_FILE_OPERATION, /* file cannot be open or read or write */
+ E_IPU_ERR_ILLEGAL_TENSOR_BUFFER_SIZE, /* tensor buffer size cannot meet the requirement, usually less than requirement*/
+ E_IPU_ERR_ILLEGAL_BUFFER_DEPTH, /* input or output buffer depth quantum is more than maximum number */
+ E_IPU_ERR_ILLEGAL_INPUT_OUTPUT_DESC, /* network description is illegal, usually mean input or output buffer quantum is wrong */
+ E_IPU_ERR_ILLEGAL_INPUT_OUTPUT_PARAM, /* user's input or output buffer quantum isn't match network description */
+ E_IPU_ERR_MAP, /* address mapping error */
+ E_IPU_ERR_INIT_FIRMWARE, /* fail to init ipu firmware */
+ E_IPU_ERR_CREATE_CHANNEL, /* fail to create channel */
+ E_IPU_ERR_DESTROY_CHANNEL, /* fail to destroy channel */
+ E_IPU_ERR_INVOKE, /* fail to invoke */
+ E_IPU_ERR_SET_MALLOC_REGION, /* fail to set malloc region for freertos */
+ E_IPU_ERR_SET_IPU_PARAMETER, /* fail to set IPU parameter */
+ E_IPU_ERR_INVALID_PITCH_ALIGNMENT, /* invalid pitch alignment */
+ E_IPU_ERR_NO_CREATED_IPU_DEVICE, /* there is no created IPU device */
+ E_IPU_ERR_GET_IPU_VERSION, /* fail to get ipu version from ipu firmware */
+ E_IPU_ERR_MISMATCH_IPU_HEAD_FILE, /* ipu head files version isn't matching */
+ E_IPU_ERR_NO_SUPPORT_REQ, /* ipu firmware do not support this request */
+ E_IPU_ERR_FAILED, /* unexpected error */
+ E_IPU_ERR_SEND_REQUEST, /* failt to send request to IPU */
+ E_IPU_ERR_GET_FIRMWARE_INFO, /* fail to get ipu firmware information */
+ E_IPU_ERR_NO_AVAILABLE_CHNID = 1<<8, /* there is no available channel */
+}IPU_ErrCode_e;
+
+typedef struct MI_IPU_TensorDesc_s {
+ MI_U32 u32TensorDim;
+ MI_IPU_ELEMENT_FORMAT eElmFormat;
+ MI_U32 u32TensorShape[MI_IPU_MAX_TENSOR_DIM]; // 3,299,299
+ char name[MAX_TENSOR_NAME_LEN];
+ MI_U32 u32InnerMostStride;
+ MI_FLOAT fScalar;
+ MI_S64 s64ZeroPoint;
+ MI_S32 s32AlignedBufSize;
+} MI_IPU_TensorDesc_t;
+
+typedef struct MI_IPU_SubNet_InputOutputDesc_s {
+ MI_U32 u32InputTensorCount;
+ MI_U32 u32OutputTensorCount;
+ MI_IPU_TensorDesc_t astMI_InputTensorDescs[MI_IPU_MAX_INPUT_TENSOR_CNT];
+ MI_IPU_TensorDesc_t astMI_OutputTensorDescs[MI_IPU_MAX_OUTPUT_TENSOR_CNT];
+} MI_IPU_SubNet_InputOutputDesc_t;
+
+typedef struct MI_IPU_Tensor_s {
+ //MI_IPU_TensorShape_t *pstTensorShape;
+ //MI_BOOL bRewiseRGBOrder;//only valid under U8 & C=3,4 or NV12
+ void *ptTensorData[2];
+ MI_PHY phyTensorAddr[2];//notice that this is miu bus addr,not cpu bus addr.
+} MI_IPU_Tensor_t;
+
+typedef struct MI_IPU_TensorVector_s {
+ MI_U32 u32TensorCount;
+ MI_IPU_Tensor_t astArrayTensors[MI_IPU_MAX_TENSOR_CNT];
+} MI_IPU_TensorVector_t;
+
+typedef struct MI_IPU_DevAttr_s {
+ MI_U32 u32MaxVariableBufSize;
+ MI_U32 u32YUV420_W_Pitch_Alignment; //default is 16
+ MI_U32 u32YUV420_H_Pitch_Alignment; //default is 2
+ MI_U32 u32XRGB_W_Pitch_Alignment; //default is 16
+} MI_IPU_DevAttr_t;
+
+typedef struct MI_IPUChnAttr_s {
+ MI_U32 u32SubNetId;
+ MI_U32 u32OutputBufDepth;
+ MI_U32 u32InputBufDepth;
+} MI_IPUChnAttr_t;
+
+typedef struct MI_IPU_OfflineModelStaticInfo_s {
+ MI_U32 u32VariableBufferSize;
+ MI_U32 u32OfflineModelSize;
+} MI_IPU_OfflineModelStaticInfo_t;
+
+#endif // !_MI_IPU_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_iqserver.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_iqserver.h
new file mode 100644
index 00000000..3d61e03e
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_iqserver.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_iqserver.h
+*
+* Created on: July 10, 2018
+* Author: Shan Li
+*/
+
+
+#ifndef _MI_IQSERVER_H
+#define _MI_IQSERVER_H
+
+#define IRQSERVER_MAJOR_VERSION 2
+#define IRQSERVER_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define IRQSERVER_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_irqserver_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_irqserver_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_irqserver_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_IRQSERVER_API_VERSION IRQSERVER_VERSION_STR(IRQSERVER_MAJOR_VERSION,IRQSERVER_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include "mi_iqserver_datatype.h"
+
+/*
+* Open IQServer
+* Param:
+* width: sensor width
+* height: sensor height
+*/
+MI_S32 MI_IQSERVER_Open(MI_U16 width, MI_U16 height, MI_S32 vpeChn);
+
+MI_S32 MI_IQSERVER_SetDataPath(char* path);
+
+MI_S32 MI_IQSERVER_SetCustFunc(MI_S32(* func)(MI_U16 data_type, MI_U32 length, MI_U8 * data));
+
+/*
+* Close IQServer
+*/
+MI_S32 MI_IQSERVER_Close();
+#endif
+
+#ifdef __cplusplus
+} //end of extern C
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_iqserver_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_iqserver_datatype.h
new file mode 100644
index 00000000..1172d807
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_iqserver_datatype.h
@@ -0,0 +1,30 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+* mi_iqserver_datatype.h
+*
+* Created on: June 27, 2018
+* Author: Jeffrey Chou
+*/
+
+#ifndef _MI_IQSERVER_DATATYPE_H_
+#define _MI_IQSERVER_DATATYPE_H_
+
+#define MI_IQSERVER_OK 0
+#define MI_ERR_IQSERVER_FAIL 1
+#define MI_ERR_IQSERVER_NULL_PTR 2
+#define MI_ERR_IQSERVER_NO_BUFF 3
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ive.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ive.h
new file mode 100644
index 00000000..dee32dcc
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ive.h
@@ -0,0 +1,810 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_IVE_H_
+#define _MI_IVE_H_
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C"{
+#endif
+#endif /* End of #ifdef __cplusplus */
+
+#include "mi_ive_datatype.h"
+
+/*****************************************************************************
+* Prototype : MI_IVE_Create
+* Description : Create IVE handle
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Create(MI_IVE_HANDLE hHandle);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Destroy
+* Description : Destroy IVE handle
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Destroy(MI_IVE_HANDLE hHandle);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Filter
+* Description : 5x5 template filter.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data.
+* The U8C1,SP420 and SP422 input formats are supported.
+* MI_IVE_DstImage_t *pstDst Output result, of same type with the input.
+* MI_IVE_FilterCtrl_t *pstFltCtrl Control parameters of filter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Filter(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_FilterCtrl_t *pstFltCtrl,MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Csc
+* Description : YUV2RGB\YUV2HSV\YUV2LAB\RGB2YUV color space conversion are supported.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data:
+* 1. SP420\SP422 type for YUV2RGB\YUV2HSV\YUV2LAB;
+* 2. U8C3_PACKAGE\U8C3_PLANAR type for RGB2YUV;
+* MI_IVE_DstImage_t *pstDst Output result:
+* 1. U8C3_PACKAGE\U8C3_PLANAR typed for YUV2RGB\YUV2HSV\YUV2LAB;
+* 2. SP420\SP422 type for RGB2YUV;
+* MI_IVE_CscCtrl_t *pstCscCtrl Control parameters for CSC
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Csc(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_CscCtrl_t *pstCscCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_FilterAndCsc
+* Description : Only support YUV2RGB color space conversion.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task.
+* MI_IVE_SrcImage_t *pstSrc Input source data.Only SP420\SP422 type are supported.
+* MI_IVE_DstImage_t *pstDst Output result.Only U8C3_PACKAGE\U8C3_PLANAR are supported.
+* MI_IVE_FilterAndCscCtrl_t *pstFltCscCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_FilterAndCsc(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_FilterAndCscCtrl_t *pstFltCscCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Sobel
+* Description : SOBEL is used to extract the gradient information.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data. Only the U8C1 input image is supported.
+* MI_IVE_DstImage_t *pstDstH The (horizontal) result of input image filtered by the input mask;
+* MI_IVE_DstImage_t *pstDstV The (vertical) result of input image filtered by the transposed mask;
+* MI_IVE_SobelCtrl_t *pstSobelCtrl Control parameters
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Sobel(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDstH, MI_IVE_DstImage_t *pstDstV,
+ MI_IVE_SobelCtrl_t *pstSobelCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_MagAndAng
+* Description : MagAndAng is used to extract the edge information.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SRC_INFO_S *pstSrc Input source data. Only the U8C1 input format is supported.
+* MI_IVE_MemInfo_t *pstDstMag Output magnitude.
+* MI_IVE_MemInfo_t *pstDstAng Output angle.
+* If the output mode is set to magnitude only,
+* this item can be set to null.
+* MI_IVE_MagAndAngCtrl_t *pstMagAndAngCtrl Control parameters
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_MagAndAng(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDstMag, MI_IVE_DstImage_t *pstDstAng,
+ MI_IVE_MagAndAngCtrl_t *pstMagAndAngCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Dilate
+* Description : 5x5 template dilate. Only the U8C1 binary image input is supported.Or else the result is not expected.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input binary image, which consists of 0 or 255;
+* MI_IVE_DstImage_t *pstDst Output result.
+* MI_IVE_DilateCtrl_t *pstDilateCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* The input value, output value, and mask value must be 0 or 255.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Dilate(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_DilateCtrl_t *pstDilateCtrl,MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Erode
+* Parameters : 5x5 template erode. Only the U8C1 binary image input is supported.Or else the result is not correct.
+* Input : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input binary image, which consists of 0 or 255;
+* MI_IVE_DstImage_t *pstDst Output result.
+* MI_IVE_ErodeCtrl_t *pstErodeCtrl Control parameters
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* The input value, output value, and mask value must be 0 or 255.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Erode(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_ErodeCtrl_t *pstErodeCtrl,MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Thresh
+* Description : Thresh operation to the input image.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data. Only the U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result
+* MI_IVE_ThreshCtrl_t *pstThrCtrl Control parameters
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Thresh(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_ThreshCtrl_t *pstThrCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_And
+* Description : Binary images' And operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 The input source1. Only U8C1 input format is supported.
+* MI_IVE_SrcImage_t *pstSrc2 The input source2.Only U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result of " src1 & src2 ".
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of two input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_And(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1,
+ MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstImage_t *pstDst, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Sub
+* Description : Two gray images' Sub operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Minuend of the input source.Only the U8C1 input format is supported.
+* MI_IVE_SrcImage_t *pstSrc2 Subtrahend of the input source.Only the U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result of src1 minus src2
+* MI_IVE_SubCtrl_t *pstSubCtrl Control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of two input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Sub(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1,
+ MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstImage_t *pstDst, MI_IVE_SubCtrl_t *pstSubCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Or
+* Description : Two binary images' Or operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Input source1. Only the U8C1 input format is supported.
+* MI_IVE_SrcImage_t *pstSrc2 Input source2. Only the U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result src1 or src2
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of two input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Or(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1,
+ MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstImage_t *pstDst, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_INTEG
+* Description : Calculate the input gray image's integral image.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data.Only the U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result.Can be U32C1 or U64C1, relied on the control parameter.
+* MI_IVE_IntegCtrl_t *pstIntegCtrl Integ Control
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* The pixel can be 32bit or 64 bit relied on the control parameter.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Integ(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_IntegCtrl_t *pstIntegCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Hist
+* Description : Calculate the input gray image's histogram.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data. Only the U8C1 input format is supported.
+* MI_IVE_DstMemInfo_t *pstDst Output result.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Hist(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstMemInfo_t *pstDst, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_ThreshS16
+* Description : S16 image's THRESH operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data.Only the S16 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result.
+* MI_IVE_ThreshS16Ctrl_t *pstThrS16Ctrl Control parameters
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of the input data must be 2-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_ThreshS16(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_ThreshS16Ctrl_t *pstThrS16Ctrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_ThreshU16
+* Description : U16 image's THRESH operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data. Only the U16 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result
+* MI_IVE_ThreshU16Ctrl_t *pstThrU16Ctrl Control parameters
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of the input data must be 2-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_ThreshU16(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_ThreshU16Ctrl_t *pstThrU16Ctrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_16BitTo8Bit
+* Description : Scale the input 16bit data to the output 8bit data.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data.Only U16C1\S16C1 input is supported.
+* MI_IVE_DstImage_t *pstDst Output result
+* MI_IVE_16BITTO8BIT_CTRL_S *pst16BitTo8BitCtrl control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of the input data must be 2-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_16BitTo8Bit(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_16bitTo8BitCtrl_t *pst16BitTo8BitCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_OrdStatFilter
+* Description : Order Statistic Filter. It can be used as median\max\min value filter.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data. Only U8C1 input is supported
+* MI_IVE_DstImage_t *pstDst Output result
+* MI_IVE_OrdStatFilter_t *pstOrdStatFltCtrl Control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_OrdStatFilter(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_OrdStatFilter_t *pstOrdStatFltCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Map
+* Description : Map a image to another through a lookup table.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source. Only the U8C1 input format is supported.
+* MI_IVE_SrcMemInfo_t *pstMap Input lookup table. Must be an U8 array of size 256.
+* MI_IVE_DstImage_t *pstDst Output result.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Map(MI_IVE_HANDLE hHandle,MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_SrcMemInfo_t *pstMap, MI_IVE_DstImage_t *pstDst,MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_EqualizeHist
+* Description : Enhance the input image's contrast through histogram equalization.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source.Only U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result.
+* MI_IVE_EQUALIZEHIST_CTRL_S *pstEqualizeHistCtrl EqualizeHist control parameter.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The physical addresses of map data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_EqualizeHist(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_EqualizeHistCtrl_t *pstEqualizeHistCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Add
+* Description : Two gray images' Add operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Augend of the input source.Only the U8C1 input format is supported.
+* MI_IVE_SrcImage_t *pstSrc2 Addend of the input source.Only the U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstDst Output result of src1 plus src2
+* MI_IVE_AddCtrl_t *pstAddCtrl Control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of two input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Add(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1,
+ MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstImage_t *pstDst, MI_IVE_AddCtrl_t *pstAddCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Xor
+* Description : Two binary images' Xor operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 The input source1.Only the U8C1 input format is supported.
+* MI_IVE_SrcImage_t *pstSrc2 The input source2.
+* MI_IVE_DstImage_t *pstDst Output result
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of two input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Xor(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1,
+ MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstImage_t *pstDst, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Ncc
+* Description : Calculate two gray images' NCC (Normalized Cross Correlation).
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Input source1. Only the U8C1 input format is supported.
+* MI_IVE_SrcImage_t *pstSrc2 Input source2. Must be of the same type��size of source1.
+* MI_IVE_DstMemInfo_t *pstDst Output result
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Ncc(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1,
+ MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstMemInfo_t *pstDst, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Ccl
+* Description : Connected Component Labeling. Only 8-Connected method is supported.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrcDst Input source
+* MI_IVE_DstMemInfo_t *pstBlob Output result of detected region;
+* MI_IVE_CclCtrl_t *pstCclCtrl CCL control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 720x640 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Ccl(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrcDst,
+ MI_IVE_DstMemInfo_t *pstBlob, MI_IVE_CclCtrl_t *pstCclCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Gmm
+* Description : Separate foreground and background using GMM(Gaussian Mixture Model) method;
+* Gray or RGB GMM are supported.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source. Only support U8C1 or U8C3_PACKAGE input.
+* MI_IVE_DstImage_t *pstFg Output foreground (Binary) image.
+* MI_IVE_DstImage_t *pstBg Output background image. Of the sampe type of pstSrc.
+* MI_IVE_MemInfo_t *pstModel Model data.
+* MI_IVE_GmmCtrl_t *pstGmmCtrl Control parameter.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 720x576 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Gmm(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc, MI_IVE_DstImage_t *pstFg,
+ MI_IVE_DstImage_t *pstBg, MI_IVE_MemInfo_t *pstModel, MI_IVE_GmmCtrl_t *pstGmmCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_CannyHysEdge
+* Description : The first part of canny Edge detection. Including step: gradient calculation,
+* magnitude and angle calculation, hysteresis threshold, NMS(Non-Maximum Suppression)
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source. Only the U8C1 input format is supported
+* MI_IVE_DstImage_t *pstEdge Output result.
+* MI_IVE_DstMemInfo_t *pstStack OutPut stack for CannyEdge
+* MI_IVE_CannyHysEdgeCtrl_t *pstCannyHysEdgeCtrl Control parameter.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned. .
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_CannyHysEdge(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc, MI_IVE_DstImage_t *pstEdge,
+ MI_IVE_DstMemInfo_t *pstStack, MI_IVE_CannyHysEdgeCtrl_t *pstCannyHysEdgeCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_CannyEdge
+* Description : The second part of canny Edge detection: trace strong edge by weak edge.
+* Parameters : MI_IVE_SrcImage_t *pstEdge Input and Output source. Only the U8C1 format is supported
+* MI_IVE_MemInfo_t *pstStack stack for CannyEdge
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_CannyEdge(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstEdge, MI_IVE_MemInfo_t *pstStack, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Lbp
+* Description : LBP calculation using the original method and a extensional method.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source.Only the U8C1 inpu format is supported.
+* MI_IVE_DstImage_t *pstDst Output result
+* MI_IVE_LbpCtrrl_t *pstLbpCtrl Control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Lbp(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1, MI_IVE_SrcImage_t *pstSrc2,
+ MI_IVE_DstImage_t *pstDst, MI_IVE_LbpCtrrl_t *pstLbpCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_NormGrad
+* Description : Gradient calculation and the output is normalized to S8.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source data
+* MI_IVE_DstImage_t *pstDstH The (horizontal) result of input image filtered by the input mask;
+* MI_IVE_DstImage_t *pstDstV The (vertical) result of input image filtered by the transposed mask;
+* MI_IVE_DstImage_t *pstDstHV Output the horizontal and vertical component in single image in package format.
+* MI_IVE_NormGradCtrl_t *pstNormGradCtrl Control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1024 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_NormGrad(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDstH, MI_IVE_DstImage_t *pstDstV, MI_IVE_DstImage_t *pstDstHV,
+ MI_IVE_NormGradCtrl_t *pstNormGradCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_LkOpticalFlow
+* Description : Calculate LK-Optical Flow in single-layer of the pyramid.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrcPre Pre-frame input source.Must be U8C1 image
+* MI_IVE_SrcImage_t *pstSrcCur Cur-frame input source.Same size��type with pstPreSrc.
+* MI_IVE_SrcMemInfo_t *pstPoint Intresting points coordinates in the cur-layer
+* for LKOpticalFlow tracking.
+* MI_IVE_MemInfo_t *pstMv Accumlative movements of the interesting points in pre-layers
+* or init 0s for the first-layer as input. init 0s .
+* Movements of the interesting points being tracked in cur-layer
+* as output.
+* MI_IVE_LKOPTICALFLOW_CTRL_S *pstLkOptiFlowCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 720x576 pixels.
+* The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* History:
+****************************************************************************/
+MI_S32 MI_IVE_LkOpticalFlow(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrcPre, MI_IVE_SrcImage_t *pstSrcCur,
+ MI_IVE_SrcMemInfo_t *pstPoint, MI_IVE_MemInfo_t *pstMv, MI_IVE_LkOpticalFlowCtrl_t *pstLkOptiFlowCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Sad
+* Description : Sum of absolute differences.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 The input source1.Only the U8C1 input format is supported.
+* MI_IVE_SrcImage_t *pstSrc2 The input source2.Only the U8C1 input format is supported.
+* MI_IVE_DstImage_t *pstSad Output result of sad value.Only the U8C1/U16C1 format is supported.
+* MI_IVE_DstImage_t *pstThr Output result of thresh.Only the U8C1 format is supported.
+* MI_IVE_SadCtrl_t *pstSadCtrl Control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of two input sources must be the same.
+* Not support in hi3516a
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Sad(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1,
+ MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstImage_t *pstSad, MI_IVE_DstImage_t *pstThr,
+ MI_IVE_SadCtrl_t *pstSadCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Resize
+* Description : Resize image
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source.
+* MI_IVE_DstImage_t *pstDst Output result
+* MVE_IVE_ResizeCtrl_t *pstResizeCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 32x12 pixels to 1920x1080 pixels.
+* The input and output height must be 2-pixel-aligned with mode YUV420SP.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Resize(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst, MVE_IVE_ResizeCtrl_t *pstResizeCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Bernsen
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source.
+* MI_IVE_DstImage_t *pstDst Output result
+* MVE_IVE_BernsenCtrl_t *pstBernsenCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* The type of source and destination must be U8C1.
+* The input size and output size must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Bernsen(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstImage_t *pstDst,MVE_IVE_BernsenCtrl_t *pstBernsenCtrl,MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_AdpThresh
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source.
+* MI_IVE_SrcImage_t *pstInteg Input integral image of source.
+* MI_IVE_DstImage_t *pstDst Output result
+* MVE_IVE_AdpThreshCtrl_t *pstAdpThrCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The physical addresses of the input data and output data must be 16-byte-aligned.
+* The type of source and destination must be U8C1.
+* The stride must be 16-pixel-aligned.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_AdpThresh(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_SrcImage_t *pstInteg, MI_IVE_DstImage_t *pstDst, MVE_IVE_AdpThreshCtrl_t *pstAdpThrCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_LineFilterHor
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrcDst Input and output source.
+* MVE_IVE_LineFilterHorCtrl_t *pstLineFilterHorCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The type of input source must be U8C1.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_LineFilterHor(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrcDst,
+ MVE_IVE_LineFilterHorCtrl_t *pstLineFilterHorCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_LineFilterVer
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrcDst Input and output source.
+* MVE_IVE_LineFilterVerCtrl_t *pstLineFilterVerCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The type of input source must be U8C1.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_LineFilterVer(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrcDst,
+ MVE_IVE_LineFilterVerCtrl_t *pstLineFilterVerCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_NoiseRemoveHor
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrcDst Input and output source.
+* MVE_IVE_NoiseRemoveHorCtrl_t *pstNoiseRemoveHorCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The type of input source must be U8C1.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_NoiseRemoveHor(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrcDst,
+ MVE_IVE_NoiseRemoveHorCtrl_t *pstNoiseRemoveHorCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_NoiseRemoveVer
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrcDst Input and output source.
+* MVE_IVE_NoiseRemoveVerCtrl_t *pstNoiseRemoveVerCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The type of input source must be U8C1.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_NoiseRemoveVer(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrcDst,
+ MVE_IVE_NoiseRemoveVerCtrl_t *pstNoiseRemoveVerCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Acc
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc0 First input source.
+* MI_IVE_SrcImage_t *pstSrc1 Second input source.
+* MVE_IVE_AccCtrl_t *pstAccCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* The size of two input source must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Acc(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc0,
+ MI_IVE_SrcImage_t *pstSrc1, MI_IVE_DstImage_t *pstDst, MVE_IVE_AccCtrl_t *pstAccCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_MVE_BAT
+* Description :
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc Input source.
+* MI_IVE_DstMemInfo_t *pstDstH First output.
+* MI_IVE_DstMemInfo_t *pstDstV Second output.
+* MVE_IVE_BatCtrl_t *pstCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The physical addresses of the input data and output data must be 16-byte-aligned.
+* The stride must be 16-pixel-aligned.
+* The type of input source must be U8C1.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_BAT(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc,
+ MI_IVE_DstMemInfo_t *pstDstH, MI_IVE_DstMemInfo_t *pstDstV, MVE_IVE_BatCtrl_t *pstCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Matrix_Transform
+* Description : Matrix transform operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Input source 1.
+* MI_IVE_SrcImage_t *pstSrc2 Input source 2.
+* MI_IVE_SrcImage_t *pstSrc3 Input source 3.
+* MI_IVE_DstImage_t *pstDst1 Output result 1
+* MI_IVE_DstImage_t *pstDst2 Output result 2
+* MI_IVE_DstImage_t *pstDst3 Output result 3
+* MI_IVE_MatrTranfCtrl_t *pstMatrTranfCtrl Control parameter
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Matrix_Transform(MI_IVE_HANDLE hHandle,
+ MI_IVE_SrcImage_t *pstSrc1, MI_IVE_SrcImage_t *pstSrc2, MI_IVE_SrcImage_t *pstSrc3,
+ MI_IVE_DstImage_t *pstDst1, MI_IVE_DstImage_t *pstDst2, MI_IVE_DstImage_t *pstDst3,
+ MI_IVE_MatrTranfCtrl_t *pstMatrTranfCtrl, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Image_Dot
+* Description : Matrix transform operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Input source 1.
+* MI_IVE_SrcImage_t *pstSrc2 Input source 2.
+* MI_IVE_DstImage_t *pstDst Output result.
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Image_Dot(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1, MI_IVE_SrcImage_t *pstSrc2,
+ MI_IVE_DstImage_t *pstDst, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_AlphaBlending
+* Description : Matrix transform operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Input source 1.
+* MI_IVE_SrcImage_t *pstSrc2 Input source 2.
+* MI_IVE_SrcImage_t *pstAlpha Input alpha table.
+* MI_IVE_DstImage_t *pstDst1 Output result
+* MI_BOOL bInstant Reserved
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_AlphaBlending(MI_IVE_HANDLE hHandle,
+ MI_IVE_SrcImage_t *pstSrc1, MI_IVE_SrcImage_t *pstSrc2, MI_IVE_SrcImage_t *pstAlpha,
+ MI_IVE_DstImage_t *pstDst, MI_BOOL bInstant);
+
+/*****************************************************************************
+* Prototype : MI_IVE_Shift_Detector
+* Description : Matrix transform operation.
+* Parameters : MI_IVE_HANDLE hHandle Handle ID of a task
+* MI_IVE_SrcImage_t *pstSrc1 Input source 1.
+* MI_IVE_SrcImage_t *pstSrc2 Input source 2.
+* MI_IVE_DstImage_t *pstDstX Output result 1.
+* MI_IVE_DstImage_t *pstDstY Output result 2.
+* MI_IVE_SHIFT_DETECT_CTRL_t *pstCtrl Control parameters.
+* MI_BOOL bInstant Reserved
+
+* Return Value : MI_SUCCESS: Success;Error codes: Failure.
+* Spec : The size of the input data ranges from 64x64 pixels to 1920x1080 pixels.
+* The stride must be 16-pixel-aligned.
+* The types, widths, heights of input sources must be the same.
+* History:
+*****************************************************************************/
+MI_S32 MI_IVE_Shift_Detector(MI_IVE_HANDLE hHandle, MI_IVE_SrcImage_t *pstSrc1, MI_IVE_SrcImage_t *pstSrc2, MI_IVE_DstImage_t *pstDstX, MI_IVE_DstImage_t *pstDstY, MI_IVE_SHIFT_DETECT_CTRL_t *pstCtrl, MI_BOOL bInstant);
+
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif
+#endif
+#endif/*_MI_IVE_H_*/
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ive_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ive_datatype.h
new file mode 100644
index 00000000..e23c8f17
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ive_datatype.h
@@ -0,0 +1,831 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_IVE_DATATYPE_H_
+#define _MI_IVE_DATATYPE_H_
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C"{
+#endif
+#endif
+
+#include "mi_common_datatype.h"
+
+#define MI_IVE_HANDLE_MAX (128)
+#define MI_IVE_HIST_NUM (256)
+#define MI_IVE_MAP_NUM (256)
+#define MI_IVE_MAX_REGION_NUM (255)
+#define MI_IVE_ST_MAX_CORNER_NUM (200)
+#define MI_IVE_MASK_SIZE_5X5 (25)
+#define MI_IVE_CANNY_STACK_RESERVED_SIZE (12)
+
+/************************************************IVE error code ***********************************/
+#define MI_IVE_ERR_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+#define MI_IVE_ERR_INVALID_CHNID MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID)
+#define MI_IVE_ERR_ILLEGAL_PARAM MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+#define MI_IVE_ERR_EXIST MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_EXIST)
+#define MI_IVE_ERR_UNEXIST MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_UNEXIST)
+#define MI_IVE_ERR_NULL_PTR MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR)
+#define MI_IVE_ERR_NOT_CONFIG MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG)
+#define MI_IVE_ERR_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT)
+#define MI_IVE_ERR_NOT_PERM MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM)
+#define MI_IVE_ERR_NOMEM MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM)
+#define MI_IVE_ERR_NOBUF MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOBUF)
+#define MI_IVE_ERR_BUF_EMPTY MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY)
+#define MI_IVE_ERR_BUF_FULL MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL)
+#define MI_IVE_ERR_SYS_NOTREADY MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY)
+#define MI_IVE_ERR_BADADDR MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BADADDR)
+#define MI_IVE_ERR_BUSY MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY)
+#define MI_IVE_ERR_CHN_NOT_STARTED MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NOT_STARTED)
+#define MI_IVE_ERR_CHN_NOT_STOPED MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NOT_STOPED)
+#define MI_IVE_ERR_NOT_INIT MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_INIT)
+#define MI_IVE_ERR_SYS_TIMEOUT MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_TIMEOUT)
+#define MI_IVE_ERR_FAILED MI_DEF_ERR(E_MI_MODULE_ID_IVE, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED)
+
+/*-----------------------------------------------*
+ * The fixed-point data type, will be used to *
+ * represent float data in hardware calculations.*
+ *-----------------------------------------------*/
+
+/*--u8bit----------------------------------------*/
+typedef unsigned char MI_U0Q8;
+typedef unsigned char MI_U1Q7;
+typedef unsigned char MI_U5Q3;
+
+/*--u16bit---------------------------------------*/
+typedef unsigned short MI_U0Q16;
+typedef unsigned short MI_U4Q12;
+typedef unsigned short MI_U6Q10;
+typedef unsigned short MI_U8Q8;
+typedef unsigned short MI_U12Q4;
+typedef unsigned short MI_U14Q2;
+
+/*--s16bit---------------------------------------*/
+typedef short MI_S9Q7;
+typedef short MI_S14Q2;
+typedef short MI_S1Q15;
+
+/*--u32bit---------------------------------------*/
+typedef unsigned int MI_U22Q10;
+typedef unsigned int MI_U25Q7;
+
+/*--s32bit---------------------------------------*/
+typedef int MI_S25Q7;
+typedef int MI_S16Q16;
+
+/*
+* Type of the MI_IVE_Image_t data.
+* Aded by tanbing 2013-7-22
+*/
+typedef enum
+{
+ E_MI_IVE_IMAGE_TYPE_U8C1 = 0x0,
+ E_MI_IVE_IMAGE_TYPE_S8C1 = 0x1,
+ E_MI_IVE_IMAGE_TYPE_YUV420SP = 0x2, /*YUV420 SemiPlanar*/
+ E_MI_IVE_IMAGE_TYPE_YUV422SP = 0x3, /*YUV422 SemiPlanar*/
+ E_MI_IVE_IMAGE_TYPE_YUV420P = 0x4, /*YUV420 Planar */
+ E_MI_IVE_IMAGE_TYPE_YUV422P = 0x5, /*YUV422 planar */
+ E_MI_IVE_IMAGE_TYPE_S8C2_PACKAGE = 0x6,
+ E_MI_IVE_IMAGE_TYPE_S8C2_PLANAR = 0x7,
+ E_MI_IVE_IMAGE_TYPE_S16C1 = 0x8,
+ E_MI_IVE_IMAGE_TYPE_U16C1 = 0x9,
+ E_MI_IVE_IMAGE_TYPE_U8C3_PACKAGE = 0xA,
+ E_MI_IVE_IMAGE_TYPE_U8C3_PLANAR = 0xB,
+ E_MI_IVE_IMAGE_TYPE_S32C1 = 0xC,
+ E_MI_IVE_IMAGE_TYPE_U32C1 = 0xD,
+ E_MI_IVE_IMAGE_TYPE_S64C1 = 0xE,
+ E_MI_IVE_IMAGE_TYPE_U64C1 = 0xF,
+
+ E_MI_IVE_IMAGE_TYPE_MAX
+
+}MI_IVE_ImageType_e;
+
+/*
+* Definition of the MI_IVE_Image_t.
+* Added by Tan Bing, 2013-7-22.
+*/
+typedef struct MI_IVE_Image_s
+{
+ MI_IVE_ImageType_e eType;
+
+ MI_PHY aphyPhyAddr[3];
+ MI_U8 *apu8VirAddr[3];
+
+ MI_U16 azu16Stride[3];
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+
+ MI_U16 u16Reserved; /*Can be used such as elemSize*/
+}MI_IVE_Image_t;
+
+typedef MI_IVE_Image_t MI_IVE_SrcImage_t;
+typedef MI_IVE_Image_t MI_IVE_DstImage_t;
+
+/*
+* Definition of the MI_IVE_MemInfo_t.This struct special purpose for input or ouput, such as Hist, CCL, ShiTomasi.
+* Added by Chen Quanfu, 2013-7-23.
+*/
+typedef struct MI_IVE_MemInfo_s
+{
+ MI_PHY phyPhyAddr;
+ MI_U8 *pu8VirAddr;
+ MI_U32 u32Size;
+}MI_IVE_MemInfo_t;
+typedef MI_IVE_MemInfo_t MI_IVE_SrcMemInfo_t;
+typedef MI_IVE_MemInfo_t MI_IVE_DstMemInfo_t;
+
+/*
+*Data struct ,created by Chen Quanfu 2013-07-19
+*/
+typedef struct MI_IVE_Data_s
+{
+ MI_PHY phyPhyAddr; /*Physical address of the data*/
+ MI_U8 *pu8VirAddr;
+
+ MI_U16 u16Stride; /*2D data stride by byte*/
+ MI_U16 u16Width; /*2D data width by byte*/
+ MI_U16 u16Height; /*2D data height*/
+
+ MI_U16 u16Reserved;
+}MI_IVE_Data_s;
+typedef MI_IVE_Data_s MI_IVE_SrcData_t;
+typedef MI_IVE_Data_s MI_IVE_DstData_t;
+
+/*
+* Definition of the union of MI_IVE_Length8bit_u.
+* Added by Tan Bing, 2013-7-22.
+*/
+typedef union
+{
+ MI_S8 s8Val;
+ MI_U8 u8Val;
+}MI_IVE_Length8bit_u;
+
+/*
+* Definition of u16 point
+*/
+typedef struct MI_IVE_PointU16_s
+{
+ MI_U16 u16X;
+ MI_U16 u16Y;
+}MI_IVE_PointU16_t;
+
+/*
+*Float point represented by Fixed-point SQ25.7
+*/
+typedef struct MI_IVE_PointS25Q7_s
+{
+ MI_S25Q7 s25q7X; /*X coordinate*/
+ MI_S25Q7 s25q7Y; /*Y coordinate*/
+}MI_IVE_PointS25Q7_t;
+
+/*
+* Definition of rect
+*/
+typedef struct MI_IVE_Rect_s
+{
+ MI_U16 u16X;
+ MI_U16 u16Y;
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+}MI_IVE_Rect_t;
+
+
+/*
+*Filter control parameters
+*/
+typedef struct MI_IVE_FilterCtrl_s
+{
+ MI_S8 as8Mask[MI_IVE_MASK_SIZE_5X5]; /*Template parameter filter coefficient*/
+ MI_U8 u8Norm; /*Normalization parameter, by right shift*/
+}MI_IVE_FilterCtrl_t;
+
+/*
+* CSC working mode.
+*/
+typedef enum
+{
+ E_MI_IVE_CSC_MODE_PIC_BT601_YUV2RGB = 0x0, /*CSC: YUV2RGB, picture transfer mode, RGB value range [0, 255]*/
+ E_MI_IVE_CSC_MODE_PIC_BT601_YUV2BGR = 0x1, /*CSC: YUV2BGR, picture transfer mode, RGB value range [0, 255]*/
+ E_MI_IVE_CSC_MODE_PIC_BT601_RGB2YUV = 0x2, /*CSC: RGB2YUV, picture transfer mode, YUV:value range [0, 255]*/
+ E_MI_IVE_CSC_MODE_PIC_BT601_BGR2YUV = 0x3, /*CSC: BGR2YUV, picture transfer mode, YUV:value range [0, 255]*/
+ E_MI_IVE_CSC_MODE_MAX
+}MI_IVE_CscMode_e;
+
+/*
+*CSC control parameters
+*/
+typedef struct MI_IVE_CscCtrl_s
+{
+ MI_IVE_CscMode_e eMode; /*Working mode*/
+}MI_IVE_CscCtrl_t;
+
+/*
+*Filter+CSC control parameters
+*/
+typedef struct MI_IVE_FilterAndCscCtrl_s
+{
+ MI_IVE_CscMode_e eMode; /*CSC working mode*/
+ MI_S8 as8Mask[MI_IVE_MASK_SIZE_5X5]; /*Template parameter filter coefficient*/
+ MI_U8 u8Norm; /*Normalization parameter, by right shift*/
+}MI_IVE_FilterAndCscCtrl_t;
+
+/*
+*SOBEL output ctrl
+*/
+typedef enum
+{
+ E_MI_IVE_SOBEL_OUT_CTRL_BOTH = 0x0, /*Output horizontal and vertical*/
+ E_MI_IVE_SOBEL_OUT_CTRL_HOR = 0x1, /*Output horizontal*/
+ E_MI_IVE_SOBEL_OUT_CTRL_VER = 0x2, /*Output vertical*/
+ E_MI_IVE_SOBEL_OUT_CTRL_MAX
+}MI_IVE_SobelOutCtrl_e;
+
+/*
+*SOBEL control parameter
+*/
+typedef struct MI_IVE_SobelCtrl_s
+{
+ MI_IVE_SobelOutCtrl_e eOutCtrl; /*Output format*/
+ MI_S8 as8Mask[MI_IVE_MASK_SIZE_5X5]; /*Template parameter*/
+}MI_IVE_SobelCtrl_t;
+
+/*
+*Type of the magnitude and angle output results
+*/
+typedef enum
+{
+ E_MI_IVE_MAG_AND_ANG_OUT_CTRL_MAG = 0x0, /*Only the magnitude is output.*/
+ E_MI_IVE_MAG_AND_ANG_OUT_CTRL_MAG_AND_ANG = 0x1, /*The magnitude and angle are output.*/
+ E_MI_IVE_MAG_AND_ANG_OUT_CTRL_MAX
+}MI_IVE_MagAndAngOutCtrl_e;
+
+/*
+*Magnitude and angle control parameter
+*/
+typedef struct MI_IVE_MagAndAngCtrl_s
+{
+ MI_IVE_MagAndAngOutCtrl_e eOutCtrl;
+ MI_U16 u16Thr;
+ MI_S8 as8Mask[MI_IVE_MASK_SIZE_5X5]; /*Template parameter.*/
+}MI_IVE_MagAndAngCtrl_t;
+
+/*
+*Dilate control parameters
+*/
+typedef struct MI_IVE_DilateCtrl_s
+{
+ MI_U8 au8Mask[MI_IVE_MASK_SIZE_5X5]; /*The template parameter value must be 0 or 255.*/
+}MI_IVE_DilateCtrl_t;
+
+/*
+*Erode control parameter
+*/
+typedef struct MI_IVE_ErodeCtrl_s
+{
+ MI_U8 au8Mask[MI_IVE_MASK_SIZE_5X5]; /*The template parameter value must be 0 or 255.*/
+}MI_IVE_ErodeCtrl_t;
+
+/*
+* Type of the Thresh mode.
+*/
+typedef enum
+{
+ E_MI_IVE_THRESH_MODE_BINARY = 0x0, /*srcVal <= lowThr, dstVal = minVal; srcVal > lowThr, dstVal = maxVal.*/
+ E_MI_IVE_THRESH_MODE_TRUNC = 0x1, /*srcVal <= lowThr, dstVal = srcVal; srcVal > lowThr, dstVal = maxVal.*/
+ E_MI_IVE_THRESH_MODE_TO_MINVAL = 0x2, /*srcVal <= lowThr, dstVal = minVal; srcVal > lowThr, dstVal = srcVal.*/
+
+ E_MI_IVE_THRESH_MODE_MIN_MID_MAX = 0x3, /*srcVal <= lowThr, dstVal = minVal; lowThr < srcVal <= highThr, dstVal = midVal; srcVal > highThr, dstVal = maxVal.*/
+ E_MI_IVE_THRESH_MODE_ORI_MID_MAX = 0x4, /*srcVal <= lowThr, dstVal = srcVal; lowThr < srcVal <= highThr, dstVal = midVal; srcVal > highThr, dstVal = maxVal.*/
+ E_MI_IVE_THRESH_MODE_MIN_MID_ORI = 0x5, /*srcVal <= lowThr, dstVal = minVal; lowThr < srcVal <= highThr, dstVal = midVal; srcVal > highThr, dstVal = srcVal.*/
+ E_MI_IVE_THRESH_MODE_MIN_ORI_MAX = 0x6, /*srcVal <= lowThr, dstVal = minVal; lowThr < srcVal <= highThr, dstVal = srcVal; srcVal > highThr, dstVal = maxVal.*/
+ E_MI_IVE_THRESH_MODE_ORI_MID_ORI = 0x7, /*srcVal <= lowThr, dstVal = srcVal; lowThr < srcVal <= highThr, dstVal = midVal; srcVal > highThr, dstVal = srcVal.*/
+
+ E_MI_IVE_THRESH_MODE_MAX
+}MI_IVE_ThreshMode_e;
+
+/*
+* Thresh control parameters.
+*/
+typedef struct MI_IVE_ThreshCtrl_s
+{
+ MI_IVE_ThreshMode_e eMode;
+ MI_U8 u8LowThr; /*user-defined threshold, 0<=u8LowThr<=255 */
+ MI_U8 u8HighThr; /*user-defined threshold, if eMode<MI_IVE_THRESH_MODE_MIN_MID_MAX, u8HighThr is not used, else 0<=u8LowThr<=u8HighThr<=255;*/
+ MI_U8 u8MinVal; /*Minimum value when tri-level thresholding*/
+ MI_U8 u8MidVal; /*Middle value when tri-level thresholding, if eMode<2, u32MidVal is not used; */
+ MI_U8 u8MaxVal; /*Maxmum value when tri-level thresholding*/
+}MI_IVE_ThreshCtrl_t;
+
+/*
+*Type of the Sub output results
+*/
+typedef enum
+{
+ E_MI_IVE_SUB_MODE_ABS = 0x0, /*Absolute value of the difference*/
+ E_MI_IVE_SUB_MODE_SMIFT = 0x1, /*The output result is obtained by shifting the result one digit right to reserve the signed bit.*/
+ E_MI_IVE_SUB_MODE_MAX
+}MI_IVE_SubMode_e;
+
+/*
+*Sub control parameters
+*/
+typedef struct MI_IVE_SubCtrl_s
+{
+ MI_IVE_SubMode_e eMode;
+}MI_IVE_SubCtrl_t;
+
+/*
+*Type of the Integ output results, created by Tan Bing, 2013-03-18
+* Modify by Chen Quanfu 2013-07-15
+* Spec: add MI_IVE_INTEG_OUT_CTRL_SQSUM output format
+*/
+typedef enum
+{
+ E_MI_IVE_INTEG_OUT_CTRL_COMBINE = 0x0,
+ E_MI_IVE_INTEG_OUT_CTRL_SUM = 0x1,
+ E_MI_IVE_INTEG_OUT_CTRL_SQSUM = 0x2,
+ E_MI_IVE_INTEG_OUT_CTRL_MAX
+}MI_IVE_IntegOutCtrl_e;
+
+/*
+* Integ control parameters,Create by Chen Quanfu 2013-07-15
+*/
+typedef struct MI_IVE_IntegCtrl_s
+{
+ MI_IVE_IntegOutCtrl_e eOutCtrl;
+}MI_IVE_IntegCtrl_t;
+
+/*
+*Type of the Thresh_S16 mode
+*/
+typedef enum
+{
+ E_MI_IVE_THRESH_S16_MODE_S16_TO_S8_MIN_MID_MAX = 0x0,
+ E_MI_IVE_THRESH_S16_MODE_S16_TO_S8_MIN_ORI_MAX = 0x1,
+ E_MI_IVE_THRESH_S16_MODE_S16_TO_U8_MIN_MID_MAX = 0x2,
+ E_MI_IVE_THRESH_S16_MODE_S16_TO_U8_MIN_ORI_MAX = 0x3,
+
+ E_MI_IVE_THRESH_S16_MODE_MAX
+}MI_IVE_ThreshS16Mode_e;
+
+/*
+*Thresh_S16 control parameters
+*/
+typedef struct MI_IVE_ThreshS16Ctrl_s
+{
+ MI_IVE_ThreshS16Mode_e eMode;
+ MI_S16 s16LowThr; /*User-defined threshold*/
+ MI_S16 s16HighThr; /*User-defined threshold*/
+ MI_IVE_Length8bit_u un8MinVal; /*Minimum value when tri-level thresholding*/
+ MI_IVE_Length8bit_u un8MidVal; /*Middle value when tri-level thresholding*/
+ MI_IVE_Length8bit_u un8MaxVal; /*Maxmum value when tri-level thresholding*/
+}MI_IVE_ThreshS16Ctrl_t;
+
+/*
+*Type of the Thresh_U16 mode
+*/
+typedef enum
+{
+ E_MI_IVE_THRESH_U16_MODE_U16_TO_U8_MIN_MID_MAX = 0x0,
+ E_MI_IVE_THRESH_U16_MODE_U16_TO_U8_MIN_ORI_MAX = 0x1,
+
+ E_MI_IVE_THRESH_U16_MODE_MAX
+}MI_IVE_ThreshU16Mode_e;
+
+/*
+*Thresh_U16 control parameters
+*/
+typedef struct MI_IVE_ThreshU16Ctrl_s
+{
+ MI_IVE_ThreshU16Mode_e eMode;
+ MI_U16 u16LowThr;
+ MI_U16 u16HighThr;
+ MI_U8 u8MinVal;
+ MI_U8 u8MidVal;
+ MI_U8 u8MaxVal;
+}MI_IVE_ThreshU16Ctrl_t;
+
+/*
+*Mode of 16BitTo8Bit
+*/
+typedef enum
+{
+ E_MI_IVE_16BIT_TO_8BIT_MODE_S16_TO_S8 = 0x0,
+ E_MI_IVE_16BIT_TO_8BIT_MODE_S16_TO_U8_ABS = 0x1,
+ E_MI_IVE_16BIT_TO_8BIT_MODE_S16_TO_U8_BIAS = 0x2,
+ E_MI_IVE_16BIT_TO_8BIT_MODE_U16_TO_U8 = 0x3,
+
+ E_MI_IVE_16BIT_TO_8BIT_MODE_MAX
+}MI_IVE_16BitTo8BitMode_e;
+
+/*
+*16BitTo8Bit control parameters
+*/
+typedef struct MI_IVE_16bitTo8BitCtrl_s
+{
+ MI_IVE_16BitTo8BitMode_e eMode;
+ MI_U16 u16Denominator;
+ MI_U8 u8Numerator;
+ MI_S8 s8Bias;
+}MI_IVE_16bitTo8BitCtrl_t;
+
+/*
+*Type of the OrdStaFilter
+*/
+typedef enum
+{
+ E_MI_IVE_ORD_STAT_FILTER_MODE_MEDIAN = 0x0,
+ E_MI_IVE_ORD_STAT_FILTER_MODE_MAX = 0x1,
+ E_MI_IVE_ORD_STAT_FILTER_MODE_MIN = 0x2,
+
+ E_MI_IVE_ORD_STAT_FILTER_MODE_ENUM_MAX
+}MI_IVE_OrdStatFilterMode_e;
+
+/*
+*OrdStaFilter control parameters
+*/
+typedef struct MI_IVE_OrdStatFilter_s
+{
+ MI_IVE_OrdStatFilterMode_e eMode;
+
+}MI_IVE_OrdStatFilter_t;
+
+/*
+* Map LUT memory struct
+*/
+typedef struct MI_IVE_MapLutMem_s
+{
+ MI_U8 au8Map[MI_IVE_MAP_NUM];
+}MI_IVE_MapLutMem_t;
+
+/*
+* Equalizehist control member struct
+*/
+typedef struct MI_IVE_EqualizeHistCtrlMem_s
+{
+ MI_U32 au32Hist[MI_IVE_HIST_NUM];
+ MI_U8 au8Map[MI_IVE_MAP_NUM];
+}MI_IVE_EqualizeHistCtrlMem_t;
+
+/*
+*Equalizehist control parameters,created by Chen Quanfu 2013-07-17
+*/
+typedef struct MI_IVE_EqualizeHistCtrl_s
+{
+ MI_IVE_MemInfo_t stMem;
+}MI_IVE_EqualizeHistCtrl_t;
+
+/*
+*Mode of Add
+*/
+typedef enum
+{
+ E_MI_IVE_ADD_MODE_ROUNDING = 0x0,
+ E_MI_IVE_ADD_MOD_CLIPPING = 0x1,
+
+ E_MI_IVE_ADD_MODE_MAX
+}MI_IVE_AddMode_e;
+
+/*
+*Add control parameters,created by Chen Quanfu 2013-07-17
+*/
+typedef struct MI_IVE_AddCtrl_s
+{
+ MI_IVE_AddMode_e eMode;
+ MI_U0Q16 u0q16X; /*x of "xA+yB"*/
+ MI_U0Q16 u0q16Y; /*y of "xA+yB"*/
+}MI_IVE_AddCtrl_t;
+
+/*
+*NCC dst memory struct
+*/
+typedef struct MI_IVE_NccDstMem_s
+{
+ MI_U64 u64Numerator;
+ MI_U64 u64QuadSum1;
+ MI_U64 u64QuadSum2;
+ MI_U8 au8Reserved[8];
+}MI_IVE_NccDstMem_t;
+
+/*
+*Region struct
+*/
+typedef struct MI_IVE_Region_s
+{
+ MI_U32 u32Area; /*Represented by the pixel number*/
+ MI_U16 u16Left; /*Circumscribed rectangle left border*/
+ MI_U16 u16Right; /*Circumscribed rectangle right border*/
+ MI_U16 u16Top; /*Circumscribed rectangle top border*/
+ MI_U16 u16Bottom; /*Circumscribed rectangle bottom border*/
+}MI_IVE_Region_t;
+
+/*
+*CCBLOB struct
+*/
+typedef struct MI_IVE_CcBlob_s
+{
+ MI_U16 u16CurAreaThr; /*Threshold of the result regions' area*/
+ MI_S8 s8LabelStatus; /*-1: Labeled failed ; 0: Labeled successfully*/
+ MI_U8 u8RegionNum; /*Number of valid region, non-continuous stored*/
+ MI_IVE_Region_t astRegion[MI_IVE_MAX_REGION_NUM]; /*Valid regions with 'u32Area>0' and 'label = ArrayIndex+1'*/
+}MI_IVE_CcBlob_t;
+
+/*
+*CCL control struct
+*/
+typedef struct MI_IVE_Ccl_CTRL_S
+{
+ MI_U16 u16InitAreaThr; /*Init threshold of region area*/
+ MI_U16 u16Step; /*Increase area step for once*/
+}MI_IVE_CclCtrl_t;
+
+/*
+*GMM control struct
+*/
+typedef struct MI_IVE_GmmCtrl_s
+{
+ MI_U22Q10 u22q10NoiseVar; /*Initial noise Variance*/
+ MI_U22Q10 u22q10MaxVar; /*Max Variance*/
+ MI_U22Q10 u22q10MinVar; /*Min Variance*/
+ MI_U0Q16 u0q16LearnRate; /*Learning rate*/
+ MI_U0Q16 u0q16BgRatio; /*Background ratio*/
+ MI_U8Q8 u8q8VarThr; /*Variance Threshold*/
+ MI_U0Q16 u0q16InitWeight; /*Initial Weight*/
+ MI_U8 u8ModelNum; /*Model number: 3 or 5*/
+}MI_IVE_GmmCtrl_t;
+
+/*
+*CannyHysEdge control struct
+*/
+typedef struct MI_IVE_CannyHysEdgeCtrl_s
+{
+ MI_IVE_MemInfo_t stMem;
+ MI_U16 u16LowThr;
+ MI_U16 u16HighThr;
+ MI_S8 as8Mask[MI_IVE_MASK_SIZE_5X5];
+} MI_IVE_CannyHysEdgeCtrl_t;
+
+/*
+*Canny stack size struct
+*/
+typedef struct MI_IVE_CannyStackSize_s
+{
+ MI_U32 u32StackSize; /*Stack size for output*/
+ MI_U8 u8Reserved[MI_IVE_CANNY_STACK_RESERVED_SIZE]; /*For 16 byte align*/
+}MI_IVE_CannyStackSize_t;
+
+/*
+*LBP compare mode
+*/
+typedef enum
+{
+ E_MI_IVE_LBP_CMP_MODE_NORMAL = 0x0, /* P(x)-P(center)>= un8BitThr.s8Val, s(x)=1; else s(x)=0; */
+ E_MI_IVE_LBP_CMP_MODE_ABS = 0x1, /* Abs(P(x)-P(center))>=un8BitThr.u8Val, s(x)=1; else s(x)=0; */
+ E_MI_IVE_LBP_CMP_MODE_ABS_MUL = 0x2,
+
+ E_MI_IVE_LBP_CMP_MODE_MAX
+}MI_IVE_LbpCmpMode_e;
+
+/*
+*LBP channel mode
+*/
+typedef enum
+{
+ E_MI_IVE_LBP_CHAL_MODE_U8C1 = 0x0,
+ E_MI_IVE_LBP_CHAL_MODE_U8C2 = 0x1,
+
+ E_MI_IVE_LBP_CHAL_MODE_MAX
+}MI_IVE_LbpChalMode_e;
+
+/*
+*LBP control struct
+*/
+typedef struct MI_IVE_LbpCtrrl_s
+{
+ MI_IVE_LbpCmpMode_e eMode;
+ MI_IVE_LbpChalMode_e chMode;
+ MI_IVE_Length8bit_u un8BitThr;
+}MI_IVE_LbpCtrrl_t;
+
+/*
+*Type of the GradientFilter output format
+*/
+typedef enum
+{
+ E_MI_IVE_NORM_GRAD_OUT_CTRL_HOR_AND_VER = 0x0,
+ E_MI_IVE_NORM_GRAD_OUT_CTRL_HOR = 0x1,
+ E_MI_IVE_NORM_GRAD_OUT_CTRL_VER = 0x2,
+ E_MI_IVE_NORM_GRAD_OUT_CTRL_COMBINE = 0x3,
+
+ E_MI_IVE_NORM_GRAD_OUT_CTRL_MAX
+}MI_IVE_NormGradOutCtrl_e;
+
+/*
+*GradientFilter control parameters
+*/
+typedef struct MI_IVE_NormGradCtrl_s
+{
+ MI_IVE_NormGradOutCtrl_e eOutCtrl;
+ MI_S8 as8Mask[MI_IVE_MASK_SIZE_5X5];
+ MI_U8 u8Norm;
+}MI_IVE_NormGradCtrl_t;
+
+/*
+* LKOpticalFlow movement
+*/
+typedef struct MI_IVE_MvS9Q7_s
+{
+ MI_S32 s32Status; /*Result of tracking: 0-success; -1-failure*/
+ MI_S9Q7 s9q7Dx; /*X-direction component of the movement*/
+ MI_S9Q7 s9q7Dy; /*Y-direction component of the movement*/
+}MI_IVE_MvS9Q7_t;
+
+typedef struct MI_IVE_LkOpticalFlowCtrl_s
+{
+ MI_U16 u16CornerNum; /*Number of the feature points,<200*/
+ MI_U0Q8 u0q8MinEigThr; /*Minimum eigenvalue threshold*/
+ MI_U8 u8IterCount; /*Maximum iteration times*/
+ MI_U0Q8 u0q8Epsilon; /*Threshold of iteration for dx^2 + dy^2 < u0q8Epsilon */
+}MI_IVE_LkOpticalFlowCtrl_t;
+
+/*
+* Sad mode
+*/
+typedef enum
+{
+ E_MI_IVE_SAD_MODE_MB_4X4 = 0x0, /*4x4*/
+ E_MI_IVE_SAD_MODE_MB_8X8 = 0x1, /*8x8*/
+ E_MI_IVE_SAD_MODE_MB_16X16 = 0x2, /*16x16*/
+
+ E_MI_IVE_SAD_MODE_MAX
+}MI_IVE_SadMode_e;
+/*
+*Sad output ctrl
+*/
+typedef enum
+{
+ E_MI_IVE_SAD_OUT_CTRL_16BIT_BOTH = 0x0, /*Output 16 bit sad and thresh*/
+ E_MI_IVE_SAD_OUT_CTRL_8BIT_BOTH = 0x1, /*Output 8 bit sad and thresh*/
+ E_MI_IVE_SAD_OUT_CTRL_16BIT_SAD = 0x2, /*Output 16 bit sad*/
+ E_MI_IVE_SAD_OUT_CTRL_8BIT_SAD = 0x3, /*Output 8 bit sad*/
+ E_MI_IVE_SAD_OUT_CTRL_THRESH = 0x4, /*Output thresh,16 bits sad */
+
+ E_MI_IVE_SAD_OUT_CTRL_MAX
+}MI_IVE_SadOutCtrl_e;
+/*
+* Sad ctrl param
+*/
+typedef struct MI_IVE_SadCtrl_s
+{
+ MI_IVE_SadMode_e eMode;
+ MI_IVE_SadOutCtrl_e eOutCtrl;
+ MI_U16 u16Thr; /*srcVal <= u16Thr, dstVal = minVal; srcVal > u16Thr, dstVal = maxVal.*/
+ MI_U8 u8MinVal; /*Min value*/
+ MI_U8 u8MaxVal; /*Max value*/
+}MI_IVE_SadCtrl_t;
+
+typedef enum
+{
+ E_MI_IVE_RESIZE_TYPE_U8C1 = 0x0,
+ E_MI_IVE_RESIZE_TYPE_U8C3_PLANAR = 0x1,
+ E_MI_IVE_RESIZE_TYPE_U8C3_PACKAGE = 0x2,
+ E_MI_IVE_RESIZE_TYPE_YUV420SP = 0x3,
+
+ E_MI_IVE_RESIZE_TYPE_MAX
+}MVE_IVE_ResizeMode_e;
+
+typedef struct _MVE_IVE_ResizeCtrl_s
+{
+ MVE_IVE_ResizeMode_e eMode; /*Input and output mode*/
+} MVE_IVE_ResizeCtrl_t;
+
+typedef enum
+{
+ E_MI_IVE_BERNSEN_MODE_NORMAL = 0x00,
+ E_MI_IVE_BERNSEN_MODE_THRESH = 0x01,
+
+ E_MI_IVE_BERNSEN_MODE_MAX
+} MVE_IVE_BernsenMode_e;
+
+typedef struct MVE_IVE_BernsenCtrl_s
+{
+ MVE_IVE_BernsenMode_e enMode;
+ MI_U8 u8WinSize; /*3 or 5*/
+ MI_U8 u8Thr;
+} MVE_IVE_BernsenCtrl_t;
+
+typedef struct MVE_IVE_AdpThreshCtrl_s
+{
+ MI_U8 u8RateThr;
+ MI_U8 u8HalfMaskx;
+ MI_U8 u8HalfMasky;
+ MI_S8 s8Offset;
+ MI_U8 u8ValueThr;
+} MVE_IVE_AdpThreshCtrl_t;
+
+typedef struct MVE_IVE_LineFilterHorCtrl_s
+{
+ MI_U8 u8GapMinLen;
+ MI_U8 u8DensityThr;
+ MI_U8 u8HorThr;
+} MVE_IVE_LineFilterHorCtrl_t;
+
+typedef struct MVE_IVE_LineFilterVerCtrl_s
+{
+ MI_U8 u8VerThr;
+} MVE_IVE_LineFilterVerCtrl_t;
+
+typedef struct MVE_IVE_NoiseRemoveHorCtrl_s
+{
+ MI_U8 u8HorThr;
+ MI_U8 u8HorThrMax;
+} MVE_IVE_NoiseRemoveHorCtrl_t;
+
+typedef struct MVE_IVE_NoiseRemoveVerCtrl_s
+{
+ MI_U8 u8VerThr;
+ MI_U8 u8VerThrMax;
+} MVE_IVE_NoiseRemoveVerCtrl_t;
+
+typedef enum
+{
+ E_MI_IVE_ACC_MODE_INCREASE = 0x0,
+ E_MI_IVE_ACC_MODE_DECREASE = 0x1,
+ E_MI_IVE_ACC_MODE_INCREASE_MAP_255TO1 = 0x2,
+
+ E_MI_IVE_ACC_MODE_MAX
+} MVE_IVE_AccMode_e;
+
+typedef struct MVE_IVE_AccCtrl_s
+{
+ MVE_IVE_AccMode_e enMode;
+} MVE_IVE_AccCtrl_t;
+
+typedef enum
+{
+ E_MI_IVE_BAT_OUT_CTRL_BOTH = 0x0, /*Output horizontal and vertical*/
+ E_MI_IVE_BAT_OUT_CTRL_HOR = 0x1, /*Output horizontal*/
+ E_MI_IVE_BAT_OUT_CTRL_VER = 0x2, /*Output vertical*/
+
+ E_MI_IVE_BAT_OUT_CTRL_MAX
+} MVE_IVE_BatMode_e;
+
+typedef struct MVE_IVE_BatCtrl_s
+{
+ MVE_IVE_BatMode_e enMode;
+ MI_U16 u16HorTimes;
+ MI_U16 u16VerTimes;
+} MVE_IVE_BatCtrl_t;
+
+typedef enum
+{
+ E_MI_IVE_MATRIX_TRANSFORM_TYPE_C1 = 0x0,
+ E_MI_IVE_MATRIX_TRANSFORM_TYPE_C2 = 0x1,
+ E_MI_IVE_MATRIX_TRANSFORM_TYPE_C3 = 0x2,
+
+ E_MI_IVE_MATRIX_TRANSFORM_TYPE_MAX
+}MVE_IVE_MatrTranfMode_e;
+
+typedef struct MI_IVE_MatrTranfCtrl_S
+{
+ MVE_IVE_MatrTranfMode_e enMode; /*Input channel mode*/
+ MI_S32 s32MatrixArray[9]; //Official
+} MI_IVE_MatrTranfCtrl_t;
+
+typedef enum
+{
+ E_MI_IVE_SHIFT_DETECT_MODE_SINGLE = 0x00,
+ E_MI_IVE_SHIFT_DETECT_MODE_MULTI = 0x01,
+
+ E_MI_IVE_SHIFT_DETECT_MODE_MAX
+} MVE_IVE_SHIFT_DETECT_MODE_e;
+
+typedef struct MVE_IVE_SHIFT_DETECT_CTRL_S
+{
+ MVE_IVE_SHIFT_DETECT_MODE_e enMode;
+ MI_U8 pyramid_level;
+ MI_U8 search_range;
+ MI_U16 u16Left;
+ MI_U16 u16Top;
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+} MI_IVE_SHIFT_DETECT_CTRL_t;
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif
+#endif
+#endif/*_MI_IVE_DATATYPE_H_*/
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ldc.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ldc.h
new file mode 100644
index 00000000..7a10d6c0
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ldc.h
@@ -0,0 +1,54 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef __MI_LDC_H__
+#define __MI_LDC_H__
+
+#include "mi_ldc_datatype.h"
+
+#define LDC_MAJOR_VERSION 2
+#define LDC_SUB_VERSION 4
+#define MACRO_TO_STR(macro) #macro
+#define LDC_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_ldc_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_ldc_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_ldc_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_LDC_API_VERSION LDC_VERSION_STR(LDC_MAJOR_VERSION,LDC_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+MI_S32 MI_LDC_CreateDevice(MI_LDC_DEV devId);
+MI_S32 MI_LDC_DestroyDevice(MI_LDC_DEV devId);
+
+MI_S32 MI_LDC_CreateChannel(MI_LDC_DEV devId, MI_LDC_CHN chnId);
+MI_S32 MI_LDC_DestroyChannel(MI_LDC_DEV devId, MI_LDC_CHN chnId);
+
+MI_S32 MI_LDC_StartChannel(MI_LDC_DEV devId, MI_LDC_CHN chnId);
+MI_S32 MI_LDC_StopChannel(MI_LDC_DEV devId, MI_LDC_CHN chnId);
+
+MI_S32 MI_LDC_GetOutputPortAttr(MI_LDC_DEV devId, MI_LDC_CHN chnId, MI_LDC_OutputPortAttr_t *pstOutputAttr);
+
+MI_S32 MI_LDC_SetConfig(MI_LDC_DEV devId, MI_LDC_CHN chnId, void *pConfigAddr, MI_U32 u32ConfigSize);
+
+MI_S32 MI_LDC_InitDev(MI_LDC_InitParam_t *pstInitParam);
+MI_S32 MI_LDC_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ldc_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ldc_datatype.h
new file mode 100644
index 00000000..1c83491e
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_ldc_datatype.h
@@ -0,0 +1,76 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_LDC_DATATYPE_H_
+#define _MI_LDC_DATATYPE_H_
+#include "mi_sys_datatype.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+ E_MI_LDC_ERR_DEV_CREATED = MI_LDC_INITIAL_ERROR_CODE, // dev has been created
+ E_MI_LDC_ERR_DEV_NOT_CREATE, // dev not be created
+ E_MI_LDC_ERR_DEV_NOT_DESTROY, // dev not be destroyed
+ E_MI_LDC_ERR_CHN_CREATED, // chn has been created
+ E_MI_LDC_ERR_CHN_NOT_CREATE, // chn not be created
+ E_MI_LDC_ERR_CHN_NOT_STOP, // chn is still working
+ E_MI_LDC_ERR_CHN_NOT_DESTROY, // chn not be destroyed
+ E_MI_LDC_ERR_PORT_NOT_UNBIND, // port not unbind
+} MI_LDC_ErrCode_e;
+
+typedef MI_U32 MI_LDC_DEV;
+typedef MI_U32 MI_LDC_CHN;
+
+typedef struct MI_LDC_OutputPortAttr_s
+{
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+ MI_SYS_PixelFormat_e ePixelFmt;
+} MI_LDC_OutputPortAttr_t;
+
+typedef struct MI_LDC_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_LDC_InitParam_t;
+
+
+#define MI_LDC_OK MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_INFO, MI_SUCCESS)
+#define MI_ERR_LDC_ILLEGAL_PARAM MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+#define MI_ERR_LDC_NULL_PTR MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR)
+#define MI_ERR_LDC_BUSY MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY)
+#define MI_ERR_LDC_FAIL MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED)
+#define MI_ERR_LDC_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+#define MI_ERR_LDC_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT)
+#define MI_ERR_LDC_MOD_INITED MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INITED)
+#define MI_ERR_LDC_MOD_NOT_INIT MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_INIT)
+#define MI_ERR_LDC_DEV_CREATED MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_DEV_CREATED)
+#define MI_ERR_LDC_DEV_NOT_CREATE MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_DEV_NOT_CREATE)
+#define MI_ERR_LDC_DEV_NOT_DESTROY MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_DEV_NOT_DESTROY)
+#define MI_ERR_LDC_CHN_CREATED MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_CHN_CREATED)
+#define MI_ERR_LDC_CHN_NOT_CREATE MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_CHN_NOT_CREATE)
+#define MI_ERR_LDC_CHN_NOT_STOP MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_CHN_NOT_STOP)
+#define MI_ERR_LDC_CHN_NOT_DESTROY MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_CHN_NOT_DESTROY)
+#define MI_ERR_LDC_PORT_NOT_DISABLE MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_DISABLE)
+#define MI_ERR_LDC_PORT_NOT_UNBIND MI_DEF_ERR(E_MI_MODULE_ID_LDC, E_MI_ERR_LEVEL_ERROR, E_MI_LDC_ERR_PORT_NOT_UNBIND)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VPE_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_md.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_md.h
new file mode 100644
index 00000000..2aafdd8b
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_md.h
@@ -0,0 +1,167 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_MD_H__
+#define __MI_MD_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef enum _MI_MD_RET_E
+{
+ MI_MD_RET_SUCCESS = 0x00000000, /*MD API execution success*/
+ MI_MD_RET_INIT_ERROR = 0x10000401, /*MD init error*/
+ MI_MD_RET_IC_CHECK_ERROR = 0x10000402, /*Incorrect platform check for MD*/
+ MI_MD_RET_INVALID_HANDLE = 0x10000403, /*Invalid MD handle*/
+ MI_MD_RET_INVALID_PARAMETER = 0x10000404, /*Invalid MD parameter*/
+ MI_MD_RET_MALLOC_ERROR = 0x10000405, /*Allocate MD workiung buffer error*/
+
+} MI_MD_RET;
+
+typedef void* MD_HANDLE;
+
+typedef enum MDMB_MODE_E
+{
+ MDMB_MODE_MB_4x4 = 0x0,
+ MDMB_MODE_MB_8x8 = 0x1,
+ MDMB_MODE_MB_16x16 = 0x2,
+ MDMB_MODE_BUTT
+} MDMB_MODE_e;
+
+typedef enum MDSAD_OUT_CTRL_E
+{
+ MDSAD_OUT_CTRL_16BIT_SAD = 0x0,
+ MDSAD_OUT_CTRL_8BIT_SAD = 0x1,
+ MDSAD_OUT_CTRL_BUTT
+} MDSAD_OUT_CTRL_e;
+
+typedef enum MDALG_MODE_E
+{
+ MDALG_MODE_FG = 0x0,
+ MDALG_MODE_SAD = 0x1,
+ MDALG_MODE_FRAMEDIFF = 0x2,
+ MDALG_MODE_BUTT
+} MDALG_MODE_e;
+
+typedef struct MDCCL_ctrl_s
+{
+ uint16_t u16InitAreaThr;
+ uint16_t u16Step;
+} MDCCL_ctrl_t;
+
+typedef struct MDPreproc_ctrl_s
+{
+ uint16_t u16Md_rgn_size;
+ uint16_t u16Align;
+} MDPreproc_ctrl_t;
+
+typedef struct MDblock_info_s
+{
+ uint16_t st_x;
+ uint16_t st_y;
+ uint16_t end_x;
+ uint16_t end_y;
+} MDblock_info_t;
+
+typedef struct MDPoint_s
+{
+ uint16_t x;
+ uint16_t y;
+} MDPoint_t;
+
+typedef struct MDROI_s
+{
+ uint8_t num;
+ MDPoint_t pnt[8];
+} MDROI_t;
+
+typedef struct MDSAD_DATA_s
+{
+ void *paddr;
+ uint32_t stride;
+ MDSAD_OUT_CTRL_e enOutCtrl;
+
+} MDSAD_DATA_t;
+
+typedef struct MDOBJ_s
+{
+ uint32_t u32Area;
+ uint16_t u16Left;
+ uint16_t u16Right;
+ uint16_t u16Top;
+ uint16_t u16Bottom;
+} MDOBJ_t;
+
+typedef struct MDOBJ_DATA_s
+{
+ uint8_t u8RegionNum;
+ MDOBJ_t *astRegion;
+ uint8_t indexofmaxobj;
+ uint32_t areaofmaxobj;
+ uint32_t areaoftotalobj;
+
+} MDOBJ_DATA_t;
+
+typedef struct MI_MD_IMG_s
+{
+ void *pu32PhyAddr;
+ uint8_t *pu8VirAddr;
+} MI_MD_IMG_t;
+
+typedef struct MI_MD_static_param_s
+{
+ uint16_t width;
+ uint16_t height;
+ uint8_t color;
+ uint32_t stride;
+ MDMB_MODE_e mb_size;
+ MDSAD_OUT_CTRL_e sad_out_ctrl;
+ MDROI_t roi_md;
+ MDALG_MODE_e md_alg_mode;
+} MI_MD_static_param_t;
+
+typedef struct MI_MD_param_s
+{
+ uint8_t sensitivity;
+ uint16_t learn_rate;
+ uint32_t md_thr;
+ uint32_t obj_num_max;
+ uint8_t LSD_open;
+} MI_MD_param_t;
+
+uint32_t MI_MD_GetLibVersion();
+MD_HANDLE MI_MD_Init(MI_MD_static_param_t *static_param, MI_MD_param_t *param);
+void MI_MD_Uninit(MD_HANDLE handle);
+int32_t MI_MD_Run(MD_HANDLE handle, const MI_MD_IMG_t* pImage);
+MI_MD_RET MI_MD_Preproc(MD_HANDLE handle, const MI_MD_IMG_t* pImage0, const MI_MD_IMG_t* pImage1, MDPreproc_ctrl_t* PpCtrl, MDSAD_DATA_t *sad_data, MDblock_info_t *md_region);
+
+MI_MD_RET MI_MD_SetParam(MD_HANDLE handle, MI_MD_param_t *param);
+MI_MD_RET MI_MD_GetParam(MD_HANDLE handle, MI_MD_param_t *param);
+MI_MD_RET MI_MD_GetMBResult(MD_HANDLE handle, uint8_t *result_img, uint32_t *result_len);
+
+MI_MD_RET MI_MD_ComputeImageSAD(MD_HANDLE handle, const MI_MD_IMG_t* pImage, MDSAD_DATA_t *sad_data);
+MI_MD_RET MI_MD_CCL(MD_HANDLE handle, MDCCL_ctrl_t* pCclCtrl, MDOBJ_DATA_t *ccobj);
+MI_MD_RET MI_MD_GetMotionCnt(MD_HANDLE handle, uint32_t *obj_cnt);
+MI_MD_RET MI_MD_LightSwitchDetect(MD_HANDLE handle, const MI_MD_IMG_t* pImage, MDOBJ_DATA_t *ccobj);
+
+void MI_MD_SetTime(MD_HANDLE handle, uint32_t time_diff);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MI_MD_H__ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_mipitx.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_mipitx.h
new file mode 100644
index 00000000..cbb937b0
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_mipitx.h
@@ -0,0 +1,52 @@
+/* Copyright (c) 2019-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_MIPITX_H_
+#define _MI_MIPITX_H_
+
+#include "mi_mipitx_datatype.h"
+
+
+#define MIPITX_MAJOR_VERSION 2
+#define MIPITX_SUB_VERSION 0
+#define MACRO_TO_STR(macro) #macro
+#define MIPITX_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_mipitx_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_mipitx_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_mipitx_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_MIPITX_API_VERSION MIPITX_VERSION_STR(MIPITX_MAJOR_VERSION,MIPITX_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_MipiTx_CreateChannel(MI_U32 u32ChannelId, MI_MipiTx_ChannelAttr_t *pstMipiTxChAttr);
+MI_S32 MI_MipiTx_DestroyChannel(MI_U32 u32ChannelId);
+
+MI_S32 MI_MipiTx_GetChannelAttr(MI_U32 u32ChannelId, MI_MipiTx_ChannelAttr_t *pstMipiTxChAttr);
+
+MI_S32 MI_MipiTx_StartChannel(MI_U32 u32ChannelId);
+MI_S32 MI_MipiTx_StopChannel(MI_U32 u32ChannelId);
+
+MI_S32 MI_MipiTx_SetTimingConfig(MI_U32 u32ChannelId, MI_MipiTx_TimingConfig_t *pstMipiTimingCfg);
+MI_S32 MI_MipiTx_GetTimingConfig(MI_U32 u32ChannelId, MI_MipiTx_TimingConfig_t *pstMipiTimingCfg);
+MI_S32 MI_MipiTx_InitDev(MI_MipiTx_InitParam_t *pstInitParam);
+MI_S32 MI_MipiTx_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_mipitx_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_mipitx_datatype.h
new file mode 100644
index 00000000..da137a1b
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_mipitx_datatype.h
@@ -0,0 +1,87 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_MIPITX_DATATYPE_H_
+#define _MI_MIPITX_DATATYPE_H_
+
+#include "mi_sys_datatype.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MI_ERR_MIPITX_CHN_HAVECREATE MI_DEF_ERR(E_MI_MODULE_ID_MIPITX, E_MI_ERR_LEVEL_WARNING, E_MI_ERR_INITED)
+#define MI_ERR_MIPITX_CHNID_INVALID MI_DEF_ERR(E_MI_MODULE_ID_MIPITX, E_MI_ERR_LEVEL_WARNING, E_MI_ERR_INVALID_CHNID)
+#define MI_ERR_MIPITX_CHN_NOTSTOP MI_DEF_ERR(E_MI_MODULE_ID_MIPITX, E_MI_ERR_LEVEL_WARNING, E_MI_ERR_CHN_NOT_STOPED)
+#define MI_ERR_MIPITX_ILLEGAL_PARAM MI_DEF_ERR(E_MI_MODULE_ID_MIPITX, E_MI_ERR_LEVEL_WARNING, E_MI_ERR_ILLEGAL_PARAM)
+
+
+#define MI_ERR_MIPITX_RUNFAIL MI_DEF_ERR(E_MI_MODULE_ID_MIPITX, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_EXIST)
+#define MI_ERR_MIPITX_NULL_PTR MI_DEF_ERR(E_MI_MODULE_ID_MIPITX, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR)
+
+typedef struct MI_MipiTx_TimingConfig_s
+{
+ MI_U8 u8Lpx;
+ MI_U8 u8ClkHsPrpr;
+ MI_U8 u8ClkZero;
+ MI_U8 u8ClkHsPre;
+ MI_U8 u8ClkHsPost;
+ MI_U8 u8ClkTrail;
+ MI_U8 u8HsPrpr;
+ MI_U8 u8HsZero;
+ MI_U8 u8HsTrail;
+} MI_MipiTx_TimingConfig_t;
+
+typedef enum
+{
+ E_MI_MIPITX_LANE_NUM_NONE = 0,
+ E_MI_MIPITX_LANE_NUM_1 = 1,
+ E_MI_MIPITX_LANE_NUM_2 = 2,
+ E_MI_MIPITX_LANE_NUM_3 = 3,
+ E_MI_MIPITX_LANE_NUM_4 = 4,
+} MI_MipiTx_LaneNum_e;
+
+typedef enum
+{
+ E_MI_MIPITX_CH_SWAP_0,
+ E_MI_MIPITX_CH_SWAP_1,
+ E_MI_MIPITX_CH_SWAP_2,
+ E_MI_MIPITX_CH_SWAP_3,
+ E_MI_MIPITX_CH_SWAP_4,
+} MI_MipiTx_ChannelSwapType_e;
+
+typedef struct
+{
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+ MI_SYS_PixelFormat_e ePixFormat; // YUV422 YVYU, RAW8
+ MI_MipiTx_LaneNum_e eLaneNum;
+
+ MI_U8 u8DCLKDelay; ///< DCLK Delay
+ MI_U32 u32Dclk; ///< DCLK ( Htt * Vtt * Fps)
+
+ MI_MipiTx_ChannelSwapType_e *peChSwapType; ///< all lane order swap
+}MI_MipiTx_ChannelAttr_t;
+
+typedef struct MI_MipiTx_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_MipiTx_InitParam_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_od.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_od.h
new file mode 100644
index 00000000..921dfda8
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_od.h
@@ -0,0 +1,108 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_OD_H__
+#define __MI_OD_H__
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+typedef enum _MI_OD_RET_E
+{
+ MI_OD_RET_SUCCESS = 0x00000000, /*OD API execution success*/
+
+ MI_OD_RET_INIT_ERROR = 0x10000501, /*OD init error*/
+ MI_OD_RET_IC_CHECK_ERROR = 0x10000502, /*Incorrect platform check for OD*/
+ MI_OD_RET_INVALID_HANDLE = 0x10000503, /*Invalid OD handle*/
+ MI_OD_RET_INVALID_PARAMETER = 0x10000504, /*Invalid OD parameter*/
+ MI_OD_RET_INVALID_WINDOW = 0x10000505, /*Invalid window*/
+ MI_OD_RET_INVALID_COLOR_TYPE = 0x10000506, /*Invalid color tpye*/
+} MI_OD_RET;
+typedef enum _MI_OD_WIN_STATE
+{
+ MI_OD_WIN_STATE_NON_TAMPER = 0,
+ MI_OD_WIN_STATE_TAMPER = 1,
+ MI_OD_WIN_STATE_NO_FEATURE = 2,
+ MI_OD_WIN_STATE_FAIL = -1,
+} MI_OD_WIN_STATE;
+
+typedef enum
+{
+ OD_Y = 1,
+ OD_COLOR_MAX
+} ODColor_e;
+
+typedef enum
+{
+ OD_WINDOW_1X1 = 0,
+ OD_WINDOW_2X2,
+ OD_WINDOW_3X3,
+ OD_WINDOW_MAX
+} ODWindow_e;
+
+typedef struct ODPoint_s
+{
+ uint16_t x;
+ uint16_t y;
+} ODPoint_t;
+
+typedef struct ODROI_s
+{
+ uint8_t num;
+ ODPoint_t pnt[8];
+} ODROI_t;
+
+typedef struct MI_OD_IMG_s
+{
+ void *pu32PhyAddr;
+ uint8_t *pu8VirAddr;
+} MI_OD_IMG_t;
+
+typedef struct MI_OD_static_param_s
+{
+ uint16_t inImgW;
+ uint16_t inImgH;
+ uint32_t inImgStride;
+ ODColor_e nClrType;
+ ODWindow_e div;
+ ODROI_t roi_od;
+ int32_t alpha;
+ int32_t M;
+ int32_t MotionSensitivity;
+
+} MI_OD_static_param_t;
+
+typedef struct MI_OD_param_s
+{
+ int32_t thd_tamper;
+ int32_t tamper_blk_thd;
+ int32_t min_duration;
+} MI_OD_param_t;
+
+typedef void* OD_HANDLE;
+
+uint32_t MI_OD_GetLibVersion();
+OD_HANDLE MI_OD_Init(MI_OD_static_param_t *static_param, MI_OD_param_t *param);
+int32_t MI_OD_Run(OD_HANDLE odHandle, const MI_OD_IMG_t* yImage);
+MI_OD_RET MI_OD_GetDetectWindowSize(OD_HANDLE odHandle, uint16_t* st_x, uint16_t* st_y, uint16_t* div_w, uint16_t* div_h);
+MI_OD_WIN_STATE MI_OD_GetWindowResult(OD_HANDLE odHandle, uint8_t col, uint8_t row);
+MI_OD_RET MI_OD_SetAttr(OD_HANDLE odHandle, MI_OD_param_t *param);
+MI_OD_RET MI_OD_GetAttr(OD_HANDLE odHandle, MI_OD_param_t *param);
+void MI_OD_Uninit(OD_HANDLE odHandle);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__MI_OD_H__
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_panel.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_panel.h
new file mode 100644
index 00000000..056bf847
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_panel.h
@@ -0,0 +1,56 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_PANEL_H_
+#define _MI_PANEL_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+#include "mi_panel_datatype.h"
+
+#define PANEL_MAJOR_VERSION 2
+#define PANEL_SUB_VERSION 12
+#define MACRO_TO_STR(macro) #macro
+#define PANEL_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_panel_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_panel_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_panel_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_PANEL_API_VERSION PANEL_VERSION_STR(PANEL_MAJOR_VERSION,PANEL_SUB_VERSION)
+
+MI_S32 MI_PANEL_Init(MI_PANEL_IntfType_e eIntfType);
+MI_S32 MI_PANEL_DeInit(void);
+MI_S32 MI_PANEL_GetTotalNum(MI_U32 *pu32TotalNum);
+MI_S32 MI_PANEL_SetPowerOn(MI_PANEL_IntfType_e eIntfType, MI_PANEL_PowerConfig_t *pstPowerCfg);
+MI_S32 MI_PANEL_GetPowerOn(MI_PANEL_IntfType_e eIntfType, MI_PANEL_PowerConfig_t *pstPowerCfg);
+MI_S32 MI_PANEL_SetBackLight(MI_PANEL_IntfType_e eIntfType, MI_PANEL_BackLightConfig_t *pstBackLightCfg);
+MI_S32 MI_PANEL_GetBackLight(MI_PANEL_IntfType_e eIntfType, MI_PANEL_BackLightConfig_t *pstBackLightCfg);
+MI_S32 MI_PANEL_SetBackLightLevel(MI_PANEL_IntfType_e eIntfType, MI_PANEL_BackLightConfig_t *pstBackLightCfg);
+MI_S32 MI_PANEL_GetBackLightLevel(MI_PANEL_IntfType_e eIntfType, MI_PANEL_BackLightConfig_t *pstBackLightCfg);
+MI_S32 MI_PANEL_SetSscConfig(MI_PANEL_IntfType_e eIntfType, MI_PANEL_SscConfig_t *pstSscCfg);
+MI_S32 MI_PANEL_SetMipiDsiConfig(MI_PANEL_IntfType_e eIntfType, MI_PANEL_MipiDsiConfig_t *pstMipiDsiCfg);
+MI_S32 MI_PANEL_SetTimingConfig(MI_PANEL_IntfType_e eIntfType, MI_PANEL_TimingConfig_t *pstTimingCfg);
+MI_S32 MI_PANEL_SetDrvCurrentConfig(MI_PANEL_IntfType_e eIntfType, MI_PANEL_DrvCurrentConfig_t *pstDrvCurrentCfg);
+MI_S32 MI_PANEL_SetOutputPattern(MI_PANEL_IntfType_e eIntfType, MI_PANEL_TestPatternConfig_t * pstTestPatternCfg);
+MI_S32 MI_PANEL_SetPanelParam(MI_PANEL_IntfType_e eIntfType, MI_PANEL_ParamConfig_t *pstParamCfg);
+MI_S32 MI_PANEL_GetPanelParam(MI_PANEL_IntfType_e eIntfType, MI_PANEL_ParamConfig_t *pstParamCfg);
+MI_S32 MI_PANEL_InitDev(MI_PANEL_InitParam_t *pstInitParam);
+MI_S32 MI_PANEL_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif ///_MI_PANEL_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_panel_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_panel_datatype.h
new file mode 100644
index 00000000..159c3ad6
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_panel_datatype.h
@@ -0,0 +1,346 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_PANEL_DATATYPE_H_
+#define _MI_PANEL_DATATYPE_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+
+
+/*-------------------------------------------------------------------------------------------------
+ * Enum
+ ------------------------------------------------------------------------------------------------*/
+
+typedef enum
+{
+ E_MI_PNL_MIPI_DSI_LANE_NONE = 0,
+ E_MI_PNL_MIPI_DSI_LANE_1 = 1,
+ E_MI_PNL_MIPI_DSI_LANE_2 = 2,
+ E_MI_PNL_MIPI_DSI_LANE_3 = 3,
+ E_MI_PNL_MIPI_DSI_LANE_4 = 4,
+}MI_PANEL_MipiDsiLaneMode_e;
+
+typedef enum
+{
+ E_MI_PNL_MIPI_DSI_RGB565 = 0,
+ E_MI_PNL_MIPI_DSI_RGB666 = 1,
+ E_MI_PNL_MIPI_DSI_LOOSELY_RGB666 = 2,
+ E_MI_PNL_MIPI_DSI_RGB888 = 3,
+}MI_PANEL_MipiDsiFormat_e;
+
+typedef enum
+{
+ E_MI_PNL_MIPI_DSI_CMD_MODE = 0,
+ E_MI_PNL_MIPI_DSI_SYNC_PULSE = 1,
+ E_MI_PNL_MIPI_DSI_SYNC_EVENT = 2,
+ E_MI_PNL_MIPI_DSI_BURST_MODE = 3,
+}MI_PANEL_MipiDsiCtrlMode_e;
+
+typedef enum
+{
+ E_MI_PNL_INTF_TTL, ///< TTL type
+ E_MI_PNL_INTF_LVDS, ///< LVDS type
+ E_MI_PNL_INTF_RSDS, ///< RSDS type
+ E_MI_PNL_INTF_MINILVDS, ///< TCON
+ E_MI_PNL_INTF_ANALOG_MINILVDS, ///< Analog TCON
+ E_MI_PNL_INTF_DIGITAL_MINILVDS, ///< Digital TCON
+ E_MI_PNL_INTF_MFC, ///< Ursa (TTL output to Ursa)
+ E_MI_PNL_INTF_DAC_I, ///< DAC output
+ E_MI_PNL_INTF_DAC_P, ///< DAC output
+ E_MI_PNL_INTF_PDPLVDS, ///< For PDP(Vsync use Manually MODE)
+ E_MI_PNL_INTF_EXT, ///< EXT LPLL TYPE
+ E_MI_PNL_INTF_MIPI_DSI, ///< Mipi DSI
+ E_MI_PNL_INTF_BT656,
+ E_MI_PNL_INTF_BT601, ///< BT601
+ E_MI_PNL_INTF_BT1120, ///< BT1120
+ E_MI_PNL_INTF_MCU_TYPE, ///< MCU Type
+ E_MI_PNL_INTF_SRGB, ///< sRGB
+ E_MI_PNL_INTF_TTL_SPI_IF, ///< TTL with SPI init interface
+}MI_PANEL_IntfType_e;
+
+typedef enum
+{
+ E_MI_PNL_ASPECT_RATIO_4_3 = 0, ///< set aspect ratio to 4 : 3
+ E_MI_PNL_ASPECT_RATIO_WIDE, ///< set aspect ratio to 16 : 9
+ E_MI_PNL_ASPECT_RATIO_OTHER, ///< resvered for other aspect ratio other than 4:3/ 16:9
+}MI_PANEL_AspectRatio_e;
+
+typedef enum
+{
+ E_MI_PNL_TI_10BIT_MODE = 0,
+ E_MI_PNL_TI_8BIT_MODE = 2,
+ E_MI_PNL_TI_6BIT_MODE = 3,
+}MI_PANEL_TiBitMode_e;
+
+typedef enum
+{
+ E_MI_PNL_OUTPUT_10BIT_MODE = 0, //default is 10bit, becasue 8bit panel can use 10bit config and 8bit config.
+ E_MI_PNL_OUTPUT_6BIT_MODE = 1, //but 10bit panel(like PDP panel) can only use 10bit config.
+ E_MI_PNL_OUTPUT_8BIT_MODE = 2, //and some PDA panel is 6bit.
+ E_MI_PNL_OUTPUT_565BIT_MODE = 3,
+}MI_PANEL_OutputFormatBitMode_e;
+
+typedef enum
+{
+ E_MI_PNL_CHG_DCLK = 0, ///<change output DClk to change Vfreq.
+ E_MI_PNL_CHG_HTOTAL = 1, ///<change H total to change Vfreq.
+ E_MI_PNL_CHG_VTOTAL = 2, ///<change V total to change Vfreq.
+}MI_PANEL_OutputTimingMode_e;
+
+typedef enum
+{
+ E_MI_PNL_CH_SWAP_0,
+ E_MI_PNL_CH_SWAP_1,
+ E_MI_PNL_CH_SWAP_2,
+ E_MI_PNL_CH_SWAP_3,
+ E_MI_PNL_CH_SWAP_4,
+}MI_PANEL_ChannelSwapType_e;
+
+typedef enum
+{
+ E_MI_PNL_MIPI_DSI_PACKET_TYPE_DCS = 0,
+ E_MI_PNL_MIPI_DSI_PACKET_TYPE_GENERIC = 1,
+}MI_PANEL_MipiDsiPacketType_e;
+/*-------------------------------------------------------------------------------------------------
+ * Structures
+ ------------------------------------------------------------------------------------------------*/
+
+typedef struct
+{
+ MI_BOOL bEn;
+}MI_PANEL_PowerConfig_t;
+
+typedef struct
+{
+ MI_BOOL bEn;
+ MI_U16 u16Duty;
+ MI_U16 u16Period;
+}MI_PANEL_BackLightConfig_t;
+
+typedef struct
+{
+ MI_BOOL bEn;
+ MI_U16 u16Freq;// khz
+ MI_U16 u16Ratio;// 1/1000
+}MI_PANEL_SscConfig_t;
+
+typedef struct
+{
+ MI_U8 u8HsTrail;
+ MI_U8 u8HsPrpr;
+ MI_U8 u8HsZero;
+ MI_U8 u8ClkHsPrpr;
+ MI_U8 u8ClkHsExit;
+ MI_U8 u8ClkTrail;
+ MI_U8 u8ClkZero;
+ MI_U8 u8ClkHsPost;
+ MI_U8 u8DaHsExit;
+ MI_U8 u8ContDet;
+
+ MI_U8 u8Lpx;
+ MI_U8 u8TaGet;
+ MI_U8 u8TaSure;
+ MI_U8 u8TaGo;
+
+ MI_U16 u16Hactive;
+ MI_U16 u16Hpw;
+ MI_U16 u16Hbp;
+ MI_U16 u16Hfp;
+
+ MI_U16 u16Vactive;
+ MI_U16 u16Vpw;
+ MI_U16 u16Vbp;
+ MI_U16 u16Vfp;
+
+ MI_U16 u16Bllp;
+ MI_U16 u16Fps;
+
+ MI_PANEL_MipiDsiLaneMode_e enLaneNum;
+ MI_PANEL_MipiDsiFormat_e enformat;
+ MI_PANEL_MipiDsiCtrlMode_e enCtrl;
+
+ MI_U8 *pu8CmdBuf;
+ MI_U32 u32CmdBufSize;
+
+ MI_U8 u8SyncCalibrate;
+ MI_U16 u16VirHsyncSt;
+ MI_U16 u16VirHsyncEnd;
+ MI_U16 u16VsyncRef;
+ MI_U16 u16DataClkSkew;
+
+ MI_U8 u8PolCh0; // channel 0 polarity, 0:HW default, 1:positive, 2:negative
+ MI_U8 u8PolCh1; // channel 1 polarity, 0:HW default, 1:positive, 2:negative
+ MI_U8 u8PolCh2; // channel 2 polarity, 0:HW default, 1:positive, 2:negative
+ MI_U8 u8PolCh3; // channel 3 polarity, 0:HW default, 1:positive, 2:negative
+ MI_U8 u8PolCh4; // channel 4 polarity, 0:HW default, 1:positive, 2:negative
+
+ MI_PANEL_MipiDsiPacketType_e ePacketType;
+}MI_PANEL_MipiDsiConfig_t;
+
+typedef struct
+{
+ MI_U16 u16HSyncWidth;
+ MI_U16 u16HSyncBackPorch;
+ MI_U16 u16HSyncFrontPorch;
+
+ MI_U16 u16VSyncWidth;
+ MI_U16 u16VSyncBackPorch;
+ MI_U16 u16VSyncFrontPorch;
+
+ MI_U16 u16HStart;
+ MI_U16 u16VStart;
+
+ MI_U16 u16Height;
+ MI_U16 u16Width;
+
+ MI_U16 u16HTotal;
+ MI_U16 u16VTotal;
+
+ MI_U16 u16Dclk;
+}MI_PANEL_TimingConfig_t;
+
+typedef struct
+{
+ MI_U16 u16DrvCurrent;
+}MI_PANEL_DrvCurrentConfig_t;
+
+typedef struct
+{
+ MI_BOOL bEn;
+ MI_U16 u16R;
+ MI_U16 u16G;
+ MI_U16 u16B;
+}MI_PANEL_TestPatternConfig_t;
+
+typedef struct
+{
+ const char *pPanelName; ///< PanelName
+ MI_U8 u8Dither; ///< PANEL_DITHER, keep the setting
+ MI_PANEL_IntfType_e eIntfType; ///< PANEL_LINK
+
+ ///////////////////////////////////////////////
+ // Board related setting
+ ///////////////////////////////////////////////
+ MI_U8 u8DualPort; ///< VOP_21[8], MOD_4A[1], PANEL_DUAL_PORT, refer to u8DoubleClk
+ MI_U8 u8SwapPort; ///< MOD_4A[0], PANEL_SWAP_PORT, refer to "LVDS output app note" A/B channel swap
+ MI_U8 u8SwapOdd_ML; ///< PANEL_SWAP_ODD_ML
+ MI_U8 u8SwapEven_ML; ///< PANEL_SWAP_EVEN_ML
+ MI_U8 u8SwapOdd_RB; ///< PANEL_SWAP_ODD_RB
+ MI_U8 u8SwapEven_RB; ///< PANEL_SWAP_EVEN_RB
+
+ MI_U8 u8SwapLVDS_POL; ///< MOD_40[5], PANEL_SWAP_LVDS_POL, for differential P/N swap
+ MI_U8 u8SwapLVDS_CH; ///< MOD_40[6], PANEL_SWAP_LVDS_CH, for pair swap
+ MI_U8 u8PDP10BIT; ///< MOD_40[3], PANEL_PDP_10BIT ,for pair swap
+ MI_U8 u8LVDS_TI_MODE; ///< MOD_40[2], PANEL_LVDS_TI_MODE, refer to "LVDS output app note"
+
+ ///////////////////////////////////////////////
+ // For TTL Only
+ ///////////////////////////////////////////////
+ MI_U8 u8DCLKDelay; ///< PANEL_DCLK_DELAY
+ MI_U8 u8InvDCLK; ///< MOD_4A[4], PANEL_INV_DCLK
+ MI_U8 u8InvDE; ///< MOD_4A[2], PANEL_INV_DE
+ MI_U8 u8InvHSync; ///< MOD_4A[12], PANEL_INV_HSYNC
+ MI_U8 u8InvVSync; ///< MOD_4A[3], PANEL_INV_VSYNC
+
+ ///////////////////////////////////////////////
+ // Output driving current setting
+ ///////////////////////////////////////////////
+ // driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
+ MI_U8 u8DCKLCurrent; ///< define PANEL_DCLK_CURRENT
+ MI_U8 u8DECurrent; ///< define PANEL_DE_CURRENT
+ MI_U8 u8ODDDataCurrent; ///< define PANEL_ODD_DATA_CURRENT
+ MI_U8 u8EvenDataCurrent; ///< define PANEL_EVEN_DATA_CURRENT
+
+ ///////////////////////////////////////////////
+ // panel on/off timing
+ ///////////////////////////////////////////////
+ MI_U16 u16OnTiming1; ///< time between panel & data while turn on power
+ MI_U16 u16OnTiming2; ///< time between data & back light while turn on power
+ MI_U16 u16OffTiming1; ///< time between back light & data while turn off power
+ MI_U16 u16OffTiming2; ///< time between data & panel while turn off power
+
+ ///////////////////////////////////////////////
+ // panel timing spec.
+ ///////////////////////////////////////////////
+ // sync related
+ MI_U16 u16HSyncWidth; ///< VOP_01[7:0], PANEL_HSYNC_WIDTH
+ MI_U16 u16HSyncBackPorch; ///< PANEL_HSYNC_BACK_PORCH, no register setting, provide value for query only
+ MI_U16 u16VSyncWidth; ///< define PANEL_VSYNC_WIDTH
+ MI_U16 u16VSyncBackPorch; ///< define PANEL_VSYNC_BACK_PORCH
+
+ // DE related
+ MI_U16 u16HStart; ///< VOP_04[11:0], PANEL_HSTART, DE H Start (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
+ MI_U16 u16VStart; ///< VOP_06[11:0], PANEL_VSTART, DE V Start
+ MI_U16 u16Width; ///< PANEL_WIDTH, DE width (VOP_05[11:0] = HEnd = HStart + Width - 1)
+ MI_U16 u16Height; ///< PANEL_HEIGHT, DE height (VOP_07[11:0], = Vend = VStart + Height - 1)
+
+ // DClk related
+ MI_U16 u16MaxHTotal; ///< PANEL_MAX_HTOTAL. Reserved for future using.
+ MI_U16 u16HTotal; ///< VOP_0C[11:0], PANEL_HTOTAL
+ MI_U16 u16MinHTotal; ///< PANEL_MIN_HTOTAL. Reserved for future using.
+ MI_U16 u16MaxVTotal; ///< PANEL_MAX_VTOTAL. Reserved for future using.
+ MI_U16 u16VTotal; ///< VOP_0D[11:0], PANEL_VTOTAL
+ MI_U16 u16MinVTotal; ///< PANEL_MIN_VTOTAL. Reserved for future using.
+ MI_U16 u16MaxDCLK; ///< PANEL_MAX_DCLK. Reserved for future using.
+ MI_U16 u16DCLK; ///< LPLL_0F[23:0], PANEL_DCLK
+ MI_U16 u16MinDCLK; ///< PANEL_MIN_DCLK. Reserved for future using.
+
+ ///< spread spectrum
+ MI_U16 u16SpreadSpectrumStep; ///< move to board define, no use now.
+ MI_U16 u16SpreadSpectrumSpan; ///< move to board define, no use now.
+
+ MI_U8 u8PwmPeriodL; ///< Initial Dimming Value
+ MI_U8 u8PwmPeriodH; ///< Max Dimming Value
+ MI_U8 u8PwmDuty; ///< Min Dimming Value
+
+ MI_U8 u8DeinterMode; ///< define PANEL_DEINTER_MODE, no use now
+ MI_PANEL_AspectRatio_e ePanelAspectRatio; ///< Panel Aspect Ratio, provide information to upper layer application for aspect ratio setting.
+
+ MI_U16 u16LVDSTxSwapValue;
+ MI_PANEL_TiBitMode_e eTiBitMode; ///< MOD_4B[1:0], refer to "LVDS output app note"
+ MI_PANEL_OutputFormatBitMode_e eOutputFormatBitMode;
+
+ MI_U8 u8SwapOdd_RG; ///< define PANEL_SWAP_ODD_RG
+ MI_U8 u8SwapEven_RG; ///< define PANEL_SWAP_EVEN_RG
+ MI_U8 u8SwapOdd_GB; ///< define PANEL_SWAP_ODD_GB
+ MI_U8 u8SwapEven_GB; ///< define PANEL_SWAP_EVEN_GB
+
+ /**
+ * Others
+ */
+ MI_U8 u8DoubleClk; ///< LPLL_03[7], define Double Clock ,LVDS dual mode
+ MI_U32 u32MaxSET; ///< define PANEL_MAX_SET
+ MI_U32 u32MinSET; ///< define PANEL_MIN_SET
+ MI_PANEL_OutputTimingMode_e eOutTimingMode; ///<Define which panel output timing change mode is used to change VFreq for same panel
+ MI_U8 u8NoiseDith; ///< PAFRC mixed with noise dither disable
+
+ MI_PANEL_ChannelSwapType_e eCh0;
+ MI_PANEL_ChannelSwapType_e eCh1;
+ MI_PANEL_ChannelSwapType_e eCh2;
+ MI_PANEL_ChannelSwapType_e eCh3;
+ MI_PANEL_ChannelSwapType_e eCh4;
+}MI_PANEL_ParamConfig_t;
+
+typedef struct MI_PANEL_InitParam_s
+{
+ MI_PANEL_IntfType_e eIntfType;
+} MI_PANEL_InitParam_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif //_MI_PANEL_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_rgn.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_rgn.h
new file mode 100644
index 00000000..69fb620a
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_rgn.h
@@ -0,0 +1,54 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_RGN_H_
+#define _MI_RGN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+#include "mi_rgn_datatype.h"
+
+#define RGN_MAJOR_VERSION 2
+#define RGN_SUB_VERSION 7
+#define MACRO_TO_STR(macro) #macro
+#define RGN_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_rgn_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_rgn_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_rgn_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_RGN_API_VERSION RGN_VERSION_STR(RGN_MAJOR_VERSION,RGN_SUB_VERSION)
+
+MI_S32 MI_RGN_Init(MI_RGN_PaletteTable_t *pstPaletteTable);
+MI_S32 MI_RGN_DeInit(void);
+MI_S32 MI_RGN_Create(MI_RGN_HANDLE hHandle, MI_RGN_Attr_t *pstRegion);
+MI_S32 MI_RGN_Destroy (MI_RGN_HANDLE hHandle);
+MI_S32 MI_RGN_GetAttr(MI_RGN_HANDLE hHandle, MI_RGN_Attr_t *pstRegion);
+MI_S32 MI_RGN_SetBitMap(MI_RGN_HANDLE hHandle, MI_RGN_Bitmap_t *pstBitmap);
+MI_S32 MI_RGN_AttachToChn(MI_RGN_HANDLE hHandle, MI_RGN_ChnPort_t* pstChnPort, MI_RGN_ChnPortParam_t *pstChnAttr);
+MI_S32 MI_RGN_DetachFromChn(MI_RGN_HANDLE hHandle, MI_RGN_ChnPort_t *pstChnPort);
+MI_S32 MI_RGN_SetDisplayAttr(MI_RGN_HANDLE hHandle, MI_RGN_ChnPort_t *pstChnPort, MI_RGN_ChnPortParam_t *pstChnPortAttr);
+MI_S32 MI_RGN_GetDisplayAttr(MI_RGN_HANDLE hHandle, MI_RGN_ChnPort_t *pstChnPort, MI_RGN_ChnPortParam_t *pstChnPortAttr);
+MI_S32 MI_RGN_GetCanvasInfo(MI_RGN_HANDLE hHandle, MI_RGN_CanvasInfo_t* pstCanvasInfo);
+MI_S32 MI_RGN_UpdateCanvas(MI_RGN_HANDLE hHandle);
+MI_S32 MI_RGN_ScaleRect(MI_RGN_ChnPort_t *pstChnPort, MI_RGN_Size_t *pstCanvasSize, MI_RGN_Size_t *pstScreenSize);
+MI_S32 MI_RGN_InitDev(MI_RGN_InitParam_t *pstInitParam);
+MI_S32 MI_RGN_DeInitDev(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_MI_RGN_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_rgn_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_rgn_datatype.h
new file mode 100644
index 00000000..c4b2b7ad
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_rgn_datatype.h
@@ -0,0 +1,244 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_RGN_DATATYPE_
+#define __MI_RGN_DATATYPE_
+
+#define MI_RGN_MAX_HANDLE 1024
+#define MI_RGN_HANDLE_NULL -1
+#define MI_RGN_MAX_PALETTE_TABLE_NUM 256
+
+typedef enum
+{
+ E_MI_RGN_MODID_VPE = 0,
+ E_MI_RGN_MODID_DIVP,
+ E_MI_RGN_MODID_LDC,
+ E_MI_RGN_MODID_MAX
+}MI_RGN_ModId_e;
+
+typedef enum
+{
+ E_MI_RGN_TYPE_OSD = 0,
+ E_MI_RGN_TYPE_COVER,
+ E_MI_RGN_TYPE_MAX
+} MI_RGN_Type_e;
+
+typedef enum
+{
+ E_MI_RGN_PIXEL_FORMAT_ARGB1555 = 0,
+ E_MI_RGN_PIXEL_FORMAT_ARGB4444,
+ E_MI_RGN_PIXEL_FORMAT_I2,
+ E_MI_RGN_PIXEL_FORMAT_I4,
+ E_MI_RGN_PIXEL_FORMAT_I8,
+ E_MI_RGN_PIXEL_FORMAT_RGB565,
+ E_MI_RGN_PIXEL_FORMAT_ARGB8888,
+ E_MI_RGN_PIXEL_FORMAT_MAX
+} MI_RGN_PixelFormat_e;
+
+typedef struct MI_RGN_ChnPort_s
+{
+ MI_RGN_ModId_e eModId;
+ MI_S32 s32DevId;
+ MI_S32 s32ChnId;
+ MI_S32 s32OutputPortId;
+}MI_RGN_ChnPort_t;
+
+typedef struct MI_RGN_Size_s
+{
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+} MI_RGN_Size_t;
+
+typedef struct MI_RGN_Bitmap_s
+{
+ MI_RGN_PixelFormat_e ePixelFormat;
+ MI_RGN_Size_t stSize;
+ void *pData;
+} MI_RGN_Bitmap_t;
+
+typedef struct MI_RGN_OsdInitParam_s
+{
+ MI_RGN_PixelFormat_e ePixelFmt;
+ MI_RGN_Size_t stSize;
+}MI_RGN_OsdInitParam_t;
+
+
+typedef struct MI_RGN_Point_s
+{
+ MI_U32 u32X;
+ MI_U32 u32Y;
+}MI_RGN_Point_t;
+
+
+typedef enum
+{
+ E_MI_RGN_ABOVE_LUMA_THRESHOLD = 0,
+ E_MI_RGN_BELOW_LUMA_THRESHOLD,
+ E_MI_RGN_LUMA_THRESHOLD_BUTT
+}MI_RGN_InvertColorMode_e;
+typedef enum
+{
+ E_MI_RGN_PIXEL_ALPHA = 0,
+ E_MI_RGN_CONSTANT_ALPHA
+}MI_RGN_AlphaMode_e;
+
+typedef struct MI_RGN_OsdInvertColorAttr_s
+{
+ MI_BOOL bEnableColorInv;
+ MI_RGN_InvertColorMode_e eInvertColorMode;
+ MI_U16 u16LumaThreshold;
+ MI_U16 u16WDivNum;
+ MI_U16 u16HDivNum;
+}MI_RGN_OsdInvertColorAttr_t;
+
+typedef struct MI_RGN_OsdArgb1555Alpha_s
+{
+ MI_U8 u8BgAlpha;
+ MI_U8 u8FgAlpha;
+}MI_RGN_OsdArgb1555Alpha_t;
+typedef union
+{
+ MI_RGN_OsdArgb1555Alpha_t stArgb1555Alpha;
+ MI_U8 u8ConstantAlpha;
+} MI_RGN_AlphaModePara_u;
+
+typedef struct MI_RGN_OsdAlphaAttr_s
+{
+ MI_RGN_AlphaMode_e eAlphaMode;
+ MI_RGN_AlphaModePara_u stAlphaPara;
+}MI_RGN_OsdAlphaAttr_t;
+
+typedef struct MI_RGN_Rect_s
+{
+ MI_S32 s32X;
+ MI_S32 s32Y;
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+}MI_RGN_Rect_t;
+
+
+typedef struct MI_RGN_CoverChnPortParam_s
+{
+ MI_U32 u32Layer;
+ MI_RGN_Size_t stSize;
+ MI_U32 u32Color;
+}MI_RGN_CoverChnPortParam_t;
+
+typedef struct MI_RGN_OsdChnPortParam_s
+{
+ MI_U32 u32Layer;
+ MI_RGN_OsdAlphaAttr_t stOsdAlphaAttr;
+ MI_RGN_OsdInvertColorAttr_t stColorInvertAttr;
+}MI_RGN_OsdChnPortParam_t;
+
+typedef struct MI_RGN_Attr_s
+{
+ MI_RGN_Type_e eType;
+ MI_RGN_OsdInitParam_t stOsdInitParam;
+}MI_RGN_Attr_t;
+
+typedef struct MI_RGN_CoverChnParam_s
+{
+ MI_RGN_Rect_t stRect;
+ MI_U32 u32Color;
+ MI_U32 u32Layer;
+}MI_RGN_CoverChnParam_t;
+
+typedef union
+{
+ MI_RGN_CoverChnPortParam_t stCoverChnPort;
+ MI_RGN_OsdChnPortParam_t stOsdChnPort;
+} MI_RGN_ChnPortParamUnion_u;
+
+typedef struct MI_RGN_ChnPortParam_s
+{
+ MI_BOOL bShow;
+ MI_RGN_Point_t stPoint;
+ MI_RGN_ChnPortParamUnion_u unPara;
+} MI_RGN_ChnPortParam_t;
+
+
+typedef struct MI_RGN_CanvasInfo_s
+{
+ MI_PHY phyAddr;
+ MI_VIRT virtAddr;
+ MI_RGN_Size_t stSize;
+ MI_U32 u32Stride;
+ MI_RGN_PixelFormat_e ePixelFmt;
+} MI_RGN_CanvasInfo_t;
+
+typedef struct MI_RGN_PaletteElement_s
+{
+ MI_U8 u8Alpha;
+ MI_U8 u8Red;
+ MI_U8 u8Green;
+ MI_U8 u8Blue;
+}MI_RGN_PaletteElement_t;
+
+typedef struct MI_RGN_PaletteTable_s
+{
+ MI_RGN_PaletteElement_t astElement[MI_RGN_MAX_PALETTE_TABLE_NUM];
+}MI_RGN_PaletteTable_t;
+
+
+typedef struct MI_RGN_InitParam_s
+{
+ MI_RGN_PaletteTable_t *pstPaletteTable;
+} MI_RGN_InitParam_t;
+
+#define MI_RGN_OK MI_SUCCESS
+
+/* PingPong buffer change when set attr, it needs to remap memory in mpi interface */
+#define MI_NOTICE_RGN_BUFFER_CHANGE MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_INFO, MI_SUCCESS)
+
+/* invlalid handle */
+#define MI_ERR_RGN_INVALID_HANDLE MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+/* invlalid device ID */
+#define MI_ERR_RGN_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+/* invlalid channel ID */
+#define MI_ERR_RGN_INVALID_CHNID MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID)
+/* at lease one parameter is illagal ,eg, an illegal enumeration value */
+#define MI_ERR_RGN_ILLEGAL_PARAM MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+/* channel exists */
+#define MI_ERR_RGN_EXIST MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_EXIST)
+/*UN exist*/
+#define MI_ERR_RGN_UNEXIST MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_UNEXIST)
+/* using a NULL point */
+#define MI_ERR_RGN_NULL_PTR MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR)
+/* try to enable or initialize system,device or channel, before configing attribute */
+#define MI_ERR_RGN_NOT_CONFIG MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG)
+/* operation is not supported by NOW */
+#define MI_ERR_RGN_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT)
+/* operation is not permitted ,eg, try to change stati attribute */
+#define MI_ERR_RGN_NOT_PERM MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM)
+/* failure caused by malloc memory */
+#define MI_ERR_RGN_NOMEM MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM)
+/* failure caused by malloc buffer */
+#define MI_ERR_RGN_NOBUF MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOBUF)
+/* no data in buffer */
+#define MI_ERR_RGN_BUF_EMPTY MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY)
+/* no buffer for new data */
+#define MI_ERR_RGN_BUF_FULL MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL)
+/* bad address, eg. used for copy_from_user & copy_to_user */
+#define MI_ERR_RGN_BADADDR MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BADADDR)
+/* resource is busy, eg. destroy a venc chn without unregistering it */
+#define MI_ERR_RGN_BUSY MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY)
+
+/* System is not ready,maybe not initialed or loaded.
+ * Returning the error code when opening a device file failed.
+ */
+#define MI_ERR_RGN_NOTREADY MI_DEF_ERR(E_MI_MODULE_ID_RGN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY)
+
+
+#endif /* End of #ifndef __MI_RGN_DATATYPE_ */
+
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sed.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sed.h
new file mode 100644
index 00000000..5f168297
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sed.h
@@ -0,0 +1,49 @@
+/*
+* mi_sed.h- Sigmastar
+*
+* Copyright (C) 2018 Sigmastar Technology Corp.
+*
+* Author: XXXX <XXXX@sigmastar.com.cn>
+*
+* This software is licensed under the terms of the GNU General Public
+* License version 2, as published by the Free Software Foundation, and
+* may be copied, distributed, and modified under those terms.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+*/
+#ifndef _MI_SED_H_
+#define _MI_SED_H_
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "mi_sed_datatype.h"
+
+#define SED_MAJOR_VERSION 2
+#define SED_SUB_VERSION 1
+#define MACRO_TO_STR(macro) #macro
+#define SED_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_sed_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_sed_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_sed_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_SED_API_VERSION SED_VERSION_STR(SED_MAJOR_VERSION, SED_SUB_VERSION)
+
+MI_S32 MI_SED_CreateChn(MI_SED_CHN SedChn, MI_SED_DetectorAttr_t* pstAttr);
+MI_S32 MI_SED_DestroyChn(MI_SED_CHN SedChn);
+MI_S32 MI_SED_StartDetector(MI_SED_CHN SedChn);
+MI_S32 MI_SED_StopDetector(MI_SED_CHN SedChn);
+MI_S32 MI_SED_AttachToVencChn(MI_SED_CHN SedChn, MI_SED_TARGET_CHN TargetChn);
+MI_S32 MI_SED_DetachFromVencChn(MI_SED_CHN SedChn, MI_SED_TARGET_CHN TargetChn);
+MI_S32 MI_SED_GetRect(MI_SED_CHN SedChn, MI_SED_RectInfo_t *pstRectInfo);
+MI_S32 MI_SED_SetDbgLevel(MI_DBG_LEVEL_e eLevel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sed_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sed_datatype.h
new file mode 100644
index 00000000..8a656a58
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sed_datatype.h
@@ -0,0 +1,139 @@
+/*
+* mi_sed_datatype.h- Sigmastar
+*
+* Copyright (C) 2018 Sigmastar Technology Corp.
+*
+* Author: XXXX <XXXX@sigmastar.com.cn>
+*
+* This software is licensed under the terms of the GNU General Public
+* License version 2, as published by the Free Software Foundation, and
+* may be copied, distributed, and modified under those terms.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+*/
+#ifndef __MI_SED_DATATYPE_
+#define __MI_SED_DATATYPE_
+
+#include "mi_common_datatype.h"
+#include "mi_sys_datatype.h"
+
+
+
+#define SED_MAX_CHN_NUM (64)
+#define SED_MAX_ROI_NUM_PER_CHN (16)
+#define SED_MAX_TARGET_CHN_NUM_PER_CHN (8)
+#define SED_MAX_CUS_DEF_ALGOPARAM_NUM (10)
+
+#define MI_DEF_SED_ERR(err) MI_DEF_ERR(29, E_MI_ERR_LEVEL_ERROR, err)
+
+/* invalid channel ID */
+#define MI_ERR_SED_INVALID_CHNID MI_DEF_SED_ERR(E_MI_ERR_INVALID_CHNID)
+/* at lease one parameter is illegal, e.g, an illegal enumeration value */
+#define MI_ERR_SED_ILLEGAL_PARAM MI_DEF_SED_ERR(E_MI_ERR_ILLEGAL_PARAM)
+/* channel exists */
+#define MI_ERR_SED_EXIST MI_DEF_SED_ERR(E_MI_ERR_EXIST)
+/*UN exist*/
+#define MI_ERR_SED_UNEXIST MI_DEF_SED_ERR(E_MI_ERR_UNEXIST)
+/* using a NULL point */
+#define MI_ERR_SED_NULL_PTR MI_DEF_SED_ERR(E_MI_ERR_NULL_PTR)
+/* failure caused by malloc memory */
+#define MI_ERR_SED_NOMEM MI_DEF_SED_ERR(E_MI_ERR_NOMEM)
+/* channel not start*/
+#define MI_ERR_SED_CHN_NOT_STARTED MI_DEF_SED_ERR(E_MI_ERR_CHN_NOT_STARTED)
+/* channel not stop*/
+#define MI_ERR_SED_CHN_NOT_STOPED MI_DEF_SED_ERR(E_MI_ERR_CHN_NOT_STOPED)
+/* channedl not enable*/
+#define MI_ERR_SED_NOT_ENABLE MI_DEF_SED_ERR(E_MI_ERR_NOT_ENABLE)
+
+//==== Variables ====
+typedef MI_S32 MI_SED_TARGET_CHN;
+
+//==== enumerates ====
+typedef enum
+{
+ E_MI_IVEOBJDETECT_ALGOPARAM = 0x0,//MD based object detection, for ROI object tracking
+ E_MI_CNNOBJDETECT_ALGOPARAM = 0x1,//CNN based object detection, for ROI object tracking
+ E_MI_MOTIONDETECT_ALGOPARAM = 0x2,//IVE cased motion detection, for AVBR motion detection
+ E_MI_ALGOPARAM_MAX,
+} MI_SED_AlgoType_e;
+
+//==== Structures ====
+typedef struct MI_SED_InputAttr_s
+{
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+ MI_U32 u32FrameRateNum;
+ MI_U32 u32FrameRateDen;
+ MI_SYS_ChnPort_t stInputPort;
+} MI_SED_InputAttr_t;
+
+
+typedef struct MI_SED_IveObjDetect_Algo_s
+{
+ MI_U32 u32VdfChn;
+ MI_U8 u8Sensitivity;
+} MI_SED_IveObjDetect_Algo_t;
+
+typedef struct MI_SED_CNNObjDetect_Algo_s
+{
+ MI_U32 u32MaxVariableBufSize;
+ MI_U32 u32IPUChnId;
+ MI_U8 *u8FwImagePath;
+ MI_U8 *u8ModelImagePath;
+} MI_SED_CNNObjDetect_Algo_t;
+
+
+typedef struct MI_SED_MotionObjDetect_Algo_s
+{
+ MI_IVE_HANDLE iveHandle;
+
+}MI_SED_MotionObjDetect_Algo_t;
+
+typedef struct MI_SED_Rect_s
+{
+ MI_U32 u32Left;
+ MI_U32 u32Top;
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+} MI_SED_Rect_t;
+
+typedef struct MI_SED_RectInfo_s
+{
+ MI_U32 u32RectCount;
+ MI_SED_Rect_t stRect[SED_MAX_ROI_NUM_PER_CHN];
+} MI_SED_RectInfo_t;
+
+typedef struct MI_SED_AlgoAttr_t
+{
+ MI_SED_AlgoType_e eType;
+ union
+ {
+ MI_SED_IveObjDetect_Algo_t stIveObjDetectAlgo;
+ MI_SED_CNNObjDetect_Algo_t stCNNObjDetectAlgo;
+ MI_SED_MotionObjDetect_Algo_t stMotionObjDetectAlgo;
+ };
+} MI_SED_AlgoAttr_t;
+
+typedef struct MI_SED_TargetAttr_s
+{
+ MI_S32 s32RltQp;
+} MI_SED_TargetAttr_t;
+
+typedef struct MI_SED_DetectorAttr_s
+{
+ //need implement
+ //include: input yuv width/height
+ // MD/OD Algo, CNN human detec
+ // Max ROI number
+ // Background Foreground
+ // framerate
+ MI_SED_InputAttr_t stInputAttr;
+ MI_SED_AlgoAttr_t stAlgoAttr; //Need custom algo result
+ MI_SED_TargetAttr_t stTargetAttr; //Target attribute for smart encoding
+} MI_SED_DetectorAttr_t;
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sensor.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sensor.h
new file mode 100644
index 00000000..56d837d8
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sensor.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_SENSOR_H_
+#define _MI_SENSOR_H_
+
+#include "mi_sensor_datatype.h"
+
+#define SENSOR_MAJOR_VERSION 2
+#define SENSOR_SUB_VERSION 4
+#define MACRO_TO_STR(macro) #macro
+#define SENSOR_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_sensor_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_sensor_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_sensor_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_SENSOR_API_VERSION SENSOR_VERSION_STR(SENSOR_MAJOR_VERSION,SENSOR_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_SNR_Enable(MI_SNR_PAD_ID_e ePADId);
+MI_S32 MI_SNR_Disable(MI_SNR_PAD_ID_e ePADId); // Stop the sensor operation, streaming, mclk
+
+MI_S32 MI_SNR_GetPadInfo(MI_SNR_PAD_ID_e ePADId, MI_SNR_PADInfo_t *pstPadInfo);
+MI_S32 MI_SNR_GetPlaneInfo(MI_SNR_PAD_ID_e ePADId, MI_U32 u32PlaneID, MI_SNR_PlaneInfo_t *pstPlaneInfo);
+
+MI_S32 MI_SNR_GetFps(MI_SNR_PAD_ID_e ePADId, MI_U32 *pFps);
+MI_S32 MI_SNR_SetFps(MI_SNR_PAD_ID_e ePADId, MI_U32 u32Fps);
+
+MI_S32 MI_SNR_GetBT656SrcType(MI_SNR_PAD_ID_e ePADId, MI_U32 u32PlaneID, MI_SNR_Anadec_SrcType_e *psttype);
+
+MI_S32 MI_SNR_QueryResCount(MI_SNR_PAD_ID_e ePADId, MI_U32 *pu32ResCount);
+MI_S32 MI_SNR_GetRes(MI_SNR_PAD_ID_e ePADId, MI_U8 u8ResIdx, MI_SNR_Res_t *pstRes);
+MI_S32 MI_SNR_GetCurRes(MI_SNR_PAD_ID_e ePADId, MI_U8 *pu8CurResIdx, MI_SNR_Res_t *pstCurRes);
+MI_S32 MI_SNR_SetRes(MI_SNR_PAD_ID_e ePADId, MI_U8 u8ResIdx);
+
+MI_S32 MI_SNR_SetOrien(MI_SNR_PAD_ID_e ePADId, MI_BOOL bMirror, MI_BOOL bFlip);
+MI_S32 MI_SNR_GetOrien(MI_SNR_PAD_ID_e ePADId, MI_BOOL *pbMirror, MI_BOOL *pbFlip);
+
+MI_S32 MI_SNR_SetPlaneMode(MI_SNR_PAD_ID_e ePADId, MI_BOOL bEnable);
+MI_S32 MI_SNR_GetPlaneMode(MI_SNR_PAD_ID_e ePADId, MI_BOOL *pbEnable);
+
+MI_S32 MI_SNR_CustFunction(MI_SNR_PAD_ID_e ePADId, MI_U32 u32CmdId, MI_U32 u32DataSize, void *pCustData, MI_SNR_CUST_DIR_e eDir);
+MI_S32 MI_SNR_InitDev(MI_SNR_InitParam_t *pstInitParam);
+MI_S32 MI_SNR_DeInitDev(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sensor_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sensor_datatype.h
new file mode 100644
index 00000000..9ab1d8bf
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sensor_datatype.h
@@ -0,0 +1,166 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_SENSOR_DATATYPE_H_
+#define _MI_SENSOR_DATATYPE_H_
+
+#include "mi_sys_datatype.h"
+#include "mi_vif_datatype.h"
+#pragma pack(push)
+#pragma pack(4)
+
+#define MI_ERR_SNR_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+#define MI_ERR_SNR_INVALID_CHNID MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID)
+#define MI_ERR_SNR_INVALID_PARA MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+#define MI_ERR_SNR_INVALID_NULL_PTR MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR)
+#define MI_ERR_SNR_FAILED_NOTCONFIG MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG)
+#define MI_ERR_SNR_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT)
+#define MI_ERR_SNR_NOT_PERM MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM)
+#define MI_ERR_SNR_NOMEM MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM)
+#define MI_ERR_SNR_BUF_EMPTY MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY)
+#define MI_ERR_SNR_BUF_FULL MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL)
+#define MI_ERR_SNR_SYS_NOTREADY MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY)
+#define MI_ERR_SNR_BUSY MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY)
+#define MI_ERR_SNR_FAIL MI_DEF_ERR(E_MI_MODULE_ID_SNR, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED)
+
+#define MI_SNR_MAX_PADNUM 4
+#define MI_SNR_MAX_PLANENUM 3
+
+typedef struct MI_SNR_Res_s
+{
+ MI_SYS_WindowRect_t stCropRect;
+ MI_SYS_WindowSize_t stOutputSize; /**< Sensor actual output size */
+
+ MI_U32 u32MaxFps; /**< Max fps in this resolution */
+ MI_U32 u32MinFps; /**< Min fps in this resolution*/
+ MI_S8 strResDesc[32]; // Need to put “HDR” here if the resolution is for HDR
+} __attribute__((packed, aligned(4))) MI_SNR_Res_t;
+
+
+typedef enum
+{
+ E_MI_SNR_HDR_HW_MODE_NONE = 0,
+ E_MI_SNR_HDR_HW_MODE_SONY_DOL = 1,
+ E_MI_SNR_HDR_HW_MODE_DCG = 2,
+ E_MI_SNR_HDR_HW_MODE_EMBEDDED_RAW8 = 3,
+ E_MI_SNR_HDR_HW_MODE_EMBEDDED_RAW10 = 4,
+ E_MI_SNR_HDR_HW_MODE_EMBEDDED_RAW12 = 5,
+ E_MI_SNR_HDR_HW_MODE_EMBEDDED_RAW16 = 6, //Only for OV2718?
+} MI_SNR_HDRHWMode_e;
+
+typedef enum
+{
+ E_MI_SNR_PAD_ID_0 = 0,
+ E_MI_SNR_PAD_ID_1 = 1,
+ E_MI_SNR_PAD_ID_2 = 2,
+ E_MI_SNR_PAD_ID_3 = 3,
+ E_MI_SNR_PAD_ID_MAX = 3,
+ E_MI_SNR_PAD_ID_NA = 0xFF,
+} MI_SNR_PAD_ID_e;
+
+typedef enum
+{
+ E_MI_SNR_HDR_SOURCE_VC0,
+ E_MI_SNR_HDR_SOURCE_VC1,
+ E_MI_SNR_HDR_SOURCE_VC2,
+ E_MI_SNR_HDR_SOURCE_VC3,
+ E_MI_SNR_HDR_SOURCE_MAX
+} MI_SNR_HDRSrc_e;
+
+typedef enum
+{
+ E_MI_SNR_CUSTDATA_TO_DRIVER,
+ E_MI_SNR_CUSTDATA_TO_USER,
+ E_MI_SNR_CUSTDATA_MAX = E_MI_SNR_CUSTDATA_TO_USER,
+} MI_SNR_CUST_DIR_e;
+
+typedef struct MI_SNR_AttrParallel_s
+{
+ MI_VIF_SyncAttr_t stSyncAttr;
+} MI_SNR_AttrParallel_t;
+// Should be the same structure definition with the one used in VIF
+
+typedef struct MI_SNR_MipiAttr_s
+{
+ MI_U32 u32LaneNum;
+ MI_U32 u32DataFormat; //0: YUV 422 format. 1: RGB pattern.
+ MI_VIF_DataYuvSeq_e eDataYUVOrder;
+ MI_U32 u32HsyncMode;
+ MI_U32 u32Sampling_delay;
+ /** < MIPI start sampling delay */ /*bit 0~7: clk_skip_ns. bit 8~15: data_skip_ns*/
+ MI_SNR_HDRHWMode_e eHdrHWmode;
+ MI_U32 u32Hdr_Virchn_num; //??
+ MI_U32 u32Long_packet_type[2]; //??
+}MI_SNR_MipiAttr_t;
+
+typedef struct MI_SNR_AttrBt656_s
+{
+ MI_U32 u32Multiplex_num;
+ MI_VIF_SyncAttr_t stSyncAttr;
+ MI_VIF_ClkEdge_e eClkEdge;
+ MI_VIF_BitOrder_e eBitSwap;
+} MI_SNR_AttrBt656_t;
+
+typedef union {
+ MI_SNR_AttrParallel_t stParallelAttr;
+ MI_SNR_MipiAttr_t stMipiAttr;
+ MI_SNR_AttrBt656_t stBt656Attr;
+} MI_SNR_IntfAttr_u;
+
+typedef struct MI_SNR_PADInfo_s
+{
+ MI_U32 u32PlaneCount; //It is different expo number for HDR. It is mux number for BT656. //??
+ MI_VIF_IntfMode_e eIntfMode;
+ MI_VIF_HDRType_e eHDRMode;
+ MI_SNR_IntfAttr_u unIntfAttr;
+ MI_BOOL bEarlyInit;
+} MI_SNR_PADInfo_t;
+
+typedef struct MI_SNR_PlaneInfo_s
+{
+ MI_U32 u32PlaneID;// For HDR long/short exposure or BT656 channel 0~3
+ MI_S8 s8SensorName[32];
+ MI_SYS_WindowRect_t stCapRect;
+ MI_SYS_BayerId_e eBayerId;
+ MI_SYS_DataPrecision_e ePixPrecision;
+ MI_SNR_HDRSrc_e eHdrSrc;
+ MI_U32 u32ShutterUs;
+ MI_U32 u32SensorGainX1024;
+ MI_U32 u32CompGain;
+ MI_SYS_PixelFormat_e ePixel;
+} MI_SNR_PlaneInfo_t;
+
+typedef enum
+{
+ E_MI_SNR_ANADEC_SRC_NO_READY = 0,
+ E_MI_SNR_ANADEC_SRC_DISCNT,
+ E_MI_SNR_ANADEC_SRC_PAL,
+ E_MI_SNR_ANADEC_SRC_NTSC,
+ E_MI_SNR_ANADEC_SRC_HD_25P,
+ E_MI_SNR_ANADEC_SRC_HD_30P,
+ E_MI_SNR_ANADEC_SRC_HD_50P,
+ E_MI_SNR_ANADEC_SRC_HD_60P,
+ E_MI_SNR_ANADEC_SRC_FHD_25P,
+ E_MI_SNR_ANADEC_SRC_FHD_30P,
+ E_MI_SNR_ANADEC_SRC_NUM
+} MI_SNR_Anadec_SrcType_e;
+
+typedef struct MI_SNR_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_SNR_InitParam_t;
+
+#pragma pack(pop)
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_shadow.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_shadow.h
new file mode 100644
index 00000000..16d9186f
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_shadow.h
@@ -0,0 +1,82 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_SHADOW_H_
+#define _MI_SHADOW_H_
+#include "mi_shadow_datatype.h"
+
+#define SHADOW_MAJOR_VERSION 2
+#define SHADOW_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define SHADOW_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_shadow_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_shadow_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_shadow_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_SHADOW_API_VERSION SHADOW_VERSION_STR(SHADOW_MAJOR_VERSION,SHADOW_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_SHADOW_RegisterDev(
+ MI_SHADOW_RegisterDevParams_t *pstDevParams,
+ MI_SHADOW_HANDLE *phShadow);
+MI_S32 MI_SHADOW_UnRegisterDev(MI_SHADOW_HANDLE hShadow);
+MI_S32 MI_SHADOW_GetOutputPortBuf(
+ MI_SHADOW_HANDLE hShadow,
+ MI_U32 u32ChnId,
+ MI_U32 u32PortId,
+ MI_SYS_BufConf_t *pstBufConfig,
+
+ MI_BOOL *pbBlockedByRateCtrl,
+ MI_SYS_BufInfo_t *pstBufInfo,
+ MI_SYS_BUF_HANDLE *phBufHandle);
+MI_S32 MI_SHADOW_GetInputPortBuf(
+ MI_SHADOW_HANDLE hShadow,
+ MI_U32 u32ChnId,
+ MI_U32 u32PortId,
+
+ MI_SYS_BufInfo_t *pstBufInfo,
+ MI_SYS_BUF_HANDLE *phBufHandle);
+MI_S32 MI_SHADOW_FinishBuf(MI_SHADOW_HANDLE hShadow, MI_SYS_BUF_HANDLE hBufHandle);
+MI_S32 MI_SHADOW_RewindBuf(MI_SHADOW_HANDLE hShadow, MI_SYS_BUF_HANDLE hBufHandle);
+MI_S32 MI_SHADOW_WaitOnInputTaskAvailable(MI_SHADOW_HANDLE hShadow ,MI_S32 u32TimeOutMs);
+
+MI_S32 MI_SHADOW_EnableChannel(MI_SHADOW_HANDLE hShadow, MI_U32 u32ChnId);
+MI_S32 MI_SHADOW_DisableChannel(MI_SHADOW_HANDLE hShadow, MI_U32 u32ChnId);
+MI_S32 MI_SHADOW_EnableOutputPort(MI_SHADOW_HANDLE hShadow, MI_U32 u32ChnId, MI_U32 u32PortId);
+MI_S32 MI_SHADOW_DisableOutputPort(MI_SHADOW_HANDLE hShadow, MI_U32 u32ChnId, MI_U32 u32PortId);
+MI_S32 MI_SHADOW_EnableInputPort(MI_SHADOW_HANDLE hShadow, MI_U32 u32ChnId, MI_U32 u32PortId);
+MI_S32 MI_SHADOW_DisableInputPort(MI_SHADOW_HANDLE hShadow, MI_U32 u32ChnId, MI_U32 u32PortId);
+MI_S32 MI_SHADOW_InitDev(MI_SHADOW_InitParam_t *pstInitParam);
+MI_S32 MI_SHADOW_DeInitDev(void);
+
+
+MI_S32 MI_SHADOW_SetInputPortBufExtConf(
+ MI_SHADOW_HANDLE hShadow,
+ MI_U32 u32ChnId,
+ MI_U32 u32PortId,
+ MI_SYS_FrameBufExtraConfig_t * pstBufExtraConf
+ );
+MI_S32 MI_SHADOW_SetOutputPortBufExtConf(
+ MI_SHADOW_HANDLE hShadow,
+ MI_U32 u32ChnId,
+ MI_U32 u32PortId,
+ MI_SYS_FrameBufExtraConfig_t * pstBufExtraConf
+ );
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif ///_MI_SHADOW_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_shadow_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_shadow_datatype.h
new file mode 100644
index 00000000..a5e327df
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_shadow_datatype.h
@@ -0,0 +1,97 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_SHADOW_DATATYPE_H_
+#define _MI_SHADOW_DATATYPE_H_
+
+#include "mi_sys_datatype.h"
+
+#define MI_SHADOW_DUMP_BUFFER_SIZE (12 * 1024)
+
+typedef enum
+{
+ MI_SHADOW_CALLBACK_EVENT_ONBINDINPUTPORT,
+ MI_SHADOW_CALLBACK_EVENT_ONBINDOUTPUTPORT,
+ MI_SHADOW_CALLBACK_EVENT_ONUNBINDINPUTPORT,
+ MI_SHADOW_CALLBACK_EVENT_ONUNBINDOUTPUTPORT,
+ MI_SHADOW_CALLBACK_EVENT_BINDMAX,
+
+ MI_SHADOW_CALLBACK_EVENT_ONDumpDEVATTR,
+ MI_SHADOW_CALLBACK_EVENT_ONDumpCHANNELATTR,
+ MI_SHADOW_CALLBACK_EVENT_ONDumpINPUTPORTATTR,
+ MI_SHADOW_CALLBACK_EVENT_ONDumpOUTPUTPORTATTR,
+ MI_SHADOW_CALLBACK_EVENT_ONHELP,
+ MI_SHADOW_CALLBACK_EVENT_DUMPMAX,
+
+ MI_SHADOW_CALLBACK_EVENT_CMDDEBUGLEVEL,
+ MI_SHADOW_CALLBACK_EVENT_CMDCHECKPOINT,
+ MI_SHADOW_CALLBACK_EVENT_CMDSELFCHECKING,
+ MI_SHADOW_CALLBACK_EVENT_CMDWORKMODEENABLE,
+ MI_SHADOW_CALLBACK_EVENT_CMDCHNENABLE,
+ MI_SHADOW_CALLBACK_EVENT_CMDDUMPALLENABLE,
+ MI_SHADOW_CALLBACK_EVENT_CMDDUMPIMAGE,
+ MI_SHADOW_CALLBACK_EVENT_CMDMAX,
+
+ MI_SHADOW_CALLBACK_EVENT_EXIT,
+ MI_SHADOW_CALLBACK_EVENT_TIMEOUT,
+ MI_SHADOW_CALLBACK_EVENT_MAX,
+} MI_SHADOW_CALLBACK_EVENT_e;
+
+typedef struct MI_SHADOW_ModuleDevInfo_s
+{
+ MI_ModuleId_e eModuleId;
+ MI_U32 u32DevId;
+ MI_U32 u32InputPortNum;
+ MI_U32 u32OutputPortNum;
+ MI_U32 u32DevChnNum;
+}MI_SHADOW_ModuleDevInfo_t;
+
+#define MI_SHADOW_HANDLE MI_HANDLE
+typedef MI_S32 (* MI_SHADOW_Callback)(MI_SYS_ChnPort_t *pstChnCurryPort, MI_SYS_ChnPort_t *pstChnPeerPort, void *pUsrData);
+typedef MI_S32 (* MI_SHADOW_DumpCallback)(MI_SHADOW_HANDLE handle, MI_U32 u32DevId, void *pUsrData);
+typedef MI_S32 (* MI_SHADOW_CmdCallback)(MI_SHADOW_HANDLE handle, MI_U32 u32DevId, MI_U8 argc, MI_S8 **argv, void *pUsrData);
+
+typedef struct MI_SHADOW_RegisterDevParams_s
+{
+ MI_SHADOW_ModuleDevInfo_t stModDevInfo;
+
+ MI_SHADOW_Callback OnBindInputPort;
+ MI_SHADOW_Callback OnBindOutputPort;
+ MI_SHADOW_Callback OnUnBindInputPort;
+ MI_SHADOW_Callback OnUnBindOutputPort;
+
+ MI_SHADOW_DumpCallback OnDumpDevAttr;
+ MI_SHADOW_DumpCallback OnDumpChannelAttr;
+ MI_SHADOW_DumpCallback OnDumpInputPortAttr;
+ MI_SHADOW_DumpCallback OnDumpOutPortAttr;
+ MI_SHADOW_DumpCallback OnHelp;
+
+ MI_SHADOW_CmdCallback CmdDebugLevel;
+ MI_SHADOW_CmdCallback CmdCheckPoint;
+ MI_SHADOW_CmdCallback CmdSelfChecking;
+ MI_SHADOW_CmdCallback CmdWorkModeEnable;
+ MI_SHADOW_CmdCallback CmdChnEnable;
+ MI_SHADOW_CmdCallback CmdDumpAllEnable;
+ MI_SHADOW_CmdCallback CmdDumpImage;
+
+ void *pUsrData;
+ MI_U8 *pDumpBuf;
+} MI_SHADOW_RegisterDevParams_t;
+
+typedef struct MI_SHADOW_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_SHADOW_InitParam_t;
+
+#endif ///_MI_SHADOW_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sys.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sys.h
new file mode 100644
index 00000000..5d39d025
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sys.h
@@ -0,0 +1,180 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_SYS_H_
+#define _MI_SYS_H_
+
+#include "mi_common.h"
+#include "mi_sys_datatype.h"
+
+#define SYS_MAJOR_VERSION 2
+#define SYS_SUB_VERSION 18.1
+#define MACRO_TO_STR(macro) #macro
+#define SYS_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_sys_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_sys_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_sys_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_SYS_API_VERSION SYS_VERSION_STR(SYS_MAJOR_VERSION,SYS_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_SYS_Init(void);
+
+MI_S32 MI_SYS_Exit (void);
+
+MI_S32 MI_SYS_BindChnPort(MI_SYS_ChnPort_t *pstSrcChnPort, MI_SYS_ChnPort_t *pstDstChnPort , MI_U32 u32SrcFrmrate, MI_U32 u32DstFrmrate);
+
+MI_S32 MI_SYS_BindChnPort2(MI_SYS_ChnPort_t *pstSrcChnPort, MI_SYS_ChnPort_t *pstDstChnPort,MI_U32 u32SrcFrmrate, MI_U32 u32DstFrmrate, MI_SYS_BindType_e eBindType, MI_U32 u32BindParam);
+
+MI_S32 MI_SYS_UnBindChnPort(MI_SYS_ChnPort_t *pstSrcChnPort, MI_SYS_ChnPort_t *pstDstChnPort);
+
+MI_S32 MI_SYS_GetBindbyDest (MI_SYS_ChnPort_t *pstDstChnPort, MI_SYS_ChnPort_t *pstSrcChnPort);
+
+MI_S32 MI_SYS_GetVersion (MI_SYS_Version_t *pstVersion);
+
+MI_S32 MI_SYS_GetCurPts (MI_U64 *pu64Pts);
+
+MI_S32 MI_SYS_InitPtsBase (MI_U64 u64PtsBase);
+
+MI_S32 MI_SYS_SyncPts (MI_U64 u64Pts);
+
+MI_S32 MI_SYS_SetReg (MI_U32 u32RegAddr, MI_U16 u16Value, MI_U16 u16Mask);
+
+MI_S32 MI_SYS_GetReg (MI_U32 u32RegAddr, MI_U16 *pu16Value);
+
+MI_S32 MI_SYS_ReadUuid (MI_U64 *u64Uuid);
+
+MI_S32 MI_SYS_SetChnMMAConf (MI_ModuleId_e eModId, MI_U32 u32DevId, MI_U32 u32ChnId, MI_U8 *pu8MMAHeapName);
+
+MI_S32 MI_SYS_GetChnMMAConf (MI_ModuleId_e eModId, MI_U32 u32DevId, MI_U32 u32ChnId, void *data, MI_U32 u32Length);
+
+MI_S32 MI_SYS_ChnInputPortGetBuf (MI_SYS_ChnPort_t *pstChnPort ,MI_SYS_BufConf_t *pstBufConf, MI_SYS_BufInfo_t *pstBufInfo , MI_SYS_BUF_HANDLE *bufHandle , MI_S32 s32TimeOutMs);
+
+MI_S32 MI_SYS_ChnInputPortPutBuf (MI_SYS_BUF_HANDLE bufHandle ,MI_SYS_BufInfo_t *pstBufInfo , MI_BOOL bDropBuf);
+
+MI_S32 MI_SYS_ChnOutputPortGetBuf (MI_SYS_ChnPort_t *pstChnPort,MI_SYS_BufInfo_t *pstBufInfo, MI_SYS_BUF_HANDLE *bufHandle);
+
+MI_S32 MI_SYS_ChnOutputPortPutBuf (MI_SYS_BUF_HANDLE hBufHandle);
+
+MI_S32 MI_SYS_SetChnOutputPortDepth(MI_SYS_ChnPort_t *pstChnPort , MI_U32 u32UserFrameDepth , MI_U32 u32BufQueueDepth);
+
+MI_S32 MI_SYS_ChnPortInjectBuf (MI_SYS_BUF_HANDLE handle ,MI_SYS_ChnPort_t *pstChnInputPort);
+
+MI_S32 MI_SYS_GetFd(MI_SYS_ChnPort_t *pstChnPort , MI_S32 *s32Fd);
+
+MI_S32 MI_SYS_CloseFd(MI_S32 s32ChnPortFd);
+
+MI_S32 MI_SYS_ConfDevPubPools(MI_ModuleId_e eModule, MI_U32 u32DevId, MI_VB_PoolListConf_t stPoolListConf);
+
+MI_S32 MI_SYS_ReleaseDevPubPools(MI_ModuleId_e eModule, MI_U32 u32DevId);
+
+MI_S32 MI_SYS_ConfGloPubPools(MI_VB_PoolListConf_t stPoolListConf);
+
+MI_S32 MI_SYS_ReleaseGloPubPools(void);
+
+MI_S32 MI_SYS_Set_Vdec_UseVbPool_Flag(MI_U32 u32Value);
+
+MI_S32 MI_SYS_ConfigPrivateMMAPool(MI_SYS_GlobalPrivPoolConfig_t *pstGlobalPrivPoolConf);
+
+MI_S32 MI_SYS_MemsetPa(MI_PHY phyPa, MI_U32 u32Val, MI_U32 u32Lenth);
+
+MI_S32 MI_SYS_MemcpyPa(MI_PHY phyDst, MI_PHY phySrc, MI_U32 u32Lenth);
+
+MI_S32 MI_SYS_BufFillPa(MI_SYS_FrameData_t *pstBuf, MI_U32 u32Val, MI_SYS_WindowRect_t *pstRect);
+
+MI_S32 MI_SYS_BufBlitPa(MI_SYS_FrameData_t *pstDstBuf, MI_SYS_WindowRect_t *pstDstRect, MI_SYS_FrameData_t *pstSrcBuf, MI_SYS_WindowRect_t *pstSrcRect);
+
+MI_S32 MI_SYS_PrivateDevChnHeapAlloc(MI_ModuleId_e eModule, MI_U32 u32Devid, MI_S32 s32ChnId, MI_U8 *pu8BufName, MI_U32 u32blkSize, MI_PHY *pphyAddr, MI_BOOL bTailAlloc);
+
+MI_S32 MI_SYS_PrivateDevChnHeapFree(MI_ModuleId_e eModule, MI_U32 u32Devid, MI_S32 s32ChnId, MI_PHY phyAddr);
+
+MI_S32 MI_SYS_EnableChnOutputPortLowLatency(MI_SYS_ChnPort_t *pstChnPort, MI_BOOL bEnable, MI_U32 u32Param);
+
+MI_S32 MI_SYS_InitDev(MI_SYS_InitParam_t *pstInitParam);
+
+MI_S32 MI_SYS_DeInitDev(void);
+
+MI_S32 MI_SYS_DupBuf(MI_SYS_BUF_HANDLE srcBufHandle , MI_SYS_BUF_HANDLE *pDupTargetBufHandle);
+
+MI_S32 MI_SYS_Va2Pa (void *pVirtualAddress, MI_PHY *pPhyAddr);
+
+/*
+N.B.
+below MMAHeapName can only be NULL or real mma heap name, do not set it with random character string.
+you can get mma heap name xxx from "mma_heap=xxx," of cat /proc/cmdline.
+*/
+MI_S32 MI_SYS_MMA_Alloc(MI_U8 *pstMMAHeapName, MI_U32 u32BlkSize ,MI_PHY *phyAddr);
+
+MI_S32 MI_SYS_MMA_Free(MI_PHY phyAddr);
+MI_S32 MI_SYS_Mmap(MI_U64 phyAddr, MI_U32 u32Size , void **ppVirtualAddress , MI_BOOL bCache);
+
+MI_S32 MI_SYS_Munmap(void *pVirtualAddress, MI_U32 u32Size);
+MI_S32 MI_SYS_FlushInvCache(void *pVirtualAddress, MI_U32 u32Length);
+
+#ifdef __USER__
+#define DEBUG_YUV_USER_API
+#ifdef DEBUG_YUV_USER_API
+typedef FILE* FILE_HANDLE;
+//return value of the following API is not standard file operation return value.
+
+/*
+return :
+FILE_HANDLE type in fact is a pointer,
+NULL:fail
+not NULL:success
+*/
+FILE_HANDLE open_yuv_file(const char *pathname, int open_for_write);
+
+/*
+return value:
+0:success
+-1:fail
+*/
+int read_yuv_file(FILE_HANDLE filehandle, MI_SYS_FrameData_t framedata);
+
+/*
+return value:
+0:success
+-1:fail
+*/
+int write_yuv_file(FILE_HANDLE filehandle, MI_SYS_FrameData_t framedata);
+
+void close_yuv_file(FILE_HANDLE filehandle);
+
+/*
+return value:
+0:success
+-1:fail
+*/
+int reset_yuv_file(FILE_HANDLE filehandle);
+
+/*
+return value:
+0:success
+-1:fail
+*/
+int is_in_yuv_file_end(FILE_HANDLE filehandle);
+#endif
+#else
+/*
+do nothing,kernel space debug API is in mi_sys_internal.h/mi_sys_internal.c
+*/
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif ///_MI_SYS_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sys_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sys_datatype.h
new file mode 100644
index 00000000..0777628d
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_sys_datatype.h
@@ -0,0 +1,467 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_SYS_DATATYPE_H_
+#define _MI_SYS_DATATYPE_H_
+
+#include "mi_common.h"
+#define MI_SYS_MAX_INPUT_PORT_CNT (16)
+#define MI_SYS_MAX_OUTPUT_PORT_CNT (5)
+#define MI_SYS_MAX_DEV_CHN_CNT (48)
+#define MI_SYS_INVLAID_SEQUENCE_NUM ((MI_U32)-1)
+
+
+//ensure that sizeof(MI_VB_PoolListConf_t) is less that 4096 !!!
+#define MI_MAX_MMA_HEAP_LENGTH (32)
+#define MI_VB_POOL_LIST_MAX_CNT (8)
+
+#define MI_SYS_INVALID_PTS (0xffffffffffffffffULL)
+
+#define MI_VB_BLK_HANDLE_INVALID (-1)
+#define MI_VB_POOL_HANDLE_INVALID (-1)
+
+/* UserHandler ExFlags start. */
+#define MI_SYS_MAP_VA 0x80000000
+#define MI_SYS_MAP_CPU_READ 0X20000000
+#define MI_SYS_MAP_CPU_WRITE 0X10000000
+
+#define MI_SYS_HANDLE_ADD_TO_LIST 0X08000000
+#define MI_SYS_HANDLE_DEL_FROM_LIST 0X04000000
+/* UserHandler ExFlags end. */
+
+
+#define MI_SYS_INVLAID_SEQUENCE_NUM ((MI_U32)-1)
+
+#define MI_SYS_SUCCESS MI_SUCCESS// do not use MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, MI_SUCCESS) !!!!
+
+/* SYS Module ErrorCode */
+#define MI_ERR_SYS_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+#define MI_ERR_SYS_INVALID_CHNID MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID)
+#define MI_ERR_SYS_ILLEGAL_PARAM MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+#define MI_ERR_SYS_EXIST MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_EXIST)
+#define MI_ERR_SYS_UNEXIST MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_UNEXIST)
+#define MI_ERR_SYS_NULL_PTR MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR)
+#define MI_ERR_SYS_NOT_CONFIG MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG)
+#define MI_ERR_SYS_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT)
+#define MI_ERR_SYS_NOT_PERM MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM)
+#define MI_ERR_SYS_NOMEM MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM)
+#define MI_ERR_SYS_NOBUF MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOBUF)
+#define MI_ERR_SYS_BUF_EMPTY MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY)
+#define MI_ERR_SYS_BUF_FULL MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL)
+#define MI_ERR_SYS_SYS_NOTREADY MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY)
+#define MI_ERR_SYS_BADADDR MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BADADDR)
+#define MI_ERR_SYS_BUSY MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY)
+#define MI_ERR_SYS_CHN_NOT_STARTED MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NOT_STARTED)
+#define MI_ERR_SYS_CHN_NOT_STOPED MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NOT_STOPED)
+#define MI_ERR_SYS_NOT_INIT MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_INIT)
+#define MI_ERR_SYS_INITED MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INITED)
+#define MI_ERR_SYS_NOT_ENABLE MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_ENABLE)
+#define MI_ERR_SYS_NOT_DISABLE MI_DEF_ERR(E_MI_MODULE_ID_SYS,E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_DISABLE)
+#define MI_ERR_SYS_TIMEOUT MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_TIMEOUT)
+#define MI_ERR_SYS_DEV_NOT_STARTED MI_DEF_ERR(E_MI_MODULE_ID_SYS,E_MI_ERR_LEVEL_ERROR, E_MI_ERR_DEV_NOT_STARTED)
+#define MI_ERR_SYS_DEV_NOT_STOPED MI_DEF_ERR(E_MI_MODULE_ID_SYS,E_MI_ERR_LEVEL_ERROR, E_MI_ERR_DEV_NOT_STOPED)
+#define MI_ERR_SYS_CHN_NO_CONTENT MI_DEF_ERR(E_MI_MODULE_ID_SYS,E_MI_ERR_LEVEL_ERROR, E_MI_ERR_CHN_NO_CONTENT)
+#define MI_ERR_SYS_NOVASAPCE MI_DEF_ERR(E_MI_MODULE_ID_SYS,E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOVASPACE)
+#define MI_ERR_SYS_NOITEM MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOITEM)
+#define MI_ERR_SYS_FAILED MI_DEF_ERR(E_MI_MODULE_ID_SYS, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED)
+
+typedef MI_S32 MI_VB_POOL_HANDLE;
+typedef MI_S32 MI_VB_BLK_HANDLE;
+typedef MI_S32 MI_SYS_BUF_HANDLE;
+
+/*
+****************************************************TODO Refine*****************************************
+*/
+
+#if !defined(TRUE) && !defined(FALSE)
+/// definition for TRUE
+#define TRUE 1
+/// definition for FALSE
+#define FALSE 0
+#endif
+
+typedef struct MI_VB_BufBlkInfo_s
+{
+ MI_VB_POOL_HANDLE poolHandle;
+ MI_U32 u32OffsetInVBPool;
+ MI_U32 u32BlkSize;
+ MI_PHY phySicalAddr;
+ void *pVirtualAddress;
+} MI_VB_BufBlkInfo_t;
+
+typedef struct MI_VB_PoolConf_s
+{
+ MI_U32 u32BlkSize;
+ MI_U32 u32BlkCnt;
+ MI_U8 u8MMAHeapName[MI_MAX_MMA_HEAP_LENGTH];
+}MI_VB_PoolConf_t;
+
+typedef struct MI_VB_PoolListConf_s
+{
+ MI_U32 u32PoolListCnt;
+ MI_VB_PoolConf_t stPoolConf[MI_VB_POOL_LIST_MAX_CNT];
+} MI_VB_PoolListConf_t;
+
+typedef enum
+{
+ E_MI_SYS_DATA_PRECISION_8BPP,
+ E_MI_SYS_DATA_PRECISION_10BPP,
+ E_MI_SYS_DATA_PRECISION_12BPP,
+ E_MI_SYS_DATA_PRECISION_14BPP,
+ E_MI_SYS_DATA_PRECISION_16BPP,
+ E_MI_SYS_DATA_PRECISION_MAX,
+} MI_SYS_DataPrecision_e;
+
+typedef enum
+{
+ E_MI_SYS_PIXEL_BAYERID_RG,
+ E_MI_SYS_PIXEL_BAYERID_GR,
+ E_MI_SYS_PIXEL_BAYERID_BG,
+ E_MI_SYS_PIXEL_BAYERID_GB,
+ E_MI_SYS_PIXEL_RGBIR_R0,
+ E_MI_SYS_PIXEL_RGBIR_G0,
+ E_MI_SYS_PIXEL_RGBIR_B0,
+ E_MI_SYS_PIXEL_RGBIR_G1,
+ E_MI_SYS_PIXEL_RGBIR_G2,
+ E_MI_SYS_PIXEL_RGBIR_I0,
+ E_MI_SYS_PIXEL_RGBIR_G3,
+ E_MI_SYS_PIXEL_RGBIR_I1,
+ E_MI_SYS_PIXEL_BAYERID_MAX,
+}MI_SYS_BayerId_e;
+
+typedef enum
+{
+ E_MI_SYS_PIXEL_FRAME_YUV422_YUYV = 0,
+ E_MI_SYS_PIXEL_FRAME_ARGB8888,
+ E_MI_SYS_PIXEL_FRAME_ABGR8888,
+ E_MI_SYS_PIXEL_FRAME_BGRA8888,
+
+ E_MI_SYS_PIXEL_FRAME_RGB565,
+ E_MI_SYS_PIXEL_FRAME_ARGB1555,
+ E_MI_SYS_PIXEL_FRAME_ARGB4444,
+ E_MI_SYS_PIXEL_FRAME_I2,
+ E_MI_SYS_PIXEL_FRAME_I4,
+ E_MI_SYS_PIXEL_FRAME_I8,
+
+ E_MI_SYS_PIXEL_FRAME_YUV_SEMIPLANAR_422,
+ E_MI_SYS_PIXEL_FRAME_YUV_SEMIPLANAR_420,
+ E_MI_SYS_PIXEL_FRAME_YUV_SEMIPLANAR_420_NV21,
+ E_MI_SYS_PIXEL_FRAME_YUV_MST_420,
+ E_MI_SYS_PIXEL_FRAME_YUV422_UYVY,
+ E_MI_SYS_PIXEL_FRAME_YUV422_YVYU,
+ E_MI_SYS_PIXEL_FRAME_YUV422_VYUY,
+
+ //vdec sigmastar private video format
+ E_MI_SYS_PIXEL_FRAME_YC420_MSTTILE1_H264,
+ E_MI_SYS_PIXEL_FRAME_YC420_MSTTILE2_H265,
+ E_MI_SYS_PIXEL_FRAME_YC420_MSTTILE3_H265,
+
+ E_MI_SYS_PIXEL_FRAME_RGB_BAYER_BASE,
+ E_MI_SYS_PIXEL_FRAME_RGB_BAYER_NUM = E_MI_SYS_PIXEL_FRAME_RGB_BAYER_BASE + E_MI_SYS_DATA_PRECISION_MAX*E_MI_SYS_PIXEL_BAYERID_MAX-1,
+
+ E_MI_SYS_PIXEL_FRAME_RGB888,
+ E_MI_SYS_PIXEL_FRAME_BGR888,
+
+ E_MI_SYS_PIXEL_FRAME_FORMAT_MAX,
+} MI_SYS_PixelFormat_e;
+
+#define RGB_BAYER_PIXEL(BitMode, PixelID) (E_MI_SYS_PIXEL_FRAME_RGB_BAYER_BASE+ BitMode*E_MI_SYS_PIXEL_BAYERID_MAX+ PixelID)
+
+typedef enum
+{
+ E_MI_SYS_COMPRESS_MODE_NONE,//no compress
+ E_MI_SYS_COMPRESS_MODE_SEG,//compress unit is 256 bytes as a segment
+ E_MI_SYS_COMPRESS_MODE_LINE,//compress unit is the whole line
+ E_MI_SYS_COMPRESS_MODE_FRAME,//compress unit is the whole frame
+ E_MI_SYS_COMPRESS_MODE_BUTT, //number
+}MI_SYS_CompressMode_e;
+
+typedef enum
+{
+ E_MI_SYS_FRAME_SCAN_MODE_PROGRESSIVE = 0x0, // progessive.
+ E_MI_SYS_FRAME_SCAN_MODE_INTERLACE = 0x1, // interlace.
+ E_MI_SYS_FRAME_SCAN_MODE_MAX,
+} MI_SYS_FrameScanMode_e;
+
+typedef enum
+{
+ E_MI_SYS_FRAME_TILE_MODE_NONE = 0,
+ E_MI_SYS_FRAME_TILE_MODE_16x16, // tile mode 16x16
+ E_MI_SYS_FRAME_TILE_MODE_16x32, // tile mode 16x32
+ E_MI_SYS_FRAME_TILE_MODE_32x16, // tile mode 32x16
+ E_MI_SYS_FRAME_TILE_MODE_32x32, // tile mode 32x32
+ E_MI_SYS_FRAME_TILE_MODE_MAX
+} MI_SYS_FrameTileMode_e;
+
+typedef enum
+{
+ E_MI_SYS_FIELDTYPE_NONE, //< no field.
+ E_MI_SYS_FIELDTYPE_TOP, //< Top field only.
+ E_MI_SYS_FIELDTYPE_BOTTOM, //< Bottom field only.
+ E_MI_SYS_FIELDTYPE_BOTH, //< Both fields.
+ E_MI_SYS_FIELDTYPE_NUM
+} MI_SYS_FieldType_e;
+
+typedef enum
+{
+ E_MI_SYS_BUFDATA_RAW = 0,
+ E_MI_SYS_BUFDATA_FRAME,
+ E_MI_SYS_BUFDATA_META,
+} MI_SYS_BufDataType_e;
+
+typedef enum
+{
+ E_MI_SYS_ROTATE_NONE, //Rotate 0 degrees
+ E_MI_SYS_ROTATE_90, //Rotate 90 degrees
+ E_MI_SYS_ROTATE_180, //Rotate 180 degrees
+ E_MI_SYS_ROTATE_270, //Rotate 270 degrees
+ E_MI_SYS_ROTATE_NUM,
+}MI_SYS_Rotate_e;
+
+typedef enum
+{
+ E_MI_SYS_BIND_TYPE_FRAME_BASE = 0x00000001,
+ E_MI_SYS_BIND_TYPE_SW_LOW_LATENCY = 0x00000002,
+ E_MI_SYS_BIND_TYPE_REALTIME = 0x00000004,
+ E_MI_SYS_BIND_TYPE_HW_AUTOSYNC = 0x00000008,
+ E_MI_SYS_BIND_TYPE_HW_RING = 0x00000010
+}MI_SYS_BindType_e;
+
+typedef enum
+{
+ E_MI_SYS_VPE_TO_VENC_PRIVATE_RING_POOL = 0,
+ E_MI_SYS_PER_CHN_PRIVATE_POOL=1,
+ E_MI_SYS_PER_DEV_PRIVATE_POOL=2,
+ E_MI_SYS_PER_CHN_PORT_OUTPUT_POOL=3,
+}MI_SYS_InsidePrivatePoolType_e;
+
+typedef enum
+{
+ E_MI_SYS_FRAME_ISP_INFO_TYPE_NONE,
+ E_MI_SYS_FRAME_ISP_INFO_TYPE_GLOBAL_GRADIENT
+}MI_SYS_FrameIspInfoType_e;
+
+
+typedef struct MI_SYS_ChnPort_s
+{
+ MI_ModuleId_e eModId;
+ MI_U32 u32DevId;
+ MI_U32 u32ChnId;
+ MI_U32 u32PortId;
+
+} MI_SYS_ChnPort_t;
+
+typedef struct MI_SYS_WindowRect_s
+{
+ MI_U16 u16X;
+ MI_U16 u16Y;
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+}MI_SYS_WindowRect_t;
+
+typedef struct MI_SYS_WindowSize_s
+{
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+}MI_SYS_WindowSize_t;
+
+typedef struct MI_SYS_RawData_s
+{
+ void* pVirAddr;
+ MI_PHY phyAddr;//notice that this is miu bus addr,not cpu bus addr.
+ MI_U32 u32BufSize;
+
+ MI_U32 u32ContentSize;
+ MI_BOOL bEndOfFrame;
+ MI_U64 u64SeqNum;
+} MI_SYS_RawData_t;
+
+typedef struct MI_SYS_MetaData_s
+{
+ void* pVirAddr;
+ MI_PHY phyAddr;//notice that this is miu bus addr,not cpu bus addr.
+
+ MI_U32 u32Size;
+ MI_U32 u32ExtraData; /*driver special flag*/
+ MI_ModuleId_e eDataFromModule;
+} MI_SYS_MetaData_t;
+
+typedef enum
+{
+ REALTIME_FRAME_DATA,
+ RINGBUF_FRAME_DATA,
+ NORMAL_FRAME_DATA,
+}MI_SYS_FrameData_PhySignalType;
+
+#define MI_SYS_REALTIME_MAGIC_PADDR ((MI_PHY)0x46414B45) //"FAKE"
+#define MI_SYS_REALTIME_MAGIC_VADDR ((void*)0x46414B45) //"FAKE"
+#define MI_SYS_REALTIME_MAGIC_PITCH ((MI_U32)0x46414B45) //"FAKE"
+
+typedef struct MI_SYS_FrameIspInfo_s
+{
+ MI_SYS_FrameIspInfoType_e eType;
+ union
+ {
+ MI_U32 u32GlobalGradient;
+ }uIspInfo;
+}MI_SYS_FrameIspInfo_t;
+
+//N.B. in MI_SYS_FrameData_t should never support u32Size,
+//for other values are enough,and not support u32Size is general standard method.
+typedef struct MI_SYS_FrameData_s
+{
+ MI_SYS_FrameTileMode_e eTileMode;
+ MI_SYS_PixelFormat_e ePixelFormat;
+ MI_SYS_CompressMode_e eCompressMode;
+ MI_SYS_FrameScanMode_e eFrameScanMode;
+ MI_SYS_FieldType_e eFieldType;
+ MI_SYS_FrameData_PhySignalType ePhylayoutType;
+
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+//in case ePhylayoutType equal to REALTIME_FRAME_DATA, pVirAddr would be MI_SYS_REALTIME_MAGIC_PADDR and phyAddr would be MI_SYS_REALTIME_MAGIC_VADDR
+
+ void* pVirAddr[3];
+ MI_PHY phyAddr[3];//notice that this is miu bus addr,not cpu bus addr.
+ MI_U32 u32Stride[3];
+ MI_U32 u32BufSize;//total size that allocated for this buffer,include consider alignment.
+
+ MI_U16 u16RingBufStartLine;//Valid in case RINGBUF_FRAME_DATA, u16RingBufStartLine must be LGE than 0 and less than u16Height
+ MI_U16 u16RingBufRealTotalHeight;///Valid in case RINGBUF_FRAME_DATA, u16RingBufStartLine must be LGE than u16Height
+
+ MI_SYS_FrameIspInfo_t stFrameIspInfo;//isp info of each frame
+ MI_SYS_WindowRect_t stContentCropWindow;
+} MI_SYS_FrameData_t;
+
+typedef struct MI_SYS_BufInfo_s
+{
+ MI_U64 u64Pts;
+ MI_U64 u64SidebandMsg;
+ MI_SYS_BufDataType_e eBufType;
+ MI_BOOL bEndOfStream;
+ MI_BOOL bUsrBuf;
+ MI_U32 u32SequenceNumber;
+ MI_BOOL bDrop;
+ union
+ {
+ MI_SYS_FrameData_t stFrameData;
+ MI_SYS_RawData_t stRawData;
+ MI_SYS_MetaData_t stMetaData;
+ };
+} MI_SYS_BufInfo_t;
+
+typedef struct MI_SYS_FrameBufExtraConfig_s
+{
+ //Buf alignment requirement in horizontal
+ MI_U16 u16BufHAlignment;
+ //Buf alignment requirement in vertical
+ MI_U16 u16BufVAlignment;
+ //Buf alignment requirement in chroma
+ MI_U16 u16BufChromaAlignment;
+ //Clear padding flag
+ MI_BOOL bClearPadding;
+}MI_SYS_FrameBufExtraConfig_t;
+
+typedef struct MI_SYS_BufFrameConfig_s
+{
+ MI_U16 u16Width;
+ MI_U16 u16Height;
+ MI_SYS_FrameScanMode_e eFrameScanMode;//
+ MI_SYS_PixelFormat_e eFormat;
+ MI_SYS_FrameBufExtraConfig_t stFrameBufExtraConf;//set by MI_SYS internal
+ //MI_U32 u32Size;//this value will be calculated through others values in this struct
+}MI_SYS_BufFrameConfig_t;
+
+typedef struct MI_SYS_BufRawConfig_s
+{
+ MI_U32 u32Size;
+}MI_SYS_BufRawConfig_t;
+
+typedef struct MI_SYS_MetaDataConfig_s
+{
+ MI_U32 u32Size;
+}MI_SYS_MetaDataConfig_t;
+
+typedef struct MI_SYS_BufConf_s
+{
+ MI_SYS_BufDataType_e eBufType;
+ MI_U32 u32Flags; //0 or MI_SYS_MAP_VA
+ MI_U64 u64TargetPts;
+ union
+ {
+ MI_SYS_BufFrameConfig_t stFrameCfg;
+ MI_SYS_BufRawConfig_t stRawCfg;
+ MI_SYS_MetaDataConfig_t stMetaCfg;
+ };
+}MI_SYS_BufConf_t;
+
+typedef struct MI_SYS_Version_s
+{
+ MI_U8 u8Version[128];
+}MI_SYS_Version_t;
+
+
+typedef struct MI_PerChnPrivHeapConf_s
+{
+ MI_ModuleId_e eModule;
+ MI_U32 u32Devid;
+ MI_U32 u32Channel;
+ MI_U8 u8MMAHeapName[MI_MAX_MMA_HEAP_LENGTH];
+ MI_U32 u32PrivateHeapSize;
+}MI_SYS_PerChnPrivHeapConf_t;
+
+typedef struct MI_PerDevPrivHeapConf_s
+{
+ MI_ModuleId_e eModule;
+ MI_U32 u32Devid;
+ MI_U32 u32Reserve;
+ MI_U8 u8MMAHeapName[MI_MAX_MMA_HEAP_LENGTH];
+ MI_U32 u32PrivateHeapSize;
+}MI_SYS_PerDevPrivHeapConf_t;
+
+typedef struct MI_SYS_PerVpe2VencRingPoolConf_s
+{
+ MI_U32 u32VencInputRingPoolStaticSize;
+ MI_U8 u8MMAHeapName[MI_MAX_MMA_HEAP_LENGTH];
+}MI_SYS_PerVpe2VencRingPoolConf_t;
+
+typedef struct MI_SYS_PerChnPortOutputPool_s
+{
+ MI_ModuleId_e eModule;
+ MI_U32 u32Devid;
+ MI_U32 u32Channel;
+ MI_U32 u32Port;
+ MI_U8 u8MMAHeapName[MI_MAX_MMA_HEAP_LENGTH];
+ MI_U32 u32PrivateHeapSize;
+}MI_SYS_PerChnPortOutputPool_t;
+
+typedef struct MI_SYS_GlobalPrivPoolConfig_s
+{
+ MI_SYS_InsidePrivatePoolType_e eConfigType;
+ MI_BOOL bCreate;
+ union
+ {
+ MI_SYS_PerChnPrivHeapConf_t stPreChnPrivPoolConfig;
+ MI_SYS_PerDevPrivHeapConf_t stPreDevPrivPoolConfig;
+ MI_SYS_PerVpe2VencRingPoolConf_t stPreVpe2VencRingPrivPoolConfig;
+ MI_SYS_PerChnPortOutputPool_t stPreChnPortOutputPrivPool;
+ }uConfig;
+}MI_SYS_GlobalPrivPoolConfig_t;
+
+typedef struct MI_SYS_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_SYS_InitParam_t;
+
+#endif ///_MI_SYS_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdec.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdec.h
new file mode 100644
index 00000000..a5783808
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdec.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+
+#ifndef _MI_VDEC_H_
+#define _MI_VDEC_H_
+
+#define MI_VDEC_GET_ESBUFFER_DIRECT
+
+#include "mi_vdec_datatype.h"
+
+#define VDEC_MAJOR_VERSION 2
+#define VDEC_SUB_VERSION 7
+#define MACRO_TO_STR(macro) #macro
+#define VDEC_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_vdec_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_vdec_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_vdec_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_VDEC_API_VERSION VDEC_VERSION_STR(VDEC_MAJOR_VERSION,VDEC_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_VDEC_InitDev(MI_VDEC_InitParam_t *pstVdecInitParam);
+MI_S32 MI_VDEC_DeInitDev(void);
+MI_S32 MI_VDEC_CreateChn(MI_VDEC_CHN VdecChn, MI_VDEC_ChnAttr_t *pstChnAttr);
+MI_S32 MI_VDEC_DestroyChn(MI_VDEC_CHN VdecChn);
+MI_S32 MI_VDEC_GetChnAttr(MI_VDEC_CHN VdecChn, MI_VDEC_ChnAttr_t *pstChnAttr);
+MI_S32 MI_VDEC_StartChn(MI_VDEC_CHN VdecChn);
+MI_S32 MI_VDEC_StopChn(MI_VDEC_CHN VdecChn);
+MI_S32 MI_VDEC_GetChnStat(MI_VDEC_CHN VdecChn, MI_VDEC_ChnStat_t *pstChnStat);
+MI_S32 MI_VDEC_FlushChn(MI_VDEC_CHN VdecChn);
+MI_S32 MI_VDEC_ResetChn(MI_VDEC_CHN VdecChn);
+MI_S32 MI_VDEC_SetChnParam(MI_VDEC_CHN VdecChn, MI_VDEC_ChnParam_t *pstChnParam);
+MI_S32 MI_VDEC_GetChnParam(MI_VDEC_CHN VdecChn, MI_VDEC_ChnParam_t *pstChnParam);
+MI_S32 MI_VDEC_SendStream(MI_VDEC_CHN VdecChn, MI_VDEC_VideoStream_t *pstVideoStream, MI_S32 s32MilliSec);
+MI_S32 MI_VDEC_GetUserData(MI_VDEC_CHN VdecChn, MI_VDEC_UserData_t *pstUserData, MI_S32 s32MilliSec);
+MI_S32 MI_VDEC_ReleaseUserData(MI_VDEC_CHN VdecChn, MI_VDEC_UserData_t *pstUserData);
+MI_S32 MI_VDEC_SetDisplayMode(MI_VDEC_CHN VdecChn, MI_VDEC_DisplayMode_e eDisplayMode);
+MI_S32 MI_VDEC_GetDisplayMode(MI_VDEC_CHN VdecChn, MI_VDEC_DisplayMode_e *peDisplayMode);
+MI_S32 MI_VDEC_SetOutputPortAttr(MI_VDEC_CHN VdecChn, MI_VDEC_OutputPortAttr_t *pstOutputPortAttr);
+MI_S32 MI_VDEC_GetOutputPortAttr(MI_VDEC_CHN VdecChn, MI_VDEC_OutputPortAttr_t *pstOutputPortAttr);
+MI_S32 MI_VDEC_SetOutputPortLayoutMode(MI_VDEC_OutbufLayoutMode_e eBufTileMode);
+MI_S32 MI_VDEC_GetOutputPortLayoutMode(MI_VDEC_OutbufLayoutMode_e *peBufTileMode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VDEC_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdec_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdec_datatype.h
new file mode 100644
index 00000000..c9bb4630
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdec_datatype.h
@@ -0,0 +1,242 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+
+#ifndef _MI_VDEC_DATATYPE_H_
+#define _MI_VDEC_DATATYPE_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_common.h"
+
+#define MI_VDEC_CHN MI_U32
+
+#define MI_DEF_VDEC_ERR(err) MI_DEF_ERR(E_MI_MODULE_ID_VDEC, E_MI_ERR_LEVEL_ERROR, err)
+
+#define MI_ERR_VDEC_INVALID_DEVID MI_DEF_VDEC_ERR(E_MI_ERR_INVALID_DEVID)
+#define MI_ERR_VDEC_INVALID_CHNID MI_DEF_VDEC_ERR(E_MI_ERR_INVALID_CHNID)
+#define MI_ERR_VDEC_ILLEGAL_PARAM MI_DEF_VDEC_ERR(E_MI_ERR_ILLEGAL_PARAM)
+#define MI_ERR_VDEC_CHN_EXIST MI_DEF_VDEC_ERR(E_MI_ERR_EXIST)
+#define MI_ERR_VDEC_CHN_UNEXIST MI_DEF_VDEC_ERR(E_MI_ERR_UNEXIST)
+#define MI_ERR_VDEC_NULL_PTR MI_DEF_VDEC_ERR(E_MI_ERR_NULL_PTR)
+#define MI_ERR_VDEC_NOT_CONFIG MI_DEF_VDEC_ERR(E_MI_ERR_NOT_CONFIG)
+#define MI_ERR_VDEC_NOT_SUPPORT MI_DEF_VDEC_ERR(E_MI_ERR_NOT_SUPPORT)
+#define MI_ERR_VDEC_NOT_PERM MI_DEF_VDEC_ERR(E_MI_ERR_NOT_PERM)
+#define MI_ERR_VDEC_NOMEM MI_DEF_VDEC_ERR(E_MI_ERR_NOMEM)
+#define MI_ERR_VDEC_NOBUF MI_DEF_VDEC_ERR(E_MI_ERR_NOBUF)
+#define MI_ERR_VDEC_BUF_EMPTY MI_DEF_VDEC_ERR(E_MI_ERR_BUF_EMPTY)
+#define MI_ERR_VDEC_BUF_FULL MI_DEF_VDEC_ERR(E_MI_ERR_BUF_FULL)
+#define MI_ERR_VDEC_SYS_NOTREADY MI_DEF_VDEC_ERR(E_MI_ERR_SYS_NOTREADY)
+#define MI_ERR_VDEC_BADADDR MI_DEF_VDEC_ERR(E_MI_ERR_BADADDR)
+#define MI_ERR_VDEC_BUSY MI_DEF_VDEC_ERR(E_MI_ERR_BUSY)
+#define MI_ERR_VDEC_CHN_NOT_START MI_DEF_VDEC_ERR(E_MI_ERR_CHN_NOT_STARTED)
+#define MI_ERR_VDEC_CHN_NOT_STOP MI_DEF_VDEC_ERR(E_MI_ERR_CHN_NOT_STOPED)
+#define MI_ERR_VDEC_NOT_INIT MI_DEF_VDEC_ERR(E_MI_ERR_NOT_INIT)
+#define MI_ERR_VDEC_INITED MI_DEF_VDEC_ERR(E_MI_ERR_INITED)
+#define MI_ERR_VDEC_NOT_ENABLE MI_DEF_VDEC_ERR(E_MI_ERR_NOT_ENABLE)
+#define MI_ERR_VDEC_NOT_DISABLE MI_DEF_VDEC_ERR(E_MI_ERR_NOT_DISABLE)
+#define MI_ERR_VDEC_SYS_TIMEOUT MI_DEF_VDEC_ERR(E_MI_ERR_SYS_TIMEOUT)
+#define MI_ERR_VDEC_NOT_STARTED MI_DEF_VDEC_ERR(E_MI_ERR_DEV_NOT_STARTED)
+#define MI_ERR_VDEC_NOT_STOPED MI_DEF_VDEC_ERR(E_MI_ERR_DEV_NOT_STOPED)
+#define MI_ERR_VDEC_CHN_NO_CONTENT MI_DEF_VDEC_ERR(E_MI_ERR_CHN_NO_CONTENT)
+#define MI_ERR_VDEC_FAILED MI_DEF_VDEC_ERR(E_MI_ERR_FAILED)
+
+typedef struct MI_VDEC_InitParam_s
+{
+ MI_BOOL bDisableLowLatency;
+} MI_VDEC_InitParam_t;
+
+typedef enum
+{
+ E_MI_VDEC_CODEC_TYPE_H264 = 0x0,
+ E_MI_VDEC_CODEC_TYPE_H265,
+ E_MI_VDEC_CODEC_TYPE_JPEG,
+ E_MI_VDEC_CODEC_TYPE_MAX
+} MI_VDEC_CodecType_e;
+
+typedef enum
+{
+ E_MI_VDEC_JPEG_FORMAT_YCBCR400 = 0x0,
+ E_MI_VDEC_JPEG_FORMAT_YCBCR420,
+ E_MI_VDEC_JPEG_FORMAT_YCBCR422,
+ E_MI_VDEC_JPEG_FORMAT_YCBCR444,
+ E_MI_VDEC_JPEG_FORMAT_MAX
+} MI_VDEC_JpegFormat_e;
+
+typedef enum
+{
+ E_MI_VDEC_VIDEO_MODE_STREAM = 0x0,
+ E_MI_VDEC_VIDEO_MODE_FRAME,
+ E_MI_VDEC_VIDEO_MODE_MAX
+} MI_VDEC_VideoMode_e;
+
+typedef enum
+{
+ E_MI_VDEC_ERR_CODE_UNKNOW = 0x0,
+ E_MI_VDEC_ERR_CODE_ILLEGAL_ACCESS,
+ E_MI_VDEC_ERR_CODE_FRMRATE_UNSUPPORT,
+ E_MI_VDEC_ERR_CODE_DEC_TIMEOUT,
+ E_MI_VDEC_ERR_CODE_OUT_OF_MEMORY,
+ E_MI_VDEC_ERR_CODE_CODEC_TYPE_UNSUPPORT,
+ E_MI_VDEC_ERR_CODE_ERR_SPS_UNSUPPORT,
+ E_MI_VDEC_ERR_CODE_ERR_PPS_UNSUPPORT,
+ E_MI_VDEC_ERR_CODE_REF_LIST_ERR,
+ E_MI_VDEC_ERR_CODE_MAX
+} MI_VDEC_ErrCode_e;
+
+typedef enum
+{
+ E_MI_VDEC_DECODE_MODE_ALL = 0x0,
+ E_MI_VDEC_DECODE_MODE_I,
+ E_MI_VDEC_DECODE_MODE_IP,
+ E_MI_VDEC_DECODE_MODE_MAX
+} MI_VDEC_DecodeMode_e;
+
+typedef enum
+{
+ E_MI_VDEC_OUTPUT_ORDER_DISPLAY = 0x0,
+ E_MI_VDEC_OUTPUT_ORDER_DECODE,
+ E_MI_VDEC_OUTPUT_ORDER_MAX,
+} MI_VDEC_OutputOrder_e;
+
+typedef enum
+{
+ E_MI_VDEC_VIDEO_FORMAT_TILE = 0x0,
+ E_MI_VDEC_VIDEO_FORMAT_REDUCE,
+ E_MI_VDEC_VIDEO_FORMAT_MAX
+} MI_VDEC_VideoFormat_e;
+
+typedef enum
+{
+ E_MI_VDEC_DISPLAY_MODE_PREVIEW = 0x0,
+ E_MI_VDEC_DISPLAY_MODE_PLAYBACK,
+ E_MI_VDEC_DISPLAY_MODE_MAX,
+} MI_VDEC_DisplayMode_e;
+
+typedef enum
+{
+ E_MI_VDEC_TILEMODE_OFF = 0x0,
+ E_MI_VDEC_TILEMODE_ON,
+ E_MI_VDEC_TILEMODE_MAX,
+}MI_VDEC_TileMode_Status_e;
+
+typedef enum
+{
+ E_MI_VDEC_DPB_MODE_NORMAL = 0,
+ E_MI_VDEC_DPB_MODE_INPLACE_ONE_BUF = 1,
+ E_MI_VDEC_DPB_MODE_INPLACE_TWO_BUF = 2,
+ E_MI_VDEC_DPB_MODE_INVALID = 0xFFFFFFFF
+} MI_VDEC_DPB_BufMode_e;
+
+typedef struct MI_VDEC_OutputPortAttr_s
+{
+ MI_U16 u16Width; // Width of target image
+ MI_U16 u16Height; // Height of target image
+}MI_VDEC_OutputPortAttr_t;
+
+typedef enum
+{
+ E_MI_VDEC_OUTBUF_LAYOUT_AUTO = 0x0,
+ E_MI_VDEC_OUTBUF_LAYOUT_LINEAR,
+ E_MI_VDEC_OUTBUF_LAYOUT_TILE,
+ E_MI_VDEC_OUTBUF_LAYOUT_MAX
+} MI_VDEC_OutbufLayoutMode_e;
+
+typedef struct MI_VDEC_JpegAttr_s
+{
+ MI_VDEC_JpegFormat_e eJpegFormat;
+}MI_VDEC_JpegAttr_t;
+
+typedef struct MI_VDEC_VideoAttr_s
+{
+ MI_U32 u32RefFrameNum;
+}MI_VDEC_VideoAttr_t;
+
+
+typedef struct MI_VDEC_ChnAttr_s
+{
+ MI_VDEC_CodecType_e eCodecType;
+ MI_U32 u32BufSize;
+ MI_U32 u32Priority;
+ MI_U32 u32PicWidth;
+ MI_U32 u32PicHeight;
+ MI_VDEC_VideoMode_e eVideoMode;
+ MI_VDEC_DPB_BufMode_e eDpbBufMode;
+ union
+ {
+ MI_VDEC_JpegAttr_t stVdecJpegAttr;
+ MI_VDEC_VideoAttr_t stVdecVideoAttr;
+ };
+} MI_VDEC_ChnAttr_t;
+
+typedef struct MI_VDEC_ChnStat_s
+{
+ MI_VDEC_CodecType_e eCodecType;
+ MI_U32 u32LeftStreamBytes;
+ MI_U32 u32LeftStreamFrames;
+ MI_U32 u32LeftPics;
+ MI_U32 u32RecvStreamFrames;
+ MI_U32 u32DecodeStreamFrames;
+ MI_BOOL bChnStart;
+ MI_VDEC_ErrCode_e eErrCode;
+} MI_VDEC_ChnStat_t;
+
+typedef struct MI_VDEC_ChnParam_s
+{
+ MI_VDEC_DecodeMode_e eDecMode;
+ MI_VDEC_OutputOrder_e eOutputOrder;
+ MI_VDEC_VideoFormat_e eVideoFormat;
+} MI_VDEC_ChnParam_t;
+
+typedef struct MI_VDEC_VideoStream_s
+{
+ MI_U8 *pu8Addr;
+ MI_U32 u32Len;
+ MI_U64 u64PTS;
+ MI_BOOL bEndOfFrame;
+ MI_BOOL bEndOfStream;
+}MI_VDEC_VideoStream_t;
+
+typedef struct MI_VDEC_UserData_s
+{
+ MI_U8 *pu8Addr;
+ MI_U32 u32Len;
+ MI_BOOL bValid;
+} MI_VDEC_UserData_t;
+
+typedef struct MI_VDEC_BufConf_s
+{
+ MI_U64 u64TargetPts;
+ MI_U32 u32BufSize;
+ MI_U8 *pu8UsrAddr;
+} MI_VDEC_BufConf_t;
+
+typedef struct MI_VDEC_BufInfo_s
+{
+ MI_U8 *pu8Addr; // kernl vir addr.
+ MI_PHY phyAddr;
+ MI_U32 u32BufSize;
+ MI_U64 u64Pts;
+ MI_BOOL bEndOfStream;
+
+ MI_BOOL bPictureStart;
+ MI_BOOL bBrokenByUs;
+} MI_VDEC_BufInfo_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VDEC_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdf.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdf.h
new file mode 100644
index 00000000..23fd8d16
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdf.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_VDF_H__
+#define __MI_VDF_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "mi_vdf_datatype.h"
+
+#define VDF_MAJOR_VERSION 2
+#define VDF_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define VDF_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_vdf_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_vdf_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_vdf_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_VDF_API_VERSION VDF_VERSION_STR(VDF_MAJOR_VERSION,VDF_SUB_VERSION)
+
+MI_S32 MI_VDF_Init(void);
+MI_S32 MI_VDF_Uninit(void);
+MI_S32 MI_VDF_CreateChn(MI_VDF_CHANNEL VdfChn, const MI_VDF_ChnAttr_t* pstAttr);
+MI_S32 MI_VDF_DestroyChn(MI_VDF_CHANNEL VdfChn);
+MI_S32 MI_VDF_SetChnAttr(MI_VDF_CHANNEL VdfChn, const MI_VDF_ChnAttr_t* pstAttr);
+MI_S32 MI_VDF_GetChnAttr(MI_VDF_CHANNEL VdfChn, MI_VDF_ChnAttr_t* pstAttr);
+MI_S32 MI_VDF_EnableSubWindow(MI_VDF_CHANNEL VdfChn, MI_U8 u8Col, MI_U8 u8Row, MI_U8 u8Enable);
+MI_S32 MI_VDF_Run(MI_VDF_WorkMode_e enWorkMode);
+MI_S32 MI_VDF_Stop(MI_VDF_WorkMode_e enWorkMode);
+MI_S32 MI_VDF_GetResult(MI_VDF_CHANNEL VdfChn, MI_VDF_Result_t* pstVdfResult, MI_S32 s32MilliSec);
+MI_S32 MI_VDF_PutResult(MI_VDF_CHANNEL VdfChn, MI_VDF_Result_t* pstVdfResult);
+MI_S32 MI_VDF_GetLibVersion(MI_VDF_CHANNEL VdfChn, MI_U32* u32VDFVersion);
+MI_S32 MI_VDF_GetDebugInfo(MI_VDF_CHANNEL VdfChn, MI_VDF_DebugInfo_t *pstDebugInfo);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MI_VDF_H__ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdf_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdf_datatype.h
new file mode 100644
index 00000000..7d5472b4
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdf_datatype.h
@@ -0,0 +1,259 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VDF_DATATYPE_H_
+#define _MI_VDF_DATATYPE_H_
+
+#include "mi_common_datatype.h"
+#include "mi_sys_datatype.h"
+#include "mi_md.h"
+#include "mi_od.h"
+#include "mi_vg.h"
+
+#define VDF_VERSION_MAXLEN 64
+#define MI_VDF_CHANNEL_MAX 8
+#define MI_VDF_MAX_WIDTH 1920
+#define MI_VDF_MAX_HEIGHT 1080
+#define MI_VDF_MIN_WIDTH 320
+#define MI_VDF_MIN_HEIGHT 180
+
+
+#define MI_VDF_MD_RST_BUF_NUM_MAX 8
+#define MI_VDF_OD_RST_BUF_NUM_MAX 16
+#define MI_RET_SUCESS 0
+
+typedef void* MD_HANDLE;
+typedef void* OD_HANDLE;
+typedef MI_S32 MI_VDF_CHANNEL;
+typedef MI_S32 MI_VDF_PORT;
+typedef MI_S32 VDF_RESULT_HANDLE;
+
+typedef struct MI_VDF_Obj_s
+{
+ MI_U16 u16LtX; //Horizontal position of window left-top point
+ MI_U16 u16LtY; //Vertical position of window left-top point
+ MI_U16 u16RbX; //Horizontal position of window right-bottom point
+ MI_U16 u16RbY; //Vertical position of window right-bottom point
+ MI_U16 u16ImgW; //the Width of the input image
+ MI_U16 u16ImgH; //the Hight of the input image
+} MI_VDF_Obj_t;
+
+typedef enum
+{
+ E_MI_VDF_COLOR_Y = 1,
+ E_MI_VDF_COLOR_MAX
+} MI_VDF_Color_e;
+
+typedef struct MI_MD_ResultSize_s
+{
+ MI_U32 u32RstStatusLen;
+ MI_U32 u32RstSadLen;
+ MI_U32 u32RstObjLen;
+} MI_MD_ResultSize_t;
+
+typedef struct MI_VDF_MdAttr_s
+{
+ MI_U8 u8Enable;
+ MI_U8 u8MdBufCnt;
+ MI_U8 u8VDFIntvl;
+ MI_U16 u16RstBufSize;
+ MI_MD_ResultSize_t stSubResultSize;
+ MDCCL_ctrl_t ccl_ctrl;
+ // MDOBJ_DATA_t ccobj;
+ MI_MD_static_param_t stMdStaticParamsIn;
+ MI_MD_param_t stMdDynamicParamsIn;
+} MI_VDF_MdAttr_t;
+
+typedef enum
+{
+ E_MI_VDF_ODWINDOW_1X1 = 0,
+ E_MI_VDF_ODWINDOW_2X2,
+ E_MI_VDF_ODWINDOW_3X3,
+ E_MI_VDF_ODWINDOW_MAX
+} MI_VDF_ODWindow_e;
+
+typedef struct MI_VDF_OdAttr_s
+{
+ MI_U8 u8Enable;
+ MI_U8 u8OdBufCnt;
+ MI_U8 u8VDFIntvl;
+ MI_U16 u16RstBufSize;
+ MI_OD_static_param_t stOdStaticParamsIn;
+ MI_OD_param_t stOdDynamicParamsIn;
+} MI_VDF_OdAttr_t;
+
+typedef struct MI_VDF_VgAttr_s
+{
+ MI_U8 u8Enable;
+ MI_U8 u8VgBufCnt;
+ MI_U8 u8VDFIntvl;
+ MI_U16 u16RstBufSize;
+
+ MI_U16 width;
+ MI_U16 height;
+ MI_U16 stride;
+
+ float object_size_thd;
+ uint8_t indoor;
+ uint8_t function_state;
+ uint16_t line_number;
+ MI_VgLine_t line[4];
+ MI_VgRegion_t vg_region;
+
+ MI_VgSet_t stVgParamsIn;
+} MI_VDF_VgAttr_t;
+
+typedef enum
+{
+ E_MI_VDF_WORK_MODE_MD = 0,
+ E_MI_VDF_WORK_MODE_OD,
+ E_MI_VDF_WORK_MODE_VG,
+ E_MI_VDF_WORK_MODE_MAX
+} MI_VDF_WorkMode_e;
+
+typedef struct MI_VDF_ChnAttr_s
+{
+ MI_VDF_WorkMode_e enWorkMode;
+ union
+ {
+ MI_VDF_MdAttr_t stMdAttr;
+ MI_VDF_OdAttr_t stOdAttr;
+ MI_VDF_VgAttr_t stVgAttr;
+ };
+} MI_VDF_ChnAttr_t;
+
+//======================= VDF Detect result =========================
+//——MD -->MI_VDF_MD_RESULT_S
+// |——Vi-Chn0 ->MD_RESULT_HANDLE_LIST
+// | |——Handle1 -->MD_RESULT_S
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-255
+// | |
+// | |——Handle2
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-255
+// | |
+// | |——Handle...
+// |
+// |——Vi-Chn1
+// | |——Handle1 -->MD_RESULT_S
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-255
+// | |
+// | |——Handle2
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-255
+// | |
+// | |——Handle...
+// |
+// |——Vi-Chnx
+// |
+
+//——OD -->MI_VDF_OD_RESULT_S
+// |——Vi-Chn0
+// | |——Handle1 -->OD_RESULT_S
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-8
+// | |
+// | |——Handle2
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-8
+// | |
+// | |——Handle...
+// |
+// |——Vi-Chn1
+// | |——Handle1 -->OD_RESULT_S
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-8
+// | |
+// | |——Handle2
+// | | |——sub-window-0
+// | | |——sub-window-1
+// | | |——...
+// | | |__sub-window-8
+// | |
+// | |——Handle...
+// |
+// |——Vi-Chnx
+// |
+
+typedef struct MDRST_STATUS_s
+{
+ MI_U8 *paddr; // 0-区块未检测运动，255-区块检测到运动
+} MDRST_STATUS_t;
+
+typedef struct MI_MD_Result_s
+{
+ MI_U64 u64Pts; //The PTS of Image
+ MI_U8 u8Enable; //=1表明该结果值有效
+ MI_MD_ResultSize_t stSubResultSize;
+ MDRST_STATUS_t* pstMdResultStatus; //The MD result of Status
+ MDSAD_DATA_t* pstMdResultSad; //The MD result of SAD
+ MDOBJ_DATA_t* pstMdResultObj; //The MD result of Obj
+} MI_MD_Result_t;
+
+typedef struct MI_OD_Result_s
+{
+ MI_U8 u8Enable;
+ MI_U8 u8WideDiv; //The number of divisions of window in horizontal direction
+ MI_U8 u8HightDiv; //The number of divisions of window in vertical direction
+ MI_U8 u8DataLen; //OD detect result readable size
+ MI_U64 u64Pts; //The PTS of Image
+ MI_S8 u8RgnAlarm[3][3]; //The OD result of the sub-window
+} MI_OD_Result_t;
+
+typedef MI_VgResult_t MI_VG_Result_t;
+
+typedef struct MI_VDF_Result_s
+{
+ MI_VDF_WorkMode_e enWorkMode;
+ VDF_RESULT_HANDLE handle;
+ union
+ {
+ MI_MD_Result_t stMdResult;
+ MI_OD_Result_t stOdResult;
+ MI_VG_Result_t stVgResult;
+ };
+} MI_VDF_Result_t;
+
+typedef struct MI_VDF_ChnStat_s
+{
+ MI_BOOL bStart;
+ MI_U8 u32LeftPic;
+ MI_U8 u32LeftRst;
+} MI_VDF_ChnStat_t;
+
+typedef struct MI_VDF_DebugInfo_s
+{
+ MI_VDF_WorkMode_e enWorkMode;
+ union
+ {
+ MI_VgDebug_t stVgDebugInfo;
+ };
+} MI_VDF_DebugInfo_t;
+
+#endif///_MI_VDF_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdisp.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdisp.h
new file mode 100644
index 00000000..621d5991
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdisp.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VDISP_H_
+#define _MI_VDISP_H_
+#include "mi_vdisp_datatype.h"
+
+#define VDISP_MAJOR_VERSION 2
+#define VDISP_SUB_VERSION 5
+#define MACRO_TO_STR(macro) #macro
+#define VDISP_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_vdisp_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_vdisp_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_vdisp_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_VDISP_API_VERSION VDISP_VERSION_STR(VDISP_MAJOR_VERSION,VDISP_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_VDISP_Init(void);
+MI_S32 MI_VDISP_Exit(void);
+
+MI_S32 MI_VDISP_OpenDevice(MI_VDISP_DEV DevId);
+MI_S32 MI_VDISP_CloseDevice(MI_VDISP_DEV DevId);
+
+MI_S32 MI_VDISP_SetOutputPortAttr(MI_VDISP_DEV DevId,
+ MI_VDISP_PORT PortId,
+ MI_VDISP_OutputPortAttr_t *pstOutputPortAttr);
+MI_S32 MI_VDISP_GetOutputPortAttr(MI_VDISP_DEV DevId,
+ MI_VDISP_PORT PortId,
+ MI_VDISP_OutputPortAttr_t *pstOutputPortAttr);
+
+MI_S32 MI_VDISP_SetInputChannelAttr(MI_VDISP_DEV DevId,
+ MI_VDISP_CHN ChnId,
+ MI_VDISP_InputChnAttr_t *pstInputChnAttr);
+MI_S32 MI_VDISP_GetInputChannelAttr(MI_VDISP_DEV DevId,
+ MI_VDISP_CHN ChnId,
+ MI_VDISP_InputChnAttr_t *pstInputChnAttr);
+
+MI_S32 MI_VDISP_EnableInputChannel(MI_VDISP_DEV DevId,
+ MI_VDISP_CHN ChnId);
+MI_S32 MI_VDISP_DisableInputChannel(MI_VDISP_DEV DevId,
+ MI_VDISP_CHN ChnId);
+
+MI_S32 MI_VDISP_StartDev(MI_VDISP_DEV DevId);
+MI_S32 MI_VDISP_StopDev(MI_VDISP_DEV DevId);
+
+MI_S32 MI_VDISP_InitDev(MI_VDISP_InitParam_t *pstInitParam);
+MI_S32 MI_VDISP_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VDISP_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdisp_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdisp_datatype.h
new file mode 100644
index 00000000..9df47f14
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vdisp_datatype.h
@@ -0,0 +1,84 @@
+/* SigmaStar trade secret */
+/* Copyright (c) [2019~2020] SigmaStar Technology.
+All rights reserved.
+
+Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+SigmaStar and be kept in strict confidence
+(SigmaStar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of SigmaStar Confidential
+Information is unlawful and strictly prohibited. SigmaStar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VDISP_DATATYPE_H_
+#define _MI_VDISP_DATATYPE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define VDISP_MAX_DEVICE_NUM 4
+#define VDISP_MAX_CHN_NUM_PER_DEV 16
+#define VDISP_MAX_INPUTPORT_NUM 1
+#define VDISP_MAX_OVERLAYINPUTCHN_NUM 4
+#define VDISP_OVERLAYINPUTCHNID VDISP_MAX_CHN_NUM_PER_DEV
+#define VDISP_MAX_OUTPUTPORT_NUM 1
+
+typedef MI_S32 MI_VDISP_DEV;
+typedef MI_S32 MI_VDISP_PORT;
+typedef MI_S32 MI_VDISP_CHN;
+
+typedef struct MI_VDISP_OutputPortAttr_s
+{
+ MI_U32 u32BgColor; /* Background color of a output port, in YUV format. [23:16]:v, [15:8]:y, [7:0]:u*/
+ MI_SYS_PixelFormat_e ePixelFormat; /* pixel format of a output port */
+ MI_U64 u64pts; /* current PTS */
+ MI_U32 u32FrmRate; /* the frame rate of output port */
+ MI_U32 u32Width; /* the frame width of a output port */
+ MI_U32 u32Height; /* the frame height of a output port */
+} MI_VDISP_OutputPortAttr_t;
+
+typedef struct MI_VDISP_InputPortAttr_s
+{
+ MI_U32 u32OutX; /* the output frame X position of this input port */
+ MI_U32 u32OutY; /* the output frame Y position of this input port */
+ MI_U32 u32OutWidth; /* the output frame width of this input port */
+ MI_U32 u32OutHeight; /* the output frame height of this input port */
+ MI_S32 s32IsFreeRun; /* is this port free run */
+} MI_VDISP_InputChnAttr_t;
+
+typedef enum
+{
+ E_MI_VDISP_ERR_DEV_OPENED=MI_VDISP_INITIAL_ERROR_CODE,
+ E_MI_VDISP_ERR_DEV_NOT_OPEN,
+ E_MI_VDISP_ERR_DEV_NOT_CLOSE,
+ E_MI_VDISP_ERR_PORT_NOT_UNBIND,
+}MI_VDISP_ErrCode_e;
+
+typedef struct MI_VDISP_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_VDISP_InitParam_t;
+
+#define MI_VDISP_ERR_FAIL (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED))
+#define MI_VDISP_ERR_INVALID_DEVID (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID))
+#define MI_VDISP_ERR_ILLEGAL_PARAM (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM))
+#define MI_VDISP_ERR_NOT_SUPPORT (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT))
+#define MI_VDISP_ERR_MOD_INITED (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INITED))
+#define MI_VDISP_ERR_MOD_NOT_INIT (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_INIT))
+#define MI_VDISP_ERR_DEV_OPENED (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_VDISP_ERR_DEV_OPENED))
+#define MI_VDISP_ERR_DEV_NOT_OPEN (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_VDISP_ERR_DEV_NOT_OPEN))
+#define MI_VDISP_ERR_DEV_NOT_STOP (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_DEV_NOT_STOPED))
+#define MI_VDISP_ERR_DEV_NOT_CLOSE (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_VDISP_ERR_DEV_NOT_CLOSE))
+#define MI_VDISP_ERR_NOT_CONFIG (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG))
+#define MI_VDISP_ERR_PORT_NOT_DISABLE (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_DISABLE))
+#define MI_VDISP_ERR_PORT_NOT_UNBIND (MI_DEF_ERR( E_MI_MODULE_ID_VDISP, E_MI_ERR_LEVEL_ERROR, E_MI_VDISP_ERR_PORT_NOT_UNBIND))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VDISP_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_venc.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_venc.h
new file mode 100644
index 00000000..2ab4c03c
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_venc.h
@@ -0,0 +1,116 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VENC_H_
+#define _MI_VENC_H_
+
+#include "mi_venc_datatype.h"
+
+#define VENC_MAJOR_VERSION 2
+#define VENC_SUB_VERSION 16
+#define MACRO_TO_STR(macro) #macro
+#define VENC_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_venc_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_venc_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_venc_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_VENC_API_VERSION VENC_VERSION_STR(VENC_MAJOR_VERSION,VENC_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+MI_S32 MI_VENC_GetChnDevid(MI_VENC_CHN VeChn, MI_U32 *pu32Devid);
+MI_S32 MI_VENC_SetModParam(MI_VENC_ModParam_t *pstModParam);
+MI_S32 MI_VENC_GetModParam(MI_VENC_ModParam_t *pstModParam);
+MI_S32 MI_VENC_CreateChn(MI_VENC_CHN VeChn, MI_VENC_ChnAttr_t *pstAttr);
+MI_S32 MI_VENC_DestroyChn(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_ResetChn(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_StartRecvPic(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_StartRecvPicEx(MI_VENC_CHN VeChn, MI_VENC_RecvPicParam_t *pstRecvParam);
+MI_S32 MI_VENC_StopRecvPic(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_Query(MI_VENC_CHN VeChn, MI_VENC_ChnStat_t *pstStat);
+MI_S32 MI_VENC_SetChnAttr(MI_VENC_CHN VeChn, MI_VENC_ChnAttr_t *pstAttr);
+MI_S32 MI_VENC_GetChnAttr(MI_VENC_CHN VeChn, MI_VENC_ChnAttr_t *pstAttr);
+MI_S32 MI_VENC_GetStream(MI_VENC_CHN VeChn, MI_VENC_Stream_t *pstStream, MI_S32 s32MilliSec);
+MI_S32 MI_VENC_ReleaseStream(MI_VENC_CHN VeChn, MI_VENC_Stream_t *pstStream);
+MI_S32 MI_VENC_InsertUserData(MI_VENC_CHN VeChn, MI_U8 *pu8Data, MI_U32 u32Len);
+MI_S32 MI_VENC_SetMaxStreamCnt(MI_VENC_CHN VeChn, MI_U32 u32MaxStrmCnt);
+MI_S32 MI_VENC_GetMaxStreamCnt(MI_VENC_CHN VeChn, MI_U32 *pu32MaxStrmCnt);
+MI_S32 MI_VENC_RequestIdr(MI_VENC_CHN VeChn, MI_BOOL bInstant);
+MI_S32 MI_VENC_EnableIdr(MI_VENC_CHN VeChn, MI_BOOL bEnableIdr);
+MI_S32 MI_VENC_SetH264IdrPicId(MI_VENC_CHN VeChn, MI_VENC_H264IdrPicIdCfg_t *pstH264eIdrPicIdCfg);
+MI_S32 MI_VENC_GetH264IdrPicId(MI_VENC_CHN VeChn, MI_VENC_H264IdrPicIdCfg_t *pstH264eIdrPicIdCfg);
+MI_S32 MI_VENC_GetFd(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_CloseFd(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_SetRoiCfg(MI_VENC_CHN VeChn, MI_VENC_RoiCfg_t *pstVencRoiCfg);
+MI_S32 MI_VENC_GetRoiCfg(MI_VENC_CHN VeChn, MI_U32 u32Index, MI_VENC_RoiCfg_t *pstVencRoiCfg);
+MI_S32 MI_VENC_SetRoiBgFrameRate(MI_VENC_CHN VeChn, MI_VENC_RoiBgFrameRate_t *pstRoiBgFrmRate);
+MI_S32 MI_VENC_GetRoiBgFrameRate(MI_VENC_CHN VeChn, MI_VENC_RoiBgFrameRate_t *pstRoiBgFrmRate);
+MI_S32 MI_VENC_SetH264SliceSplit(MI_VENC_CHN VeChn, MI_VENC_ParamH264SliceSplit_t *pstSliceSplit);
+MI_S32 MI_VENC_GetH264SliceSplit(MI_VENC_CHN VeChn, MI_VENC_ParamH264SliceSplit_t *pstSliceSplit);
+MI_S32 MI_VENC_SetH264InterPred(MI_VENC_CHN VeChn, MI_VENC_ParamH264InterPred_t *pstH264InterPred);
+MI_S32 MI_VENC_GetH264InterPred(MI_VENC_CHN VeChn, MI_VENC_ParamH264InterPred_t *pstH264InterPred);
+MI_S32 MI_VENC_SetH264IntraPred(MI_VENC_CHN VeChn, MI_VENC_ParamH264IntraPred_t *pstH264IntraPred);
+MI_S32 MI_VENC_GetH264IntraPred(MI_VENC_CHN VeChn, MI_VENC_ParamH264IntraPred_t *pstH264IntraPred);
+MI_S32 MI_VENC_SetH264Trans(MI_VENC_CHN VeChn, MI_VENC_ParamH264Trans_t *pstH264Trans);
+MI_S32 MI_VENC_GetH264Trans(MI_VENC_CHN VeChn, MI_VENC_ParamH264Trans_t *pstH264Trans);
+MI_S32 MI_VENC_SetH264Entropy(MI_VENC_CHN VeChn, MI_VENC_ParamH264Entropy_t *pstH264EntropyEnc);
+MI_S32 MI_VENC_GetH264Entropy(MI_VENC_CHN VeChn, MI_VENC_ParamH264Entropy_t *pstH264EntropyEnc);
+MI_S32 MI_VENC_SetH264Dblk(MI_VENC_CHN VeChn, MI_VENC_ParamH264Dblk_t *pstH264Dblk);
+MI_S32 MI_VENC_GetH264Dblk(MI_VENC_CHN VeChn, MI_VENC_ParamH264Dblk_t *pstH264Dblk);
+MI_S32 MI_VENC_SetH264Vui(MI_VENC_CHN VeChn, MI_VENC_ParamH264Vui_t*pstH264Vui);
+MI_S32 MI_VENC_GetH264Vui(MI_VENC_CHN VeChn, MI_VENC_ParamH264Vui_t *pstH264Vui);
+MI_S32 MI_VENC_SetH265SliceSplit(MI_VENC_CHN VeChn, MI_VENC_ParamH265SliceSplit_t *pstSliceSplit);
+MI_S32 MI_VENC_GetH265SliceSplit(MI_VENC_CHN VeChn, MI_VENC_ParamH265SliceSplit_t *pstSliceSplit);
+MI_S32 MI_VENC_SetH265InterPred(MI_VENC_CHN VeChn, MI_VENC_ParamH265InterPred_t *pstH265InterPred);
+MI_S32 MI_VENC_GetH265InterPred(MI_VENC_CHN VeChn, MI_VENC_ParamH265InterPred_t *pstH265InterPred);
+MI_S32 MI_VENC_SetH265IntraPred(MI_VENC_CHN VeChn, MI_VENC_ParamH265IntraPred_t *pstH265IntraPred);
+MI_S32 MI_VENC_GetH265IntraPred(MI_VENC_CHN VeChn, MI_VENC_ParamH265IntraPred_t *pstH265IntraPred);
+MI_S32 MI_VENC_SetH265Trans(MI_VENC_CHN VeChn, MI_VENC_ParamH265Trans_t *pstH265Trans);
+MI_S32 MI_VENC_GetH265Trans(MI_VENC_CHN VeChn, MI_VENC_ParamH265Trans_t *pstH265Trans);
+MI_S32 MI_VENC_SetH265Dblk(MI_VENC_CHN VeChn, MI_VENC_ParamH265Dblk_t *pstH265Dblk);
+MI_S32 MI_VENC_GetH265Dblk(MI_VENC_CHN VeChn, MI_VENC_ParamH265Dblk_t *pstH265Dblk);
+MI_S32 MI_VENC_SetH265Vui(MI_VENC_CHN VeChn, MI_VENC_ParamH265Vui_t*pstH265Vui);
+MI_S32 MI_VENC_GetH265Vui(MI_VENC_CHN VeChn, MI_VENC_ParamH265Vui_t *pstH265Vui);
+MI_S32 MI_VENC_SetJpegParam(MI_VENC_CHN VeChn, MI_VENC_ParamJpeg_t *pstJpegParam);
+MI_S32 MI_VENC_GetJpegParam(MI_VENC_CHN VeChn, MI_VENC_ParamJpeg_t *pstJpegParam);
+MI_S32 MI_VENC_SetRcParam(MI_VENC_CHN VeChn, MI_VENC_RcParam_t *pstRcParam);
+MI_S32 MI_VENC_GetRcParam(MI_VENC_CHN VeChn, MI_VENC_RcParam_t *pstRcParam);
+MI_S32 MI_VENC_SetRefParam(MI_VENC_CHN VeChn, MI_VENC_ParamRef_t *pstRefParam);
+MI_S32 MI_VENC_GetRefParam(MI_VENC_CHN VeChn, MI_VENC_ParamRef_t *pstRefParam);
+MI_S32 MI_VENC_SetCrop(MI_VENC_CHN VeChn, MI_VENC_CropCfg_t *pstCropCfg);
+MI_S32 MI_VENC_GetCrop(MI_VENC_CHN VeChn, MI_VENC_CropCfg_t *pstCropCfg);
+MI_S32 MI_VENC_SetFrameLostStrategy(MI_VENC_CHN VeChn, MI_VENC_ParamFrameLost_t *pstFrmLostParam);
+MI_S32 MI_VENC_GetFrameLostStrategy(MI_VENC_CHN VeChn, MI_VENC_ParamFrameLost_t *pstFrmLostParam);
+MI_S32 MI_VENC_SetSuperFrameCfg(MI_VENC_CHN VeChn, MI_VENC_SuperFrameCfg_t *pstSuperFrmParam);
+MI_S32 MI_VENC_GetSuperFrameCfg(MI_VENC_CHN VeChn, MI_VENC_SuperFrameCfg_t *pstSuperFrmParam);
+MI_S32 MI_VENC_SetRcPriority(MI_VENC_CHN VeChn, MI_VENC_RcPriority_e *peRcPriority);
+MI_S32 MI_VENC_GetRcPriority(MI_VENC_CHN VeChn, MI_VENC_RcPriority_e *peRcPriority);
+MI_S32 MI_VENC_DupChn(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_SetInputSourceConfig(MI_VENC_CHN VeChn, MI_VENC_InputSourceConfig_t *pstInputSourceConfig);
+MI_S32 MI_VENC_AllocCustomMap (MI_VENC_CHN VeChn, MI_PHY *pPhyAddr, void **ppCpuAddr);
+MI_S32 MI_VENC_ApplyCustomMap (MI_VENC_CHN VeChn, MI_PHY PhyAddr);
+MI_S32 MI_VENC_GetLastHistoStaticInfo (MI_VENC_CHN VeChn, MI_VENC_FrameHistoStaticInfo_t** ppFrmHistoStaticInfo);
+MI_S32 MI_VENC_ReleaseHistoStaticInfo(MI_VENC_CHN VeChn);
+MI_S32 MI_VENC_SetAdvCustRcAttr(MI_VENC_CHN VeChn, MI_VENC_AdvCustRcAttr_t *pstAdvCustRcAttr);
+MI_S32 MI_VENC_SetSmartDetInfo(MI_VENC_CHN VeChn, MI_VENC_SmartDetInfo_t *pstSmartDetInfo);
+MI_S32 MI_VENC_SetIntraRefresh(MI_VENC_CHN VeChn, MI_VENC_IntraRefresh_t *pstIntraRefresh);
+MI_S32 MI_VENC_GetIntraRefresh(MI_VENC_CHN VeChn, MI_VENC_IntraRefresh_t *pstIntraRefresh);
+MI_S32 MI_VENC_InitDev(MI_VENC_InitParam_t *pstInitParam);
+MI_S32 MI_VENC_DeInitDev(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_venc_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_venc_datatype.h
new file mode 100644
index 00000000..e846e027
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_venc_datatype.h
@@ -0,0 +1,944 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef __MI_VENC_DATATYPE_
+#define __MI_VENC_DATATYPE_
+
+#include "mi_common_datatype.h"
+#include "mi_sys_datatype.h"
+
+#define MI_VENC_MAX_CHN_NUM_PER_MODULE (9)
+#define MI_VENC_MAX_CHN_NUM_PER_DC (3)
+#define VENC_CUST_MAP_NUM (2)
+#define VENC_MAX_SAD_RANGE_NUM (16)
+
+//max supported channel number. But the number would be limited by each module.
+#define VENC_MAX_CHN_NUM (16) //from SPEC
+
+
+#define MI_DEF_VENC_ERR(err) MI_DEF_ERR(E_MI_MODULE_ID_VENC, E_MI_ERR_LEVEL_ERROR, err)
+
+#define MI_VENC_OK MI_DEF_VENC_ERR(MI_SUCCESS)
+
+/* invalid handle */
+//#define MI_ERR_VENC_INVALID_HANDLE MI_DEF_VENC_ERR(E_MI_ERR_INVALID_DEVID)
+
+/* invalid device ID */
+#define MI_ERR_VENC_INVALID_DEVID MI_DEF_VENC_ERR(E_MI_ERR_INVALID_DEVID)
+/* invalid channel ID */
+#define MI_ERR_VENC_INVALID_CHNID MI_DEF_VENC_ERR(E_MI_ERR_INVALID_CHNID)
+/* at lease one parameter is illegal, e.g, an illegal enumeration value */
+#define MI_ERR_VENC_ILLEGAL_PARAM MI_DEF_VENC_ERR(E_MI_ERR_ILLEGAL_PARAM)
+/* channel exists */
+#define MI_ERR_VENC_EXIST MI_DEF_VENC_ERR(E_MI_ERR_EXIST)
+/*UN exist*/
+#define MI_ERR_VENC_UNEXIST MI_DEF_VENC_ERR(E_MI_ERR_UNEXIST)
+/* using a NULL point */
+#define MI_ERR_VENC_NULL_PTR MI_DEF_VENC_ERR(E_MI_ERR_NULL_PTR)
+/* try to enable or initialize system,device or channel, before configuring attribute */
+#define MI_ERR_VENC_NOT_CONFIG MI_DEF_VENC_ERR(E_MI_ERR_NOT_CONFIG)
+/* operation is not supported by NOW */
+#define MI_ERR_VENC_NOT_SUPPORT MI_DEF_VENC_ERR(E_MI_ERR_NOT_SUPPORT)
+/* operation is not permitted, e.g, try to change static attribute */
+#define MI_ERR_VENC_NOT_PERM MI_DEF_VENC_ERR(E_MI_ERR_NOT_PERM)
+/* failure caused by malloc memory */
+#define MI_ERR_VENC_NOMEM MI_DEF_VENC_ERR(E_MI_ERR_NOMEM)
+/* failure caused by malloc buffer */
+#define MI_ERR_VENC_NOBUF MI_DEF_VENC_ERR(E_MI_ERR_NOBUF)
+/* no data in buffer */
+#define MI_ERR_VENC_BUF_EMPTY MI_DEF_VENC_ERR(E_MI_ERR_BUF_EMPTY)
+/* no buffer for new data */
+#define MI_ERR_VENC_BUF_FULL MI_DEF_VENC_ERR(E_MI_ERR_BUF_FULL)
+/* System is not ready,maybe not initialed or loaded.
+ * Returning the error code when opening a device file failed.
+ */
+#define MI_ERR_VENC_NOTREADY MI_DEF_VENC_ERR(E_MI_ERR_SYS_NOTREADY)
+
+/* bad address, e.g. used for copy_from_user & copy_to_user */
+#define MI_ERR_VENC_BADADDR MI_DEF_VENC_ERR(E_MI_ERR_BADADDR)
+/* resource is busy, e.g. destroy a VENC channel without unregistering it */
+#define MI_ERR_VENC_BUSY MI_DEF_VENC_ERR(E_MI_ERR_BUSY)
+
+/* channel not start*/
+#define MI_ERR_VENC_CHN_NOT_STARTED MI_DEF_VENC_ERR(E_MI_ERR_CHN_NOT_STARTED)
+/* channel not stop*/
+#define MI_ERR_VENC_CHN_NOT_STOPPED MI_DEF_VENC_ERR(E_MI_ERR_CHN_NOT_STOPED)
+
+#define MI_ERR_VENC_PRIVATE_START MI_DEF_VENC_ERR(MI_VENC_INITIAL_ERROR_CODE)
+/* to be removed later */
+#define MI_ERR_VENC_UNDEFINED MI_DEF_VENC_ERR(E_MI_ERR_FAILED)
+
+/* No error but return it's VENC no error.*/
+//#define MI_ERR_VENC_NONE MI_DEF_VENC_ERR(0)
+
+/* =======================================================
+ * Missing definitions
+ * =======================================================*/
+#define RC_TEXTURE_THR_SIZE 1 // Fixme
+
+/* =======================================================
+ * Missing Types
+ * =======================================================*/
+//FIXME add dummy fields at least
+/*
+#define MI_VENC_ParamModH264e_t MI_VENC_ParamModH265e_t
+#define MI_VENC_ParamModVenc_t MI_VENC_ParamModH265e_t
+*/
+
+/* =======================================================
+ * Data Types
+ * =======================================================*/
+
+//==== Enumerates ====
+typedef enum
+{
+ E_MI_VENC_MODTYPE_VENC = 1, //!< E_MI_VENC_MODTYPE_VENC
+ E_MI_VENC_MODTYPE_H264E, //!< E_MI_VENC_MODTYPE_H264E
+ E_MI_VENC_MODTYPE_H265E, //!< E_MI_VENC_MODTYPE_H265E
+ E_MI_VENC_MODTYPE_JPEGE, //!< E_MI_VENC_MODTYPE_JPEGE
+ E_MI_VENC_MODTYPE_MAX //!< E_MI_VENC_MODTYPE_MAX
+} MI_VENC_ModType_e;
+
+typedef enum
+{
+ E_MI_VENC_BASE_IDR = 0,
+ E_MI_VENC_BASE_P_REFTOIDR,
+ E_MI_VENC_BASE_P_REFBYBASE,
+ E_MI_VENC_BASE_P_REFBYENHANCE,
+ E_MI_VENC_ENHANCE_P_REFBYENHANCE,
+ E_MI_VENC_ENHANCE_P_NOTFORREF,
+ E_MI_VENC_REF_TYPE_MAX
+} MI_VENC_H264eRefType_e;
+typedef MI_VENC_H264eRefType_e MI_VENC_H265eRefType_e;
+
+typedef enum
+{
+ E_MI_VENC_H264E_NALU_PSLICE = 1,
+ E_MI_VENC_H264E_NALU_ISLICE = 5,
+ E_MI_VENC_H264E_NALU_SEI = 6,
+ E_MI_VENC_H264E_NALU_SPS = 7,
+ E_MI_VENC_H264E_NALU_PPS = 8,
+ E_MI_VENC_H264E_NALU_IPSLICE = 9,
+ E_MI_VENC_H264E_NALU_PREFIX = 14,
+ E_MI_VENC_H264E_NALU_MAX
+} MI_VENC_H264eNaluType_e;
+
+typedef enum
+{
+ E_MI_VENC_H264E_REFSLICE_FOR_1X = 1,
+ E_MI_VENC_H264E_REFSLICE_FOR_2X = 2,
+ E_MI_VENC_H264E_REFSLICE_FOR_4X,
+ E_MI_VENC_H264E_REFSLICE_FOR_MAX = 5
+} MI_VENC_H264eRefSliceType_e;
+
+typedef enum
+{
+ E_MI_VENC_JPEGE_PACK_ECS = 5,
+ E_MI_VENC_JPEGE_PACK_APP = 6,
+ E_MI_VENC_JPEGE_PACK_VDO = 7,
+ E_MI_VENC_JPEGE_PACK_PIC = 8,
+ E_MI_VENC_JPEGE_PACK_MAX
+} MI_VENC_JpegePackType_e;
+
+typedef enum
+{
+ E_MI_VENC_H265E_NALU_PSLICE = 1,
+ E_MI_VENC_H265E_NALU_ISLICE = 19,
+ E_MI_VENC_H265E_NALU_VPS = 32,
+ E_MI_VENC_H265E_NALU_SPS = 33,
+ E_MI_VENC_H265E_NALU_PPS = 34,
+ E_MI_VENC_H265E_NALU_SEI = 39,
+ E_MI_VENC_H265E_NALU_MAX
+} MI_VENC_H265eNaulType_e;
+
+typedef enum
+{
+ E_MI_VENC_RC_MODE_H264CBR = 1,
+ E_MI_VENC_RC_MODE_H264VBR,
+ E_MI_VENC_RC_MODE_H264ABR,
+ E_MI_VENC_RC_MODE_H264FIXQP,
+ E_MI_VENC_RC_MODE_H264AVBR,
+ E_MI_VENC_RC_MODE_MJPEGCBR,
+ E_MI_VENC_RC_MODE_MJPEGFIXQP,
+ E_MI_VENC_RC_MODE_H265CBR,
+ E_MI_VENC_RC_MODE_H265VBR,
+ E_MI_VENC_RC_MODE_H265FIXQP,
+ E_MI_VENC_RC_MODE_H265AVBR,
+ E_MI_VENC_RC_MODE_MAX,
+} MI_VENC_RcMode_e;
+
+typedef enum
+{
+ E_MI_VENC_SUPERFRM_NONE,
+ E_MI_VENC_SUPERFRM_DISCARD,
+ E_MI_VENC_SUPERFRM_REENCODE,
+ E_MI_VENC_SUPERFRM_MAX
+} MI_VENC_SuperFrmMode_e;
+
+typedef enum
+{
+ E_MI_VENC_H264E_IDR_PIC_ID_MODE_USR,
+} MI_VENC_H264eIdrPicIdMode_e;
+
+typedef enum
+{
+ E_MI_VENC_FRMLOST_NORMAL,
+ E_MI_VENC_FRMLOST_PSKIP,
+ E_MI_VENC_FRMLOST_MAX,
+} MI_VENC_FrameLostMode_e;
+
+typedef enum
+{
+ E_MI_VENC_RC_PRIORITY_BITRATE_FIRST = 1,
+ E_MI_VENC_RC_PRIORITY_FRAMEBITS_FIRST,
+ E_MI_VENC_RC_PRIORITY_MAX,
+} MI_VENC_RcPriority_e;
+
+typedef enum
+{
+ E_MI_VENC_INPUT_MODE_NORMAL_FRMBASE = 0, /*Handshake with input by about 3 buffers in frame mode*/
+ E_MI_VENC_INPUT_MODE_RING_ONE_FRM, /*Handshake with input by one buffer in ring mode*/
+ E_MI_VENC_INPUT_MODE_RING_HALF_FRM, /*Handshake with input by half buffer in ring mode*/
+ E_MI_VENC_INPUT_MODE_MAX
+} MI_VENC_InputSrcBufferMode_e;
+
+typedef enum
+{
+ E_MI_VENC_MD_DET=1,
+ E_MI_VENC_ROI_DET,
+ E_MI_VENC_SMART_DET_MAX,
+} MI_VENC_SmartDetType_e;
+
+//==== Structures ====
+
+typedef struct MI_VENC_Rect_s
+{
+ MI_U32 u32Left;
+ MI_U32 u32Top;
+ MI_U32 u32Width;
+ MI_U32 u32Height;
+} MI_VENC_Rect_t;
+
+typedef union MI_VENC_DataType_s
+{
+ MI_VENC_H264eNaluType_e eH264EType;
+ MI_VENC_JpegePackType_e eJPEGEType;
+ MI_VENC_H265eNaulType_e eH265EType;
+} MI_VENC_DataType_t;
+
+typedef struct MI_VENC_PackInfo_s
+{
+ MI_VENC_DataType_t stPackType;
+ MI_U32 u32PackOffset;
+ MI_U32 u32PackLength;
+ MI_U32 u32SliceId;
+} MI_VENC_PackInfo_t;
+
+typedef struct MI_VENC_Pack_s
+{
+ MI_PHY phyAddr;
+ MI_U8 *pu8Addr;
+ MI_U32 u32Len;
+ MI_U64 u64PTS;
+ MI_BOOL bFrameEnd;
+ MI_VENC_DataType_t stDataType;
+ MI_U32 u32Offset;
+ MI_U32 u32DataNum;
+ MI_VENC_PackInfo_t asackInfo[8];
+} MI_VENC_Pack_t;
+
+typedef struct MI_VENC_StreamInfoH264_s
+{
+ MI_U32 u32PicBytesNum;
+ MI_U32 u32PSkipMbNum;
+ MI_U32 u32IpcmMbNum;
+ MI_U32 u32Inter16x8MbNum;
+ MI_U32 u32Inter16x16MbNum;
+ MI_U32 u32Inter8x16MbNum;
+ MI_U32 u32Inter8x8MbNum;
+ MI_U32 u32Intra16MbNum;
+ MI_U32 u32Intra8MbNum;
+ MI_U32 u32Intra4MbNum;
+ MI_VENC_H264eRefSliceType_e eRefSliceType;
+ MI_VENC_H264eRefType_e eRefType;
+ MI_U32 u32UpdateAttrCnt;
+ MI_U32 u32StartQp;
+} MI_VENC_StreamInfoH264_t;
+
+typedef struct MI_VENC_StreamInfoJpeg_s
+{
+ MI_U32 u32PicBytesNum;
+ MI_U32 u32UpdateAttrCnt;
+ MI_U32 u32Qfactor;
+} MI_VENC_StreamInfoJpeg_t;
+
+typedef struct MI_VENC_StreamInfoH265_s
+{
+ MI_U32 u32PicBytesNum;
+ MI_U32 u32Inter64x64CuNum;
+ MI_U32 u32Inter32x32CuNum;
+ MI_U32 u32Inter16x16CuNum;
+ MI_U32 u32Inter8x8CuNum;
+ MI_U32 u32Intra32x32CuNum;
+ MI_U32 u32Intra16x16CuNum;
+ MI_U32 u32Intra8x8CuNum;
+ MI_U32 u32Intra4x4CuNum;
+ MI_VENC_H265eRefType_e eRefType;
+ MI_U32 u32UpdateAttrCnt;
+ MI_U32 u32StartQp;
+} MI_VENC_StreamInfoH265_t;
+
+typedef struct MI_VENC_Stream_s
+{
+ MI_VENC_Pack_t *pstPack;
+ MI_U32 u32PackCount;
+ MI_U32 u32Seq;
+ MI_SYS_BUF_HANDLE hMiSys;
+ union
+ {
+ MI_VENC_StreamInfoH264_t stH264Info;
+ MI_VENC_StreamInfoJpeg_t stJpegInfo;
+ MI_VENC_StreamInfoH265_t stH265Info;
+ };
+} MI_VENC_Stream_t;
+
+typedef struct MI_VENC_StreamBufInfo_s
+{
+ MI_PHY phyAddr;
+ void *pUserAddr;
+ MI_U32 u32BufSize;
+} MI_VENC_StreamBufInfo_t;
+
+typedef struct MI_VENC_AttrH264_s
+{
+ MI_U32 u32MaxPicWidth;
+ MI_U32 u32MaxPicHeight;
+ MI_U32 u32BufSize;
+ MI_U32 u32Profile;
+ MI_BOOL bByFrame;
+ MI_U32 u32PicWidth;
+ MI_U32 u32PicHeight;
+ MI_U32 u32BFrameNum;
+ MI_U32 u32RefNum;
+} MI_VENC_AttrH264_t;
+
+/*
+typedef struct MI_VENC_AttrMjpeg_s
+{
+ MI_U32 u32MaxPicWidth;
+ MI_U32 u32MaxPicHeight;
+ MI_U32 u32BufSize;
+ MI_BOOL bByFrame;
+ MI_U32 u32PicWidth;
+ MI_U32 u32PicHeight;
+} MI_VENC_AttrMjpeg_t;
+*/
+
+typedef struct MI_VENC_AttrJpeg_s
+{
+ MI_U32 u32MaxPicWidth;
+ MI_U32 u32MaxPicHeight;
+ MI_U32 u32BufSize;
+ MI_BOOL bByFrame;
+ MI_U32 u32PicWidth;
+ MI_U32 u32PicHeight;
+ MI_BOOL bSupportDCF;
+ MI_U32 u32RestartMakerPerRowCnt;
+} MI_VENC_AttrJpeg_t;
+
+typedef struct MI_VENC_AttrH265_s
+{
+ MI_U32 u32MaxPicWidth;
+ MI_U32 u32MaxPicHeight;
+ MI_U32 u32BufSize;
+ MI_U32 u32Profile;
+ MI_BOOL bByFrame;
+ MI_U32 u32PicWidth;
+ MI_U32 u32PicHeight;
+ MI_U32 u32BFrameNum;
+ MI_U32 u32RefNum;
+} MI_VENC_AttrH265_t;
+
+typedef struct MI_VENC_Attr_s
+{
+ MI_VENC_ModType_e eType;
+ union
+ {
+ MI_VENC_AttrH264_t stAttrH264e;
+ //MI_VENC_AttrMjpeg_t stAttrMjpeg;
+ MI_VENC_AttrJpeg_t stAttrJpeg;
+ MI_VENC_AttrH265_t stAttrH265e;
+ };
+} MI_VENC_Attr_t;
+
+typedef struct MI_VENC_ChnStat_s
+{
+ MI_U32 u32LeftPics;
+ MI_U32 u32LeftStreamBytes;
+ MI_U32 u32LeftStreamFrames;
+ MI_U32 u32LeftStreamMillisec;
+ MI_U32 u32CurPacks;
+ MI_U32 u32LeftRecvPics;
+ MI_U32 u32LeftEncPics;
+ MI_U32 u32FrmRateNum;
+ MI_U32 u32FrmRateDen;
+ MI_U32 u32BitRate;
+} MI_VENC_ChnStat_t;
+
+typedef struct MI_VENC_ParamH264SliceSplit_s
+{
+ MI_BOOL bSplitEnable;
+ MI_U32 u32SliceRowCount;
+} MI_VENC_ParamH264SliceSplit_t;
+
+typedef struct MI_VENC_ParamH264InterPred_s
+{
+ /* search window */
+ MI_U32 u32HWSize;
+ MI_U32 u32VWSize;
+ MI_BOOL bInter16x16PredEn;
+ MI_BOOL bInter16x8PredEn;
+ MI_BOOL bInter8x16PredEn;
+ MI_BOOL bInter8x8PredEn;
+ MI_BOOL bInter8x4PredEn;
+ MI_BOOL bInter4x8PredEn;
+ MI_BOOL bInter4x4PredEn;
+ MI_BOOL bExtedgeEn;
+} MI_VENC_ParamH264InterPred_t;
+
+typedef struct MI_VENC_ParamH264IntraPred_s
+{
+ MI_BOOL bIntra16x16PredEn;
+ MI_BOOL bIntraNxNPredEn;
+ MI_BOOL bConstrainedIntraPredFlag; //special naming for CODEC ISO SPEC.
+ MI_BOOL bIpcmEn;
+ MI_U32 u32Intra16x16Penalty;
+ MI_U32 u32Intra4x4Penalty;
+ MI_BOOL bIntraPlanarPenalty;
+} MI_VENC_ParamH264IntraPred_t;
+
+typedef struct MI_VENC_ParamH264Trans_s
+{
+ MI_U32 u32IntraTransMode;
+ MI_U32 u32InterTransMode;
+ MI_S32 s32ChromaQpIndexOffset;
+} MI_VENC_ParamH264Trans_t;
+
+typedef struct MI_VENC_ParamH264Entropy_s
+{
+ MI_U32 u32EntropyEncModeI;
+ MI_U32 u32EntropyEncModeP;
+} MI_VENC_ParamH264Entropy_t;
+
+typedef struct MI_VENC_ParamH265InterPred_s
+{
+ /* search window */
+ MI_U32 u32HWSize;
+ MI_U32 u32VWSize;
+ MI_BOOL bInter16x16PredEn;
+ MI_BOOL bInter16x8PredEn;
+ MI_BOOL bInter8x16PredEn;
+ MI_BOOL bInter8x8PredEn;
+ MI_BOOL bInter8x4PredEn;
+ MI_BOOL bInter4x8PredEn;
+ MI_BOOL bInter4x4PredEn;
+ MI_U32 u32Inter32x32Penalty;
+ MI_U32 u32Inter16x16Penalty;
+ MI_U32 u32Inter8x8Penalty;
+ MI_BOOL bExtedgeEn;
+} MI_VENC_ParamH265InterPred_t;
+
+typedef struct MI_VENC_ParamH265IntraPred_s
+{
+ MI_BOOL bIntra32x32PredEn;
+ MI_BOOL bIntra16x16PredEn;
+ MI_BOOL bIntra8x8PredEn;
+ MI_BOOL bConstrainedIntraPredFlag;
+ MI_U32 u32Intra32x32Penalty;
+ MI_U32 u32Intra16x16Penalty;
+ MI_U32 u32Intra8x8Penalty;
+} MI_VENC_ParamH265IntraPred_t;
+
+typedef struct MI_VENC_ParamH265Trans_s
+{
+ MI_U32 u32IntraTransMode;
+ MI_U32 u32InterTransMode;
+ MI_S32 s32ChromaQpIndexOffset;
+} MI_VENC_ParamH265Trans_t;
+
+typedef struct MI_VENC_ParamH264Dblk_s
+{
+ MI_U32 disable_deblocking_filter_idc; //special naming for CODEC ISO SPEC.
+ MI_S32 slice_alpha_c0_offset_div2; //special naming for CODEC ISO SPEC.
+ MI_S32 slice_beta_offset_div2; //special naming for CODEC ISO SPEC.
+} MI_VENC_ParamH264Dblk_t;
+
+typedef struct MI_VENC_ParamH264VuiAspectRatio_s
+{
+ MI_U8 u8AspectRatioInfoPresentFlag;
+ MI_U8 u8AspectRatioIdc;
+ MI_U8 u8OverscanInfoPresentFlag;
+ MI_U8 u8OverscanAppropriateFlag;
+ MI_U16 u16SarWidth;
+ MI_U16 u16SarHeight;
+} MI_VENC_ParamH264VuiAspectRatio_t;
+
+typedef struct MI_VENC_ParamH264VuiTimeInfo_s
+{
+ MI_U8 u8TimingInfoPresentFlag;
+ MI_U8 u8FixedFrameRateFlag;
+ MI_U32 u32NumUnitsInTick;
+ MI_U32 u32TimeScale;
+} MI_VENC_ParamH264VuiTimeInfo_t;
+
+typedef struct MI_VENC_ParamH264VuiVideoSignal_s
+{
+ MI_U8 u8VideoSignalTypePresentFlag;
+ MI_U8 u8VideoFormat;
+ MI_U8 u8VideoFullRangeFlag;
+ MI_U8 u8ColourDescriptionPresentFlag;
+ MI_U8 u8ColourPrimaries;
+ MI_U8 u8TransferCharacteristics;
+ MI_U8 u8MatrixCoefficients;
+} MI_VENC_ParamH264VuiVideoSignal_t;
+
+typedef struct MI_VENC_ParamH264Vui_s
+{
+ MI_VENC_ParamH264VuiAspectRatio_t stVuiAspectRatio;
+ MI_VENC_ParamH264VuiTimeInfo_t stVuiTimeInfo;
+ MI_VENC_ParamH264VuiVideoSignal_t stVuiVideoSignal;
+} MI_VENC_ParamH264Vui_t;
+
+typedef struct MI_VENC_ParamH265VuiAspectRatio_s
+{
+ MI_U8 u8AspectRatioInfoPresentFlag;
+ MI_U8 u8AspectRatioIdc;
+ MI_U8 u8OverscanInfoPresentFlag;
+ MI_U8 u8OverscanAppropriateFlag;
+ MI_U16 u16SarWidth;
+ MI_U16 u16SarHeight;
+} MI_VENC_ParamH265VuiAspectRatio_t;
+
+typedef struct MI_VENC_ParamH265VuiTimeInfo_s
+{
+ MI_U8 u8TimingInfoPresentFlag;
+ //MI_U8 u8FixedFrameRateFlag;
+ MI_U32 u32NumUnitsInTick;
+ MI_U32 u32TimeScale;
+} MI_VENC_ParamH265VuiTimeInfo_t;
+
+typedef struct MI_VENC_ParamH265VuiVideoSignal_s
+{
+ MI_U8 u8VideoSignalTypePresentFlag;
+ MI_U8 u8VideoFormat;
+ MI_U8 u8VideoFullRangeFlag;
+ MI_U8 u8ColourDescriptionPresentFlag;
+ MI_U8 u8ColourPrimaries;
+ MI_U8 u8TransferCharacteristics;
+ MI_U8 u8MatrixCoefficients;
+} MI_VENC_ParamH265VuiVideoSignal_t;
+
+typedef struct MI_VENC_ParamH265Vui_s
+{
+ MI_VENC_ParamH265VuiAspectRatio_t stVuiAspectRatio;
+ MI_VENC_ParamH265VuiTimeInfo_t stVuiTimeInfo;
+ MI_VENC_ParamH265VuiVideoSignal_t stVuiVideoSignal;
+} MI_VENC_ParamH265Vui_t;
+
+typedef struct MI_VENC_ParamH265SliceSplit_s
+{
+ MI_BOOL bSplitEnable;
+ MI_U32 u32SliceRowCount;
+} MI_VENC_ParamH265SliceSplit_t;
+
+typedef struct MI_VENC_ParamH265Dblk_s
+{
+ MI_U32 disable_deblocking_filter_idc; //special naming for CODEC ISO SPEC.
+ MI_S32 slice_tc_offset_div2; //special naming for CODEC ISO SPEC.
+ MI_S32 slice_beta_offset_div2; //special naming for CODEC ISO SPEC.
+} MI_VENC_ParamH265Dblk_t;
+
+typedef struct MI_VENC_ParamJpeg_s
+{
+ MI_U32 u32Qfactor;
+ MI_U8 au8YQt[64];
+ MI_U8 au8CbCrQt[64];
+ MI_U32 u32McuPerEcs;
+} MI_VENC_ParamJpeg_t;
+
+typedef struct MI_VENC_ParamMjpeg_s
+{
+ MI_U8 au8YQt[64];
+ MI_U32 u32McuPerEcs;
+} MI_VENC_ParamMjpeg_t;
+
+typedef struct MI_VENC_RoiCfg_s
+{
+ MI_U32 u32Index;
+ MI_BOOL bEnable;
+ MI_BOOL bAbsQp;
+ MI_S32 s32Qp;
+ MI_VENC_Rect_t stRect;
+} MI_VENC_RoiCfg_t;
+
+typedef struct MI_VENC_RoiBgFrameRate_s
+{
+ MI_S32 s32SrcFrmRate;
+ MI_S32 s32DstFrmRate;
+} MI_VENC_RoiBgFrameRate_t;
+
+typedef struct MI_VENC_ParamRef_s
+{
+ MI_U32 u32Base;
+ MI_U32 u32Enhance;
+ MI_BOOL bEnablePred;
+} MI_VENC_ParamRef_t;
+
+typedef struct MI_VENC_AttrH264Cbr_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32StatTime;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32BitRate;
+ MI_U32 u32FluctuateLevel;
+} MI_VENC_AttrH264Cbr_t;
+
+typedef struct MI_VENC_AttrH264Vbr_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32StatTime;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32MaxBitRate;
+ MI_U32 u32MaxQp;
+ MI_U32 u32MinQp;
+} MI_VENC_AttrH264Vbr_t;
+
+typedef struct MI_VENC_AttrH264FixQp_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32IQp;
+ MI_U32 u32PQp;
+} MI_VENC_AttrH264FixQp_t;
+
+typedef struct MI_VENC_AttrH264Abr_s
+{
+ MI_U32 u32Gop; /*the interval of ISLICE. */
+ MI_U32 u32StatTime; /* the rate statistic time, the unit is seconds(s) */
+ MI_U32 u32SrcFrmRateNum;/* the input frame rate of the venc */
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32AvgBitRate; /* average bitrate */
+ MI_U32 u32MaxBitRate; /* the max bitrate */
+} MI_VENC_AttrH264Abr_t;
+
+typedef struct MI_VENC_AttrH264Avbr_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32StatTime;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32MaxBitRate;
+ MI_U32 u32MaxQp;
+ MI_U32 u32MinQp;
+} MI_VENC_AttrH264Avbr_t;
+
+typedef struct MI_VENC_AttrMjpegCbr_s
+{
+ MI_U32 u32BitRate;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+} MI_VENC_AttrMjpegCbr_t;
+
+typedef struct MI_VENC_AttrMjpegFixQp_s
+{
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32Qfactor;
+} MI_VENC_AttrMjpegFixQp_t;
+
+typedef struct MI_VENC_AttrH265Cbr_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32StatTime;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32BitRate;
+ MI_U32 u32FluctuateLevel;
+} MI_VENC_AttrH265Cbr_t;
+
+typedef struct MI_VENC_AttrH265Vbr_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32StatTime;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32MaxBitRate;
+ MI_U32 u32MaxQp;
+ MI_U32 u32MinQp;
+} MI_VENC_AttrH265Vbr_t;
+
+typedef struct MI_VENC_AttrH265FixQp_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32IQp;
+ MI_U32 u32PQp;
+} MI_VENC_AttrH265FixQp_t;
+
+typedef struct MI_VENC_AttrH265Avbr_s
+{
+ MI_U32 u32Gop;
+ MI_U32 u32StatTime;
+ MI_U32 u32SrcFrmRateNum;
+ MI_U32 u32SrcFrmRateDen;
+ MI_U32 u32MaxBitRate;
+ MI_U32 u32MaxQp;
+ MI_U32 u32MinQp;
+} MI_VENC_AttrH265Avbr_t;
+
+typedef struct MI_VENC_RcAttr_s
+{
+ MI_VENC_RcMode_e eRcMode;
+ union
+ {
+ MI_VENC_AttrH264Cbr_t stAttrH264Cbr;
+ MI_VENC_AttrH264Vbr_t stAttrH264Vbr;
+ MI_VENC_AttrH264FixQp_t stAttrH264FixQp;
+ MI_VENC_AttrH264Abr_t stAttrH264Abr;
+ MI_VENC_AttrH264Avbr_t stAttrH264Avbr;
+ MI_VENC_AttrMjpegCbr_t stAttrMjpegCbr;
+ MI_VENC_AttrMjpegFixQp_t stAttrMjpegFixQp;
+ MI_VENC_AttrH265Cbr_t stAttrH265Cbr;
+ MI_VENC_AttrH265Vbr_t stAttrH265Vbr;
+ MI_VENC_AttrH265FixQp_t stAttrH265FixQp;
+ MI_VENC_AttrH265Avbr_t stAttrH265Avbr;
+ };
+ void* pRcAttr;
+} MI_VENC_RcAttr_t;
+
+typedef struct MI_VENC_ChnAttr_s
+{
+ MI_VENC_Attr_t stVeAttr;
+ MI_VENC_RcAttr_t stRcAttr;
+} MI_VENC_ChnAttr_t;
+
+typedef struct MI_VENC_ParamH264Vbr_s
+{
+ MI_S32 s32IPQPDelta;
+ MI_S32 s32ChangePos;
+ MI_U32 u32MaxIQp;
+ MI_U32 u32MinIQp;
+ MI_U32 u32MaxIPProp;
+} MI_VENC_ParamH264Vbr_t;
+
+typedef struct MI_VENC_ParamH264Cbr_s
+{
+ MI_U32 u32MaxQp;
+ MI_U32 u32MinQp;
+ MI_S32 s32IPQPDelta;
+ MI_U32 u32MaxIQp;
+ MI_U32 u32MinIQp;
+ MI_U32 u32MaxIPProp;
+} MI_VENC_ParamH264Cbr_t;
+
+typedef struct MI_VENC_ParamH264Avbr_s
+{
+ MI_S32 s32IPQPDelta;
+ MI_S32 s32ChangePos;
+ MI_U32 u32MinIQp;
+ MI_U32 u32MaxIPProp;
+ MI_U32 u32MaxIQp;
+ MI_U32 u32MaxISize;
+ MI_U32 u32MaxPSize;
+ MI_U32 u32MinStillPercent;
+ MI_U32 u32MaxStillQp;
+ MI_U32 u32MotionSensitivity;
+} MI_VENC_ParamH264Avbr_t;
+
+typedef struct MI_VENC_ParamMjpegCbr_s
+{
+ MI_U32 u32MaxQfactor;
+ MI_U32 u32MinQfactor;
+} MI_VENC_ParamMjpegCbr_t;
+
+typedef struct MI_VENC_ParamH265Vbr_s
+{
+ MI_S32 s32IPQPDelta;
+ MI_S32 s32ChangePos;
+ MI_U32 u32MaxIQp;
+ MI_U32 u32MinIQp;
+ MI_U32 u32MaxIPProp;
+} MI_VENC_ParamH265Vbr_t;
+
+typedef struct MI_VENC_ParamH265Cbr_s
+{
+ MI_U32 u32MaxQp;
+ MI_U32 u32MinQp;
+ MI_S32 s32IPQPDelta;
+ MI_U32 u32MaxIQp;
+ MI_U32 u32MinIQp;
+ MI_U32 u32MaxIPProp;
+} MI_VENC_ParamH265Cbr_t;
+
+typedef struct MI_VENC_ParamH265Avbr_s
+{
+ MI_S32 s32IPQPDelta;
+ MI_S32 s32ChangePos;
+ MI_U32 u32MinIQp;
+ MI_U32 u32MaxIPProp;
+ MI_U32 u32MaxIQp;
+ MI_U32 u32MaxISize;
+ MI_U32 u32MaxPSize;
+ MI_U32 u32MinStillPercent;
+ MI_U32 u32MaxStillQp;
+ MI_U32 u32MotionSensitivity;
+} MI_VENC_ParamH265Avbr_t;
+
+typedef struct MI_VENC_RcParam_s
+{
+ MI_U32 au32ThrdI[RC_TEXTURE_THR_SIZE];
+ MI_U32 au32ThrdP[RC_TEXTURE_THR_SIZE];
+ MI_U32 u32RowQpDelta;
+ union
+ {
+ MI_VENC_ParamH264Cbr_t stParamH264Cbr;
+ MI_VENC_ParamH264Vbr_t stParamH264VBR;
+ MI_VENC_ParamH264Avbr_t stParamH264Avbr;
+ MI_VENC_ParamMjpegCbr_t stParamMjpegCbr;
+ MI_VENC_ParamH265Cbr_t stParamH265Cbr;
+ MI_VENC_ParamH265Vbr_t stParamH265Vbr;
+ MI_VENC_ParamH265Avbr_t stParamH265Avbr;
+ };
+ void* pRcParam;
+} MI_VENC_RcParam_t;
+
+typedef struct MI_VENC_CropCfg_s
+{
+ MI_BOOL bEnable; /* Crop region enable */
+ MI_VENC_Rect_t stRect; /* Crop region, note: s32X must be multi of 16 */
+} MI_VENC_CropCfg_t;
+
+typedef struct MI_VENC_RecvPicParam_s
+{
+ MI_S32 s32RecvPicNum;
+} MI_VENC_RecvPicParam_t;
+
+typedef struct MI_VENC_H264IdrPicIdCfg_s
+{
+ MI_VENC_H264eIdrPicIdMode_e eH264eIdrPicIdMode;
+ MI_U32 u32H264eIdrPicId;
+} MI_VENC_H264IdrPicIdCfg_t;
+
+typedef struct MI_VENC_ParamFrameLost_s
+{
+ MI_BOOL bFrmLostOpen;
+ MI_U32 u32FrmLostBpsThr;
+ MI_VENC_FrameLostMode_e eFrmLostMode;
+ MI_U32 u32EncFrmGaps;
+} MI_VENC_ParamFrameLost_t;
+
+typedef struct MI_VENC_SuperFrameCfg_s
+{
+ MI_VENC_SuperFrmMode_e eSuperFrmMode;
+ MI_U32 u32SuperIFrmBitsThr;
+ MI_U32 u32SuperPFrmBitsThr;
+ MI_U32 u32SuperBFrmBitsThr;
+} MI_VENC_SuperFrameCfg_t;
+
+typedef struct MI_VENC_ParamModH265e_s
+{
+ MI_U32 u32OneStreamBuffer;
+ MI_U32 u32H265eMiniBufMode;
+} MI_VENC_ParamModH265e_t;
+
+typedef struct MI_VENC_ParamModJpege_s
+{
+ MI_U32 u32OneStreamBuffer;
+ MI_U32 u32JpegeMiniBufMode;
+} MI_VENC_ParamModJpege_t;
+
+typedef struct MI_VENC_ModParam_s
+{
+ MI_VENC_ModType_e eVencModType;
+ union
+ {
+ //MI_VENC_ParamModVenc_t stVencModParam; //not defined yet
+ //MI_VENC_ParamModH264e_t stH264eModParam; //not defined yet
+ MI_VENC_ParamModH265e_t stH265eModParam;
+ MI_VENC_ParamModJpege_t stJpegeModParam;
+ };
+} MI_VENC_ModParam_t;
+
+typedef struct MI_VENC_InputSourceConfig_s
+{
+ MI_VENC_InputSrcBufferMode_e eInputSrcBufferMode;
+}MI_VENC_InputSourceConfig_t;
+
+typedef struct MI_VENC_FrameHistoStaticInfo_s
+{
+ MI_U8 u8PicSkip;
+ MI_U16 u16PicType;
+ MI_U32 u32PicPoc;
+ MI_U32 u32PicSliNum;
+ MI_U32 u32PicNumIntra;
+ MI_U32 u32PicNumMerge;
+ MI_U32 u32PicNumSkip;
+ MI_U32 u32PicAvgCtuQp;
+ MI_U32 u32PicByte;
+ MI_U32 u32GopPicIdx;
+ MI_U32 u32PicNum;
+ MI_U32 u32PicDistLow;
+ MI_U32 u32PicDistHigh;
+} MI_VENC_FrameHistoStaticInfo_t;
+
+typedef struct MI_VENC_AdvCustRcAttr_s
+{
+ MI_BOOL bEnableQPMap;
+ MI_BOOL bAbsQP;
+ MI_BOOL bEnableModeMap;
+ MI_BOOL bEnabelHistoStaticInfo;
+} MI_VENC_AdvCustRcAttr_t;
+
+typedef struct MI_VENC_MdInfo_s
+{
+ MI_U16 u16SadRangeRatio[VENC_MAX_SAD_RANGE_NUM];
+} MI_VENC_MdInfo_t;
+
+typedef struct MI_VENC_SmartDetInfo_s
+{
+ MI_VENC_SmartDetType_e eSmartDetType;
+ union
+ {
+ MI_VENC_MdInfo_t stMdInfo;
+ MI_BOOL bRoiExist;
+ };
+ MI_U8 u8ProtectFrmNum;
+} MI_VENC_SmartDetInfo_t;
+
+typedef struct MI_VENC_IntraRefresh_s
+{
+ MI_BOOL bEnable;
+ MI_U32 u32RefreshLineNum;
+ MI_U32 u32ReqIQp;
+}MI_VENC_IntraRefresh_t;
+
+typedef struct MI_VENC_InitParam_s
+{
+ MI_U32 u32MaxWidth;
+ MI_U32 u32MaxHeight;
+}MI_VENC_InitParam_t;
+#endif /* End of #ifndef __MI_VENC_DATATYPE_ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vg.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vg.h
new file mode 100644
index 00000000..2d842858
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vg.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+/*
+ * mi_vg.h
+ * Author: chiao.su
+ */
+
+#ifndef MI_VG_H_
+#define MI_VG_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+
+#define VG_MAJOR_VERSION 2
+#define VG_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define VG_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_vg_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_vg_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_vg_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_VG_API_VERSION VG_VERSION_STR(VG_MAJOR_VERSION,VG_SUB_VERSION)
+
+#define MAX_NUMBER 4
+
+typedef enum _MI_VG_RET_E
+{
+ MI_VG_RET_SUCCESS = 0x00000000, /*VG Success*/
+ MI_VG_RET_INIT_ERROR = 0x10000301, /*VG init error*/
+ MI_VG_RET_IC_CHECK_ERROR = 0x10000302, /*VG platform check error*/
+ MI_VG_RET_INVALID_USER_INFO_POINTER = 0x10000303, /*Invalid user information pointer*/
+ MI_VG_RET_INVALID_FUNCTION_STATE = 0x10000304, /*Invalid function state*/
+ MI_VG_RET_INVALID_OBJECT_THRESHOLD = 0x10000305, /*Invalid object threshold*/
+ MI_VG_RET_INVALID_THRESHOLD_POINTER = 0x10000306, /*Invalid threshold pointer*/
+ MI_VG_RET_INVALID_ENVIRONMENT_STATE = 0x10000307, /*Invalid environment state*/
+ MI_VG_RET_INVALID_ENVIRONMENT_POINTER = 0x10000308, /*Invalid environment pointer*/
+ MI_VG_RET_INVALID_LINE_NUMBER = 0x10000309, /*Invalid line number*/
+ MI_VG_RET_INVALID_LINE_POINTER = 0x1000030A, /*Invalid line pointer*/
+ MI_VG_RET_INVALID_LINE_COORDINATE = 0x1000030B, /*Invalid line coordinate*/
+ MI_VG_RET_INVALID_LINE_COORDINATE_POINTER = 0x1000030C, /*Invalid line coordinate pointer*/
+ MI_VG_RET_INVALID_LINE_MAGIC_NUMBER = 0x1000030D, /*Invalid line magic number*/
+ MI_VG_RET_INVALID_REGION_COORDINATE_POINTER = 0x1000030E, /*Invalid region coordinate pointer*/
+ MI_VG_RET_INVALID_REGION_MAGIC_NUMBER = 0x1000030F, /*Invalid region magic number*/
+ MI_VG_RET_INVALID_REGION_COORDINATE = 0x10000310, /*Invalid region coordinate*/
+ MI_VG_RET_INVALID_HANDLE = 0x10000311, /*Invalid VG handle*/
+ MI_VG_RET_INVALID_HANDLE_MAGIC_NUMBER = 0x10000312, /*Invalid handle magic number*/
+ MI_VG_RET_INVALID_INPUT_POINTER = 0x10000313, /*Invalid input pointer*/
+ MI_VG_RET_OPERATE_ERROR = 0x10000314, /*VG operate error*/
+ MI_VG_RET_INVALID_ALARM_POINTER = 0x10000315, /*Invalid alarm pointer*/
+ MI_VG_RET_INVALID_DEBUG_POINTER = 0x10000316, /*Invalid debug pointer*/
+ MI_VG_RET_INVALID_DETECT_PARAMETER_POINTER = 0x10000317, /*Invalid detect parameters pointer*/
+ MI_VG_RET_INVALID_FUNCTION_SWITCH = 0x10000318, /*Invalid function switch*/
+ MI_VG_RET_INVALID_DETECT_THRESHOLD = 0x10000319 /*Invalid detection threshold*/
+} MI_VG_RET;
+
+typedef enum _VgFunction
+{
+ VG_VIRTUAL_GATE = 2,
+ VG_REGION_INVASION = 3
+} VgFunction;
+
+typedef enum _VgRegion_Dir
+{
+ VG_REGION_ENTER = 0,
+ VG_REGION_LEAVING = 1,
+ VG_REGION_CROSS = 2
+} VgRegion_Dir;
+
+typedef enum _VgSize_Sensitively
+{
+ VG_SENSITIVELY_MIN = 0,
+ VG_SENSITIVELY_LOW = 1,
+ VG_SENSITIVELY_MIDDLE = 2,
+ VG_SENSITIVELY_HIGH = 3,
+ VG_SENSITIVELY_MAX = 4
+} VgSize_Sensitively;
+
+typedef struct _VG_Point_t
+{
+ int32_t x;
+ int32_t y;
+} MI_VG_Point_t;
+
+typedef struct _VG_Line_t
+{
+ MI_VG_Point_t px; //point x
+ MI_VG_Point_t py; //point y
+ MI_VG_Point_t pdx; //point direction x
+ MI_VG_Point_t pdy; //point direction y
+} MI_VgLine_t;
+
+typedef struct _VG_Region_t
+{
+ MI_VG_Point_t p_one; //point one
+ MI_VG_Point_t p_two; //point two
+ MI_VG_Point_t p_three; //point three
+ MI_VG_Point_t p_four; //point four
+
+ int region_dir; //Region direction;
+} MI_VgRegion_t;
+
+typedef struct _MI_VgSet_t
+{
+ //Common Information
+ float object_size_thd;
+ uint16_t line_number;
+ uint8_t indoor;
+
+ //Line info
+ MI_VG_Point_t fp[MAX_NUMBER]; //First point
+ MI_VG_Point_t sp[MAX_NUMBER]; //Second point
+ MI_VG_Point_t fdp[MAX_NUMBER]; //First direction point
+ MI_VG_Point_t sdp[MAX_NUMBER]; //Second direction point
+
+ //Function
+ uint8_t function_state;
+
+ //Region info
+ MI_VG_Point_t first_p; //First point
+ MI_VG_Point_t second_p; //Second point
+ MI_VG_Point_t third_p; //Third point
+ MI_VG_Point_t fourth_p; //Fourth point
+
+ //Region direction
+ uint8_t region_direction;
+
+ //Magic_number
+ int32_t magic_number;
+} MI_VgSet_t;
+
+typedef struct _MI_VgBoundingBox_t
+{
+ int32_t up; //Min y
+ int32_t down; //Max y
+ int32_t left; //Min x
+ int32_t right; //Max x
+} MI_VgBoundingBox_t;
+
+typedef struct _MI_VgResult_t
+{
+ int32_t alarm[MAX_NUMBER];
+ int32_t alarm_cnt;
+ MI_VgBoundingBox_t bounding_box[20];
+} MI_VgResult_t;
+
+typedef struct _MI_VdDetectThd_t
+{
+ uint8_t function_switch;
+ uint8_t detect_thd;
+} MI_VgDetectThd;
+
+typedef struct _MI_VgDebug_t
+{
+ //Common Information
+ uint16_t background_state;
+ uint32_t version; //Modify date
+ uint32_t debug_object_size;
+ uint32_t debug_state;
+
+ //Line info
+ MI_VG_Point_t dfp[MAX_NUMBER]; //Debug First point
+ MI_VG_Point_t dsp[MAX_NUMBER]; //Debug Second point
+ MI_VG_Point_t dfdp[MAX_NUMBER]; //Debug First direction point
+ MI_VG_Point_t dsdp[MAX_NUMBER]; //Debug Second direction point
+} MI_VgDebug_t;
+
+typedef void* MI_VG_HANDLE;
+
+MI_VG_HANDLE MI_VG_Init(MI_VgSet_t* vg_user_info, uint16_t width, uint16_t height);
+
+MI_VG_RET MI_VG_Uninit(MI_VG_HANDLE vg_handle);
+
+MI_VG_RET MI_VG_Reset(MI_VG_HANDLE vg_handle);
+
+MI_VG_RET MI_VG_SetFunction(MI_VgSet_t* vg_user_info, uint8_t function_state);
+
+MI_VG_RET MI_VG_SetObjSizeThd(MI_VgSet_t* vg_user_info, float size_thd);
+
+MI_VG_RET MI_VG_GetObjSizeThd(MI_VgSet_t* vg_user_info, float* size_thd);
+
+MI_VG_RET MI_VG_SetScene(MI_VgSet_t* vg_user_info, int8_t scene);
+
+MI_VG_RET MI_VG_GetScene(MI_VgSet_t* vg_user_info, int8_t* scene);
+
+MI_VG_RET MI_VG_SetLineNumber(MI_VgSet_t* vg_user_info, uint16_t lineno);
+
+MI_VG_RET MI_VG_GetLineNumber(MI_VgSet_t* vg_user_info, uint16_t* lineno);
+
+MI_VG_RET MI_VG_SetLineAndDir(MI_VgSet_t* vg_user_info, MI_VgLine_t* line_coordinate, uint16_t lineno);
+
+MI_VG_RET MI_VG_GetLineAndDir(MI_VgSet_t* vg_user_info, MI_VgLine_t* line_coordinate, uint16_t lineno);
+
+MI_VG_RET MI_VG_SetRegionAndDir(MI_VgSet_t* vg_user_info, MI_VgRegion_t* region_coordinate);
+
+MI_VG_RET MI_VG_SetDetectThd(MI_VG_HANDLE vg_handle, MI_VgDetectThd* detect_parms);
+
+MI_VG_RET MI_VG_Run(MI_VG_HANDLE vg_handle, uint8_t* _ucMask);
+
+MI_VG_RET MI_VG_GetResult(MI_VG_HANDLE vg_handle, MI_VgResult_t *cross_alarm);
+
+MI_VG_RET MI_VG_GetDebugInfo(MI_VG_HANDLE vg_handle, MI_VgDebug_t *debug_info);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MI_VG_H_ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vif.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vif.h
new file mode 100644
index 00000000..02c5640a
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vif.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VIF_H_
+#define _MI_VIF_H_
+
+
+#include "mi_vif_datatype.h"
+
+#define VIF_MAJOR_VERSION 2
+#define VIF_SUB_VERSION 3
+#define MACRO_TO_STR(macro) #macro
+#define VIF_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_vif_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_vif_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_vif_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_VIF_API_VERSION VIF_VERSION_STR(VIF_MAJOR_VERSION,VIF_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_VIF_SetDevAttr(MI_VIF_DEV u32VifDev, MI_VIF_DevAttr_t *pstDevAttr);
+MI_S32 MI_VIF_GetDevAttr(MI_VIF_DEV u32VifDev, MI_VIF_DevAttr_t *pstDevAttr);
+MI_S32 MI_VIF_EnableDev(MI_VIF_DEV u32VifDev);
+MI_S32 MI_VIF_DisableDev(MI_VIF_DEV u32VifDev);
+MI_S32 MI_VIF_SetChnPortAttr(MI_VIF_CHN u32VifChn, MI_VIF_PORT u32ChnPort, MI_VIF_ChnPortAttr_t *pstAttr);
+MI_S32 MI_VIF_GetChnPortAttr(MI_VIF_CHN u32VifChn, MI_VIF_PORT u32ChnPort, MI_VIF_ChnPortAttr_t *pstAttr);
+MI_S32 MI_VIF_EnableChnPort(MI_VIF_CHN u32VifChn, MI_VIF_PORT u32ChnPort);
+MI_S32 MI_VIF_DisableChnPort(MI_VIF_CHN u32VifChn, MI_VIF_PORT u32ChnPort);
+MI_S32 MI_VIF_Query(MI_VIF_CHN u32VifChn, MI_VIF_PORT u32ChnPort, MI_VIF_ChnPortStat_t *pstStat);
+MI_S32 MI_VIF_SetDev2SnrPadMux(MI_VIF_Dev2SnrPadMuxCfg_t *pstVifDevMap, MI_U8 u8Length);
+MI_S32 MI_VIF_InitDev(MI_VIF_InitParam_t *pstInitParam);
+MI_S32 MI_VIF_DeInitDev(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VIF_H_
+
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vif_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vif_datatype.h
new file mode 100644
index 00000000..ff6ff657
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vif_datatype.h
@@ -0,0 +1,302 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VIF_DATATYPE_H_
+#define _MI_VIF_DATATYPE_H_
+
+#include "mi_sys_datatype.h"
+
+#pragma pack(push)
+#pragma pack(4)
+
+typedef enum
+{
+ E_MI_VIF_ERR_INVALID_PORTID = E_MI_ERR_MAX + 1,
+ E_MI_VIF_ERR_FAILED_DEVNOTENABLE, /* device not enable*/
+ E_MI_VIF_ERR_FAILED_DEVNOTDISABLE, /* device not disable*/
+ E_MI_VIF_ERR_FAILED_PORTNOTENABLE, /* port not enable*/
+ E_MI_VIF_ERR_FAILED_PORTNOTDISABLE, /* port not disable*/
+ E_MI_VIF_ERR_CFG_TIMEOUT, /* config timeout*/
+ E_MI_VIF_ERR_NORM_UNMATCH, /* video norm of ADC and VIU is unmatch*/
+ E_MI_VIF_ERR_INVALID_WAYID, /* invlalid way ID */
+ E_MI_VIF_ERR_INVALID_PHYCHNID, /* invalid phychn id*/
+ E_MI_VIF_ERR_FAILED_NOTBIND, /* device or channel not bind */
+ E_MI_VIF_ERR_FAILED_BINDED, /* device or channel not unbind */
+} MI_VIF_ErrCode_e;
+
+#define MI_VIF_SUCCESS (0)
+#define MI_VIF_FAIL (1)
+
+#define MI_ERR_VIF_INVALID_DEVID MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID)
+#define MI_ERR_VIF_INVALID_CHNID MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_CHNID)
+#define MI_ERR_VIF_INVALID_PARA MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM)
+#define MI_ERR_VIF_INVALID_NULL_PTR MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR)
+#define MI_ERR_VIF_FAILED_NOTCONFIG MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG)
+#define MI_ERR_VIF_NOT_SUPPORT MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT)
+#define MI_ERR_VIF_NOT_PERM MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_PERM)
+#define MI_ERR_VIF_NOMEM MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOMEM)
+#define MI_ERR_VIF_BUF_EMPTY MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_EMPTY)
+#define MI_ERR_VIF_BUF_FULL MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUF_FULL)
+#define MI_ERR_VIF_SYS_NOTREADY MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_SYS_NOTREADY)
+
+#define MI_ERR_VIF_BUSY MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BUSY)
+#define MI_ERR_VIF_INVALID_PORTID MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_INVALID_PORTID)/* 0xA0108040*/
+#define MI_ERR_VIF_FAILED_DEVNOTENABLE MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_FAILED_DEVNOTENABLE)/* 0xA0108040*/
+#define MI_ERR_VIF_FAILED_DEVNOTDISABLE MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_FAILED_DEVNOTDISABLE)/* 0xA0108041*/
+#define MI_ERR_VIF_FAILED_PORTNOTENABLE MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_FAILED_PORTNOTENABLE)/* 0xA0108042*/
+#define MI_ERR_VIF_FAILED_PORTNOTDISABLE MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_FAILED_PORTNOTDISABLE)/* 0xA0108042*/
+#define MI_ERR_VIF_CFG_TIMEOUT MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_CFG_TIMEOUT)/* 0xA0108043*/
+#define MI_ERR_VIF_NORM_UNMATCH MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_NORM_UNMATCH)/* 0xA0108044*/
+#define MI_ERR_VIF_INVALID_WAYID MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_INVALID_WAYID)/* 0xA0108045*/
+#define MI_ERR_VIF_INVALID_PHYCHNID MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_INVALID_PHYCHNID)/* 0xA0108046*/
+#define MI_ERR_VIF_FAILED_NOTBIND MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_FAILED_NOTBIND)/* 0xA0108047*/
+#define MI_ERR_VIF_FAILED_BINDED MI_DEF_ERR(E_MI_MODULE_ID_VIF, E_MI_ERR_LEVEL_ERROR, E_MI_VIF_ERR_FAILED_BINDED)/* 0xA0108048*/
+
+//typedef signed int MI_VIF_DEV;
+typedef signed int MI_VIF_CHN;
+typedef signed int MI_VIF_PORT;
+typedef signed int MI_VIF_WAY;
+
+/* interface mode of video input */
+/*
+BT 601: 16位数据传输；21芯；Y、U、V信号同时传输。并行数据，行场同步有单独输出;
+BT 656: 8位数据传输； 9芯，不需要同步信号；串行视频传输；传输速率是601的2倍；
+ 先传Y，后传UV。656输出的是串行数据，行场同步信号嵌入在数据流中
+
+656只是数据传输接口而已，可以说是作为601的一个传输方式。
+简单的说ITU-R BT.601是"演播室数字电视编码参数"标准,而ITU-R BT.656 则是ITU-R BT.601附件A中的数字接口标准,
+用于主要数字视频设备(包括芯 片)之间采用27Mhz/s并口或243Mb/s串行接口的数字传输接口标准.
+
+601号建议
+
+ 它规定了取样频率与取样结构。
+ 例如：在4：2：2等级的编码中，规定亮度信号和色差信号的取样频率分别为13.5MHZ和6.75MHZ ,
+ 取样结构为正交结构,即按行、场、帧重复,每行中的R-Y和B-Y取样与奇次(1,3,5……)Y的取样同位置，
+ 即取样结构是固定的，取样点在电视屏幕上的相对位置不变。
+ 它规定了编码方式。
+ 对亮度信号和两个色差信号进行线性PCM编码，每个取样点取8比特量化。
+ 同时，规定在数字编码时，不使用A/D转换的整个动态范围，只给亮度信号分配220个量化级， 黑电平对应于量化级16，白电平对应于量化级235。
+ 为每个色差信号分配224个量化级，色差信号的零电平对应于量化级128。
+
+以4：2：2编码标准为例，其比特流为：13.5×8+6.75×8×2 = 216Mb/S。
+若采用4：4：4编码方式，即对复合信号直接编码，其抽样频率取为13.3×8=106.4 Mb/S
+*/
+
+typedef enum
+{
+ /*
+ 输入数据的协议符合标准BT.656 协议，端口 数据输入模式为亮度色度复合模式，分量模 式为单分量。
+ */
+ E_MI_VIF_MODE_BT656,
+ /*
+ 如果是Sensor，则为VI_MODE_DIGITAL_CAMERA 输入数据的协议为Digital camera 协议，
+ 端口 数据输入模式为亮度色度复合模式，分量模 式为单分量
+ */
+ E_MI_VIF_MODE_DIGITAL_CAMERA,
+ /*
+ BT.1120 协议（BT.656+双分量），端口数据输入模式为亮度色度分离模式，分量模式为双分量。
+ */
+ E_MI_VIF_MODE_BT1120_STANDARD,
+ /*
+ BT.1120 interleave 模式，端口数据输入模式为亮度色度分离模式，分量模式为双分量。
+ */
+ E_MI_VIF_MODE_BT1120_INTERLEAVED,
+ E_MI_VIF_MODE_MIPI,
+ E_MI_VIF_MODE_MAX
+} MI_VIF_IntfMode_e;
+
+typedef enum
+{
+ /* BT656 multiple ch mode */
+ E_MI_VIF_WORK_MODE_1MULTIPLEX,
+ E_MI_VIF_WORK_MODE_2MULTIPLEX,
+ E_MI_VIF_WORK_MODE_4MULTIPLEX,
+
+ /* RGB mode for MIPI/Parallel sensor */
+ E_MI_VIF_WORK_MODE_RGB_REALTIME,
+ E_MI_VIF_WORK_MODE_RGB_FRAMEMODE,
+ E_MI_VIF_WORK_MODE_MAX
+} MI_VIF_WorkMode_e;
+
+
+typedef enum
+{
+ E_MI_VIF_FRAMERATE_FULL,
+ E_MI_VIF_FRAMERATE_HALF,
+ E_MI_VIF_FRAMERATE_QUARTER,
+ E_MI_VIF_FRAMERATE_OCTANT,
+ E_MI_VIF_FRAMERATE_THREE_QUARTERS,
+ E_MI_VIF_FRAMERATE_MAX
+} MI_VIF_FrameRate_e;
+
+/*
+输入数据顺序（仅支持 YUV 格式）
+
+VI_INPUT_DATA_VUVU YUV 数据通过分离模式输入时，C 分量的输入排列顺序为 VUVU。
+VI_INPUT_DATA_UVUV YUV 数据通过分离模式输入时，C 分量的输入排列顺序为 UVUV。
+VI_INPUT_DATA_UYVY YUV 数据通过复合模式输入时，顺序为UYVY。
+VI_INPUT_DATA_VYUY YUV 数据通过复合模式输入时，顺序为VYUY。
+VI_INPUT_DATA_YUYV YUV 数据通过复合模式输入时，顺序为YUYV。
+VI_INPUT_DATA_YVYU YUV 数据通过复合模式输入时，顺序为YVYU。
+*/
+typedef enum
+{
+ /*The input sequence of the second component(only contains u and v) in BT.1120 mode */
+ E_MI_VIF_INPUT_DATA_VUVU = 0,
+ E_MI_VIF_INPUT_DATA_UVUV,
+
+ /* The input sequence for yuv */
+ E_MI_VIF_INPUT_DATA_UYVY = 0,
+ E_MI_VIF_INPUT_DATA_VYUY,
+ E_MI_VIF_INPUT_DATA_YUYV,
+ E_MI_VIF_INPUT_DATA_YVYU,
+ E_MI_VIF_INPUT_DATA_MAX
+} MI_VIF_DataYuvSeq_e;
+
+
+typedef enum
+{
+ // 时钟单沿模式，且VI 设备在上升沿采样
+ E_MI_VIF_CLK_EDGE_SINGLE_UP,
+ // 时钟单沿模式，且VI 设备在下降沿采样
+ E_MI_VIF_CLK_EDGE_SINGLE_DOWN,
+ // 前端送过来双沿数据时，VI 进行双沿采样
+ E_MI_VIF_CLK_EDGE_DOUBLE,
+ E_MI_VIF_CLK_EDGE_MAX
+} MI_VIF_ClkEdge_e;
+
+
+typedef enum
+{
+ E_MI_VIF_BITORDER_NORMAL = 0,
+ E_MI_VIF_BITORDER_REVERSED
+} MI_VIF_BitOrder_e;
+
+typedef enum
+{
+ E_MI_VIF_HDR_TYPE_OFF,
+ E_MI_VIF_HDR_TYPE_VC, //virtual channel mode HDR,vc0->long, vc1->short
+ E_MI_VIF_HDR_TYPE_DOL,
+ E_MI_VIF_HDR_TYPE_EMBEDDED, //compressed HDR mode
+ E_MI_VIF_HDR_TYPE_LI, //Line interlace HDR
+ E_MI_VIF_HDR_TYPE_MAX
+} MI_VIF_HDRType_e;
+
+typedef enum
+{
+ E_MI_VIF_PIN_POLAR_POS,
+ E_MI_VIF_PIN_POLAR_NEG
+} MI_VIF_Polar_e;
+
+typedef struct MI_VIF_SyncAttr_s
+{
+ MI_VIF_Polar_e eVsyncPolarity;
+ MI_VIF_Polar_e eHsyncPolarity;
+ MI_VIF_Polar_e ePclkPolarity;
+ MI_U32 VsyncDelay;
+ MI_U32 HsyncDelay;
+ MI_U32 PclkDelay;
+} MI_VIF_SyncAttr_t;
+
+typedef struct MI_VIF_DevAttr_s
+{
+ MI_VIF_IntfMode_e eIntfMode;
+ MI_VIF_WorkMode_e eWorkMode;
+ MI_VIF_HDRType_e eHDRType;
+ MI_VIF_ClkEdge_e eClkEdge; //BT656
+ MI_VIF_DataYuvSeq_e eDataSeq; //mipi
+ MI_VIF_BitOrder_e eBitOrder;//adjust bit order layout BT656
+ MI_VIF_SyncAttr_t stSyncAttr;//parallel, BT656
+} MI_VIF_DevAttr_t;
+
+typedef struct MI_VIF_ChnPortAttr_s
+{
+ /*
+ 采集区域起始坐标用于配置需要采集的矩形图像相对于原始图像起始点的位置。
+ stCapRect 的宽与高为静态属性， 其他项为动态属性；无次属性
+ stCapRect 是针对原始图像进行裁剪；
+ stCapRect 中 s32X 和u32Width 必须 2 对齐；
+ s32Y 和u32Height 逐行采集时必须 2 对齐
+ s32Y 和u32Height 隔行采集时必须 4 对齐
+ */
+ MI_SYS_WindowRect_t stCapRect;
+
+ // stDestSize 的等于stCapRect,或者宽高都减少1/2
+ MI_SYS_WindowSize_t stDestSize;
+
+ /*
+ 抽场选择用于在原始图像为隔行输入时，用户可选择仅捕获其中的一场
+ 为防止图像上下抖动现象，仅支持捕获两场或底场
+ */
+ MI_SYS_FieldType_e eCapSel;
+
+ // 扫描模式用于在原始图像为隔行/逐行输入
+ MI_SYS_FrameScanMode_e eScanMode;
+
+ // 输出格式 enPixFormat 可以动态改变, 支持 semi-planar4:2:2 和 semi-planar4:2:0
+ MI_SYS_PixelFormat_e ePixFormat;
+
+ MI_VIF_FrameRate_e eFrameRate;
+
+ // 如果设置 E_MI_VIF_WORK_MODE_RGB_FRAMEMODE，
+ // u32FrameModeLineCount表示VIF通知下一级的时机
+ MI_U32 u32FrameModeLineCount;
+} MI_VIF_ChnPortAttr_t;
+
+typedef struct MI_VIF_ChnPortStat_s
+{
+ // 通道是否使能
+ MI_BOOL bEnable;
+ // 中断计数
+ // can not support ?
+ MI_U32 u32IntCnt;
+ // 每10 秒的平均帧率，该值不一定精确
+ MI_U32 u32FrameRate;
+ // 中断丢失计数,该结构体的中断丢失计数一直在增加，说明 VI 工作出现异常
+ // can not support?
+ MI_U32 u32LostInt;
+ // 获取VB 失败计数
+ MI_U32 u32VbFail;
+ // 图像宽度
+ MI_U32 u32PicWidth;
+ // 图像高度
+ MI_U32 u32PicHeight;
+} MI_VIF_ChnPortStat_t;
+
+typedef enum
+{
+ E_MI_VIF_SNRPAD_ID_0 = 0,
+ E_MI_VIF_SNRPAD_ID_1 = 1,
+ E_MI_VIF_SNRPAD_ID_2 = 2,
+ E_MI_VIF_SNRPAD_ID_3 = 3,
+ E_MI_VIF_SNRPAD_ID_MAX,
+ E_MI_VIF_SNRPAD_ID_NA = 0xFF,
+}MI_VIF_SNRPad_e;
+
+typedef struct MI_VIF_VIFDev2SnrPadMuxConf_s
+{
+ MI_VIF_SNRPad_e eSensorPadID; //sensor Pad id
+ MI_U32 u32PlaneID; //For HDR,0 is short exposure, 1 is long exposure
+} MI_VIF_Dev2SnrPadMuxCfg_t;
+
+typedef struct MI_VIF_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_VIF_InitParam_t;
+
+#pragma pack(pop)
+
+#endif //_MI_VIF_DATATYPE_H_
+
+
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vpe.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vpe.h
new file mode 100644
index 00000000..efd69428
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vpe.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VPE_H_
+#define _MI_VPE_H_
+
+#include "mi_vpe_datatype.h"
+
+#define VPE_MAJOR_VERSION 2
+#define VPE_SUB_VERSION 12
+#define MACRO_TO_STR(macro) #macro
+#define VPE_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_vpe_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_vpe_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_vpe_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_VPE_API_VERSION VPE_VERSION_STR(VPE_MAJOR_VERSION,VPE_SUB_VERSION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MI_S32 MI_VPE_CreateChannel(MI_VPE_CHANNEL VpeCh, MI_VPE_ChannelAttr_t *pstVpeChAttr);
+MI_S32 MI_VPE_DestroyChannel(MI_VPE_CHANNEL VpeCh);
+MI_S32 MI_VPE_GetChannelAttr(MI_VPE_CHANNEL VpeCh, MI_VPE_ChannelAttr_t *pstVpeChAttr);
+MI_S32 MI_VPE_SetChannelAttr(MI_VPE_CHANNEL VpeCh, MI_VPE_ChannelAttr_t *pstVpeChAttr);
+
+MI_S32 MI_VPE_StartChannel(MI_VPE_CHANNEL VpeCh);
+MI_S32 MI_VPE_StopChannel(MI_VPE_CHANNEL VpeCh);
+
+MI_S32 MI_VPE_SetChannelParam(MI_VPE_CHANNEL VpeCh, MI_VPE_ChannelPara_t *pstVpeParam);
+MI_S32 MI_VPE_GetChannelParam(MI_VPE_CHANNEL VpeCh, MI_VPE_ChannelPara_t *pstVpeParam);
+
+MI_S32 MI_VPE_SetChannelCrop(MI_VPE_CHANNEL VpeCh, MI_SYS_WindowRect_t *pstCropInfo);
+MI_S32 MI_VPE_GetChannelCrop(MI_VPE_CHANNEL VpeCh, MI_SYS_WindowRect_t *pstCropInfo);
+MI_S32 MI_VPE_GetChannelRegionLuma(MI_VPE_CHANNEL VpeCh, MI_VPE_RegionInfo_t *pstRegionInfo, MI_U32 *pu32LumaData,MI_S32 s32MilliSec);
+MI_S32 MI_VPE_SetChannelRotation(MI_VPE_CHANNEL VpeCh, MI_SYS_Rotate_e eType);
+MI_S32 MI_VPE_GetChannelRotation(MI_VPE_CHANNEL VpeCh, MI_SYS_Rotate_e *pType);
+
+MI_S32 MI_VPE_EnablePort(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort);
+MI_S32 MI_VPE_DisablePort(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort);
+MI_S32 MI_VPE_SetPortMode(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort, MI_VPE_PortMode_t *pstVpeMode);
+MI_S32 MI_VPE_GetPortMode(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort, MI_VPE_PortMode_t *pstVpeMode);
+MI_S32 MI_VPE_SetPortCrop(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort, MI_SYS_WindowRect_t *pstOutCropInfo);
+MI_S32 MI_VPE_GetPortCrop(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort, MI_SYS_WindowRect_t *pstOutCropInfo);
+
+MI_S32 MI_VPE_SetPortShowPosition(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort, MI_SYS_WindowRect_t *pstPortPositionInfo);
+MI_S32 MI_VPE_GetPortShowPosition(MI_VPE_CHANNEL VpeCh, MI_VPE_PORT VpePort, MI_SYS_WindowRect_t *pstPortPositionInfo);
+
+MI_S32 MI_VPE_SkipFrame(MI_VPE_CHANNEL VpeCh, MI_U32 u32FrameNum);
+
+MI_S32 MI_VPE_LDCBegViewConfig(MI_VPE_CHANNEL VpeCh);
+MI_S32 MI_VPE_LDCEndViewConfig(MI_VPE_CHANNEL VpeCh);
+MI_S32 MI_VPE_LDCSetViewConfig(MI_VPE_CHANNEL VpeCh, void *pConfigAddr, MI_U32 u32ConfigSize);
+
+MI_S32 MI_VPE_Alloc_IspDataBuf(MI_U32 u32Size,void **pUserVirAddr);
+MI_S32 MI_VPE_Free_IspDataBuf(void *pUserBuf);
+
+
+MI_S32 MI_VPE_InitDev(MI_VPE_InitParam_t *pstInitParam);
+MI_S32 MI_VPE_DeInitDev(void);
+
+MI_S32 MI_VPE_CallBackTask_Register(MI_VPE_CallBackParam_t *pstCallBackParam);
+MI_S32 MI_VPE_CallBackTask_Unregister(MI_VPE_CallBackParam_t *pstCallBackParam);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif///_MI_VPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vpe_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vpe_datatype.h
new file mode 100644
index 00000000..22f2be82
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_vpe_datatype.h
@@ -0,0 +1,210 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+#ifndef _MI_VPE_DATATYPE_H_
+#define _MI_VPE_DATATYPE_H_
+#include "mi_sys_datatype.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define MI_VPE_OK (0)
+#define MI_ERR_VPE_INVALID_CHNID (0xA0078001) //The VPE channel ID is invalid.
+#define MI_ERR_VPE_INVALID_PORTID (0xA0078002) //The VPE outport ID is invalid.
+#define MI_ERR_VPE_ILLEGAL_PARAM (0xA0078003) //The VPE parameter is invalid.
+#define MI_ERR_VPE_EXIST (0xA0078004) //A VPE channel is created.
+#define MI_ERR_VPE_UNEXIST (0xA0078005) //No VPE channel is created.
+#define MI_ERR_VPE_NULL_PTR (0xA0078006) //The pointer of the input parameter is null.
+#define MI_ERR_VPE_NOT_SUPPORT (0xA0078008) //The operation is not supported.
+#define MI_ERR_VPE_NOT_PERM (0xA0078009) //The operation is forbidden.
+#define MI_ERR_VPE_NOMEM (0xA007800C) //The memory fails to be allocated.
+#define MI_ERR_VPE_NOBUF (0xA007800D) //The buffer pool fails to be allocated.
+#define MI_ERR_VPE_BUF_EMPTY (0xA007800E) //The picture queue is empty.
+#define MI_ERR_VPE_NOTREADY (0xA0078010) //The VPE is not initialized.
+#define MI_ERR_VPE_BUSY (0xA0078012) //The VPE is busy.
+
+
+typedef MI_U32 MI_VPE_CHANNEL;
+typedef MI_U32 MI_VPE_PORT;
+
+typedef enum
+{
+ E_MI_VPE_RUN_INVALID = 0x00,
+ E_MI_VPE_RUN_DVR_MODE = 0x01,
+ E_MI_VPE_RUN_CAM_TOP_MODE = 0x02,
+ E_MI_VPE_RUN_CAM_BOTTOM_MODE = 0x04,
+ E_MI_VPE_RUN_CAM_MODE = E_MI_VPE_RUN_CAM_TOP_MODE|E_MI_VPE_RUN_CAM_BOTTOM_MODE,
+ E_MI_VPE_RUN_REALTIME_TOP_MODE = 0x08,
+ E_MI_VPE_RUN_REALTIME_BOTTOM_MODE = 0x10,
+ E_MI_VPE_RUN_REALTIME_MODE = E_MI_VPE_RUN_REALTIME_TOP_MODE | E_MI_VPE_RUN_REALTIME_BOTTOM_MODE,
+ E_MI_VPE_RUNNING_MODE_MAX,
+} MI_VPE_RunningMode_e;
+
+typedef enum
+{
+ E_MI_VPE_HDR_TYPE_OFF,
+ E_MI_VPE_HDR_TYPE_VC, //virtual channel mode HDR,vc0->long, vc1->short
+ E_MI_VPE_HDR_TYPE_DOL,
+ E_MI_VPE_HDR_TYPE_EMBEDDED, //compressed HDR mode
+ E_MI_VPE_HDR_TYPE_LI, //Line interlace HDR
+ E_MI_VPE_HDR_TYPE_MAX
+} MI_VPE_HDRType_e;
+
+typedef enum
+{
+ E_MI_VPE_SENSOR_INVALID = 0,
+ E_MI_VPE_SENSOR0,
+ E_MI_VPE_SENSOR1,
+ E_MI_VPE_SENSOR2,
+ E_MI_VPE_SENSOR3,
+ E_MI_VPE_SENSOR_MAX
+}MI_VPE_SensorChannel_e;
+
+typedef enum
+{
+ E_MI_VPE_3DNR_LEVEL_OFF,
+ E_MI_VPE_3DNR_LEVEL1,
+ E_MI_VPE_3DNR_LEVEL2,
+ E_MI_VPE_3DNR_LEVEL3,
+ E_MI_VPE_3DNR_LEVEL4,
+ E_MI_VPE_3DNR_LEVEL5,
+ E_MI_VPE_3DNR_LEVEL6,
+ E_MI_VPE_3DNR_LEVEL7,
+ E_MI_VPE_3DNR_LEVEL_NUM
+}MI_VPE_3DNR_Level_e;
+
+typedef enum
+{
+ E_MI_VPE_ZOOM_LDC_NULL,
+ E_MI_VPE_ZOOM_LDC_PORT0 = 0X01,
+ E_MI_VPE_ZOOM_LDC_PORT1 = 0X02,
+ E_MI_VPE_ZOOM_LDC_PORT2 = 0X04,
+ E_MI_VPE_ZOOM_LDC_MAX = E_MI_VPE_ZOOM_LDC_PORT0|
+ E_MI_VPE_ZOOM_LDC_PORT1|E_MI_VPE_ZOOM_LDC_PORT2,
+}MI_VPE_ChnPortMode_e;
+
+typedef struct MI_VPE_IspApiHeader_s
+{
+ MI_U32 u32HeadSize; //Size of MIIspApiHeader_t
+ MI_U32 u32DataLen; //Data length;
+ MI_U32 u32CtrlID; //Function ID
+ MI_U32 u32Channel; //Isp channel number
+ MI_S32 s32Ret; //Isp api retuen value
+} MI_VPE_IspApiHeader_t;
+
+typedef struct MI_VPE_IspInitPara_s
+{
+ MI_U32 u32Revision;
+ MI_U32 u32Size;
+ MI_U8 u8Data[64];
+}MI_VPE_IspInitPara_t;
+
+typedef struct MI_VPE_ChannelAttr_s
+{
+ MI_U16 u16MaxW;
+ MI_U16 u16MaxH;
+ MI_SYS_PixelFormat_e ePixFmt;
+ MI_VPE_HDRType_e eHDRType;
+ MI_VPE_SensorChannel_e eSensorBindId;
+
+ MI_BOOL bNrEn;
+ MI_BOOL bEdgeEn;
+ MI_BOOL bEsEn;
+ MI_BOOL bContrastEn;
+ MI_BOOL bUvInvert;
+ MI_BOOL bRotation;
+ MI_VPE_RunningMode_e eRunningMode;
+ MI_VPE_IspInitPara_t tIspInitPara;
+ MI_BOOL bEnLdc; // true port3 for ldc or for Isp(skip pass2)
+ MI_U32 u32ChnPortMode;
+}MI_VPE_ChannelAttr_t;
+
+typedef struct MI_VPE_PqParam_s
+{
+ MI_U8 u8NrcSfStr; //0 ~ 255;
+ MI_U8 u8NrcTfStr; //0 ~ 255
+ MI_U8 u8NrySfStr; //0 ~ 255
+ MI_U8 u8NryTfStr; //0 ~ 255
+ MI_U8 u8NryBlendMotionTh; //0 ~ 15
+ MI_U8 u8NryBlendStillTh; //0 ~ 15
+ MI_U8 u8NryBlendMotionWei; //0 ~ 31
+ MI_U8 u8NryBlendOtherWei; //0 ~ 31
+ MI_U8 u8NryBlendStillWei; //0 ~ 31
+ MI_U8 u8EdgeGain[6];//0~255
+ MI_U8 u8Contrast;//0~255
+} MI_VPE_PqParam_t;
+
+typedef struct MI_VPE_ChannelPara_s
+{
+ MI_VPE_PqParam_t stPqParam; // only dvr use
+ MI_VPE_HDRType_e eHDRType;
+ MI_VPE_3DNR_Level_e e3DNRLevel;
+ MI_BOOL bMirror;
+ MI_BOOL bFlip;
+ MI_BOOL bWdrEn; //Wdr on/off not use
+ MI_BOOL bEnLdc;
+} MI_VPE_ChannelPara_t;
+
+typedef struct MI_VPE_RegionInfo_s
+{
+ MI_SYS_WindowRect_t *pstWinRect; // region attribute
+ MI_U32 u32RegionNum; // count of the region
+} MI_VPE_RegionInfo_t;
+
+/*Define attributes of Vpe port's work mode*/
+typedef struct MI_VPE_PortMode_s
+{
+ MI_U16 u16Width; // Width of target image
+ MI_U16 u16Height; // Height of target image
+ MI_BOOL bMirror;
+ MI_BOOL bFlip;
+ MI_SYS_PixelFormat_e ePixelFormat; // Pixel format of target image
+ MI_SYS_CompressMode_e eCompressMode; // Compression mode of the output
+}MI_VPE_PortMode_t;
+
+typedef struct MI_VPE_InitParam_s
+{
+ MI_U32 u32DevId;
+ MI_U8 *u8Data;
+} MI_VPE_InitParam_t;
+
+typedef MI_S32 (*MI_VPE_CALLBK_FUNC)(MI_U64 u64Data);
+
+typedef enum
+{
+ E_MI_VPE_CALLBACK_ISR,
+ E_MI_VPE_CALLBACK_MAX,
+} MI_VPE_CallBackMode_e;
+
+typedef enum
+{
+ E_MI_VPE_IRQ_ISPVSYNC,
+ E_MI_VPE_IRQ_ISPFRAMEDONE,
+ E_MI_VPE_IRQ_MAX,
+} MI_VPE_IrqType_e;
+
+typedef struct MI_VPE_CallBackParam_s
+{
+ MI_VPE_CallBackMode_e eCallBackMode;
+ MI_VPE_IrqType_e eIrqType;
+ MI_VPE_CALLBK_FUNC pfnCallBackFunc;
+ MI_U64 u64Data;
+} MI_VPE_CallBackParam_t;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif///_MI_VPE_DATATYPE_H_
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_wlan.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_wlan.h
new file mode 100644
index 00000000..2d420492
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_wlan.h
@@ -0,0 +1,421 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef _MI_WLAN_H_
+#define _MI_WLAN_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mi_wlan_datatype.h"
+
+#define WLAN_MAJOR_VERSION 1
+#define WLAN_SUB_VERSION 0
+#define MACRO_TO_STR(macro) #macro
+#define WLAN_VERSION_STR(major_version,sub_version) ({char *tmp = sub_version/100 ? \
+ "mi_wlan_version_" MACRO_TO_STR(major_version)"." MACRO_TO_STR(sub_version) : sub_version/10 ? \
+ "mi_wlan_version_" MACRO_TO_STR(major_version)".0" MACRO_TO_STR(sub_version) : \
+ "mi_wlan_version_" MACRO_TO_STR(major_version)".00" MACRO_TO_STR(sub_version);tmp;})
+#define MI_WLAN_API_VERSION WLAN_VERSION_STR(DIVP_MAJOR_VERSION,DIVP_SUB_VERSION)
+
+
+
+
+#define MI_WLAN_ERR_FAIL (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_FAILED))
+#define MI_WLAN_ERR_INVALID_DEVID (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INVALID_DEVID))
+#define MI_WLAN_ERR_ILLEGAL_PARAM (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_ILLEGAL_PARAM))
+#define MI_WLAN_ERR_NOT_SUPPORT (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_SUPPORT))
+#define MI_WLAN_ERR_MOD_INITED (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INITED))
+#define MI_WLAN_ERR_MOD_NOT_INIT (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_INIT))
+#define MI_WLAN_ERR_NOT_CONFIG (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NOT_CONFIG))
+#define MI_WLAN_ERR_INVAL_HANDLE (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_BADADDR))
+#define MI_WLAN_ERR_NULL_PTR (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_NULL_PTR))
+#define MI_WLAN_ERR_INITED (MI_DEF_ERR( E_MI_MODULE_ID_WLAN, E_MI_ERR_LEVEL_ERROR, E_MI_ERR_INITED))
+
+/// WLAN max MAC len
+#define MI_WLAN_MAX_MAC_LEN 32
+/// WLAN max SSID len
+#define MI_WLAN_MAX_SSID_LEN 128
+/// WLAN max password len
+#define MI_WLAN_MAX_PASSWD_LEN 40
+/// WLAN max AP number
+#define MI_WLAN_MAX_APINFO_NUM 64
+/// WLAN max path len
+#define MI_WLAN_MAX_FOLDERPATH_LEN 256
+/// WLAN interface len
+#define MI_MAX_INTERFACE_NAME 64
+// WLAN BSSID len
+#define MI_WLAN_BSSID_LEN 48
+// WLAN MAX hosts AP connected
+#define MI_WLAN_MAX_HOSTS 64
+// WLAN MAX host name length
+#define MI_WLAN_MAX_HOST_NAME_LEN 256
+
+#define MI_RESULT MI_S32
+
+// HANDLE indicates certain wifi connection
+typedef MI_S32 WLAN_HANDLE;
+
+
+
+typedef enum
+{
+ /// WLAN module security key off
+ E_MI_WLAN_SECURITY_NONE = 1 << 0,
+ /// WLAN module security key unknow
+ E_MI_WLAN_SECURITY_UNKNOWTYPE = 1 << 1,
+ /// WLAN module security key WEP
+ E_MI_WLAN_SECURITY_WEP = 1 << 2,
+ /// WLAN module security key WPA
+ E_MI_WLAN_SECURITY_WPA = 1 << 3,
+ /// WLAN module security key WPA2
+ E_MI_WLAN_SECURITY_WPA2 = 1 << 4,
+ /// WLAN module max
+ E_MI_WLAN_SECURITY_MAX = 0xff,
+} MI_WLAN_Security_e;
+
+
+typedef enum
+{
+ /// WLAN module encrypt type none
+ E_MI_WLAN_ENCRYPT_NONE = 1 << 0,
+ /// WLAN module encrypt type unknown
+ E_MI_WLAN_ENCRYPT_UNKNOWN = 1 << 1,
+ /// WLAN module encrypt type WEP
+ E_MI_WLAN_ENCRYPT_WEP = 1 << 2,
+ /// WLAN module encrypt type TKIP
+ E_MI_WLAN_ENCRYPT_TKIP = 1 << 3,
+ /// WLAN module encrypt type AES
+ E_MI_WLAN_ENCRYPT_AES = 1 << 4,
+ /// WLAN module max
+ E_MI_WLAN_ENCRYPT_MAX = 0xff,
+} MI_WLAN_Encrypt_e;
+
+
+typedef enum
+{
+ /// WLAN network infrastructure type
+ E_MI_WLAN_NETWORKTYPE_INFRA,
+ /// WLAN network AP type
+ E_MI_WLAN_NETWORKTYPE_AP,
+ /// WLAN network AdHoc type
+ E_MI_WLAN_NETWORKTYPE_ADHOC,
+ /// WLAN network Monitor type
+ E_MI_WLAN_NETWORKTYPE_MONITOR,
+ /// WLAN network mode master
+ E_MI_WLAN_NETWORKTYPE_MASTER,
+ /// WLAN network mode slave
+ E_MI_WLAN_NETWORKTYPE_SLAVE,
+ /// WLAN param max
+ E_MI_WLAN_NETWORKTYPE_MAX
+} MI_WLAN_NetworkType_e;
+
+
+typedef enum
+{
+ /// Authentication Suite PSK
+ E_MI_WLAN_AUTH_SUITE_PSK,
+ /// Authentication Suite unknown
+ E_MI_WLAN_AUTH_SUITE_UNKNOWN,
+ E_MI_WLAN_AUTH_SUITE_MAX
+
+} MI_WLAN_Authentication_Suite_e;
+
+
+
+
+typedef enum
+{
+ /**
+ * WPA_DISCONNECTED - Disconnected state
+ */
+ WPA_DISCONNECTED,
+
+ /**
+ * WPA_INTERFACE_DISABLED - Interface disabled
+ */
+ WPA_INTERFACE_DISABLED,
+
+ /**
+ * WPA_INACTIVE - Inactive state (wpa_supplicant disabled)
+ */
+ WPA_INACTIVE,
+
+ /**
+ * WPA_SCANNING - Scanning for a network
+ */
+ WPA_SCANNING,
+
+ /**
+ * WPA_AUTHENTICATING - Trying to authenticate with a BSS/SSID
+ */
+ WPA_AUTHENTICATING,
+
+ /**
+ * WPA_ASSOCIATING - Trying to associate with a BSS/SSID
+ */
+ WPA_ASSOCIATING,
+
+ /**
+ * WPA_ASSOCIATED - Association completed
+ */
+ WPA_ASSOCIATED,
+
+ /**
+ * WPA_4WAY_HANDSHAKE - WPA 4-Way Key Handshake in progress
+ */
+ WPA_4WAY_HANDSHAKE,
+
+ /**
+ * WPA_GROUP_HANDSHAKE - WPA Group Key Handshake in progress
+ */
+ WPA_GROUP_HANDSHAKE,
+
+ /**
+ * WPA_COMPLETED - All authentication completed
+ */
+ WPA_COMPLETED
+} MI_WLAN_WPAStatus_e;
+
+
+/// WLAN init parameter
+typedef struct MI_WLAN_InitParams_s
+{
+ /// json description file of wifi dongle
+ MI_U8 au8JsonConfFilePath[MI_WLAN_MAX_FOLDERPATH_LEN];
+ /// reserved
+ MI_U64 u64Reserved;
+} MI_WLAN_InitParams_t;
+
+
+/// WLAN open parameter
+typedef struct MI_WLAN_OpenParam_s
+{
+ // WLAN network type
+ MI_WLAN_NetworkType_e eNetworkType;
+ // reserved
+ MI_BOOL bReserved;
+} MI_WLAN_OpenParams_t;
+
+
+/// WLAN connect info
+typedef struct
+{
+ // WLan security mode
+ MI_WLAN_Security_e eSecurity;
+ // WLan SSID
+ MI_U8 au8SSId[MI_WLAN_MAX_SSID_LEN];
+ // WLan password
+ MI_U8 au8Password[MI_WLAN_MAX_PASSWD_LEN];
+ // WLAN connect overtime
+ MI_U32 OverTimeMs;
+} MI_WLAN_ConnectParam_t;
+
+
+typedef struct
+{
+ MI_U8 curLVL;
+ MI_U8 maxLVL;
+ MI_S8 signalSTR;
+} MI_WLAN_Quality_t;
+
+
+typedef struct
+{
+ // WLAN Security mode
+ MI_WLAN_Security_e eSecurity;
+ // WLAN Encryption type
+ MI_WLAN_Encrypt_e eGroupCipher;
+ // WLAN Encryption type
+ MI_WLAN_Encrypt_e ePairCipher;
+ // WLAN authenticationb suite
+ MI_WLAN_Authentication_Suite_e eAuthSuite;
+} MI_WLAN_Cipher_t;
+
+/// WLAN ap info
+typedef struct MI_WLAN_APInfo_s
+{
+ // WLAN CELL ID
+ MI_U16 u16CellId;
+ // WLAN Frequency GHz
+ MI_FLOAT fFrequency;
+ // WLAN Bitrate Mb/s
+ MI_FLOAT fBitRate;
+ // WLAN Quality
+ MI_WLAN_Quality_t stQuality;
+ // WLAN Encryption key on/off
+ MI_BOOL bEncryptKey;
+ // WLAN SSID
+ MI_U8 au8SSId[MI_WLAN_MAX_SSID_LEN];
+ // WLAN Channel
+ MI_U8 u8Channel;
+ // WLAN MAC
+ MI_U8 au8Mac[MI_WLAN_MAX_MAC_LEN];
+ // WLAN Encryption type
+ MI_WLAN_Encrypt_e eEncrypt;
+ // WLAN AP type (Infrastructure / Ad-Hoc)
+ MI_WLAN_NetworkType_e eMode;
+ // WLAN cipher kit
+ MI_WLAN_Cipher_t stCipher[2];
+} MI_WLAN_APInfo_t;
+
+/// WLAN ap info
+typedef struct MI_WLAN_ScanParam_s
+{
+ // WLan set block mode
+ MI_BOOL bBlock; //reserved
+} MI_WLAN_ScanParam_t;
+
+/// WLAN ap info
+typedef struct MI_WLAN_ScanResult_s
+{
+ // WLan AP number
+ MI_WLAN_APInfo_t stAPInfo[MI_WLAN_MAX_APINFO_NUM];
+ MI_U8 u8APNumber;
+} MI_WLAN_ScanResult_t;
+
+
+typedef struct MI_WLAN_Status_sta_s
+{
+ MI_U8 bssid[MI_WLAN_BSSID_LEN];
+ MI_U32 freq;
+ MI_U8 ssid[MI_WLAN_MAX_SSID_LEN];
+ MI_U16 id;
+ MI_WLAN_NetworkType_e mode;
+ MI_WLAN_Cipher_t stCipher;
+ MI_U8 key_mgmt[12];
+ MI_WLAN_WPAStatus_e state;
+ MI_U8 address[MI_WLAN_BSSID_LEN];
+ MI_U8 ip_address[16];
+ MI_U32 channel;
+ MI_U32 RSSI;
+ MI_U8 Bandwidth[8];
+} MI_WLAN_Status_sta_t;
+
+typedef struct MI_WLAN_Status_host_s
+{
+ MI_U8 hostname[MI_WLAN_MAX_HOST_NAME_LEN];
+ MI_U8 ipaddr[16];
+ MI_U8 macaddr[18];
+ MI_U64 connectedtime;
+
+} MI_WLAN_Status_host_t;
+
+typedef struct MI_WLAN_Status_ap_s
+{
+ MI_WLAN_Status_host_t astHosts[MI_WLAN_MAX_HOSTS];
+ MI_U16 u16HostNum;
+} MI_WLAN_Status_ap_t;
+
+typedef union MI_WLAN_Status_s
+{
+ MI_WLAN_Status_sta_t stStaStatus;
+ MI_WLAN_Status_ap_t stApStatus;
+} MI_WLAN_Status_t;
+
+
+//------------------------------------------------------------------------------
+/// @brief setup wlan init parameter , parse wifi config file and internel component
+/// @param[in] *pstInitParams
+/// @return MI_SUCCESS: success.
+/// @return MI_WLAN_ERR_FAIL: init fail.
+/// @return MI_WLAN_ERR_INITED: already inited.
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_Init(MI_WLAN_InitParams_t *pstInitParams);
+
+//------------------------------------------------------------------------------
+/// @brief do wlan deinit , deinit config file parser and internel component
+/// @param none
+/// @return MI_SUCCESS: success.
+/// @return MI_WLAN_ERR_MOD_NOT_INIT: call MI_WLAN_Init first.
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_DeInit(void);
+
+//------------------------------------------------------------------------------
+/// @brief open wifi device
+/// @param[in] *pstParam witch workmode wifi work on
+/// @return MI_SUCCESS: success.
+/// @return MI_WLAN_ERR_MOD_NOT_INIT: call MI_WLAN_Init first
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_Open(MI_WLAN_OpenParams_t *pstParam);
+
+//------------------------------------------------------------------------------
+/// @brief close wifi device
+/// @param none.
+/// @return MI_SUCCESS: success
+/// @return MI_WLAN_ERR_NOT_CONFIG: Process success.
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_Close(void);
+
+//------------------------------------------------------------------------------
+/// @brief connect wifi service
+///
+/// infra mode : connect to certain wifi network
+/// ap mode: start dns hdcp service and wait hosts to connect
+/// @param[in/out] hWLan wlan handle.
+/// (<0)indicates a new connection and will be assigned a sensible ID if connecton set up
+/// (>0)indicates an set up connection
+/// @param[in] *pstConnectParam :.
+/// infra mode:contains nessesarry information to establish a sta connection
+/// @return MI_SUCCESS: connect success.
+/// @return MI_WLAN_ERR_MOD_NOT_INIT: open wlan device first
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_Connect(WLAN_HANDLE *hWLan, MI_WLAN_ConnectParam_t *pstConnectParam);
+
+//------------------------------------------------------------------------------
+/// @brief disconnect wlan
+/// @param[in] hWLan wlan handle.
+/// @return MI_SUCCESS: Process success.
+/// @return MI_WLAN_ERR_NOT_CONFIG: set up a wlan connection first
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_Disconnect(WLAN_HANDLE hWLan);
+
+//------------------------------------------------------------------------------
+/// @brief scan ap info
+/// @param[in] *pstParam info param. //reserved
+/// @param[out] *pstResult result.
+/// @return MI_SUCCESS: success.
+/// @return MI_WLAN_ERR_NOT_CONFIG: open wlan first
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_Scan(MI_WLAN_ScanParam_t *pstParam, MI_WLAN_ScanResult_t *pstResult);
+
+//------------------------------------------------------------------------------
+/// @brief set wlan debug level
+/// @param[in] eDgbLevel debug level.
+/// @return MI_OK: Process success.
+/// @return MI_ERR_FAILED: Process failed
+//------------------------------------------------------------------------------
+//MI_RESULT MI_WLAN_SetDebugLevel(MI_DBG_LEVEL_e eDgbLevel);
+
+//------------------------------------------------------------------------------
+/// @brief get current wlan status
+/// @param[in] the struct to store wlan status
+/// @return MI_SUCCESS: Process success.
+/// @return MI_WLAN_ERR_NOT_CONFIG: open wlan first
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_GetStatus(MI_WLAN_Status_t *status);
+
+//------------------------------------------------------------------------------
+/// @brief get wlan chip version
+/// @return MI_OK: Process success
+/// @return MI_ERR_FAILED: Process failed
+//------------------------------------------------------------------------------
+MI_RESULT MI_WLAN_GetWlanChipVersion(MI_U8 *ChipVersion);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_wlan_datatype.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_wlan_datatype.h
new file mode 100644
index 00000000..e19bf39a
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/mi_wlan_datatype.h
@@ -0,0 +1,73 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+ herein regardless in any format shall remain the sole proprietary of
+ Sigmastar Technology Corp. and be kept in strict confidence
+ (��Sigmastar Confidential Information��) by the recipient.
+ Any unauthorized act including without limitation unauthorized disclosure,
+ copying, use, reproduction, sale, distribution, modification, disassembling,
+ reverse engineering and compiling of the contents of Sigmastar Confidential
+ Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+ rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+#ifndef __MI_WLAN_DATATYPE_H__
+#define __MI_WLAN_DATATYPE_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DBG_LEVEL_FATAL (1)
+#define DBG_LEVEL_ERROR (2)
+#define DBG_LEVEL_WARN (3)
+#define DBG_LEVEL_INFO (4)
+#define DBG_LEVEL_DEBUG (5)
+#define DBG_LEVEL_ENTRY (6)
+
+#define DBG_LEVEL DBG_LEVEL_WARN
+
+#define COLOR_NONE "\033[0m"
+#define COLOR_BLACK "\033[0;30m"
+#define COLOR_BLUE "\033[0;34m"
+#define COLOR_GREEN "\033[0;32m"
+#define COLOR_CYAN "\033[0;36m"
+#define COLOR_RED "\033[0;31m"
+#define COLOR_YELLOW "\033[1;33m"
+#define COLOR_WHITE "\033[1;37m"
+
+#define DBG_ENTRY(fmt, args...) ({do{if(DBG_LEVEL>=DBG_LEVEL_ENTRY){printf(COLOR_CYAN"[WLAN_ENTRY]:%s[%d]: ", __FUNCTION__,__LINE__);printf(fmt, ##args);printf(COLOR_NONE);}}while(0);})
+#define DBG_DEBUG(fmt, args...) ({do{if(DBG_LEVEL>=DBG_LEVEL_DEBUG){printf(COLOR_WHITE"[WLAN_BDG]:%s[%d]: ", __FUNCTION__,__LINE__);printf(fmt, ##args);printf(COLOR_NONE);}}while(0);})
+#define DBG_INFO(fmt, args...) ({do{if(DBG_LEVEL>=DBG_LEVEL_INFO) {printf(COLOR_GREEN"[WLAN_INFO]:%s[%d]: ", __FUNCTION__,__LINE__);printf(fmt, ##args);printf(COLOR_NONE);}}while(0);})
+#define DBG_WRN(fmt, args...) ({do{if(DBG_LEVEL>=DBG_LEVEL_WARN) {printf(COLOR_YELLOW"[WLAN_WRN]:%s[%d]: ", __FUNCTION__,__LINE__);printf(fmt, ##args);printf(COLOR_NONE);}}while(0);})
+#define DBG_ERR(fmt, args...) ({do{if(DBG_LEVEL>=DBG_LEVEL_ERROR){printf(COLOR_RED"[WLAN_ERR]:%s[%d]: ", __FUNCTION__,__LINE__);printf(fmt, ##args);printf(COLOR_NONE);}}while(0);})
+#define DBG_FATAL(fmt, args...) ({do{if(DBG_LEVEL>=DBG_LEVEL_FATAL){printf(COLOR_RED"[WLAN_FATAL]:%s[%d]: ", __FUNCTION__,__LINE__);printf(fmt, ##args);printf(COLOR_NONE);}}while(0);})
+
+
+
+typedef enum
+{
+ E_WLAN_CMD_INIT = 0,
+ E_WLAN_CMD_OPEN,
+ E_WLAN_CMD_CLOSE,
+ E_WLAN_CMD_DEINIT,
+ E_WLAN_CMD_SCAN,
+ E_WLAN_CMD_CONNECT,
+ E_WLAN_CMD_CONNECT_addNetWork,
+ E_WLAN_CMD_DISCONNECT,
+ E_WLAN_CMD_STATUS,
+ E_WLAN_CMD_VERSION,
+ E_WLAN_CMD_CHANNEL,
+ E_WLAN_CMD_NUM
+} E_WLAN_CMD;
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/sigma_isp_general.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/sigma_isp_general.h
new file mode 100644
index 00000000..f048d760
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/sigma_isp_general.h
@@ -0,0 +1,570 @@
+/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
+ All rights reserved.
+
+ Unless otherwise stipulated in writing, any and all information contained
+herein regardless in any format shall remain the sole proprietary of
+Sigmastar Technology Corp. and be kept in strict confidence
+(Sigmastar Confidential Information) by the recipient.
+Any unauthorized act including without limitation unauthorized disclosure,
+copying, use, reproduction, sale, distribution, modification, disassembling,
+reverse engineering and compiling of the contents of Sigmastar Confidential
+Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
+rights to any and all damages, losses, costs and expenses resulting therefrom.
+*/
+
+
+#ifndef MSTAR_ISP_GENERAL_H_
+#define MSTAR_ISP_GENERAL_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef void* ISP_DBGBUF_HANDLE;
+
+//#include <isp_types.h>
+/// data type unsigned char, data length 1 byte
+typedef unsigned char MS_U8; // 1 byte
+/// data type unsigned short, data length 2 byte
+typedef unsigned short MS_U16; // 2 bytes
+/// data type unsigned int, data length 4 byte
+typedef unsigned int MS_U32; // 4 bytes
+/// data type unsigned int, data length 8 byte
+typedef unsigned long long MS_U64; // 8 bytes
+/// data type signed char, data length 1 byte
+typedef signed char MS_S8; // 1 byte
+/// data type signed short, data length 2 byte
+typedef signed short MS_S16; // 2 bytes
+/// data type signed int, data length 4 byte
+typedef signed int MS_S32; // 4 bytes
+/// data type signed int, data length 8 byte
+typedef signed long long MS_S64; // 8 bytes
+/// data type float, data length 4 byte
+typedef float MS_FLOAT; // 4 bytes
+
+typedef unsigned char MI_U8; // 1 byte
+typedef unsigned short MI_U16; // 2 bytes
+typedef unsigned int MI_U32; // 4 bytes
+typedef unsigned long long MI_U64; // 8 bytes
+typedef signed char MI_S8; // 1 byte
+typedef signed short MI_S16; // 2 bytes
+typedef signed int MI_S32; // 4 bytes
+typedef signed long long MI_S64; // 8 bytes
+/*
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_FALSE = 0,
+ SS_TRUE = !SS_FALSE,
+ SS_BOOL_MAX
+} MI_ISP_BOOL_e;
+
+typedef enum __attribute__ ((aligned (4)))
+{
+ SS_OP_TYP_AUTO = 0,
+ SS_OP_TYP_MANUAL = !SS_OP_TYP_AUTO,
+ SS_OP_TYP_MODE_MAX
+} MI_ISP_OP_TYPE_e;
+*/
+typedef enum __attribute__ ((aligned (4)))
+{
+ MS_FALSE = 0,
+ MS_TRUE = !MS_FALSE,
+ MS_BOOL_MAX = 0x7FFFFFFF
+} MS_CAM_BOOL;
+
+#define FAIL (-1)
+#define SUCCESS (0)
+
+#if !defined(NULL)
+#define NULL (0)
+#endif
+
+#if !defined(TRUE) && !defined(FALSE)
+/// definition for TRUE
+#define TRUE 1
+/// definition for FALSE
+#define FALSE 0
+#endif
+
+#define LIMIT(x, low, high) (((x) > (high)) ? (high) : (((x) < (low)) ? (low) : (x)))
+
+#ifdef sign
+#undef sign
+#endif
+#define sign(a) (((a) > 0) ? (1) : (-1))
+
+#define CAMERA_ISR_FREQ_SEC (0)
+#define CAMERA_ISR_FREQ_NSEC (10000000) //(1000*1000*1000) // 1sec
+
+#define PACK_ALIGN_TAG(n) __attribute__((packed, aligned(n)))
+#define LIMIT_BITS(x, bits) ((x) > ((1<<(bits))-1) ? (((1<<(bits))-1)) : (x))
+typedef void *(*THREAD_P)(void *);
+
+#define AE_WIN_MAX_WIDTH (32)//(16)
+#define AE_WIN_MAX_HEIGHT (32)//(24)
+#define AE_HIST_WIN_MAX_WIDTH (128)
+#define AE_HIST_WIN_MAX_HEIGHT (90)
+#define AE_HIST_BIN0 (40)
+#define AE_HIST_BINX (128)
+#define AE_IR_HIST_BIN (256)
+#define AE_HIST_OUT_BIN (256)
+
+#define HDR_STATS_LEN (1024)
+
+#define AWB_WIN_MAX_WIDTH (128)
+#define AWB_WIN_MAX_HEIGHT (90)
+#define AWB_BLOCK_MIN_VALID_X (4)
+#define AWB_BLOCK_MIN_VALID_Y (2)
+
+#define AWB_LV_CT_TBL_NUM 18
+#define AWB_CT_TBL_NUM 10
+
+typedef struct
+{
+ MS_U8 uAvgR;
+ MS_U8 uAvgG;
+ MS_U8 uAvgB;
+ MS_U8 uAvgY;
+} MS_AE_AVGS;
+
+typedef struct
+{
+ MS_U8 uAvgR;
+ MS_U8 uAvgG;
+ MS_U8 uAvgB;
+} MS_AWB_AVGS;
+
+// crop range
+typedef struct
+{
+ unsigned int x;
+ unsigned int y;
+ unsigned int width;
+ unsigned int height;
+ unsigned int degree;
+ char mirror_flip;
+} ISP_CROP_RANGE;
+
+// input source/output destination
+typedef enum
+{
+ // source
+ ISP_DATA_SRC_TV,
+ ISP_DATA_SRC_SENSOR,
+ ISP_DATA_SRC_RDMA,
+
+ // destination
+ ISP_DATA_DST_ICP,
+ ISP_DATA_DST_WDMA_SIF,
+ ISP_DATA_DST_WDMA_ISP,
+ ISP_DATA_DST_WDMA_ISPDS,
+ ISP_DATA_DST_WDMA_ISPSWAPYC,
+ ISP_DATA_DST_WDMA_VDOS,
+ ISP_DATA_DST_WDMA_ISP_GREY,
+ ISP_DATA_DST_WDMA_ISP_OUT,
+ ISP_DATA_DST_WDMA_RGBIR_IN
+} ISP_DATA_SRCDST;
+typedef enum
+{
+ ISP_SRC_SENSOR,
+ ISP_SRC_RDMA,
+} ISP_DATA_SRC;
+
+typedef struct
+{
+ unsigned int x;
+ unsigned int y;
+ unsigned int width;
+ unsigned int height;
+} ISP_WDMA_CROP_RANGE;
+// color space
+typedef enum
+{
+ ISP_COLOR_SPACE_YUV,
+ ISP_COLOR_SPACE_BAYER,
+} ISP_COLOR_SPACE;
+
+// data precision
+typedef enum
+{
+ ISP_DATAPRECISION_8 = 0,
+ ISP_DATAPRECISION_10 = 1,
+ ISP_DATAPRECISION_16 = 2,
+ ISP_DATAPRECISION_12 = 3,
+ ISP_DATAPRECISION_1T4P_8 = 4,
+ ISP_DATAPRECISION_1T4P_10 = 5,
+ ISP_DATAPRECISION_1T4P_16 = 6,
+ ISP_DATAPRECISION_1T4P_12 = 7
+} ISP_DATAPRECISION;
+
+typedef enum
+{
+ BAYER_RG = 0,
+ BAYER_GR = 1,
+ BAYER_BG = 2,
+ BAYER_GB = 3
+} SEN_BAYER;
+
+typedef enum
+{
+ RGBIR_R0 = 0,
+ RGBIR_G0 = 1,
+ RGBIR_B0 = 2,
+ RGBIR_G1 = 3,
+ RGBIR_G2 = 4,
+ RGBIR_I0 = 5,
+ RGBIR_G3 = 6,
+ RGBIR_I1 = 7,
+ RGBIR_NONE = 8,
+} SEN_RGBIR;
+
+
+// input/output configuration
+typedef struct
+{
+ ISP_CROP_RANGE crop_range;
+ ISP_DATA_SRCDST srcdst;
+ ISP_DATAPRECISION data_precision;
+ ISP_COLOR_SPACE colorspace;
+} ISP_INOUT_CONFIG;
+/*
+// data control path
+typedef enum
+{
+ ISP_CTL_PATH_SENSOR_ISP_ICP, // preview
+ ISP_CTL_PATH_SENSOR_WDMA_RDMA_ISP_ICP, // preview with ring buffer
+ ISP_CTL_PATH_SENSOR_WDMA, // capture raw
+ ISP_CTL_PATH_RDMA_ISPDS_WDMA, // iterative processing raw
+ ISP_CTL_PATH_RDMA_ISPDP_WDMA, // software trigger capture
+ ISP_CTL_PATH_RDMA_ISP_ICP // software trigger capture
+} ISP_CTL_PATH;
+*/
+
+/*
+typedef enum {
+ CAMERA_ID_REAR1 = 0,
+ CAMERA_ID_REAR2 = 1,
+ CAMERA_ID_FRONT1 = 2,
+ CAMERA_ID_FRONT2 = 3,
+ CAMERA_ID_TV1 = 4,
+ CAMERA_ID_TV2 = 5,
+ CAMERA_ID_PG = 6,
+ CAMERA_ID_AUTO = 7,
+ CAMERA_ID_END = 8
+} CameraModule_id_t;
+*/
+
+typedef enum
+{
+ IQ_OBC,
+ IQ_WBG,
+ IQ_WBG0,
+ IQ_WBG1,
+ IQ_LSC,
+ IQ_CROSSTALK,
+ IQ_AEAWB_STATS,
+ IQ_DPC,
+ IQ_SPIKE_NR,
+ IQ_MEAN_FILTER, // mean filter
+ IQ_NOISE_MASKING, // noise masking
+ IQ_FALSECOLOR,
+ IQ_CFAi, // De-Mosaic
+ IQ_CFAi_NR, // Post Denoise
+ IQ_DNR,
+ IQ_DNR_LUM,
+ IQ_AF_STATS,
+ IQ_CCM,
+ IQ_UVCM,
+ IQ_GAMMA_RAW_LC,
+ IQ_GAMMA_RGB_LC,
+ IQ_GAMMA16TO16,
+ IQ_ALSC,
+ IQ_MOTION,
+ IQ_ROTATE,
+ IQ_END
+} ISP_IQ_BLK;
+
+typedef enum
+{
+ ISP_WDMA_ICP,
+ ISP_WDMA_SIF,
+ ISP_WDMA_ISP,
+ ISP_WDMA_ISPDS,
+ ISP_WDMA_ISPSWAPYC,
+ ISP_WDMA_VDOS,
+ ISP_WDMA_ISP_GREY,
+ ISP_WDMA_ISP_OUT,
+ ISP_WDMA_RGBIR_IN,
+ ISP_WDMA_DEFAULT_SIF,
+ ISP_WDMA_DEFAULT_YC
+} WDMA_PATH;
+
+typedef struct
+{
+ MS_U32 width;
+ MS_U32 height;
+ MS_U32 x;
+ MS_U32 y;
+ WDMA_PATH wdma_path;
+ MS_U32 miu_addr;
+} PACK_ALIGN_TAG(1) ISP_WDMA_ATTR;
+
+// AE functions
+typedef struct
+{
+ MS_U16 u2BlkSize_x;
+ MS_U16 u2BlkSize_y;
+ MS_U16 u2BlkNum_x;
+ MS_U16 u2BlkNum_y;
+} ISP_AE_WIN;
+
+typedef struct
+{
+ MS_U16 Rgbir_stats[AE_IR_HIST_BIN];
+} ISP_RGBIR_STATS;
+
+typedef struct
+{
+ MS_U16 HDR_stats[HDR_STATS_LEN];
+} ISP_HDR_STATS;
+
+typedef struct
+{
+ MS_U8 uAvgR;
+ MS_U8 uAvgG;
+ MS_U8 uAvgB;
+ MS_U8 uAvgY;
+} ISP_AE_AVGS;
+
+typedef struct
+{
+ MS_U16 u2HistR[AE_HIST_BIN0];
+ MS_U16 u2HistG[AE_HIST_BIN0];
+ MS_U16 u2HistB[AE_HIST_BIN0];
+} ISP_AE_HIST0;
+
+typedef struct
+{
+ MS_U16 u2HistY[AE_HIST_BINX];
+} ISP_AE_HISTX;
+
+typedef struct
+{
+ ISP_AE_HIST0 Hist0;
+ ISP_AE_HISTX Hist1;
+ ISP_AE_HISTX Hist2;
+ ISP_RGBIR_STATS HistIR;
+ ISP_AE_AVGS Avgs[AE_WIN_MAX_WIDTH * AE_WIN_MAX_HEIGHT];
+ ISP_AE_AVGS Avgs1[AE_WIN_MAX_WIDTH * AE_WIN_MAX_HEIGHT];
+} PACK_ALIGN_TAG(16) ISP_AE_STATIS;
+
+#if 1
+// crop config, isp_crop_cfg
+typedef struct {
+ int x_start;
+ int y_start;
+ int width;
+ int height;
+} ISP_CROP_WIN, IspCropWin_t;
+#endif
+
+#if 1
+typedef struct {
+ MS_U16 u2BlkNum_x;
+ MS_U16 u2BlkNum_y;
+ MS_U16 u2BlkVaild_x;
+ MS_U16 u2BlkVaild_y;
+ MS_U16 u2BlkValidLowLux_x;
+ MS_U16 u2BlkValidLowLux_y;
+ MS_U8 AccEnhanceRatio;
+} ISP_AWB_WIN, IspAwbWin_t;
+#endif
+
+typedef struct
+{
+ MS_U16 u2Stawin_x_offset;
+ MS_U16 u2Stawin_x_size;
+ MS_U16 u2Stawin_y_offset;
+ MS_U16 u2Stawin_y_size;
+ //MS_BOOL roi_mode;
+} ISP_HISTO_WIN;
+
+typedef struct
+{
+ MS_U8 acc_sft;
+ MS_U16 u2BlkSize_x;
+ MS_U16 u2BlkSize_y;
+ MS_U16 u2BlkNum_x;
+ MS_U16 u2BlkNum_y;
+ MS_U16 u2Blk_h_offset;
+ MS_U16 u2Blk_v_offset;
+} ISP_HISTO_ATTR;
+
+typedef struct
+{
+ MS_U16 nRgain; /** R channel */
+ MS_U16 nGrgain; /** Gr channel */
+ MS_U16 nGbgain; /** Gb channel */
+ MS_U16 nBgain; /** B channel */
+} IspAwbGain_t;
+
+typedef struct {
+ MS_U8 uAvgR;
+ MS_U8 uAvgG;
+ MS_U8 uAvgB;
+} PACK_ALIGN_TAG(1) ISP_AWB_AVGS, IspAwbBlkAvg_t;
+
+typedef struct {
+ IspAwbBlkAvg_t tRow[AWB_WIN_MAX_WIDTH];
+} PACK_ALIGN_TAG(16) IspAwbAvgRow_t;
+
+typedef struct {
+ ISP_AWB_AVGS Avgs[AWB_WIN_MAX_WIDTH * AWB_WIN_MAX_HEIGHT];
+ //IspAwbAvgRow_t Avgs[AWB_WIN_MAX_HEIGHT];
+} PACK_ALIGN_TAG(16) ISP_AWB_STATIS,IspAwbStatis_t;
+
+typedef enum
+{
+ SIF_BUS_PARL = 0,
+ SIF_BUS_MIPI = 1
+} SIF_BUS;
+
+typedef enum
+{
+ CLK_POL_POS = 0,
+ CLK_POL_NEG
+} CLK_POL;
+
+typedef enum
+{
+ ISP_DNR_PATH_BEFORE_HDR = 0,
+ ISP_DNR_PATH_AFTER_HDR
+} ISP_DNR_PATH_SEL;
+
+typedef struct
+{
+ MS_U32 x;
+ MS_U32 y;
+ MS_U32 h;
+ MS_U32 w;
+}RECT_t;
+
+typedef enum
+{
+ eIspInOutMode_RealTimeModeNoHDR = 0,
+ eIspInOutMode_RealTimeModeHDR = 1,
+ eIspInOutMode_FrameModeNoHDR = 2,
+ eIspInOutMode_FrameModeHDR = 3,
+ eIspInOutMode_RealTimeModeYuv = 4,
+ eIspInOutMode_FrameModeYuv = 5,
+}IspInOutMode_e;
+
+typedef enum
+{
+ eIspHDRType_OFF,
+ eIspHDRType_VC, //virtual channel mode HDR, vc0->long, vc1->short
+ eIspHDRType_DOL,
+ eIspHDRType_EMB, //compressed HDR mode
+ eIspHDRType_LI, //Line interlace HDR
+ eIspHDRType_MAX
+}IspHDRType_e;
+
+typedef enum
+{
+ eIspBayerID_RG = 0,
+ eIspBayerID_GR = 1,
+ eIspBayerID_BG = 2,
+ eIspBayerID_GB = 3,
+}IspBayerID_e;
+
+typedef enum
+{
+ eIspPixelFmt_8Bit = 0,
+ eIspPixelFmt_10Bit = 1,
+ eIspPixelFmt_16Bit = 2,
+ eIspPixelFmt_12Bit = 3,
+}IspPixelFmt_e;
+
+//infinity5
+typedef enum
+{
+ eIsp3DNRCompressLevel_0 = 0, //12-bit
+ eIsp3DNRCompressLevel_1 = 1, //10-bit
+ eIsp3DNRCompressLevel_2 = 2, //8-bit
+ eIsp3DNRCompressLevel_3 = 3, //reserved
+}Isp3DNRCompressLevel_e;
+
+//infinity6
+typedef enum
+{
+ eIspDNRBitDepth_8 = 0, //8-bit
+ eIspDNRBitDepth_12 = 1, //12-bit
+}IspDNRBitDepth_e;
+
+typedef enum
+{
+ eIspDNRBlockMode = 0, // block mode
+ eIspDNRLinearMode = 1, // linear mode
+}IspDNRDataArrange_e;
+
+typedef enum
+{
+ eIspDNRBlock_128 = 0, // for 128 byte block width
+ eIspDNRBlock_256 = 1, // for 256 byte block width
+}IspDNRBlockWidth_e;
+
+typedef enum
+{
+ eIspDNRDramRow_2K = 0, // for 2K byte/Row in DRAM
+ eIspDNRDramRow_1K = 1, // for 1K byte/Row in DRAM
+}IspDNRDramRowMode_e;
+
+typedef struct
+{
+ MS_U16 u16InWidth;
+ MS_U16 u16InHeight;
+ SEN_BAYER eBayerId;
+ Isp3DNRCompressLevel_e eBitDepth;
+ IspDNRDataArrange_e eDataMode;
+ IspDNRBlockWidth_e eBlockWidth;
+ IspDNRDramRowMode_e eRowMode;
+ MS_U32 u32HistBaseAddr;
+ MS_U32 u32RefBaseAddr[4];
+ MS_CAM_BOOL bRingMode;
+}IspDNRAttr_t;
+
+typedef struct
+{
+ MS_U16 u16InWidth;
+ MS_U16 u16InHeight;
+ IspDNRBitDepth_e eBitDepth;
+ IspDNRDataArrange_e eDataMode;
+ IspDNRBlockWidth_e eBlockWidth;
+ IspDNRDramRowMode_e eRowMode;
+ MS_U32 u32BaseAddr[4];
+ MS_U8 u8MiuReqNum;
+ MS_U8 u8MiuReqCycle;
+}IspROTAttr_t;
+
+typedef struct
+{
+ IspInOutMode_e eMode;
+ IspHDRType_e eHdrType;
+ MS_U16 u16InWidth;
+ MS_U16 u16InHeight;
+ RECT_t tCrop;
+ SEN_BAYER eBayerID;
+ ISP_DATAPRECISION ePixelFmt;
+ ISP_AE_WIN tAeWin;
+ IspAwbWin_t tAwbWin;
+ SEN_RGBIR eRGBIRID; //infinity5.
+ MS_CAM_BOOL bRoation;
+ MS_U16 u16IQWidth;
+ MS_U16 u16IQHeight;
+}IspInOutAttr_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* MSTAR_ISP_GENERAL_H_ */
diff --git a/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/ssnn.h b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/ssnn.h
new file mode 100644
index 00000000..1b504d82
--- /dev/null
+++ b/br-ext-chip-sigmastar/package/sigmastar-osdrv-ssc335/files/include/ssnn.h
@@ -0,0 +1,81 @@
+#ifndef _SSNN_H
+#define _SSNN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// ==================================================================================================
+// Structure Definition
+// ==================================================================================================
+
+typedef struct
+{
+ // == Model-dependent settings == //
+ int target_height;
+ int target_width;
+
+ // == General settings == //
+ float prob_thresh;
+ float nms_thresh;
+ int num_threads;
+ int max_detection;
+ int init_network_index;
+}network_config;
+
+typedef struct
+{
+ short int x_min, y_min; // top-left corner
+ short int x_max, y_max; // bottom-right corner
+ short int class_idx;
+ float prob;
+}BBox;
+
+typedef struct
+{
+ network_config *cfg;
+ void *net;
+ BBox *boxes; // Only for detector
+ float *probs; // Only for classifier
+ float *feature; // Only for feature extractor
+ int num_detection;
+}NetworkHandle;
+
+// ==================================================================================================
+// Enumerations
+// ==================================================================================================
+
+enum E_NETWORK_TYPE
+{
+ CLASSIFIER,
+ DETECTOR,
+ FEATURE
+};
+
+// ==================================================================================================
+// API
+// ==================================================================================================
+
+int Init_Network(NetworkHandle **phandle, network_config *cfg);
+void Release_Network(NetworkHandle **phandle);
+int Forward_Network(NetworkHandle *handle, unsigned char *data, int height, int width, int color);
+int Get_Detection(NetworkHandle *handle, int img_height, int img_width); // Only for detector
+int Get_Prob(NetworkHandle *handle); // Only for classifier
+int Get_Feature(NetworkHandle *handle); // Only for feature extractor
+int Change_Model(NetworkHandle *handle, int network_index);
+int Get_Num_Classes(NetworkHandle *handle);
+int Get_Network_Type(NetworkHandle *handle);
+int Get_Size_Alignment(NetworkHandle *handle);
+int Get_Feature_Size(NetworkHandle *handle);
+
+// -- For automatically adjusting target size based on area constraints -- //
+int Set_Input_Min_Max_Area(NetworkHandle *handle, int min_area, int max_area);
+
+// -- For advanced usage -- //
+int Forward_Network_Stride(NetworkHandle *handle, unsigned char *data, int height, int width, int color, int stride);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file