mirror of https://github.com/OpenIPC/firmware.git
Fix init for Hi3519v101
Dmitry Ermakov
parent
42039ccae1
commit
14d4cf3c13
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@ -2,7 +2,7 @@
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#
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# This is part of OpenIPC.org project | 2022.01.07
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#
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#set -x
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# SoC detect
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chipid=$(ipcinfo --chip_id)
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@ -18,7 +18,9 @@ os_mem_size=${os_mem_size:=32}
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# Sensor config
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# SNS_TYPE=$(awk -F '=' '$1=="sensor"{print $2}' RS=" " /proc/cmdline)
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SNS_TYPE0=$(fw_printenv -n sensor)
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SNS_TYPE0=${SNS_TYPE0:=ov4689}
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SNS_TYPE0=${SNS_TYPE0:=imx290}
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SNS_TYPE1="NULL"
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WORK_MODE="single_pipe"
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report_error() {
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echo "******* Error: There's something wrong, please check! *****"
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@ -69,6 +71,10 @@ remove_audio() {
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}
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sysconfig() {
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devmem 0x100503c4 32 0x7
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devmem 0x100503c0 32 0x11011f
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devmem 0x100503c4 32 0xc004
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devmem 0x100503c0 32 0x110113
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vicap_pin_mux() {
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#sensor0 pinmux
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devmem 0x1204017c 32 0x1 #SENSOR0_CLK
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@ -228,9 +234,8 @@ sysconfig() {
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vicap1_pwrdn >/dev/null
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fi
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#clkcfg
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clkcfg() {
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devmem 0x120100e4 32 0x1fff0000 # I2C0-3/SSP0-3 unreset, ir,enable clk gate
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devmem 0x120100e4 32 0x1ff70000 # I2C0-3/SSP0-3 unreset, ir,enable clk gate
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devmem 0x1201003c 32 0x31000100 # MIPI VI ISP unreset
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devmem 0x12010050 32 0x2 # VEDU0 unreset
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devmem 0x12010058 32 0x2 # VPSS0 unreset
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@ -269,8 +274,6 @@ sysconfig() {
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# pcie clk enable
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devmem 0x120100b0 32 0x000001f0
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echo "clock configure operation done!"
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}
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vi_vpss_online_config() {
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# -------------vi vpss online open
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@ -378,7 +381,7 @@ insert_sns() {
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devmem 0x12010040 32 0x14 # sensor0 clk_en, 24MHz
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i2c0_pin_mux
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;;
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imx290 | imx385)
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imx290)
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tmp=0x18
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# SDK config: IVE:396M, GDC:475M, VGS:500M, VEDU:600M, VPSS:300M
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#imx290:viu0:340M,isp0:214M, viu1:340M,isp1:214M
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@ -387,6 +390,19 @@ insert_sns() {
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devmem 0x12010040 32 0x18 # sensor0 clk_en, 37.125MHz
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i2c0_pin_mux
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;;
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imx385)
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tmp=0x18
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devmem 0x12010040 32 0x18
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devmem 0x12040190 32 0x2
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devmem 0x1204018c 32 0x2
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devmem 0x1204099c 32 0x120
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devmem 0x12040998 32 0x120
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insmod hi_ssp_sony.ko
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devmem 0x12040184 32 0x1
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devmem 0x12040188 32 0x1
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devmem 0x12040010 32 0x2
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devmem 0x12040014 32 0x2
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;;
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ov4689)
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tmp=0x14
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# SDK config: IVE:396M, GDC:475M, VGS:500M, VEDU:600M, VPSS:300M
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@ -557,6 +573,11 @@ insert_ko() {
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devmem 0x12010044 32 0x4ff0
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devmem 0x12010044 32 0x4
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devmem 0x12040098 32 0x3
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devmem 0x120100DC 32 0x6
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devmem 0x1204008C 32 0x1
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devmem 0x12040094 32 0x1
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echo "==== Your input Sensor0 type is $SNS_TYPE0 ===="
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echo "==== Your input Sensor1 type is $SNS_TYPE1 ===="
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}
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@ -568,8 +589,8 @@ remove_ko() {
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rmmod hi_pwm
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rmmod hi_piris
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#rmmod hi3519v101_photo
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rmmod hi3519v101_ive
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rmmod hi3519v101_photo
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#rmmod hi3519v101_ive
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rmmod hi3519v101_rc
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rmmod hi3519v101_jpege
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@ -0,0 +1,80 @@
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[sensor]
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Sensor_type=stSnsOs08a10Obj
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Mode=WDR_MODE_NONE
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DllFile=libsns_os08a10.so
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[mode]
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input_mode=INPUT_MODE_MIPI
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dev_attr=0
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[mipi]
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data_type=2
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lane_id=0|1|2|3|-1|-1|-1|-1|
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[isp_image]
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Isp_FrameRate=30
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Isp_Bayer=BAYER_BGGR
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[vi_dev]
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Input_mod=VI_MODE_MIPI
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Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
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;VI_WORK_MODE_2Multiplex,
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;VI_WORK_MODE_4Multiplex
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Combine_mode =0 ;Y/C composite or separation mode
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;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
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;VI_COMBINE_SEPARATE, /*Separate mode */
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Comp_mode =0 ;Component mode (single-component or dual-component)
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;VI_COMP_MODE_SINGLE = 0, /*single component mode */
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;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
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Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
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;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
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;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
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Mask_num =2 ;Component mask
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Mask_0 =0xFFF00000
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Mask_1 =0x0
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Scan_mode = 1;VI_SCAN_INTERLACED = 0
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;VI_SCAN_PROGRESSIVE,
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Data_seq =3 ;data sequence (ONLY for YUV format)
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;----2th component U/V sequence in bt1120
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; VI_INPUT_DATA_VUVU = 0,
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; VI_INPUT_DATA_UVUV,
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;----input sequence for yuv
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; VI_INPUT_DATA_UYVY = 0,
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; VI_INPUT_DATA_VYUY,
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; VI_INPUT_DATA_YUYV,
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; VI_INPUT_DATA_YVYU
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Vsync =1 ; vertical synchronization signal
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;VI_VSYNC_FIELD = 0,
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;VI_VSYNC_PULSE,
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VsyncNeg=1 ;Polarity of the vertical synchronization signal
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;VI_VSYNC_NEG_HIGH = 0,
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;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
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Hsync =0 ;Attribute of the horizontal synchronization signal
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;VI_HSYNC_VALID_SINGNAL = 0,
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;VI_HSYNC_PULSE,
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HsyncNeg =0 ;Polarity of the horizontal synchronization signal
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;VI_HSYNC_NEG_HIGH = 0,
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;VI_HSYNC_NEG_LOW
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VsyncValid =1 ;Attribute of the valid vertical synchronization signal
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;VI_VSYNC_NORM_PULSE = 0,
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;VI_VSYNC_VALID_SINGAL,
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VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
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;VI_VSYNC_VALID_NEG_HIGH = 0,
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;VI_VSYNC_VALID_NEG_LOW
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Timingblank_HsyncHfb =0 ;Horizontal front blanking width
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Timingblank_HsyncAct =1280 ;Horizontal effetive width
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Timingblank_HsyncHbb =0 ;Horizontal back blanking width
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Timingblank_VsyncVfb =0 ;Vertical front blanking height
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Timingblank_VsyncVact =720 ;Vertical effetive width
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Timingblank_VsyncVbb=0 ;Vertical back blanking height
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Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
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Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
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Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
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DataPath=1
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InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
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DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
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DevRect_x=0
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DevRect_y=0
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DevRect_w=3840
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DevRect_h=2160
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@ -57,7 +57,7 @@ define HISILICON_OSDRV_HI3519V101_INSTALL_TARGET_CMDS
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$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_pwm.ko
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$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_sensor_i2c.ko
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$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_sensor_spi.ko
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# $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_ssp_sony.ko
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$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_ssp_sony.ko
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# $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_user.ko
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$(INSTALL) -m 755 -d $(TARGET_DIR)/usr/bin
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