mirror of https://github.com/OpenIPC/firmware.git
Add IMX291 DC for Hi3516Dv100
parent
feb80cde38
commit
0f30c4a2bc
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@ -180,6 +180,13 @@ insert_sns() {
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insmod sensor_spi.ko
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;;
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imx291)
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devmem 0x200f0050 32 0x2 # i2c0_scl
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devmem 0x200f0054 32 0x2 # i2c0_sda
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devmem 0x2003002c 32 0x90005 # sensor unreset, clk 37.125MHz, VI 148MHz
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;;
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imx117)
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devmem 0x200f0050 32 0x1 # spi0_sclk
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devmem 0x200f0054 32 0x1 # spi0_sdo
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@ -287,7 +294,7 @@ insert_ko() {
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insert_audio
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insmod hi_mipi.ko
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insmod wdt.ko
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#insmod wdt.ko
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echo "==== Your input Sensor type is $SENSOR ===="
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}
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@ -0,0 +1,76 @@
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[sensor]
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Sensor_type=imx291
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Mode=WDR_MODE_NONE
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DllFile=libsns_imx291_dc.so
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[mode]
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input_mode=INPUT_MODE_CMOS_18V
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dev_attr=0
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[isp_image]
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Isp_FrameRate=30
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Isp_Bayer=BAYER_GBRG
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[vi_dev]
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Input_mod=VI_MODE_DIGITAL_CAMERA
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Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
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;VI_WORK_MODE_2Multiplex,
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;VI_WORK_MODE_4Multiplex
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Combine_mode =0 ;Y/C composite or separation mode
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;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
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;VI_COMBINE_SEPARATE, /*Separate mode */
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Comp_mode =0 ;Component mode (single-component or dual-component)
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;VI_COMP_MODE_SINGLE = 0, /*single component mode */
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;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
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Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
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;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
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;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
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Mask_num =2 ;Component mask
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Mask_0 =0xFFF0000
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Mask_1 =0x0
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Scan_mode = 1;VI_SCAN_INTERLACED = 0
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;VI_SCAN_PROGRESSIVE,
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Data_seq =2 ;data sequence (ONLY for YUV format)
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;----2th component U/V sequence in bt1120
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; VI_INPUT_DATA_VUVU = 0,
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; VI_INPUT_DATA_UVUV,
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;----input sequence for yuv
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; VI_INPUT_DATA_UYVY = 0,
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; VI_INPUT_DATA_VYUY,
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; VI_INPUT_DATA_YUYV,
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; VI_INPUT_DATA_YVYU
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Vsync =1 ; vertical synchronization signal
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;VI_VSYNC_FIELD = 0,
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;VI_VSYNC_PULSE,
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VsyncNeg=0 ;Polarity of the vertical synchronization signal
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;VI_VSYNC_NEG_HIGH = 0,
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;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
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Hsync =0 ;Attribute of the horizontal synchronization signal
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;VI_HSYNC_VALID_SINGNAL = 0,
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;VI_HSYNC_PULSE,
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HsyncNeg =0 ;Polarity of the horizontal synchronization signal
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;VI_HSYNC_NEG_HIGH = 0,
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;VI_HSYNC_NEG_LOW
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VsyncValid =1 ;Attribute of the valid vertical synchronization signal
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;VI_VSYNC_NORM_PULSE = 0,
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;VI_VSYNC_VALID_SINGAL,
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VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
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;VI_VSYNC_VALID_NEG_HIGH = 0,
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;VI_VSYNC_VALID_NEG_LOW
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Timingblank_HsyncHfb =0 ;Horizontal front blanking width
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Timingblank_HsyncAct =1920 ;Horizontal effetive width
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Timingblank_HsyncHbb =0 ;Horizontal back blanking width
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Timingblank_VsyncVfb =0 ;Vertical front blanking height
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Timingblank_VsyncVact =1080 ;Vertical effetive width
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Timingblank_VsyncVbb=0 ;Vertical back blanking height
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Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
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Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
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Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
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DataPath=1
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InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
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DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
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DevRect_x=0
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DevRect_y=30
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DevRect_w=1920
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DevRect_h=1080
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