From 0178aa0952c84590c76b529046838739dbf556ab Mon Sep 17 00:00:00 2001 From: Dmitry Ilyin Date: Wed, 26 Jan 2022 21:23:31 +0300 Subject: [PATCH] Update ov9712 config and add experimental AWB features (#168) --- .../sensor/config/ov9712_i2c_dc_720p.ini | 197 ++---------------- 1 file changed, 21 insertions(+), 176 deletions(-) diff --git a/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/ov9712_i2c_dc_720p.ini b/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/ov9712_i2c_dc_720p.ini index 7addea21..389d51d5 100644 --- a/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/ov9712_i2c_dc_720p.ini +++ b/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/ov9712_i2c_dc_720p.ini @@ -8,7 +8,7 @@ Mode =0 ;WDR_MODE_NONE = 0 DllFile =/usr/lib/sensors/libsns_ov9712_i2c_dc.so ;sensor lib path -[mode] +[mode] input_mode =4 ;INPUT_MODE_MIPI = 0 ;INPUT_MODE_SUBLVDS = 1 ;INPUT_MODE_LVDS = 2 ...etc @@ -17,53 +17,13 @@ dev_attr = 2 ;mipi_dev_attr_t = 0 ;lvds_dev_attr_t = 1 ;NULL =2 -[mipi] -;----------only for mipi_dev--------- -data_type =-1 ;raw data type: 8/10/12/14 bit - ;RAW_DATA_8BIT = 1 - ;RAW_DATA_10BIT = 2 - ;RAW_DATA_12BIT = 3 - ;RAW_DATA_14BIT = 4 -lane_id = -1|-1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable - -[lvds] -;----------only for lvds_dev--------- -img_size_w = -1 ;oringnal sensor input image size W -img_size_h = -1 ;oringnal sensor input image size H -wdr_mode = -1 ;HI_WDR_MODE_NONE =0 - ;HI_WDR_MODE_2F = 1 - ;HI_WDR_MODE_3F = 2 - ;HI_WDR_MODE_4F =3 -sync_mode = -1 ;LVDS_SYNC_MODE_SOL = 0 - ;LVDS_SYNC_MODE_SAV = 1 -raw_data_type = -1 ;RAW_DATA_8BIT = 0 - ;RAW_DATA_10BIT = 1 - ;RAW_DATA_12BIT = 2 - ;RAW_DATA_14BIT = 3 -data_endian = -1 ;LVDS_ENDIAN_LITTLE = 0 - ;LVDS_ENDIAN_BIG = 1 -sync_code_endian =-1 ;LVDS_ENDIAN_LITTLE = 0 - ;LVDS_ENDIAN_BIG = 1 -lane_id = -1|-1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable -lvds_lane_num = -1 ;LVDS_LANE_NUM -wdr_vc_num = -1 ;WDR_VC_NUM -sync_code_num = -1 ;SYNC_CODE_NUM -sync_code_0 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| -sync_code_1 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| -sync_code_2 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| -sync_code_3 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| -sync_code_4 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| -sync_code_5 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| -sync_code_6 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| -sync_code_7 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| - [isp_image] Isp_x =0 Isp_y =0 Isp_W =1280 Isp_H =720 Isp_FrameRate=25 -Isp_Bayer =3 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3 +Isp_Bayer =3 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3 [vi_dev] @@ -96,25 +56,25 @@ Data_seq =2 ;data sequence (ONLY for YUV format) ; VI_INPUT_DATA_VYUY, ; VI_INPUT_DATA_YUYV, ; VI_INPUT_DATA_YVYU - + Vsync =0 ; vertical synchronization signal - ;VI_VSYNC_FIELD = 0, + ;VI_VSYNC_FIELD = 0, ;VI_VSYNC_PULSE, VsyncNeg=0 ;Polarity of the vertical synchronization signal - ;VI_VSYNC_NEG_HIGH = 0, - ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E + ;VI_VSYNC_NEG_HIGH = 0, + ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E Hsync =0 ;Attribute of the horizontal synchronization signal ;VI_HSYNC_VALID_SINGNAL = 0, ;VI_HSYNC_PULSE, HsyncNeg =0 ;Polarity of the horizontal synchronization signal - ;VI_HSYNC_NEG_HIGH = 0, + ;VI_HSYNC_NEG_HIGH = 0, ;VI_HSYNC_NEG_LOW VsyncValid =1 ;Attribute of the valid vertical synchronization signal ;VI_VSYNC_NORM_PULSE = 0, - ;VI_VSYNC_VALID_SINGAL, + ;VI_VSYNC_VALID_SINGAL, VsyncValidNeg =0;Polarity of the valid vertical synchronization signal ;VI_VSYNC_VALID_NEG_HIGH = 0, - ;VI_VSYNC_VALID_NEG_LOW + ;VI_VSYNC_VALID_NEG_LOW Timingblank_HsyncHfb =408 ;Horizontal front blanking width Timingblank_HsyncAct =1280 ;Horizontal effetive width Timingblank_HsyncHbb =0 ;Horizontal back blanking width @@ -125,24 +85,19 @@ Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) -;----- only for bt656 ---------- -FixCode =0 ;BT656_FIXCODE_1 = 0, - ;BT656_FIXCODE_0 -FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0 - ;BT656_FIELD_POLAR_NSTD DataPath =1 ;ISP enable or bypass ;VI_PATH_BYPASS = 0,/* ISP bypass */ ;VI_PATH_ISP = 1,/* ISP enable */ ;VI_PATH_RAW = 2,/* Capture raw data, for debug */ InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1, DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1 -DevRect_x=0 ; -DevRect_y=0 ; -DevRect_w=1280 ; -DevRect_h=720 ; +DevRect_x=0 +DevRect_y=0 +DevRect_w=1280 +DevRect_h=720 [vi_chn] -CapRect_X =0 +CapRect_X =0 CapRect_Y =0 CapRect_Width=1280 CapRect_Height=720 @@ -152,125 +107,15 @@ CapSel =2 ;Frame/field select. ONLY used in interlaced mode ;VI_CAPSEL_TOP = 0, /* top field */ ;VI_CAPSEL_BOTTOM, /* bottom field */ ;VI_CAPSEL_BOTH, /* top and bottom field */ - PixFormat =19;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22 ;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc CompressMode =0 ;COMPRESS_MODE_NONE = 0 ;COMPRESS_MODE_SEG =1 ...etc -SrcFrameRate=-1 ;Source frame rate. -1: not controll -FrameRate =-1 ;Target frame rate. -1: not controll - -[vpss_group] -Vpss_DciEn =FALSE -Vpss_IeEn =FALSE -Vpss_NrEn =TRUE -Vpss_HistEn =FALSE -Vpss_DieMode=1 ;Define de-interlace mode - ;VPSS_DIE_MODE_AUTO = 0, - ;VPSS_DIE_MODE_NODIE = 1, - ;VPSS_DIE_MODE_DIE = 2, - -[vpss_corp] -Crop_enable =FALSE -Coordinate =1 ;VPSS_CROP_RATIO_COOR = 0, /*Ratio coordinate*/ - ;VPSS_CROP_ABS_COOR = 1 /*Absolute coordinate*/ -Crop_X =128 -Crop_Y =128 -Crop_W =1158 -Crop_H =562 - -[vpss_chn] -Vpss_W =1280 -Vpss_H =720 -CompressMode=0 ;COMPRESS_MODE_NONE = 0 - ;COMPRESS_MODE_SEG =1 ...etc -Mirror =FALSE;Whether to mirror -Flip =FALSE;Whether to flip - -[vb_conf] -VbCnt=10 -vbTimes=15 ;when raw=8bit vbTimes = 10 - ;when raw=10/12 bit vbTimes = 15 - ;when raw=14/16 bit vbTimes = 20 -[venc_comm] -venc_chn =1 ;create venc chn number;(0,2] -BufCnt = 1 ;network meida-trans bufcnt - -[venc_0] -PicWidth =1280 -PicHeight =720 -Profile =2 -RcMode =VENC_RC_MODE_H264CBR - -Gop =50 -StatTime =2 -ViFrmRate =25 -TargetFrmRate=25 -;----- only for VENC_RC_MODE_H264CBR ---------- -BitRate=4096 -FluctuateLevel=0 -;----- only for VENC_RC_MODE_H264VBR ---------- -MaxBitRate =10000 - -MaxQp=32 -MinQp=24 -;----- only for VENC_RC_MODE_H264FIXQP ---------- -IQp=45 - -PQp=40 -;-------- for REF_EX IsliceEnable------ -IsliceEnable = FALSE ;IsliceEnable and ViEnable is mutual exclusion -IsRefreshEnable = FALSE ;IsliceEnable and bRefreshEnable both TRUE is effective -RefreshLineNum = 12 ;PicHeight/16/6 6 is empirical value,ask Fuyang -ReqIQp = 30 -;-------- for REF_EX ViEnable------ -ViEnable = TRUE -ViInterval = 50 ; 2s -ViQpDelta = 2 - -[venc_1] -PicWidth =1280 -PicHeight =720 -Profile =2 -RcMode =VENC_RC_MODE_H264CBR - -Gop =50 -StatTime =2 -ViFrmRate =25 -TargetFrmRate=25 -;----- only for VENC_RC_MODE_H264CBR ---------- -BitRate=4096 -FluctuateLevel=0 -;----- only for VENC_RC_MODE_H264VBR ---------- -MaxBitRate =10000 - -MaxQp=32 - -MinQp=24 -;----- only for VENC_RC_MODE_H264FIXQP ---------- -IQp=40 - -PQp=45 -;-------- for REF_EX IsliceEnable------ -IsliceEnable = FALSE ;IsliceEnable and ViEnable is mutual exclusion -IsRefreshEnable = FALSE ;IsliceEnable and bRefreshEnable both TRUE is effective -RefreshLineNum = 12 ;PicHeight/16/6 6 is empirical value,ask Fuyang -ReqIQp = 30 -;-------- for REF_EX ViEnable------ -ViEnable = TRUE -ViInterval = 50 ; 2s -ViQpDelta = 2 - -[bind] -ViDev =0 -ViChn =0 -VpssGrp =0 -VpssChn = 0 -VoDev =0 -VoChn =0 -ViSnapChn =0 -VpssSnapGrp=0 -VpssSnapChn=1 -VencSnapGrp=1 -VencSnapChn=3 +[AWB] +AdvAWBAttr=1|8|0x30|0xFF9|0 +; HI_BOOL bAccuPrior, recommended 0 for outdoor, 1 for indoor +; HI_U8 u8Tolerance, Range:[0x0, 0xFF], AWB adjust tolerance,for outdoor, this value should be small, recommended 4 +; HI_U16 u16CurveLLimit, Range:[0x0, 0x100], Left limit of AWB Curve, recommended for indoor 0xE0, outdoor 0xE0 +; HI_U16 u16CurveRLimit, Range:[0x100, 0xFFF], Right Limit of AWB Curve,recommended for indoor 0x130, outdoor 0x120 +; HI_BOOL bGainNormEn